Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv



Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21677 1 T3 4 T7 1 T8 22
auto[1] 20993 1 T3 8 T8 18 T10 6



Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21869 1 T3 10 T7 1 T8 20
auto[1] 20801 1 T3 2 T8 20 T10 4



Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21030 1 T3 6 T8 16 T10 2
auto[1] 21640 1 T3 6 T7 1 T8 24



Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23770 1 T3 6 T7 1 T8 20
auto[1] 18900 1 T3 6 T8 20 T10 4



Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20718 1 T3 6 T8 20 T10 4
auto[1] 21952 1 T3 6 T7 1 T8 20



Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21692 1 T3 6 T8 18 T20 20
auto[1] 20978 1 T3 6 T7 1 T8 22



Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 749 1 T8 1 T13 3 T14 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 602 1 T8 1 T13 1 T14 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 687 1 T8 2 T13 5 T14 6
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 551 1 T8 2 T13 4 T14 5
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 725 1 T13 1 T14 4 T75 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 582 1 T13 1 T14 2 T75 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1195 1 T8 1 T13 3 T14 7
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1038 1 T8 1 T13 1 T14 7
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 760 1 T13 2 T14 3 T75 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 603 1 T14 1 T75 1 T41 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 727 1 T8 1 T13 5 T14 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 575 1 T8 1 T13 4 T14 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 679 1 T3 1 T8 1 T13 4
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 550 1 T3 1 T8 1 T13 3
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 748 1 T3 1 T7 1 T13 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 596 1 T3 1 T13 1 T14 8
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 710 1 T20 1 T13 1 T14 6
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 570 1 T20 1 T13 1 T14 5
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 702 1 T8 1 T13 1 T14 4
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 563 1 T8 1 T13 1 T14 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 744 1 T13 1 T14 4 T36 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 590 1 T13 1 T14 3 T36 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 719 1 T20 3 T13 1 T14 5
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 553 1 T20 3 T13 1 T14 5
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 692 1 T8 1 T10 1 T20 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 531 1 T8 1 T10 1 T20 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 783 1 T13 3 T14 5 T75 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 588 1 T13 1 T14 3 T75 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 701 1 T8 2 T20 2 T13 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 563 1 T8 2 T20 2 T13 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 722 1 T8 1 T20 1 T13 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 579 1 T8 1 T20 1 T14 5
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 760 1 T8 1 T13 6 T14 8
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 605 1 T8 1 T13 4 T14 5
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 712 1 T3 1 T8 1 T13 6
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 565 1 T3 1 T8 1 T13 5
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 710 1 T3 1 T20 1 T13 4
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 555 1 T3 1 T20 1 T13 4
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 727 1 T8 1 T13 3 T14 10
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 571 1 T8 1 T13 3 T14 6
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 721 1 T14 7 T36 4 T21 3
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 568 1 T14 5 T36 4 T21 3
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 703 1 T3 1 T10 1 T13 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 572 1 T3 1 T10 1 T13 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 785 1 T8 1 T13 1 T14 6
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 626 1 T8 1 T13 1 T14 5
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 744 1 T10 1 T20 1 T13 5
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 578 1 T10 1 T20 1 T13 3
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 718 1 T3 1 T20 2 T13 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 568 1 T3 1 T20 2 T13 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 703 1 T20 3 T13 4 T14 10
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 539 1 T20 3 T13 3 T14 6
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 752 1 T8 1 T13 2 T14 6
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 600 1 T8 1 T14 5 T75 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 741 1 T13 6 T14 2 T41 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 586 1 T13 5 T14 1 T36 3
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 723 1 T20 1 T13 4 T14 7
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 584 1 T20 1 T13 3 T14 5
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 719 1 T8 2 T13 3 T14 6
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 565 1 T8 2 T13 2 T14 6
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 781 1 T13 3 T14 4 T36 4
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 623 1 T13 3 T14 3 T36 4
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 728 1 T8 2 T10 1 T13 5
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 561 1 T8 2 T10 1 T13 3

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