Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
reset_cross 6 0 6 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12025 1 T1 4 T6 4 T8 21
auto[1] 17462 1 T1 5 T6 1 T8 16


Summary for Variable reset_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for reset_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25187 1 T1 6 T2 1 T3 6
auto[1] 6812 1 T1 3 T6 2 T8 11


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13235 1 T1 9 T2 1 T5 1
auto[1] 18764 1 T3 6 T8 20 T10 4


Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for reset_cross

Bins
reset_cpenable_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 2990 1 T1 4 T6 2 T8 4
auto[0] auto[0] auto[1] 6714 1 T8 12 T20 7 T13 11
auto[0] auto[1] auto[0] 3047 1 T1 2 T6 1 T8 2
auto[0] auto[1] auto[1] 9924 1 T8 8 T20 9 T13 9
auto[1] auto[0] auto[0] 2321 1 T6 2 T8 5 T13 5
auto[1] auto[1] auto[0] 4491 1 T1 3 T8 6 T20 6


User Defined Cross Bins for reset_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%