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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 98.23 96.58 99.62 96.00 96.37 100.00 99.02


Total test records in report: 1114
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T1013 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3533127402 Aug 19 04:31:55 PM PDT 24 Aug 19 04:31:57 PM PDT 24 48535628 ps
T1014 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3960986160 Aug 19 04:30:52 PM PDT 24 Aug 19 04:30:53 PM PDT 24 23546030 ps
T1015 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2992982304 Aug 19 04:30:41 PM PDT 24 Aug 19 04:30:42 PM PDT 24 23302053 ps
T1016 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4238083478 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 149787970 ps
T1017 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2939506811 Aug 19 04:30:59 PM PDT 24 Aug 19 04:31:00 PM PDT 24 83141089 ps
T71 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2006937236 Aug 19 04:31:03 PM PDT 24 Aug 19 04:31:05 PM PDT 24 306379194 ps
T1018 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.4084563903 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 42154744 ps
T1019 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3951215369 Aug 19 04:31:02 PM PDT 24 Aug 19 04:31:03 PM PDT 24 1474166173 ps
T1020 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3178888768 Aug 19 04:30:52 PM PDT 24 Aug 19 04:30:53 PM PDT 24 76256292 ps
T1021 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3259684046 Aug 19 04:30:59 PM PDT 24 Aug 19 04:30:59 PM PDT 24 30626946 ps
T1022 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1254203385 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:54 PM PDT 24 21143600 ps
T1023 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2938080042 Aug 19 04:30:56 PM PDT 24 Aug 19 04:30:56 PM PDT 24 74436211 ps
T1024 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3706525971 Aug 19 04:30:54 PM PDT 24 Aug 19 04:31:06 PM PDT 24 374202256 ps
T1025 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.743951457 Aug 19 04:31:08 PM PDT 24 Aug 19 04:31:08 PM PDT 24 52894722 ps
T1026 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2788937948 Aug 19 04:30:59 PM PDT 24 Aug 19 04:31:00 PM PDT 24 26413742 ps
T1027 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3019287696 Aug 19 04:31:06 PM PDT 24 Aug 19 04:31:07 PM PDT 24 18182430 ps
T1028 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.4019640501 Aug 19 04:30:43 PM PDT 24 Aug 19 04:30:45 PM PDT 24 33106924 ps
T1029 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2542655118 Aug 19 04:30:48 PM PDT 24 Aug 19 04:30:49 PM PDT 24 64507139 ps
T1030 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.4095777465 Aug 19 04:30:51 PM PDT 24 Aug 19 04:30:53 PM PDT 24 556994313 ps
T1031 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1486467365 Aug 19 04:31:55 PM PDT 24 Aug 19 04:31:56 PM PDT 24 45986327 ps
T116 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3759676513 Aug 19 04:30:49 PM PDT 24 Aug 19 04:30:50 PM PDT 24 20987701 ps
T1032 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3460723765 Aug 19 04:31:06 PM PDT 24 Aug 19 04:31:06 PM PDT 24 49938427 ps
T1033 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2276830934 Aug 19 04:31:02 PM PDT 24 Aug 19 04:31:03 PM PDT 24 19039886 ps
T1034 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3233778019 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:54 PM PDT 24 251451851 ps
T1035 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1385847896 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:56 PM PDT 24 128506976 ps
T1036 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1551808077 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:56 PM PDT 24 216497765 ps
T152 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.4035186217 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:54 PM PDT 24 221081579 ps
T1037 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1862147446 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:56 PM PDT 24 225656559 ps
T1038 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2144802051 Aug 19 04:31:01 PM PDT 24 Aug 19 04:31:01 PM PDT 24 35181896 ps
T1039 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2647716111 Aug 19 04:31:01 PM PDT 24 Aug 19 04:31:04 PM PDT 24 43178860 ps
T153 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.680668345 Aug 19 04:31:05 PM PDT 24 Aug 19 04:31:07 PM PDT 24 603556205 ps
T1040 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.4216184229 Aug 19 04:31:02 PM PDT 24 Aug 19 04:31:03 PM PDT 24 44681323 ps
T117 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.18711331 Aug 19 04:30:57 PM PDT 24 Aug 19 04:30:58 PM PDT 24 25200512 ps
T1041 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.613700755 Aug 19 04:30:42 PM PDT 24 Aug 19 04:30:43 PM PDT 24 41662797 ps
T150 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2687219991 Aug 19 04:30:55 PM PDT 24 Aug 19 04:30:56 PM PDT 24 112394037 ps
T1042 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.4281261903 Aug 19 04:32:09 PM PDT 24 Aug 19 04:32:10 PM PDT 24 50034429 ps
T1043 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3054193189 Aug 19 04:30:55 PM PDT 24 Aug 19 04:30:58 PM PDT 24 276209650 ps
T1044 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.4158678028 Aug 19 04:31:55 PM PDT 24 Aug 19 04:31:57 PM PDT 24 116496047 ps
T1045 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1497809943 Aug 19 04:31:05 PM PDT 24 Aug 19 04:31:05 PM PDT 24 18608048 ps
T151 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2883333615 Aug 19 04:31:13 PM PDT 24 Aug 19 04:31:14 PM PDT 24 113741778 ps
T1046 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.166108572 Aug 19 04:30:58 PM PDT 24 Aug 19 04:30:59 PM PDT 24 75412597 ps
T1047 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.278697509 Aug 19 04:30:57 PM PDT 24 Aug 19 04:30:57 PM PDT 24 34580666 ps
T1048 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2497578068 Aug 19 04:31:21 PM PDT 24 Aug 19 04:31:21 PM PDT 24 45619440 ps
T1049 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2275026576 Aug 19 04:30:56 PM PDT 24 Aug 19 04:30:57 PM PDT 24 18249027 ps
T1050 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.533505359 Aug 19 04:31:05 PM PDT 24 Aug 19 04:31:07 PM PDT 24 434681220 ps
T1051 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.178699007 Aug 19 04:31:13 PM PDT 24 Aug 19 04:31:14 PM PDT 24 19474367 ps
T1052 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2046251800 Aug 19 04:31:18 PM PDT 24 Aug 19 04:31:19 PM PDT 24 17921903 ps
T1053 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.4280301935 Aug 19 04:31:11 PM PDT 24 Aug 19 04:31:12 PM PDT 24 48400927 ps
T1054 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.322580688 Aug 19 04:31:11 PM PDT 24 Aug 19 04:31:12 PM PDT 24 26488363 ps
T1055 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3890551914 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:54 PM PDT 24 67051484 ps
T1056 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.781356453 Aug 19 04:31:07 PM PDT 24 Aug 19 04:31:07 PM PDT 24 17521879 ps
T1057 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.245403851 Aug 19 04:31:15 PM PDT 24 Aug 19 04:31:16 PM PDT 24 21380363 ps
T72 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2754358301 Aug 19 04:31:11 PM PDT 24 Aug 19 04:31:13 PM PDT 24 286408966 ps
T1058 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3446070266 Aug 19 04:30:55 PM PDT 24 Aug 19 04:30:56 PM PDT 24 43023567 ps
T1059 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3693712918 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:54 PM PDT 24 18244315 ps
T1060 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1430870991 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:54 PM PDT 24 30580916 ps
T1061 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1467886433 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 125686339 ps
T1062 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1339081853 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:55 PM PDT 24 71809479 ps
T68 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1887628149 Aug 19 04:31:11 PM PDT 24 Aug 19 04:31:13 PM PDT 24 388679953 ps
T1063 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.925161965 Aug 19 04:31:55 PM PDT 24 Aug 19 04:31:56 PM PDT 24 30574671 ps
T1064 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.364694749 Aug 19 04:31:01 PM PDT 24 Aug 19 04:31:02 PM PDT 24 22539766 ps
T1065 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2813638609 Aug 19 04:31:11 PM PDT 24 Aug 19 04:31:12 PM PDT 24 46874012 ps
T1066 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1095888646 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:54 PM PDT 24 176591292 ps
T1067 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3182113373 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 22392671 ps
T1068 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2195583742 Aug 19 04:31:55 PM PDT 24 Aug 19 04:31:58 PM PDT 24 428835173 ps
T1069 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.838153873 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 52308188 ps
T1070 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3785465965 Aug 19 04:31:15 PM PDT 24 Aug 19 04:31:16 PM PDT 24 190309691 ps
T1071 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1622802608 Aug 19 04:30:53 PM PDT 24 Aug 19 04:30:54 PM PDT 24 48582465 ps
T1072 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.407822861 Aug 19 04:31:01 PM PDT 24 Aug 19 04:31:03 PM PDT 24 35992390 ps
T1073 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3077312736 Aug 19 04:31:11 PM PDT 24 Aug 19 04:31:12 PM PDT 24 47309001 ps
T1074 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2261478761 Aug 19 04:30:57 PM PDT 24 Aug 19 04:30:59 PM PDT 24 410027846 ps
T1075 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3035572296 Aug 19 04:31:19 PM PDT 24 Aug 19 04:31:25 PM PDT 24 47070256 ps
T1076 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2486217021 Aug 19 04:32:25 PM PDT 24 Aug 19 04:32:27 PM PDT 24 221763082 ps
T1077 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.986300836 Aug 19 04:30:52 PM PDT 24 Aug 19 04:30:54 PM PDT 24 256309346 ps
T1078 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.4066802590 Aug 19 04:31:11 PM PDT 24 Aug 19 04:31:12 PM PDT 24 20588527 ps
T1079 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2108675993 Aug 19 04:31:24 PM PDT 24 Aug 19 04:31:25 PM PDT 24 46275619 ps
T1080 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3186521567 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 63596735 ps
T1081 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1695535824 Aug 19 04:30:47 PM PDT 24 Aug 19 04:30:48 PM PDT 24 54491205 ps
T1082 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.1803652831 Aug 19 04:31:16 PM PDT 24 Aug 19 04:31:18 PM PDT 24 97495546 ps
T1083 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1712544277 Aug 19 04:30:38 PM PDT 24 Aug 19 04:30:39 PM PDT 24 25551727 ps
T118 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3700606046 Aug 19 04:31:02 PM PDT 24 Aug 19 04:31:02 PM PDT 24 44744097 ps
T1084 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1419743679 Aug 19 04:31:02 PM PDT 24 Aug 19 04:31:02 PM PDT 24 19030683 ps
T1085 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1067895457 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 155335410 ps
T1086 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2107794520 Aug 19 04:31:55 PM PDT 24 Aug 19 04:31:57 PM PDT 24 821706142 ps
T1087 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1854248623 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 96405949 ps
T1088 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1074645878 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 21850749 ps
T1089 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1990324720 Aug 19 04:31:17 PM PDT 24 Aug 19 04:31:18 PM PDT 24 41063489 ps
T1090 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2255954228 Aug 19 04:30:48 PM PDT 24 Aug 19 04:30:49 PM PDT 24 141263608 ps
T1091 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.122174380 Aug 19 04:31:15 PM PDT 24 Aug 19 04:31:16 PM PDT 24 19944112 ps
T1092 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.559647620 Aug 19 04:31:00 PM PDT 24 Aug 19 04:31:01 PM PDT 24 17915624 ps
T1093 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.57023674 Aug 19 04:31:04 PM PDT 24 Aug 19 04:31:05 PM PDT 24 20512334 ps
T1094 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1224741783 Aug 19 04:31:14 PM PDT 24 Aug 19 04:31:15 PM PDT 24 79736796 ps
T1095 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.488658157 Aug 19 04:31:03 PM PDT 24 Aug 19 04:31:04 PM PDT 24 386425148 ps
T119 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1417998476 Aug 19 04:31:56 PM PDT 24 Aug 19 04:31:57 PM PDT 24 33073196 ps
T1096 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3401597903 Aug 19 04:30:47 PM PDT 24 Aug 19 04:30:47 PM PDT 24 67774759 ps
T1097 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3307123866 Aug 19 04:30:51 PM PDT 24 Aug 19 04:30:52 PM PDT 24 29503559 ps
T1098 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1172188091 Aug 19 04:30:51 PM PDT 24 Aug 19 04:30:52 PM PDT 24 165062188 ps
T1099 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2133992299 Aug 19 04:31:13 PM PDT 24 Aug 19 04:31:13 PM PDT 24 36713272 ps
T1100 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.491996736 Aug 19 04:30:47 PM PDT 24 Aug 19 04:30:49 PM PDT 24 108909204 ps
T1101 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3031880279 Aug 19 04:30:58 PM PDT 24 Aug 19 04:30:58 PM PDT 24 19161120 ps
T1102 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.175936955 Aug 19 04:30:59 PM PDT 24 Aug 19 04:31:01 PM PDT 24 326181391 ps
T1103 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3568850117 Aug 19 04:31:11 PM PDT 24 Aug 19 04:31:12 PM PDT 24 17480392 ps
T1104 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1854727511 Aug 19 04:32:28 PM PDT 24 Aug 19 04:32:29 PM PDT 24 27031324 ps
T1105 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3685224730 Aug 19 04:31:08 PM PDT 24 Aug 19 04:31:08 PM PDT 24 28406672 ps
T1106 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.251852694 Aug 19 04:31:03 PM PDT 24 Aug 19 04:31:03 PM PDT 24 29128272 ps
T120 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3951039129 Aug 19 04:31:00 PM PDT 24 Aug 19 04:31:02 PM PDT 24 214374062 ps
T1107 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1531830451 Aug 19 04:30:54 PM PDT 24 Aug 19 04:30:55 PM PDT 24 29975371 ps
T1108 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.864877074 Aug 19 04:30:48 PM PDT 24 Aug 19 04:30:48 PM PDT 24 31341445 ps
T1109 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3807692755 Aug 19 04:31:16 PM PDT 24 Aug 19 04:31:16 PM PDT 24 16066105 ps
T1110 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1470171544 Aug 19 04:31:12 PM PDT 24 Aug 19 04:31:13 PM PDT 24 33312213 ps
T1111 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3452741074 Aug 19 04:31:09 PM PDT 24 Aug 19 04:31:09 PM PDT 24 32594099 ps
T1112 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2746946384 Aug 19 04:30:54 PM PDT 24 Aug 19 04:31:00 PM PDT 24 39341336 ps
T1113 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3893247052 Aug 19 04:31:04 PM PDT 24 Aug 19 04:31:05 PM PDT 24 58114956 ps
T1114 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3952042304 Aug 19 04:31:18 PM PDT 24 Aug 19 04:31:19 PM PDT 24 45850817 ps

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.1984985463
Short name T8
Test name
Test status
Simulation time 516710335 ps
CPU time 1.32 seconds
Started Aug 19 05:50:32 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 200944 kb
Host smart-0e4e69cf-5223-482c-a1b4-d94282040cdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984985463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.1984985463
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.216399905
Short name T12
Test name
Test status
Simulation time 102068498 ps
CPU time 1.17 seconds
Started Aug 19 05:50:30 PM PDT 24
Finished Aug 19 05:50:31 PM PDT 24
Peak memory 209292 kb
Host smart-7373ff97-e419-4ca9-b5ba-260f5f0cdf1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216399905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.216399905
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all.2734433886
Short name T21
Test name
Test status
Simulation time 2682534598 ps
CPU time 4.38 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 201312 kb
Host smart-d2ce6b17-1bac-4024-adc8-fd7edf868890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734433886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.2734433886
Directory /workspace/8.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.2930217917
Short name T26
Test name
Test status
Simulation time 2294342652 ps
CPU time 1.43 seconds
Started Aug 19 05:50:21 PM PDT 24
Finished Aug 19 05:50:22 PM PDT 24
Peak memory 217668 kb
Host smart-46583fa7-2723-473a-a35e-46ea0e61bc30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930217917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2930217917
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.547990252
Short name T24
Test name
Test status
Simulation time 2744135812 ps
CPU time 10.45 seconds
Started Aug 19 05:51:28 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 201352 kb
Host smart-68e3dd3e-a1dd-46b8-8a6c-12ed24cb4dd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547990252 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.547990252
Directory /workspace/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.267159588
Short name T53
Test name
Test status
Simulation time 231318826 ps
CPU time 1.51 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:32:02 PM PDT 24
Peak memory 200040 kb
Host smart-26a28a39-d1a4-4508-9617-6336aacf91b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267159588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err
.267159588
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.133540421
Short name T232
Test name
Test status
Simulation time 48460175 ps
CPU time 0.65 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:50:50 PM PDT 24
Peak memory 201376 kb
Host smart-0885b91c-b378-4cbb-8912-e445d94c7ba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133540421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.133540421
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3231768568
Short name T89
Test name
Test status
Simulation time 945186255 ps
CPU time 1.93 seconds
Started Aug 19 05:51:53 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 201072 kb
Host smart-f85dd591-f141-4fc9-b57e-31ac4f3aab32
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231768568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3231768568
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.1442675935
Short name T80
Test name
Test status
Simulation time 1810668330 ps
CPU time 6.52 seconds
Started Aug 19 05:50:19 PM PDT 24
Finished Aug 19 05:50:26 PM PDT 24
Peak memory 201368 kb
Host smart-d66daef4-46ea-4d52-9fea-f8aaf88455dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442675935 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.1442675935
Directory /workspace/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2568517642
Short name T157
Test name
Test status
Simulation time 40819992 ps
CPU time 0.64 seconds
Started Aug 19 04:30:47 PM PDT 24
Finished Aug 19 04:30:48 PM PDT 24
Peak memory 195276 kb
Host smart-1a7304bd-2bf8-45d4-a718-d24fc88bac1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568517642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.2568517642
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2753679719
Short name T62
Test name
Test status
Simulation time 22657481 ps
CPU time 0.62 seconds
Started Aug 19 04:32:30 PM PDT 24
Finished Aug 19 04:32:31 PM PDT 24
Peak memory 195012 kb
Host smart-8227b216-2f33-4085-9b63-a63e70202de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753679719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2753679719
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.2632290199
Short name T138
Test name
Test status
Simulation time 516385058 ps
CPU time 0.79 seconds
Started Aug 19 05:50:23 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 198132 kb
Host smart-5dc2c09b-4a00-4856-8d5c-30bed444be0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632290199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2632290199
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.561413094
Short name T50
Test name
Test status
Simulation time 244195307 ps
CPU time 1.42 seconds
Started Aug 19 04:30:42 PM PDT 24
Finished Aug 19 04:30:43 PM PDT 24
Peak memory 196528 kb
Host smart-734d48f6-4fd8-4731-943a-451141ed9381
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561413094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.561413094
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.2937271429
Short name T58
Test name
Test status
Simulation time 352148711 ps
CPU time 1.01 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 200184 kb
Host smart-16264cdd-5551-4d3f-8623-5e92f9628fa8
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937271429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_
cm_ctrl_config_regwen.2937271429
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.3890865159
Short name T38
Test name
Test status
Simulation time 48009156 ps
CPU time 0.79 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 198868 kb
Host smart-e2007dfa-2ba2-4164-85f3-b11ec0bcba0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890865159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.3890865159
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.2992982304
Short name T1015
Test name
Test status
Simulation time 23302053 ps
CPU time 0.64 seconds
Started Aug 19 04:30:41 PM PDT 24
Finished Aug 19 04:30:42 PM PDT 24
Peak memory 195056 kb
Host smart-743f6512-a7e1-4545-b427-b57bbba7b4fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992982304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.2992982304
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.533505359
Short name T1050
Test name
Test status
Simulation time 434681220 ps
CPU time 1.51 seconds
Started Aug 19 04:31:05 PM PDT 24
Finished Aug 19 04:31:07 PM PDT 24
Peak memory 200728 kb
Host smart-2fe71306-247d-438e-b559-16699a64ad75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533505359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err
.533505359
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.3990435567
Short name T167
Test name
Test status
Simulation time 67259414 ps
CPU time 0.72 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 199152 kb
Host smart-22cde46d-5c31-4a41-88b3-a4720b9d51d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990435567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.3990435567
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1887628149
Short name T68
Test name
Test status
Simulation time 388679953 ps
CPU time 1.66 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:13 PM PDT 24
Peak memory 200764 kb
Host smart-404ecbb6-667c-4f38-9f06-9b91c3fd0358
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887628149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1887628149
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.2551301904
Short name T164
Test name
Test status
Simulation time 61124939 ps
CPU time 0.74 seconds
Started Aug 19 05:51:02 PM PDT 24
Finished Aug 19 05:51:03 PM PDT 24
Peak memory 199148 kb
Host smart-4355b932-5830-4158-9122-bd0149171bdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551301904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.2551301904
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.500591049
Short name T588
Test name
Test status
Simulation time 79073311 ps
CPU time 0.68 seconds
Started Aug 19 05:51:29 PM PDT 24
Finished Aug 19 05:51:30 PM PDT 24
Peak memory 198516 kb
Host smart-99204e4f-69cb-451e-b523-2a05fe8cfe93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500591049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disa
ble_rom_integrity_check.500591049
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3233778019
Short name T1034
Test name
Test status
Simulation time 251451851 ps
CPU time 1.47 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 201132 kb
Host smart-70964b04-bdcf-4143-a4a7-d4947e3285b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233778019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3233778019
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.3897437109
Short name T190
Test name
Test status
Simulation time 29952215 ps
CPU time 0.63 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 198092 kb
Host smart-5e44a865-8081-4cce-9a53-929ef60dfa5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897437109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.3897437109
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4238083478
Short name T1016
Test name
Test status
Simulation time 149787970 ps
CPU time 0.84 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 195140 kb
Host smart-81f0d700-b6f2-49ca-a4df-7c43e33bd68f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238083478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.4
238083478
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.166044715
Short name T1002
Test name
Test status
Simulation time 165807505 ps
CPU time 2.16 seconds
Started Aug 19 04:30:49 PM PDT 24
Finished Aug 19 04:30:51 PM PDT 24
Peak memory 195440 kb
Host smart-c8bb98dc-e91b-4568-af49-f69f84ffc01f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166044715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.166044715
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3401597903
Short name T1096
Test name
Test status
Simulation time 67774759 ps
CPU time 0.65 seconds
Started Aug 19 04:30:47 PM PDT 24
Finished Aug 19 04:30:47 PM PDT 24
Peak memory 196460 kb
Host smart-c1b41c7e-ded3-4add-88b8-16a3a86d144f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401597903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3
401597903
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2316879057
Short name T162
Test name
Test status
Simulation time 68382174 ps
CPU time 0.73 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 195372 kb
Host smart-e8b02227-0027-4fab-bae8-cf4da7c1c7d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316879057 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2316879057
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.122174380
Short name T1091
Test name
Test status
Simulation time 19944112 ps
CPU time 0.63 seconds
Started Aug 19 04:31:15 PM PDT 24
Finished Aug 19 04:31:16 PM PDT 24
Peak memory 197488 kb
Host smart-8209d849-9d8f-4d87-931c-30edb42dbe98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122174380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.122174380
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.613700755
Short name T1041
Test name
Test status
Simulation time 41662797 ps
CPU time 0.7 seconds
Started Aug 19 04:30:42 PM PDT 24
Finished Aug 19 04:30:43 PM PDT 24
Peak memory 197392 kb
Host smart-652f3a7a-080f-48a2-8837-2a2600c36db1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613700755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sam
e_csr_outstanding.613700755
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3951215369
Short name T1019
Test name
Test status
Simulation time 1474166173 ps
CPU time 1.5 seconds
Started Aug 19 04:31:02 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 195552 kb
Host smart-5b88b2d2-5184-4e80-bcbd-e44e18a56f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951215369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.3951215369
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.4084563903
Short name T1018
Test name
Test status
Simulation time 42154744 ps
CPU time 1.01 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 195056 kb
Host smart-3b0c5e6a-d839-472c-9dd8-efd6e88a3c8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084563903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.4
084563903
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3951039129
Short name T120
Test name
Test status
Simulation time 214374062 ps
CPU time 1.97 seconds
Started Aug 19 04:31:00 PM PDT 24
Finished Aug 19 04:31:02 PM PDT 24
Peak memory 195448 kb
Host smart-8ffd17b1-003b-4dc5-a6eb-3b17be1d21e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951039129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.3
951039129
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2504578711
Short name T60
Test name
Test status
Simulation time 27013760 ps
CPU time 0.7 seconds
Started Aug 19 04:31:07 PM PDT 24
Finished Aug 19 04:31:08 PM PDT 24
Peak memory 198448 kb
Host smart-e152cb4f-6484-4c2e-ac06-92590f0056fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504578711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2
504578711
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1603133699
Short name T1011
Test name
Test status
Simulation time 62920701 ps
CPU time 0.78 seconds
Started Aug 19 04:30:55 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 195368 kb
Host smart-3b32ad79-46a3-433c-91f8-ee2feb0ff6c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603133699 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.1603133699
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.3140416122
Short name T115
Test name
Test status
Simulation time 18481951 ps
CPU time 0.63 seconds
Started Aug 19 04:31:00 PM PDT 24
Finished Aug 19 04:31:00 PM PDT 24
Peak memory 195324 kb
Host smart-032e7e0a-e44a-4162-b897-3ed6bc228733
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140416122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.3140416122
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2172420557
Short name T61
Test name
Test status
Simulation time 19551012 ps
CPU time 0.67 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 195188 kb
Host smart-6bc9c238-e812-4129-83d6-1236e8393caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172420557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.2172420557
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2195583742
Short name T1068
Test name
Test status
Simulation time 428835173 ps
CPU time 2.31 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:31:58 PM PDT 24
Peak memory 193824 kb
Host smart-11d4896e-f273-4d39-92d5-910d74a4abcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195583742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2195583742
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1551808077
Short name T1036
Test name
Test status
Simulation time 216497765 ps
CPU time 1.83 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 200596 kb
Host smart-a4ebb65e-2ded-429a-97d4-7365189074ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551808077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1551808077
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2647716111
Short name T1039
Test name
Test status
Simulation time 43178860 ps
CPU time 0.9 seconds
Started Aug 19 04:31:01 PM PDT 24
Finished Aug 19 04:31:04 PM PDT 24
Peak memory 195280 kb
Host smart-3811bd38-2bca-4a58-bdfc-e503de3f0653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647716111 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.2647716111
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1417998476
Short name T119
Test name
Test status
Simulation time 33073196 ps
CPU time 0.64 seconds
Started Aug 19 04:31:56 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 197016 kb
Host smart-d4372854-5473-4827-ad56-dd5d1cf5d6c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417998476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1417998476
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.2667444076
Short name T155
Test name
Test status
Simulation time 19510931 ps
CPU time 0.61 seconds
Started Aug 19 04:31:00 PM PDT 24
Finished Aug 19 04:31:00 PM PDT 24
Peak memory 195124 kb
Host smart-983bcc97-22ca-43df-9497-7f27f2881793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667444076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.2667444076
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3702934729
Short name T121
Test name
Test status
Simulation time 44779803 ps
CPU time 0.67 seconds
Started Aug 19 04:30:57 PM PDT 24
Finished Aug 19 04:30:57 PM PDT 24
Peak memory 195192 kb
Host smart-4cbc8f21-b0f3-49f4-ad10-23dfd568e145
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702934729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.3702934729
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2846269745
Short name T1006
Test name
Test status
Simulation time 245617669 ps
CPU time 1.02 seconds
Started Aug 19 04:30:56 PM PDT 24
Finished Aug 19 04:30:57 PM PDT 24
Peak memory 196280 kb
Host smart-959cfc72-ea6d-455f-bbb9-ecbc8919e4d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846269745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.2846269745
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.229046820
Short name T1004
Test name
Test status
Simulation time 89963663 ps
CPU time 1.16 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 197632 kb
Host smart-e5fdeb23-d59c-42a3-84ca-e89866734b76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229046820 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.229046820
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.3307123866
Short name T1097
Test name
Test status
Simulation time 29503559 ps
CPU time 0.62 seconds
Started Aug 19 04:30:51 PM PDT 24
Finished Aug 19 04:30:52 PM PDT 24
Peak memory 195216 kb
Host smart-4e24fa83-ed8a-42b9-9684-c4a6ededcf71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307123866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3307123866
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1254203385
Short name T1022
Test name
Test status
Simulation time 21143600 ps
CPU time 0.64 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 195232 kb
Host smart-53d957cb-3c28-453e-ab3e-0c39b5975087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254203385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1254203385
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3533127402
Short name T1013
Test name
Test status
Simulation time 48535628 ps
CPU time 0.99 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 192540 kb
Host smart-e42c99cf-3dd8-4772-b182-cb173761304c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533127402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3533127402
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.3554042411
Short name T49
Test name
Test status
Simulation time 119305462 ps
CPU time 2.12 seconds
Started Aug 19 04:31:03 PM PDT 24
Finished Aug 19 04:31:05 PM PDT 24
Peak memory 196508 kb
Host smart-f7a35583-a897-45be-82aa-a28fa9d6b0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554042411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.3554042411
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.646329421
Short name T52
Test name
Test status
Simulation time 114497015 ps
CPU time 1.52 seconds
Started Aug 19 04:31:10 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 196756 kb
Host smart-0218106d-e52d-4bd1-ba21-583e4b30868f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646329421 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.646329421
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2997631803
Short name T112
Test name
Test status
Simulation time 102306433 ps
CPU time 0.66 seconds
Started Aug 19 04:31:12 PM PDT 24
Finished Aug 19 04:31:13 PM PDT 24
Peak memory 195316 kb
Host smart-ce511d98-d5e7-4e0d-96c2-2c789f553671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997631803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2997631803
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.1864793219
Short name T156
Test name
Test status
Simulation time 36549439 ps
CPU time 0.59 seconds
Started Aug 19 04:31:06 PM PDT 24
Finished Aug 19 04:31:07 PM PDT 24
Peak memory 195132 kb
Host smart-6aa4fa9e-d5a5-4dc8-a632-e12b6adda9f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864793219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.1864793219
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1531830451
Short name T1107
Test name
Test status
Simulation time 29975371 ps
CPU time 0.73 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 197408 kb
Host smart-50a5aa80-afd7-4af5-9174-f0f6b219e18d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531830451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.1531830451
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1854248623
Short name T1087
Test name
Test status
Simulation time 96405949 ps
CPU time 0.85 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 195420 kb
Host smart-8bfc7814-b68a-4cfb-baa3-914b48af06f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854248623 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.1854248623
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3019287696
Short name T1027
Test name
Test status
Simulation time 18182430 ps
CPU time 0.65 seconds
Started Aug 19 04:31:06 PM PDT 24
Finished Aug 19 04:31:07 PM PDT 24
Peak memory 195180 kb
Host smart-6abce6cd-318c-426c-9f90-f4844469b036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019287696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3019287696
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.1913187506
Short name T1003
Test name
Test status
Simulation time 62306404 ps
CPU time 0.58 seconds
Started Aug 19 04:31:03 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 195192 kb
Host smart-07740a2f-e6b3-4d92-83ee-aca6a914d64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913187506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.1913187506
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2276830934
Short name T1033
Test name
Test status
Simulation time 19039886 ps
CPU time 0.71 seconds
Started Aug 19 04:31:02 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 195364 kb
Host smart-3f076459-aceb-4f92-8d1b-15ec8a1d7921
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276830934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.2276830934
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.1803652831
Short name T1082
Test name
Test status
Simulation time 97495546 ps
CPU time 1.98 seconds
Started Aug 19 04:31:16 PM PDT 24
Finished Aug 19 04:31:18 PM PDT 24
Peak memory 196540 kb
Host smart-26fa0e72-5630-42fa-bf5a-7292b898b3e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803652831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.1803652831
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.2754358301
Short name T72
Test name
Test status
Simulation time 286408966 ps
CPU time 1.55 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:13 PM PDT 24
Peak memory 200504 kb
Host smart-dfabfc50-d720-4633-8c00-299685b7a5c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754358301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.2754358301
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1855408657
Short name T161
Test name
Test status
Simulation time 87085731 ps
CPU time 0.79 seconds
Started Aug 19 04:31:25 PM PDT 24
Finished Aug 19 04:31:26 PM PDT 24
Peak memory 195444 kb
Host smart-e3aa778c-e3f0-469d-b50f-9b6b159e4c5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855408657 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.1855408657
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.57023674
Short name T1093
Test name
Test status
Simulation time 20512334 ps
CPU time 0.65 seconds
Started Aug 19 04:31:04 PM PDT 24
Finished Aug 19 04:31:05 PM PDT 24
Peak memory 197380 kb
Host smart-e86827d3-5f75-4683-89d9-c04807be4718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57023674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.57023674
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.2275026576
Short name T1049
Test name
Test status
Simulation time 18249027 ps
CPU time 0.59 seconds
Started Aug 19 04:30:56 PM PDT 24
Finished Aug 19 04:30:57 PM PDT 24
Peak memory 195084 kb
Host smart-562a2fb0-8f10-4858-80aa-5e01c0ba3cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275026576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.2275026576
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2788937948
Short name T1026
Test name
Test status
Simulation time 26413742 ps
CPU time 0.67 seconds
Started Aug 19 04:30:59 PM PDT 24
Finished Aug 19 04:31:00 PM PDT 24
Peak memory 195200 kb
Host smart-f75661ad-61cd-49d1-b8b9-f55cbcc132f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788937948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.2788937948
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.4095777465
Short name T1030
Test name
Test status
Simulation time 556994313 ps
CPU time 2.3 seconds
Started Aug 19 04:30:51 PM PDT 24
Finished Aug 19 04:30:53 PM PDT 24
Peak memory 197964 kb
Host smart-85143ebf-a40f-4dac-b82e-8b331ed31b42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095777465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.4095777465
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.488658157
Short name T1095
Test name
Test status
Simulation time 386425148 ps
CPU time 1.42 seconds
Started Aug 19 04:31:03 PM PDT 24
Finished Aug 19 04:31:04 PM PDT 24
Peak memory 200444 kb
Host smart-0f8a9fea-22f3-4042-9da6-bc4a02805ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488658157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err
.488658157
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.166108572
Short name T1046
Test name
Test status
Simulation time 75412597 ps
CPU time 0.8 seconds
Started Aug 19 04:30:58 PM PDT 24
Finished Aug 19 04:30:59 PM PDT 24
Peak memory 195436 kb
Host smart-7b6ecf84-4c15-4536-9d2c-7f00bdd202e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166108572 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.166108572
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.18711331
Short name T117
Test name
Test status
Simulation time 25200512 ps
CPU time 0.67 seconds
Started Aug 19 04:30:57 PM PDT 24
Finished Aug 19 04:30:58 PM PDT 24
Peak memory 197384 kb
Host smart-27852a8a-904f-4750-9b12-164ab1bc7880
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18711331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.18711331
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2813638609
Short name T1065
Test name
Test status
Simulation time 46874012 ps
CPU time 0.64 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 195240 kb
Host smart-d6699859-dd47-4bb1-afe9-df418ed5a9e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813638609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2813638609
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.2108675993
Short name T1079
Test name
Test status
Simulation time 46275619 ps
CPU time 0.7 seconds
Started Aug 19 04:31:24 PM PDT 24
Finished Aug 19 04:31:25 PM PDT 24
Peak memory 198524 kb
Host smart-691d539d-197b-465e-abaa-66baecf496dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108675993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.2108675993
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1537189893
Short name T69
Test name
Test status
Simulation time 94591651 ps
CPU time 1.89 seconds
Started Aug 19 04:31:14 PM PDT 24
Finished Aug 19 04:31:16 PM PDT 24
Peak memory 196804 kb
Host smart-70b001bc-f004-4453-83fa-282396cb5478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537189893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1537189893
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2883333615
Short name T151
Test name
Test status
Simulation time 113741778 ps
CPU time 1.2 seconds
Started Aug 19 04:31:13 PM PDT 24
Finished Aug 19 04:31:14 PM PDT 24
Peak memory 195460 kb
Host smart-7cf659d5-318e-4f76-bc91-f3a137cae57d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883333615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.2883333615
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3890551914
Short name T1055
Test name
Test status
Simulation time 67051484 ps
CPU time 0.92 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 195352 kb
Host smart-75186fa1-ffee-4ec0-8774-64b0dd2800ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890551914 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.3890551914
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.743951457
Short name T1025
Test name
Test status
Simulation time 52894722 ps
CPU time 0.67 seconds
Started Aug 19 04:31:08 PM PDT 24
Finished Aug 19 04:31:08 PM PDT 24
Peak memory 195224 kb
Host smart-8f72fd9b-7dce-4971-afc8-5cb892cb87bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743951457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.743951457
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.146561110
Short name T160
Test name
Test status
Simulation time 33373563 ps
CPU time 0.64 seconds
Started Aug 19 04:31:04 PM PDT 24
Finished Aug 19 04:31:05 PM PDT 24
Peak memory 195224 kb
Host smart-1c7b7a6f-c83c-43ac-9baa-faebd1e60bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146561110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.146561110
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.2124132258
Short name T124
Test name
Test status
Simulation time 42817921 ps
CPU time 0.73 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 198540 kb
Host smart-c21cd412-b910-4792-b670-c4fb0dd533b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124132258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.2124132258
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.1095888646
Short name T1066
Test name
Test status
Simulation time 176591292 ps
CPU time 1.33 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 196588 kb
Host smart-e32ad8bb-b9e0-467f-88a6-9ce238ac5009
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095888646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1095888646
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.986300836
Short name T1077
Test name
Test status
Simulation time 256309346 ps
CPU time 1.54 seconds
Started Aug 19 04:30:52 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 200824 kb
Host smart-98079039-0a7f-4137-a3fc-71bf14cbd802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986300836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err
.986300836
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3178888768
Short name T1020
Test name
Test status
Simulation time 76256292 ps
CPU time 1.06 seconds
Started Aug 19 04:30:52 PM PDT 24
Finished Aug 19 04:30:53 PM PDT 24
Peak memory 197860 kb
Host smart-0cdcd9d1-50d2-43b2-ada5-f33a965140cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178888768 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.3178888768
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.322580688
Short name T1054
Test name
Test status
Simulation time 26488363 ps
CPU time 0.6 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 195224 kb
Host smart-38d4f358-17d1-4563-ba1a-3625950dc5ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322580688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.322580688
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1470171544
Short name T1110
Test name
Test status
Simulation time 33312213 ps
CPU time 0.62 seconds
Started Aug 19 04:31:12 PM PDT 24
Finished Aug 19 04:31:13 PM PDT 24
Peak memory 195132 kb
Host smart-706ed364-0be0-4cff-bbe8-eb173222bc2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470171544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1470171544
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2148261139
Short name T126
Test name
Test status
Simulation time 66860862 ps
CPU time 0.88 seconds
Started Aug 19 04:30:55 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 200024 kb
Host smart-8543cb82-6a65-4a9c-bed3-37f8e066cfd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148261139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.2148261139
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1224741783
Short name T1094
Test name
Test status
Simulation time 79736796 ps
CPU time 1.15 seconds
Started Aug 19 04:31:14 PM PDT 24
Finished Aug 19 04:31:15 PM PDT 24
Peak memory 196276 kb
Host smart-634f89ee-6d29-478d-b7e4-0ef245d51a72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224741783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.1224741783
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3878341164
Short name T55
Test name
Test status
Simulation time 235165917 ps
CPU time 1.65 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:13 PM PDT 24
Peak memory 200552 kb
Host smart-5ada240e-13e0-4554-a6f9-ccf530a87fee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878341164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3878341164
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3446070266
Short name T1058
Test name
Test status
Simulation time 43023567 ps
CPU time 0.83 seconds
Started Aug 19 04:30:55 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 195424 kb
Host smart-a6de15cb-1f48-4ba4-930f-56f066b98072
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446070266 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.3446070266
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.407822861
Short name T1072
Test name
Test status
Simulation time 35992390 ps
CPU time 0.68 seconds
Started Aug 19 04:31:01 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 197372 kb
Host smart-2cfb20b0-d15a-47fb-894a-6ad061f46f08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407822861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.407822861
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3035572296
Short name T1075
Test name
Test status
Simulation time 47070256 ps
CPU time 0.63 seconds
Started Aug 19 04:31:19 PM PDT 24
Finished Aug 19 04:31:25 PM PDT 24
Peak memory 195240 kb
Host smart-448fe83c-bae5-49f1-8949-6e2a916d2790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035572296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.3035572296
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.4254818461
Short name T123
Test name
Test status
Simulation time 51455566 ps
CPU time 0.88 seconds
Started Aug 19 04:30:52 PM PDT 24
Finished Aug 19 04:30:53 PM PDT 24
Peak memory 195276 kb
Host smart-9b93f91c-76cd-4148-8ce3-4f3c882b7c66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254818461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.4254818461
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.885803289
Short name T996
Test name
Test status
Simulation time 332234979 ps
CPU time 2.54 seconds
Started Aug 19 04:31:02 PM PDT 24
Finished Aug 19 04:31:04 PM PDT 24
Peak memory 197544 kb
Host smart-0195ef23-9b30-46ad-bfea-3aa9cc9061a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885803289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.885803289
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3239007636
Short name T67
Test name
Test status
Simulation time 94043354 ps
CPU time 1.14 seconds
Started Aug 19 04:31:07 PM PDT 24
Finished Aug 19 04:31:08 PM PDT 24
Peak memory 200596 kb
Host smart-df42efd0-7ced-43c9-aab4-0dcd357f9953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239007636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.3239007636
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3186521567
Short name T1080
Test name
Test status
Simulation time 63596735 ps
CPU time 1.18 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 196852 kb
Host smart-aa9c8e45-da2a-465a-87b3-ff4251d1c9d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186521567 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.3186521567
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1006221474
Short name T114
Test name
Test status
Simulation time 64289993 ps
CPU time 0.63 seconds
Started Aug 19 04:31:12 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 195308 kb
Host smart-1a0e704a-4c63-4920-8f73-d01831d50770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006221474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.1006221474
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3685224730
Short name T1105
Test name
Test status
Simulation time 28406672 ps
CPU time 0.65 seconds
Started Aug 19 04:31:08 PM PDT 24
Finished Aug 19 04:31:08 PM PDT 24
Peak memory 195092 kb
Host smart-3a4b9b7b-32f1-4559-ba4d-a55add65955e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685224730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3685224730
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1430870991
Short name T1060
Test name
Test status
Simulation time 30580916 ps
CPU time 0.74 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 195364 kb
Host smart-3d1025da-46da-4729-8e47-b6d3c1b034bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430870991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.1430870991
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.3706525971
Short name T1024
Test name
Test status
Simulation time 374202256 ps
CPU time 2.17 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:31:06 PM PDT 24
Peak memory 197512 kb
Host smart-8fc5d537-1bfa-4495-9437-e24bc7aa7d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706525971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.3706525971
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3785465965
Short name T1070
Test name
Test status
Simulation time 190309691 ps
CPU time 1.68 seconds
Started Aug 19 04:31:15 PM PDT 24
Finished Aug 19 04:31:16 PM PDT 24
Peak memory 200760 kb
Host smart-3d663695-17ae-4c55-a001-ebbe42d6ecd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785465965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.3785465965
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.740947314
Short name T1009
Test name
Test status
Simulation time 76908391 ps
CPU time 1.01 seconds
Started Aug 19 04:30:50 PM PDT 24
Finished Aug 19 04:30:51 PM PDT 24
Peak memory 200172 kb
Host smart-b77567fa-e476-4bd5-9f28-17d0a1168adc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740947314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.740947314
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2107794520
Short name T1086
Test name
Test status
Simulation time 821706142 ps
CPU time 1.85 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 193652 kb
Host smart-dbbd7ff2-2762-4a57-b79b-b91e71ed72b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107794520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.2
107794520
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2939506811
Short name T1017
Test name
Test status
Simulation time 83141089 ps
CPU time 0.65 seconds
Started Aug 19 04:30:59 PM PDT 24
Finished Aug 19 04:31:00 PM PDT 24
Peak memory 195308 kb
Host smart-952becb7-e386-4fe2-a146-b4177a311f70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939506811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.2
939506811
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1573410506
Short name T1007
Test name
Test status
Simulation time 106196683 ps
CPU time 0.84 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:31:56 PM PDT 24
Peak memory 192676 kb
Host smart-db56790b-7b10-463f-ba96-d02962ab8847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573410506 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.1573410506
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.864877074
Short name T1108
Test name
Test status
Simulation time 31341445 ps
CPU time 0.59 seconds
Started Aug 19 04:30:48 PM PDT 24
Finished Aug 19 04:30:48 PM PDT 24
Peak memory 197468 kb
Host smart-ca370edf-aa81-4b78-ba4c-4f6289b610b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864877074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.864877074
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1854727511
Short name T1104
Test name
Test status
Simulation time 27031324 ps
CPU time 0.59 seconds
Started Aug 19 04:32:28 PM PDT 24
Finished Aug 19 04:32:29 PM PDT 24
Peak memory 195024 kb
Host smart-7fe7fa8a-374c-4d57-9c93-f1d5b684534a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854727511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1854727511
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1230060429
Short name T122
Test name
Test status
Simulation time 100019052 ps
CPU time 0.81 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:53 PM PDT 24
Peak memory 195272 kb
Host smart-a24f4b68-3d1a-4dcc-a0af-47a6bf56689b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230060429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.1230060429
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2006937236
Short name T71
Test name
Test status
Simulation time 306379194 ps
CPU time 2.18 seconds
Started Aug 19 04:31:03 PM PDT 24
Finished Aug 19 04:31:05 PM PDT 24
Peak memory 200836 kb
Host smart-742eaf72-f9c5-4085-b535-a0f31e27546c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006937236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.2006937236
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.175936955
Short name T1102
Test name
Test status
Simulation time 326181391 ps
CPU time 1.02 seconds
Started Aug 19 04:30:59 PM PDT 24
Finished Aug 19 04:31:01 PM PDT 24
Peak memory 200624 kb
Host smart-229a57f8-5d82-4c7d-9889-40707603d73d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175936955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.
175936955
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2497578068
Short name T1048
Test name
Test status
Simulation time 45619440 ps
CPU time 0.64 seconds
Started Aug 19 04:31:21 PM PDT 24
Finished Aug 19 04:31:21 PM PDT 24
Peak memory 195088 kb
Host smart-11cb650d-7353-4e9a-9afd-553ad5c1d5c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497578068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2497578068
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2046251800
Short name T1052
Test name
Test status
Simulation time 17921903 ps
CPU time 0.63 seconds
Started Aug 19 04:31:18 PM PDT 24
Finished Aug 19 04:31:19 PM PDT 24
Peak memory 195068 kb
Host smart-e6a2844c-9678-461c-948d-67e2f25712f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046251800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2046251800
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1330230233
Short name T64
Test name
Test status
Simulation time 23406679 ps
CPU time 0.67 seconds
Started Aug 19 04:31:21 PM PDT 24
Finished Aug 19 04:31:21 PM PDT 24
Peak memory 195232 kb
Host smart-eed7df5e-5605-4620-bf3c-0ec88832277c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330230233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.1330230233
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3960986160
Short name T1014
Test name
Test status
Simulation time 23546030 ps
CPU time 0.65 seconds
Started Aug 19 04:30:52 PM PDT 24
Finished Aug 19 04:30:53 PM PDT 24
Peak memory 195132 kb
Host smart-6b51102e-22c5-41f2-92c2-2c45dffb77c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960986160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.3960986160
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.4066802590
Short name T1078
Test name
Test status
Simulation time 20588527 ps
CPU time 0.62 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 195132 kb
Host smart-453217e4-0e96-4021-9a49-c13029a548b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066802590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.4066802590
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.781356453
Short name T1056
Test name
Test status
Simulation time 17521879 ps
CPU time 0.64 seconds
Started Aug 19 04:31:07 PM PDT 24
Finished Aug 19 04:31:07 PM PDT 24
Peak memory 195176 kb
Host smart-0cb01692-2ed8-43ad-9df9-58fa06f2c244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781356453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.781356453
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3302472514
Short name T1000
Test name
Test status
Simulation time 30718757 ps
CPU time 0.62 seconds
Started Aug 19 04:31:35 PM PDT 24
Finished Aug 19 04:31:35 PM PDT 24
Peak memory 195132 kb
Host smart-c5cef043-cd08-4247-b27e-345bf1197a90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302472514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3302472514
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.251852694
Short name T1106
Test name
Test status
Simulation time 29128272 ps
CPU time 0.59 seconds
Started Aug 19 04:31:03 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 195236 kb
Host smart-34881869-9eca-4b33-9066-010c8b947438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251852694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.251852694
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3893247052
Short name T1113
Test name
Test status
Simulation time 58114956 ps
CPU time 0.62 seconds
Started Aug 19 04:31:04 PM PDT 24
Finished Aug 19 04:31:05 PM PDT 24
Peak memory 195240 kb
Host smart-c4abce95-5d79-4e12-a537-d0bbf768cebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893247052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3893247052
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.3460723765
Short name T1032
Test name
Test status
Simulation time 49938427 ps
CPU time 0.58 seconds
Started Aug 19 04:31:06 PM PDT 24
Finished Aug 19 04:31:06 PM PDT 24
Peak memory 195132 kb
Host smart-60e5e56f-236a-4d4f-9fa3-ec36fc91aa3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460723765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.3460723765
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1941555285
Short name T1005
Test name
Test status
Simulation time 101887018 ps
CPU time 0.77 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 195228 kb
Host smart-58796602-ae8d-4612-add9-0e75536c7ad9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941555285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.1
941555285
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3054193189
Short name T1043
Test name
Test status
Simulation time 276209650 ps
CPU time 2.85 seconds
Started Aug 19 04:30:55 PM PDT 24
Finished Aug 19 04:30:58 PM PDT 24
Peak memory 199200 kb
Host smart-03bdcada-57f8-44a5-92aa-fbb7cf5cbe12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054193189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.3
054193189
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1712544277
Short name T1083
Test name
Test status
Simulation time 25551727 ps
CPU time 0.63 seconds
Started Aug 19 04:30:38 PM PDT 24
Finished Aug 19 04:30:39 PM PDT 24
Peak memory 195184 kb
Host smart-8239967a-1091-4dac-a4e2-769d29936511
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712544277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.1
712544277
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1172188091
Short name T1098
Test name
Test status
Simulation time 165062188 ps
CPU time 0.95 seconds
Started Aug 19 04:30:51 PM PDT 24
Finished Aug 19 04:30:52 PM PDT 24
Peak memory 195336 kb
Host smart-e164cc70-8183-4d46-b25e-685c2b1f01e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172188091 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.1172188091
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.1622802608
Short name T1071
Test name
Test status
Simulation time 48582465 ps
CPU time 0.63 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 198468 kb
Host smart-34fd60d2-c29f-44e1-b762-fd8b275b2b76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622802608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.1622802608
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.688847164
Short name T158
Test name
Test status
Simulation time 16667915 ps
CPU time 0.59 seconds
Started Aug 19 04:30:56 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 195084 kb
Host smart-170ca2d0-d1ff-4b2e-9ec5-109f861e7877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688847164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.688847164
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.4280301935
Short name T1053
Test name
Test status
Simulation time 48400927 ps
CPU time 0.7 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 195272 kb
Host smart-f683bd25-6aa5-419f-992a-bc1578cb2b53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280301935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.4280301935
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.4019640501
Short name T1028
Test name
Test status
Simulation time 33106924 ps
CPU time 1.44 seconds
Started Aug 19 04:30:43 PM PDT 24
Finished Aug 19 04:30:45 PM PDT 24
Peak memory 195588 kb
Host smart-421ddd8b-cf19-4848-847f-1c9da27a51ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019640501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.4019640501
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2687219991
Short name T150
Test name
Test status
Simulation time 112394037 ps
CPU time 1.15 seconds
Started Aug 19 04:30:55 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 200164 kb
Host smart-5c9a3bf4-f7ef-4e1b-9344-ca32c7f5cfc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687219991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.2687219991
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1419743679
Short name T1084
Test name
Test status
Simulation time 19030683 ps
CPU time 0.67 seconds
Started Aug 19 04:31:02 PM PDT 24
Finished Aug 19 04:31:02 PM PDT 24
Peak memory 195232 kb
Host smart-5b1a502c-0457-40d9-a33b-2f977c02bceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419743679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.1419743679
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1074645878
Short name T1088
Test name
Test status
Simulation time 21850749 ps
CPU time 0.61 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 195232 kb
Host smart-d9b5f163-456f-4e62-bfd1-8895fdc159f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074645878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1074645878
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.3952042304
Short name T1114
Test name
Test status
Simulation time 45850817 ps
CPU time 0.67 seconds
Started Aug 19 04:31:18 PM PDT 24
Finished Aug 19 04:31:19 PM PDT 24
Peak memory 195232 kb
Host smart-58b890f1-601e-4ce2-90b2-45aa1605fca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952042304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3952042304
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.460886430
Short name T65
Test name
Test status
Simulation time 19883153 ps
CPU time 0.59 seconds
Started Aug 19 04:31:03 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 195228 kb
Host smart-7126cc1d-db3b-4e99-8a6a-9bcf5548f534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460886430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.460886430
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.3807692755
Short name T1109
Test name
Test status
Simulation time 16066105 ps
CPU time 0.58 seconds
Started Aug 19 04:31:16 PM PDT 24
Finished Aug 19 04:31:16 PM PDT 24
Peak memory 195132 kb
Host smart-a757ec35-033e-4dd6-819a-5af93ae76976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807692755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.3807692755
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3568850117
Short name T1103
Test name
Test status
Simulation time 17480392 ps
CPU time 0.66 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 195192 kb
Host smart-48a33342-8c7b-457d-bfa4-844ccb8094ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568850117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3568850117
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.1122188276
Short name T1008
Test name
Test status
Simulation time 18500666 ps
CPU time 0.61 seconds
Started Aug 19 04:31:02 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 195140 kb
Host smart-b901859f-cc42-4690-b9e1-c0d28aac49d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122188276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.1122188276
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3077312736
Short name T1073
Test name
Test status
Simulation time 47309001 ps
CPU time 0.67 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 195184 kb
Host smart-039e1910-1b5d-4d70-9afe-9cc4f4ec13bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077312736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3077312736
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2133992299
Short name T1099
Test name
Test status
Simulation time 36713272 ps
CPU time 0.57 seconds
Started Aug 19 04:31:13 PM PDT 24
Finished Aug 19 04:31:13 PM PDT 24
Peak memory 195124 kb
Host smart-d33a792e-67d1-4dc5-ac7a-49f8de42c08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133992299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2133992299
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.178699007
Short name T1051
Test name
Test status
Simulation time 19474367 ps
CPU time 0.67 seconds
Started Aug 19 04:31:13 PM PDT 24
Finished Aug 19 04:31:14 PM PDT 24
Peak memory 195220 kb
Host smart-74e3aa78-efc7-465b-9c43-5b443748a22f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178699007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.178699007
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.4052173393
Short name T113
Test name
Test status
Simulation time 39378787 ps
CPU time 0.79 seconds
Started Aug 19 04:30:57 PM PDT 24
Finished Aug 19 04:30:58 PM PDT 24
Peak memory 195212 kb
Host smart-0492d93e-255c-4ea5-9ef2-2def2f7a05fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052173393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.4
052173393
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1862147446
Short name T1037
Test name
Test status
Simulation time 225656559 ps
CPU time 1.98 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 195380 kb
Host smart-389e86ab-5e62-43cf-8c0a-478d1a517bc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862147446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1
862147446
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2144802051
Short name T1038
Test name
Test status
Simulation time 35181896 ps
CPU time 0.64 seconds
Started Aug 19 04:31:01 PM PDT 24
Finished Aug 19 04:31:01 PM PDT 24
Peak memory 197800 kb
Host smart-ea4df5c2-7c4d-4253-9f78-15b9e9e54b08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144802051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.2
144802051
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1339081853
Short name T1062
Test name
Test status
Simulation time 71809479 ps
CPU time 1.32 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 197972 kb
Host smart-f9550e3c-f2ba-4ed5-9a27-58175bb2a5ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339081853 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.1339081853
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3700606046
Short name T118
Test name
Test status
Simulation time 44744097 ps
CPU time 0.66 seconds
Started Aug 19 04:31:02 PM PDT 24
Finished Aug 19 04:31:02 PM PDT 24
Peak memory 197704 kb
Host smart-1c525cfb-5c5f-46cc-acdd-e9a5dba05b71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700606046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.3700606046
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3182113373
Short name T1067
Test name
Test status
Simulation time 22392671 ps
CPU time 0.61 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 195236 kb
Host smart-d04fb754-f097-4bab-a363-552fc891ea87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182113373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.3182113373
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.245403851
Short name T1057
Test name
Test status
Simulation time 21380363 ps
CPU time 0.73 seconds
Started Aug 19 04:31:15 PM PDT 24
Finished Aug 19 04:31:16 PM PDT 24
Peak memory 197496 kb
Host smart-087788ab-758b-43f7-b8dd-792c5b5be052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245403851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sam
e_csr_outstanding.245403851
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.2927843774
Short name T70
Test name
Test status
Simulation time 226788051 ps
CPU time 1.94 seconds
Started Aug 19 04:31:00 PM PDT 24
Finished Aug 19 04:31:02 PM PDT 24
Peak memory 196680 kb
Host smart-bf21e3b4-8317-4dee-8d7e-60aec0e9f80d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927843774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.2927843774
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1467886433
Short name T1061
Test name
Test status
Simulation time 125686339 ps
CPU time 1.04 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 195572 kb
Host smart-af0f53eb-2b22-4121-841a-2c3959eb4bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467886433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1467886433
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1990324720
Short name T1089
Test name
Test status
Simulation time 41063489 ps
CPU time 0.63 seconds
Started Aug 19 04:31:17 PM PDT 24
Finished Aug 19 04:31:18 PM PDT 24
Peak memory 195208 kb
Host smart-742f967f-dc10-4b7c-b4ac-435ef5134d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990324720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.1990324720
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1497809943
Short name T1045
Test name
Test status
Simulation time 18608048 ps
CPU time 0.6 seconds
Started Aug 19 04:31:05 PM PDT 24
Finished Aug 19 04:31:05 PM PDT 24
Peak memory 195240 kb
Host smart-c012b4d7-2c59-4e3f-82ab-48f192f21098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497809943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1497809943
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3452741074
Short name T1111
Test name
Test status
Simulation time 32594099 ps
CPU time 0.61 seconds
Started Aug 19 04:31:09 PM PDT 24
Finished Aug 19 04:31:09 PM PDT 24
Peak memory 195208 kb
Host smart-d3edf3cd-11ce-4154-a3cc-2752b8ef4ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452741074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3452741074
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.1009695755
Short name T159
Test name
Test status
Simulation time 41576991 ps
CPU time 0.61 seconds
Started Aug 19 04:31:16 PM PDT 24
Finished Aug 19 04:31:17 PM PDT 24
Peak memory 195116 kb
Host smart-6abf2249-9e04-4c4b-8263-c051e80c8a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009695755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.1009695755
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.3693712918
Short name T1059
Test name
Test status
Simulation time 18244315 ps
CPU time 0.61 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 195448 kb
Host smart-2c3215dc-0c0e-4471-b4e2-454826e8461f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693712918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3693712918
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.971931302
Short name T1012
Test name
Test status
Simulation time 101617017 ps
CPU time 0.6 seconds
Started Aug 19 04:31:11 PM PDT 24
Finished Aug 19 04:31:12 PM PDT 24
Peak memory 195220 kb
Host smart-c63c6fce-0ac1-479d-8fd1-804464669743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971931302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.971931302
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.559647620
Short name T1092
Test name
Test status
Simulation time 17915624 ps
CPU time 0.59 seconds
Started Aug 19 04:31:00 PM PDT 24
Finished Aug 19 04:31:01 PM PDT 24
Peak memory 195212 kb
Host smart-ccd117e7-dd59-4170-ba12-85c802428957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559647620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.559647620
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.2021757332
Short name T154
Test name
Test status
Simulation time 24677662 ps
CPU time 0.62 seconds
Started Aug 19 04:31:02 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 195132 kb
Host smart-1be0535d-dd09-4461-888a-3c3f7bc51d96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021757332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.2021757332
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.364694749
Short name T1064
Test name
Test status
Simulation time 22539766 ps
CPU time 0.61 seconds
Started Aug 19 04:31:01 PM PDT 24
Finished Aug 19 04:31:02 PM PDT 24
Peak memory 195244 kb
Host smart-df815b52-a734-40d0-9558-d63872c9db37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364694749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.364694749
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.4163525576
Short name T998
Test name
Test status
Simulation time 62122089 ps
CPU time 0.56 seconds
Started Aug 19 04:31:02 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 195132 kb
Host smart-3a53286c-d717-4f8f-b8e2-d813c060bb17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163525576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.4163525576
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2259746579
Short name T1001
Test name
Test status
Simulation time 42239097 ps
CPU time 0.79 seconds
Started Aug 19 04:30:52 PM PDT 24
Finished Aug 19 04:30:53 PM PDT 24
Peak memory 195412 kb
Host smart-03390558-d13a-4234-a1a2-18cbd5a28317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259746579 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.2259746579
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3759676513
Short name T116
Test name
Test status
Simulation time 20987701 ps
CPU time 0.63 seconds
Started Aug 19 04:30:49 PM PDT 24
Finished Aug 19 04:30:50 PM PDT 24
Peak memory 197404 kb
Host smart-afa47a6c-1609-4f0e-bbc2-296be653bff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759676513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3759676513
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.278697509
Short name T1047
Test name
Test status
Simulation time 34580666 ps
CPU time 0.62 seconds
Started Aug 19 04:30:57 PM PDT 24
Finished Aug 19 04:30:57 PM PDT 24
Peak memory 195192 kb
Host smart-cac0756b-7ccf-4778-90b0-512062af2a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278697509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.278697509
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.4216184229
Short name T1040
Test name
Test status
Simulation time 44681323 ps
CPU time 0.9 seconds
Started Aug 19 04:31:02 PM PDT 24
Finished Aug 19 04:31:03 PM PDT 24
Peak memory 195200 kb
Host smart-3cea97f5-afdd-42eb-94a9-3fbc3b1ff6ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216184229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.4216184229
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1041487107
Short name T997
Test name
Test status
Simulation time 119233938 ps
CPU time 1.2 seconds
Started Aug 19 04:32:05 PM PDT 24
Finished Aug 19 04:32:07 PM PDT 24
Peak memory 194688 kb
Host smart-39806569-9d5e-4b75-9272-6bebccf4250e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041487107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1041487107
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.4035186217
Short name T152
Test name
Test status
Simulation time 221081579 ps
CPU time 1.44 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:54 PM PDT 24
Peak memory 200552 kb
Host smart-afb6e9c6-c765-4125-a5de-d2a2b2f7ec2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035186217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.4035186217
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.4281261903
Short name T1042
Test name
Test status
Simulation time 50034429 ps
CPU time 1.4 seconds
Started Aug 19 04:32:09 PM PDT 24
Finished Aug 19 04:32:10 PM PDT 24
Peak memory 197452 kb
Host smart-83e8d1d6-2eb4-4040-b520-ce76b3dbfe3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281261903 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.4281261903
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1511353123
Short name T125
Test name
Test status
Simulation time 23122054 ps
CPU time 0.62 seconds
Started Aug 19 04:30:55 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 197436 kb
Host smart-908237b4-53fb-4fee-a427-b63d290033b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511353123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1511353123
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.3259684046
Short name T1021
Test name
Test status
Simulation time 30626946 ps
CPU time 0.59 seconds
Started Aug 19 04:30:59 PM PDT 24
Finished Aug 19 04:30:59 PM PDT 24
Peak memory 195108 kb
Host smart-a999d484-ed79-4f13-9e49-db5ecbab38ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259684046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.3259684046
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.925161965
Short name T1063
Test name
Test status
Simulation time 30574671 ps
CPU time 0.88 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:31:56 PM PDT 24
Peak memory 192368 kb
Host smart-f2d6d413-7c60-4595-aa95-912b771791b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925161965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sam
e_csr_outstanding.925161965
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.491996736
Short name T1100
Test name
Test status
Simulation time 108909204 ps
CPU time 1.34 seconds
Started Aug 19 04:30:47 PM PDT 24
Finished Aug 19 04:30:49 PM PDT 24
Peak memory 197456 kb
Host smart-42afe167-4d28-43ff-bed4-3509e26859c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491996736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.491996736
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.4258434883
Short name T54
Test name
Test status
Simulation time 198205291 ps
CPU time 1.57 seconds
Started Aug 19 04:30:57 PM PDT 24
Finished Aug 19 04:30:59 PM PDT 24
Peak memory 200496 kb
Host smart-6de08916-8a00-4ca8-ae37-b01fbf05c6a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258434883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.4258434883
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2494876757
Short name T1010
Test name
Test status
Simulation time 37543587 ps
CPU time 0.81 seconds
Started Aug 19 04:30:38 PM PDT 24
Finished Aug 19 04:30:38 PM PDT 24
Peak memory 195444 kb
Host smart-5715b623-35de-4e57-81d8-8ec92d647f8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494876757 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.2494876757
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.1695535824
Short name T1081
Test name
Test status
Simulation time 54491205 ps
CPU time 0.65 seconds
Started Aug 19 04:30:47 PM PDT 24
Finished Aug 19 04:30:48 PM PDT 24
Peak memory 197416 kb
Host smart-b6ec91a4-821c-469c-9c5b-01524ec0bd65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695535824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1695535824
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.3031880279
Short name T1101
Test name
Test status
Simulation time 19161120 ps
CPU time 0.59 seconds
Started Aug 19 04:30:58 PM PDT 24
Finished Aug 19 04:30:58 PM PDT 24
Peak memory 195236 kb
Host smart-f7f4fe3a-5ec6-44ca-b1c1-ca1a37590d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031880279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.3031880279
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2746946384
Short name T1112
Test name
Test status
Simulation time 39341336 ps
CPU time 0.76 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:31:00 PM PDT 24
Peak memory 198928 kb
Host smart-43b30b1d-99fe-4f53-b700-888b85148343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746946384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.2746946384
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1385847896
Short name T1035
Test name
Test status
Simulation time 128506976 ps
CPU time 2.43 seconds
Started Aug 19 04:30:53 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 197716 kb
Host smart-75c063f8-b4bf-410a-8fe0-cfb1a8e5212d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385847896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1385847896
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2486217021
Short name T1076
Test name
Test status
Simulation time 221763082 ps
CPU time 1.67 seconds
Started Aug 19 04:32:25 PM PDT 24
Finished Aug 19 04:32:27 PM PDT 24
Peak memory 200672 kb
Host smart-d11772bf-a899-4ace-9662-6d9dbd217ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486217021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.2486217021
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2255954228
Short name T1090
Test name
Test status
Simulation time 141263608 ps
CPU time 0.83 seconds
Started Aug 19 04:30:48 PM PDT 24
Finished Aug 19 04:30:49 PM PDT 24
Peak memory 195436 kb
Host smart-179cae72-fb4d-466b-8a12-965172cd855e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255954228 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2255954228
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.838153873
Short name T1069
Test name
Test status
Simulation time 52308188 ps
CPU time 0.61 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 195192 kb
Host smart-3ee28429-aec4-43a5-86dc-e3b81bd1fa20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838153873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.838153873
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1067895457
Short name T1085
Test name
Test status
Simulation time 155335410 ps
CPU time 0.91 seconds
Started Aug 19 04:30:54 PM PDT 24
Finished Aug 19 04:30:55 PM PDT 24
Peak memory 198736 kb
Host smart-5ba8f881-ef9b-4b77-86b0-ebe1500f1642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067895457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.1067895457
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2261478761
Short name T1074
Test name
Test status
Simulation time 410027846 ps
CPU time 2.08 seconds
Started Aug 19 04:30:57 PM PDT 24
Finished Aug 19 04:30:59 PM PDT 24
Peak memory 196596 kb
Host smart-60b696d1-6013-4d9d-b636-4f080a0a15c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261478761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.2261478761
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.4158678028
Short name T1044
Test name
Test status
Simulation time 116496047 ps
CPU time 1.24 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:31:57 PM PDT 24
Peak memory 197612 kb
Host smart-85bc4d2c-2cf1-4a4f-b80e-45535361b137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158678028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.4158678028
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1486467365
Short name T1031
Test name
Test status
Simulation time 45986327 ps
CPU time 0.87 seconds
Started Aug 19 04:31:55 PM PDT 24
Finished Aug 19 04:31:56 PM PDT 24
Peak memory 193084 kb
Host smart-2ae25c92-52c6-47c3-bede-0a1e122e7a35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486467365 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.1486467365
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.4033497420
Short name T999
Test name
Test status
Simulation time 41819957 ps
CPU time 0.61 seconds
Started Aug 19 04:32:20 PM PDT 24
Finished Aug 19 04:32:20 PM PDT 24
Peak memory 197164 kb
Host smart-0fdb7b47-282a-4b85-bbad-c8e094fc2b92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033497420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.4033497420
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2542655118
Short name T1029
Test name
Test status
Simulation time 64507139 ps
CPU time 0.6 seconds
Started Aug 19 04:30:48 PM PDT 24
Finished Aug 19 04:30:49 PM PDT 24
Peak memory 195244 kb
Host smart-60d5483b-9158-4e20-acda-d998130fdd82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542655118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.2542655118
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2938080042
Short name T1023
Test name
Test status
Simulation time 74436211 ps
CPU time 0.71 seconds
Started Aug 19 04:30:56 PM PDT 24
Finished Aug 19 04:30:56 PM PDT 24
Peak memory 197516 kb
Host smart-207dab21-7813-4aa6-a7ad-c0af68e6322c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938080042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.2938080042
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.433340185
Short name T48
Test name
Test status
Simulation time 496892456 ps
CPU time 2.45 seconds
Started Aug 19 04:31:05 PM PDT 24
Finished Aug 19 04:31:07 PM PDT 24
Peak memory 197716 kb
Host smart-7b6f097e-da25-4e6b-8569-0388a15cb0a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433340185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.433340185
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.680668345
Short name T153
Test name
Test status
Simulation time 603556205 ps
CPU time 1.29 seconds
Started Aug 19 04:31:05 PM PDT 24
Finished Aug 19 04:31:07 PM PDT 24
Peak memory 195600 kb
Host smart-9bcc51ac-f96a-4120-aba2-f2c8c5980b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680668345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.
680668345
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3033550486
Short name T741
Test name
Test status
Simulation time 153474724 ps
CPU time 0.86 seconds
Started Aug 19 05:50:13 PM PDT 24
Finished Aug 19 05:50:14 PM PDT 24
Peak memory 200048 kb
Host smart-99d395f1-57a1-4dd8-a905-68d8d2445567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033550486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3033550486
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.3234121974
Short name T991
Test name
Test status
Simulation time 55167190 ps
CPU time 0.84 seconds
Started Aug 19 05:50:15 PM PDT 24
Finished Aug 19 05:50:16 PM PDT 24
Peak memory 199204 kb
Host smart-1a1709f5-e3cf-4160-be4e-d51b01985c9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234121974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.3234121974
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3419025453
Short name T636
Test name
Test status
Simulation time 29595377 ps
CPU time 0.63 seconds
Started Aug 19 05:50:19 PM PDT 24
Finished Aug 19 05:50:19 PM PDT 24
Peak memory 198028 kb
Host smart-bd4f10dd-7872-41a9-8b0f-74a3ca668a0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419025453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.3419025453
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.3754577255
Short name T914
Test name
Test status
Simulation time 403000472 ps
CPU time 0.8 seconds
Started Aug 19 05:50:09 PM PDT 24
Finished Aug 19 05:50:10 PM PDT 24
Peak memory 198400 kb
Host smart-d03b7b0b-3351-4f36-a31d-ac0dc944d41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754577255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3754577255
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.1857405345
Short name T623
Test name
Test status
Simulation time 45977621 ps
CPU time 0.64 seconds
Started Aug 19 05:50:16 PM PDT 24
Finished Aug 19 05:50:17 PM PDT 24
Peak memory 197404 kb
Host smart-9d8d2c57-bf67-4dfd-b4fb-fb7b473880b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857405345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.1857405345
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3475615451
Short name T767
Test name
Test status
Simulation time 31713527 ps
CPU time 0.61 seconds
Started Aug 19 05:50:07 PM PDT 24
Finished Aug 19 05:50:08 PM PDT 24
Peak memory 198120 kb
Host smart-88043d8f-120a-4343-b06b-b18c2fdf02cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475615451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3475615451
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.1405358169
Short name T374
Test name
Test status
Simulation time 44839736 ps
CPU time 0.73 seconds
Started Aug 19 05:50:16 PM PDT 24
Finished Aug 19 05:50:17 PM PDT 24
Peak memory 201320 kb
Host smart-afca96d6-9d6a-4234-bea2-199f5ac5c6c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405358169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.1405358169
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.2003653575
Short name T340
Test name
Test status
Simulation time 128939959 ps
CPU time 0.72 seconds
Started Aug 19 05:50:10 PM PDT 24
Finished Aug 19 05:50:10 PM PDT 24
Peak memory 198536 kb
Host smart-49951a6e-7122-49ff-b2ac-0bae35dc868d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003653575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wa
keup_race.2003653575
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.2866006465
Short name T617
Test name
Test status
Simulation time 137560384 ps
CPU time 0.82 seconds
Started Aug 19 05:50:14 PM PDT 24
Finished Aug 19 05:50:15 PM PDT 24
Peak memory 199704 kb
Host smart-f9cc94be-9080-48d7-9e27-9229ead21783
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866006465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.2866006465
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.2801646239
Short name T456
Test name
Test status
Simulation time 150661736 ps
CPU time 0.8 seconds
Started Aug 19 05:50:18 PM PDT 24
Finished Aug 19 05:50:19 PM PDT 24
Peak memory 209400 kb
Host smart-4a69a2ff-f564-4c7b-a08a-b6fb48984fbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801646239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.2801646239
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.1456022370
Short name T17
Test name
Test status
Simulation time 927039961 ps
CPU time 1.44 seconds
Started Aug 19 05:50:16 PM PDT 24
Finished Aug 19 05:50:17 PM PDT 24
Peak memory 218384 kb
Host smart-312642df-248f-4324-a574-7a68c943642d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456022370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1456022370
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3481792506
Short name T766
Test name
Test status
Simulation time 344858723 ps
CPU time 0.98 seconds
Started Aug 19 05:50:16 PM PDT 24
Finished Aug 19 05:50:17 PM PDT 24
Peak memory 200712 kb
Host smart-596de916-dec8-4213-af0c-18a9983fedd5
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481792506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.3481792506
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2516325837
Short name T806
Test name
Test status
Simulation time 797491323 ps
CPU time 3.08 seconds
Started Aug 19 05:50:09 PM PDT 24
Finished Aug 19 05:50:13 PM PDT 24
Peak memory 201060 kb
Host smart-beface48-8f20-40d1-ae2f-c4efb2d87eb8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516325837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2516325837
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3660669512
Short name T379
Test name
Test status
Simulation time 892453272 ps
CPU time 3.06 seconds
Started Aug 19 05:50:05 PM PDT 24
Finished Aug 19 05:50:09 PM PDT 24
Peak memory 201188 kb
Host smart-2ba4b44c-35d6-4a09-aac0-802ef4a53d3e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660669512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3660669512
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3552576933
Short name T310
Test name
Test status
Simulation time 53602666 ps
CPU time 0.93 seconds
Started Aug 19 05:50:08 PM PDT 24
Finished Aug 19 05:50:09 PM PDT 24
Peak memory 199348 kb
Host smart-e891403d-432a-4057-b4e5-6624e977e27d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552576933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3552576933
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.22521344
Short name T876
Test name
Test status
Simulation time 29479829 ps
CPU time 0.68 seconds
Started Aug 19 05:50:22 PM PDT 24
Finished Aug 19 05:50:23 PM PDT 24
Peak memory 199424 kb
Host smart-89dd470c-c86d-4db0-b373-ebce3f82d3a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22521344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.22521344
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.1277918962
Short name T246
Test name
Test status
Simulation time 5933623440 ps
CPU time 2.74 seconds
Started Aug 19 05:50:02 PM PDT 24
Finished Aug 19 05:50:05 PM PDT 24
Peak memory 201340 kb
Host smart-eed3ef1a-899a-4a85-b156-85121bac7430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277918962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.1277918962
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all_with_rand_reset.634019236
Short name T22
Test name
Test status
Simulation time 814632524 ps
CPU time 3.67 seconds
Started Aug 19 05:50:09 PM PDT 24
Finished Aug 19 05:50:12 PM PDT 24
Peak memory 201308 kb
Host smart-238d396d-be8b-4267-9068-51c3ed02bccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634019236 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all_with_rand_reset.634019236
Directory /workspace/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup.752678357
Short name T859
Test name
Test status
Simulation time 433015398 ps
CPU time 1.07 seconds
Started Aug 19 05:50:18 PM PDT 24
Finished Aug 19 05:50:20 PM PDT 24
Peak memory 199632 kb
Host smart-6074f0e3-b687-41ac-b213-a2d6d8628b3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752678357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.752678357
Directory /workspace/0.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.2541774913
Short name T235
Test name
Test status
Simulation time 105850581 ps
CPU time 0.84 seconds
Started Aug 19 05:50:12 PM PDT 24
Finished Aug 19 05:50:13 PM PDT 24
Peak memory 199440 kb
Host smart-83405293-6509-422d-85d2-82aeac2ca4d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541774913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.2541774913
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.3553270664
Short name T351
Test name
Test status
Simulation time 72908056 ps
CPU time 0.83 seconds
Started Aug 19 05:50:04 PM PDT 24
Finished Aug 19 05:50:05 PM PDT 24
Peak memory 200648 kb
Host smart-1618b66f-a7d0-4078-87a6-8da11ee140a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553270664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.3553270664
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.3259029362
Short name T948
Test name
Test status
Simulation time 138185626 ps
CPU time 0.72 seconds
Started Aug 19 05:50:18 PM PDT 24
Finished Aug 19 05:50:19 PM PDT 24
Peak memory 198772 kb
Host smart-95f0b54c-a905-4bdb-9a9f-2d56b2f470e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259029362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.3259029362
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1311718240
Short name T686
Test name
Test status
Simulation time 32315605 ps
CPU time 0.59 seconds
Started Aug 19 05:50:09 PM PDT 24
Finished Aug 19 05:50:10 PM PDT 24
Peak memory 197328 kb
Host smart-54805fa3-005d-4725-b889-8321100896ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311718240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.1311718240
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.331052154
Short name T401
Test name
Test status
Simulation time 578421188 ps
CPU time 0.84 seconds
Started Aug 19 05:50:09 PM PDT 24
Finished Aug 19 05:50:10 PM PDT 24
Peak memory 198436 kb
Host smart-7dedc21b-e767-4277-8a6f-1f18eb887bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331052154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.331052154
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.4222175279
Short name T797
Test name
Test status
Simulation time 49517900 ps
CPU time 0.63 seconds
Started Aug 19 05:50:13 PM PDT 24
Finished Aug 19 05:50:13 PM PDT 24
Peak memory 198024 kb
Host smart-62357e25-9923-44be-9491-078163c8e9fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222175279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.4222175279
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.2636537231
Short name T893
Test name
Test status
Simulation time 24861567 ps
CPU time 0.61 seconds
Started Aug 19 05:50:15 PM PDT 24
Finished Aug 19 05:50:16 PM PDT 24
Peak memory 198424 kb
Host smart-eca3b994-f6fa-4910-82ba-f0821d9b1e42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636537231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2636537231
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.3077533820
Short name T672
Test name
Test status
Simulation time 79530408 ps
CPU time 0.68 seconds
Started Aug 19 05:50:40 PM PDT 24
Finished Aug 19 05:50:41 PM PDT 24
Peak memory 201344 kb
Host smart-49fc47bd-fae9-405b-b57b-ce18edcf2652
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077533820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.3077533820
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.2761772476
Short name T831
Test name
Test status
Simulation time 145292094 ps
CPU time 0.93 seconds
Started Aug 19 05:50:21 PM PDT 24
Finished Aug 19 05:50:22 PM PDT 24
Peak memory 199576 kb
Host smart-1689c7a6-7488-4bf2-97ac-9f28eb67d5b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761772476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.2761772476
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.2031359351
Short name T828
Test name
Test status
Simulation time 122503213 ps
CPU time 0.79 seconds
Started Aug 19 05:50:12 PM PDT 24
Finished Aug 19 05:50:13 PM PDT 24
Peak memory 199184 kb
Host smart-b1be7ce2-54da-48b4-ac2c-a7a45d25a31b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031359351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.2031359351
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.4099319376
Short name T684
Test name
Test status
Simulation time 100099306 ps
CPU time 1 seconds
Started Aug 19 05:50:11 PM PDT 24
Finished Aug 19 05:50:12 PM PDT 24
Peak memory 209488 kb
Host smart-a668373a-dcba-4772-945a-ad0c09dddbaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099319376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.4099319376
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.1827438599
Short name T978
Test name
Test status
Simulation time 26994062 ps
CPU time 0.68 seconds
Started Aug 19 05:50:08 PM PDT 24
Finished Aug 19 05:50:09 PM PDT 24
Peak memory 199496 kb
Host smart-3bd4c259-f991-4007-b43a-ac034029ea11
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827438599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_c
m_ctrl_config_regwen.1827438599
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.272931130
Short name T486
Test name
Test status
Simulation time 1166306286 ps
CPU time 2.3 seconds
Started Aug 19 05:50:02 PM PDT 24
Finished Aug 19 05:50:04 PM PDT 24
Peak memory 201164 kb
Host smart-066aafea-8639-4147-bd09-71dfd294b9c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272931130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.272931130
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.66526391
Short name T690
Test name
Test status
Simulation time 1386603697 ps
CPU time 2.43 seconds
Started Aug 19 05:50:14 PM PDT 24
Finished Aug 19 05:50:16 PM PDT 24
Peak memory 201036 kb
Host smart-f11c2a8c-bdcb-4fa0-95d1-a5097acae7b8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66526391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.66526391
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.127843866
Short name T343
Test name
Test status
Simulation time 95610182 ps
CPU time 0.8 seconds
Started Aug 19 05:50:08 PM PDT 24
Finished Aug 19 05:50:09 PM PDT 24
Peak memory 199420 kb
Host smart-a4ebb24e-5d03-4240-bb58-7c8e74939851
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127843866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.127843866
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.317547735
Short name T354
Test name
Test status
Simulation time 31757788 ps
CPU time 0.66 seconds
Started Aug 19 05:50:07 PM PDT 24
Finished Aug 19 05:50:08 PM PDT 24
Peak memory 199452 kb
Host smart-fae14c8d-7908-4b50-a378-006734564bf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317547735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.317547735
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.3425909088
Short name T323
Test name
Test status
Simulation time 370834066 ps
CPU time 1.1 seconds
Started Aug 19 05:50:13 PM PDT 24
Finished Aug 19 05:50:14 PM PDT 24
Peak memory 200364 kb
Host smart-25bbb5bb-20f4-4ebe-b891-7eb314b2fbad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425909088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.3425909088
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1973029813
Short name T436
Test name
Test status
Simulation time 5472884968 ps
CPU time 7.8 seconds
Started Aug 19 05:49:59 PM PDT 24
Finished Aug 19 05:50:07 PM PDT 24
Peak memory 201352 kb
Host smart-759a4463-6a8f-4aec-9249-e02b1a3a35a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973029813 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all_with_rand_reset.1973029813
Directory /workspace/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.3715234914
Short name T950
Test name
Test status
Simulation time 246697229 ps
CPU time 0.66 seconds
Started Aug 19 05:50:11 PM PDT 24
Finished Aug 19 05:50:12 PM PDT 24
Peak memory 198316 kb
Host smart-3e56cd80-f3b7-4ccc-baf5-cda118e382cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715234914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.3715234914
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.136239324
Short name T537
Test name
Test status
Simulation time 282131975 ps
CPU time 1.43 seconds
Started Aug 19 05:50:05 PM PDT 24
Finished Aug 19 05:50:06 PM PDT 24
Peak memory 200868 kb
Host smart-21189e0b-9d05-414c-a0a2-ce3018b02667
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136239324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.136239324
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.1955834672
Short name T317
Test name
Test status
Simulation time 71449507 ps
CPU time 0.84 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:50:50 PM PDT 24
Peak memory 200188 kb
Host smart-46170506-a445-4b73-9b1e-5cc1e0577dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955834672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.1955834672
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1685630932
Short name T322
Test name
Test status
Simulation time 31539772 ps
CPU time 0.71 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 197940 kb
Host smart-9f1f0145-7eb8-4df5-8c58-e34177ef9ec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685630932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.1685630932
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.4106167716
Short name T946
Test name
Test status
Simulation time 113620566 ps
CPU time 0.83 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:13 PM PDT 24
Peak memory 198152 kb
Host smart-3a22decf-0529-4d3c-b217-ea57965ae5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106167716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.4106167716
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.3254686430
Short name T778
Test name
Test status
Simulation time 49832796 ps
CPU time 0.67 seconds
Started Aug 19 05:50:58 PM PDT 24
Finished Aug 19 05:50:59 PM PDT 24
Peak memory 198080 kb
Host smart-fd0c634b-921b-45ed-8670-06ce011a357b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254686430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.3254686430
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.2835268544
Short name T170
Test name
Test status
Simulation time 27716206 ps
CPU time 0.6 seconds
Started Aug 19 05:51:16 PM PDT 24
Finished Aug 19 05:51:16 PM PDT 24
Peak memory 198108 kb
Host smart-f1c03685-bfb4-4e2a-9523-ee6dd10d78bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835268544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2835268544
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.2011729374
Short name T377
Test name
Test status
Simulation time 87869400 ps
CPU time 0.63 seconds
Started Aug 19 05:50:46 PM PDT 24
Finished Aug 19 05:50:47 PM PDT 24
Peak memory 201372 kb
Host smart-ab46c192-5426-4e45-a0b9-241f12196b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011729374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.2011729374
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.1089138935
Short name T496
Test name
Test status
Simulation time 260566808 ps
CPU time 0.86 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 198428 kb
Host smart-193f79e5-9db6-4b0d-b691-5f448d8a3007
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089138935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_w
akeup_race.1089138935
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.696194239
Short name T793
Test name
Test status
Simulation time 45921906 ps
CPU time 0.63 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 198320 kb
Host smart-342c1cd8-f814-4610-acbd-d4ce3ecef1dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696194239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.696194239
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.1943961070
Short name T974
Test name
Test status
Simulation time 156879293 ps
CPU time 0.75 seconds
Started Aug 19 05:50:52 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 209388 kb
Host smart-7e7517ec-8876-4246-90e1-e40646afbf7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943961070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1943961070
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.1205162115
Short name T755
Test name
Test status
Simulation time 173834783 ps
CPU time 0.92 seconds
Started Aug 19 05:50:45 PM PDT 24
Finished Aug 19 05:50:46 PM PDT 24
Peak memory 200064 kb
Host smart-d40c6397-e610-4592-be15-77908c5648e9
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205162115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_
cm_ctrl_config_regwen.1205162115
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3213571558
Short name T921
Test name
Test status
Simulation time 1149637075 ps
CPU time 2.15 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 201068 kb
Host smart-6718bcc5-8f53-42c8-bab4-2cb8f0724682
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213571558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3213571558
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.90619315
Short name T599
Test name
Test status
Simulation time 1108807041 ps
CPU time 2.52 seconds
Started Aug 19 05:50:45 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 201112 kb
Host smart-0915a28e-7cea-4a60-b222-a193d0fd0fa4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90619315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.90619315
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1697881011
Short name T250
Test name
Test status
Simulation time 66562885 ps
CPU time 0.81 seconds
Started Aug 19 05:50:58 PM PDT 24
Finished Aug 19 05:50:59 PM PDT 24
Peak memory 199176 kb
Host smart-f62e7444-dbd1-4d84-b899-3ace7223af93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697881011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1697881011
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.3035890921
Short name T288
Test name
Test status
Simulation time 29472280 ps
CPU time 0.74 seconds
Started Aug 19 05:51:02 PM PDT 24
Finished Aug 19 05:51:03 PM PDT 24
Peak memory 199428 kb
Host smart-0d99f79f-deb4-4fb1-aa3c-468fb33bc053
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035890921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.3035890921
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all.3452832779
Short name T429
Test name
Test status
Simulation time 3289249255 ps
CPU time 2.48 seconds
Started Aug 19 05:50:45 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 201232 kb
Host smart-20e0a144-480a-4b0b-87fb-6af89e1103ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452832779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.3452832779
Directory /workspace/10.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3599750881
Short name T131
Test name
Test status
Simulation time 1500907061 ps
CPU time 2.07 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 201408 kb
Host smart-e56ea9b8-12b7-4b57-a1d9-f36cf477756c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599750881 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all_with_rand_reset.3599750881
Directory /workspace/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.1475628158
Short name T457
Test name
Test status
Simulation time 137933140 ps
CPU time 0.97 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:45 PM PDT 24
Peak memory 199116 kb
Host smart-ce6a54d5-c3a4-4afd-9aed-e30d360d3d04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475628158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.1475628158
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.3331923343
Short name T238
Test name
Test status
Simulation time 330635023 ps
CPU time 1.01 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 200212 kb
Host smart-a3c73bad-afdc-415d-8db9-2ada6746b72b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331923343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.3331923343
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3810783178
Short name T110
Test name
Test status
Simulation time 42378491 ps
CPU time 0.72 seconds
Started Aug 19 05:50:48 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 198888 kb
Host smart-b2e920f4-dad5-4e25-badf-1169398daa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810783178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3810783178
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.1679665342
Short name T428
Test name
Test status
Simulation time 57282907 ps
CPU time 0.82 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 199212 kb
Host smart-296af613-bb17-4c8d-83ec-1d12918e21b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679665342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.1679665342
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3748957679
Short name T743
Test name
Test status
Simulation time 39010494 ps
CPU time 0.57 seconds
Started Aug 19 05:50:48 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 197984 kb
Host smart-581f71aa-3348-4151-9030-447860e0e711
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748957679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.3748957679
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.2645575893
Short name T512
Test name
Test status
Simulation time 112684295 ps
CPU time 0.84 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 198288 kb
Host smart-1f60f467-b467-4494-92a0-fe72feeb0939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645575893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.2645575893
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.3025754847
Short name T529
Test name
Test status
Simulation time 50694661 ps
CPU time 0.66 seconds
Started Aug 19 05:51:18 PM PDT 24
Finished Aug 19 05:51:19 PM PDT 24
Peak memory 198184 kb
Host smart-0db6dff1-ff8d-46cf-a9de-e94f0f8c4126
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025754847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.3025754847
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1670609625
Short name T183
Test name
Test status
Simulation time 104615903 ps
CPU time 0.6 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:51:00 PM PDT 24
Peak memory 198132 kb
Host smart-515e1906-6073-4502-a5fb-ef89c48b012d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670609625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1670609625
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.1646666674
Short name T895
Test name
Test status
Simulation time 559615382 ps
CPU time 0.99 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 199828 kb
Host smart-f4864d3c-39c1-4d5f-ae30-c22bff8c4829
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646666674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_w
akeup_race.1646666674
Directory /workspace/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.2598729596
Short name T711
Test name
Test status
Simulation time 67564847 ps
CPU time 0.68 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:51:00 PM PDT 24
Peak memory 199192 kb
Host smart-8bc14d55-20e2-42c1-8b14-5ccd5c05726e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598729596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.2598729596
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.3168941125
Short name T691
Test name
Test status
Simulation time 113178003 ps
CPU time 0.91 seconds
Started Aug 19 05:50:52 PM PDT 24
Finished Aug 19 05:50:53 PM PDT 24
Peak memory 209324 kb
Host smart-48f5e09b-564d-442d-a51a-97d919ae4508
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168941125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3168941125
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.3426330835
Short name T920
Test name
Test status
Simulation time 250032832 ps
CPU time 0.83 seconds
Started Aug 19 05:50:41 PM PDT 24
Finished Aug 19 05:50:42 PM PDT 24
Peak memory 198700 kb
Host smart-4312cc7b-c394-454b-8342-8600189a9cd4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426330835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_
cm_ctrl_config_regwen.3426330835
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1524097559
Short name T845
Test name
Test status
Simulation time 917427545 ps
CPU time 2.52 seconds
Started Aug 19 05:50:47 PM PDT 24
Finished Aug 19 05:50:50 PM PDT 24
Peak memory 201120 kb
Host smart-a3a7127d-c04b-45c7-b906-adfe3f920dc0
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524097559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1524097559
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1590048729
Short name T241
Test name
Test status
Simulation time 2025688888 ps
CPU time 2.29 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:50:53 PM PDT 24
Peak memory 201124 kb
Host smart-e55c4c1a-2e93-42a7-8b38-b462b2b171b4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590048729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1590048729
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.699709824
Short name T935
Test name
Test status
Simulation time 341731449 ps
CPU time 0.91 seconds
Started Aug 19 05:51:02 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 199132 kb
Host smart-9dcc7d43-c056-4a1e-8cce-d0b9a0d1bc9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699709824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_
mubi.699709824
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.982148936
Short name T862
Test name
Test status
Simulation time 29104772 ps
CPU time 0.68 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 199440 kb
Host smart-3c9bfbfc-6fbc-4080-83d3-faa51db4773a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982148936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.982148936
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.1817519245
Short name T103
Test name
Test status
Simulation time 310172826 ps
CPU time 1.48 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:05 PM PDT 24
Peak memory 201148 kb
Host smart-d2b6ef99-6b86-4bc7-a8b7-9582a1087c29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817519245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.1817519245
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all_with_rand_reset.3092719179
Short name T135
Test name
Test status
Simulation time 6113491678 ps
CPU time 14.39 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:51:03 PM PDT 24
Peak memory 201416 kb
Host smart-d30d5339-084a-437b-b2b7-b43dba273cd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092719179 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand_reset.3092719179
Directory /workspace/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.1203106711
Short name T807
Test name
Test status
Simulation time 44777963 ps
CPU time 0.71 seconds
Started Aug 19 05:51:27 PM PDT 24
Finished Aug 19 05:51:28 PM PDT 24
Peak memory 199244 kb
Host smart-870e1330-4f68-4be5-bdb6-7eb3c30ca776
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203106711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.1203106711
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.3458322405
Short name T403
Test name
Test status
Simulation time 198235185 ps
CPU time 1 seconds
Started Aug 19 05:50:47 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 199988 kb
Host smart-1ba52704-dfbb-4cf2-884b-2b4931a885bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458322405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.3458322405
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.258265041
Short name T391
Test name
Test status
Simulation time 142143491 ps
CPU time 0.74 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:45 PM PDT 24
Peak memory 198872 kb
Host smart-42e1eb59-a176-475f-8612-f8af964278c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258265041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.258265041
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.2595008986
Short name T666
Test name
Test status
Simulation time 39498630 ps
CPU time 0.6 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 197864 kb
Host smart-c8b282cf-1d41-41c3-ad3c-ce4c3794524c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595008986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.2595008986
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.3230509380
Short name T864
Test name
Test status
Simulation time 276308159 ps
CPU time 0.87 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 198176 kb
Host smart-fd347753-9bac-4972-9506-0a84876b0645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230509380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.3230509380
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.3028961904
Short name T774
Test name
Test status
Simulation time 40471018 ps
CPU time 0.64 seconds
Started Aug 19 05:50:41 PM PDT 24
Finished Aug 19 05:50:42 PM PDT 24
Peak memory 198140 kb
Host smart-37c1dfc3-e9c2-4efa-a29f-13f7aeea8bb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028961904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.3028961904
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.890134859
Short name T688
Test name
Test status
Simulation time 51597647 ps
CPU time 0.67 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 198100 kb
Host smart-50740449-afb5-4a76-b520-ee0e419b7b0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890134859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.890134859
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.1511898371
Short name T41
Test name
Test status
Simulation time 43177717 ps
CPU time 0.71 seconds
Started Aug 19 05:51:05 PM PDT 24
Finished Aug 19 05:51:06 PM PDT 24
Peak memory 201316 kb
Host smart-4fb2ef76-8c24-4b8e-b08f-cac594295d56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511898371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.1511898371
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.65794964
Short name T771
Test name
Test status
Simulation time 220052379 ps
CPU time 1.13 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:50:50 PM PDT 24
Peak memory 199692 kb
Host smart-2a9087ee-bdc0-4b00-988e-36c11baa82d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65794964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup
_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wak
eup_race.65794964
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.4073035082
Short name T224
Test name
Test status
Simulation time 126567973 ps
CPU time 0.74 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 199140 kb
Host smart-dd21b43d-5113-4073-b146-cc8292b5fd31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073035082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.4073035082
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.341234259
Short name T380
Test name
Test status
Simulation time 105808518 ps
CPU time 0.91 seconds
Started Aug 19 05:51:05 PM PDT 24
Finished Aug 19 05:51:06 PM PDT 24
Peak memory 209332 kb
Host smart-246a8e94-0bed-482f-9dc3-770356ba7c55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341234259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.341234259
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.2036811665
Short name T590
Test name
Test status
Simulation time 344416675 ps
CPU time 0.98 seconds
Started Aug 19 05:50:40 PM PDT 24
Finished Aug 19 05:50:41 PM PDT 24
Peak memory 200768 kb
Host smart-1a91ff2c-eaae-46b6-8c7f-ae9271e0273f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036811665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.2036811665
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2038584940
Short name T28
Test name
Test status
Simulation time 1234419561 ps
CPU time 2.24 seconds
Started Aug 19 05:50:46 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 201040 kb
Host smart-8745d694-f3de-49ca-8ae9-48f3a268a91f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038584940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2038584940
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2319876471
Short name T930
Test name
Test status
Simulation time 983055025 ps
CPU time 2.54 seconds
Started Aug 19 05:50:48 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 201108 kb
Host smart-5e25fa25-f58c-4957-958d-79902d2f1909
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319876471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2319876471
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3610554122
Short name T847
Test name
Test status
Simulation time 94114348 ps
CPU time 0.86 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 199552 kb
Host smart-48958615-ed26-4730-b128-39f6202f44a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610554122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3610554122
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.3161501701
Short name T894
Test name
Test status
Simulation time 46199233 ps
CPU time 0.66 seconds
Started Aug 19 05:50:46 PM PDT 24
Finished Aug 19 05:50:47 PM PDT 24
Peak memory 198560 kb
Host smart-18602850-c934-47b4-ae2c-b09ddd1fa039
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161501701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3161501701
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.1481663455
Short name T14
Test name
Test status
Simulation time 3627375397 ps
CPU time 4.92 seconds
Started Aug 19 05:51:22 PM PDT 24
Finished Aug 19 05:51:28 PM PDT 24
Peak memory 201216 kb
Host smart-661e5764-9873-4785-a746-81f385cdc92f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481663455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.1481663455
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all_with_rand_reset.4014498181
Short name T82
Test name
Test status
Simulation time 7754038240 ps
CPU time 11.15 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:51:07 PM PDT 24
Peak memory 201368 kb
Host smart-1084b83c-825e-47de-b9a4-ef13b823d051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014498181 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand_reset.4014498181
Directory /workspace/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.1194927226
Short name T514
Test name
Test status
Simulation time 302520250 ps
CPU time 0.9 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 199536 kb
Host smart-cbb34c3c-9224-4aa6-9473-b7bb30d5a026
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194927226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.1194927226
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.573364130
Short name T314
Test name
Test status
Simulation time 175805197 ps
CPU time 0.87 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 199956 kb
Host smart-a6f04175-9520-4bc8-8c4a-a5e1c2dcc882
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573364130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.573364130
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.2458137912
Short name T985
Test name
Test status
Simulation time 35988095 ps
CPU time 0.77 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 198948 kb
Host smart-f742aeb8-7921-497e-b76b-299597cdd890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458137912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2458137912
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.524520030
Short name T266
Test name
Test status
Simulation time 82343527 ps
CPU time 0.68 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 199136 kb
Host smart-ad4ebd65-8955-46c1-9850-e58722809c83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524520030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disa
ble_rom_integrity_check.524520030
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.120016433
Short name T85
Test name
Test status
Simulation time 31117082 ps
CPU time 0.64 seconds
Started Aug 19 05:50:47 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 197972 kb
Host smart-6fc43976-9429-4c98-8802-1155323669ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120016433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_
malfunc.120016433
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.2716588484
Short name T524
Test name
Test status
Simulation time 114034343 ps
CPU time 0.86 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:45 PM PDT 24
Peak memory 199440 kb
Host smart-f948b734-ac6e-46ed-992a-a1204892ec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716588484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2716588484
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.803027720
Short name T645
Test name
Test status
Simulation time 97711634 ps
CPU time 0.64 seconds
Started Aug 19 05:50:48 PM PDT 24
Finished Aug 19 05:50:49 PM PDT 24
Peak memory 197448 kb
Host smart-4fa5b8c5-1017-4f34-b432-c92d61b790e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803027720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.803027720
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.1289765219
Short name T393
Test name
Test status
Simulation time 36017218 ps
CPU time 0.66 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:50:59 PM PDT 24
Peak memory 198100 kb
Host smart-4b292f48-a6f0-4564-a276-d8bfb68ba28e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289765219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.1289765219
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.1089807608
Short name T365
Test name
Test status
Simulation time 45437498 ps
CPU time 0.68 seconds
Started Aug 19 05:51:11 PM PDT 24
Finished Aug 19 05:51:17 PM PDT 24
Peak memory 201296 kb
Host smart-15ba388b-f2b6-4310-9469-09a1959de53d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089807608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.1089807608
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.2083356343
Short name T185
Test name
Test status
Simulation time 296298294 ps
CPU time 1.1 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 199732 kb
Host smart-366beb98-c70d-4b17-8160-63a10009351b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083356343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.2083356343
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.296762812
Short name T200
Test name
Test status
Simulation time 123146494 ps
CPU time 0.8 seconds
Started Aug 19 05:50:47 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 198728 kb
Host smart-5d31b2dd-2746-40a6-a02f-a57ca8aa9a89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296762812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.296762812
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.1779978371
Short name T179
Test name
Test status
Simulation time 154995812 ps
CPU time 0.78 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 201248 kb
Host smart-f119065d-873e-4ce1-a198-165a115f2007
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779978371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.1779978371
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.804210585
Short name T900
Test name
Test status
Simulation time 316955149 ps
CPU time 0.75 seconds
Started Aug 19 05:51:02 PM PDT 24
Finished Aug 19 05:51:03 PM PDT 24
Peak memory 198748 kb
Host smart-3a1366c3-b6ef-4c02-a388-11b3e5a57e4d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804210585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_c
m_ctrl_config_regwen.804210585
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1928640604
Short name T440
Test name
Test status
Simulation time 1001372517 ps
CPU time 2.49 seconds
Started Aug 19 05:50:57 PM PDT 24
Finished Aug 19 05:51:00 PM PDT 24
Peak memory 201148 kb
Host smart-485d54f1-ae39-4560-84d6-53fbc3eae039
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928640604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1928640604
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1909999023
Short name T839
Test name
Test status
Simulation time 1288623545 ps
CPU time 1.84 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 201088 kb
Host smart-8e13ca3d-6530-48c5-a092-5f6606cc3813
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909999023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1909999023
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.1106402241
Short name T422
Test name
Test status
Simulation time 51506712 ps
CPU time 0.87 seconds
Started Aug 19 05:51:04 PM PDT 24
Finished Aug 19 05:51:05 PM PDT 24
Peak memory 199240 kb
Host smart-162e2ae8-bb9b-4423-b3f4-303bfc7ea916
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106402241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1106402241
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.1367606249
Short name T614
Test name
Test status
Simulation time 61005577 ps
CPU time 0.64 seconds
Started Aug 19 05:50:55 PM PDT 24
Finished Aug 19 05:50:56 PM PDT 24
Peak memory 198552 kb
Host smart-1ac5e3c6-061b-4844-9154-a8e020a67e43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367606249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1367606249
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.419620009
Short name T949
Test name
Test status
Simulation time 665045780 ps
CPU time 1.44 seconds
Started Aug 19 05:50:58 PM PDT 24
Finished Aug 19 05:51:05 PM PDT 24
Peak memory 201188 kb
Host smart-5d4b592c-2143-4263-acd9-6bfa75cea2a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419620009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.419620009
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all_with_rand_reset.1128580428
Short name T45
Test name
Test status
Simulation time 5352638726 ps
CPU time 21.06 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:24 PM PDT 24
Peak memory 209536 kb
Host smart-b20ec6b0-5775-40df-ae52-c85f516269ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128580428 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all_with_rand_reset.1128580428
Directory /workspace/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.3818352345
Short name T585
Test name
Test status
Simulation time 270558337 ps
CPU time 1.37 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 200772 kb
Host smart-4151d544-2929-4f95-b116-98be2c29484e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818352345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.3818352345
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.3534639949
Short name T713
Test name
Test status
Simulation time 395384779 ps
CPU time 1.11 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 200868 kb
Host smart-40c1c5f4-088a-4f0b-9138-9e7de449773f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534639949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.3534639949
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.3654918835
Short name T452
Test name
Test status
Simulation time 39560948 ps
CPU time 0.95 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:51:01 PM PDT 24
Peak memory 200868 kb
Host smart-a0d64564-cb65-4ef8-b946-0a3b8c91fe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654918835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.3654918835
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.295640964
Short name T329
Test name
Test status
Simulation time 73691072 ps
CPU time 0.71 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:50:59 PM PDT 24
Peak memory 198688 kb
Host smart-92e977c0-e654-4954-858e-494c7e7088cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295640964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disa
ble_rom_integrity_check.295640964
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.4293633801
Short name T409
Test name
Test status
Simulation time 32821614 ps
CPU time 0.61 seconds
Started Aug 19 05:50:52 PM PDT 24
Finished Aug 19 05:50:53 PM PDT 24
Peak memory 197128 kb
Host smart-992551e3-86ea-4c8e-b3c9-9755f57056c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293633801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.4293633801
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.2727391510
Short name T822
Test name
Test status
Simulation time 398799091 ps
CPU time 0.82 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 198144 kb
Host smart-7ae1582e-6ccf-40f3-85eb-02af72f744d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727391510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2727391510
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.1662033808
Short name T892
Test name
Test status
Simulation time 43850985 ps
CPU time 0.6 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:45 PM PDT 24
Peak memory 197440 kb
Host smart-41fadeed-207b-4ee4-a0c9-fa204c53ab86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662033808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.1662033808
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.491696726
Short name T473
Test name
Test status
Simulation time 34040510 ps
CPU time 0.59 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 197964 kb
Host smart-2f40c58e-5820-4c82-9322-8696336cd7d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491696726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.491696726
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.80041163
Short name T245
Test name
Test status
Simulation time 78516631 ps
CPU time 0.66 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 201132 kb
Host smart-6374715a-2987-4195-b077-80a749977023
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80041163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid
.80041163
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.943366770
Short name T717
Test name
Test status
Simulation time 107141090 ps
CPU time 0.88 seconds
Started Aug 19 05:51:00 PM PDT 24
Finished Aug 19 05:51:01 PM PDT 24
Peak memory 198356 kb
Host smart-09ff860d-566c-4b5d-b463-d3372851299c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943366770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wa
keup_race.943366770
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.1148078565
Short name T969
Test name
Test status
Simulation time 109823020 ps
CPU time 0.83 seconds
Started Aug 19 05:50:57 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 199696 kb
Host smart-3eaedced-a25d-4ee5-94fb-108cade33e4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148078565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.1148078565
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.3198100723
Short name T909
Test name
Test status
Simulation time 349298579 ps
CPU time 0.79 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:43 PM PDT 24
Peak memory 209340 kb
Host smart-e2b1ad71-16ff-4f0c-930f-18c235d430cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198100723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3198100723
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1684818997
Short name T811
Test name
Test status
Simulation time 868911070 ps
CPU time 2.99 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:17 PM PDT 24
Peak memory 201048 kb
Host smart-a12dac57-396d-4b0b-a40e-ed24531b93fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684818997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1684818997
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.650481809
Short name T376
Test name
Test status
Simulation time 2145160328 ps
CPU time 2.15 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 200980 kb
Host smart-c1780765-6bff-43d2-9edf-b7c9fdc76417
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650481809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.650481809
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2485776240
Short name T705
Test name
Test status
Simulation time 154684435 ps
CPU time 0.89 seconds
Started Aug 19 05:51:01 PM PDT 24
Finished Aug 19 05:51:02 PM PDT 24
Peak memory 199096 kb
Host smart-e87f70bb-0218-4a76-8d9a-bf743ba33310
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485776240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2485776240
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.1719483210
Short name T659
Test name
Test status
Simulation time 39503266 ps
CPU time 0.67 seconds
Started Aug 19 05:50:57 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 199396 kb
Host smart-e2ce2d2b-612a-4ec5-86f0-d608b30ecd84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719483210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.1719483210
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.2516148166
Short name T255
Test name
Test status
Simulation time 1182145889 ps
CPU time 3.29 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:53 PM PDT 24
Peak memory 201152 kb
Host smart-177e6eab-980b-4bad-800d-91d9473d5c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516148166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.2516148166
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all_with_rand_reset.3241012797
Short name T79
Test name
Test status
Simulation time 4324309124 ps
CPU time 6.83 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:50:58 PM PDT 24
Peak memory 201352 kb
Host smart-806ff3c5-52d2-45fa-ae10-53a126c95fa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241012797 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand_reset.3241012797
Directory /workspace/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.3172542442
Short name T511
Test name
Test status
Simulation time 64169062 ps
CPU time 0.74 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:51:00 PM PDT 24
Peak memory 199168 kb
Host smart-2c3d02a6-8cca-4e6f-9355-8451970296bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172542442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.3172542442
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.4062312517
Short name T95
Test name
Test status
Simulation time 290567527 ps
CPU time 1.42 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 200980 kb
Host smart-32269a75-3e4e-4db9-93ed-e28ffa17d802
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062312517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.4062312517
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.3285433082
Short name T823
Test name
Test status
Simulation time 34005520 ps
CPU time 0.63 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:50 PM PDT 24
Peak memory 199204 kb
Host smart-9c68ffef-ddf1-42eb-8bc5-ac4683cadeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285433082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3285433082
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.2721363778
Short name T810
Test name
Test status
Simulation time 68227781 ps
CPU time 0.74 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 198448 kb
Host smart-277fc0d9-b633-4667-94c4-bddc27b339ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721363778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.2721363778
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.486087279
Short name T438
Test name
Test status
Simulation time 29067083 ps
CPU time 0.62 seconds
Started Aug 19 05:50:48 PM PDT 24
Finished Aug 19 05:50:49 PM PDT 24
Peak memory 198024 kb
Host smart-d41640b4-07fc-43a8-b574-73c0ae345524
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486087279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_
malfunc.486087279
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.604737605
Short name T729
Test name
Test status
Simulation time 109443631 ps
CPU time 0.89 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 199164 kb
Host smart-539a63d5-ce24-4cab-95d9-af65dbfaca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604737605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.604737605
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.208308527
Short name T952
Test name
Test status
Simulation time 73441691 ps
CPU time 0.6 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 198096 kb
Host smart-89fb4942-761b-47ed-b01c-09f01b3484a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208308527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.208308527
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.2792418006
Short name T886
Test name
Test status
Simulation time 56081049 ps
CPU time 0.62 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:51:05 PM PDT 24
Peak memory 198136 kb
Host smart-f2a486a3-1e12-4a2b-b3eb-70a99ebec777
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792418006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.2792418006
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.4213920738
Short name T976
Test name
Test status
Simulation time 78466521 ps
CPU time 0.65 seconds
Started Aug 19 05:50:45 PM PDT 24
Finished Aug 19 05:50:46 PM PDT 24
Peak memory 201352 kb
Host smart-7b060ce7-01e5-4916-bf81-94774efa9944
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213920738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.4213920738
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.100056787
Short name T404
Test name
Test status
Simulation time 185028018 ps
CPU time 0.88 seconds
Started Aug 19 05:51:15 PM PDT 24
Finished Aug 19 05:51:22 PM PDT 24
Peak memory 198656 kb
Host smart-e9a0d614-cc2a-4e4f-8eb3-7f55b6455ffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100056787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wa
keup_race.100056787
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.2028844624
Short name T211
Test name
Test status
Simulation time 42205189 ps
CPU time 0.81 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 198728 kb
Host smart-ff0a4cb4-b60c-4046-b26f-324d0db294f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028844624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.2028844624
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.3184965460
Short name T668
Test name
Test status
Simulation time 155068582 ps
CPU time 0.79 seconds
Started Aug 19 05:50:47 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 209408 kb
Host smart-e989642d-1c0c-4ec5-8f1e-2aefe0643b2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184965460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.3184965460
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.4121376277
Short name T279
Test name
Test status
Simulation time 120071938 ps
CPU time 0.88 seconds
Started Aug 19 05:51:01 PM PDT 24
Finished Aug 19 05:51:02 PM PDT 24
Peak memory 198776 kb
Host smart-fc87f9fd-84ee-4266-a061-d791d8d5f82a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121376277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_
cm_ctrl_config_regwen.4121376277
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2315940900
Short name T867
Test name
Test status
Simulation time 1190050886 ps
CPU time 2.22 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:46 PM PDT 24
Peak memory 201108 kb
Host smart-791b977f-d5bb-49e0-bcbf-efe91da8770b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315940900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2315940900
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3267852619
Short name T885
Test name
Test status
Simulation time 1256360410 ps
CPU time 2.43 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:56 PM PDT 24
Peak memory 201044 kb
Host smart-fa9b3bd0-2def-4060-99bd-f09af5b67fc4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267852619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3267852619
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.225181238
Short name T34
Test name
Test status
Simulation time 67750820 ps
CPU time 0.91 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:45 PM PDT 24
Peak memory 199204 kb
Host smart-5bc3fd4e-e97c-43c7-89d7-6d585472dc99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225181238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_
mubi.225181238
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.1753465405
Short name T906
Test name
Test status
Simulation time 30431678 ps
CPU time 0.67 seconds
Started Aug 19 05:50:48 PM PDT 24
Finished Aug 19 05:50:49 PM PDT 24
Peak memory 197592 kb
Host smart-9f09ca99-da89-488f-b4a2-ba502a8df129
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753465405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1753465405
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.2917284622
Short name T765
Test name
Test status
Simulation time 1606037765 ps
CPU time 4.37 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:50:56 PM PDT 24
Peak memory 201152 kb
Host smart-89f6563a-e3f2-4f2b-ab1d-a8c047ea7103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917284622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.2917284622
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.1191243500
Short name T820
Test name
Test status
Simulation time 6230176663 ps
CPU time 10.3 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:51:02 PM PDT 24
Peak memory 201408 kb
Host smart-f9a3b087-5c86-4545-b04b-7bb83b11c142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191243500 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand_reset.1191243500
Directory /workspace/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.2576406811
Short name T459
Test name
Test status
Simulation time 103308362 ps
CPU time 0.79 seconds
Started Aug 19 05:51:02 PM PDT 24
Finished Aug 19 05:51:03 PM PDT 24
Peak memory 199176 kb
Host smart-51a8bb91-b324-48e3-be6a-d570a6c56c18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576406811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.2576406811
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.3783405556
Short name T730
Test name
Test status
Simulation time 223865156 ps
CPU time 0.85 seconds
Started Aug 19 05:51:02 PM PDT 24
Finished Aug 19 05:51:03 PM PDT 24
Peak memory 199696 kb
Host smart-a99e389a-d291-4b37-b36c-e0b67b242002
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783405556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.3783405556
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.1882604516
Short name T840
Test name
Test status
Simulation time 79240221 ps
CPU time 0.72 seconds
Started Aug 19 05:50:55 PM PDT 24
Finished Aug 19 05:50:56 PM PDT 24
Peak memory 198820 kb
Host smart-f1216498-af70-4a6d-b79c-fe35304d1d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882604516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.1882604516
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.3022852805
Short name T977
Test name
Test status
Simulation time 59427847 ps
CPU time 0.84 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 199040 kb
Host smart-f153ab66-1269-4951-bad6-e48fe3efd195
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022852805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.3022852805
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.2493587218
Short name T499
Test name
Test status
Simulation time 34180594 ps
CPU time 0.6 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:53 PM PDT 24
Peak memory 197972 kb
Host smart-58fb49bc-1daf-4c3f-a33c-3e51d1c23fd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493587218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.2493587218
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.2942531145
Short name T857
Test name
Test status
Simulation time 201062795 ps
CPU time 0.87 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 198176 kb
Host smart-9336553e-f4cf-4958-a58d-3180d8088f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942531145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.2942531145
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.2168940498
Short name T321
Test name
Test status
Simulation time 41314809 ps
CPU time 0.59 seconds
Started Aug 19 05:50:47 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 198096 kb
Host smart-fa1af332-39d8-4e5a-a02e-31972cc0b3c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168940498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.2168940498
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.2544138460
Short name T926
Test name
Test status
Simulation time 36987928 ps
CPU time 0.63 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:51:02 PM PDT 24
Peak memory 198188 kb
Host smart-c1b3b2c0-1a83-41cb-ac1f-13e7ebe68c5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544138460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.2544138460
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.3570141226
Short name T749
Test name
Test status
Simulation time 146488685 ps
CPU time 0.73 seconds
Started Aug 19 05:50:54 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 201316 kb
Host smart-17e562b2-5076-4c4f-bdde-489351d282a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570141226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.3570141226
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.2735089975
Short name T197
Test name
Test status
Simulation time 222001752 ps
CPU time 1.11 seconds
Started Aug 19 05:51:18 PM PDT 24
Finished Aug 19 05:51:19 PM PDT 24
Peak memory 199740 kb
Host smart-25c81875-f7b4-4528-9f39-4a528b927c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735089975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_w
akeup_race.2735089975
Directory /workspace/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.2975945490
Short name T692
Test name
Test status
Simulation time 53728790 ps
CPU time 0.76 seconds
Started Aug 19 05:51:15 PM PDT 24
Finished Aug 19 05:51:16 PM PDT 24
Peak memory 199140 kb
Host smart-f0e6767c-da41-41c0-ab28-ed43ab083ff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975945490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2975945490
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.3723258941
Short name T768
Test name
Test status
Simulation time 252846075 ps
CPU time 0.82 seconds
Started Aug 19 05:50:54 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 209404 kb
Host smart-4c1bddd6-5d9b-415e-a60b-2d0a3a6862a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723258941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.3723258941
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.2839238272
Short name T860
Test name
Test status
Simulation time 372303523 ps
CPU time 0.8 seconds
Started Aug 19 05:50:46 PM PDT 24
Finished Aug 19 05:50:47 PM PDT 24
Peak memory 199856 kb
Host smart-1b62f50f-8952-44a5-a152-3ef7e04a4291
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839238272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.2839238272
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1117559959
Short name T546
Test name
Test status
Simulation time 820860735 ps
CPU time 2.9 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:56 PM PDT 24
Peak memory 201100 kb
Host smart-0f2f675f-1023-4bf3-af23-94524182850c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117559959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1117559959
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1306774714
Short name T530
Test name
Test status
Simulation time 2061719962 ps
CPU time 2.04 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 200840 kb
Host smart-cf3e58d1-aaa9-44c6-a235-49bffd4e1f6b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306774714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1306774714
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2935650239
Short name T699
Test name
Test status
Simulation time 53176097 ps
CPU time 0.89 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 199424 kb
Host smart-d4670475-73fa-4cdf-a369-2967e5596571
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935650239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2935650239
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.3256772029
Short name T735
Test name
Test status
Simulation time 28576499 ps
CPU time 0.67 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:53 PM PDT 24
Peak memory 199428 kb
Host smart-74becc23-831e-4896-9d8e-26ba08943c8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256772029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3256772029
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.2234795629
Short name T358
Test name
Test status
Simulation time 731676294 ps
CPU time 2.2 seconds
Started Aug 19 05:50:57 PM PDT 24
Finished Aug 19 05:51:05 PM PDT 24
Peak memory 201248 kb
Host smart-5de8e3f6-47ff-4038-addb-86ca38329c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234795629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.2234795629
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup.2781961099
Short name T442
Test name
Test status
Simulation time 409930877 ps
CPU time 1.01 seconds
Started Aug 19 05:50:55 PM PDT 24
Finished Aug 19 05:50:56 PM PDT 24
Peak memory 199572 kb
Host smart-b3fcf15d-c997-4e45-92ba-268a9a9ee392
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781961099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.2781961099
Directory /workspace/16.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.2637171003
Short name T201
Test name
Test status
Simulation time 418330534 ps
CPU time 1.12 seconds
Started Aug 19 05:51:07 PM PDT 24
Finished Aug 19 05:51:08 PM PDT 24
Peak memory 200180 kb
Host smart-291d69fe-fc73-41b3-be49-b9f3361723bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637171003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.2637171003
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.1784247162
Short name T107
Test name
Test status
Simulation time 37508953 ps
CPU time 0.79 seconds
Started Aug 19 05:50:52 PM PDT 24
Finished Aug 19 05:50:53 PM PDT 24
Peak memory 199108 kb
Host smart-6c7fe06e-aab1-490d-a510-28fd9bf70b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784247162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1784247162
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.1165677087
Short name T384
Test name
Test status
Simulation time 67285930 ps
CPU time 0.74 seconds
Started Aug 19 05:50:48 PM PDT 24
Finished Aug 19 05:50:49 PM PDT 24
Peak memory 197700 kb
Host smart-11812686-deca-4da7-9edf-3aafdef0e191
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165677087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.1165677087
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.1614027118
Short name T719
Test name
Test status
Simulation time 65291954 ps
CPU time 0.61 seconds
Started Aug 19 05:50:55 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 197972 kb
Host smart-2215215a-2eba-4fc8-8680-314d0f5a8e6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614027118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.1614027118
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.695787499
Short name T790
Test name
Test status
Simulation time 204892594 ps
CPU time 0.82 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 198096 kb
Host smart-67c2f17d-7971-4776-bc3b-7566d2277ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695787499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.695787499
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.2532475246
Short name T596
Test name
Test status
Simulation time 52295312 ps
CPU time 0.68 seconds
Started Aug 19 05:51:08 PM PDT 24
Finished Aug 19 05:51:09 PM PDT 24
Peak memory 198084 kb
Host smart-e7b52180-dab4-46be-af54-6b3e930ee4f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532475246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.2532475246
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.1888263370
Short name T582
Test name
Test status
Simulation time 46029020 ps
CPU time 0.73 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:36 PM PDT 24
Peak memory 198132 kb
Host smart-f61b0b29-b377-431f-a70e-49b9d4a7ac4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888263370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.1888263370
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3101672146
Short name T276
Test name
Test status
Simulation time 86775997 ps
CPU time 0.72 seconds
Started Aug 19 05:51:02 PM PDT 24
Finished Aug 19 05:51:02 PM PDT 24
Peak memory 201332 kb
Host smart-025aa552-6e77-4435-8f19-57eabe88110f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101672146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3101672146
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.3952289590
Short name T830
Test name
Test status
Simulation time 331065831 ps
CPU time 0.96 seconds
Started Aug 19 05:50:55 PM PDT 24
Finished Aug 19 05:50:56 PM PDT 24
Peak memory 199528 kb
Host smart-cf04b11f-1974-465c-9792-d5ba59c38154
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952289590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.3952289590
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.1847427543
Short name T218
Test name
Test status
Simulation time 29973938 ps
CPU time 0.69 seconds
Started Aug 19 05:50:54 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 199416 kb
Host smart-30f36988-108f-4a0e-bb9f-e5d1420f769b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847427543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.1847427543
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.3371458536
Short name T191
Test name
Test status
Simulation time 194396008 ps
CPU time 0.74 seconds
Started Aug 19 05:50:57 PM PDT 24
Finished Aug 19 05:50:58 PM PDT 24
Peak memory 209452 kb
Host smart-188f9ed4-55c5-4def-b1b3-7eb1bc313e92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371458536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.3371458536
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.1884248753
Short name T257
Test name
Test status
Simulation time 159186356 ps
CPU time 1.13 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 200192 kb
Host smart-4ceeeee4-3546-48db-99e2-6a02ca52382c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884248753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_
cm_ctrl_config_regwen.1884248753
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4011893955
Short name T605
Test name
Test status
Simulation time 1087723651 ps
CPU time 2.06 seconds
Started Aug 19 05:50:54 PM PDT 24
Finished Aug 19 05:50:56 PM PDT 24
Peak memory 201072 kb
Host smart-6099f8a9-a0ed-4840-ab40-f742274e815d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011893955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4011893955
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1072081077
Short name T563
Test name
Test status
Simulation time 873029465 ps
CPU time 3.5 seconds
Started Aug 19 05:51:18 PM PDT 24
Finished Aug 19 05:51:21 PM PDT 24
Peak memory 201152 kb
Host smart-8a896634-3970-496c-b727-4dce42155a4b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072081077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1072081077
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1853818104
Short name T375
Test name
Test status
Simulation time 72061637 ps
CPU time 0.91 seconds
Started Aug 19 05:51:05 PM PDT 24
Finished Aug 19 05:51:07 PM PDT 24
Peak memory 199196 kb
Host smart-a04f1e37-2e99-4c9a-8268-8fda39ff9a1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853818104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1853818104
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.289363168
Short name T518
Test name
Test status
Simulation time 35608285 ps
CPU time 0.69 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:53 PM PDT 24
Peak memory 199412 kb
Host smart-e60f59ef-7203-410a-bac0-49be78c83e24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289363168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.289363168
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all.555204205
Short name T737
Test name
Test status
Simulation time 1651427731 ps
CPU time 4.72 seconds
Started Aug 19 05:51:09 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 201184 kb
Host smart-6ce6ae3d-ab7b-4950-b1f2-1cae6198a53f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555204205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.555204205
Directory /workspace/17.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.4095518276
Short name T56
Test name
Test status
Simulation time 3293257521 ps
CPU time 10.84 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:51:02 PM PDT 24
Peak memory 201360 kb
Host smart-58559322-553c-46b0-923f-d0fdf4a000f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095518276 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand_reset.4095518276
Directory /workspace/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.3531495764
Short name T383
Test name
Test status
Simulation time 362499328 ps
CPU time 0.93 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 199748 kb
Host smart-a1098235-c562-431f-8cb9-ed33d398ba76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531495764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.3531495764
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.3691727210
Short name T262
Test name
Test status
Simulation time 176518581 ps
CPU time 1.1 seconds
Started Aug 19 05:51:27 PM PDT 24
Finished Aug 19 05:51:28 PM PDT 24
Peak memory 200260 kb
Host smart-67bc1745-2e77-4e72-9de1-4fde4830cf77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691727210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.3691727210
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1597789386
Short name T975
Test name
Test status
Simulation time 144413019 ps
CPU time 0.85 seconds
Started Aug 19 05:51:09 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 200332 kb
Host smart-6e332e9c-0eae-4402-9802-1e8877d05b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597789386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1597789386
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.2566652422
Short name T547
Test name
Test status
Simulation time 91009930 ps
CPU time 0.72 seconds
Started Aug 19 05:50:54 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 199236 kb
Host smart-badcbea5-2668-4ca0-9a18-28120cc80d4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566652422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.2566652422
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1544268920
Short name T287
Test name
Test status
Simulation time 33958024 ps
CPU time 0.6 seconds
Started Aug 19 05:50:55 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 197828 kb
Host smart-82639f45-07be-48aa-acc4-88f3c773a688
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544268920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.1544268920
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.4163187409
Short name T587
Test name
Test status
Simulation time 204163180 ps
CPU time 0.87 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 198052 kb
Host smart-0667a770-88bc-4670-80e7-942986f9dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163187409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.4163187409
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1546965453
Short name T223
Test name
Test status
Simulation time 32963073 ps
CPU time 0.6 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 197980 kb
Host smart-25bdf2b6-4d09-448f-8b00-747662b37545
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546965453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1546965453
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.3983176425
Short name T544
Test name
Test status
Simulation time 41375148 ps
CPU time 0.68 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 201348 kb
Host smart-72b8ec80-64d2-4312-b00a-05e42caad5c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983176425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.3983176425
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.1347997020
Short name T78
Test name
Test status
Simulation time 108570570 ps
CPU time 0.85 seconds
Started Aug 19 05:50:58 PM PDT 24
Finished Aug 19 05:50:59 PM PDT 24
Peak memory 198564 kb
Host smart-4c1d5972-7e54-42d7-86ff-e1fb09328fd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347997020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.1347997020
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.3498103685
Short name T618
Test name
Test status
Simulation time 47253611 ps
CPU time 0.79 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 199164 kb
Host smart-46853143-54c0-43e0-9f5b-190b1aaaeef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498103685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3498103685
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.1826991670
Short name T754
Test name
Test status
Simulation time 125996448 ps
CPU time 0.81 seconds
Started Aug 19 05:50:56 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 209520 kb
Host smart-14f9d819-215e-48ad-8158-91ab5ac84e3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826991670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.1826991670
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.644429328
Short name T281
Test name
Test status
Simulation time 130306251 ps
CPU time 0.76 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:51:00 PM PDT 24
Peak memory 199192 kb
Host smart-3125b7ce-9178-4cc6-ad63-a321df78dccb
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644429328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_c
m_ctrl_config_regwen.644429328
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1839008713
Short name T465
Test name
Test status
Simulation time 1265596997 ps
CPU time 2.01 seconds
Started Aug 19 05:51:10 PM PDT 24
Finished Aug 19 05:51:12 PM PDT 24
Peak memory 201084 kb
Host smart-1d77ad29-5433-4ea5-91fc-80b6abcc5793
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839008713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1839008713
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1111756276
Short name T878
Test name
Test status
Simulation time 905635360 ps
CPU time 2.34 seconds
Started Aug 19 05:51:06 PM PDT 24
Finished Aug 19 05:51:08 PM PDT 24
Peak memory 201064 kb
Host smart-0b0f8400-83fb-4322-8680-6521cd5b961a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111756276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1111756276
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1561009030
Short name T212
Test name
Test status
Simulation time 51701524 ps
CPU time 0.92 seconds
Started Aug 19 05:51:18 PM PDT 24
Finished Aug 19 05:51:19 PM PDT 24
Peak memory 199728 kb
Host smart-9ba0a839-58fa-4737-aea4-09e0814c63e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561009030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1561009030
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.3751703866
Short name T558
Test name
Test status
Simulation time 62046143 ps
CPU time 0.61 seconds
Started Aug 19 05:51:04 PM PDT 24
Finished Aug 19 05:51:05 PM PDT 24
Peak memory 198556 kb
Host smart-09b36344-1793-4d1a-8b7e-0396f0d68c2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751703866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3751703866
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all.791945521
Short name T660
Test name
Test status
Simulation time 400410681 ps
CPU time 1.79 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:05 PM PDT 24
Peak memory 200892 kb
Host smart-e4cee44a-baa7-4d81-bf64-f8aa8038e1b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791945521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.791945521
Directory /workspace/18.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all_with_rand_reset.4167006132
Short name T762
Test name
Test status
Simulation time 15537934552 ps
CPU time 11.03 seconds
Started Aug 19 05:50:52 PM PDT 24
Finished Aug 19 05:51:08 PM PDT 24
Peak memory 201368 kb
Host smart-61ece0f8-6044-459d-8d81-572114bcd5e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167006132 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all_with_rand_reset.4167006132
Directory /workspace/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.476002170
Short name T184
Test name
Test status
Simulation time 293374127 ps
CPU time 0.91 seconds
Started Aug 19 05:50:54 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 199800 kb
Host smart-7e7be493-0f30-4412-b090-1b1dd47f4241
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476002170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.476002170
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.3650393537
Short name T443
Test name
Test status
Simulation time 502847771 ps
CPU time 1.06 seconds
Started Aug 19 05:51:02 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 200960 kb
Host smart-249d2ae8-fd79-422b-aab7-d3fb2feff2f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650393537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.3650393537
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.2407663843
Short name T988
Test name
Test status
Simulation time 29692197 ps
CPU time 0.74 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 198824 kb
Host smart-899b6c46-bb66-4450-a895-8d801b5d5755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407663843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.2407663843
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.535854931
Short name T390
Test name
Test status
Simulation time 33068629 ps
CPU time 0.62 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 197984 kb
Host smart-4b0db0e4-b5d6-488d-bdcb-f64e0b34d238
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535854931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_
malfunc.535854931
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.454869881
Short name T413
Test name
Test status
Simulation time 666726195 ps
CPU time 0.79 seconds
Started Aug 19 05:50:47 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 198164 kb
Host smart-4a17c1ee-013b-4db3-ab7b-90527c544eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454869881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.454869881
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.2950403991
Short name T924
Test name
Test status
Simulation time 62200587 ps
CPU time 0.6 seconds
Started Aug 19 05:51:00 PM PDT 24
Finished Aug 19 05:51:01 PM PDT 24
Peak memory 198096 kb
Host smart-93358a81-1cb6-406d-a188-08f82c5e7bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950403991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.2950403991
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.3241852808
Short name T398
Test name
Test status
Simulation time 27697602 ps
CPU time 0.6 seconds
Started Aug 19 05:51:07 PM PDT 24
Finished Aug 19 05:51:08 PM PDT 24
Peak memory 198440 kb
Host smart-ec349ad7-06cb-4769-aa60-da52728880ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241852808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.3241852808
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1641935268
Short name T955
Test name
Test status
Simulation time 40290162 ps
CPU time 0.73 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 201284 kb
Host smart-e5c53836-191f-4aea-8762-1d6c14bb354c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641935268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1641935268
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.2268016552
Short name T603
Test name
Test status
Simulation time 337194134 ps
CPU time 0.97 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:05 PM PDT 24
Peak memory 199652 kb
Host smart-59ca792a-3ae1-4e30-8e67-a0a88e1553e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268016552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_w
akeup_race.2268016552
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.1836088863
Short name T525
Test name
Test status
Simulation time 200039462 ps
CPU time 0.89 seconds
Started Aug 19 05:51:07 PM PDT 24
Finished Aug 19 05:51:08 PM PDT 24
Peak memory 199936 kb
Host smart-7bcfde5c-4a62-401e-8df4-772e73197d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836088863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.1836088863
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.2130255919
Short name T937
Test name
Test status
Simulation time 85818017 ps
CPU time 1.01 seconds
Started Aug 19 05:51:10 PM PDT 24
Finished Aug 19 05:51:11 PM PDT 24
Peak memory 209364 kb
Host smart-eeb2df2d-42e5-420c-b31e-b48a9281f30a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130255919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.2130255919
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.478130823
Short name T901
Test name
Test status
Simulation time 64951086 ps
CPU time 0.67 seconds
Started Aug 19 05:50:54 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 198624 kb
Host smart-ff099163-5c92-4154-882f-d22e0c6659d1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478130823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_c
m_ctrl_config_regwen.478130823
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.925570130
Short name T877
Test name
Test status
Simulation time 1299579318 ps
CPU time 1.8 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 201168 kb
Host smart-1cce69ec-9692-40b1-bec6-6737b5b835e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925570130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.925570130
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3034995900
Short name T804
Test name
Test status
Simulation time 1018579510 ps
CPU time 2.36 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:56 PM PDT 24
Peak memory 200852 kb
Host smart-fd42823b-4aec-4399-bb44-c0143b0b381b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034995900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3034995900
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.756172206
Short name T99
Test name
Test status
Simulation time 115996616 ps
CPU time 0.88 seconds
Started Aug 19 05:50:49 PM PDT 24
Finished Aug 19 05:50:49 PM PDT 24
Peak memory 199096 kb
Host smart-de5ffd4e-fa46-4738-b798-f5cf664398b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756172206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_
mubi.756172206
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.848553031
Short name T517
Test name
Test status
Simulation time 54395551 ps
CPU time 0.6 seconds
Started Aug 19 05:51:09 PM PDT 24
Finished Aug 19 05:51:10 PM PDT 24
Peak memory 198576 kb
Host smart-5c727b6b-703f-40f9-8c17-dbcfd38f7ea7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848553031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.848553031
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all.464089963
Short name T631
Test name
Test status
Simulation time 1630667844 ps
CPU time 2.71 seconds
Started Aug 19 05:51:08 PM PDT 24
Finished Aug 19 05:51:11 PM PDT 24
Peak memory 201228 kb
Host smart-a93187b3-e918-4d4d-9bf9-0c131cbd05d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464089963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.464089963
Directory /workspace/19.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.702509914
Short name T292
Test name
Test status
Simulation time 3125077022 ps
CPU time 10.52 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 201156 kb
Host smart-b618748e-b2e3-413e-8a12-1e6d81a4ba56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702509914 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_reset.702509914
Directory /workspace/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.1563369234
Short name T538
Test name
Test status
Simulation time 192586900 ps
CPU time 1.22 seconds
Started Aug 19 05:50:54 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 200780 kb
Host smart-390b8749-111e-40c1-94b9-8f7f2d9d39c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563369234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.1563369234
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.2136796640
Short name T242
Test name
Test status
Simulation time 187796059 ps
CPU time 1.11 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 200248 kb
Host smart-14533d05-34c5-4573-961d-b25bbc028ce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136796640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.2136796640
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.2945471384
Short name T7
Test name
Test status
Simulation time 17355952 ps
CPU time 0.63 seconds
Started Aug 19 05:50:13 PM PDT 24
Finished Aug 19 05:50:13 PM PDT 24
Peak memory 199200 kb
Host smart-a16be6a6-b5b6-413f-9d56-6fe28de2a598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945471384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2945471384
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.1422425519
Short name T550
Test name
Test status
Simulation time 61915545 ps
CPU time 0.82 seconds
Started Aug 19 05:50:24 PM PDT 24
Finished Aug 19 05:50:25 PM PDT 24
Peak memory 199124 kb
Host smart-f5a2d26e-6d09-46c7-857e-68b145fb1359
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422425519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.1422425519
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1028006785
Short name T412
Test name
Test status
Simulation time 38044723 ps
CPU time 0.62 seconds
Started Aug 19 05:50:19 PM PDT 24
Finished Aug 19 05:50:19 PM PDT 24
Peak memory 198056 kb
Host smart-a433dcd3-7e41-4834-bd8b-b7c1bba248ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028006785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1028006785
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.1423715969
Short name T385
Test name
Test status
Simulation time 45159526 ps
CPU time 0.64 seconds
Started Aug 19 05:50:10 PM PDT 24
Finished Aug 19 05:50:11 PM PDT 24
Peak memory 198096 kb
Host smart-e8c28f9b-5395-455f-8e55-6ef19ddee40d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423715969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1423715969
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.1488420169
Short name T219
Test name
Test status
Simulation time 49524640 ps
CPU time 0.63 seconds
Started Aug 19 05:50:29 PM PDT 24
Finished Aug 19 05:50:30 PM PDT 24
Peak memory 198432 kb
Host smart-daa87843-7118-4714-b274-f0d96879ecd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488420169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1488420169
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2133105522
Short name T359
Test name
Test status
Simulation time 80717122 ps
CPU time 0.66 seconds
Started Aug 19 05:50:12 PM PDT 24
Finished Aug 19 05:50:12 PM PDT 24
Peak memory 201368 kb
Host smart-dd18df85-2d98-4182-a12c-d70b989f034e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133105522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2133105522
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.2464271339
Short name T186
Test name
Test status
Simulation time 219066117 ps
CPU time 1.13 seconds
Started Aug 19 05:50:03 PM PDT 24
Finished Aug 19 05:50:04 PM PDT 24
Peak memory 199628 kb
Host smart-84a8a4b5-086f-438c-9d1d-2feaeb4cf2a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464271339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wa
keup_race.2464271339
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.2291218328
Short name T841
Test name
Test status
Simulation time 121492913 ps
CPU time 0.87 seconds
Started Aug 19 05:50:09 PM PDT 24
Finished Aug 19 05:50:10 PM PDT 24
Peak memory 199728 kb
Host smart-ef8e459e-195b-49e2-ad04-7b0a70403d78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291218328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2291218328
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.3962949698
Short name T786
Test name
Test status
Simulation time 121958162 ps
CPU time 0.87 seconds
Started Aug 19 05:50:18 PM PDT 24
Finished Aug 19 05:50:19 PM PDT 24
Peak memory 209388 kb
Host smart-e7fbfa3e-c7ff-4d13-bb0e-031846d728ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962949698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3962949698
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.2718068168
Short name T19
Test name
Test status
Simulation time 622986925 ps
CPU time 2.17 seconds
Started Aug 19 05:50:30 PM PDT 24
Finished Aug 19 05:50:32 PM PDT 24
Peak memory 216580 kb
Host smart-da480fb2-8b5f-46ba-b010-882c6d7bb824
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718068168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.2718068168
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.1725263728
Short name T979
Test name
Test status
Simulation time 203071002 ps
CPU time 0.95 seconds
Started Aug 19 05:50:25 PM PDT 24
Finished Aug 19 05:50:26 PM PDT 24
Peak memory 199824 kb
Host smart-ed290414-8db4-48c3-b637-c278b90a47fd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725263728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c
m_ctrl_config_regwen.1725263728
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.834942870
Short name T627
Test name
Test status
Simulation time 1050201574 ps
CPU time 2.65 seconds
Started Aug 19 05:50:07 PM PDT 24
Finished Aug 19 05:50:10 PM PDT 24
Peak memory 201148 kb
Host smart-2fdd978f-7cd4-444c-8c63-c6be9023183e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834942870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.834942870
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3356617878
Short name T531
Test name
Test status
Simulation time 3134985819 ps
CPU time 2.11 seconds
Started Aug 19 05:50:38 PM PDT 24
Finished Aug 19 05:50:41 PM PDT 24
Peak memory 201248 kb
Host smart-16d50847-d995-41ab-a307-00a1b969ca1e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356617878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3356617878
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.139392487
Short name T256
Test name
Test status
Simulation time 520207088 ps
CPU time 0.83 seconds
Started Aug 19 05:50:10 PM PDT 24
Finished Aug 19 05:50:11 PM PDT 24
Peak memory 199216 kb
Host smart-7ee6dbe5-3fde-4994-ac87-c6ac912532ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139392487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.139392487
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.2159311035
Short name T504
Test name
Test status
Simulation time 26273564 ps
CPU time 0.65 seconds
Started Aug 19 05:50:08 PM PDT 24
Finished Aug 19 05:50:09 PM PDT 24
Peak memory 198636 kb
Host smart-15d2d176-8711-4ccb-b8ab-67ca822474d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159311035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.2159311035
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.2541110906
Short name T966
Test name
Test status
Simulation time 2274703641 ps
CPU time 7.64 seconds
Started Aug 19 05:50:16 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 201252 kb
Host smart-e10f0dbf-ac4a-4b19-82ff-e06b06a0f636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541110906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.2541110906
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2181678353
Short name T92
Test name
Test status
Simulation time 4458716049 ps
CPU time 6.35 seconds
Started Aug 19 05:50:19 PM PDT 24
Finished Aug 19 05:50:26 PM PDT 24
Peak memory 201328 kb
Host smart-785d9ce7-5622-45f7-b69b-66b9ba3aca1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181678353 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_reset.2181678353
Directory /workspace/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.1415081137
Short name T565
Test name
Test status
Simulation time 66136165 ps
CPU time 0.78 seconds
Started Aug 19 05:50:03 PM PDT 24
Finished Aug 19 05:50:04 PM PDT 24
Peak memory 198260 kb
Host smart-77bcb93e-c4c1-4e04-ad5a-4fdd1ca94b0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415081137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.1415081137
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.1397119238
Short name T639
Test name
Test status
Simulation time 55751023 ps
CPU time 0.71 seconds
Started Aug 19 05:50:18 PM PDT 24
Finished Aug 19 05:50:19 PM PDT 24
Peak memory 199184 kb
Host smart-b1248213-77ae-4f8d-b611-c2a22edeea22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397119238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1397119238
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.1577622837
Short name T318
Test name
Test status
Simulation time 58040118 ps
CPU time 0.81 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 200216 kb
Host smart-4a55d97c-2e08-472a-a144-196b0ca6b4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577622837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1577622837
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.33786940
Short name T25
Test name
Test status
Simulation time 83420725 ps
CPU time 0.69 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 198432 kb
Host smart-134aa3f1-c9b2-4265-a6f7-afa0fce4e054
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33786940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disab
le_rom_integrity_check.33786940
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.1908525558
Short name T624
Test name
Test status
Simulation time 37670037 ps
CPU time 0.59 seconds
Started Aug 19 05:51:08 PM PDT 24
Finished Aug 19 05:51:09 PM PDT 24
Peak memory 197240 kb
Host smart-d8bc0454-41ad-4efc-a92b-1290158e4a76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908525558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.1908525558
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.4271671363
Short name T957
Test name
Test status
Simulation time 110557621 ps
CPU time 0.84 seconds
Started Aug 19 05:51:09 PM PDT 24
Finished Aug 19 05:51:10 PM PDT 24
Peak memory 199404 kb
Host smart-c579348f-888a-412f-b496-43d17813a505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271671363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.4271671363
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2854371032
Short name T560
Test name
Test status
Simulation time 42457974 ps
CPU time 0.61 seconds
Started Aug 19 05:51:21 PM PDT 24
Finished Aug 19 05:51:22 PM PDT 24
Peak memory 198092 kb
Host smart-89b34704-e414-4773-9d2f-4e5124df8a2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854371032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2854371032
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.2275876331
Short name T788
Test name
Test status
Simulation time 73230918 ps
CPU time 0.62 seconds
Started Aug 19 05:51:09 PM PDT 24
Finished Aug 19 05:51:09 PM PDT 24
Peak memory 198120 kb
Host smart-13e1fba1-d45b-45d1-963e-a0272f5130bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275876331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2275876331
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.1109543112
Short name T431
Test name
Test status
Simulation time 45633563 ps
CPU time 0.69 seconds
Started Aug 19 05:51:08 PM PDT 24
Finished Aug 19 05:51:09 PM PDT 24
Peak memory 201284 kb
Host smart-5923bd94-8d01-43e9-8b13-fb74fb563a2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109543112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.1109543112
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.2125142691
Short name T446
Test name
Test status
Simulation time 217034199 ps
CPU time 0.87 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 199612 kb
Host smart-23adc249-c121-4469-8801-e2d1bc09eab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125142691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_w
akeup_race.2125142691
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.427118412
Short name T175
Test name
Test status
Simulation time 42193475 ps
CPU time 0.64 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 199124 kb
Host smart-5d704a4e-0702-4868-8f3a-de1add482316
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427118412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.427118412
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3675356445
Short name T513
Test name
Test status
Simulation time 100661889 ps
CPU time 0.93 seconds
Started Aug 19 05:51:15 PM PDT 24
Finished Aug 19 05:51:16 PM PDT 24
Peak memory 209476 kb
Host smart-bf586496-7e19-4c50-92fb-b79b93f296e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675356445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3675356445
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.1645304876
Short name T882
Test name
Test status
Simulation time 279884177 ps
CPU time 0.92 seconds
Started Aug 19 05:51:22 PM PDT 24
Finished Aug 19 05:51:23 PM PDT 24
Peak memory 199936 kb
Host smart-4084c82a-0681-4928-8de2-fec7e2dfe08b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645304876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.1645304876
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2500142821
Short name T271
Test name
Test status
Simulation time 793019303 ps
CPU time 3.4 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:16 PM PDT 24
Peak memory 201120 kb
Host smart-ccbd0e34-d559-435e-ba46-93af64f8ffb3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500142821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2500142821
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3334610007
Short name T532
Test name
Test status
Simulation time 1267948698 ps
CPU time 2.17 seconds
Started Aug 19 05:51:22 PM PDT 24
Finished Aug 19 05:51:24 PM PDT 24
Peak memory 201136 kb
Host smart-442e6ea0-d7bd-4567-8393-533165e83dd4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334610007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3334610007
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.3495935834
Short name T785
Test name
Test status
Simulation time 67069004 ps
CPU time 0.93 seconds
Started Aug 19 05:51:11 PM PDT 24
Finished Aug 19 05:51:13 PM PDT 24
Peak memory 199424 kb
Host smart-53ac87d7-d9f7-4925-b67c-5286252a9cdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495935834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3495935834
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.4578695
Short name T958
Test name
Test status
Simulation time 33520898 ps
CPU time 0.72 seconds
Started Aug 19 05:51:15 PM PDT 24
Finished Aug 19 05:51:16 PM PDT 24
Peak memory 198596 kb
Host smart-caf4654d-2b4c-47ba-9e0f-79989f0115ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4578695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.4578695
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.988225849
Short name T204
Test name
Test status
Simulation time 646537020 ps
CPU time 1.8 seconds
Started Aug 19 05:51:21 PM PDT 24
Finished Aug 19 05:51:23 PM PDT 24
Peak memory 201148 kb
Host smart-e2a5d545-402e-45cc-b22b-e6236d2fae63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988225849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.988225849
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all_with_rand_reset.3701964750
Short name T100
Test name
Test status
Simulation time 2166118248 ps
CPU time 7.89 seconds
Started Aug 19 05:51:17 PM PDT 24
Finished Aug 19 05:51:25 PM PDT 24
Peak memory 201328 kb
Host smart-a3c450c8-2489-4f65-a25f-b42b276167af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701964750 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all_with_rand_reset.3701964750
Directory /workspace/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.3596017984
Short name T480
Test name
Test status
Simulation time 288122498 ps
CPU time 1.26 seconds
Started Aug 19 05:51:11 PM PDT 24
Finished Aug 19 05:51:12 PM PDT 24
Peak memory 199756 kb
Host smart-124d105f-1f79-4d3d-b3a0-4ff3a25225f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596017984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.3596017984
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.845881654
Short name T595
Test name
Test status
Simulation time 425353747 ps
CPU time 1.17 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 200944 kb
Host smart-437d6f76-2d80-4753-b111-707d5c215039
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845881654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.845881654
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.1439812552
Short name T995
Test name
Test status
Simulation time 30921612 ps
CPU time 0.78 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 198804 kb
Host smart-5bb3672a-c4c2-42bb-b34b-d4caa2ff25cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439812552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1439812552
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.4007315260
Short name T779
Test name
Test status
Simulation time 62050278 ps
CPU time 0.87 seconds
Started Aug 19 05:51:27 PM PDT 24
Finished Aug 19 05:51:28 PM PDT 24
Peak memory 198332 kb
Host smart-936c3c84-e475-4b4d-ac0f-7c1ee090bef4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007315260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.4007315260
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.3751053267
Short name T142
Test name
Test status
Simulation time 32094011 ps
CPU time 0.63 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 197956 kb
Host smart-f3d85711-f98b-4e38-b3c0-f12101b49b1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751053267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.3751053267
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.3692304444
Short name T258
Test name
Test status
Simulation time 398336434 ps
CPU time 0.88 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 198428 kb
Host smart-0d1c7d2b-6f8a-4fe5-a4f2-87f70f39028d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692304444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.3692304444
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.1149529272
Short name T474
Test name
Test status
Simulation time 43632205 ps
CPU time 0.69 seconds
Started Aug 19 05:51:22 PM PDT 24
Finished Aug 19 05:51:22 PM PDT 24
Peak memory 198032 kb
Host smart-45d8fd56-4cec-48c2-8d6b-76fc3164281c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149529272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.1149529272
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.997154166
Short name T602
Test name
Test status
Simulation time 59708431 ps
CPU time 0.62 seconds
Started Aug 19 05:51:08 PM PDT 24
Finished Aug 19 05:51:09 PM PDT 24
Peak memory 198124 kb
Host smart-31b3806c-1dc7-4188-bbe2-b0de489c0daa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997154166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.997154166
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.281780256
Short name T887
Test name
Test status
Simulation time 40880992 ps
CPU time 0.69 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:35 PM PDT 24
Peak memory 201280 kb
Host smart-f93f3ebe-1de3-44df-91ae-a179224b6a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281780256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invali
d.281780256
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.4211859781
Short name T368
Test name
Test status
Simulation time 112803191 ps
CPU time 0.89 seconds
Started Aug 19 05:51:10 PM PDT 24
Finished Aug 19 05:51:11 PM PDT 24
Peak memory 198436 kb
Host smart-2d4e46ea-1218-43a4-9a85-9e443c1260d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211859781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_w
akeup_race.4211859781
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.144668058
Short name T536
Test name
Test status
Simulation time 71682869 ps
CPU time 0.71 seconds
Started Aug 19 05:51:08 PM PDT 24
Finished Aug 19 05:51:09 PM PDT 24
Peak memory 199160 kb
Host smart-d7aa7300-c4e8-4aa4-ae7c-51859b1c3a25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144668058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.144668058
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.2488409351
Short name T697
Test name
Test status
Simulation time 118716984 ps
CPU time 0.8 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:33 PM PDT 24
Peak memory 209428 kb
Host smart-da7783ea-9aeb-4d37-a4bc-5cba6be16e88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488409351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.2488409351
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.2250487947
Short name T535
Test name
Test status
Simulation time 150491155 ps
CPU time 0.74 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:51:00 PM PDT 24
Peak memory 198700 kb
Host smart-537bea91-ef93-4ae7-9471-914de56bfd99
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250487947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.2250487947
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3422012566
Short name T608
Test name
Test status
Simulation time 836154325 ps
CPU time 3.41 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:18 PM PDT 24
Peak memory 201084 kb
Host smart-28de2c8a-070e-433e-9bad-9a296852a148
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422012566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3422012566
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1546185046
Short name T680
Test name
Test status
Simulation time 1618884766 ps
CPU time 2.18 seconds
Started Aug 19 05:51:19 PM PDT 24
Finished Aug 19 05:51:21 PM PDT 24
Peak memory 201068 kb
Host smart-0c2ec639-3dd6-4b09-8389-87a83c0d4449
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546185046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1546185046
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3322788381
Short name T2
Test name
Test status
Simulation time 173700122 ps
CPU time 0.84 seconds
Started Aug 19 05:51:16 PM PDT 24
Finished Aug 19 05:51:17 PM PDT 24
Peak memory 199348 kb
Host smart-e2be2a38-9796-4030-aa86-858f52916783
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322788381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3322788381
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.3605651804
Short name T203
Test name
Test status
Simulation time 41301425 ps
CPU time 0.67 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 198664 kb
Host smart-4446c81e-d664-4839-a986-cae6b403a098
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605651804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3605651804
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all.1826713754
Short name T675
Test name
Test status
Simulation time 1517583321 ps
CPU time 3.34 seconds
Started Aug 19 05:51:21 PM PDT 24
Finished Aug 19 05:51:24 PM PDT 24
Peak memory 201152 kb
Host smart-2e2a97c4-00eb-4d57-a8ff-66ec0682f01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826713754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.1826713754
Directory /workspace/21.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.2998896603
Short name T23
Test name
Test status
Simulation time 3245854012 ps
CPU time 8.65 seconds
Started Aug 19 05:51:27 PM PDT 24
Finished Aug 19 05:51:36 PM PDT 24
Peak memory 200528 kb
Host smart-61856b13-a118-4932-97f5-a76e94c2f977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998896603 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.2998896603
Directory /workspace/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.3572027342
Short name T10
Test name
Test status
Simulation time 102792364 ps
CPU time 0.71 seconds
Started Aug 19 05:51:10 PM PDT 24
Finished Aug 19 05:51:11 PM PDT 24
Peak memory 198328 kb
Host smart-1d14bb28-813c-4881-8d4d-160f12fa2876
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572027342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.3572027342
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.3650771104
Short name T290
Test name
Test status
Simulation time 375151421 ps
CPU time 0.91 seconds
Started Aug 19 05:51:03 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 200256 kb
Host smart-196b7003-4438-427c-8838-4eb831a9ef39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650771104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.3650771104
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.505410330
Short name T448
Test name
Test status
Simulation time 33885083 ps
CPU time 1.07 seconds
Started Aug 19 05:51:19 PM PDT 24
Finished Aug 19 05:51:20 PM PDT 24
Peak memory 201012 kb
Host smart-aeaecbb6-cf93-4dd7-9166-3b069a4acd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505410330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.505410330
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.3205863037
Short name T143
Test name
Test status
Simulation time 92118282 ps
CPU time 0.71 seconds
Started Aug 19 05:51:27 PM PDT 24
Finished Aug 19 05:51:27 PM PDT 24
Peak memory 198592 kb
Host smart-521806d1-b224-4b39-9e7e-f028ac93162d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205863037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.3205863037
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3301407672
Short name T5
Test name
Test status
Simulation time 31342569 ps
CPU time 0.63 seconds
Started Aug 19 05:51:26 PM PDT 24
Finished Aug 19 05:51:27 PM PDT 24
Peak memory 197960 kb
Host smart-79c1e826-3cd8-454b-bbe0-68c4d92eaaed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301407672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.3301407672
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2279020798
Short name T671
Test name
Test status
Simulation time 110227286 ps
CPU time 0.83 seconds
Started Aug 19 05:51:22 PM PDT 24
Finished Aug 19 05:51:23 PM PDT 24
Peak memory 198388 kb
Host smart-a9eb6c11-f0e1-4983-a44b-81bab57c928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279020798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2279020798
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.1270985013
Short name T571
Test name
Test status
Simulation time 65173007 ps
CPU time 0.61 seconds
Started Aug 19 05:51:15 PM PDT 24
Finished Aug 19 05:51:16 PM PDT 24
Peak memory 197368 kb
Host smart-128b6c45-b371-4df7-aabc-f4349bea678b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270985013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.1270985013
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.3710003653
Short name T234
Test name
Test status
Simulation time 33251000 ps
CPU time 0.6 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:13 PM PDT 24
Peak memory 198440 kb
Host smart-7e1f16da-dfec-440f-96be-1e4d02e1ff97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710003653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3710003653
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.2182207935
Short name T610
Test name
Test status
Simulation time 42978767 ps
CPU time 0.72 seconds
Started Aug 19 05:51:11 PM PDT 24
Finished Aug 19 05:51:12 PM PDT 24
Peak memory 201300 kb
Host smart-dcee9fca-8b36-427d-ac47-770a66ddbaf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182207935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.2182207935
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.4085140018
Short name T247
Test name
Test status
Simulation time 309484413 ps
CPU time 0.92 seconds
Started Aug 19 05:51:17 PM PDT 24
Finished Aug 19 05:51:23 PM PDT 24
Peak memory 199812 kb
Host smart-afaa981d-15e4-4c4d-a4f6-37549b8f2fea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085140018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_w
akeup_race.4085140018
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.3128947589
Short name T543
Test name
Test status
Simulation time 113190106 ps
CPU time 0.76 seconds
Started Aug 19 05:51:01 PM PDT 24
Finished Aug 19 05:51:02 PM PDT 24
Peak memory 199144 kb
Host smart-8e987fff-d552-419e-bdd4-8edef17fed2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128947589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.3128947589
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.2960014816
Short name T508
Test name
Test status
Simulation time 120164208 ps
CPU time 0.86 seconds
Started Aug 19 05:51:29 PM PDT 24
Finished Aug 19 05:51:30 PM PDT 24
Peak memory 208424 kb
Host smart-aefc2386-3d6e-486b-8367-4052ef570ff0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960014816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.2960014816
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.1221665501
Short name T818
Test name
Test status
Simulation time 70075527 ps
CPU time 0.65 seconds
Started Aug 19 05:51:23 PM PDT 24
Finished Aug 19 05:51:24 PM PDT 24
Peak memory 198584 kb
Host smart-a7f37010-524b-4e8f-a479-b2e11b28e152
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221665501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.1221665501
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2784530293
Short name T764
Test name
Test status
Simulation time 933933464 ps
CPU time 3.27 seconds
Started Aug 19 05:51:00 PM PDT 24
Finished Aug 19 05:51:03 PM PDT 24
Peak memory 201124 kb
Host smart-1e94452c-3107-4dc2-a446-368dcdb07d9b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784530293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2784530293
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.217228186
Short name T225
Test name
Test status
Simulation time 796910959 ps
CPU time 2.89 seconds
Started Aug 19 05:51:04 PM PDT 24
Finished Aug 19 05:51:07 PM PDT 24
Peak memory 201120 kb
Host smart-a04eabb2-eed6-4bd7-bd58-9ada2d61c9dd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217228186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.217228186
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.161030459
Short name T629
Test name
Test status
Simulation time 193539719 ps
CPU time 0.89 seconds
Started Aug 19 05:50:59 PM PDT 24
Finished Aug 19 05:51:01 PM PDT 24
Peak memory 199376 kb
Host smart-e16d71ec-634e-4bdc-aba6-32f239bf1dbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161030459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_
mubi.161030459
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.2761277663
Short name T497
Test name
Test status
Simulation time 52515475 ps
CPU time 0.64 seconds
Started Aug 19 05:51:06 PM PDT 24
Finished Aug 19 05:51:12 PM PDT 24
Peak memory 198548 kb
Host smart-94fabc76-4138-47e8-8c7d-ee2193fd210e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761277663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.2761277663
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.657739915
Short name T794
Test name
Test status
Simulation time 1655486025 ps
CPU time 6.08 seconds
Started Aug 19 05:51:09 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 201232 kb
Host smart-e1c0610b-8de8-4145-a226-da98609188a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657739915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.657739915
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.1150682510
Short name T132
Test name
Test status
Simulation time 2167055470 ps
CPU time 3.35 seconds
Started Aug 19 05:51:23 PM PDT 24
Finished Aug 19 05:51:26 PM PDT 24
Peak memory 201324 kb
Host smart-41b1ca92-c30e-4fe1-9078-9e8d9072ab2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150682510 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand_reset.1150682510
Directory /workspace/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup.3589362644
Short name T475
Test name
Test status
Simulation time 254959013 ps
CPU time 1.25 seconds
Started Aug 19 05:51:01 PM PDT 24
Finished Aug 19 05:51:03 PM PDT 24
Peak memory 199564 kb
Host smart-1d46b9d8-3c0d-446f-b1be-c66ffc43c193
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589362644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.3589362644
Directory /workspace/22.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.271412013
Short name T579
Test name
Test status
Simulation time 47334076 ps
CPU time 0.67 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 199312 kb
Host smart-c1276b62-db27-42d5-a16a-f27d42d67c2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271412013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.271412013
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.629790619
Short name T982
Test name
Test status
Simulation time 150531502 ps
CPU time 0.74 seconds
Started Aug 19 05:51:17 PM PDT 24
Finished Aug 19 05:51:18 PM PDT 24
Peak memory 198772 kb
Host smart-2bab4970-788c-454c-a13c-f8e2bff6050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629790619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.629790619
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2435423781
Short name T1
Test name
Test status
Simulation time 61451458 ps
CPU time 0.72 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 199240 kb
Host smart-df7a67c5-f8d9-43a7-82e9-4d43ef5d7521
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435423781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2435423781
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.2100144074
Short name T344
Test name
Test status
Simulation time 40304925 ps
CPU time 0.6 seconds
Started Aug 19 05:51:12 PM PDT 24
Finished Aug 19 05:51:12 PM PDT 24
Peak memory 197272 kb
Host smart-8ae72317-09bb-4b0c-84b7-8057451c2253
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100144074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.2100144074
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.2049739307
Short name T254
Test name
Test status
Simulation time 203797543 ps
CPU time 0.86 seconds
Started Aug 19 05:51:19 PM PDT 24
Finished Aug 19 05:51:20 PM PDT 24
Peak memory 198124 kb
Host smart-8c4c819f-274a-497f-ba89-fac82b02e48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049739307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.2049739307
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.4268200977
Short name T97
Test name
Test status
Simulation time 68729148 ps
CPU time 0.64 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 197392 kb
Host smart-a6a1b122-c23c-4b00-906e-b457d9d756ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268200977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.4268200977
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.845629205
Short name T751
Test name
Test status
Simulation time 31134728 ps
CPU time 0.62 seconds
Started Aug 19 05:51:21 PM PDT 24
Finished Aug 19 05:51:22 PM PDT 24
Peak memory 198108 kb
Host smart-43d6de58-525d-4766-b363-1704b9620076
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845629205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.845629205
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.2893480040
Short name T43
Test name
Test status
Simulation time 39755238 ps
CPU time 0.68 seconds
Started Aug 19 05:51:29 PM PDT 24
Finished Aug 19 05:51:30 PM PDT 24
Peak memory 201360 kb
Host smart-ca2de9d5-9c91-43e9-a6f9-567e7d936338
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893480040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.2893480040
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.2976260502
Short name T269
Test name
Test status
Simulation time 302122584 ps
CPU time 1.4 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:16 PM PDT 24
Peak memory 199644 kb
Host smart-626487f3-e384-4b4a-bd88-152032d7ddb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976260502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w
akeup_race.2976260502
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.1117749468
Short name T479
Test name
Test status
Simulation time 63227964 ps
CPU time 0.84 seconds
Started Aug 19 05:51:21 PM PDT 24
Finished Aug 19 05:51:22 PM PDT 24
Peak memory 199164 kb
Host smart-bddb8727-7e14-4a13-b6e4-ec82b2553c53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117749468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.1117749468
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3427431969
Short name T187
Test name
Test status
Simulation time 102518532 ps
CPU time 1.05 seconds
Started Aug 19 05:51:18 PM PDT 24
Finished Aug 19 05:51:19 PM PDT 24
Peak memory 209460 kb
Host smart-1d0a11f7-4e1e-47c7-a84e-6f139173d854
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427431969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3427431969
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.3932336783
Short name T673
Test name
Test status
Simulation time 199600005 ps
CPU time 1.08 seconds
Started Aug 19 05:51:12 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 199856 kb
Host smart-4de75d65-cb8c-4667-8bc0-a57ca6790402
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932336783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_
cm_ctrl_config_regwen.3932336783
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2267901560
Short name T337
Test name
Test status
Simulation time 832388987 ps
CPU time 3.04 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 201108 kb
Host smart-2d5c0083-2dce-4a6a-bc5d-454e8bc05a26
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267901560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2267901560
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2612385016
Short name T144
Test name
Test status
Simulation time 1203325624 ps
CPU time 2.05 seconds
Started Aug 19 05:51:08 PM PDT 24
Finished Aug 19 05:51:10 PM PDT 24
Peak memory 201124 kb
Host smart-c38c7dd2-7ba6-4adb-9d17-d7225dcb8927
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612385016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2612385016
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.514562933
Short name T217
Test name
Test status
Simulation time 113932100 ps
CPU time 0.93 seconds
Started Aug 19 05:51:17 PM PDT 24
Finished Aug 19 05:51:18 PM PDT 24
Peak memory 199348 kb
Host smart-a8b8d908-870a-4c44-9321-52ee4f609726
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514562933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_
mubi.514562933
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.2766080375
Short name T447
Test name
Test status
Simulation time 58965852 ps
CPU time 0.64 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:35 PM PDT 24
Peak memory 198532 kb
Host smart-9d65013a-6de1-4ec0-981a-8aea54823d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766080375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.2766080375
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.3417648106
Short name T111
Test name
Test status
Simulation time 4801941716 ps
CPU time 4.39 seconds
Started Aug 19 05:51:29 PM PDT 24
Finished Aug 19 05:51:34 PM PDT 24
Peak memory 201260 kb
Host smart-a5013034-178a-4a16-8b48-560a99902a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417648106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.3417648106
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.1396340108
Short name T742
Test name
Test status
Simulation time 4364807817 ps
CPU time 12.14 seconds
Started Aug 19 05:51:16 PM PDT 24
Finished Aug 19 05:51:34 PM PDT 24
Peak memory 201368 kb
Host smart-2e7708f1-2c50-48ae-9e0a-779fbe9f314c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396340108 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_reset.1396340108
Directory /workspace/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.1970414807
Short name T296
Test name
Test status
Simulation time 321525566 ps
CPU time 0.87 seconds
Started Aug 19 05:51:21 PM PDT 24
Finished Aug 19 05:51:22 PM PDT 24
Peak memory 199580 kb
Host smart-ca0d7e42-8a24-42c6-acda-36e5fdf8da80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970414807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.1970414807
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.1155319232
Short name T425
Test name
Test status
Simulation time 55062704 ps
CPU time 0.69 seconds
Started Aug 19 05:51:21 PM PDT 24
Finished Aug 19 05:51:21 PM PDT 24
Peak memory 199016 kb
Host smart-20a84a13-da91-41b8-bc2b-e6796c66d523
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155319232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.1155319232
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.3550621046
Short name T306
Test name
Test status
Simulation time 100221432 ps
CPU time 0.85 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 200076 kb
Host smart-da717ea0-cda4-4a4e-9222-59b33e2e2f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550621046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.3550621046
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.3887396329
Short name T501
Test name
Test status
Simulation time 72988403 ps
CPU time 0.7 seconds
Started Aug 19 05:51:36 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 199144 kb
Host smart-93020635-5cd7-45c2-b4cb-c2cfcaaeb1e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887396329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.3887396329
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3031537124
Short name T837
Test name
Test status
Simulation time 57142359 ps
CPU time 0.58 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 197344 kb
Host smart-b1fd79de-50c9-473c-9b30-f347beeee3ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031537124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3031537124
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.2764433794
Short name T821
Test name
Test status
Simulation time 111625502 ps
CPU time 0.88 seconds
Started Aug 19 05:51:22 PM PDT 24
Finished Aug 19 05:51:23 PM PDT 24
Peak memory 199164 kb
Host smart-8d436070-473e-4aa0-a15a-fef22e48eb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764433794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.2764433794
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.2209616074
Short name T632
Test name
Test status
Simulation time 37223236 ps
CPU time 0.64 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:36 PM PDT 24
Peak memory 197392 kb
Host smart-6573b81e-682e-4fe5-bf46-f393cd9230a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209616074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.2209616074
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.3611624094
Short name T468
Test name
Test status
Simulation time 38518489 ps
CPU time 0.6 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 198056 kb
Host smart-40a2de11-98e7-4021-9228-4f73b5d40333
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611624094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.3611624094
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.3785776113
Short name T373
Test name
Test status
Simulation time 73965525 ps
CPU time 0.69 seconds
Started Aug 19 05:51:16 PM PDT 24
Finished Aug 19 05:51:17 PM PDT 24
Peak memory 201320 kb
Host smart-444648d4-6657-42eb-8c00-b2575ef210d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785776113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.3785776113
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.2934435109
Short name T736
Test name
Test status
Simulation time 217322824 ps
CPU time 1.06 seconds
Started Aug 19 05:51:33 PM PDT 24
Finished Aug 19 05:51:35 PM PDT 24
Peak memory 199732 kb
Host smart-5c41a75a-2009-4eb2-a256-7dfbb2c6e580
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934435109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_w
akeup_race.2934435109
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.1540940983
Short name T209
Test name
Test status
Simulation time 117092049 ps
CPU time 0.84 seconds
Started Aug 19 05:51:19 PM PDT 24
Finished Aug 19 05:51:20 PM PDT 24
Peak memory 199716 kb
Host smart-fda1ac10-d411-4481-8356-a48b6e82582f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540940983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1540940983
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.3967746582
Short name T723
Test name
Test status
Simulation time 115198640 ps
CPU time 0.96 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:35 PM PDT 24
Peak memory 201244 kb
Host smart-481c47a4-c34a-4039-9cdb-96c75f872f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967746582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.3967746582
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.2084537387
Short name T693
Test name
Test status
Simulation time 88409887 ps
CPU time 0.94 seconds
Started Aug 19 05:51:20 PM PDT 24
Finished Aug 19 05:51:21 PM PDT 24
Peak memory 200176 kb
Host smart-9856fa1f-a0b5-4262-861a-bafc5b9cd4ed
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084537387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_
cm_ctrl_config_regwen.2084537387
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3949225018
Short name T780
Test name
Test status
Simulation time 1034068525 ps
CPU time 1.9 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:34 PM PDT 24
Peak memory 201120 kb
Host smart-22e1ce42-173d-48c6-a9c9-78afdaf8f2ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949225018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3949225018
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3763367501
Short name T484
Test name
Test status
Simulation time 1008181366 ps
CPU time 2.18 seconds
Started Aug 19 05:51:33 PM PDT 24
Finished Aug 19 05:51:36 PM PDT 24
Peak memory 201160 kb
Host smart-f26db9df-73f9-45ff-a49d-54cb2ead054a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763367501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3763367501
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.82975364
Short name T370
Test name
Test status
Simulation time 51674927 ps
CPU time 0.88 seconds
Started Aug 19 05:51:18 PM PDT 24
Finished Aug 19 05:51:19 PM PDT 24
Peak memory 199356 kb
Host smart-fb5d5241-8043-44a2-b209-4823842bb9db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82975364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.82975364
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.1126904391
Short name T922
Test name
Test status
Simulation time 127020849 ps
CPU time 0.62 seconds
Started Aug 19 05:51:27 PM PDT 24
Finished Aug 19 05:51:28 PM PDT 24
Peak memory 198544 kb
Host smart-74c64f4a-62c0-420c-813b-2b47771a98f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126904391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.1126904391
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all.2371404662
Short name T718
Test name
Test status
Simulation time 2189345771 ps
CPU time 5.11 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:40 PM PDT 24
Peak memory 201244 kb
Host smart-8b8f4edc-d735-4d81-b5d9-65283ead1e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371404662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.2371404662
Directory /workspace/24.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.2262488089
Short name T220
Test name
Test status
Simulation time 271903455 ps
CPU time 0.88 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:32 PM PDT 24
Peak memory 199516 kb
Host smart-6c588da5-1e70-4355-b6dd-404b46d4d4b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262488089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.2262488089
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.4037891098
Short name T649
Test name
Test status
Simulation time 75463080 ps
CPU time 0.66 seconds
Started Aug 19 05:51:25 PM PDT 24
Finished Aug 19 05:51:26 PM PDT 24
Peak memory 198300 kb
Host smart-c7785c6f-bc3e-4966-b5fb-7d6220247b75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037891098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.4037891098
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3786350267
Short name T362
Test name
Test status
Simulation time 26745615 ps
CPU time 0.69 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 198680 kb
Host smart-4b68c3a2-bfae-4c78-8d21-6d15b802474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786350267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3786350267
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.3853883012
Short name T752
Test name
Test status
Simulation time 73675424 ps
CPU time 0.7 seconds
Started Aug 19 05:51:24 PM PDT 24
Finished Aug 19 05:51:25 PM PDT 24
Peak memory 198636 kb
Host smart-2f5d8b1c-a046-4f3b-9e75-0a5e482c1241
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853883012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.3853883012
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.53953752
Short name T278
Test name
Test status
Simulation time 31212985 ps
CPU time 0.59 seconds
Started Aug 19 05:51:13 PM PDT 24
Finished Aug 19 05:51:14 PM PDT 24
Peak memory 197280 kb
Host smart-89deec79-7ba9-488c-96ab-e690a5c6eb48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53953752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_m
alfunc.53953752
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.460737530
Short name T335
Test name
Test status
Simulation time 111999905 ps
CPU time 0.84 seconds
Started Aug 19 05:51:28 PM PDT 24
Finished Aug 19 05:51:29 PM PDT 24
Peak memory 198180 kb
Host smart-f8643fb4-f5f9-4191-b711-b1c7d3a2bea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460737530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.460737530
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.2548598203
Short name T936
Test name
Test status
Simulation time 51291672 ps
CPU time 0.69 seconds
Started Aug 19 05:51:15 PM PDT 24
Finished Aug 19 05:51:15 PM PDT 24
Peak memory 197444 kb
Host smart-3b856b90-7de6-4782-b6f6-6e8c7047fe46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548598203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2548598203
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.1920663895
Short name T172
Test name
Test status
Simulation time 49477184 ps
CPU time 0.66 seconds
Started Aug 19 05:51:17 PM PDT 24
Finished Aug 19 05:51:18 PM PDT 24
Peak memory 198108 kb
Host smart-307815e3-cb41-4e7b-8cef-65f22c7d7d00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920663895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.1920663895
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.2994392076
Short name T394
Test name
Test status
Simulation time 71048767 ps
CPU time 0.73 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:38 PM PDT 24
Peak memory 201292 kb
Host smart-c6fd613b-cd23-47e4-96a9-140319b3d2fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994392076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.2994392076
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.2179045346
Short name T586
Test name
Test status
Simulation time 429752585 ps
CPU time 0.96 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:33 PM PDT 24
Peak memory 199868 kb
Host smart-588a0b58-cfd2-49a0-aea2-ac334c02c10d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179045346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_w
akeup_race.2179045346
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.1435551561
Short name T333
Test name
Test status
Simulation time 38567185 ps
CPU time 0.74 seconds
Started Aug 19 05:51:23 PM PDT 24
Finished Aug 19 05:51:24 PM PDT 24
Peak memory 199200 kb
Host smart-a7b2411c-ad50-4903-9763-dde339e1a283
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435551561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1435551561
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.1826569875
Short name T237
Test name
Test status
Simulation time 156726835 ps
CPU time 0.79 seconds
Started Aug 19 05:51:19 PM PDT 24
Finished Aug 19 05:51:20 PM PDT 24
Peak memory 209404 kb
Host smart-ff39f6ce-2fba-4426-8e25-9b880e8ccf32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826569875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1826569875
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.1706154227
Short name T809
Test name
Test status
Simulation time 256071798 ps
CPU time 1.34 seconds
Started Aug 19 05:51:22 PM PDT 24
Finished Aug 19 05:51:23 PM PDT 24
Peak memory 200808 kb
Host smart-4e7d7e12-05ef-4d5a-a5f0-41f9276e6158
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706154227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_
cm_ctrl_config_regwen.1706154227
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1255537738
Short name T581
Test name
Test status
Simulation time 797994401 ps
CPU time 2.21 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:16 PM PDT 24
Peak memory 201140 kb
Host smart-2b1611da-a497-49d3-b53e-535da79fb75f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255537738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1255537738
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1381928301
Short name T295
Test name
Test status
Simulation time 1249848685 ps
CPU time 1.91 seconds
Started Aug 19 05:51:14 PM PDT 24
Finished Aug 19 05:51:16 PM PDT 24
Peak memory 201028 kb
Host smart-f830b0b2-d3d6-4700-8874-8932d8048e88
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381928301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1381928301
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1064968527
Short name T646
Test name
Test status
Simulation time 154414364 ps
CPU time 0.86 seconds
Started Aug 19 05:51:33 PM PDT 24
Finished Aug 19 05:51:34 PM PDT 24
Peak memory 199460 kb
Host smart-dec08b5c-d061-46ad-9dca-1a123d23dff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064968527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1064968527
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.3095393750
Short name T987
Test name
Test status
Simulation time 26784959 ps
CPU time 0.67 seconds
Started Aug 19 05:51:10 PM PDT 24
Finished Aug 19 05:51:10 PM PDT 24
Peak memory 198584 kb
Host smart-9b848a60-20d1-426a-b258-fa21e3deae8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095393750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.3095393750
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.1429704715
Short name T722
Test name
Test status
Simulation time 2413076070 ps
CPU time 6.18 seconds
Started Aug 19 05:51:28 PM PDT 24
Finished Aug 19 05:51:34 PM PDT 24
Peak memory 201300 kb
Host smart-c16c1007-0ee3-426b-9bee-31f5c8b31097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429704715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1429704715
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.2323872175
Short name T44
Test name
Test status
Simulation time 7229704415 ps
CPU time 16.68 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 201312 kb
Host smart-14255a08-6396-4bed-b6f6-a4d97b27cae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323872175 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.2323872175
Directory /workspace/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.1908942461
Short name T349
Test name
Test status
Simulation time 74229224 ps
CPU time 0.67 seconds
Started Aug 19 05:51:27 PM PDT 24
Finished Aug 19 05:51:27 PM PDT 24
Peak memory 198320 kb
Host smart-cce1f002-e3d7-497f-b7b9-f922be27b740
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908942461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.1908942461
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.2820874692
Short name T633
Test name
Test status
Simulation time 303244798 ps
CPU time 1.45 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:33 PM PDT 24
Peak memory 201024 kb
Host smart-4fc188f5-2b77-44bd-bf1c-4e5031321972
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820874692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.2820874692
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.442213410
Short name T493
Test name
Test status
Simulation time 64764040 ps
CPU time 0.73 seconds
Started Aug 19 05:51:22 PM PDT 24
Finished Aug 19 05:51:23 PM PDT 24
Peak memory 198864 kb
Host smart-004a187c-e7e8-49d1-b562-e2f7b0430325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442213410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.442213410
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.3907799307
Short name T678
Test name
Test status
Simulation time 74915644 ps
CPU time 0.75 seconds
Started Aug 19 05:51:27 PM PDT 24
Finished Aug 19 05:51:28 PM PDT 24
Peak memory 199192 kb
Host smart-0a8cc32f-732e-42e4-8ef3-68b1759aeee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907799307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.3907799307
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3610286157
Short name T609
Test name
Test status
Simulation time 30152466 ps
CPU time 0.61 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:33 PM PDT 24
Peak memory 197276 kb
Host smart-608c64d5-ca89-4e40-9283-a66e2b22c6c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610286157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.3610286157
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.2697319247
Short name T293
Test name
Test status
Simulation time 363349329 ps
CPU time 0.82 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:36 PM PDT 24
Peak memory 198144 kb
Host smart-0df2033a-5656-4a86-9560-92921d63b529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697319247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.2697319247
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.137107086
Short name T101
Test name
Test status
Simulation time 28394038 ps
CPU time 0.66 seconds
Started Aug 19 05:51:40 PM PDT 24
Finished Aug 19 05:51:41 PM PDT 24
Peak memory 197376 kb
Host smart-0151bc12-d598-413b-a6cf-ce6b336eadef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137107086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.137107086
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.3002136560
Short name T454
Test name
Test status
Simulation time 67342312 ps
CPU time 0.58 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:49 PM PDT 24
Peak memory 198428 kb
Host smart-2808dfd4-2fa9-4bfc-91ad-8d95c10db54d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002136560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3002136560
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.3833291949
Short name T395
Test name
Test status
Simulation time 41843726 ps
CPU time 0.67 seconds
Started Aug 19 05:51:36 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 201128 kb
Host smart-cc56d141-54d7-4db3-8342-c6190cbeb11b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833291949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.3833291949
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.2920869391
Short name T981
Test name
Test status
Simulation time 173034265 ps
CPU time 0.64 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 198356 kb
Host smart-5f14e39b-7970-4d33-854f-3433dd3005b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920869391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_w
akeup_race.2920869391
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.278705956
Short name T640
Test name
Test status
Simulation time 42279119 ps
CPU time 0.68 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:31 PM PDT 24
Peak memory 199064 kb
Host smart-eb4ef1f1-2364-4303-8024-63e9e7645048
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278705956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.278705956
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.202521490
Short name T400
Test name
Test status
Simulation time 175520556 ps
CPU time 0.82 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:32 PM PDT 24
Peak memory 209324 kb
Host smart-db99b8b9-a90b-4bc2-a778-4ffca4a020fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202521490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.202521490
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.2687239333
Short name T542
Test name
Test status
Simulation time 243641205 ps
CPU time 1.05 seconds
Started Aug 19 05:51:30 PM PDT 24
Finished Aug 19 05:51:31 PM PDT 24
Peak memory 200112 kb
Host smart-44fa47f3-79dd-449c-82d3-53f56f982642
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687239333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_
cm_ctrl_config_regwen.2687239333
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.725889058
Short name T432
Test name
Test status
Simulation time 926906561 ps
CPU time 2.54 seconds
Started Aug 19 05:51:26 PM PDT 24
Finished Aug 19 05:51:28 PM PDT 24
Peak memory 200968 kb
Host smart-b58eb145-e2b6-431a-af74-07323e3c1b0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725889058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.725889058
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1607891980
Short name T746
Test name
Test status
Simulation time 1212551841 ps
CPU time 2.1 seconds
Started Aug 19 05:51:26 PM PDT 24
Finished Aug 19 05:51:29 PM PDT 24
Peak memory 201112 kb
Host smart-8031b54f-89e9-4a6f-a9fe-46f6f7595961
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607891980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1607891980
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.1085678359
Short name T613
Test name
Test status
Simulation time 54234006 ps
CPU time 0.89 seconds
Started Aug 19 05:51:39 PM PDT 24
Finished Aug 19 05:51:40 PM PDT 24
Peak memory 199268 kb
Host smart-5cd36b04-67b1-4275-bff5-6647ddf525f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085678359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1085678359
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1229472708
Short name T601
Test name
Test status
Simulation time 42109915 ps
CPU time 0.74 seconds
Started Aug 19 05:51:24 PM PDT 24
Finished Aug 19 05:51:25 PM PDT 24
Peak memory 199364 kb
Host smart-6cd1a016-7527-40e0-9db5-1d28c41930ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229472708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1229472708
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all.441857258
Short name T829
Test name
Test status
Simulation time 1015838083 ps
CPU time 1.95 seconds
Started Aug 19 05:51:22 PM PDT 24
Finished Aug 19 05:51:24 PM PDT 24
Peak memory 201228 kb
Host smart-5a469118-9aba-45cb-927e-a713f4fbb549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441857258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.441857258
Directory /workspace/26.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all_with_rand_reset.2349452548
Short name T734
Test name
Test status
Simulation time 5952540956 ps
CPU time 8.52 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 201388 kb
Host smart-7f7bb14d-47d6-47bb-a35b-05af21fc81c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349452548 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all_with_rand_reset.2349452548
Directory /workspace/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.2568953532
Short name T332
Test name
Test status
Simulation time 77579163 ps
CPU time 0.68 seconds
Started Aug 19 05:51:39 PM PDT 24
Finished Aug 19 05:51:40 PM PDT 24
Peak memory 198312 kb
Host smart-70f60be6-a281-4992-b9ca-8dff00c7e50b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568953532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2568953532
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.3686344174
Short name T905
Test name
Test status
Simulation time 304682365 ps
CPU time 1.12 seconds
Started Aug 19 05:51:28 PM PDT 24
Finished Aug 19 05:51:29 PM PDT 24
Peak memory 200116 kb
Host smart-c433b7dc-c8db-4845-88f0-61e536cc2210
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686344174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.3686344174
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.593944249
Short name T352
Test name
Test status
Simulation time 52346382 ps
CPU time 0.66 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:33 PM PDT 24
Peak memory 198636 kb
Host smart-5c10acf4-b3f1-4d52-83f9-f14d82ebf283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593944249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.593944249
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.445210104
Short name T460
Test name
Test status
Simulation time 50584899 ps
CPU time 0.79 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:36 PM PDT 24
Peak memory 199204 kb
Host smart-9daef727-00b4-46e8-b78b-d55b343eed81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445210104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disa
ble_rom_integrity_check.445210104
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1299184998
Short name T140
Test name
Test status
Simulation time 33182347 ps
CPU time 0.61 seconds
Started Aug 19 05:51:29 PM PDT 24
Finished Aug 19 05:51:29 PM PDT 24
Peak memory 197264 kb
Host smart-cde0301a-1959-481a-9eb5-a5ecd852b4be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299184998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.1299184998
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.448287098
Short name T817
Test name
Test status
Simulation time 53801999 ps
CPU time 0.63 seconds
Started Aug 19 05:51:29 PM PDT 24
Finished Aug 19 05:51:30 PM PDT 24
Peak memory 197968 kb
Host smart-ffbc8257-5d12-4da0-9359-0d4742e71a22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448287098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.448287098
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.3898504841
Short name T655
Test name
Test status
Simulation time 38557016 ps
CPU time 0.6 seconds
Started Aug 19 05:51:30 PM PDT 24
Finished Aug 19 05:51:31 PM PDT 24
Peak memory 198068 kb
Host smart-d7b827bb-323b-405d-b982-2ac16c28ddc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898504841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3898504841
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.576689062
Short name T904
Test name
Test status
Simulation time 45935471 ps
CPU time 0.75 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:36 PM PDT 24
Peak memory 201360 kb
Host smart-098d23e1-21da-4c84-abfc-bb37390bee64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576689062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invali
d.576689062
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.3106255777
Short name T289
Test name
Test status
Simulation time 188470474 ps
CPU time 0.71 seconds
Started Aug 19 05:51:37 PM PDT 24
Finished Aug 19 05:51:38 PM PDT 24
Peak memory 198384 kb
Host smart-3fa8f9b6-8bf5-438f-8284-7e05965a0e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106255777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_w
akeup_race.3106255777
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.1198286027
Short name T843
Test name
Test status
Simulation time 73961825 ps
CPU time 0.63 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:33 PM PDT 24
Peak memory 198320 kb
Host smart-9977b450-306d-4106-b141-ab9449baf0ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198286027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1198286027
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.979366546
Short name T437
Test name
Test status
Simulation time 495462104 ps
CPU time 0.82 seconds
Started Aug 19 05:51:19 PM PDT 24
Finished Aug 19 05:51:20 PM PDT 24
Peak memory 209412 kb
Host smart-566cd3e0-0a5f-48f2-a033-2f527172d2f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979366546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.979366546
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.1010756245
Short name T528
Test name
Test status
Simulation time 109390420 ps
CPU time 0.93 seconds
Started Aug 19 05:51:36 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 198932 kb
Host smart-432b4de0-a0a9-4403-8430-991ab5e97f52
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010756245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_
cm_ctrl_config_regwen.1010756245
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.23646109
Short name T94
Test name
Test status
Simulation time 848441506 ps
CPU time 2.87 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 201092 kb
Host smart-0c9e4601-6628-426a-bfa6-7fc47188a41c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23646109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.23646109
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.653075083
Short name T747
Test name
Test status
Simulation time 1082609366 ps
CPU time 1.86 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 201172 kb
Host smart-6b75a69e-fdbf-4a9e-81cb-2291c17d099c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653075083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.653075083
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2802530098
Short name T285
Test name
Test status
Simulation time 72888428 ps
CPU time 0.93 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 199084 kb
Host smart-fa4fccaa-981c-4308-8543-6ec76cb78030
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802530098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2802530098
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.103025649
Short name T573
Test name
Test status
Simulation time 34015761 ps
CPU time 0.63 seconds
Started Aug 19 05:51:39 PM PDT 24
Finished Aug 19 05:51:40 PM PDT 24
Peak memory 199356 kb
Host smart-3256b7ae-f870-4034-8152-090bbe4bf1f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103025649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.103025649
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all.536189923
Short name T498
Test name
Test status
Simulation time 704347708 ps
CPU time 1.49 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 201196 kb
Host smart-45dc9506-c1c1-4e24-96e4-9fc7d79a01ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536189923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.536189923
Directory /workspace/27.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.1448720942
Short name T418
Test name
Test status
Simulation time 207961235 ps
CPU time 0.71 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:51:52 PM PDT 24
Peak memory 198636 kb
Host smart-9fce8df9-fa67-412f-9613-49fcc7baacef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448720942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.1448720942
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.188845473
Short name T903
Test name
Test status
Simulation time 369822021 ps
CPU time 1.07 seconds
Started Aug 19 05:51:29 PM PDT 24
Finished Aug 19 05:51:30 PM PDT 24
Peak memory 200196 kb
Host smart-d84b5eba-469d-4fcc-83bf-4ef7c263ea9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188845473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.188845473
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.1394875654
Short name T683
Test name
Test status
Simulation time 39593110 ps
CPU time 0.78 seconds
Started Aug 19 05:51:36 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 199032 kb
Host smart-7bf4bf44-49e3-4cdc-ad2a-3a10e545a9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394875654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.1394875654
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.3668877757
Short name T168
Test name
Test status
Simulation time 100964289 ps
CPU time 0.71 seconds
Started Aug 19 05:51:44 PM PDT 24
Finished Aug 19 05:51:45 PM PDT 24
Peak memory 199196 kb
Host smart-7d9add8d-2d7c-4d8d-9d50-8d6044a972b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668877757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.3668877757
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3340003271
Short name T915
Test name
Test status
Simulation time 29750701 ps
CPU time 0.64 seconds
Started Aug 19 05:51:18 PM PDT 24
Finished Aug 19 05:51:18 PM PDT 24
Peak memory 197264 kb
Host smart-a9d9f25f-35b2-40f4-b033-cac2e9cb0375
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340003271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.3340003271
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.3708919227
Short name T606
Test name
Test status
Simulation time 112124351 ps
CPU time 0.86 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 199176 kb
Host smart-44967d44-ae3d-452c-a9e7-6e1b50f01ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708919227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.3708919227
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.291603772
Short name T348
Test name
Test status
Simulation time 39122995 ps
CPU time 0.61 seconds
Started Aug 19 05:51:24 PM PDT 24
Finished Aug 19 05:51:25 PM PDT 24
Peak memory 198020 kb
Host smart-a7d2f792-df4d-4a23-998a-b96c95eaf242
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291603772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.291603772
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.3221943707
Short name T472
Test name
Test status
Simulation time 62043143 ps
CPU time 0.63 seconds
Started Aug 19 05:51:36 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 198108 kb
Host smart-76a5a908-97bf-4eed-99e3-2ddcd3d4a875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221943707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3221943707
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.3131231222
Short name T931
Test name
Test status
Simulation time 75739247 ps
CPU time 0.67 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 201356 kb
Host smart-0a52cd24-0fae-4717-a840-90752e696453
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131231222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.3131231222
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.988482610
Short name T896
Test name
Test status
Simulation time 267402557 ps
CPU time 0.84 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:32 PM PDT 24
Peak memory 198604 kb
Host smart-1b194716-6e11-42d4-a1fd-408af6c60229
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988482610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wa
keup_race.988482610
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.3992695945
Short name T933
Test name
Test status
Simulation time 82981107 ps
CPU time 0.96 seconds
Started Aug 19 05:51:41 PM PDT 24
Finished Aug 19 05:51:42 PM PDT 24
Peak memory 199900 kb
Host smart-e6f3d22f-978d-4a2c-9677-63fc039ba36b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992695945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.3992695945
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.1473469402
Short name T689
Test name
Test status
Simulation time 253980494 ps
CPU time 0.81 seconds
Started Aug 19 05:51:44 PM PDT 24
Finished Aug 19 05:51:45 PM PDT 24
Peak memory 209508 kb
Host smart-65bb2378-71b8-412f-bbcc-fa85b1b8ecbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473469402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1473469402
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.1907290276
Short name T57
Test name
Test status
Simulation time 106121862 ps
CPU time 0.84 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 198724 kb
Host smart-75e981de-c4e7-48e3-a743-5d616a343d1a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907290276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_
cm_ctrl_config_regwen.1907290276
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1939380224
Short name T477
Test name
Test status
Simulation time 1061834432 ps
CPU time 2.05 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:45 PM PDT 24
Peak memory 201168 kb
Host smart-f4e5115c-a942-4d5a-bb15-beb78a474a1d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939380224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1939380224
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4277353645
Short name T750
Test name
Test status
Simulation time 926020946 ps
CPU time 3.45 seconds
Started Aug 19 05:51:19 PM PDT 24
Finished Aug 19 05:51:23 PM PDT 24
Peak memory 201048 kb
Host smart-8a4eb3b9-955a-40c2-a329-b301c14d3815
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277353645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4277353645
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2702762366
Short name T846
Test name
Test status
Simulation time 144134222 ps
CPU time 0.85 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:36 PM PDT 24
Peak memory 199204 kb
Host smart-a92bee71-968f-4caf-a0db-64aed98e8efb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702762366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2702762366
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.2317040805
Short name T939
Test name
Test status
Simulation time 34692046 ps
CPU time 0.63 seconds
Started Aug 19 05:51:29 PM PDT 24
Finished Aug 19 05:51:30 PM PDT 24
Peak memory 199348 kb
Host smart-c35fcdae-cdf3-4d7e-83f8-656313a02226
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317040805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2317040805
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all.4018666185
Short name T554
Test name
Test status
Simulation time 1308510398 ps
CPU time 2.9 seconds
Started Aug 19 05:51:37 PM PDT 24
Finished Aug 19 05:51:40 PM PDT 24
Peak memory 201028 kb
Host smart-b3f40439-900f-4f53-b51f-075d99eb3d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018666185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.4018666185
Directory /workspace/28.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.62523184
Short name T426
Test name
Test status
Simulation time 323286832 ps
CPU time 1.02 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:32 PM PDT 24
Peak memory 199908 kb
Host smart-d7169d9e-9a11-4780-8af9-ba94d1d048f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62523184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.62523184
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.3143052127
Short name T490
Test name
Test status
Simulation time 55115954 ps
CPU time 0.78 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 199320 kb
Host smart-3a12195e-07a2-48d8-b5a2-b8a4b76b97c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143052127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.3143052127
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.2549482455
Short name T267
Test name
Test status
Simulation time 74034906 ps
CPU time 0.72 seconds
Started Aug 19 05:51:33 PM PDT 24
Finished Aug 19 05:51:33 PM PDT 24
Peak memory 198796 kb
Host smart-7425b9f0-4ff4-44fb-88d0-7e9b27ca31ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549482455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2549482455
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2374432740
Short name T971
Test name
Test status
Simulation time 29421728 ps
CPU time 0.63 seconds
Started Aug 19 05:51:39 PM PDT 24
Finished Aug 19 05:51:40 PM PDT 24
Peak memory 198072 kb
Host smart-721085c2-9fc0-4d88-8828-d8a3b5df5149
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374432740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.2374432740
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.2249670146
Short name T515
Test name
Test status
Simulation time 417466446 ps
CPU time 0.83 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:50 PM PDT 24
Peak memory 198480 kb
Host smart-c3261cd6-ead7-4999-a327-d7604de0bb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249670146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.2249670146
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.151111370
Short name T506
Test name
Test status
Simulation time 202165984 ps
CPU time 0.59 seconds
Started Aug 19 05:51:47 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 198168 kb
Host smart-4120d891-4a7d-4161-bc6b-6cc7acfd5765
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151111370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.151111370
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.1423032828
Short name T478
Test name
Test status
Simulation time 22667310 ps
CPU time 0.63 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:35 PM PDT 24
Peak memory 198088 kb
Host smart-d8677faa-ce52-4c39-847d-51ce17a588de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423032828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.1423032828
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.1646550648
Short name T417
Test name
Test status
Simulation time 56265501 ps
CPU time 0.7 seconds
Started Aug 19 05:51:37 PM PDT 24
Finished Aug 19 05:51:38 PM PDT 24
Peak memory 201328 kb
Host smart-1f95cc84-f701-468f-adf7-860917dc382b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646550648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.1646550648
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.952087404
Short name T824
Test name
Test status
Simulation time 280847002 ps
CPU time 0.9 seconds
Started Aug 19 05:51:26 PM PDT 24
Finished Aug 19 05:51:27 PM PDT 24
Peak memory 199688 kb
Host smart-a3bc014c-4dcb-42f7-9249-fc986c5efd81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952087404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wa
keup_race.952087404
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.1062591070
Short name T562
Test name
Test status
Simulation time 84319241 ps
CPU time 0.73 seconds
Started Aug 19 05:51:40 PM PDT 24
Finished Aug 19 05:51:41 PM PDT 24
Peak memory 198300 kb
Host smart-e3fb4166-bfb2-4139-88ba-9eb393fecb81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062591070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.1062591070
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.402294377
Short name T775
Test name
Test status
Simulation time 159546774 ps
CPU time 0.77 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:51:52 PM PDT 24
Peak memory 209452 kb
Host smart-fd4a83b3-3ec2-4510-b343-b2dcb5b430a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402294377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.402294377
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.759909472
Short name T548
Test name
Test status
Simulation time 109228036 ps
CPU time 0.94 seconds
Started Aug 19 05:51:28 PM PDT 24
Finished Aug 19 05:51:29 PM PDT 24
Peak memory 200036 kb
Host smart-89d61755-394a-4bda-9fde-5e091ebd86a6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759909472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_c
m_ctrl_config_regwen.759909472
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4193749339
Short name T396
Test name
Test status
Simulation time 1179208472 ps
CPU time 2.3 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:34 PM PDT 24
Peak memory 200948 kb
Host smart-2d997a94-34db-4d27-8591-a6eb776b1fd2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193749339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4193749339
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2479302107
Short name T700
Test name
Test status
Simulation time 897985568 ps
CPU time 2.71 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:45 PM PDT 24
Peak memory 201064 kb
Host smart-1796de7b-fcfc-4e8f-8901-ef9bd9bd03a9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479302107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2479302107
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.976418774
Short name T450
Test name
Test status
Simulation time 50761648 ps
CPU time 0.84 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:32 PM PDT 24
Peak memory 199080 kb
Host smart-7bb91d36-fef0-4ba5-ab20-a54253d11302
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976418774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_
mubi.976418774
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1226967193
Short name T796
Test name
Test status
Simulation time 29788222 ps
CPU time 0.69 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:46 PM PDT 24
Peak memory 199404 kb
Host smart-0023049e-9c2e-47bd-ae2e-757ceaaab20e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226967193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1226967193
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.2428487234
Short name T291
Test name
Test status
Simulation time 1536085825 ps
CPU time 5.64 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 201208 kb
Host smart-c2ad765d-401e-45dd-8daa-9baaa5f686dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428487234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.2428487234
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.4252324463
Short name T962
Test name
Test status
Simulation time 4280059649 ps
CPU time 11.72 seconds
Started Aug 19 05:51:29 PM PDT 24
Finished Aug 19 05:51:40 PM PDT 24
Peak memory 201368 kb
Host smart-7ee8971a-01d0-4bd5-bf83-1d7eb740bb3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252324463 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.4252324463
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.4074274188
Short name T540
Test name
Test status
Simulation time 327698402 ps
CPU time 1.06 seconds
Started Aug 19 05:51:32 PM PDT 24
Finished Aug 19 05:51:34 PM PDT 24
Peak memory 199720 kb
Host smart-91c75158-a801-4d47-9b9c-4eb6c9894eec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074274188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.4074274188
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.3388619988
Short name T316
Test name
Test status
Simulation time 76524958 ps
CPU time 0.74 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:35 PM PDT 24
Peak memory 199304 kb
Host smart-62f02a45-9f89-40e7-be45-a4a887f5e92b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388619988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.3388619988
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.4061147062
Short name T105
Test name
Test status
Simulation time 25193491 ps
CPU time 0.83 seconds
Started Aug 19 05:50:29 PM PDT 24
Finished Aug 19 05:50:30 PM PDT 24
Peak memory 198892 kb
Host smart-ebb35ffe-243e-4c2a-869e-bd469ccaecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061147062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.4061147062
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.3717393715
Short name T502
Test name
Test status
Simulation time 199389185 ps
CPU time 0.71 seconds
Started Aug 19 05:50:21 PM PDT 24
Finished Aug 19 05:50:22 PM PDT 24
Peak memory 199212 kb
Host smart-5df4bc3e-4a05-4e77-b0a2-4376428d9b17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717393715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.3717393715
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.494015563
Short name T137
Test name
Test status
Simulation time 30022800 ps
CPU time 0.67 seconds
Started Aug 19 05:50:35 PM PDT 24
Finished Aug 19 05:50:35 PM PDT 24
Peak memory 198004 kb
Host smart-5e12e59c-1601-49aa-87ce-4abbefc05a82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494015563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_m
alfunc.494015563
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.3127378658
Short name T658
Test name
Test status
Simulation time 442577353 ps
CPU time 0.84 seconds
Started Aug 19 05:50:21 PM PDT 24
Finished Aug 19 05:50:22 PM PDT 24
Peak memory 198432 kb
Host smart-6d690afe-4e36-48f2-ac08-4035823ab90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127378658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3127378658
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.1816868432
Short name T611
Test name
Test status
Simulation time 66800129 ps
CPU time 0.62 seconds
Started Aug 19 05:50:32 PM PDT 24
Finished Aug 19 05:50:32 PM PDT 24
Peak memory 198176 kb
Host smart-f7447f01-0124-4f1e-9c1f-86251619b818
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816868432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1816868432
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.4232854051
Short name T676
Test name
Test status
Simulation time 87903228 ps
CPU time 0.61 seconds
Started Aug 19 05:50:20 PM PDT 24
Finished Aug 19 05:50:20 PM PDT 24
Peak memory 197428 kb
Host smart-36677831-fb99-4faf-bebb-481a43f1cdb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232854051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.4232854051
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.2007194457
Short name T414
Test name
Test status
Simulation time 42196906 ps
CPU time 0.72 seconds
Started Aug 19 05:50:27 PM PDT 24
Finished Aug 19 05:50:27 PM PDT 24
Peak memory 200304 kb
Host smart-595f23f3-a35d-44b7-93f3-f857bf4b2e8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007194457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.2007194457
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.558183937
Short name T32
Test name
Test status
Simulation time 73786070 ps
CPU time 0.64 seconds
Started Aug 19 05:50:23 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 198320 kb
Host smart-da52808a-9cf1-4bf1-a525-95026fc9d4b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558183937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wak
eup_race.558183937
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.4292627981
Short name T732
Test name
Test status
Simulation time 81486670 ps
CPU time 1.02 seconds
Started Aug 19 05:50:22 PM PDT 24
Finished Aug 19 05:50:23 PM PDT 24
Peak memory 199984 kb
Host smart-3205901a-be2a-4ad8-9dc2-7ba8640e8840
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292627981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.4292627981
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.670261257
Short name T826
Test name
Test status
Simulation time 108782234 ps
CPU time 1.1 seconds
Started Aug 19 05:50:30 PM PDT 24
Finished Aug 19 05:50:31 PM PDT 24
Peak memory 209476 kb
Host smart-f56a2483-e04a-40e1-859f-7cb71d8b5991
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670261257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.670261257
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.751970001
Short name T18
Test name
Test status
Simulation time 2263056755 ps
CPU time 1.37 seconds
Started Aug 19 05:50:11 PM PDT 24
Finished Aug 19 05:50:13 PM PDT 24
Peak memory 217636 kb
Host smart-5c4492f4-6fc5-42b2-bd36-6c8d0c71e189
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751970001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.751970001
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.342291150
Short name T641
Test name
Test status
Simulation time 248423681 ps
CPU time 1.26 seconds
Started Aug 19 05:50:15 PM PDT 24
Finished Aug 19 05:50:16 PM PDT 24
Peak memory 199960 kb
Host smart-c297762e-d32f-47ad-91a3-e0f3ed10c6dc
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342291150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm
_ctrl_config_regwen.342291150
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2445991381
Short name T259
Test name
Test status
Simulation time 961085324 ps
CPU time 2.01 seconds
Started Aug 19 05:50:15 PM PDT 24
Finished Aug 19 05:50:17 PM PDT 24
Peak memory 201056 kb
Host smart-7edd27a5-1ebd-4c48-bfaa-f2251f03805c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445991381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2445991381
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2762105024
Short name T469
Test name
Test status
Simulation time 893071192 ps
CPU time 2.79 seconds
Started Aug 19 05:50:13 PM PDT 24
Finished Aug 19 05:50:16 PM PDT 24
Peak memory 201112 kb
Host smart-70595299-667b-45bc-bab9-7b4d5510113c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762105024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2762105024
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1893805686
Short name T880
Test name
Test status
Simulation time 190313814 ps
CPU time 0.87 seconds
Started Aug 19 05:50:17 PM PDT 24
Finished Aug 19 05:50:18 PM PDT 24
Peak memory 199456 kb
Host smart-ceae4a02-dd5c-4d46-a4e2-a8d2e318710a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893805686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1893805686
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.184998211
Short name T993
Test name
Test status
Simulation time 41464542 ps
CPU time 0.68 seconds
Started Aug 19 05:50:31 PM PDT 24
Finished Aug 19 05:50:32 PM PDT 24
Peak memory 199412 kb
Host smart-1beb4e6a-baf6-4d63-b775-db737ade0302
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184998211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.184998211
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all.3092121036
Short name T36
Test name
Test status
Simulation time 2481665856 ps
CPU time 3.54 seconds
Started Aug 19 05:50:13 PM PDT 24
Finished Aug 19 05:50:17 PM PDT 24
Peak memory 201216 kb
Host smart-f8676c49-5504-4249-b566-5f3482fd2593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092121036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.3092121036
Directory /workspace/3.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.1201504903
Short name T980
Test name
Test status
Simulation time 265005969 ps
CPU time 1.21 seconds
Started Aug 19 05:50:22 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 199876 kb
Host smart-96e2e4ba-a0af-43c9-8195-6701faefcf95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201504903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.1201504903
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.4009826005
Short name T371
Test name
Test status
Simulation time 211906763 ps
CPU time 1.31 seconds
Started Aug 19 05:50:12 PM PDT 24
Finished Aug 19 05:50:14 PM PDT 24
Peak memory 200204 kb
Host smart-e491f96d-6bf9-474b-af95-3c3ad7dc3f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009826005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.4009826005
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.143142845
Short name T584
Test name
Test status
Simulation time 21794321 ps
CPU time 0.74 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 199192 kb
Host smart-5afdee7b-9dd6-4198-a003-d90169b6a4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143142845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.143142845
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.2998482876
Short name T6
Test name
Test status
Simulation time 80207861 ps
CPU time 0.67 seconds
Started Aug 19 05:51:24 PM PDT 24
Finished Aug 19 05:51:29 PM PDT 24
Peak memory 199160 kb
Host smart-a7735bc3-0137-4296-b1d3-b6369f2f4f36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998482876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.2998482876
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3772370250
Short name T739
Test name
Test status
Simulation time 40307004 ps
CPU time 0.6 seconds
Started Aug 19 05:51:41 PM PDT 24
Finished Aug 19 05:51:42 PM PDT 24
Peak memory 198076 kb
Host smart-b292279d-1081-4397-a2ca-0895d1468b32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772370250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.3772370250
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.3959341357
Short name T685
Test name
Test status
Simulation time 380269665 ps
CPU time 0.82 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 198152 kb
Host smart-51b11e82-75e2-4c72-8fa3-f4ea4dabdde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959341357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.3959341357
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.2752856723
Short name T709
Test name
Test status
Simulation time 59475510 ps
CPU time 0.65 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 197452 kb
Host smart-289cfe49-71f7-45e9-8533-ea93b6e5300a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752856723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2752856723
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.370500509
Short name T591
Test name
Test status
Simulation time 51267650 ps
CPU time 0.62 seconds
Started Aug 19 05:51:45 PM PDT 24
Finished Aug 19 05:51:46 PM PDT 24
Peak memory 198120 kb
Host smart-da881af6-99db-47a7-9f88-7498fdd2dac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370500509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.370500509
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.426767342
Short name T324
Test name
Test status
Simulation time 39921628 ps
CPU time 0.72 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 201360 kb
Host smart-67172323-0e91-4556-92f0-5c0395ad1fd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426767342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invali
d.426767342
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.1804602931
Short name T701
Test name
Test status
Simulation time 385221767 ps
CPU time 0.82 seconds
Started Aug 19 05:51:41 PM PDT 24
Finished Aug 19 05:51:42 PM PDT 24
Peak memory 198740 kb
Host smart-49819f42-d41b-46e3-a8d6-c5ee111eeeb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804602931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w
akeup_race.1804602931
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.1987117613
Short name T910
Test name
Test status
Simulation time 84219621 ps
CPU time 0.97 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 199916 kb
Host smart-502351d3-d8ea-4947-b50b-41472fd9053c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987117613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.1987117613
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.3173216472
Short name T541
Test name
Test status
Simulation time 161022614 ps
CPU time 0.82 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 209508 kb
Host smart-f2394433-8f5a-4e8b-9bd4-e23dcf9d7994
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173216472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.3173216472
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.779748391
Short name T687
Test name
Test status
Simulation time 296631643 ps
CPU time 0.97 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 200068 kb
Host smart-0e1fa22a-b94c-43b3-8c9c-50974a66d3a6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779748391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_c
m_ctrl_config_regwen.779748391
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3928802471
Short name T972
Test name
Test status
Simulation time 1973287587 ps
CPU time 1.75 seconds
Started Aug 19 05:51:44 PM PDT 24
Finished Aug 19 05:51:46 PM PDT 24
Peak memory 201096 kb
Host smart-911ccd2b-c967-4e4c-b0a8-2e3104267a52
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928802471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3928802471
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.894958626
Short name T492
Test name
Test status
Simulation time 1392162644 ps
CPU time 2.42 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:34 PM PDT 24
Peak memory 201152 kb
Host smart-4a85c7e4-fe57-409e-9ffd-002aec6fd685
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894958626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.894958626
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.921546808
Short name T207
Test name
Test status
Simulation time 52921122 ps
CPU time 0.88 seconds
Started Aug 19 05:51:30 PM PDT 24
Finished Aug 19 05:51:31 PM PDT 24
Peak memory 199640 kb
Host smart-000ed490-ce7d-4225-b95b-179cdd23b9b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921546808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_
mubi.921546808
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.2079509881
Short name T965
Test name
Test status
Simulation time 74190904 ps
CPU time 0.64 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 198560 kb
Host smart-851f1057-dc45-4026-b375-fdfc5d362a9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079509881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2079509881
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all.1646174443
Short name T679
Test name
Test status
Simulation time 1371240554 ps
CPU time 2.18 seconds
Started Aug 19 05:51:37 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 201172 kb
Host smart-4d2dd7e9-ea5e-46d0-8030-cee2f10909b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646174443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.1646174443
Directory /workspace/30.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.4095410522
Short name T816
Test name
Test status
Simulation time 3671343582 ps
CPU time 6.39 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 201364 kb
Host smart-5c4b642e-8e5a-4493-8ae6-6e9614687cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095410522 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_reset.4095410522
Directory /workspace/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup.2936500683
Short name T424
Test name
Test status
Simulation time 94153599 ps
CPU time 0.66 seconds
Started Aug 19 05:51:35 PM PDT 24
Finished Aug 19 05:51:36 PM PDT 24
Peak memory 199180 kb
Host smart-44cdf274-3d60-4560-ab35-c41e3e3c0e61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936500683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.2936500683
Directory /workspace/30.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.3688662578
Short name T405
Test name
Test status
Simulation time 540925903 ps
CPU time 1.2 seconds
Started Aug 19 05:51:50 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 200908 kb
Host smart-1cc8ff1e-a3ff-494d-afab-cb0acf6567f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688662578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.3688662578
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.3305937064
Short name T644
Test name
Test status
Simulation time 41255049 ps
CPU time 0.9 seconds
Started Aug 19 05:51:39 PM PDT 24
Finished Aug 19 05:51:40 PM PDT 24
Peak memory 200308 kb
Host smart-707a5c9a-98e1-4cbe-8e33-9ad78e778db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305937064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3305937064
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.299978502
Short name T147
Test name
Test status
Simulation time 55268485 ps
CPU time 0.79 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 199192 kb
Host smart-f132d6f8-0ef8-4349-aa52-f377de6efe91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299978502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disa
ble_rom_integrity_check.299978502
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.433415993
Short name T141
Test name
Test status
Simulation time 39173955 ps
CPU time 0.6 seconds
Started Aug 19 05:52:01 PM PDT 24
Finished Aug 19 05:52:02 PM PDT 24
Peak memory 197992 kb
Host smart-a4f01dff-5661-4cab-b467-351b325a40f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433415993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_
malfunc.433415993
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.2145724909
Short name T9
Test name
Test status
Simulation time 385994616 ps
CPU time 0.84 seconds
Started Aug 19 05:52:03 PM PDT 24
Finished Aug 19 05:52:04 PM PDT 24
Peak memory 198084 kb
Host smart-74243084-348a-4456-ba71-58616ad66984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145724909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.2145724909
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.1691684445
Short name T800
Test name
Test status
Simulation time 47777876 ps
CPU time 0.68 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:50 PM PDT 24
Peak memory 197376 kb
Host smart-897699d8-23ce-4640-830b-5536d3caa1a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691684445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1691684445
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.1364948405
Short name T277
Test name
Test status
Simulation time 22121419 ps
CPU time 0.62 seconds
Started Aug 19 05:51:41 PM PDT 24
Finished Aug 19 05:51:42 PM PDT 24
Peak memory 198092 kb
Host smart-a968d9d2-2e65-4875-b81a-28b7ab31f6fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364948405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1364948405
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.1477382066
Short name T630
Test name
Test status
Simulation time 45459770 ps
CPU time 0.73 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 201364 kb
Host smart-394ed314-8230-43c5-a468-224870661573
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477382066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.1477382066
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.3901591147
Short name T566
Test name
Test status
Simulation time 85665215 ps
CPU time 0.78 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:31 PM PDT 24
Peak memory 198392 kb
Host smart-86d80e18-85f5-493e-afe3-7c58c71f08d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901591147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_w
akeup_race.3901591147
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.1001156339
Short name T327
Test name
Test status
Simulation time 38131911 ps
CPU time 0.78 seconds
Started Aug 19 05:51:30 PM PDT 24
Finished Aug 19 05:51:31 PM PDT 24
Peak memory 199084 kb
Host smart-b796b6f7-6efd-4189-8218-d43e2a67cefd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001156339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.1001156339
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.1455399705
Short name T853
Test name
Test status
Simulation time 97419866 ps
CPU time 0.94 seconds
Started Aug 19 05:51:45 PM PDT 24
Finished Aug 19 05:51:46 PM PDT 24
Peak memory 209032 kb
Host smart-da93c651-0155-4336-b61f-bba79a6567fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455399705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.1455399705
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.2667833808
Short name T199
Test name
Test status
Simulation time 67597991 ps
CPU time 0.65 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 199216 kb
Host smart-167b8535-62a7-43fa-9f2e-2509ae7f16f1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667833808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_
cm_ctrl_config_regwen.2667833808
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1249297728
Short name T388
Test name
Test status
Simulation time 802611290 ps
CPU time 3.09 seconds
Started Aug 19 05:51:33 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 201116 kb
Host smart-216312a2-4af7-4577-8418-fb93264820e5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249297728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1249297728
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1485123939
Short name T206
Test name
Test status
Simulation time 64865682 ps
CPU time 0.92 seconds
Started Aug 19 05:51:33 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 199172 kb
Host smart-b54aa089-53c2-49f6-820d-8d2856989b72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485123939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1485123939
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.3726422113
Short name T364
Test name
Test status
Simulation time 31758524 ps
CPU time 0.66 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 199404 kb
Host smart-ae9447b5-6775-4d4a-ae95-898438f00c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726422113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3726422113
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.3809618512
Short name T482
Test name
Test status
Simulation time 1158680280 ps
CPU time 3.77 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:46 PM PDT 24
Peak memory 201240 kb
Host smart-a61e9b0c-66ef-4b0a-a03f-dcae0075fc7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809618512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.3809618512
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.75346076
Short name T46
Test name
Test status
Simulation time 2679523216 ps
CPU time 10.78 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:53 PM PDT 24
Peak memory 201380 kb
Host smart-4cd66fff-7047-4f50-a4e6-5c5a5bfccf12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75346076 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand_reset.75346076
Directory /workspace/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.597980236
Short name T959
Test name
Test status
Simulation time 113181157 ps
CPU time 0.79 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:51:52 PM PDT 24
Peak memory 198548 kb
Host smart-62b00fc1-6124-46ae-9fe9-01d9feac1fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597980236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.597980236
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.1139739964
Short name T947
Test name
Test status
Simulation time 536546171 ps
CPU time 1.02 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:49 PM PDT 24
Peak memory 201012 kb
Host smart-496333f4-f09c-4d57-b3a2-8a599d058ed5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139739964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.1139739964
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.3895163364
Short name T621
Test name
Test status
Simulation time 79357050 ps
CPU time 0.67 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 198656 kb
Host smart-59011596-5e98-47c0-b376-2f20eac48a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895163364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3895163364
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.1243757222
Short name T346
Test name
Test status
Simulation time 66852902 ps
CPU time 0.68 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:49 PM PDT 24
Peak memory 198684 kb
Host smart-affb0cc0-7897-499b-bbe2-028459586ef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243757222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.1243757222
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.138660283
Short name T302
Test name
Test status
Simulation time 40002007 ps
CPU time 0.59 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:32 PM PDT 24
Peak memory 197264 kb
Host smart-c455e28b-03a7-43c2-b11c-7570ff9e7737
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138660283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_
malfunc.138660283
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.2448646003
Short name T423
Test name
Test status
Simulation time 110846848 ps
CPU time 0.83 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:50 PM PDT 24
Peak memory 198152 kb
Host smart-c6b73891-0e62-4c3b-94d5-1fddd8bd6d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448646003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2448646003
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.735807864
Short name T189
Test name
Test status
Simulation time 76342853 ps
CPU time 0.62 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:35 PM PDT 24
Peak memory 198100 kb
Host smart-d74ac37c-1107-4673-9f81-00af2ae2dd22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735807864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.735807864
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.2606472008
Short name T226
Test name
Test status
Simulation time 41742866 ps
CPU time 0.64 seconds
Started Aug 19 05:51:36 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 198444 kb
Host smart-98c58c3b-6404-4076-b8af-60414d59fb1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606472008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2606472008
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.3623462152
Short name T357
Test name
Test status
Simulation time 42113942 ps
CPU time 0.76 seconds
Started Aug 19 05:51:39 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 201520 kb
Host smart-f2ac78db-db96-44e2-885c-8e5ee817a409
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623462152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.3623462152
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.581484032
Short name T919
Test name
Test status
Simulation time 220616162 ps
CPU time 0.83 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 198584 kb
Host smart-230df42b-e0a9-410c-9d13-1354a0e97238
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581484032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wa
keup_race.581484032
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.1656071229
Short name T350
Test name
Test status
Simulation time 195975229 ps
CPU time 0.89 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 199972 kb
Host smart-ea520c23-298e-4d3f-a747-b9fddc2020d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656071229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.1656071229
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.4114877018
Short name T439
Test name
Test status
Simulation time 115102074 ps
CPU time 0.96 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 209584 kb
Host smart-f9dc4ffd-13fb-4190-846c-4266d6866d3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114877018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.4114877018
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.4037127162
Short name T708
Test name
Test status
Simulation time 613718184 ps
CPU time 0.75 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 198872 kb
Host smart-8d1f682b-3689-44e4-b0b1-cd10ada46226
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037127162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_
cm_ctrl_config_regwen.4037127162
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1977143501
Short name T695
Test name
Test status
Simulation time 1322294410 ps
CPU time 2.14 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 201120 kb
Host smart-b13a142a-e679-43a6-97c6-933135f4bce0
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977143501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1977143501
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.592592451
Short name T827
Test name
Test status
Simulation time 1048104037 ps
CPU time 2.63 seconds
Started Aug 19 05:51:36 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 201100 kb
Host smart-08a7c1c9-d269-4991-bf7d-32bf023f7374
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592592451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.592592451
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3211785242
Short name T73
Test name
Test status
Simulation time 173171290 ps
CPU time 0.95 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 199380 kb
Host smart-acea6ca3-7807-47b7-91bd-8fa9ee27f517
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211785242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3211785242
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.1710901918
Short name T433
Test name
Test status
Simulation time 55154971 ps
CPU time 0.63 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:35 PM PDT 24
Peak memory 198528 kb
Host smart-300ea49c-5ecc-470b-a9da-da117f23e8b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710901918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1710901918
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.1172641443
Short name T174
Test name
Test status
Simulation time 4651870026 ps
CPU time 3.66 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 201392 kb
Host smart-db075179-4176-42c7-a1dd-8631b48d2820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172641443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.1172641443
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all_with_rand_reset.756388916
Short name T134
Test name
Test status
Simulation time 1466646950 ps
CPU time 5.79 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:49 PM PDT 24
Peak memory 201304 kb
Host smart-4e835f66-8a11-46c7-97e2-642d9f222bed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756388916 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_reset.756388916
Directory /workspace/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.3738048654
Short name T407
Test name
Test status
Simulation time 251083377 ps
CPU time 0.91 seconds
Started Aug 19 05:51:31 PM PDT 24
Finished Aug 19 05:51:32 PM PDT 24
Peak memory 199696 kb
Host smart-ea72f17c-b0f6-4f10-83d9-c01e8bba882e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738048654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.3738048654
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.1717087781
Short name T173
Test name
Test status
Simulation time 277608479 ps
CPU time 0.76 seconds
Started Aug 19 05:51:28 PM PDT 24
Finished Aug 19 05:51:28 PM PDT 24
Peak memory 199364 kb
Host smart-bce448af-f507-4b47-833e-2f0fc2c284ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717087781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.1717087781
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.2993898054
Short name T674
Test name
Test status
Simulation time 130455335 ps
CPU time 0.8 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 200020 kb
Host smart-ca29bbab-5a1e-418a-903d-c877c43bbede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993898054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.2993898054
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.4058702225
Short name T622
Test name
Test status
Simulation time 63674976 ps
CPU time 0.71 seconds
Started Aug 19 05:52:07 PM PDT 24
Finished Aug 19 05:52:07 PM PDT 24
Peak memory 199208 kb
Host smart-7e905a2a-8979-4b4a-8be8-462cd03a4047
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058702225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.4058702225
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3063897753
Short name T555
Test name
Test status
Simulation time 40147146 ps
CPU time 0.59 seconds
Started Aug 19 05:51:55 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 197948 kb
Host smart-90579198-5a11-47c0-91d6-790a583a1f44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063897753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.3063897753
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.1068335613
Short name T355
Test name
Test status
Simulation time 218887119 ps
CPU time 0.85 seconds
Started Aug 19 05:51:58 PM PDT 24
Finished Aug 19 05:51:59 PM PDT 24
Peak memory 198440 kb
Host smart-8b7e3b50-8721-423c-aec2-a787674f02a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068335613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.1068335613
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.3213053623
Short name T850
Test name
Test status
Simulation time 91099760 ps
CPU time 0.64 seconds
Started Aug 19 05:51:54 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 197264 kb
Host smart-fc561413-39ab-4198-a40a-d34fe7aad570
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213053623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3213053623
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.4068617168
Short name T567
Test name
Test status
Simulation time 73649029 ps
CPU time 0.59 seconds
Started Aug 19 05:52:03 PM PDT 24
Finished Aug 19 05:52:03 PM PDT 24
Peak memory 198120 kb
Host smart-02605248-04be-4f1b-90bf-172177067016
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068617168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.4068617168
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.2903645686
Short name T647
Test name
Test status
Simulation time 43615570 ps
CPU time 0.68 seconds
Started Aug 19 05:51:53 PM PDT 24
Finished Aug 19 05:51:53 PM PDT 24
Peak memory 201368 kb
Host smart-79e20c4a-5d85-422f-b5fa-6a61391ca2e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903645686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.2903645686
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.3101992263
Short name T589
Test name
Test status
Simulation time 66046422 ps
CPU time 0.64 seconds
Started Aug 19 05:51:52 PM PDT 24
Finished Aug 19 05:51:52 PM PDT 24
Peak memory 198344 kb
Host smart-a2f7a33d-c549-4f48-8d87-c59a25c92dbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101992263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_w
akeup_race.3101992263
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.469666898
Short name T832
Test name
Test status
Simulation time 82211757 ps
CPU time 0.83 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:49 PM PDT 24
Peak memory 199112 kb
Host smart-1f4f346b-6f8c-44a1-a350-b2b47df78242
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469666898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.469666898
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.1003020769
Short name T583
Test name
Test status
Simulation time 113861338 ps
CPU time 1.11 seconds
Started Aug 19 05:51:44 PM PDT 24
Finished Aug 19 05:51:45 PM PDT 24
Peak memory 209432 kb
Host smart-a5d976b0-c362-442d-bfec-2f9eadd9769b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003020769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1003020769
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.1667341423
Short name T59
Test name
Test status
Simulation time 244252085 ps
CPU time 1.24 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:51 PM PDT 24
Peak memory 200196 kb
Host smart-178b725c-c6ff-4294-ae79-28349e6bc239
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667341423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_
cm_ctrl_config_regwen.1667341423
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3586646976
Short name T874
Test name
Test status
Simulation time 1035527250 ps
CPU time 2.03 seconds
Started Aug 19 05:51:41 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 201080 kb
Host smart-50a30fa4-1e5b-4614-ae7a-d7bcf23a7f2d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586646976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3586646976
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1530490611
Short name T625
Test name
Test status
Simulation time 813577490 ps
CPU time 2.96 seconds
Started Aug 19 05:51:50 PM PDT 24
Finished Aug 19 05:51:53 PM PDT 24
Peak memory 200968 kb
Host smart-c05d2b7c-baef-4331-98e9-1aac6f595763
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530490611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1530490611
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.3662712436
Short name T650
Test name
Test status
Simulation time 67655944 ps
CPU time 0.91 seconds
Started Aug 19 05:51:59 PM PDT 24
Finished Aug 19 05:52:00 PM PDT 24
Peak memory 199192 kb
Host smart-e8291524-8856-4bbb-8d36-d3bc64e0f6eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662712436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3662712436
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.3913246716
Short name T463
Test name
Test status
Simulation time 58021394 ps
CPU time 0.63 seconds
Started Aug 19 05:51:34 PM PDT 24
Finished Aug 19 05:51:35 PM PDT 24
Peak memory 198520 kb
Host smart-1bced287-bee5-47bb-9ce0-7a86c22ab50c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913246716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3913246716
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all.109668848
Short name T453
Test name
Test status
Simulation time 1888154333 ps
CPU time 5.68 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 201160 kb
Host smart-8a38c70a-426c-4d0f-a47c-3c917447b1d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109668848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.109668848
Directory /workspace/33.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.3677248384
Short name T872
Test name
Test status
Simulation time 7585310427 ps
CPU time 11.33 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:52:02 PM PDT 24
Peak memory 201344 kb
Host smart-fbe1b2ec-f025-4269-ad13-bf9fc67e1828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677248384 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand_reset.3677248384
Directory /workspace/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.3317497854
Short name T594
Test name
Test status
Simulation time 221683966 ps
CPU time 1.14 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:45 PM PDT 24
Peak memory 199672 kb
Host smart-c00b6164-3a7d-4c9f-8909-d2e686417905
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317497854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.3317497854
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.3867653897
Short name T908
Test name
Test status
Simulation time 272635047 ps
CPU time 0.93 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 201016 kb
Host smart-2d9f9258-4aa2-4f10-9a75-2189183335fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867653897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.3867653897
Directory /workspace/33.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.1247295908
Short name T782
Test name
Test status
Simulation time 65995707 ps
CPU time 0.84 seconds
Started Aug 19 05:51:54 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 200264 kb
Host smart-fbbc148c-3f18-45fb-af6a-9b1c77af0c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247295908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1247295908
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.3061111239
Short name T345
Test name
Test status
Simulation time 76916877 ps
CPU time 0.68 seconds
Started Aug 19 05:51:56 PM PDT 24
Finished Aug 19 05:51:57 PM PDT 24
Peak memory 198800 kb
Host smart-cef38913-cfdd-4af0-9ed7-d3fa9117c40f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061111239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.3061111239
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3085624497
Short name T932
Test name
Test status
Simulation time 44125095 ps
CPU time 0.57 seconds
Started Aug 19 05:51:40 PM PDT 24
Finished Aug 19 05:51:41 PM PDT 24
Peak memory 197984 kb
Host smart-c0b50ee6-47b0-4e2b-b21a-989f58dbbf9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085624497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.3085624497
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.849930193
Short name T294
Test name
Test status
Simulation time 1839796594 ps
CPU time 0.82 seconds
Started Aug 19 05:52:14 PM PDT 24
Finished Aug 19 05:52:15 PM PDT 24
Peak memory 197996 kb
Host smart-82e35808-32ad-4cc5-a1e9-add69abd8fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849930193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.849930193
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.426161201
Short name T341
Test name
Test status
Simulation time 47236724 ps
CPU time 0.67 seconds
Started Aug 19 05:51:56 PM PDT 24
Finished Aug 19 05:51:57 PM PDT 24
Peak memory 198080 kb
Host smart-bf466e02-5dc5-42e3-858a-12e7dc52b867
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426161201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.426161201
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.183284486
Short name T39
Test name
Test status
Simulation time 181710796 ps
CPU time 0.63 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 198128 kb
Host smart-8f4a75f6-36cd-4fad-bc1b-4fa8812a63e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183284486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.183284486
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2925541767
Short name T866
Test name
Test status
Simulation time 84221828 ps
CPU time 0.68 seconds
Started Aug 19 05:51:59 PM PDT 24
Finished Aug 19 05:52:00 PM PDT 24
Peak memory 201316 kb
Host smart-462ff5ef-0a7f-48e6-877e-ac55ce4c397a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925541767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2925541767
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.1376052559
Short name T208
Test name
Test status
Simulation time 63603405 ps
CPU time 0.74 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 198380 kb
Host smart-83a08603-1ecd-4158-b4dc-dbbe35463f20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376052559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_w
akeup_race.1376052559
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.729923102
Short name T620
Test name
Test status
Simulation time 42267624 ps
CPU time 0.69 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:49 PM PDT 24
Peak memory 199156 kb
Host smart-fe389fe8-f982-4ae5-95b4-6afba7ff66fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729923102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.729923102
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.2515839256
Short name T569
Test name
Test status
Simulation time 95108855 ps
CPU time 0.91 seconds
Started Aug 19 05:51:44 PM PDT 24
Finished Aug 19 05:51:45 PM PDT 24
Peak memory 209508 kb
Host smart-275855e4-5313-46a3-9fbd-c77be87749d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515839256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.2515839256
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.3988282122
Short name T769
Test name
Test status
Simulation time 276716521 ps
CPU time 0.81 seconds
Started Aug 19 05:51:40 PM PDT 24
Finished Aug 19 05:51:41 PM PDT 24
Peak memory 199964 kb
Host smart-16166f8d-d086-4140-89d1-3ec17dfea38a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988282122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_
cm_ctrl_config_regwen.3988282122
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2391501556
Short name T576
Test name
Test status
Simulation time 828067201 ps
CPU time 2.47 seconds
Started Aug 19 05:51:41 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 201096 kb
Host smart-d3feb1d3-c17c-4977-bdfb-3e1542d6c87c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391501556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2391501556
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3722170754
Short name T868
Test name
Test status
Simulation time 868807636 ps
CPU time 3.38 seconds
Started Aug 19 05:51:56 PM PDT 24
Finished Aug 19 05:52:00 PM PDT 24
Peak memory 201132 kb
Host smart-fb1897c1-5622-40c9-b07f-07faf89167b2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722170754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3722170754
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3921673582
Short name T509
Test name
Test status
Simulation time 228970979 ps
CPU time 0.91 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 199404 kb
Host smart-80663cb7-a578-4495-a365-11581af65c94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921673582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3921673582
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.1565539303
Short name T814
Test name
Test status
Simulation time 52512560 ps
CPU time 0.63 seconds
Started Aug 19 05:51:57 PM PDT 24
Finished Aug 19 05:51:57 PM PDT 24
Peak memory 199412 kb
Host smart-a97d7484-5d2d-47ec-ba9c-0cd04a711c1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565539303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1565539303
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all.590288200
Short name T488
Test name
Test status
Simulation time 2561665274 ps
CPU time 2.84 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:51:54 PM PDT 24
Peak memory 201292 kb
Host smart-80004c03-de32-4e5d-9062-41d823d63d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590288200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.590288200
Directory /workspace/34.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.1767113785
Short name T51
Test name
Test status
Simulation time 6409465293 ps
CPU time 9.41 seconds
Started Aug 19 05:51:55 PM PDT 24
Finished Aug 19 05:52:04 PM PDT 24
Peak memory 201376 kb
Host smart-b486c176-ac59-4541-8962-4cb33c2e25df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767113785 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand_reset.1767113785
Directory /workspace/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup.1969393224
Short name T274
Test name
Test status
Simulation time 226815655 ps
CPU time 0.84 seconds
Started Aug 19 05:51:36 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 199780 kb
Host smart-36a0825a-69b8-4c98-a06a-dc76f693c816
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969393224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.1969393224
Directory /workspace/34.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.2333115234
Short name T510
Test name
Test status
Simulation time 471546797 ps
CPU time 1.18 seconds
Started Aug 19 05:51:43 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 200972 kb
Host smart-fce125c9-2f13-48db-ac2d-2e1c49fc4ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333115234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.2333115234
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.874150229
Short name T902
Test name
Test status
Simulation time 91276524 ps
CPU time 0.76 seconds
Started Aug 19 05:51:47 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 198936 kb
Host smart-451e1e64-2a64-4e5b-94bd-30e74d70c64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874150229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.874150229
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.1273435362
Short name T331
Test name
Test status
Simulation time 75481228 ps
CPU time 0.69 seconds
Started Aug 19 05:51:47 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 199124 kb
Host smart-3d2a7ff5-3363-468e-9769-52f07b4cbcb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273435362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.1273435362
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.715855405
Short name T372
Test name
Test status
Simulation time 29692294 ps
CPU time 0.61 seconds
Started Aug 19 05:51:47 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 197340 kb
Host smart-c41ae21b-5e6e-4812-b2c8-277b9397ed98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715855405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.715855405
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.80379233
Short name T748
Test name
Test status
Simulation time 270717128 ps
CPU time 0.8 seconds
Started Aug 19 05:51:53 PM PDT 24
Finished Aug 19 05:51:54 PM PDT 24
Peak memory 198136 kb
Host smart-09f6ff7b-010e-435c-8127-7aadf2125f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80379233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.80379233
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.3027244016
Short name T451
Test name
Test status
Simulation time 48480431 ps
CPU time 0.67 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:43 PM PDT 24
Peak memory 197316 kb
Host smart-b41e4fa7-54e4-43a5-9354-7ca76b55e5af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027244016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.3027244016
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.1084546991
Short name T669
Test name
Test status
Simulation time 36547252 ps
CPU time 0.65 seconds
Started Aug 19 05:51:45 PM PDT 24
Finished Aug 19 05:51:45 PM PDT 24
Peak memory 198084 kb
Host smart-1ded80a9-98ef-491d-bb5d-19d948b7b114
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084546991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1084546991
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.1085995267
Short name T336
Test name
Test status
Simulation time 55587394 ps
CPU time 0.67 seconds
Started Aug 19 05:52:01 PM PDT 24
Finished Aug 19 05:52:01 PM PDT 24
Peak memory 201320 kb
Host smart-a50b04a1-66e1-496d-a01b-4f57d1375f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085995267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.1085995267
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.1199300654
Short name T229
Test name
Test status
Simulation time 212910982 ps
CPU time 0.8 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 198572 kb
Host smart-cb69b2e2-6f91-4aa1-a7bf-aa071dc8a760
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199300654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.1199300654
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.3819995500
Short name T193
Test name
Test status
Simulation time 23025706 ps
CPU time 0.66 seconds
Started Aug 19 05:51:47 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 199200 kb
Host smart-5301da94-0252-45c8-a080-fc075f18da92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819995500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.3819995500
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.1262428259
Short name T954
Test name
Test status
Simulation time 106252853 ps
CPU time 0.94 seconds
Started Aug 19 05:51:45 PM PDT 24
Finished Aug 19 05:51:46 PM PDT 24
Peak memory 209284 kb
Host smart-f3459aea-5ac4-4512-a27f-ff16101b368b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262428259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.1262428259
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.2301501799
Short name T519
Test name
Test status
Simulation time 97204102 ps
CPU time 0.85 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:38 PM PDT 24
Peak memory 199192 kb
Host smart-03e0d4b9-95fa-4c6e-9c11-f8628c010e7c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301501799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.2301501799
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.215325420
Short name T858
Test name
Test status
Simulation time 1927462758 ps
CPU time 2.04 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:51 PM PDT 24
Peak memory 201060 kb
Host smart-b6971f32-3788-4bd8-a7ed-a2a17c52c16a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215325420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.215325420
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1811395312
Short name T326
Test name
Test status
Simulation time 815545450 ps
CPU time 2.92 seconds
Started Aug 19 05:51:50 PM PDT 24
Finished Aug 19 05:51:53 PM PDT 24
Peak memory 201012 kb
Host smart-e94fc18a-4175-49c2-8bd0-98c669d74730
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811395312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1811395312
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3975196770
Short name T194
Test name
Test status
Simulation time 99160645 ps
CPU time 0.8 seconds
Started Aug 19 05:51:59 PM PDT 24
Finished Aug 19 05:52:00 PM PDT 24
Peak memory 199112 kb
Host smart-44608288-eda8-4963-a1fb-8ee28846e29c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975196770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3975196770
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.2993081025
Short name T87
Test name
Test status
Simulation time 30337380 ps
CPU time 0.71 seconds
Started Aug 19 05:51:44 PM PDT 24
Finished Aug 19 05:51:45 PM PDT 24
Peak memory 198600 kb
Host smart-68d24c52-7c18-469d-aea2-886da5676613
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993081025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2993081025
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all.2420534579
Short name T851
Test name
Test status
Simulation time 108530153 ps
CPU time 0.74 seconds
Started Aug 19 05:54:49 PM PDT 24
Finished Aug 19 05:54:51 PM PDT 24
Peak memory 198800 kb
Host smart-919f1cd7-1a2b-4bfe-9c1f-3e7b20088c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420534579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.2420534579
Directory /workspace/35.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all_with_rand_reset.768636810
Short name T93
Test name
Test status
Simulation time 4075938041 ps
CPU time 6.03 seconds
Started Aug 19 05:51:54 PM PDT 24
Finished Aug 19 05:52:00 PM PDT 24
Peak memory 201368 kb
Host smart-0e4bce50-c061-4a1b-8dac-2343b02d34f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768636810 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all_with_rand_reset.768636810
Directory /workspace/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.1461391746
Short name T879
Test name
Test status
Simulation time 90901478 ps
CPU time 0.71 seconds
Started Aug 19 05:51:50 PM PDT 24
Finished Aug 19 05:51:50 PM PDT 24
Peak memory 198332 kb
Host smart-bd9ff115-cf74-4b9c-b9b9-c34e1ba48848
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461391746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.1461391746
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.1516709437
Short name T491
Test name
Test status
Simulation time 278305706 ps
CPU time 1.3 seconds
Started Aug 19 05:51:40 PM PDT 24
Finished Aug 19 05:51:42 PM PDT 24
Peak memory 200848 kb
Host smart-8d833f61-5b09-4b3b-b907-6e05850da15d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516709437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.1516709437
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.2429805800
Short name T445
Test name
Test status
Simulation time 20601654 ps
CPU time 0.64 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:49 PM PDT 24
Peak memory 198692 kb
Host smart-011e805b-02c7-44b6-9b64-026e2c0884cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429805800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2429805800
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2946253834
Short name T944
Test name
Test status
Simulation time 59516105 ps
CPU time 0.85 seconds
Started Aug 19 05:51:50 PM PDT 24
Finished Aug 19 05:51:51 PM PDT 24
Peak memory 199188 kb
Host smart-282c19fa-7b59-4284-b413-0b5f7054a4f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946253834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.2946253834
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.1080378467
Short name T240
Test name
Test status
Simulation time 36990499 ps
CPU time 0.61 seconds
Started Aug 19 05:52:23 PM PDT 24
Finished Aug 19 05:52:23 PM PDT 24
Peak memory 198076 kb
Host smart-915b11e6-13c6-4c51-87c5-d9fdd1c1d66d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080378467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.1080378467
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.2975751296
Short name T505
Test name
Test status
Simulation time 108220276 ps
CPU time 0.9 seconds
Started Aug 19 05:51:57 PM PDT 24
Finished Aug 19 05:51:58 PM PDT 24
Peak memory 198128 kb
Host smart-2cde5e54-3e3b-4438-a2d2-ed92c6f9d667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975751296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.2975751296
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.20826395
Short name T363
Test name
Test status
Simulation time 47774939 ps
CPU time 0.6 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 198088 kb
Host smart-0e8f4c94-4e57-4aed-911c-5aaacb334f15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20826395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.20826395
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.3807872380
Short name T681
Test name
Test status
Simulation time 72722752 ps
CPU time 0.68 seconds
Started Aug 19 05:51:52 PM PDT 24
Finished Aug 19 05:51:53 PM PDT 24
Peak memory 198096 kb
Host smart-1cb0df7f-d19e-4758-b873-110a3e14b7ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807872380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3807872380
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.3349347358
Short name T773
Test name
Test status
Simulation time 47020992 ps
CPU time 0.7 seconds
Started Aug 19 05:52:03 PM PDT 24
Finished Aug 19 05:52:04 PM PDT 24
Peak memory 201368 kb
Host smart-fff3faff-f839-40b5-a04f-e49ced6be581
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349347358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.3349347358
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.1796952501
Short name T598
Test name
Test status
Simulation time 294998896 ps
CPU time 1.33 seconds
Started Aug 19 05:52:02 PM PDT 24
Finished Aug 19 05:52:03 PM PDT 24
Peak memory 199608 kb
Host smart-dd1b7764-ad5e-4b49-88d0-9867bf63763d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796952501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_w
akeup_race.1796952501
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.2283975638
Short name T552
Test name
Test status
Simulation time 102748580 ps
CPU time 0.86 seconds
Started Aug 19 05:51:55 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 199944 kb
Host smart-30e75554-5c6f-42a7-9827-5ab8c33ff915
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283975638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2283975638
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.3278714372
Short name T657
Test name
Test status
Simulation time 118251170 ps
CPU time 0.82 seconds
Started Aug 19 05:52:04 PM PDT 24
Finished Aug 19 05:52:05 PM PDT 24
Peak memory 209404 kb
Host smart-ff25925a-4b0d-4164-98b0-0bebc929a2c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278714372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3278714372
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.3538778713
Short name T792
Test name
Test status
Simulation time 633299670 ps
CPU time 0.84 seconds
Started Aug 19 05:52:17 PM PDT 24
Finished Aug 19 05:52:18 PM PDT 24
Peak memory 200056 kb
Host smart-e6e1493c-8d2b-4f3a-b22d-c26231e896c7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538778713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_
cm_ctrl_config_regwen.3538778713
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4043146523
Short name T929
Test name
Test status
Simulation time 767770256 ps
CPU time 2.96 seconds
Started Aug 19 05:51:54 PM PDT 24
Finished Aug 19 05:51:57 PM PDT 24
Peak memory 201128 kb
Host smart-59736626-6517-49f7-ba0f-e3dfc1f9b9e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043146523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4043146523
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3767224470
Short name T934
Test name
Test status
Simulation time 826273911 ps
CPU time 2.77 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:51 PM PDT 24
Peak memory 201004 kb
Host smart-527f1c86-ccc5-49a8-8212-58712b971390
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767224470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3767224470
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1964020106
Short name T696
Test name
Test status
Simulation time 525509918 ps
CPU time 0.86 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:51:52 PM PDT 24
Peak memory 199636 kb
Host smart-9502a72f-bae6-4806-aa02-09dc4e942890
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964020106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1964020106
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.3136623672
Short name T578
Test name
Test status
Simulation time 29975709 ps
CPU time 0.7 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:50 PM PDT 24
Peak memory 199408 kb
Host smart-9f93dc3e-50ed-47be-be88-4a12df653e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136623672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3136623672
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.1438825923
Short name T311
Test name
Test status
Simulation time 2587777241 ps
CPU time 2.42 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:41 PM PDT 24
Peak memory 201280 kb
Host smart-995b190f-7d89-4b9c-a0d5-685eaa70ac64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438825923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.1438825923
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.1605766331
Short name T968
Test name
Test status
Simulation time 123665660 ps
CPU time 0.71 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:47 PM PDT 24
Peak memory 198348 kb
Host smart-2681dfff-1076-48af-ab2d-5351a116547c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605766331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.1605766331
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.2484990040
Short name T852
Test name
Test status
Simulation time 183471153 ps
CPU time 1.14 seconds
Started Aug 19 05:51:56 PM PDT 24
Finished Aug 19 05:51:57 PM PDT 24
Peak memory 200128 kb
Host smart-8f5ffc60-9a4c-4640-a803-6ef546c7fddc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484990040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.2484990040
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.1743268597
Short name T777
Test name
Test status
Simulation time 61069526 ps
CPU time 0.79 seconds
Started Aug 19 05:51:52 PM PDT 24
Finished Aug 19 05:51:53 PM PDT 24
Peak memory 200216 kb
Host smart-20c575ba-24ff-46f8-9612-db7b7e889980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743268597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.1743268597
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.3275673914
Short name T419
Test name
Test status
Simulation time 80492969 ps
CPU time 0.68 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:51:52 PM PDT 24
Peak memory 199148 kb
Host smart-68c7fff3-6801-4c42-9d9d-a7a31b3749e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275673914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.3275673914
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.1782734714
Short name T928
Test name
Test status
Simulation time 40271143 ps
CPU time 0.6 seconds
Started Aug 19 05:51:38 PM PDT 24
Finished Aug 19 05:51:39 PM PDT 24
Peak memory 197324 kb
Host smart-fb913a3c-4dd9-4239-ab25-0d8c0cc434a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782734714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.1782734714
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.1104378088
Short name T261
Test name
Test status
Simulation time 212588303 ps
CPU time 0.84 seconds
Started Aug 19 05:52:01 PM PDT 24
Finished Aug 19 05:52:02 PM PDT 24
Peak memory 198156 kb
Host smart-eb603a02-4f7b-424b-928e-03d7bda9dc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104378088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1104378088
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.1397937134
Short name T96
Test name
Test status
Simulation time 52118389 ps
CPU time 0.64 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:51:52 PM PDT 24
Peak memory 198096 kb
Host smart-e9027ff7-ac51-4cd3-9bbb-70a98355a042
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397937134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.1397937134
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.1122386306
Short name T973
Test name
Test status
Simulation time 30488197 ps
CPU time 0.61 seconds
Started Aug 19 05:51:57 PM PDT 24
Finished Aug 19 05:51:58 PM PDT 24
Peak memory 198088 kb
Host smart-c4617a20-8284-4347-9b36-6b1557cac5b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122386306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.1122386306
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.3146118929
Short name T268
Test name
Test status
Simulation time 203232443 ps
CPU time 0.63 seconds
Started Aug 19 05:51:54 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 201364 kb
Host smart-73fa33e3-36f9-4ceb-939a-1b6fc387db04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146118929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.3146118929
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.1629471825
Short name T805
Test name
Test status
Simulation time 723032395 ps
CPU time 0.81 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:50 PM PDT 24
Peak memory 198476 kb
Host smart-711227b5-a88f-496d-8715-3cf6bf3355ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629471825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_w
akeup_race.1629471825
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.2886599034
Short name T870
Test name
Test status
Simulation time 59642440 ps
CPU time 0.87 seconds
Started Aug 19 05:51:45 PM PDT 24
Finished Aug 19 05:51:46 PM PDT 24
Peak memory 199144 kb
Host smart-37e25c25-f8a5-4710-95c8-513b65d70323
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886599034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.2886599034
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.2871996245
Short name T651
Test name
Test status
Simulation time 321071916 ps
CPU time 0.8 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 209416 kb
Host smart-aeed7487-7c32-40fe-86fa-c76b285d704a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871996245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.2871996245
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3066280783
Short name T286
Test name
Test status
Simulation time 70568717 ps
CPU time 0.64 seconds
Started Aug 19 05:52:02 PM PDT 24
Finished Aug 19 05:52:03 PM PDT 24
Peak memory 198604 kb
Host smart-d476e0e5-3c1a-4698-81a9-ce650529a830
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066280783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_
cm_ctrl_config_regwen.3066280783
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1810900178
Short name T648
Test name
Test status
Simulation time 747573177 ps
CPU time 3.03 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:51 PM PDT 24
Peak memory 201116 kb
Host smart-858dc683-1af4-4384-88d9-73b076d38f10
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810900178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1810900178
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2037617054
Short name T761
Test name
Test status
Simulation time 1197821535 ps
CPU time 2.13 seconds
Started Aug 19 05:51:46 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 201080 kb
Host smart-9276e427-fce1-4ec7-b3f6-548457e83acf
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037617054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2037617054
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1065178454
Short name T654
Test name
Test status
Simulation time 179745928 ps
CPU time 0.91 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:49 PM PDT 24
Peak memory 199360 kb
Host smart-6bc7f463-7051-4527-851f-2919875756e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065178454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1065178454
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.3328579897
Short name T248
Test name
Test status
Simulation time 29174320 ps
CPU time 0.66 seconds
Started Aug 19 05:51:47 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 198612 kb
Host smart-20e1a723-2827-4e19-b1a7-3860bb0272d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328579897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.3328579897
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all.987718856
Short name T127
Test name
Test status
Simulation time 282429546 ps
CPU time 1.68 seconds
Started Aug 19 05:51:42 PM PDT 24
Finished Aug 19 05:51:44 PM PDT 24
Peak memory 201092 kb
Host smart-3faa28d2-9b7e-47a1-b307-7f8cca613ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987718856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.987718856
Directory /workspace/37.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all_with_rand_reset.1920118409
Short name T923
Test name
Test status
Simulation time 4486132926 ps
CPU time 6.95 seconds
Started Aug 19 05:51:48 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 201408 kb
Host smart-45679adb-b502-441e-8f8a-8fae52f48b5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920118409 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all_with_rand_reset.1920118409
Directory /workspace/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.3379552045
Short name T798
Test name
Test status
Simulation time 44692174 ps
CPU time 0.67 seconds
Started Aug 19 05:52:25 PM PDT 24
Finished Aug 19 05:52:25 PM PDT 24
Peak memory 198312 kb
Host smart-a858dcf0-089b-4e08-8502-ccf77d5d7852
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379552045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.3379552045
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.1941409106
Short name T757
Test name
Test status
Simulation time 163630398 ps
CPU time 0.77 seconds
Started Aug 19 05:51:51 PM PDT 24
Finished Aug 19 05:51:52 PM PDT 24
Peak memory 199404 kb
Host smart-d1b80840-0582-4f40-a827-bde2ac112b5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941409106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.1941409106
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.2742015768
Short name T361
Test name
Test status
Simulation time 141226343 ps
CPU time 0.67 seconds
Started Aug 19 05:51:58 PM PDT 24
Finished Aug 19 05:51:59 PM PDT 24
Peak memory 198692 kb
Host smart-e43f8685-66a6-41a1-b474-a425f94e84fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742015768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2742015768
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.4272272229
Short name T165
Test name
Test status
Simulation time 48943365 ps
CPU time 0.71 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:12 PM PDT 24
Peak memory 198748 kb
Host smart-0552e030-ccdb-4a56-a944-ffc08b570fc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272272229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.4272272229
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.923032203
Short name T791
Test name
Test status
Simulation time 37474309 ps
CPU time 0.58 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:50 PM PDT 24
Peak memory 197332 kb
Host smart-3fc91a13-f297-4398-b713-ac4806cb4548
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923032203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_
malfunc.923032203
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.3794002707
Short name T703
Test name
Test status
Simulation time 110565965 ps
CPU time 0.89 seconds
Started Aug 19 05:51:55 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 199148 kb
Host smart-116801bf-6440-496a-b79d-fcd31f4e8cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794002707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.3794002707
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.313082281
Short name T283
Test name
Test status
Simulation time 33470107 ps
CPU time 0.61 seconds
Started Aug 19 05:51:58 PM PDT 24
Finished Aug 19 05:51:59 PM PDT 24
Peak memory 198000 kb
Host smart-3dd5e32a-c8de-4d83-b5a0-31daa594a433
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313082281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.313082281
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3853544266
Short name T86
Test name
Test status
Simulation time 40171080 ps
CPU time 0.66 seconds
Started Aug 19 05:51:54 PM PDT 24
Finished Aug 19 05:51:54 PM PDT 24
Peak memory 198436 kb
Host smart-a7909d29-be24-4a5d-9a1e-134dee202389
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853544266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3853544266
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.2580145463
Short name T960
Test name
Test status
Simulation time 71753558 ps
CPU time 0.65 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 201320 kb
Host smart-ad41bb86-0f97-4baf-b209-413668733019
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580145463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.2580145463
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.841118419
Short name T789
Test name
Test status
Simulation time 97698725 ps
CPU time 0.78 seconds
Started Aug 19 05:52:05 PM PDT 24
Finished Aug 19 05:52:06 PM PDT 24
Peak memory 199172 kb
Host smart-3a49de5b-94db-425c-b16e-da7916b00079
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841118419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wa
keup_race.841118419
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.1512339593
Short name T652
Test name
Test status
Simulation time 64406521 ps
CPU time 0.7 seconds
Started Aug 19 05:52:03 PM PDT 24
Finished Aug 19 05:52:04 PM PDT 24
Peak memory 199108 kb
Host smart-14940f90-9086-4ebd-8f53-63f286a5708f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512339593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.1512339593
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.1874252813
Short name T619
Test name
Test status
Simulation time 98612427 ps
CPU time 0.92 seconds
Started Aug 19 05:52:07 PM PDT 24
Finished Aug 19 05:52:08 PM PDT 24
Peak memory 209512 kb
Host smart-c7560b75-16ae-48f0-8065-24320837234a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874252813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.1874252813
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2780048926
Short name T942
Test name
Test status
Simulation time 172690554 ps
CPU time 0.74 seconds
Started Aug 19 05:52:02 PM PDT 24
Finished Aug 19 05:52:03 PM PDT 24
Peak memory 198692 kb
Host smart-e5017647-242a-44da-bdd3-53d589326da0
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780048926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_
cm_ctrl_config_regwen.2780048926
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1845626932
Short name T31
Test name
Test status
Simulation time 1060654040 ps
CPU time 2.09 seconds
Started Aug 19 05:51:55 PM PDT 24
Finished Aug 19 05:52:03 PM PDT 24
Peak memory 201152 kb
Host smart-5c66acee-30bc-4764-a916-b6cba30211cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845626932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1845626932
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3171841635
Short name T464
Test name
Test status
Simulation time 891377506 ps
CPU time 2.21 seconds
Started Aug 19 05:51:57 PM PDT 24
Finished Aug 19 05:51:59 PM PDT 24
Peak memory 200948 kb
Host smart-6274b172-669b-46db-9e82-cf6ff988aa09
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171841635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3171841635
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3279068484
Short name T366
Test name
Test status
Simulation time 79990523 ps
CPU time 0.81 seconds
Started Aug 19 05:51:59 PM PDT 24
Finished Aug 19 05:52:00 PM PDT 24
Peak memory 199320 kb
Host smart-f7de93c8-bbc1-4522-8f1f-f67cb9a872ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279068484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3279068484
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.2486214141
Short name T664
Test name
Test status
Simulation time 28689653 ps
CPU time 0.67 seconds
Started Aug 19 05:51:54 PM PDT 24
Finished Aug 19 05:51:54 PM PDT 24
Peak memory 199412 kb
Host smart-afcbb82f-3172-4222-b547-6c294f7617d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486214141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.2486214141
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all.2250574853
Short name T315
Test name
Test status
Simulation time 2056342936 ps
CPU time 6.37 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:15 PM PDT 24
Peak memory 201140 kb
Host smart-7b688d9c-4d9e-46b5-894b-a3469966e0ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250574853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.2250574853
Directory /workspace/38.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.160610212
Short name T47
Test name
Test status
Simulation time 2284677896 ps
CPU time 8.98 seconds
Started Aug 19 05:51:55 PM PDT 24
Finished Aug 19 05:52:04 PM PDT 24
Peak memory 201220 kb
Host smart-0a4847af-136e-4447-a864-56e95ad8141e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160610212 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand_reset.160610212
Directory /workspace/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.1277215984
Short name T783
Test name
Test status
Simulation time 247589023 ps
CPU time 0.84 seconds
Started Aug 19 05:51:58 PM PDT 24
Finished Aug 19 05:51:59 PM PDT 24
Peak memory 199596 kb
Host smart-efd7f0ae-e8cd-414a-9280-60c698e76839
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277215984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.1277215984
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.1139198258
Short name T410
Test name
Test status
Simulation time 218482277 ps
CPU time 0.86 seconds
Started Aug 19 05:51:50 PM PDT 24
Finished Aug 19 05:51:51 PM PDT 24
Peak memory 199652 kb
Host smart-cdf0bda6-3226-42d3-8797-5d5b58203a9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139198258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.1139198258
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1620499928
Short name T264
Test name
Test status
Simulation time 48840335 ps
CPU time 0.76 seconds
Started Aug 19 05:52:10 PM PDT 24
Finished Aug 19 05:52:11 PM PDT 24
Peak memory 199204 kb
Host smart-b2fafdba-7bf1-4779-8052-a1f801461ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620499928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1620499928
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.3818927276
Short name T740
Test name
Test status
Simulation time 56004861 ps
CPU time 0.74 seconds
Started Aug 19 05:51:57 PM PDT 24
Finished Aug 19 05:51:57 PM PDT 24
Peak memory 199192 kb
Host smart-b747b8d5-5022-48e3-b1a8-cd1a20dfa627
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818927276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.3818927276
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.1804998937
Short name T559
Test name
Test status
Simulation time 29184640 ps
CPU time 0.63 seconds
Started Aug 19 05:51:56 PM PDT 24
Finished Aug 19 05:51:57 PM PDT 24
Peak memory 197964 kb
Host smart-efadcb8f-88e6-4133-ab31-3e856321921c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804998937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.1804998937
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.111165411
Short name T891
Test name
Test status
Simulation time 398366519 ps
CPU time 0.87 seconds
Started Aug 19 05:52:03 PM PDT 24
Finished Aug 19 05:52:04 PM PDT 24
Peak memory 198396 kb
Host smart-b142f19c-eb20-4dac-82d0-7340c5ce020a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111165411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.111165411
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.153765879
Short name T539
Test name
Test status
Simulation time 63875557 ps
CPU time 0.73 seconds
Started Aug 19 05:52:01 PM PDT 24
Finished Aug 19 05:52:02 PM PDT 24
Peak memory 198084 kb
Host smart-cec27fe4-18f4-4712-a8b9-0f5c50568a97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153765879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.153765879
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.2208635015
Short name T171
Test name
Test status
Simulation time 53323862 ps
CPU time 0.62 seconds
Started Aug 19 05:51:53 PM PDT 24
Finished Aug 19 05:51:54 PM PDT 24
Peak memory 198120 kb
Host smart-cfeb5dcf-ba38-4980-904e-a2d8e025737b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208635015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2208635015
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.3570729095
Short name T334
Test name
Test status
Simulation time 76430946 ps
CPU time 0.75 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:12 PM PDT 24
Peak memory 201472 kb
Host smart-fc00554b-4c36-4ec2-b293-77fd83821f5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570729095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.3570729095
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.3498906688
Short name T76
Test name
Test status
Simulation time 36961710 ps
CPU time 0.68 seconds
Started Aug 19 05:51:56 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 199132 kb
Host smart-6955757c-a516-4bd7-a358-df806f6ce7bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498906688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.3498906688
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.2305959257
Short name T37
Test name
Test status
Simulation time 39505007 ps
CPU time 0.72 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:09 PM PDT 24
Peak memory 199092 kb
Host smart-44950a0a-f854-4cc3-b2f5-601486f9b821
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305959257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.2305959257
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.477446279
Short name T865
Test name
Test status
Simulation time 103304629 ps
CPU time 1.13 seconds
Started Aug 19 05:52:04 PM PDT 24
Finished Aug 19 05:52:05 PM PDT 24
Peak memory 209432 kb
Host smart-1fe835d6-f254-404f-9c3e-da31b1b2e046
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477446279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.477446279
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.2702922765
Short name T963
Test name
Test status
Simulation time 324378492 ps
CPU time 1 seconds
Started Aug 19 05:52:00 PM PDT 24
Finished Aug 19 05:52:01 PM PDT 24
Peak memory 199912 kb
Host smart-cd9aecec-98dc-498c-a80e-6d64aa426c51
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702922765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_
cm_ctrl_config_regwen.2702922765
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1018815607
Short name T615
Test name
Test status
Simulation time 822479219 ps
CPU time 3.15 seconds
Started Aug 19 05:52:24 PM PDT 24
Finished Aug 19 05:52:27 PM PDT 24
Peak memory 201164 kb
Host smart-613f40ae-4345-41e0-8aa9-0eebce87e9cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018815607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1018815607
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3151989128
Short name T202
Test name
Test status
Simulation time 1003161072 ps
CPU time 2.85 seconds
Started Aug 19 05:51:58 PM PDT 24
Finished Aug 19 05:52:01 PM PDT 24
Peak memory 201140 kb
Host smart-04de6b0b-6f75-480b-baf4-4629cfd754fc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151989128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3151989128
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1686319269
Short name T300
Test name
Test status
Simulation time 74163289 ps
CPU time 0.93 seconds
Started Aug 19 05:52:01 PM PDT 24
Finished Aug 19 05:52:02 PM PDT 24
Peak memory 199240 kb
Host smart-54bba643-f924-42e1-948f-3da879dd0b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686319269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1686319269
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.2090517942
Short name T244
Test name
Test status
Simulation time 48360683 ps
CPU time 0.66 seconds
Started Aug 19 05:51:55 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 199400 kb
Host smart-dc43fb8e-e383-4e63-a41c-2f1f53bcb60c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090517942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.2090517942
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all.4070083352
Short name T20
Test name
Test status
Simulation time 289193596 ps
CPU time 1.17 seconds
Started Aug 19 05:51:57 PM PDT 24
Finished Aug 19 05:51:59 PM PDT 24
Peak memory 200936 kb
Host smart-d945cfe3-3330-4c3e-8eed-152b24ffee0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070083352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.4070083352
Directory /workspace/39.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.2826633044
Short name T521
Test name
Test status
Simulation time 5255749913 ps
CPU time 17.38 seconds
Started Aug 19 05:52:14 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 201368 kb
Host smart-d30a469d-d866-4ae8-b954-fac001add276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826633044 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand_reset.2826633044
Directory /workspace/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.2256039792
Short name T710
Test name
Test status
Simulation time 348960315 ps
CPU time 0.97 seconds
Started Aug 19 05:51:53 PM PDT 24
Finished Aug 19 05:51:54 PM PDT 24
Peak memory 199852 kb
Host smart-77c9fb19-0bc2-44f3-979c-56c889a5c0a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256039792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.2256039792
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.127772032
Short name T214
Test name
Test status
Simulation time 210736041 ps
CPU time 1.22 seconds
Started Aug 19 05:52:10 PM PDT 24
Finished Aug 19 05:52:11 PM PDT 24
Peak memory 200940 kb
Host smart-06a60a82-44d2-47ac-acb5-5b4ec48913c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127772032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.127772032
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.289564794
Short name T927
Test name
Test status
Simulation time 72757096 ps
CPU time 0.89 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:45 PM PDT 24
Peak memory 200296 kb
Host smart-21730c50-e7de-477d-bc9a-6f73db98f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289564794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.289564794
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.1206890044
Short name T146
Test name
Test status
Simulation time 95655824 ps
CPU time 0.75 seconds
Started Aug 19 05:50:34 PM PDT 24
Finished Aug 19 05:50:35 PM PDT 24
Peak memory 198816 kb
Host smart-eb19d6c9-3da8-4397-bd59-149b78d118be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206890044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.1206890044
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1098523628
Short name T136
Test name
Test status
Simulation time 28825473 ps
CPU time 0.63 seconds
Started Aug 19 05:50:25 PM PDT 24
Finished Aug 19 05:50:26 PM PDT 24
Peak memory 197924 kb
Host smart-731ccf70-22b2-4e40-a1ae-64ee4802e12a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098523628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1098523628
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.593930502
Short name T102
Test name
Test status
Simulation time 408137758 ps
CPU time 0.85 seconds
Started Aug 19 05:50:23 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 198140 kb
Host smart-aed5d62d-ebdc-4d33-9e5f-b5997d19093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593930502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.593930502
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.2824990876
Short name T16
Test name
Test status
Simulation time 46877626 ps
CPU time 0.69 seconds
Started Aug 19 05:50:41 PM PDT 24
Finished Aug 19 05:50:42 PM PDT 24
Peak memory 197332 kb
Host smart-fd3365f9-699c-4261-8600-b7a248bb1748
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824990876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.2824990876
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.1716681692
Short name T221
Test name
Test status
Simulation time 53349809 ps
CPU time 0.64 seconds
Started Aug 19 05:50:31 PM PDT 24
Finished Aug 19 05:50:32 PM PDT 24
Peak memory 198104 kb
Host smart-7c40ea5d-5c0b-46cf-ad13-b846da78f3f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716681692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.1716681692
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.636622799
Short name T889
Test name
Test status
Simulation time 83586775 ps
CPU time 0.68 seconds
Started Aug 19 05:50:21 PM PDT 24
Finished Aug 19 05:50:22 PM PDT 24
Peak memory 201364 kb
Host smart-b05e421e-7083-40a7-ac36-3c9a04ebffb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636622799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid
.636622799
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.3649138135
Short name T458
Test name
Test status
Simulation time 46919251 ps
CPU time 0.65 seconds
Started Aug 19 05:50:17 PM PDT 24
Finished Aug 19 05:50:18 PM PDT 24
Peak memory 199172 kb
Host smart-51f142c7-3f21-4417-9d33-2376cf71e9e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649138135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.3649138135
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.1398722106
Short name T825
Test name
Test status
Simulation time 70353459 ps
CPU time 0.7 seconds
Started Aug 19 05:50:18 PM PDT 24
Finished Aug 19 05:50:18 PM PDT 24
Peak memory 199220 kb
Host smart-bf6fc363-edb1-434d-bc2f-c537590fb024
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398722106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1398722106
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.293700449
Short name T487
Test name
Test status
Simulation time 150500126 ps
CPU time 0.87 seconds
Started Aug 19 05:50:21 PM PDT 24
Finished Aug 19 05:50:22 PM PDT 24
Peak memory 209432 kb
Host smart-0f877cbb-8490-48f6-933e-36a34fd4d2c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293700449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.293700449
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2502558864
Short name T27
Test name
Test status
Simulation time 891150292 ps
CPU time 1.57 seconds
Started Aug 19 05:50:30 PM PDT 24
Finished Aug 19 05:50:31 PM PDT 24
Peak memory 216572 kb
Host smart-e15fe047-6baf-4fa7-98eb-24394b90dbd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502558864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2502558864
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.2452526281
Short name T738
Test name
Test status
Simulation time 133266290 ps
CPU time 0.77 seconds
Started Aug 19 05:50:23 PM PDT 24
Finished Aug 19 05:50:23 PM PDT 24
Peak memory 199468 kb
Host smart-16da96a4-a2f1-4aea-bde7-47eb9ebafe4f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452526281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c
m_ctrl_config_regwen.2452526281
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3108689357
Short name T925
Test name
Test status
Simulation time 1230582735 ps
CPU time 2.27 seconds
Started Aug 19 05:50:21 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 201180 kb
Host smart-6210addf-c316-4db5-869a-e966b1b51440
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108689357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3108689357
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1210728264
Short name T731
Test name
Test status
Simulation time 956438440 ps
CPU time 3.4 seconds
Started Aug 19 05:50:38 PM PDT 24
Finished Aug 19 05:50:41 PM PDT 24
Peak memory 201120 kb
Host smart-9d691f33-db46-4768-b8d5-50798158bdb4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210728264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1210728264
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2051270528
Short name T992
Test name
Test status
Simulation time 49727751 ps
CPU time 0.9 seconds
Started Aug 19 05:50:21 PM PDT 24
Finished Aug 19 05:50:22 PM PDT 24
Peak memory 199320 kb
Host smart-188e315e-f1ba-41ab-83c8-74387d737065
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051270528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2051270528
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.3158155781
Short name T74
Test name
Test status
Simulation time 30724785 ps
CPU time 0.65 seconds
Started Aug 19 05:50:16 PM PDT 24
Finished Aug 19 05:50:17 PM PDT 24
Peak memory 197540 kb
Host smart-18039d9c-8b1f-4562-97e2-eb45c4218e6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158155781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.3158155781
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.2005736244
Short name T367
Test name
Test status
Simulation time 1425539971 ps
CPU time 2.29 seconds
Started Aug 19 05:50:22 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 201204 kb
Host smart-ec6075ba-aae6-40da-ac3e-785a54909293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005736244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.2005736244
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.3019525392
Short name T130
Test name
Test status
Simulation time 2030105424 ps
CPU time 8.05 seconds
Started Aug 19 05:50:26 PM PDT 24
Finished Aug 19 05:50:35 PM PDT 24
Peak memory 201276 kb
Host smart-f7535fef-c282-4f79-bae2-a65d3dfcc9fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019525392 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_reset.3019525392
Directory /workspace/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.2500988838
Short name T273
Test name
Test status
Simulation time 149843385 ps
CPU time 0.97 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:35 PM PDT 24
Peak memory 198588 kb
Host smart-498e392d-f599-44d6-b4e0-39cfbd9283e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500988838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.2500988838
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.2396394447
Short name T568
Test name
Test status
Simulation time 449147894 ps
CPU time 1.26 seconds
Started Aug 19 05:50:28 PM PDT 24
Finished Aug 19 05:50:30 PM PDT 24
Peak memory 200904 kb
Host smart-5aea099f-3f4d-4254-b1b2-c8b9448ff262
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396394447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.2396394447
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.136870190
Short name T106
Test name
Test status
Simulation time 40552178 ps
CPU time 0.85 seconds
Started Aug 19 05:52:08 PM PDT 24
Finished Aug 19 05:52:09 PM PDT 24
Peak memory 200220 kb
Host smart-a05169e7-4187-4216-9ff3-2a9e38717bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136870190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.136870190
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.1952925996
Short name T462
Test name
Test status
Simulation time 69752403 ps
CPU time 0.76 seconds
Started Aug 19 05:52:12 PM PDT 24
Finished Aug 19 05:52:13 PM PDT 24
Peak memory 199088 kb
Host smart-9361e3fc-fe6c-4cad-a1bd-13ca91e84853
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952925996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.1952925996
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.845745452
Short name T11
Test name
Test status
Simulation time 40586428 ps
CPU time 0.59 seconds
Started Aug 19 05:52:04 PM PDT 24
Finished Aug 19 05:52:05 PM PDT 24
Peak memory 198152 kb
Host smart-44a03cb1-42ae-4fb0-83a3-a567f44786b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845745452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_
malfunc.845745452
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.722673936
Short name T813
Test name
Test status
Simulation time 381014256 ps
CPU time 0.82 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 198116 kb
Host smart-861ff4f4-c7e1-448a-a1a8-146233d16161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722673936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.722673936
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.4282860000
Short name T706
Test name
Test status
Simulation time 47354582 ps
CPU time 0.66 seconds
Started Aug 19 05:51:56 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 197276 kb
Host smart-1e07ccc5-af1f-4e13-9068-e52eb5d5b2fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282860000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.4282860000
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.714819298
Short name T938
Test name
Test status
Simulation time 50720652 ps
CPU time 0.61 seconds
Started Aug 19 05:51:55 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 198120 kb
Host smart-c927d5b7-6a28-4ac3-bb89-de4a1afee2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714819298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.714819298
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.1616927993
Short name T299
Test name
Test status
Simulation time 44180624 ps
CPU time 0.75 seconds
Started Aug 19 05:52:08 PM PDT 24
Finished Aug 19 05:52:09 PM PDT 24
Peak memory 201324 kb
Host smart-777f91ec-e890-48f1-b172-19709e67792e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616927993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.1616927993
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.1487472458
Short name T177
Test name
Test status
Simulation time 347603995 ps
CPU time 0.89 seconds
Started Aug 19 05:52:20 PM PDT 24
Finished Aug 19 05:52:21 PM PDT 24
Peak memory 199732 kb
Host smart-11596718-64a6-4e92-9aec-d55fffa6aeff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487472458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.1487472458
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.3884577729
Short name T523
Test name
Test status
Simulation time 39638790 ps
CPU time 0.81 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 199220 kb
Host smart-222e1a3a-753c-40be-b9bd-60c21d431f72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884577729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3884577729
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.3417078626
Short name T84
Test name
Test status
Simulation time 159668796 ps
CPU time 0.75 seconds
Started Aug 19 05:52:03 PM PDT 24
Finished Aug 19 05:52:04 PM PDT 24
Peak memory 209360 kb
Host smart-f9f71af3-b4c7-4fa5-92bd-dc886841b8a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417078626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.3417078626
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.3883956959
Short name T597
Test name
Test status
Simulation time 71985241 ps
CPU time 0.86 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 199832 kb
Host smart-42fcdf87-7590-45c0-9738-56c1d2dc78bc
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883956959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_
cm_ctrl_config_regwen.3883956959
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3350766274
Short name T149
Test name
Test status
Simulation time 831035304 ps
CPU time 2.86 seconds
Started Aug 19 05:52:18 PM PDT 24
Finished Aug 19 05:52:21 PM PDT 24
Peak memory 201168 kb
Host smart-8e15ee00-eb10-4060-91b6-12324f3d1024
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350766274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3350766274
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3186618089
Short name T483
Test name
Test status
Simulation time 883362659 ps
CPU time 2.26 seconds
Started Aug 19 05:52:13 PM PDT 24
Finished Aug 19 05:52:16 PM PDT 24
Peak memory 201240 kb
Host smart-19ee12a6-3a25-4825-b003-1e6fac75ec97
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186618089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3186618089
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.3608696046
Short name T913
Test name
Test status
Simulation time 64325409 ps
CPU time 0.86 seconds
Started Aug 19 05:52:05 PM PDT 24
Finished Aug 19 05:52:06 PM PDT 24
Peak memory 199684 kb
Host smart-779f0773-21f2-4957-b4e4-d7a7f41d32e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608696046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3608696046
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.49400374
Short name T707
Test name
Test status
Simulation time 33238352 ps
CPU time 0.65 seconds
Started Aug 19 05:51:54 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 199232 kb
Host smart-35ce75a7-52b0-4357-b7ad-4e0923bf8847
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49400374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.49400374
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.3663935952
Short name T470
Test name
Test status
Simulation time 1656786650 ps
CPU time 2.72 seconds
Started Aug 19 05:51:58 PM PDT 24
Finished Aug 19 05:52:01 PM PDT 24
Peak memory 201224 kb
Host smart-5f6a94bc-9d53-48e2-9a37-542e8bca9bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663935952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.3663935952
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all_with_rand_reset.4248132201
Short name T98
Test name
Test status
Simulation time 2176761280 ps
CPU time 7.5 seconds
Started Aug 19 05:51:59 PM PDT 24
Finished Aug 19 05:52:07 PM PDT 24
Peak memory 201408 kb
Host smart-8aea494f-d463-4d81-a993-3288f9a1d4eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248132201 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand_reset.4248132201
Directory /workspace/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.60141824
Short name T353
Test name
Test status
Simulation time 267216385 ps
CPU time 0.89 seconds
Started Aug 19 05:52:06 PM PDT 24
Finished Aug 19 05:52:07 PM PDT 24
Peak memory 199872 kb
Host smart-172bdce9-92cc-4f0c-94b5-6e462e578522
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60141824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.60141824
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.858357731
Short name T471
Test name
Test status
Simulation time 792960345 ps
CPU time 1.05 seconds
Started Aug 19 05:52:08 PM PDT 24
Finished Aug 19 05:52:09 PM PDT 24
Peak memory 201008 kb
Host smart-912b7cf4-741d-49cc-8c28-0a0282858749
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858357731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.858357731
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.3191291155
Short name T312
Test name
Test status
Simulation time 79320044 ps
CPU time 0.96 seconds
Started Aug 19 05:52:21 PM PDT 24
Finished Aug 19 05:52:22 PM PDT 24
Peak memory 200792 kb
Host smart-4a2018b2-67fb-40d4-8cb4-fcae8ed00714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191291155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.3191291155
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.1818983394
Short name T298
Test name
Test status
Simulation time 55418301 ps
CPU time 0.84 seconds
Started Aug 19 05:52:02 PM PDT 24
Finished Aug 19 05:52:02 PM PDT 24
Peak memory 199368 kb
Host smart-45fd5690-6940-4137-b233-a17772387fed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818983394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.1818983394
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.888431244
Short name T984
Test name
Test status
Simulation time 31109200 ps
CPU time 0.64 seconds
Started Aug 19 05:52:03 PM PDT 24
Finished Aug 19 05:52:04 PM PDT 24
Peak memory 197228 kb
Host smart-101b7a4e-9999-43af-921a-bf4859bdbfc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888431244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_
malfunc.888431244
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.2683551962
Short name T382
Test name
Test status
Simulation time 206961080 ps
CPU time 0.85 seconds
Started Aug 19 05:51:49 PM PDT 24
Finished Aug 19 05:51:50 PM PDT 24
Peak memory 198160 kb
Host smart-9929a20a-c7f5-4d62-9c3d-03829e14daf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683551962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2683551962
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.1279190267
Short name T181
Test name
Test status
Simulation time 32694016 ps
CPU time 0.63 seconds
Started Aug 19 05:52:06 PM PDT 24
Finished Aug 19 05:52:06 PM PDT 24
Peak memory 198156 kb
Host smart-7bea5420-7fef-4353-8ca7-5b600f8699fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279190267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.1279190267
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.3035490712
Short name T612
Test name
Test status
Simulation time 77209720 ps
CPU time 0.62 seconds
Started Aug 19 05:52:08 PM PDT 24
Finished Aug 19 05:52:09 PM PDT 24
Peak memory 198064 kb
Host smart-594bf163-71bb-4ab4-81eb-f1908c1ae3a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035490712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.3035490712
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.990709388
Short name T461
Test name
Test status
Simulation time 116863141 ps
CPU time 0.67 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 201308 kb
Host smart-e6d5d975-7cbc-4c86-9e3e-63d52c2cf13c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990709388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invali
d.990709388
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.2846575046
Short name T319
Test name
Test status
Simulation time 220697876 ps
CPU time 1.13 seconds
Started Aug 19 05:51:50 PM PDT 24
Finished Aug 19 05:51:51 PM PDT 24
Peak memory 199752 kb
Host smart-6af19aa7-cc23-4686-b5e9-4217a9444e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846575046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_w
akeup_race.2846575046
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.803798445
Short name T222
Test name
Test status
Simulation time 64859578 ps
CPU time 0.69 seconds
Started Aug 19 05:52:24 PM PDT 24
Finished Aug 19 05:52:25 PM PDT 24
Peak memory 199208 kb
Host smart-9561863f-bb7f-47b3-b4a8-d8c234d63fd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803798445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.803798445
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1224841297
Short name T911
Test name
Test status
Simulation time 102145338 ps
CPU time 1.05 seconds
Started Aug 19 05:52:07 PM PDT 24
Finished Aug 19 05:52:08 PM PDT 24
Peak memory 209476 kb
Host smart-1217c90c-c3eb-4ede-b97e-593df7d3b6b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224841297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1224841297
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.729796564
Short name T662
Test name
Test status
Simulation time 243961142 ps
CPU time 1.2 seconds
Started Aug 19 05:52:00 PM PDT 24
Finished Aug 19 05:52:01 PM PDT 24
Peak memory 199928 kb
Host smart-4c9868b6-1be2-4acc-ae88-fe213d566498
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729796564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_c
m_ctrl_config_regwen.729796564
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.430976138
Short name T406
Test name
Test status
Simulation time 999314881 ps
CPU time 2.69 seconds
Started Aug 19 05:52:08 PM PDT 24
Finished Aug 19 05:52:11 PM PDT 24
Peak memory 201000 kb
Host smart-55b14fb8-0b11-4f60-898d-e1d7951cc40e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430976138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.430976138
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4158223172
Short name T347
Test name
Test status
Simulation time 917569469 ps
CPU time 2.04 seconds
Started Aug 19 05:52:13 PM PDT 24
Finished Aug 19 05:52:15 PM PDT 24
Peak memory 201088 kb
Host smart-8faf01ac-7fea-4ed7-be3a-af095db8db14
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158223172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4158223172
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1037628902
Short name T381
Test name
Test status
Simulation time 108501738 ps
CPU time 0.88 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 199284 kb
Host smart-949166ff-f5e0-4714-bf59-aa9b4ce3a245
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037628902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1037628902
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.738016821
Short name T871
Test name
Test status
Simulation time 29149743 ps
CPU time 0.71 seconds
Started Aug 19 05:52:01 PM PDT 24
Finished Aug 19 05:52:02 PM PDT 24
Peak memory 198516 kb
Host smart-97f70956-3ef9-4dc6-bdfe-2a5f10c9a474
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738016821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.738016821
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.1210697366
Short name T13
Test name
Test status
Simulation time 1363013394 ps
CPU time 2.74 seconds
Started Aug 19 05:51:52 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 201140 kb
Host smart-96bedbd5-a1ac-438a-84dd-40c4f91dc39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210697366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.1210697366
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.1085159458
Short name T941
Test name
Test status
Simulation time 274504988 ps
CPU time 0.84 seconds
Started Aug 19 05:52:16 PM PDT 24
Finished Aug 19 05:52:17 PM PDT 24
Peak memory 198576 kb
Host smart-36f76331-3db0-4249-bcef-d6ed080cc85e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085159458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.1085159458
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.3920280012
Short name T961
Test name
Test status
Simulation time 91510706 ps
CPU time 0.72 seconds
Started Aug 19 05:52:08 PM PDT 24
Finished Aug 19 05:52:09 PM PDT 24
Peak memory 199336 kb
Host smart-34f1a5b7-c372-465c-abc0-0debbd23ffb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920280012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.3920280012
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.1440620329
Short name T481
Test name
Test status
Simulation time 26831882 ps
CPU time 0.67 seconds
Started Aug 19 05:51:54 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 199216 kb
Host smart-ce6e70c9-e74c-4180-8d24-52329e7c420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440620329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.1440620329
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.416620905
Short name T642
Test name
Test status
Simulation time 69646211 ps
CPU time 0.92 seconds
Started Aug 19 05:52:06 PM PDT 24
Finished Aug 19 05:52:07 PM PDT 24
Peak memory 199472 kb
Host smart-090b6aa5-ee7b-4c4e-afb0-abd0b41f959d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416620905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disa
ble_rom_integrity_check.416620905
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.400350183
Short name T280
Test name
Test status
Simulation time 31234501 ps
CPU time 0.58 seconds
Started Aug 19 05:52:00 PM PDT 24
Finished Aug 19 05:52:01 PM PDT 24
Peak memory 197232 kb
Host smart-3bba8518-fc36-48d7-9ac7-ad192226a193
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400350183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_
malfunc.400350183
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.3889968375
Short name T230
Test name
Test status
Simulation time 1310371954 ps
CPU time 0.8 seconds
Started Aug 19 05:52:04 PM PDT 24
Finished Aug 19 05:52:05 PM PDT 24
Peak memory 198092 kb
Host smart-794bbdad-a37e-40d3-808e-3ef738d15ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889968375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.3889968375
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.1563248280
Short name T760
Test name
Test status
Simulation time 77717449 ps
CPU time 0.61 seconds
Started Aug 19 05:52:14 PM PDT 24
Finished Aug 19 05:52:15 PM PDT 24
Peak memory 197368 kb
Host smart-6776faab-705a-4f36-ac41-fab51cbb68da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563248280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.1563248280
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.3788483948
Short name T387
Test name
Test status
Simulation time 91727238 ps
CPU time 0.63 seconds
Started Aug 19 05:52:10 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 198404 kb
Host smart-9bff7f85-22f1-44c2-aeb8-4a6e21072250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788483948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.3788483948
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.2090911736
Short name T724
Test name
Test status
Simulation time 83859832 ps
CPU time 0.69 seconds
Started Aug 19 05:52:13 PM PDT 24
Finished Aug 19 05:52:14 PM PDT 24
Peak memory 201312 kb
Host smart-54ab4c37-c5cd-434d-9300-b3a1598b8a9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090911736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.2090911736
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.2546482344
Short name T526
Test name
Test status
Simulation time 223629993 ps
CPU time 0.99 seconds
Started Aug 19 05:52:08 PM PDT 24
Finished Aug 19 05:52:09 PM PDT 24
Peak memory 199504 kb
Host smart-4beadf7b-6b11-4997-8104-63cd74fedf13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546482344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_w
akeup_race.2546482344
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.3767782644
Short name T951
Test name
Test status
Simulation time 73075581 ps
CPU time 0.94 seconds
Started Aug 19 05:52:04 PM PDT 24
Finished Aug 19 05:52:05 PM PDT 24
Peak memory 199096 kb
Host smart-fffb631e-c3bd-4c3b-841b-41753ce6902b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767782644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3767782644
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.2555577279
Short name T328
Test name
Test status
Simulation time 162286594 ps
CPU time 0.78 seconds
Started Aug 19 05:52:07 PM PDT 24
Finished Aug 19 05:52:07 PM PDT 24
Peak memory 209372 kb
Host smart-b7de2422-aae8-47a8-9300-52430e2d48a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555577279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.2555577279
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1514350657
Short name T626
Test name
Test status
Simulation time 267530693 ps
CPU time 0.72 seconds
Started Aug 19 05:52:26 PM PDT 24
Finished Aug 19 05:52:27 PM PDT 24
Peak memory 198696 kb
Host smart-0f12e37d-7d46-4152-a7cb-fdd65986d621
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514350657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.1514350657
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.152383613
Short name T520
Test name
Test status
Simulation time 905933045 ps
CPU time 2.5 seconds
Started Aug 19 05:52:06 PM PDT 24
Finished Aug 19 05:52:08 PM PDT 24
Peak memory 201160 kb
Host smart-8a431516-5b40-4861-a05c-7321b14a5451
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152383613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.152383613
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2118310784
Short name T182
Test name
Test status
Simulation time 1095030876 ps
CPU time 2.66 seconds
Started Aug 19 05:52:19 PM PDT 24
Finished Aug 19 05:52:21 PM PDT 24
Peak memory 201116 kb
Host smart-8c844ca3-bf60-4376-8cd8-ca76d851016a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118310784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2118310784
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2364463168
Short name T888
Test name
Test status
Simulation time 79587350 ps
CPU time 0.86 seconds
Started Aug 19 05:52:21 PM PDT 24
Finished Aug 19 05:52:22 PM PDT 24
Peak memory 199504 kb
Host smart-a3b8311b-c186-421a-80d6-fa839d155ba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364463168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2364463168
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.744802347
Short name T233
Test name
Test status
Simulation time 29783533 ps
CPU time 0.65 seconds
Started Aug 19 05:52:10 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 199360 kb
Host smart-2b8cd142-b53e-452f-8759-a1d62b2959e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744802347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.744802347
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.2499219868
Short name T196
Test name
Test status
Simulation time 273037622 ps
CPU time 0.9 seconds
Started Aug 19 05:52:17 PM PDT 24
Finished Aug 19 05:52:18 PM PDT 24
Peak memory 200772 kb
Host smart-a21b674a-ce61-4ee3-b0df-203491b293ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499219868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.2499219868
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1416652202
Short name T66
Test name
Test status
Simulation time 3109979839 ps
CPU time 8.06 seconds
Started Aug 19 05:52:05 PM PDT 24
Finished Aug 19 05:52:13 PM PDT 24
Peak memory 201412 kb
Host smart-8c09d721-66b5-40e3-b267-3fb9b783b358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416652202 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all_with_rand_reset.1416652202
Directory /workspace/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.3916192992
Short name T416
Test name
Test status
Simulation time 185684447 ps
CPU time 1.07 seconds
Started Aug 19 05:51:58 PM PDT 24
Finished Aug 19 05:51:59 PM PDT 24
Peak memory 199552 kb
Host smart-b7a6efda-ef92-4061-ade0-fe41534c89c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916192992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.3916192992
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.1700348355
Short name T466
Test name
Test status
Simulation time 497444689 ps
CPU time 1.26 seconds
Started Aug 19 05:52:23 PM PDT 24
Finished Aug 19 05:52:24 PM PDT 24
Peak memory 200844 kb
Host smart-ff32a813-2f6a-451e-913d-718f57405c30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700348355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.1700348355
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.2124115267
Short name T500
Test name
Test status
Simulation time 25608367 ps
CPU time 0.7 seconds
Started Aug 19 05:52:04 PM PDT 24
Finished Aug 19 05:52:05 PM PDT 24
Peak memory 198768 kb
Host smart-8aaeccd7-c1cb-4d29-ad3b-f09b7a5d4145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124115267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2124115267
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.2972765720
Short name T756
Test name
Test status
Simulation time 55923578 ps
CPU time 0.73 seconds
Started Aug 19 05:52:04 PM PDT 24
Finished Aug 19 05:52:05 PM PDT 24
Peak memory 199200 kb
Host smart-dfd3befc-db9d-4cd2-81a4-3aca82521bd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972765720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.2972765720
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3961360417
Short name T33
Test name
Test status
Simulation time 39946020 ps
CPU time 0.61 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 198056 kb
Host smart-17196a53-1c9c-49cc-97e3-c7e4813a9765
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961360417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3961360417
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.3006863704
Short name T392
Test name
Test status
Simulation time 598305340 ps
CPU time 0.8 seconds
Started Aug 19 05:52:23 PM PDT 24
Finished Aug 19 05:52:24 PM PDT 24
Peak memory 198044 kb
Host smart-c7ff181a-c5dd-40df-be2e-16f0caeca1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006863704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.3006863704
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.1600037344
Short name T378
Test name
Test status
Simulation time 36091975 ps
CPU time 0.7 seconds
Started Aug 19 05:52:02 PM PDT 24
Finished Aug 19 05:52:03 PM PDT 24
Peak memory 198080 kb
Host smart-7599d0ff-bf11-4f1e-99c1-3b40a3f5c037
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600037344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.1600037344
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.2931108631
Short name T303
Test name
Test status
Simulation time 117137885 ps
CPU time 0.63 seconds
Started Aug 19 05:52:15 PM PDT 24
Finished Aug 19 05:52:15 PM PDT 24
Peak memory 198100 kb
Host smart-ff42068f-18ac-46d9-9817-a932e5279d20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931108631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.2931108631
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.376643856
Short name T29
Test name
Test status
Simulation time 45838312 ps
CPU time 0.73 seconds
Started Aug 19 05:52:22 PM PDT 24
Finished Aug 19 05:52:22 PM PDT 24
Peak memory 201304 kb
Host smart-e05d7778-dd11-4b96-8903-e622c6dcf624
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376643856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invali
d.376643856
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.3982776443
Short name T408
Test name
Test status
Simulation time 163534821 ps
CPU time 0.99 seconds
Started Aug 19 05:52:05 PM PDT 24
Finished Aug 19 05:52:06 PM PDT 24
Peak memory 198668 kb
Host smart-63e1fe19-6937-46b0-acb9-edcd1b4ab76e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982776443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_w
akeup_race.3982776443
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1388069013
Short name T863
Test name
Test status
Simulation time 73921832 ps
CPU time 0.99 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:12 PM PDT 24
Peak memory 199964 kb
Host smart-b7cae145-ef23-4a07-8b45-0d4f699d9154
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388069013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1388069013
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.2421855983
Short name T35
Test name
Test status
Simulation time 155828113 ps
CPU time 0.83 seconds
Started Aug 19 05:52:06 PM PDT 24
Finished Aug 19 05:52:07 PM PDT 24
Peak memory 209396 kb
Host smart-5b4fbd76-8bcb-41de-8b32-cb958ebc13ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421855983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.2421855983
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.2266565327
Short name T360
Test name
Test status
Simulation time 64963962 ps
CPU time 0.75 seconds
Started Aug 19 05:52:17 PM PDT 24
Finished Aug 19 05:52:17 PM PDT 24
Peak memory 199184 kb
Host smart-1c2d5d6f-77b0-4168-8c11-e0a5a236c37a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266565327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.2266565327
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3891103726
Short name T577
Test name
Test status
Simulation time 872328180 ps
CPU time 3.3 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:15 PM PDT 24
Peak memory 201056 kb
Host smart-bee9224b-eb39-48b0-9a8a-72d63f55ad7c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891103726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3891103726
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3380221872
Short name T210
Test name
Test status
Simulation time 2533186313 ps
CPU time 2.12 seconds
Started Aug 19 05:52:14 PM PDT 24
Finished Aug 19 05:52:17 PM PDT 24
Peak memory 201112 kb
Host smart-53a90878-3288-4e60-a45e-5f5fa8463e59
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380221872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3380221872
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3436111537
Short name T399
Test name
Test status
Simulation time 141765011 ps
CPU time 0.87 seconds
Started Aug 19 05:52:19 PM PDT 24
Finished Aug 19 05:52:20 PM PDT 24
Peak memory 199296 kb
Host smart-fa655f78-a83b-446e-a417-b33e0db3f2c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436111537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3436111537
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.1733461944
Short name T665
Test name
Test status
Simulation time 28161931 ps
CPU time 0.7 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:28 PM PDT 24
Peak memory 199404 kb
Host smart-ff6b8323-8814-4d42-8dd7-00837e87500a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733461944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1733461944
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all.2097086031
Short name T917
Test name
Test status
Simulation time 4345554696 ps
CPU time 3.08 seconds
Started Aug 19 05:52:07 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 201288 kb
Host smart-3397f11c-0265-4b57-a92f-5e6e0d6398a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097086031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2097086031
Directory /workspace/43.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all_with_rand_reset.1253050316
Short name T83
Test name
Test status
Simulation time 4176265574 ps
CPU time 14.69 seconds
Started Aug 19 05:52:07 PM PDT 24
Finished Aug 19 05:52:22 PM PDT 24
Peak memory 201340 kb
Host smart-7a473426-c618-4db4-ab3f-d97ccee9e418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253050316 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all_with_rand_reset.1253050316
Directory /workspace/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.2757494302
Short name T970
Test name
Test status
Simulation time 88537334 ps
CPU time 0.83 seconds
Started Aug 19 05:52:14 PM PDT 24
Finished Aug 19 05:52:15 PM PDT 24
Peak memory 199172 kb
Host smart-c0855573-48fe-482a-8a75-7a3ceacdd8c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757494302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.2757494302
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.3600174273
Short name T758
Test name
Test status
Simulation time 465609834 ps
CPU time 1.37 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:28 PM PDT 24
Peak memory 201020 kb
Host smart-8460694f-1040-4fe1-ac3b-f63c287b0d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600174273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.3600174273
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.2767445862
Short name T304
Test name
Test status
Simulation time 70188319 ps
CPU time 0.76 seconds
Started Aug 19 05:52:07 PM PDT 24
Finished Aug 19 05:52:08 PM PDT 24
Peak memory 199860 kb
Host smart-84a9abff-7cfe-4dd7-bd40-cc3cd4422a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767445862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.2767445862
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2828937904
Short name T485
Test name
Test status
Simulation time 56470618 ps
CPU time 0.87 seconds
Started Aug 19 05:52:18 PM PDT 24
Finished Aug 19 05:52:19 PM PDT 24
Peak memory 199224 kb
Host smart-8657963e-b152-4c79-b109-ba9c4ef32c8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828937904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2828937904
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3932388761
Short name T784
Test name
Test status
Simulation time 31105444 ps
CPU time 0.64 seconds
Started Aug 19 05:52:08 PM PDT 24
Finished Aug 19 05:52:08 PM PDT 24
Peak memory 197968 kb
Host smart-58645fbf-21d3-4a8f-9cb5-3fde7c94514c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932388761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.3932388761
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.305176112
Short name T656
Test name
Test status
Simulation time 113278840 ps
CPU time 0.85 seconds
Started Aug 19 05:52:04 PM PDT 24
Finished Aug 19 05:52:05 PM PDT 24
Peak memory 199188 kb
Host smart-1ac9b0c7-5cca-4f86-b0f7-3e452325ec25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305176112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.305176112
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.3796580437
Short name T803
Test name
Test status
Simulation time 75115938 ps
CPU time 0.65 seconds
Started Aug 19 05:52:22 PM PDT 24
Finished Aug 19 05:52:23 PM PDT 24
Peak memory 197380 kb
Host smart-8f36211d-30ea-4dba-9065-8402df27a717
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796580437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.3796580437
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.1819820106
Short name T698
Test name
Test status
Simulation time 94215377 ps
CPU time 0.64 seconds
Started Aug 19 05:52:23 PM PDT 24
Finished Aug 19 05:52:24 PM PDT 24
Peak memory 198112 kb
Host smart-c154ccc8-46ed-4027-b189-c56f43725be1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819820106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1819820106
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.4117048876
Short name T637
Test name
Test status
Simulation time 91259963 ps
CPU time 0.69 seconds
Started Aug 19 05:52:15 PM PDT 24
Finished Aug 19 05:52:16 PM PDT 24
Peak memory 201324 kb
Host smart-8d36ffbd-1d01-4188-801f-0e925cb4f357
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117048876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.4117048876
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.3339117644
Short name T772
Test name
Test status
Simulation time 370463702 ps
CPU time 0.99 seconds
Started Aug 19 05:52:06 PM PDT 24
Finished Aug 19 05:52:07 PM PDT 24
Peak memory 199916 kb
Host smart-f7896cb9-3ea5-49f3-bf7b-0ee3830e06b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339117644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_w
akeup_race.3339117644
Directory /workspace/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.3494583569
Short name T249
Test name
Test status
Simulation time 107035844 ps
CPU time 0.92 seconds
Started Aug 19 05:52:18 PM PDT 24
Finished Aug 19 05:52:19 PM PDT 24
Peak memory 199932 kb
Host smart-b6c0d11d-73cc-4366-82a5-c8fcc9a60490
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494583569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.3494583569
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.2524936924
Short name T663
Test name
Test status
Simulation time 117553308 ps
CPU time 0.83 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:29 PM PDT 24
Peak memory 209388 kb
Host smart-5217a789-d0fa-4376-8606-b30936eba927
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524936924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.2524936924
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.1589322339
Short name T549
Test name
Test status
Simulation time 38993064 ps
CPU time 0.72 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:11 PM PDT 24
Peak memory 199132 kb
Host smart-9ce616b4-0124-4f86-a48e-d86b5eb1b498
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589322339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.1589322339
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1813787542
Short name T148
Test name
Test status
Simulation time 821425025 ps
CPU time 3.12 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:13 PM PDT 24
Peak memory 201032 kb
Host smart-bd98b229-d46c-4cba-b06b-aebfb1260e30
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813787542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1813787542
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.173575946
Short name T763
Test name
Test status
Simulation time 976398948 ps
CPU time 2.56 seconds
Started Aug 19 05:52:01 PM PDT 24
Finished Aug 19 05:52:04 PM PDT 24
Peak memory 201076 kb
Host smart-b82a5dbf-5fee-4052-972c-6d2bbec79f34
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173575946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.173575946
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2316471785
Short name T188
Test name
Test status
Simulation time 54259615 ps
CPU time 0.85 seconds
Started Aug 19 05:52:13 PM PDT 24
Finished Aug 19 05:52:14 PM PDT 24
Peak memory 199276 kb
Host smart-bd689439-9efb-4873-b35c-c7115103aff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316471785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2316471785
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1854974764
Short name T301
Test name
Test status
Simulation time 30345140 ps
CPU time 0.68 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:12 PM PDT 24
Peak memory 198540 kb
Host smart-83c24ad4-5f1a-4b3d-8316-cb9b8787384b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854974764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1854974764
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all.701963753
Short name T402
Test name
Test status
Simulation time 1432614067 ps
CPU time 2.88 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 201256 kb
Host smart-6ab87c02-2a44-45c4-9f8b-daa09ba18a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701963753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.701963753
Directory /workspace/44.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all_with_rand_reset.4270475244
Short name T898
Test name
Test status
Simulation time 3793967902 ps
CPU time 9.1 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:21 PM PDT 24
Peak memory 201364 kb
Host smart-43e955ba-3e46-4869-9170-e6ce30ba7a92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270475244 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_reset.4270475244
Directory /workspace/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.2622469485
Short name T3
Test name
Test status
Simulation time 139904240 ps
CPU time 0.75 seconds
Started Aug 19 05:52:06 PM PDT 24
Finished Aug 19 05:52:06 PM PDT 24
Peak memory 198392 kb
Host smart-752ec5f3-92f8-4eb6-85d5-2ff9a5b00ce7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622469485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.2622469485
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.2747424621
Short name T704
Test name
Test status
Simulation time 349734130 ps
CPU time 1.04 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:13 PM PDT 24
Peak memory 200884 kb
Host smart-f31fdc0e-9721-40c9-b95a-64c8d8edb0a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747424621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.2747424621
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.25845646
Short name T799
Test name
Test status
Simulation time 21634823 ps
CPU time 0.69 seconds
Started Aug 19 05:52:25 PM PDT 24
Finished Aug 19 05:52:25 PM PDT 24
Peak memory 198740 kb
Host smart-a1665c54-81f3-4c1f-a901-987af8913452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25845646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.25845646
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.2276412380
Short name T956
Test name
Test status
Simulation time 102288267 ps
CPU time 0.66 seconds
Started Aug 19 05:52:24 PM PDT 24
Finished Aug 19 05:52:24 PM PDT 24
Peak memory 198676 kb
Host smart-28a1a7dc-5ac8-4bdc-9e90-d2145c134cc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276412380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.2276412380
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3890211392
Short name T239
Test name
Test status
Simulation time 45411449 ps
CPU time 0.56 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 197292 kb
Host smart-39d534fb-5a84-4894-be8d-91f2cb2a053c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890211392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.3890211392
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.687088131
Short name T572
Test name
Test status
Simulation time 107244638 ps
CPU time 0.87 seconds
Started Aug 19 05:52:20 PM PDT 24
Finished Aug 19 05:52:21 PM PDT 24
Peak memory 198440 kb
Host smart-3b8257e1-5462-4b51-bc31-e14411149c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687088131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.687088131
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.659513568
Short name T213
Test name
Test status
Simulation time 51226926 ps
CPU time 0.71 seconds
Started Aug 19 05:52:18 PM PDT 24
Finished Aug 19 05:52:19 PM PDT 24
Peak memory 197328 kb
Host smart-460545b8-2150-4cf5-a26a-be876b5869f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659513568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.659513568
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.898362966
Short name T420
Test name
Test status
Simulation time 69616214 ps
CPU time 0.58 seconds
Started Aug 19 05:52:24 PM PDT 24
Finished Aug 19 05:52:25 PM PDT 24
Peak memory 198120 kb
Host smart-79bc6674-2558-43bc-99e5-bb5b35f7f1a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898362966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.898362966
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.1668048124
Short name T430
Test name
Test status
Simulation time 187226926 ps
CPU time 0.66 seconds
Started Aug 19 05:52:20 PM PDT 24
Finished Aug 19 05:52:20 PM PDT 24
Peak memory 201324 kb
Host smart-9e34c3b6-8dfd-48df-8f80-049b0c6eb209
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668048124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.1668048124
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.2907638817
Short name T616
Test name
Test status
Simulation time 267788066 ps
CPU time 0.81 seconds
Started Aug 19 05:52:57 PM PDT 24
Finished Aug 19 05:52:58 PM PDT 24
Peak memory 198616 kb
Host smart-6561f3d6-026a-4dd7-95d9-ebafa65decdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907638817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.2907638817
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.642359313
Short name T88
Test name
Test status
Simulation time 104580097 ps
CPU time 0.77 seconds
Started Aug 19 05:52:19 PM PDT 24
Finished Aug 19 05:52:20 PM PDT 24
Peak memory 199160 kb
Host smart-62cbed7f-266e-4212-9a6d-80434c81c6a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642359313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.642359313
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.2170164713
Short name T918
Test name
Test status
Simulation time 165455575 ps
CPU time 0.8 seconds
Started Aug 19 05:52:19 PM PDT 24
Finished Aug 19 05:52:19 PM PDT 24
Peak memory 209404 kb
Host smart-695e5ee4-140c-49e2-9523-9728714bcc52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170164713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2170164713
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2283466288
Short name T435
Test name
Test status
Simulation time 35022576 ps
CPU time 0.65 seconds
Started Aug 19 05:52:12 PM PDT 24
Finished Aug 19 05:52:13 PM PDT 24
Peak memory 198524 kb
Host smart-d7a5ba1a-1819-4271-82d7-7064ad4d8559
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283466288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_
cm_ctrl_config_regwen.2283466288
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1519997835
Short name T607
Test name
Test status
Simulation time 1027466526 ps
CPU time 2.28 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 201088 kb
Host smart-57ed22d8-6241-405b-82f5-75036d4667c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519997835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1519997835
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.797371145
Short name T251
Test name
Test status
Simulation time 1073624958 ps
CPU time 1.93 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 200944 kb
Host smart-4a8bfdfd-aab0-4f3e-9e4b-06347a0a8010
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797371145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.797371145
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3649774700
Short name T881
Test name
Test status
Simulation time 53329006 ps
CPU time 0.88 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:52:35 PM PDT 24
Peak memory 199392 kb
Host smart-639be1da-935b-42b3-bf33-b7c5eaa9e008
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649774700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3649774700
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.3183584864
Short name T964
Test name
Test status
Simulation time 32744031 ps
CPU time 0.67 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:12 PM PDT 24
Peak memory 198544 kb
Host smart-5f29c761-0fa9-4ec6-892b-ce2655adc97e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183584864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.3183584864
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all.2706533927
Short name T527
Test name
Test status
Simulation time 76184325 ps
CPU time 0.99 seconds
Started Aug 19 05:52:24 PM PDT 24
Finished Aug 19 05:52:25 PM PDT 24
Peak memory 200300 kb
Host smart-6e5215f9-4208-4eab-a1b7-d8c1665f7675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706533927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.2706533927
Directory /workspace/45.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2582807721
Short name T727
Test name
Test status
Simulation time 8084012544 ps
CPU time 10.82 seconds
Started Aug 19 05:52:22 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 201360 kb
Host smart-d5de7b35-f819-4471-9f13-2689b3e61e05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582807721 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all_with_rand_reset.2582807721
Directory /workspace/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.1018140594
Short name T855
Test name
Test status
Simulation time 41425266 ps
CPU time 0.61 seconds
Started Aug 19 05:52:28 PM PDT 24
Finished Aug 19 05:52:29 PM PDT 24
Peak memory 198320 kb
Host smart-41e54319-f46f-4338-b552-ab017769ea47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018140594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.1018140594
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.1536751310
Short name T176
Test name
Test status
Simulation time 113479006 ps
CPU time 0.91 seconds
Started Aug 19 05:52:12 PM PDT 24
Finished Aug 19 05:52:13 PM PDT 24
Peak memory 199380 kb
Host smart-9721d537-60a7-4db3-85e3-dc7aee612786
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536751310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1536751310
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.559436340
Short name T728
Test name
Test status
Simulation time 60770667 ps
CPU time 0.69 seconds
Started Aug 19 05:52:14 PM PDT 24
Finished Aug 19 05:52:15 PM PDT 24
Peak memory 198872 kb
Host smart-aa2c7a27-7135-4cb5-83c5-1eccfa0d8950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559436340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.559436340
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.1531018917
Short name T694
Test name
Test status
Simulation time 57625318 ps
CPU time 0.78 seconds
Started Aug 19 05:52:29 PM PDT 24
Finished Aug 19 05:52:30 PM PDT 24
Peak memory 199136 kb
Host smart-cc0d5b53-c4e1-4be5-bbe7-4234f1b33e62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531018917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.1531018917
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1836032419
Short name T884
Test name
Test status
Simulation time 39179444 ps
CPU time 0.59 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:12 PM PDT 24
Peak memory 197276 kb
Host smart-fb740183-42b0-429f-aa61-756ba893ecd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836032419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.1836032419
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.2375655468
Short name T313
Test name
Test status
Simulation time 115747003 ps
CPU time 0.84 seconds
Started Aug 19 05:52:22 PM PDT 24
Finished Aug 19 05:52:23 PM PDT 24
Peak memory 199164 kb
Host smart-7f1c7eb5-06c3-40bb-9b39-ec962cdd1fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375655468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2375655468
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.404521716
Short name T325
Test name
Test status
Simulation time 36743750 ps
CPU time 0.59 seconds
Started Aug 19 05:52:17 PM PDT 24
Finished Aug 19 05:52:18 PM PDT 24
Peak memory 198080 kb
Host smart-0dd0b254-e688-46d1-aba1-dc0d187c734d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404521716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.404521716
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.2984095541
Short name T592
Test name
Test status
Simulation time 57275622 ps
CPU time 0.61 seconds
Started Aug 19 05:52:25 PM PDT 24
Finished Aug 19 05:52:26 PM PDT 24
Peak memory 198080 kb
Host smart-3e35e30a-e14c-4fc5-bc18-bc293d316d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984095541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2984095541
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.1739366440
Short name T570
Test name
Test status
Simulation time 44144340 ps
CPU time 0.69 seconds
Started Aug 19 05:52:22 PM PDT 24
Finished Aug 19 05:52:23 PM PDT 24
Peak memory 201136 kb
Host smart-ee4da47f-7b54-4517-aa14-803e9088e3a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739366440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.1739366440
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.3951834978
Short name T356
Test name
Test status
Simulation time 337453406 ps
CPU time 0.92 seconds
Started Aug 19 05:52:20 PM PDT 24
Finished Aug 19 05:52:21 PM PDT 24
Peak memory 199616 kb
Host smart-3fe87967-db5d-4525-a111-21ecc95871ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951834978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_w
akeup_race.3951834978
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.1552726539
Short name T192
Test name
Test status
Simulation time 173763780 ps
CPU time 0.86 seconds
Started Aug 19 05:52:26 PM PDT 24
Finished Aug 19 05:52:27 PM PDT 24
Peak memory 199172 kb
Host smart-08029581-a76d-4342-9471-d029c08d592f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552726539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.1552726539
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.3758771297
Short name T30
Test name
Test status
Simulation time 108674704 ps
CPU time 0.95 seconds
Started Aug 19 05:52:13 PM PDT 24
Finished Aug 19 05:52:14 PM PDT 24
Peak memory 209400 kb
Host smart-834743f2-6632-4b16-a76e-31c60edb8915
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758771297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.3758771297
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.3345909895
Short name T386
Test name
Test status
Simulation time 49183980 ps
CPU time 0.77 seconds
Started Aug 19 05:52:09 PM PDT 24
Finished Aug 19 05:52:10 PM PDT 24
Peak memory 198640 kb
Host smart-aca9df9e-6ad5-4b30-8307-8da2b9ed7f63
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345909895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_
cm_ctrl_config_regwen.3345909895
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2546671491
Short name T600
Test name
Test status
Simulation time 853708251 ps
CPU time 2.39 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 201188 kb
Host smart-0dc5271e-a7cb-4263-9915-584d25067b86
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546671491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2546671491
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.547326819
Short name T593
Test name
Test status
Simulation time 924665640 ps
CPU time 2.53 seconds
Started Aug 19 05:52:20 PM PDT 24
Finished Aug 19 05:52:23 PM PDT 24
Peak memory 200936 kb
Host smart-a6c408d3-6f65-430f-a8c8-1825425f56c5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547326819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.547326819
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2367321831
Short name T263
Test name
Test status
Simulation time 169830252 ps
CPU time 0.92 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 199316 kb
Host smart-0cae2f5f-066c-46b8-a9bd-ec7a09b15763
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367321831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2367321831
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.2016228864
Short name T574
Test name
Test status
Simulation time 30116749 ps
CPU time 0.69 seconds
Started Aug 19 05:52:08 PM PDT 24
Finished Aug 19 05:52:09 PM PDT 24
Peak memory 199404 kb
Host smart-4fc5a516-2a4c-4390-974c-baedca5269b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016228864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2016228864
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all.607163805
Short name T849
Test name
Test status
Simulation time 1490943335 ps
CPU time 5.2 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:39 PM PDT 24
Peak memory 201208 kb
Host smart-b0daba9a-002b-4d91-ab21-62c8c64c8600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607163805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.607163805
Directory /workspace/46.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.1960854809
Short name T63
Test name
Test status
Simulation time 1753999070 ps
CPU time 6.63 seconds
Started Aug 19 05:52:15 PM PDT 24
Finished Aug 19 05:52:22 PM PDT 24
Peak memory 201316 kb
Host smart-b585ee92-4d01-4dfa-b330-df01fe2f2120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960854809 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.1960854809
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.3859247105
Short name T545
Test name
Test status
Simulation time 341643133 ps
CPU time 1.05 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:34 PM PDT 24
Peak memory 199880 kb
Host smart-615df0d7-dcbe-4d19-97b9-aaf49da3a6bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859247105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.3859247105
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.2970306629
Short name T715
Test name
Test status
Simulation time 93001888 ps
CPU time 0.74 seconds
Started Aug 19 05:52:19 PM PDT 24
Finished Aug 19 05:52:20 PM PDT 24
Peak memory 199316 kb
Host smart-f3e9fcdc-5051-4c45-995e-93c6cf3b6383
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970306629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.2970306629
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.3812666673
Short name T534
Test name
Test status
Simulation time 38904171 ps
CPU time 0.7 seconds
Started Aug 19 05:52:14 PM PDT 24
Finished Aug 19 05:52:15 PM PDT 24
Peak memory 198872 kb
Host smart-9ab8f858-83bc-4742-9869-0dc185015313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812666673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3812666673
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.665345608
Short name T834
Test name
Test status
Simulation time 83816789 ps
CPU time 0.67 seconds
Started Aug 19 05:52:18 PM PDT 24
Finished Aug 19 05:52:19 PM PDT 24
Peak memory 199152 kb
Host smart-67604f66-30eb-408a-8982-bb210ecc4f32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665345608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disa
ble_rom_integrity_check.665345608
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.816982041
Short name T231
Test name
Test status
Simulation time 37318283 ps
CPU time 0.61 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:27 PM PDT 24
Peak memory 197300 kb
Host smart-cc974d05-90d2-43f4-ad74-2dd1283280d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816982041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_
malfunc.816982041
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.4017031435
Short name T753
Test name
Test status
Simulation time 406492819 ps
CPU time 0.85 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:12 PM PDT 24
Peak memory 198108 kb
Host smart-1b5ad98f-4f50-4f9b-945f-f333a95f7920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017031435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.4017031435
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.3109579528
Short name T178
Test name
Test status
Simulation time 58363456 ps
CPU time 0.64 seconds
Started Aug 19 05:52:24 PM PDT 24
Finished Aug 19 05:52:25 PM PDT 24
Peak memory 198004 kb
Host smart-0692f8b3-493e-41f2-9bb8-f41fd90e4c8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109579528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.3109579528
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.3344130274
Short name T634
Test name
Test status
Simulation time 35761713 ps
CPU time 0.6 seconds
Started Aug 19 05:52:26 PM PDT 24
Finished Aug 19 05:52:27 PM PDT 24
Peak memory 198064 kb
Host smart-aeaad636-edf5-474d-8756-95f2ac015199
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344130274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.3344130274
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.3245589083
Short name T759
Test name
Test status
Simulation time 52159816 ps
CPU time 0.72 seconds
Started Aug 19 05:52:21 PM PDT 24
Finished Aug 19 05:52:27 PM PDT 24
Peak memory 201368 kb
Host smart-f7f8d2fe-cdbc-4b4b-9342-f17985a49e41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245589083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.3245589083
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.3007767076
Short name T270
Test name
Test status
Simulation time 293618295 ps
CPU time 1.36 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 199608 kb
Host smart-9b05e28f-c83f-4d9c-b9de-e39b43fc6df3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007767076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_w
akeup_race.3007767076
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.4118127803
Short name T856
Test name
Test status
Simulation time 65584880 ps
CPU time 0.92 seconds
Started Aug 19 05:52:22 PM PDT 24
Finished Aug 19 05:52:23 PM PDT 24
Peak memory 199208 kb
Host smart-13eb0170-8395-4201-9644-b318841753ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118127803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.4118127803
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.2074718203
Short name T421
Test name
Test status
Simulation time 149050110 ps
CPU time 0.84 seconds
Started Aug 19 05:52:25 PM PDT 24
Finished Aug 19 05:52:26 PM PDT 24
Peak memory 201140 kb
Host smart-9ed64d52-b835-4125-83bf-694919660ac0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074718203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.2074718203
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.3628771012
Short name T712
Test name
Test status
Simulation time 28454077 ps
CPU time 0.68 seconds
Started Aug 19 05:52:15 PM PDT 24
Finished Aug 19 05:52:16 PM PDT 24
Peak memory 198612 kb
Host smart-5246a68d-7fd8-4649-8ebc-78b3808a5177
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628771012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_
cm_ctrl_config_regwen.3628771012
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3358972106
Short name T835
Test name
Test status
Simulation time 1161340469 ps
CPU time 2.26 seconds
Started Aug 19 05:54:09 PM PDT 24
Finished Aug 19 05:54:11 PM PDT 24
Peak memory 201108 kb
Host smart-1bd272fb-8f1f-498d-88d4-8143b68db502
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358972106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3358972106
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1514713092
Short name T564
Test name
Test status
Simulation time 815449177 ps
CPU time 3.21 seconds
Started Aug 19 05:52:23 PM PDT 24
Finished Aug 19 05:52:26 PM PDT 24
Peak memory 201220 kb
Host smart-45ba8f3b-3ac0-42d8-a411-f0696383d0fb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514713092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1514713092
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.2663644981
Short name T899
Test name
Test status
Simulation time 265179624 ps
CPU time 0.9 seconds
Started Aug 19 05:52:11 PM PDT 24
Finished Aug 19 05:52:12 PM PDT 24
Peak memory 199288 kb
Host smart-af0dd197-721c-4677-80d3-a0a4fcc80e68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663644981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2663644981
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.3078910196
Short name T90
Test name
Test status
Simulation time 52368120 ps
CPU time 0.6 seconds
Started Aug 19 05:52:22 PM PDT 24
Finished Aug 19 05:52:22 PM PDT 24
Peak memory 198604 kb
Host smart-c995279d-77e4-4374-9cdd-8564b0397480
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078910196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.3078910196
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.4229260416
Short name T604
Test name
Test status
Simulation time 2886882268 ps
CPU time 3.8 seconds
Started Aug 19 05:52:19 PM PDT 24
Finished Aug 19 05:52:23 PM PDT 24
Peak memory 201216 kb
Host smart-a759a4f4-ef2b-4b66-9608-7fad3213bbba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229260416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.4229260416
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1193181371
Short name T702
Test name
Test status
Simulation time 14987607952 ps
CPU time 7.65 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:39 PM PDT 24
Peak memory 201408 kb
Host smart-77e45348-39a1-468b-a7b2-b1eda88d63be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193181371 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_reset.1193181371
Directory /workspace/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.1519669386
Short name T305
Test name
Test status
Simulation time 337488285 ps
CPU time 0.94 seconds
Started Aug 19 05:52:16 PM PDT 24
Finished Aug 19 05:52:17 PM PDT 24
Peak memory 199712 kb
Host smart-5753d046-4afb-4750-b61e-dc298de1c05e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519669386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.1519669386
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.2863690020
Short name T897
Test name
Test status
Simulation time 65372703 ps
CPU time 0.63 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 199192 kb
Host smart-0efde59c-4691-4d93-8045-829caf71bc52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863690020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.2863690020
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.1813293059
Short name T494
Test name
Test status
Simulation time 82961385 ps
CPU time 0.89 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 200280 kb
Host smart-5008958f-f941-4b95-bcb2-a21f1ca178e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813293059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.1813293059
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.614831013
Short name T787
Test name
Test status
Simulation time 67597638 ps
CPU time 0.72 seconds
Started Aug 19 05:52:42 PM PDT 24
Finished Aug 19 05:52:43 PM PDT 24
Peak memory 199204 kb
Host smart-10edd779-54a5-4439-a365-c6de68326321
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614831013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disa
ble_rom_integrity_check.614831013
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2031429306
Short name T434
Test name
Test status
Simulation time 29443794 ps
CPU time 0.65 seconds
Started Aug 19 05:52:29 PM PDT 24
Finished Aug 19 05:52:30 PM PDT 24
Peak memory 198064 kb
Host smart-1821c02c-37bd-4716-ac9b-fe9c44044f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031429306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.2031429306
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.2895125249
Short name T844
Test name
Test status
Simulation time 388030128 ps
CPU time 0.85 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:34 PM PDT 24
Peak memory 198144 kb
Host smart-42e6319c-7c2a-4802-8fca-f4a37e5ffe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895125249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2895125249
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.2259617251
Short name T15
Test name
Test status
Simulation time 38073136 ps
CPU time 0.61 seconds
Started Aug 19 05:52:36 PM PDT 24
Finished Aug 19 05:52:37 PM PDT 24
Peak memory 198036 kb
Host smart-a7e11812-0821-4c77-a620-74852b73fe63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259617251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.2259617251
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.423650124
Short name T873
Test name
Test status
Simulation time 55728755 ps
CPU time 0.58 seconds
Started Aug 19 05:52:41 PM PDT 24
Finished Aug 19 05:52:42 PM PDT 24
Peak memory 198104 kb
Host smart-1ce18924-82cd-4b30-ae60-eb565d0278dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423650124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.423650124
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.2820373652
Short name T838
Test name
Test status
Simulation time 42441896 ps
CPU time 0.76 seconds
Started Aug 19 05:52:28 PM PDT 24
Finished Aug 19 05:52:29 PM PDT 24
Peak memory 201308 kb
Host smart-77c79748-bb4f-44bb-a552-d58ba9d9a7aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820373652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.2820373652
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.3809623154
Short name T444
Test name
Test status
Simulation time 168693468 ps
CPU time 0.7 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:28 PM PDT 24
Peak memory 198336 kb
Host smart-3c4ffb6f-6aa1-491e-a8a6-6af6f134b885
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809623154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w
akeup_race.3809623154
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.3939128366
Short name T726
Test name
Test status
Simulation time 73975451 ps
CPU time 0.93 seconds
Started Aug 19 05:52:12 PM PDT 24
Finished Aug 19 05:52:14 PM PDT 24
Peak memory 199844 kb
Host smart-c9e48b09-d1b5-41d4-be49-d70931091315
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939128366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.3939128366
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.3253728072
Short name T42
Test name
Test status
Simulation time 94466113 ps
CPU time 0.94 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 209452 kb
Host smart-f2d3573d-e0ca-4feb-abee-3a26be5b2651
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253728072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.3253728072
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.986250810
Short name T907
Test name
Test status
Simulation time 57892049 ps
CPU time 0.78 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 199192 kb
Host smart-30c3beaf-6b75-46ee-a1dc-7d2473b04c40
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986250810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_c
m_ctrl_config_regwen.986250810
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.44160661
Short name T489
Test name
Test status
Simulation time 1636983256 ps
CPU time 1.77 seconds
Started Aug 19 05:52:24 PM PDT 24
Finished Aug 19 05:52:26 PM PDT 24
Peak memory 201104 kb
Host smart-f325323a-275b-490e-8498-53f6a79484f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44160661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.44160661
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.366901121
Short name T945
Test name
Test status
Simulation time 1000229542 ps
CPU time 2.04 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:29 PM PDT 24
Peak memory 201176 kb
Host smart-07cf6092-e247-4998-95c8-1077887f88cd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366901121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.366901121
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1039932549
Short name T227
Test name
Test status
Simulation time 92419239 ps
CPU time 0.91 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:34 PM PDT 24
Peak memory 199172 kb
Host smart-45f29647-f1b0-401f-bd46-4554c5fe8933
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039932549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1039932549
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.1247766335
Short name T861
Test name
Test status
Simulation time 28855573 ps
CPU time 0.65 seconds
Started Aug 19 05:52:37 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 199356 kb
Host smart-f50799ce-54db-4827-a5b8-c2ef466c164f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247766335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1247766335
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.1495838986
Short name T725
Test name
Test status
Simulation time 156912932 ps
CPU time 1.02 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:28 PM PDT 24
Peak memory 198796 kb
Host smart-b0423131-8234-4e45-a2a6-9c2dbb563d0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495838986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.1495838986
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all_with_rand_reset.4126776041
Short name T128
Test name
Test status
Simulation time 12099635328 ps
CPU time 12.86 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:44 PM PDT 24
Peak memory 201372 kb
Host smart-47cdc03e-eaa2-48a4-a115-525a7f73100f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126776041 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_reset.4126776041
Directory /workspace/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.754893129
Short name T943
Test name
Test status
Simulation time 268352665 ps
CPU time 0.85 seconds
Started Aug 19 05:52:22 PM PDT 24
Finished Aug 19 05:52:23 PM PDT 24
Peak memory 199544 kb
Host smart-a7010b21-fda7-485d-a443-183ac3d3743f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754893129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.754893129
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.2354566184
Short name T812
Test name
Test status
Simulation time 54157699 ps
CPU time 0.7 seconds
Started Aug 19 05:52:20 PM PDT 24
Finished Aug 19 05:52:21 PM PDT 24
Peak memory 199192 kb
Host smart-08a3a057-c4b4-42da-b6f5-81b0ae27f194
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354566184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.2354566184
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.918068749
Short name T441
Test name
Test status
Simulation time 36792956 ps
CPU time 0.82 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 200292 kb
Host smart-5ef14821-0fc4-4936-83ee-5df4339436a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918068749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.918068749
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.3413665113
Short name T163
Test name
Test status
Simulation time 56201780 ps
CPU time 0.82 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 199212 kb
Host smart-7ca3f07c-06d4-4b3f-898e-d4cf94441d15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413665113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.3413665113
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3402836386
Short name T716
Test name
Test status
Simulation time 29768996 ps
CPU time 0.61 seconds
Started Aug 19 05:52:38 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 197972 kb
Host smart-23fa8122-2e05-4794-ae37-277789235532
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402836386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3402836386
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.3824046785
Short name T869
Test name
Test status
Simulation time 721647468 ps
CPU time 0.82 seconds
Started Aug 19 05:52:37 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 198416 kb
Host smart-0c3fee72-21c2-4e79-8750-400c4f44fcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824046785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3824046785
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.684281382
Short name T4
Test name
Test status
Simulation time 31790715 ps
CPU time 0.6 seconds
Started Aug 19 05:52:36 PM PDT 24
Finished Aug 19 05:52:37 PM PDT 24
Peak memory 198088 kb
Host smart-edcfc559-e2fa-4751-9bc9-acfd1cb3e5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684281382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.684281382
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.2512266260
Short name T854
Test name
Test status
Simulation time 35842603 ps
CPU time 0.64 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:52:34 PM PDT 24
Peak memory 198088 kb
Host smart-d107da3e-6e6e-4959-a9be-2599a5f9cafc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512266260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.2512266260
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2386284979
Short name T720
Test name
Test status
Simulation time 75725633 ps
CPU time 0.67 seconds
Started Aug 19 05:52:28 PM PDT 24
Finished Aug 19 05:52:29 PM PDT 24
Peak memory 201292 kb
Host smart-1289ee8b-5479-438d-86c9-0c86732771d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386284979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2386284979
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.662331780
Short name T75
Test name
Test status
Simulation time 176722415 ps
CPU time 1.04 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:35 PM PDT 24
Peak memory 198360 kb
Host smart-377aba9f-2b9c-48e8-b837-d8582c3a3233
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662331780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wa
keup_race.662331780
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.492384735
Short name T989
Test name
Test status
Simulation time 101761729 ps
CPU time 0.74 seconds
Started Aug 19 05:52:26 PM PDT 24
Finished Aug 19 05:52:27 PM PDT 24
Peak memory 198712 kb
Host smart-803fdc08-ebe5-415d-9a41-b4545e74b1ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492384735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.492384735
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.3954472258
Short name T260
Test name
Test status
Simulation time 560171271 ps
CPU time 0.78 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 209452 kb
Host smart-015116a9-33c3-46ad-a56a-273116d0332b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954472258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.3954472258
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.1940179190
Short name T533
Test name
Test status
Simulation time 96498367 ps
CPU time 0.97 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 200144 kb
Host smart-a84b7d2b-c363-496a-9c77-7ffc8731a7f7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940179190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_
cm_ctrl_config_regwen.1940179190
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1207279881
Short name T553
Test name
Test status
Simulation time 832159471 ps
CPU time 2.85 seconds
Started Aug 19 05:52:25 PM PDT 24
Finished Aug 19 05:52:28 PM PDT 24
Peak memory 201044 kb
Host smart-d1ceb508-3a6a-4643-9593-8bac240407a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207279881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1207279881
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1303217247
Short name T145
Test name
Test status
Simulation time 1745976550 ps
CPU time 1.93 seconds
Started Aug 19 05:52:41 PM PDT 24
Finished Aug 19 05:52:43 PM PDT 24
Peak memory 201116 kb
Host smart-867c447d-205a-434b-a5b4-8d4408748e21
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303217247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1303217247
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.4061214246
Short name T275
Test name
Test status
Simulation time 53086673 ps
CPU time 0.86 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:52:35 PM PDT 24
Peak memory 199284 kb
Host smart-74af45f6-d6b3-4ee6-ad58-90100ab0797a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061214246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4061214246
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.1110190880
Short name T883
Test name
Test status
Simulation time 31188874 ps
CPU time 0.68 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 199432 kb
Host smart-276e3f4e-e60f-40cc-8ef1-c62088002afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110190880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1110190880
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all.2386291042
Short name T272
Test name
Test status
Simulation time 602936066 ps
CPU time 2.6 seconds
Started Aug 19 05:52:26 PM PDT 24
Finished Aug 19 05:52:28 PM PDT 24
Peak memory 201208 kb
Host smart-d0e899e0-0eb0-4fbf-8aa8-efdbc1825369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386291042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.2386291042
Directory /workspace/49.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.3961921983
Short name T983
Test name
Test status
Simulation time 6867299127 ps
CPU time 8.43 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:43 PM PDT 24
Peak memory 201376 kb
Host smart-0b34ad27-d642-4c6d-9c19-f6b8de39a65a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961921983 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.3961921983
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.3443641177
Short name T236
Test name
Test status
Simulation time 134256562 ps
CPU time 0.92 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:36 PM PDT 24
Peak memory 199592 kb
Host smart-9d9a00bf-2e11-47d8-999c-74cf29493956
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443641177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.3443641177
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.2201622287
Short name T467
Test name
Test status
Simulation time 302464694 ps
CPU time 1.07 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 201012 kb
Host smart-b519e3cb-9b28-453a-92c3-6345104208e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201622287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.2201622287
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.2556317996
Short name T108
Test name
Test status
Simulation time 18622512 ps
CPU time 0.63 seconds
Started Aug 19 05:50:38 PM PDT 24
Finished Aug 19 05:50:39 PM PDT 24
Peak memory 198648 kb
Host smart-5eb61792-0f81-4984-8566-eaefcbb8d028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556317996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.2556317996
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.3792704475
Short name T890
Test name
Test status
Simulation time 67330918 ps
CPU time 0.85 seconds
Started Aug 19 05:50:20 PM PDT 24
Finished Aug 19 05:50:21 PM PDT 24
Peak memory 199156 kb
Host smart-79d403bb-fcca-4214-9bc7-caf8abfbccd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792704475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.3792704475
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1002565031
Short name T819
Test name
Test status
Simulation time 38697555 ps
CPU time 0.6 seconds
Started Aug 19 05:50:21 PM PDT 24
Finished Aug 19 05:50:22 PM PDT 24
Peak memory 197980 kb
Host smart-c3e51ab9-92ac-4e76-a531-f785bdf3d4d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002565031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.1002565031
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.124764101
Short name T994
Test name
Test status
Simulation time 126949466 ps
CPU time 0.84 seconds
Started Aug 19 05:50:23 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 199464 kb
Host smart-42a96cbf-a1cd-4758-be0a-89ef5b288f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124764101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.124764101
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.4042550886
Short name T801
Test name
Test status
Simulation time 42327335 ps
CPU time 0.67 seconds
Started Aug 19 05:50:31 PM PDT 24
Finished Aug 19 05:50:31 PM PDT 24
Peak memory 197384 kb
Host smart-8ab1e5eb-42ee-4ac5-844e-d6f6d8326f13
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042550886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.4042550886
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.619012998
Short name T40
Test name
Test status
Simulation time 30185230 ps
CPU time 0.59 seconds
Started Aug 19 05:50:39 PM PDT 24
Finished Aug 19 05:50:40 PM PDT 24
Peak memory 198084 kb
Host smart-36c005d0-8953-4f19-ad62-671a2fdd363d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619012998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.619012998
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.2755627446
Short name T503
Test name
Test status
Simulation time 45509385 ps
CPU time 0.77 seconds
Started Aug 19 05:50:23 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 201300 kb
Host smart-cff5b4fb-a4dc-4543-ac14-7fb75227ee99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755627446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.2755627446
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.3129220078
Short name T551
Test name
Test status
Simulation time 417062588 ps
CPU time 0.98 seconds
Started Aug 19 05:50:16 PM PDT 24
Finished Aug 19 05:50:17 PM PDT 24
Peak memory 199932 kb
Host smart-bf81652b-eb7b-4226-a47f-4115f3525394
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129220078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa
keup_race.3129220078
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.3373187972
Short name T307
Test name
Test status
Simulation time 30947471 ps
CPU time 0.62 seconds
Started Aug 19 05:50:22 PM PDT 24
Finished Aug 19 05:50:23 PM PDT 24
Peak memory 198288 kb
Host smart-8b386b12-ee9e-42cd-a0a7-342f4f4b3fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373187972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.3373187972
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.3960217575
Short name T580
Test name
Test status
Simulation time 103640751 ps
CPU time 0.97 seconds
Started Aug 19 05:50:30 PM PDT 24
Finished Aug 19 05:50:31 PM PDT 24
Peak memory 209504 kb
Host smart-9e7a906f-7241-411f-bd42-c998d3915188
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960217575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.3960217575
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1610990979
Short name T833
Test name
Test status
Simulation time 173320477 ps
CPU time 0.96 seconds
Started Aug 19 05:50:37 PM PDT 24
Finished Aug 19 05:50:38 PM PDT 24
Peak memory 198812 kb
Host smart-fa8c6f5b-7c4c-4cff-98ed-663148f518f4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610990979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_c
m_ctrl_config_regwen.1610990979
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3725243047
Short name T330
Test name
Test status
Simulation time 800292686 ps
CPU time 3.09 seconds
Started Aug 19 05:50:28 PM PDT 24
Finished Aug 19 05:50:32 PM PDT 24
Peak memory 201152 kb
Host smart-3ef4c8e6-927d-4f8c-8a0a-892cd9dc1140
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725243047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3725243047
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.355252035
Short name T916
Test name
Test status
Simulation time 1326436064 ps
CPU time 2.43 seconds
Started Aug 19 05:50:23 PM PDT 24
Finished Aug 19 05:50:26 PM PDT 24
Peak memory 201084 kb
Host smart-e3574bdb-3ea4-4d7b-aa7c-eb8e4fa7b45b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355252035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.355252035
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2732163756
Short name T507
Test name
Test status
Simulation time 140440076 ps
CPU time 0.84 seconds
Started Aug 19 05:50:38 PM PDT 24
Finished Aug 19 05:50:39 PM PDT 24
Peak memory 199200 kb
Host smart-af3e98d5-5d7e-46f4-9922-b0c8920c048a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732163756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2732163756
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.2695116940
Short name T195
Test name
Test status
Simulation time 30791722 ps
CPU time 0.7 seconds
Started Aug 19 05:50:36 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 199384 kb
Host smart-bf27bc8f-532a-46b6-bfa2-9433ce08b956
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695116940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.2695116940
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all.2170646705
Short name T104
Test name
Test status
Simulation time 2442418722 ps
CPU time 5.58 seconds
Started Aug 19 05:50:18 PM PDT 24
Finished Aug 19 05:50:24 PM PDT 24
Peak memory 201228 kb
Host smart-4fb2a69f-8e98-40c3-8a48-f419d186f15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170646705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.2170646705
Directory /workspace/5.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.3064137939
Short name T81
Test name
Test status
Simulation time 7540006009 ps
CPU time 18.86 seconds
Started Aug 19 05:50:38 PM PDT 24
Finished Aug 19 05:50:57 PM PDT 24
Peak memory 201344 kb
Host smart-c0d678d0-278e-4e3f-945e-2f96331427e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064137939 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_reset.3064137939
Directory /workspace/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.977120088
Short name T986
Test name
Test status
Simulation time 257496288 ps
CPU time 0.95 seconds
Started Aug 19 05:50:25 PM PDT 24
Finished Aug 19 05:50:26 PM PDT 24
Peak memory 199544 kb
Host smart-72b2a6fa-6e24-4279-998e-2531547f0fb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977120088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.977120088
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.1136210136
Short name T415
Test name
Test status
Simulation time 347066832 ps
CPU time 1.05 seconds
Started Aug 19 05:50:27 PM PDT 24
Finished Aug 19 05:50:28 PM PDT 24
Peak memory 200304 kb
Host smart-cf27fefe-d04c-4ec6-aa68-34e496cce168
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136210136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.1136210136
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.3638711525
Short name T216
Test name
Test status
Simulation time 60108515 ps
CPU time 0.8 seconds
Started Aug 19 05:50:35 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 199000 kb
Host smart-ab2da7a5-1081-4827-916d-804a627dc251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638711525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3638711525
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.1218943613
Short name T215
Test name
Test status
Simulation time 45809603 ps
CPU time 0.74 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:33 PM PDT 24
Peak memory 199208 kb
Host smart-870e4695-343d-41a6-b6ea-09b8a8dfa74d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218943613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.1218943613
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1544450462
Short name T953
Test name
Test status
Simulation time 29360173 ps
CPU time 0.66 seconds
Started Aug 19 05:50:30 PM PDT 24
Finished Aug 19 05:50:31 PM PDT 24
Peak memory 197964 kb
Host smart-bb61114f-02d5-48fa-a68f-7b603cd3e53a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544450462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.1544450462
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.2788461479
Short name T714
Test name
Test status
Simulation time 199246210 ps
CPU time 0.87 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 198388 kb
Host smart-b64a9d6a-f9e7-41a8-90df-30631fc1a947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788461479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.2788461479
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.267466011
Short name T744
Test name
Test status
Simulation time 34273204 ps
CPU time 0.61 seconds
Started Aug 19 05:50:38 PM PDT 24
Finished Aug 19 05:50:38 PM PDT 24
Peak memory 198020 kb
Host smart-4099b9b0-c6b6-4eba-9de2-75a98d3f4b81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267466011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.267466011
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.2166890045
Short name T795
Test name
Test status
Simulation time 49617981 ps
CPU time 0.6 seconds
Started Aug 19 05:50:36 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 198052 kb
Host smart-ec127863-04fa-48d3-b7a2-274b1b7ca08f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166890045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2166890045
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.4169899952
Short name T369
Test name
Test status
Simulation time 74547719 ps
CPU time 0.7 seconds
Started Aug 19 05:50:40 PM PDT 24
Finished Aug 19 05:50:41 PM PDT 24
Peak memory 201316 kb
Host smart-40d8ec8b-f84c-4311-8879-2e54ca3fe23a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169899952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.4169899952
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.1545480278
Short name T169
Test name
Test status
Simulation time 72257568 ps
CPU time 0.64 seconds
Started Aug 19 05:50:36 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 198296 kb
Host smart-3232ca07-1b64-4c45-9591-77975a7e3229
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545480278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wa
keup_race.1545480278
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.2619388502
Short name T575
Test name
Test status
Simulation time 79573140 ps
CPU time 0.74 seconds
Started Aug 19 05:50:22 PM PDT 24
Finished Aug 19 05:50:23 PM PDT 24
Peak memory 199176 kb
Host smart-27377e75-22cd-4eff-863e-0d39e08f03f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619388502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.2619388502
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.2062606492
Short name T397
Test name
Test status
Simulation time 204151671 ps
CPU time 0.9 seconds
Started Aug 19 05:50:46 PM PDT 24
Finished Aug 19 05:50:47 PM PDT 24
Peak memory 198760 kb
Host smart-72086633-f371-46f1-9cd0-ec86e06fa42f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062606492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_c
m_ctrl_config_regwen.2062606492
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.965123970
Short name T342
Test name
Test status
Simulation time 817885334 ps
CPU time 2.36 seconds
Started Aug 19 05:50:36 PM PDT 24
Finished Aug 19 05:50:38 PM PDT 24
Peak memory 201216 kb
Host smart-a26b1f28-38ad-4736-adac-0d4284672966
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965123970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.965123970
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2214754122
Short name T427
Test name
Test status
Simulation time 887216645 ps
CPU time 3.28 seconds
Started Aug 19 05:50:37 PM PDT 24
Finished Aug 19 05:50:40 PM PDT 24
Peak memory 201072 kb
Host smart-34ffd001-4b75-45f9-a246-f9f1a3735c82
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214754122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2214754122
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.284406406
Short name T198
Test name
Test status
Simulation time 150251456 ps
CPU time 0.84 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:43 PM PDT 24
Peak memory 199200 kb
Host smart-78db9b4c-24c9-4da1-81a4-d1374d6d50f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284406406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.284406406
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.3286946993
Short name T338
Test name
Test status
Simulation time 66540238 ps
CPU time 0.65 seconds
Started Aug 19 05:50:32 PM PDT 24
Finished Aug 19 05:50:33 PM PDT 24
Peak memory 198552 kb
Host smart-a2402696-1373-49d3-87c1-3475d413ac3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286946993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3286946993
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all.1058262890
Short name T109
Test name
Test status
Simulation time 7377163563 ps
CPU time 5.56 seconds
Started Aug 19 05:50:28 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 201188 kb
Host smart-c933aa06-09c7-4630-ab55-83d9f4ca75a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058262890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.1058262890
Directory /workspace/6.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.2074099152
Short name T129
Test name
Test status
Simulation time 14760787223 ps
CPU time 9.56 seconds
Started Aug 19 05:50:41 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 201336 kb
Host smart-35d2ba62-8d6a-458e-977b-40601df16efb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074099152 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all_with_rand_reset.2074099152
Directory /workspace/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.3495393747
Short name T635
Test name
Test status
Simulation time 229844780 ps
CPU time 1.17 seconds
Started Aug 19 05:50:39 PM PDT 24
Finished Aug 19 05:50:41 PM PDT 24
Peak memory 199732 kb
Host smart-94bc9bb8-733d-4b92-a50e-3495af3d0e77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495393747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.3495393747
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.781955039
Short name T389
Test name
Test status
Simulation time 324473440 ps
CPU time 1.55 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:43 PM PDT 24
Peak memory 201012 kb
Host smart-31f85599-18be-4d31-b94d-11c4f4a5c3a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781955039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.781955039
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.485546197
Short name T557
Test name
Test status
Simulation time 54976067 ps
CPU time 0.7 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:49 PM PDT 24
Peak memory 198756 kb
Host smart-c8b2250a-e2cb-4c24-8fa2-bf373a5d9232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485546197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.485546197
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.102131839
Short name T339
Test name
Test status
Simulation time 58814503 ps
CPU time 0.81 seconds
Started Aug 19 05:50:35 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 199208 kb
Host smart-9239f818-a84c-4028-87b5-67778bdb26ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102131839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disab
le_rom_integrity_check.102131839
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3343039771
Short name T682
Test name
Test status
Simulation time 30801802 ps
CPU time 0.63 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 197276 kb
Host smart-7f4683b2-d72d-4e5a-b5e1-46e90bda9f79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343039771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.3343039771
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.3692004327
Short name T320
Test name
Test status
Simulation time 113792948 ps
CPU time 0.85 seconds
Started Aug 19 05:50:45 PM PDT 24
Finished Aug 19 05:50:46 PM PDT 24
Peak memory 198428 kb
Host smart-8e5c602f-6d41-4987-a36d-1f15fbb05076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692004327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.3692004327
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.545530441
Short name T661
Test name
Test status
Simulation time 23878270 ps
CPU time 0.64 seconds
Started Aug 19 05:50:30 PM PDT 24
Finished Aug 19 05:50:30 PM PDT 24
Peak memory 198084 kb
Host smart-3ecb99ce-6c9e-41b6-bb96-d577672fecd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545530441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.545530441
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.1090567318
Short name T561
Test name
Test status
Simulation time 49874196 ps
CPU time 0.69 seconds
Started Aug 19 05:50:41 PM PDT 24
Finished Aug 19 05:50:41 PM PDT 24
Peak memory 198116 kb
Host smart-d98c280b-1a05-49ff-a815-073365b88e97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090567318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1090567318
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.978830078
Short name T940
Test name
Test status
Simulation time 99687538 ps
CPU time 0.65 seconds
Started Aug 19 05:50:46 PM PDT 24
Finished Aug 19 05:50:47 PM PDT 24
Peak memory 201356 kb
Host smart-bf4591a1-e670-4550-a9dd-2f847d123774
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978830078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid
.978830078
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.1449627974
Short name T733
Test name
Test status
Simulation time 31240170 ps
CPU time 0.66 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 198280 kb
Host smart-091b7022-991f-4f8a-bd29-5aad6dfa86d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449627974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wa
keup_race.1449627974
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.346691215
Short name T180
Test name
Test status
Simulation time 104894203 ps
CPU time 0.81 seconds
Started Aug 19 05:50:35 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 199700 kb
Host smart-94876d72-0918-4752-a051-05303ef7d922
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346691215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.346691215
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.3263910149
Short name T205
Test name
Test status
Simulation time 112871261 ps
CPU time 0.97 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 209400 kb
Host smart-daa2245d-bb10-41cb-87ab-265006a4feba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263910149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3263910149
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.1607992720
Short name T643
Test name
Test status
Simulation time 170087583 ps
CPU time 0.84 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:43 PM PDT 24
Peak memory 198948 kb
Host smart-1389bfaf-096b-4fb0-994f-d144c2b557e4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607992720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_c
m_ctrl_config_regwen.1607992720
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2743070924
Short name T875
Test name
Test status
Simulation time 1092745821 ps
CPU time 2.38 seconds
Started Aug 19 05:50:38 PM PDT 24
Finished Aug 19 05:50:40 PM PDT 24
Peak memory 201084 kb
Host smart-74dcfe88-4199-4ce8-8db6-1aadb5e05098
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743070924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2743070924
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1100397160
Short name T265
Test name
Test status
Simulation time 985984489 ps
CPU time 2.87 seconds
Started Aug 19 05:50:45 PM PDT 24
Finished Aug 19 05:50:48 PM PDT 24
Peak memory 201076 kb
Host smart-4abb441f-cf3a-4854-a43c-dfdf4ecbe8cb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100397160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1100397160
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.843017062
Short name T848
Test name
Test status
Simulation time 109068048 ps
CPU time 0.86 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 199648 kb
Host smart-fe3b207f-e633-478d-953c-892b3a7c1448
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843017062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.843017062
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.1623416592
Short name T449
Test name
Test status
Simulation time 38331301 ps
CPU time 0.64 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 198524 kb
Host smart-fb74950c-5731-4f51-8d24-940fd221c78e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623416592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.1623416592
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.3670313221
Short name T721
Test name
Test status
Simulation time 379906936 ps
CPU time 1.66 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:35 PM PDT 24
Peak memory 201108 kb
Host smart-addd03c4-885f-41dc-8ed5-dad4d5a36bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670313221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.3670313221
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all_with_rand_reset.3016139274
Short name T808
Test name
Test status
Simulation time 4099807558 ps
CPU time 8.75 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:50 PM PDT 24
Peak memory 201408 kb
Host smart-39bf36e2-3f20-4dd9-847a-90f39a0c5aa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016139274 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all_with_rand_reset.3016139274
Directory /workspace/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.3295226424
Short name T802
Test name
Test status
Simulation time 122726428 ps
CPU time 0.75 seconds
Started Aug 19 05:50:40 PM PDT 24
Finished Aug 19 05:50:40 PM PDT 24
Peak memory 198540 kb
Host smart-758005ba-46fb-4235-8356-ac4247403a1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295226424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.3295226424
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.1740780491
Short name T243
Test name
Test status
Simulation time 61220846 ps
CPU time 0.67 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 198528 kb
Host smart-b3c8f797-3b38-4c19-8625-044beaa63078
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740780491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.1740780491
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.791271999
Short name T455
Test name
Test status
Simulation time 40651621 ps
CPU time 0.96 seconds
Started Aug 19 05:50:31 PM PDT 24
Finished Aug 19 05:50:32 PM PDT 24
Peak memory 200264 kb
Host smart-a2ebda02-d3d0-432d-a9ca-1a4b58ffd7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791271999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.791271999
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.4241621635
Short name T166
Test name
Test status
Simulation time 66770366 ps
CPU time 0.82 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 199152 kb
Host smart-c54e9ee3-ddae-4315-9fa8-59cb7f38d201
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241621635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.4241621635
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2446726198
Short name T628
Test name
Test status
Simulation time 29019657 ps
CPU time 0.62 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 198056 kb
Host smart-2acffc1c-c21b-4a71-ac1b-1df5b10714e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446726198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.2446726198
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.1709840909
Short name T556
Test name
Test status
Simulation time 109085538 ps
CPU time 0.85 seconds
Started Aug 19 05:50:46 PM PDT 24
Finished Aug 19 05:50:47 PM PDT 24
Peak memory 199468 kb
Host smart-1c12aff4-b72e-4248-890a-47bdb7288cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709840909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.1709840909
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.4232601869
Short name T677
Test name
Test status
Simulation time 51496768 ps
CPU time 0.68 seconds
Started Aug 19 05:50:31 PM PDT 24
Finished Aug 19 05:50:31 PM PDT 24
Peak memory 198156 kb
Host smart-d2790822-3d62-4f35-8e43-e8b9e0a63e79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232601869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.4232601869
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.77846889
Short name T253
Test name
Test status
Simulation time 51152255 ps
CPU time 0.61 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:42 PM PDT 24
Peak memory 198128 kb
Host smart-2f7539f2-a7f9-4f0b-a70a-ac6bc10c27c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77846889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.77846889
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.2527633231
Short name T91
Test name
Test status
Simulation time 70920593 ps
CPU time 0.69 seconds
Started Aug 19 05:50:35 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 201312 kb
Host smart-7ab6941a-70d2-4ddf-a4ce-335e761362f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527633231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.2527633231
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.3410844755
Short name T282
Test name
Test status
Simulation time 73395675 ps
CPU time 0.72 seconds
Started Aug 19 05:50:39 PM PDT 24
Finished Aug 19 05:50:40 PM PDT 24
Peak memory 198348 kb
Host smart-271acffc-d37c-4141-b1a9-ccca4ef80451
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410844755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa
keup_race.3410844755
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.2745448692
Short name T776
Test name
Test status
Simulation time 58639763 ps
CPU time 0.91 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:43 PM PDT 24
Peak memory 199148 kb
Host smart-0bcee5f1-0ea4-47f3-982d-ffc148799cfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745448692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2745448692
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.2065382253
Short name T781
Test name
Test status
Simulation time 284884898 ps
CPU time 0.77 seconds
Started Aug 19 05:50:40 PM PDT 24
Finished Aug 19 05:50:41 PM PDT 24
Peak memory 209400 kb
Host smart-895d6adf-da76-4625-9481-83ae04f13a76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065382253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2065382253
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.144834888
Short name T522
Test name
Test status
Simulation time 170193370 ps
CPU time 0.68 seconds
Started Aug 19 05:50:30 PM PDT 24
Finished Aug 19 05:50:31 PM PDT 24
Peak memory 198556 kb
Host smart-377970f5-5b1f-4916-be0f-94b7e5f7ec25
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144834888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm
_ctrl_config_regwen.144834888
Directory /workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1921716304
Short name T967
Test name
Test status
Simulation time 1347027505 ps
CPU time 2.35 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:35 PM PDT 24
Peak memory 201128 kb
Host smart-1b11b718-f975-4111-9e4b-c028566a3599
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921716304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1921716304
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3571818353
Short name T516
Test name
Test status
Simulation time 798872732 ps
CPU time 3.33 seconds
Started Aug 19 05:50:33 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 201028 kb
Host smart-3d3b1820-ea46-4e91-b1c9-bd016f952515
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571818353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3571818353
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1545378120
Short name T815
Test name
Test status
Simulation time 80974809 ps
CPU time 0.8 seconds
Started Aug 19 05:50:37 PM PDT 24
Finished Aug 19 05:50:38 PM PDT 24
Peak memory 199288 kb
Host smart-53b45a1c-866d-4773-ace4-95f0d4d69b50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545378120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1545378120
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.433591479
Short name T411
Test name
Test status
Simulation time 49218670 ps
CPU time 0.7 seconds
Started Aug 19 05:50:31 PM PDT 24
Finished Aug 19 05:50:32 PM PDT 24
Peak memory 198608 kb
Host smart-c16bed35-8fcc-44b9-bb25-5e408b13483a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433591479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.433591479
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.631785382
Short name T912
Test name
Test status
Simulation time 5687238301 ps
CPU time 8.37 seconds
Started Aug 19 05:50:46 PM PDT 24
Finished Aug 19 05:50:54 PM PDT 24
Peak memory 201356 kb
Host smart-56ef21c0-19bb-43d6-8170-021c90264b7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631785382 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_reset.631785382
Directory /workspace/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.2429126498
Short name T308
Test name
Test status
Simulation time 628398129 ps
CPU time 0.8 seconds
Started Aug 19 05:50:38 PM PDT 24
Finished Aug 19 05:50:38 PM PDT 24
Peak memory 198204 kb
Host smart-2636d09f-ea8c-4c9a-97ec-5a5385520f0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429126498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.2429126498
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.184998052
Short name T990
Test name
Test status
Simulation time 114738320 ps
CPU time 0.8 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:43 PM PDT 24
Peak memory 200096 kb
Host smart-bdc5af0a-8b27-4aee-bd7a-a735e1c46116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184998052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.184998052
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.3874145842
Short name T770
Test name
Test status
Simulation time 75277799 ps
CPU time 0.7 seconds
Started Aug 19 05:50:52 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 199220 kb
Host smart-6336952f-d2b6-467e-bd3e-aba5970bf7e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874145842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.3874145842
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2183575882
Short name T297
Test name
Test status
Simulation time 30161036 ps
CPU time 0.63 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 197992 kb
Host smart-472860c1-d2d1-4dec-9662-6c99f764d3e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183575882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.2183575882
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.2087265337
Short name T139
Test name
Test status
Simulation time 197157839 ps
CPU time 0.89 seconds
Started Aug 19 05:50:50 PM PDT 24
Finished Aug 19 05:50:51 PM PDT 24
Peak memory 198092 kb
Host smart-f05e7dd7-f717-4c4b-a2a4-5c4bfeb41621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087265337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.2087265337
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.484204687
Short name T653
Test name
Test status
Simulation time 43034614 ps
CPU time 0.61 seconds
Started Aug 19 05:50:53 PM PDT 24
Finished Aug 19 05:50:53 PM PDT 24
Peak memory 198012 kb
Host smart-70e73139-b367-4e93-adfb-73d5399b383e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484204687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.484204687
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.197705369
Short name T842
Test name
Test status
Simulation time 59226651 ps
CPU time 0.59 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:43 PM PDT 24
Peak memory 198136 kb
Host smart-a1aa1378-621f-4744-8c45-185bc03b58c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197705369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.197705369
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.4269142550
Short name T836
Test name
Test status
Simulation time 67357778 ps
CPU time 0.67 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 201364 kb
Host smart-ffc5d650-3f24-45b7-8ce2-15602c49d9a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269142550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.4269142550
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.1804350852
Short name T228
Test name
Test status
Simulation time 107399532 ps
CPU time 0.83 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 199216 kb
Host smart-af0c61a0-d360-46b3-b710-42cf81cb0567
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804350852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wa
keup_race.1804350852
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.3444188810
Short name T309
Test name
Test status
Simulation time 42992835 ps
CPU time 0.61 seconds
Started Aug 19 05:50:36 PM PDT 24
Finished Aug 19 05:50:36 PM PDT 24
Peak memory 198256 kb
Host smart-a6972980-8491-4dda-91ce-59236f20781a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444188810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.3444188810
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.3807830979
Short name T667
Test name
Test status
Simulation time 97420412 ps
CPU time 0.93 seconds
Started Aug 19 05:50:48 PM PDT 24
Finished Aug 19 05:50:49 PM PDT 24
Peak memory 209408 kb
Host smart-46f8187a-23c0-4a30-98c2-8f257cc4e017
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807830979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.3807830979
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1353216949
Short name T638
Test name
Test status
Simulation time 85792662 ps
CPU time 0.63 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 198644 kb
Host smart-ac2d52f8-685b-49ba-ba2c-ae46ee07ad3b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353216949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_c
m_ctrl_config_regwen.1353216949
Directory /workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3347323116
Short name T495
Test name
Test status
Simulation time 1969644237 ps
CPU time 1.98 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:46 PM PDT 24
Peak memory 201116 kb
Host smart-5d1e0cab-162e-4ecf-8222-62b38ea6d51e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347323116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3347323116
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4205245607
Short name T284
Test name
Test status
Simulation time 923757931 ps
CPU time 2.49 seconds
Started Aug 19 05:50:42 PM PDT 24
Finished Aug 19 05:50:45 PM PDT 24
Peak memory 201080 kb
Host smart-6072885a-df96-4d62-9bfd-d6b5079ec0c4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205245607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4205245607
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2427817496
Short name T670
Test name
Test status
Simulation time 65095166 ps
CPU time 0.89 seconds
Started Aug 19 05:50:51 PM PDT 24
Finished Aug 19 05:50:52 PM PDT 24
Peak memory 199180 kb
Host smart-fd1a709d-ef38-4af7-9833-0dc86f60bfe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427817496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2427817496
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.3222745504
Short name T252
Test name
Test status
Simulation time 30685058 ps
CPU time 0.67 seconds
Started Aug 19 05:50:38 PM PDT 24
Finished Aug 19 05:50:38 PM PDT 24
Peak memory 198564 kb
Host smart-5b93e31a-6f45-47cb-9303-a3a1ef930929
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222745504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.3222745504
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all.1467409039
Short name T476
Test name
Test status
Simulation time 1180081893 ps
CPU time 4.58 seconds
Started Aug 19 05:50:44 PM PDT 24
Finished Aug 19 05:50:49 PM PDT 24
Peak memory 201236 kb
Host smart-a22fcd39-03c4-47ce-bae5-d7b11c7c4984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467409039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.1467409039
Directory /workspace/9.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all_with_rand_reset.2449571061
Short name T133
Test name
Test status
Simulation time 7509926723 ps
CPU time 16.76 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:51:00 PM PDT 24
Peak memory 201376 kb
Host smart-fe09d3ff-f4d1-40c5-b41f-746facf3e26b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449571061 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all_with_rand_reset.2449571061
Directory /workspace/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.1654130929
Short name T77
Test name
Test status
Simulation time 121630577 ps
CPU time 0.93 seconds
Started Aug 19 05:50:43 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 199196 kb
Host smart-39a7cddf-61ab-4731-8c49-e85e60342919
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654130929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1654130929
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.1899448442
Short name T745
Test name
Test status
Simulation time 434741958 ps
CPU time 1.12 seconds
Started Aug 19 05:50:39 PM PDT 24
Finished Aug 19 05:50:41 PM PDT 24
Peak memory 200944 kb
Host smart-4c5945dc-3bc0-4ff7-a03d-d815e92cdd2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899448442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.1899448442
Directory /workspace/9.pwrmgr_wakeup_reset/latest
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