Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

2

T3

22

T4

8

auto[1]

21763

1

T3

14

T4

6

T6

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22751

1

T1

2

T3

16

T4

2

auto[1]

21712

1

T3

20

T4

12

T6

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21696

1

T3

16

T4

4

T6

4

auto[1]

22767

1

T1

2

T3

20

T4

10

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24981

1

T1

1

T3

18

T4

7

auto[1]

19482

1

T1

1

T3

18

T4

7

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21914

1

T3

18

T4

4

T6

3

auto[1]

22549

1

T1

2

T3

18

T4

10

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T3

24

T4

2

auto[1]

21911

1

T3

12

T4

12

T6

4

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

776

1

T7

1

T9

3

T33

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

588

1

T7

1

T9

3

T33

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

769

1

T6

1

T7

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

587

1

T7

1

T9

1

T15

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

819

1

T3

1

T9

1

T15

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

643

1

T3

1

T9

1

T15

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1224

1

T1

1

T3

1

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1060

1

T1

1

T3

1

T5

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

765

1

T6

1

T9

2

T15

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

601

1

T9

2

T15

3

T27

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

808

1

T3

1

T7

2

T9

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

638

1

T3

1

T7

2

T9

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

793

1

T3

1

T7

1

T9

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

625

1

T3

1

T7

1

T9

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

774

1

T4

1

T6

1

T7

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

598

1

T4

1

T7

3

T15

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

740

1

T3

1

T7

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

576

1

T3

1

T7

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

774

1

T3

1

T7

2

T9

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

575

1

T3

1

T7

2

T9

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

708

1

T7

1

T9

1

T15

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

555

1

T7

1

T9

1

T15

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

740

1

T3

2

T7

1

T9

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

567

1

T3

2

T7

1

T9

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

752

1

T7

2

T9

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

574

1

T7

2

T9

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

793

1

T3

1

T4

2

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

609

1

T3

1

T4

2

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

772

1

T3

1

T4

1

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

607

1

T3

1

T4

1

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

734

1

T3

1

T9

2

T15

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

556

1

T3

1

T9

2

T15

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

751

1

T3

1

T7

2

T9

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

588

1

T3

1

T7

2

T9

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

736

1

T3

1

T7

2

T9

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

570

1

T3

1

T7

2

T9

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

740

1

T7

3

T9

2

T33

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

555

1

T7

3

T9

2

T33

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

761

1

T3

1

T7

4

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

597

1

T3

1

T7

4

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

728

1

T7

2

T9

1

T33

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

573

1

T7

2

T9

1

T33

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

767

1

T6

1

T7

2

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

608

1

T7

2

T9

1

T15

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

773

1

T3

1

T6

1

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

596

1

T3

1

T7

1

T9

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

747

1

T7

1

T9

2

T15

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

593

1

T7

1

T9

2

T15

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

773

1

T3

2

T9

1

T32

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

607

1

T3

2

T9

1

T32

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

839

1

T3

1

T7

2

T9

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

646

1

T3

1

T7

2

T9

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

742

1

T6

2

T7

2

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

586

1

T7

2

T9

1

T38

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

766

1

T4

1

T7

1

T9

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

594

1

T4

1

T7

1

T9

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

768

1

T7

2

T9

1

T15

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

603

1

T7

2

T9

1

T15

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

807

1

T7

2

T9

1

T42

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

625

1

T7

2

T9

1

T42

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

790

1

T4

1

T7

1

T9

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

629

1

T4

1

T7

1

T9

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

752

1

T4

1

T7

1

T15

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

553

1

T4

1

T7

1

T61

1