Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7963

1

T1

27

T3

20

T9

18

auto[1]

10916

1

T1

31

T3

81

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5833	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6336	1			T1	24		T2	1		T3	27
reset_info_cp[2]	2959	1			T1	9		T3	13		T4	1
reset_info_cp[4]	3823	1			T1	12		T3	18		T4	1
reset_info_cp[8]	104	1			T3	1		T9	1		T13	1
reset_info_cp[16]	101	1			T9	1		T13	1		T26	3
reset_info_cp[32]	108	1			T10	1		T13	1		T23	1
reset_info_cp[64]	113	1			T3	1		T7	1		T9	1
reset_info_cp[128]	122	1			T3	1		T13	2		T23	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3055	1			T1	11		T3	20		T9	18
reset_info_cp[1]	auto[1]	2661	1			T1	12		T3	6		T4	1
reset_info_cp[2]	auto[0]	942	1			T1	3		T10	12		T13	21
reset_info_cp[2]	auto[1]	2017	1			T1	6		T3	13		T4	1
reset_info_cp[4]	auto[0]	1339	1			T1	5		T10	2		T13	39
reset_info_cp[4]	auto[1]	2484	1			T1	7		T3	18		T4	1
reset_info_cp[8]	auto[0]	45	1			T77	1		T69	1		T71	1
reset_info_cp[8]	auto[1]	59	1			T3	1		T9	1		T13	1
reset_info_cp[16]	auto[0]	50	1			T13	1		T26	2		T126	1
reset_info_cp[16]	auto[1]	51	1			T9	1		T26	1		T43	2
reset_info_cp[32]	auto[0]	47	1			T10	1		T13	1		T23	1
reset_info_cp[32]	auto[1]	61	1			T43	1		T76	1		T77	3
reset_info_cp[64]	auto[0]	45	1			T13	2		T23	1		T26	3
reset_info_cp[64]	auto[1]	68	1			T3	1		T7	1		T9	1
reset_info_cp[128]	auto[0]	55	1			T13	1		T23	1		T26	3
reset_info_cp[128]	auto[1]	67	1			T3	1		T13	1		T26	1