| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.44 | 99.40 | 99.31 | 99.88 | 99.83 | 99.46 | 98.77 |
| T502 | /workspace/coverage/default/5.rstmgr_sw_rst.2179812834 | Feb 04 12:53:57 PM PST 24 | Feb 04 12:54:01 PM PST 24 | 129775882 ps | ||
| T503 | /workspace/coverage/default/40.rstmgr_por_stretcher.357903738 | Feb 04 12:53:48 PM PST 24 | Feb 04 12:53:52 PM PST 24 | 72646767 ps | ||
| T504 | /workspace/coverage/default/45.rstmgr_reset.4243376390 | Feb 04 12:53:58 PM PST 24 | Feb 04 12:54:05 PM PST 24 | 853868084 ps | ||
| T505 | /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2601539580 | Feb 04 12:52:40 PM PST 24 | Feb 04 12:52:43 PM PST 24 | 244399083 ps | ||
| T506 | /workspace/coverage/default/44.rstmgr_stress_all.1966760872 | Feb 04 12:53:54 PM PST 24 | Feb 04 12:54:15 PM PST 24 | 3391138076 ps | ||
| T507 | /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.4140753412 | Feb 04 12:53:49 PM PST 24 | Feb 04 12:53:53 PM PST 24 | 96204735 ps | ||
| T508 | /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1641612372 | Feb 04 12:53:25 PM PST 24 | Feb 04 12:53:31 PM PST 24 | 248153523 ps | ||
| T509 | /workspace/coverage/default/7.rstmgr_stress_all.4010502407 | Feb 04 12:52:16 PM PST 24 | Feb 04 12:52:24 PM PST 24 | 1212792035 ps | ||
| T510 | /workspace/coverage/default/43.rstmgr_reset.954672995 | Feb 04 12:53:47 PM PST 24 | Feb 04 12:53:54 PM PST 24 | 1333324111 ps | ||
| T511 | /workspace/coverage/default/2.rstmgr_sw_rst.50399241 | Feb 04 12:52:02 PM PST 24 | Feb 04 12:52:08 PM PST 24 | 374958863 ps | ||
| T512 | /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.198512052 | Feb 04 12:52:21 PM PST 24 | Feb 04 12:52:24 PM PST 24 | 183078133 ps | ||
| T513 | /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2711653230 | Feb 04 12:52:50 PM PST 24 | Feb 04 12:52:52 PM PST 24 | 172948682 ps | ||
| T514 | /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1486565316 | Feb 04 12:53:37 PM PST 24 | Feb 04 12:53:39 PM PST 24 | 194193901 ps | ||
| T515 | /workspace/coverage/default/2.rstmgr_alert_test.3519898573 | Feb 04 12:51:53 PM PST 24 | Feb 04 12:51:56 PM PST 24 | 86563586 ps | ||
| T516 | /workspace/coverage/default/26.rstmgr_stress_all.360182319 | Feb 04 12:53:11 PM PST 24 | Feb 04 12:53:29 PM PST 24 | 3232347357 ps | ||
| T517 | /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1985911089 | Feb 04 12:52:38 PM PST 24 | Feb 04 12:52:41 PM PST 24 | 163206193 ps | ||
| T518 | /workspace/coverage/default/14.rstmgr_reset.1898744132 | Feb 04 12:52:15 PM PST 24 | Feb 04 12:52:21 PM PST 24 | 1252006472 ps | ||
| T519 | /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2290180484 | Feb 04 12:52:09 PM PST 24 | Feb 04 12:52:19 PM PST 24 | 1220078300 ps | ||
| T520 | /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2906567885 | Feb 04 12:53:25 PM PST 24 | Feb 04 12:53:35 PM PST 24 | 1229119408 ps | ||
| T521 | /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1709613085 | Feb 04 12:53:15 PM PST 24 | Feb 04 12:53:18 PM PST 24 | 89783728 ps | ||
| T522 | /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1130777264 | Feb 04 12:53:50 PM PST 24 | Feb 04 12:53:53 PM PST 24 | 109572744 ps | ||
| T523 | /workspace/coverage/default/7.rstmgr_sw_rst.1102811046 | Feb 04 12:52:06 PM PST 24 | Feb 04 12:52:15 PM PST 24 | 135198774 ps | ||
| T524 | /workspace/coverage/default/30.rstmgr_smoke.60438504 | Feb 04 12:53:17 PM PST 24 | Feb 04 12:53:21 PM PST 24 | 114233994 ps | ||
| T525 | /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1101938930 | Feb 04 12:53:47 PM PST 24 | Feb 04 12:53:52 PM PST 24 | 255861401 ps | ||
| T526 | /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2317207428 | Feb 04 12:52:41 PM PST 24 | Feb 04 12:52:43 PM PST 24 | 120733651 ps | ||
| T527 | /workspace/coverage/default/19.rstmgr_stress_all.3504104932 | Feb 04 12:52:44 PM PST 24 | Feb 04 12:52:54 PM PST 24 | 2628515207 ps | ||
| T528 | /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1964639479 | Feb 04 12:52:02 PM PST 24 | Feb 04 12:52:06 PM PST 24 | 244126039 ps | ||
| T529 | /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3998692786 | Feb 04 12:53:36 PM PST 24 | Feb 04 12:53:38 PM PST 24 | 101166041 ps | ||
| T530 | /workspace/coverage/default/9.rstmgr_sw_rst.891895494 | Feb 04 12:52:20 PM PST 24 | Feb 04 12:52:24 PM PST 24 | 144035456 ps | ||
| T531 | /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3707998139 | Feb 04 12:52:21 PM PST 24 | Feb 04 12:52:30 PM PST 24 | 1875086986 ps | ||
| T532 | /workspace/coverage/default/15.rstmgr_reset.2130955691 | Feb 04 12:52:20 PM PST 24 | Feb 04 12:52:28 PM PST 24 | 961588436 ps | ||
| T533 | /workspace/coverage/default/42.rstmgr_smoke.2509620444 | Feb 04 12:53:39 PM PST 24 | Feb 04 12:53:41 PM PST 24 | 191119175 ps | ||
| T534 | /workspace/coverage/default/25.rstmgr_stress_all.606924773 | Feb 04 12:53:11 PM PST 24 | Feb 04 12:53:40 PM PST 24 | 7811086302 ps | ||
| T535 | /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.131180538 | Feb 04 12:52:16 PM PST 24 | Feb 04 12:52:19 PM PST 24 | 149612384 ps | ||
| T536 | /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.234493048 | Feb 04 12:52:39 PM PST 24 | Feb 04 12:52:47 PM PST 24 | 1221508668 ps | ||
| T537 | /workspace/coverage/default/4.rstmgr_por_stretcher.2860645489 | Feb 04 12:52:13 PM PST 24 | Feb 04 12:52:16 PM PST 24 | 104654364 ps | ||
| T538 | /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.395311848 | Feb 04 12:52:42 PM PST 24 | Feb 04 12:52:43 PM PST 24 | 119031980 ps | ||
| T539 | /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.618992427 | Feb 04 12:53:35 PM PST 24 | Feb 04 12:53:38 PM PST 24 | 187333656 ps | ||
| T540 | /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.97384750 | Feb 04 12:52:02 PM PST 24 | Feb 04 12:52:07 PM PST 24 | 188332476 ps | ||
| T541 | /workspace/coverage/default/37.rstmgr_alert_test.1925330979 | Feb 04 12:53:45 PM PST 24 | Feb 04 12:53:48 PM PST 24 | 85114659 ps | ||
| T542 | /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.209321600 | Feb 04 12:53:12 PM PST 24 | Feb 04 12:53:16 PM PST 24 | 244536538 ps | ||
| T543 | /workspace/coverage/default/15.rstmgr_alert_test.726601246 | Feb 04 12:52:15 PM PST 24 | Feb 04 12:52:17 PM PST 24 | 69155326 ps | ||
| T544 | /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4109482545 | Feb 04 12:53:56 PM PST 24 | Feb 04 12:54:01 PM PST 24 | 94742601 ps | ||
| T545 | /workspace/coverage/default/19.rstmgr_smoke.850838322 | Feb 04 12:52:39 PM PST 24 | Feb 04 12:52:42 PM PST 24 | 253488864 ps | ||
| T546 | /workspace/coverage/default/27.rstmgr_stress_all.3826235312 | Feb 04 12:53:13 PM PST 24 | Feb 04 12:53:30 PM PST 24 | 3265888451 ps | ||
| T547 | /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2720217313 | Feb 04 12:52:23 PM PST 24 | Feb 04 12:52:38 PM PST 24 | 1877498318 ps | ||
| T548 | /workspace/coverage/default/37.rstmgr_sw_rst.1454854758 | Feb 04 12:53:42 PM PST 24 | Feb 04 12:53:46 PM PST 24 | 441110514 ps | ||
| T549 | /workspace/coverage/default/21.rstmgr_smoke.1901327341 | Feb 04 12:52:37 PM PST 24 | Feb 04 12:52:40 PM PST 24 | 119525033 ps | ||
| T550 | /workspace/coverage/default/45.rstmgr_alert_test.1802893687 | Feb 04 12:53:50 PM PST 24 | Feb 04 12:53:53 PM PST 24 | 84527105 ps | ||
| T551 | /workspace/coverage/default/26.rstmgr_alert_test.514449128 | Feb 04 12:53:10 PM PST 24 | Feb 04 12:53:16 PM PST 24 | 64240676 ps | ||
| T552 | /workspace/coverage/default/29.rstmgr_stress_all.3960476387 | Feb 04 12:53:20 PM PST 24 | Feb 04 12:53:31 PM PST 24 | 1858128385 ps | ||
| T553 | /workspace/coverage/default/11.rstmgr_alert_test.3429142979 | Feb 04 12:52:17 PM PST 24 | Feb 04 12:52:20 PM PST 24 | 78278638 ps | ||
| T554 | /workspace/coverage/default/26.rstmgr_smoke.2975924898 | Feb 04 12:53:14 PM PST 24 | Feb 04 12:53:16 PM PST 24 | 256821093 ps | ||
| T555 | /workspace/coverage/default/27.rstmgr_smoke.651541069 | Feb 04 12:53:13 PM PST 24 | Feb 04 12:53:16 PM PST 24 | 128207261 ps | ||
| T556 | /workspace/coverage/default/12.rstmgr_sw_rst.2572711272 | Feb 04 12:52:19 PM PST 24 | Feb 04 12:52:22 PM PST 24 | 122981256 ps | ||
| T557 | /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1913771429 | Feb 04 12:52:03 PM PST 24 | Feb 04 12:52:07 PM PST 24 | 243867972 ps | ||
| T558 | /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4004860138 | Feb 04 12:53:40 PM PST 24 | Feb 04 12:53:43 PM PST 24 | 139330102 ps | ||
| T559 | /workspace/coverage/default/42.rstmgr_stress_all.2343432183 | Feb 04 12:53:45 PM PST 24 | Feb 04 12:53:58 PM PST 24 | 2651138670 ps | ||
| T560 | /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1534273424 | Feb 04 12:53:19 PM PST 24 | Feb 04 12:53:29 PM PST 24 | 1891790380 ps | ||
| T561 | /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3170147935 | Feb 04 12:53:47 PM PST 24 | Feb 04 12:53:58 PM PST 24 | 2365127964 ps | ||
| T562 | /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3662570297 | Feb 04 12:53:17 PM PST 24 | Feb 04 12:53:21 PM PST 24 | 244110431 ps | ||
| T563 | /workspace/coverage/default/39.rstmgr_sw_rst.2811928037 | Feb 04 12:53:54 PM PST 24 | Feb 04 12:54:01 PM PST 24 | 127773117 ps | ||
| T564 | /workspace/coverage/default/39.rstmgr_alert_test.745221478 | Feb 04 12:53:54 PM PST 24 | Feb 04 12:54:00 PM PST 24 | 68818188 ps | ||
| T565 | /workspace/coverage/default/33.rstmgr_reset.1091944941 | Feb 04 12:53:19 PM PST 24 | Feb 04 12:53:25 PM PST 24 | 688700992 ps | ||
| T566 | /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.60671851 | Feb 04 12:53:44 PM PST 24 | Feb 04 12:53:48 PM PST 24 | 105153263 ps | ||
| T567 | /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.914534162 | Feb 04 12:52:20 PM PST 24 | Feb 04 12:52:24 PM PST 24 | 125414044 ps | ||
| T568 | /workspace/coverage/default/48.rstmgr_smoke.3435690657 | Feb 04 12:53:48 PM PST 24 | Feb 04 12:53:52 PM PST 24 | 186620871 ps | ||
| T569 | /workspace/coverage/default/38.rstmgr_reset.1876583925 | Feb 04 12:53:44 PM PST 24 | Feb 04 12:53:54 PM PST 24 | 1959209570 ps | ||
| T570 | /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.675748701 | Feb 04 12:53:50 PM PST 24 | Feb 04 12:53:53 PM PST 24 | 101121492 ps | ||
| T571 | /workspace/coverage/default/35.rstmgr_sw_rst.1752152229 | Feb 04 12:53:14 PM PST 24 | Feb 04 12:53:17 PM PST 24 | 146746165 ps | ||
| T572 | /workspace/coverage/default/29.rstmgr_sw_rst.1374729073 | Feb 04 12:53:16 PM PST 24 | Feb 04 12:53:20 PM PST 24 | 140538293 ps | ||
| T573 | /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3829585047 | Feb 04 12:52:36 PM PST 24 | Feb 04 12:52:40 PM PST 24 | 184318286 ps | ||
| T574 | /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3468898239 | Feb 04 12:53:52 PM PST 24 | Feb 04 12:53:59 PM PST 24 | 102572152 ps | ||
| T575 | /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2352301047 | Feb 04 12:53:19 PM PST 24 | Feb 04 12:53:22 PM PST 24 | 246707299 ps | ||
| T576 | /workspace/coverage/default/37.rstmgr_smoke.1979287906 | Feb 04 12:53:40 PM PST 24 | Feb 04 12:53:42 PM PST 24 | 124330628 ps | ||
| T577 | /workspace/coverage/default/18.rstmgr_sw_rst.481321127 | Feb 04 12:52:39 PM PST 24 | Feb 04 12:52:44 PM PST 24 | 539077418 ps | ||
| T578 | /workspace/coverage/default/17.rstmgr_reset.4242641135 | Feb 04 12:52:33 PM PST 24 | Feb 04 12:52:39 PM PST 24 | 1515376252 ps | ||
| T579 | /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1318582283 | Feb 04 12:52:22 PM PST 24 | Feb 04 12:52:33 PM PST 24 | 2355083422 ps | ||
| T580 | /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1011876090 | Feb 04 12:53:46 PM PST 24 | Feb 04 12:53:55 PM PST 24 | 1884469836 ps | ||
| T581 | /workspace/coverage/default/22.rstmgr_sw_rst.2690861809 | Feb 04 12:52:37 PM PST 24 | Feb 04 12:52:40 PM PST 24 | 141361999 ps | ||
| T582 | /workspace/coverage/default/12.rstmgr_reset.3978370911 | Feb 04 12:52:21 PM PST 24 | Feb 04 12:52:29 PM PST 24 | 1075033360 ps | ||
| T583 | /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.939336520 | Feb 04 12:52:40 PM PST 24 | Feb 04 12:52:43 PM PST 24 | 152333097 ps | ||
| T584 | /workspace/coverage/default/47.rstmgr_alert_test.2766451248 | Feb 04 12:53:40 PM PST 24 | Feb 04 12:53:42 PM PST 24 | 73399776 ps | ||
| T585 | /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3841194851 | Feb 04 12:53:20 PM PST 24 | Feb 04 12:53:24 PM PST 24 | 154788047 ps | ||
| T586 | /workspace/coverage/default/44.rstmgr_sw_rst.1024255350 | Feb 04 12:53:56 PM PST 24 | Feb 04 12:54:01 PM PST 24 | 115536561 ps | ||
| T587 | /workspace/coverage/default/3.rstmgr_reset.765192223 | Feb 04 12:51:56 PM PST 24 | Feb 04 12:52:05 PM PST 24 | 1772052072 ps | ||
| T588 | /workspace/coverage/default/39.rstmgr_smoke.2765738536 | Feb 04 12:53:45 PM PST 24 | Feb 04 12:53:48 PM PST 24 | 197786909 ps | ||
| T589 | /workspace/coverage/default/3.rstmgr_sw_rst.215389217 | Feb 04 12:52:09 PM PST 24 | Feb 04 12:52:16 PM PST 24 | 353154961 ps | ||
| T590 | /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2705439443 | Feb 04 12:53:38 PM PST 24 | Feb 04 12:53:41 PM PST 24 | 245325066 ps | ||
| T591 | /workspace/coverage/default/20.rstmgr_alert_test.4159303823 | Feb 04 12:52:36 PM PST 24 | Feb 04 12:52:38 PM PST 24 | 71032975 ps | ||
| T592 | /workspace/coverage/default/16.rstmgr_sw_rst.1609067681 | Feb 04 12:52:34 PM PST 24 | Feb 04 12:52:38 PM PST 24 | 260916956 ps | ||
| T593 | /workspace/coverage/default/7.rstmgr_smoke.3072813403 | Feb 04 12:52:20 PM PST 24 | Feb 04 12:52:24 PM PST 24 | 246772988 ps | ||
| T594 | /workspace/coverage/default/4.rstmgr_sw_rst.2204427079 | Feb 04 12:51:58 PM PST 24 | Feb 04 12:52:03 PM PST 24 | 413283038 ps | ||
| T595 | /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1797841634 | Feb 04 12:52:21 PM PST 24 | Feb 04 12:52:24 PM PST 24 | 244329389 ps | ||
| T596 | /workspace/coverage/default/33.rstmgr_stress_all.2726506754 | Feb 04 12:53:17 PM PST 24 | Feb 04 12:53:40 PM PST 24 | 4814646880 ps | ||
| T597 | /workspace/coverage/default/15.rstmgr_por_stretcher.3044581993 | Feb 04 12:52:25 PM PST 24 | Feb 04 12:52:32 PM PST 24 | 104369469 ps | ||
| T598 | /workspace/coverage/default/41.rstmgr_por_stretcher.1347448987 | Feb 04 12:53:57 PM PST 24 | Feb 04 12:54:00 PM PST 24 | 78484994 ps | ||
| T599 | /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3424396751 | Feb 04 12:52:50 PM PST 24 | Feb 04 12:52:52 PM PST 24 | 88989719 ps | ||
| T600 | /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2913510984 | Feb 04 12:53:44 PM PST 24 | Feb 04 12:53:46 PM PST 24 | 101954131 ps | ||
| T601 | /workspace/coverage/default/41.rstmgr_smoke.2524665068 | Feb 04 12:53:40 PM PST 24 | Feb 04 12:53:43 PM PST 24 | 254282315 ps | ||
| T602 | /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3954292748 | Feb 04 12:53:15 PM PST 24 | Feb 04 12:53:18 PM PST 24 | 113454288 ps | ||
| T603 | /workspace/coverage/default/7.rstmgr_alert_test.1001453712 | Feb 04 12:52:16 PM PST 24 | Feb 04 12:52:19 PM PST 24 | 73996650 ps | ||
| T604 | /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3551261274 | Feb 04 12:53:46 PM PST 24 | Feb 04 12:53:50 PM PST 24 | 246497232 ps | ||
| T605 | /workspace/coverage/default/6.rstmgr_smoke.4200805947 | Feb 04 12:51:59 PM PST 24 | Feb 04 12:52:04 PM PST 24 | 187792239 ps | ||
| T606 | /workspace/coverage/default/47.rstmgr_por_stretcher.2684551993 | Feb 04 12:53:37 PM PST 24 | Feb 04 12:53:39 PM PST 24 | 106522277 ps | ||
| T68 | /workspace/coverage/default/0.rstmgr_sec_cm.4046395590 | Feb 04 12:51:57 PM PST 24 | Feb 04 12:52:14 PM PST 24 | 9084277017 ps | ||
| T607 | /workspace/coverage/default/15.rstmgr_sw_rst.1227719360 | Feb 04 12:52:21 PM PST 24 | Feb 04 12:52:26 PM PST 24 | 293482902 ps | ||
| T608 | /workspace/coverage/default/34.rstmgr_alert_test.1855294317 | Feb 04 12:53:19 PM PST 24 | Feb 04 12:53:22 PM PST 24 | 77081645 ps | ||
| T609 | /workspace/coverage/default/45.rstmgr_sw_rst.701089502 | Feb 04 12:53:58 PM PST 24 | Feb 04 12:54:05 PM PST 24 | 430324069 ps | ||
| T610 | /workspace/coverage/default/7.rstmgr_por_stretcher.580514020 | Feb 04 12:52:10 PM PST 24 | Feb 04 12:52:14 PM PST 24 | 250946212 ps | ||
| T611 | /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2704947530 | Feb 04 12:51:57 PM PST 24 | Feb 04 12:52:01 PM PST 24 | 152533815 ps | ||
| T612 | /workspace/coverage/default/21.rstmgr_reset.622223230 | Feb 04 12:52:37 PM PST 24 | Feb 04 12:52:45 PM PST 24 | 1499747485 ps | ||
| T613 | /workspace/coverage/default/7.rstmgr_reset.2559861300 | Feb 04 12:52:15 PM PST 24 | Feb 04 12:52:21 PM PST 24 | 871326414 ps | ||
| T614 | /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2574104556 | Feb 04 12:52:15 PM PST 24 | Feb 04 12:52:19 PM PST 24 | 166036728 ps | ||
| T615 | /workspace/coverage/default/10.rstmgr_alert_test.680337726 | Feb 04 12:52:22 PM PST 24 | Feb 04 12:52:26 PM PST 24 | 84078889 ps | ||
| T616 | /workspace/coverage/default/48.rstmgr_sw_rst.433313798 | Feb 04 12:53:41 PM PST 24 | Feb 04 12:53:44 PM PST 24 | 139982003 ps | ||
| T617 | /workspace/coverage/default/1.rstmgr_por_stretcher.2076511589 | Feb 04 12:53:57 PM PST 24 | Feb 04 12:54:01 PM PST 24 | 169070742 ps | ||
| T618 | /workspace/coverage/default/13.rstmgr_por_stretcher.2727458304 | Feb 04 12:52:14 PM PST 24 | Feb 04 12:52:17 PM PST 24 | 213530790 ps | ||
| T619 | /workspace/coverage/default/37.rstmgr_por_stretcher.3660732472 | Feb 04 12:53:39 PM PST 24 | Feb 04 12:53:41 PM PST 24 | 201779212 ps | ||
| T620 | /workspace/coverage/default/46.rstmgr_smoke.568683450 | Feb 04 12:53:39 PM PST 24 | Feb 04 12:53:41 PM PST 24 | 111998697 ps |
| Test location | /workspace/coverage/default/9.rstmgr_smoke.932658607 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 121694518 ps |
| CPU time | 1.15 seconds |
| Started | Feb 04 12:52:06 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 200220 kb |
| Host | smart-0e841e14-5cde-4b80-8f03-3df53fa893be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932658607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.932658607 |
| Directory | /workspace/9.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sw_rst.3840920113 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 143203703 ps |
| CPU time | 1.96 seconds |
| Started | Feb 04 12:52:42 PM PST 24 |
| Finished | Feb 04 12:52:45 PM PST 24 |
| Peak memory | 200076 kb |
| Host | smart-9167b315-b8e5-48e7-86dd-57004049b253 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840920113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3840920113 |
| Directory | /workspace/17.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/14.rstmgr_stress_all.3174177498 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 12552249509 ps |
| CPU time | 42.3 seconds |
| Started | Feb 04 12:52:19 PM PST 24 |
| Finished | Feb 04 12:53:04 PM PST 24 |
| Peak memory | 200208 kb |
| Host | smart-696c9c5e-6788-4515-a4a5-cbc987099d71 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174177498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3174177498 |
| Directory | /workspace/14.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1944744030 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 496196824 ps |
| CPU time | 1.95 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:03 PM PST 24 |
| Peak memory | 200484 kb |
| Host | smart-77fe2b31-1465-4c93-9c10-38c6e34ae307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944744030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err .1944744030 |
| Directory | /workspace/6.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sec_cm.1222547980 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 16537989591 ps |
| CPU time | 26.71 seconds |
| Started | Feb 04 12:51:53 PM PST 24 |
| Finished | Feb 04 12:52:22 PM PST 24 |
| Peak memory | 217992 kb |
| Host | smart-74544d3e-76fb-4911-a931-b86be66bfc16 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222547980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1222547980 |
| Directory | /workspace/1.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.926192908 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 113730711 ps |
| CPU time | 1.61 seconds |
| Started | Feb 04 12:36:46 PM PST 24 |
| Finished | Feb 04 12:36:51 PM PST 24 |
| Peak memory | 200600 kb |
| Host | smart-b1965af2-f21b-4e99-95b2-ca4d3bc70fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926192908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.926192908 |
| Directory | /workspace/4.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3857147798 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2359803002 ps |
| CPU time | 9.27 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:27 PM PST 24 |
| Peak memory | 217120 kb |
| Host | smart-30836bab-933d-48dd-b45a-809b673fcf8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857147798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3857147798 |
| Directory | /workspace/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/32.rstmgr_stress_all.2025337910 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 4875813468 ps |
| CPU time | 23.67 seconds |
| Started | Feb 04 12:53:23 PM PST 24 |
| Finished | Feb 04 12:53:51 PM PST 24 |
| Peak memory | 200288 kb |
| Host | smart-dca84d5f-0ad3-4168-b335-8a958d6613fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025337910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2025337910 |
| Directory | /workspace/32.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2625443714 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 113448145 ps |
| CPU time | 1.02 seconds |
| Started | Feb 04 12:51:59 PM PST 24 |
| Finished | Feb 04 12:52:04 PM PST 24 |
| Peak memory | 200132 kb |
| Host | smart-aaf7d81a-5f12-4e4e-89c5-7cccde65109b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625443714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2625443714 |
| Directory | /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3988259205 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 890878040 ps |
| CPU time | 3.1 seconds |
| Started | Feb 04 12:36:59 PM PST 24 |
| Finished | Feb 04 12:37:11 PM PST 24 |
| Peak memory | 200556 kb |
| Host | smart-b741aea4-3e17-4125-8e35-ca9a702731a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988259205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er r.3988259205 |
| Directory | /workspace/14.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/28.rstmgr_alert_test.2199526963 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 128916500 ps |
| CPU time | 0.85 seconds |
| Started | Feb 04 12:53:22 PM PST 24 |
| Finished | Feb 04 12:53:27 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-54cc03b3-27b0-457f-9363-dd1095ee31ea |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199526963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2199526963 |
| Directory | /workspace/28.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.723721491 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1217994262 ps |
| CPU time | 5.49 seconds |
| Started | Feb 04 12:53:18 PM PST 24 |
| Finished | Feb 04 12:53:26 PM PST 24 |
| Peak memory | 217332 kb |
| Host | smart-91c1c28f-a033-49a4-b9fd-7dbb358b1e2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=723721491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.723721491 |
| Directory | /workspace/34.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1204796672 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 155358028 ps |
| CPU time | 2.12 seconds |
| Started | Feb 04 12:36:51 PM PST 24 |
| Finished | Feb 04 12:37:00 PM PST 24 |
| Peak memory | 200624 kb |
| Host | smart-1b26e649-6841-4311-b69d-a2ef90afed9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204796672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1204796672 |
| Directory | /workspace/8.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1786291249 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 918866678 ps |
| CPU time | 2.93 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:04 PM PST 24 |
| Peak memory | 200568 kb |
| Host | smart-b8553bc4-dc97-4010-ad88-16a1422d741c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786291249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err .1786291249 |
| Directory | /workspace/7.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1452596651 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 129371471 ps |
| CPU time | 1.09 seconds |
| Started | Feb 04 12:37:08 PM PST 24 |
| Finished | Feb 04 12:37:19 PM PST 24 |
| Peak memory | 200232 kb |
| Host | smart-2ff37835-d80d-4746-9da1-285363f6d5d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452596651 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1452596651 |
| Directory | /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1184644703 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1231756105 ps |
| CPU time | 5.69 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:47 PM PST 24 |
| Peak memory | 221992 kb |
| Host | smart-a74ab3a6-3cd2-4bbd-82ea-00ce68ec89b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184644703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1184644703 |
| Directory | /workspace/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2949123953 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 192831127 ps |
| CPU time | 1.46 seconds |
| Started | Feb 04 12:36:58 PM PST 24 |
| Finished | Feb 04 12:37:09 PM PST 24 |
| Peak memory | 200648 kb |
| Host | smart-cc16ef4f-540f-48c0-a1c4-2f5f3672ff40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949123953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s ame_csr_outstanding.2949123953 |
| Directory | /workspace/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.rstmgr_por_stretcher.1221448444 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 215616003 ps |
| CPU time | 0.9 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199740 kb |
| Host | smart-04c5bdb9-a9f9-4ebf-a617-1bbf28af4ec8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221448444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1221448444 |
| Directory | /workspace/0.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2655598593 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 244485783 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:52:17 PM PST 24 |
| Finished | Feb 04 12:52:20 PM PST 24 |
| Peak memory | 217144 kb |
| Host | smart-60da7da3-f7e2-4957-91ae-1415214e79d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655598593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2655598593 |
| Directory | /workspace/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3265356853 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 800116822 ps |
| CPU time | 2.72 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:07 PM PST 24 |
| Peak memory | 200556 kb |
| Host | smart-83e7b026-bf7e-485d-a309-ed5f3d757f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265356853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er r.3265356853 |
| Directory | /workspace/10.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.211178809 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 786825207 ps |
| CPU time | 2.64 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:07 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-e25c9386-08a1-4354-9c80-e0107f9ff2df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211178809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err. 211178809 |
| Directory | /workspace/9.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3647067761 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 214367381 ps |
| CPU time | 1.59 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:53 PM PST 24 |
| Peak memory | 200636 kb |
| Host | smart-72325039-4d83-420a-9990-dec358628069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647067761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3 647067761 |
| Directory | /workspace/0.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1807571545 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1180462004 ps |
| CPU time | 5.21 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:57 PM PST 24 |
| Peak memory | 200688 kb |
| Host | smart-c6482550-c1c0-44e6-9928-74425ee756d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807571545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1 807571545 |
| Directory | /workspace/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3043704797 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 82942874 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:36:45 PM PST 24 |
| Finished | Feb 04 12:36:49 PM PST 24 |
| Peak memory | 200348 kb |
| Host | smart-3c6afe32-0f97-453c-ae0b-a792caf7d8cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043704797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3 043704797 |
| Directory | /workspace/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1101113354 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 123904206 ps |
| CPU time | 1.03 seconds |
| Started | Feb 04 12:36:46 PM PST 24 |
| Finished | Feb 04 12:36:50 PM PST 24 |
| Peak memory | 200380 kb |
| Host | smart-bb02e397-d108-4b64-b14c-07f6bac1b2ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101113354 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1101113354 |
| Directory | /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3326917532 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 84533686 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:36:39 PM PST 24 |
| Finished | Feb 04 12:36:40 PM PST 24 |
| Peak memory | 200352 kb |
| Host | smart-b76e2679-6f68-407e-bee1-b8e1604a930c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326917532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3326917532 |
| Directory | /workspace/0.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1331813484 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 270156612 ps |
| CPU time | 1.63 seconds |
| Started | Feb 04 12:36:46 PM PST 24 |
| Finished | Feb 04 12:36:51 PM PST 24 |
| Peak memory | 200528 kb |
| Host | smart-985956bc-c618-4485-b97f-a9911eb46c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331813484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa me_csr_outstanding.1331813484 |
| Directory | /workspace/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1605377467 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 564327530 ps |
| CPU time | 4.13 seconds |
| Started | Feb 04 12:36:47 PM PST 24 |
| Finished | Feb 04 12:36:55 PM PST 24 |
| Peak memory | 200712 kb |
| Host | smart-363b262c-2182-475f-93ce-40f75816704e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605377467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1605377467 |
| Directory | /workspace/0.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.136001267 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 925283310 ps |
| CPU time | 3.14 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:55 PM PST 24 |
| Peak memory | 200484 kb |
| Host | smart-35e99d88-12a8-45c6-a74d-81c75b5cc2a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136001267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err. 136001267 |
| Directory | /workspace/0.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4010442159 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 432780806 ps |
| CPU time | 2.43 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:55 PM PST 24 |
| Peak memory | 200528 kb |
| Host | smart-59c829be-cb0a-4959-bb09-5b4fde82dc0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010442159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.4 010442159 |
| Directory | /workspace/1.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1890852054 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 272613881 ps |
| CPU time | 3.11 seconds |
| Started | Feb 04 12:36:41 PM PST 24 |
| Finished | Feb 04 12:36:48 PM PST 24 |
| Peak memory | 200724 kb |
| Host | smart-4dfa57ab-5ffc-4224-ab63-f1675f96ba23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890852054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1 890852054 |
| Directory | /workspace/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1624700969 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 128279988 ps |
| CPU time | 0.88 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:53 PM PST 24 |
| Peak memory | 200372 kb |
| Host | smart-a17eb872-ae31-45ba-84fb-23b9e8a40abb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624700969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1 624700969 |
| Directory | /workspace/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1049057666 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 96582543 ps |
| CPU time | 0.94 seconds |
| Started | Feb 04 12:36:51 PM PST 24 |
| Finished | Feb 04 12:36:59 PM PST 24 |
| Peak memory | 200416 kb |
| Host | smart-0b8f73d8-6cae-48cc-adfb-17a2f1fe065a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049057666 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1049057666 |
| Directory | /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.96902328 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 70153395 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:53 PM PST 24 |
| Peak memory | 200392 kb |
| Host | smart-f573c615-3af3-453e-a15e-b00e4812f788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96902328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.96902328 |
| Directory | /workspace/1.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3688921855 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 135539320 ps |
| CPU time | 1.18 seconds |
| Started | Feb 04 12:36:51 PM PST 24 |
| Finished | Feb 04 12:36:58 PM PST 24 |
| Peak memory | 200576 kb |
| Host | smart-4206b828-6953-4b42-9096-d7ddb34cb4ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688921855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa me_csr_outstanding.3688921855 |
| Directory | /workspace/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1276835046 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 186413639 ps |
| CPU time | 2.67 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:55 PM PST 24 |
| Peak memory | 200580 kb |
| Host | smart-27d897e1-d52a-4283-9749-ad2e627c1087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276835046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1276835046 |
| Directory | /workspace/1.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.336694964 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 941530587 ps |
| CPU time | 3.15 seconds |
| Started | Feb 04 12:36:46 PM PST 24 |
| Finished | Feb 04 12:36:52 PM PST 24 |
| Peak memory | 200552 kb |
| Host | smart-76190391-3db7-458e-96d1-f5f1b1538c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336694964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err. 336694964 |
| Directory | /workspace/1.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1091617460 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 124106586 ps |
| CPU time | 0.96 seconds |
| Started | Feb 04 12:36:56 PM PST 24 |
| Finished | Feb 04 12:37:06 PM PST 24 |
| Peak memory | 200312 kb |
| Host | smart-90d844bc-5ae7-4eed-bd9d-ccf4aab9980b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091617460 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1091617460 |
| Directory | /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3225603159 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 75397459 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:37:01 PM PST 24 |
| Finished | Feb 04 12:37:14 PM PST 24 |
| Peak memory | 200360 kb |
| Host | smart-1f85dca8-efeb-4e41-b169-72973f9252d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225603159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3225603159 |
| Directory | /workspace/10.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1369893875 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 118414446 ps |
| CPU time | 0.98 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200396 kb |
| Host | smart-46c3f597-ab51-45df-a110-b16c14bb4e8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369893875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s ame_csr_outstanding.1369893875 |
| Directory | /workspace/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2476571359 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 214858616 ps |
| CPU time | 1.84 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:02 PM PST 24 |
| Peak memory | 200352 kb |
| Host | smart-21a36430-b447-407e-857e-f804f709d6c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476571359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2476571359 |
| Directory | /workspace/10.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1627250922 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 172022350 ps |
| CPU time | 1.18 seconds |
| Started | Feb 04 12:36:56 PM PST 24 |
| Finished | Feb 04 12:37:06 PM PST 24 |
| Peak memory | 200416 kb |
| Host | smart-bd49ee21-ddf7-4c83-8884-55c714e69b99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627250922 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1627250922 |
| Directory | /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.373323028 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 73147341 ps |
| CPU time | 0.75 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:53 PM PST 24 |
| Peak memory | 200348 kb |
| Host | smart-4a3429af-05b4-468f-8153-8385abbcf19f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373323028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.373323028 |
| Directory | /workspace/11.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1666748081 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 100827527 ps |
| CPU time | 1.23 seconds |
| Started | Feb 04 12:36:56 PM PST 24 |
| Finished | Feb 04 12:37:06 PM PST 24 |
| Peak memory | 200300 kb |
| Host | smart-bcade96e-b762-4d22-93a9-b160667c609e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666748081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1666748081 |
| Directory | /workspace/11.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2767144499 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 832086886 ps |
| CPU time | 2.69 seconds |
| Started | Feb 04 12:36:56 PM PST 24 |
| Finished | Feb 04 12:37:08 PM PST 24 |
| Peak memory | 200504 kb |
| Host | smart-28de0a9a-f79d-4b96-98cd-49905b767ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767144499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er r.2767144499 |
| Directory | /workspace/11.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2330206686 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 147073775 ps |
| CPU time | 1.29 seconds |
| Started | Feb 04 12:36:58 PM PST 24 |
| Finished | Feb 04 12:37:09 PM PST 24 |
| Peak memory | 200592 kb |
| Host | smart-10560f85-ed04-4450-a150-71be99ca4009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330206686 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2330206686 |
| Directory | /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1550686035 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 104233942 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200336 kb |
| Host | smart-efc089c6-9bc3-4d66-ac04-b4e8865ab7a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550686035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1550686035 |
| Directory | /workspace/12.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1167068186 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 128203580 ps |
| CPU time | 1.01 seconds |
| Started | Feb 04 12:37:00 PM PST 24 |
| Finished | Feb 04 12:37:11 PM PST 24 |
| Peak memory | 200368 kb |
| Host | smart-acc18820-051e-48de-9328-b01e34949b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167068186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s ame_csr_outstanding.1167068186 |
| Directory | /workspace/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2762337208 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 247566566 ps |
| CPU time | 1.73 seconds |
| Started | Feb 04 12:36:57 PM PST 24 |
| Finished | Feb 04 12:37:08 PM PST 24 |
| Peak memory | 200528 kb |
| Host | smart-d7dd004d-50f8-470a-9b9d-d2877bb724d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762337208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2762337208 |
| Directory | /workspace/12.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3280818007 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 463198513 ps |
| CPU time | 1.94 seconds |
| Started | Feb 04 12:36:58 PM PST 24 |
| Finished | Feb 04 12:37:09 PM PST 24 |
| Peak memory | 200532 kb |
| Host | smart-ba158643-97da-4114-921b-058f1fbbc60f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280818007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er r.3280818007 |
| Directory | /workspace/12.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1029654559 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 124249739 ps |
| CPU time | 1 seconds |
| Started | Feb 04 12:36:54 PM PST 24 |
| Finished | Feb 04 12:37:03 PM PST 24 |
| Peak memory | 200388 kb |
| Host | smart-79671d8b-16ce-44ea-b01d-1c6c55a85489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029654559 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1029654559 |
| Directory | /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3314605987 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 74790522 ps |
| CPU time | 0.78 seconds |
| Started | Feb 04 12:37:02 PM PST 24 |
| Finished | Feb 04 12:37:14 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-7c829b2c-3a67-485a-8559-43e6c3945fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314605987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3314605987 |
| Directory | /workspace/13.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4062975880 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 97864665 ps |
| CPU time | 1.23 seconds |
| Started | Feb 04 12:37:08 PM PST 24 |
| Finished | Feb 04 12:37:19 PM PST 24 |
| Peak memory | 200268 kb |
| Host | smart-2af6cdcd-fbd4-4913-8894-b647589a7c27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062975880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s ame_csr_outstanding.4062975880 |
| Directory | /workspace/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2783269322 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 175621979 ps |
| CPU time | 2.41 seconds |
| Started | Feb 04 12:36:59 PM PST 24 |
| Finished | Feb 04 12:37:10 PM PST 24 |
| Peak memory | 200580 kb |
| Host | smart-15531cff-7d1e-4354-ac38-2ebe367d0a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783269322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2783269322 |
| Directory | /workspace/13.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2787140516 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 413325951 ps |
| CPU time | 1.73 seconds |
| Started | Feb 04 12:36:58 PM PST 24 |
| Finished | Feb 04 12:37:09 PM PST 24 |
| Peak memory | 200524 kb |
| Host | smart-2720be6e-d054-4bdd-9b46-8a1dc83474bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787140516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er r.2787140516 |
| Directory | /workspace/13.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3346271627 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 65190066 ps |
| CPU time | 0.86 seconds |
| Started | Feb 04 12:36:54 PM PST 24 |
| Finished | Feb 04 12:37:04 PM PST 24 |
| Peak memory | 200380 kb |
| Host | smart-eab47762-28b7-4ae5-8051-fcce76dd9786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346271627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3346271627 |
| Directory | /workspace/14.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3998191314 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 110121118 ps |
| CPU time | 1.33 seconds |
| Started | Feb 04 12:37:10 PM PST 24 |
| Finished | Feb 04 12:37:27 PM PST 24 |
| Peak memory | 200604 kb |
| Host | smart-6aa48f1c-2a6e-4f51-9985-2929b040dc45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998191314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s ame_csr_outstanding.3998191314 |
| Directory | /workspace/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.257849925 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 92902589 ps |
| CPU time | 1.17 seconds |
| Started | Feb 04 12:37:08 PM PST 24 |
| Finished | Feb 04 12:37:19 PM PST 24 |
| Peak memory | 200460 kb |
| Host | smart-094e07a9-f695-4968-8052-207f16e542cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257849925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.257849925 |
| Directory | /workspace/14.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3223039390 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 181149949 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:36:59 PM PST 24 |
| Finished | Feb 04 12:37:09 PM PST 24 |
| Peak memory | 200392 kb |
| Host | smart-10949102-8168-435d-bdcf-e3d90eeb1ab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223039390 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3223039390 |
| Directory | /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3763879113 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 78487207 ps |
| CPU time | 0.8 seconds |
| Started | Feb 04 12:37:08 PM PST 24 |
| Finished | Feb 04 12:37:19 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-6662c72b-b298-410a-bfd0-286074e60977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763879113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3763879113 |
| Directory | /workspace/15.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2392154212 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 136703092 ps |
| CPU time | 1.34 seconds |
| Started | Feb 04 12:37:03 PM PST 24 |
| Finished | Feb 04 12:37:15 PM PST 24 |
| Peak memory | 200668 kb |
| Host | smart-8d2d0323-5f6b-48e0-b43e-f36e45564da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392154212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s ame_csr_outstanding.2392154212 |
| Directory | /workspace/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3310244571 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 534661654 ps |
| CPU time | 3.6 seconds |
| Started | Feb 04 12:36:59 PM PST 24 |
| Finished | Feb 04 12:37:12 PM PST 24 |
| Peak memory | 208776 kb |
| Host | smart-b4e4f449-e14c-4d40-811b-e2bb8c0c82c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310244571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3310244571 |
| Directory | /workspace/15.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2722268090 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 497836401 ps |
| CPU time | 1.93 seconds |
| Started | Feb 04 12:37:10 PM PST 24 |
| Finished | Feb 04 12:37:27 PM PST 24 |
| Peak memory | 200616 kb |
| Host | smart-e75fa423-71ff-4cad-bc32-d060ca7baf16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722268090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er r.2722268090 |
| Directory | /workspace/15.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2345848140 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 110072838 ps |
| CPU time | 1.1 seconds |
| Started | Feb 04 12:37:04 PM PST 24 |
| Finished | Feb 04 12:37:16 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-5703f82b-d4b3-4280-aff9-267aa66130d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345848140 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2345848140 |
| Directory | /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2512200345 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 67206675 ps |
| CPU time | 0.76 seconds |
| Started | Feb 04 12:36:59 PM PST 24 |
| Finished | Feb 04 12:37:09 PM PST 24 |
| Peak memory | 200352 kb |
| Host | smart-3153b145-66cd-4677-b3b2-7c0de359cc3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512200345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2512200345 |
| Directory | /workspace/16.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2149075757 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 84247648 ps |
| CPU time | 0.89 seconds |
| Started | Feb 04 12:37:03 PM PST 24 |
| Finished | Feb 04 12:37:15 PM PST 24 |
| Peak memory | 200328 kb |
| Host | smart-f5bc9212-8687-4408-b5fb-4d0643d9f7b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149075757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s ame_csr_outstanding.2149075757 |
| Directory | /workspace/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3248887923 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 177414728 ps |
| CPU time | 2.47 seconds |
| Started | Feb 04 12:37:08 PM PST 24 |
| Finished | Feb 04 12:37:20 PM PST 24 |
| Peak memory | 200688 kb |
| Host | smart-ce7ac391-d87b-46d2-9f5c-681b31667f61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248887923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3248887923 |
| Directory | /workspace/16.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1709081115 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 473442138 ps |
| CPU time | 1.85 seconds |
| Started | Feb 04 12:36:56 PM PST 24 |
| Finished | Feb 04 12:37:07 PM PST 24 |
| Peak memory | 200632 kb |
| Host | smart-fce891e3-2961-4b22-af3d-7c065ee38067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709081115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er r.1709081115 |
| Directory | /workspace/16.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2347803914 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 179124389 ps |
| CPU time | 1.17 seconds |
| Started | Feb 04 12:37:04 PM PST 24 |
| Finished | Feb 04 12:37:16 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-570a1aa7-fc1e-42a3-9ece-a9b8d90b5bf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347803914 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2347803914 |
| Directory | /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2180652926 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 57149879 ps |
| CPU time | 0.85 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200372 kb |
| Host | smart-3fccbf9e-9efe-4ff0-84c8-da8dd9055f36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180652926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2180652926 |
| Directory | /workspace/17.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.331845492 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 158367490 ps |
| CPU time | 1.1 seconds |
| Started | Feb 04 12:37:00 PM PST 24 |
| Finished | Feb 04 12:37:11 PM PST 24 |
| Peak memory | 200368 kb |
| Host | smart-5cace1b5-578c-4673-9bfe-9f641a36052b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331845492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa me_csr_outstanding.331845492 |
| Directory | /workspace/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2120763670 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 500450415 ps |
| CPU time | 3.67 seconds |
| Started | Feb 04 12:37:03 PM PST 24 |
| Finished | Feb 04 12:37:18 PM PST 24 |
| Peak memory | 200560 kb |
| Host | smart-fab84222-deaf-4dae-839c-ca14c8aabe7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120763670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2120763670 |
| Directory | /workspace/17.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2295197255 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 493071645 ps |
| CPU time | 1.97 seconds |
| Started | Feb 04 12:37:09 PM PST 24 |
| Finished | Feb 04 12:37:26 PM PST 24 |
| Peak memory | 200484 kb |
| Host | smart-e03c8572-d013-423d-a3ba-7f545b11ec8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295197255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er r.2295197255 |
| Directory | /workspace/17.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3566313671 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 95992656 ps |
| CPU time | 0.95 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:01 PM PST 24 |
| Peak memory | 200140 kb |
| Host | smart-130993ad-e229-4426-adc2-0db72ed786f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566313671 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3566313671 |
| Directory | /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4247378206 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 72122677 ps |
| CPU time | 0.75 seconds |
| Started | Feb 04 12:36:54 PM PST 24 |
| Finished | Feb 04 12:37:03 PM PST 24 |
| Peak memory | 200372 kb |
| Host | smart-167428af-521a-48a2-bbcb-80aff5d4daf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247378206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4247378206 |
| Directory | /workspace/18.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3265294540 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 134823690 ps |
| CPU time | 1.21 seconds |
| Started | Feb 04 12:37:08 PM PST 24 |
| Finished | Feb 04 12:37:19 PM PST 24 |
| Peak memory | 200528 kb |
| Host | smart-ab4a0541-54c3-4572-8d8a-9258df711751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265294540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s ame_csr_outstanding.3265294540 |
| Directory | /workspace/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.621567766 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 300699185 ps |
| CPU time | 2.22 seconds |
| Started | Feb 04 12:36:54 PM PST 24 |
| Finished | Feb 04 12:37:03 PM PST 24 |
| Peak memory | 200560 kb |
| Host | smart-761e36bf-f06f-4a9d-acaa-c44d4aea33d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621567766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.621567766 |
| Directory | /workspace/18.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2536084588 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 473710871 ps |
| CPU time | 1.78 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:03 PM PST 24 |
| Peak memory | 200552 kb |
| Host | smart-9330b0b4-079f-4efc-ac3d-14cae4478f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536084588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er r.2536084588 |
| Directory | /workspace/18.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1871171737 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 147997503 ps |
| CPU time | 0.99 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200392 kb |
| Host | smart-7c054fb9-3fd5-4ab1-8b53-287f30ec6c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871171737 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1871171737 |
| Directory | /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1861560257 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 62490571 ps |
| CPU time | 0.72 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:02 PM PST 24 |
| Peak memory | 200368 kb |
| Host | smart-be5b86ee-8688-4b74-90a0-1674bc34bb07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861560257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1861560257 |
| Directory | /workspace/19.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2876249916 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 114161519 ps |
| CPU time | 1.25 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:03 PM PST 24 |
| Peak memory | 200592 kb |
| Host | smart-9e101411-6ad6-4189-ac68-a25313966f58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876249916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s ame_csr_outstanding.2876249916 |
| Directory | /workspace/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3132405378 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 564291844 ps |
| CPU time | 3.56 seconds |
| Started | Feb 04 12:36:47 PM PST 24 |
| Finished | Feb 04 12:36:54 PM PST 24 |
| Peak memory | 200604 kb |
| Host | smart-9143e6b7-9681-4d82-8f96-191d01aa5ba0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132405378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3132405378 |
| Directory | /workspace/19.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3539379264 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 799029583 ps |
| CPU time | 2.73 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:04 PM PST 24 |
| Peak memory | 200536 kb |
| Host | smart-126a5177-d3e6-40ab-aafd-8dfbb94d3148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539379264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er r.3539379264 |
| Directory | /workspace/19.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2111118506 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 162784020 ps |
| CPU time | 1.96 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:06 PM PST 24 |
| Peak memory | 200600 kb |
| Host | smart-c17da3e4-4386-42ba-8794-b1c153143db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111118506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2 111118506 |
| Directory | /workspace/2.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2146203107 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 266072426 ps |
| CPU time | 3.16 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:03 PM PST 24 |
| Peak memory | 199924 kb |
| Host | smart-d2d15d3b-0d9d-4aea-89fd-f381d2982c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146203107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2 146203107 |
| Directory | /workspace/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1359795905 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 94447008 ps |
| CPU time | 0.76 seconds |
| Started | Feb 04 12:36:51 PM PST 24 |
| Finished | Feb 04 12:37:00 PM PST 24 |
| Peak memory | 200288 kb |
| Host | smart-df8ea0e0-1185-4624-8bcf-ec65aedb2a75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359795905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1 359795905 |
| Directory | /workspace/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2349588203 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 120821680 ps |
| CPU time | 0.92 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:53 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-8a9d485f-840d-4b7a-939c-1874aa322b32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349588203 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2349588203 |
| Directory | /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2742273448 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 73786674 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:00 PM PST 24 |
| Peak memory | 200312 kb |
| Host | smart-40661006-ae0e-4eca-84f9-79784b2ceed4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742273448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2742273448 |
| Directory | /workspace/2.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.471975176 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 126941567 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:36:50 PM PST 24 |
| Finished | Feb 04 12:36:57 PM PST 24 |
| Peak memory | 200352 kb |
| Host | smart-bc96ac3e-83ad-493c-8f9b-212601587f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471975176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam e_csr_outstanding.471975176 |
| Directory | /workspace/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3649719302 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 163455116 ps |
| CPU time | 2.14 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:55 PM PST 24 |
| Peak memory | 200712 kb |
| Host | smart-5d122b32-e853-4883-b7bd-095cf38b2dec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649719302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3649719302 |
| Directory | /workspace/2.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3507888997 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 435649377 ps |
| CPU time | 1.91 seconds |
| Started | Feb 04 12:36:49 PM PST 24 |
| Finished | Feb 04 12:36:55 PM PST 24 |
| Peak memory | 200476 kb |
| Host | smart-18e739f8-55e8-4fcf-9c4f-b19aa760cde6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507888997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err .3507888997 |
| Directory | /workspace/2.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2131471692 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 267613477 ps |
| CPU time | 1.65 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:06 PM PST 24 |
| Peak memory | 200580 kb |
| Host | smart-f21b7923-7ea8-4a10-9f60-b516b8224057 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131471692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2 131471692 |
| Directory | /workspace/3.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2609555398 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2299043217 ps |
| CPU time | 9.32 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:09 PM PST 24 |
| Peak memory | 200552 kb |
| Host | smart-0fe3832f-3b39-4474-aa3b-7f833547e46c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609555398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2 609555398 |
| Directory | /workspace/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2634523942 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 90700661 ps |
| CPU time | 0.76 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200348 kb |
| Host | smart-bc0891ee-f2a4-4640-8e05-a2130e4676a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634523942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2 634523942 |
| Directory | /workspace/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.34640410 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 144249086 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:36:54 PM PST 24 |
| Finished | Feb 04 12:37:02 PM PST 24 |
| Peak memory | 200372 kb |
| Host | smart-face2211-71f6-4cda-852d-beee9ac94f06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34640410 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.34640410 |
| Directory | /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1352284737 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 81950943 ps |
| CPU time | 0.79 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:00 PM PST 24 |
| Peak memory | 200348 kb |
| Host | smart-85758bf6-08e0-4a86-a58b-276214ca060b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352284737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1352284737 |
| Directory | /workspace/3.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.465837788 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 162820843 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:36:51 PM PST 24 |
| Finished | Feb 04 12:36:59 PM PST 24 |
| Peak memory | 200356 kb |
| Host | smart-f9367125-0831-4afb-a0e7-86b67df7ba1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465837788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam e_csr_outstanding.465837788 |
| Directory | /workspace/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3782029007 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 450234484 ps |
| CPU time | 3.27 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:07 PM PST 24 |
| Peak memory | 200540 kb |
| Host | smart-d46ca7f6-293b-49ea-87d5-b7b54faa6034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782029007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3782029007 |
| Directory | /workspace/3.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.439257834 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 796907585 ps |
| CPU time | 2.6 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:55 PM PST 24 |
| Peak memory | 200608 kb |
| Host | smart-267f65ff-49b0-4c2d-8b50-8ffd8578d7b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439257834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err. 439257834 |
| Directory | /workspace/3.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3369562434 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 216160837 ps |
| CPU time | 1.5 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:01 PM PST 24 |
| Peak memory | 200484 kb |
| Host | smart-68878f5b-b2ae-41b7-a0ac-c491197623da |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369562434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3 369562434 |
| Directory | /workspace/4.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2012449919 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1559004969 ps |
| CPU time | 8.15 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:12 PM PST 24 |
| Peak memory | 200504 kb |
| Host | smart-519e49bd-ee6d-4e71-9936-37793e18cfab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012449919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2 012449919 |
| Directory | /workspace/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3057943757 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 140899563 ps |
| CPU time | 0.88 seconds |
| Started | Feb 04 12:36:51 PM PST 24 |
| Finished | Feb 04 12:36:59 PM PST 24 |
| Peak memory | 200348 kb |
| Host | smart-1ec3151e-a6ed-47ee-ae72-648549a79278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057943757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3 057943757 |
| Directory | /workspace/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2637812607 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 143324523 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200420 kb |
| Host | smart-122bc76d-c7d3-49da-9765-3c9b16be5dff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637812607 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2637812607 |
| Directory | /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1350228767 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 61899385 ps |
| CPU time | 0.74 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:01 PM PST 24 |
| Peak memory | 200344 kb |
| Host | smart-4b465173-7f56-4091-abf4-3475455e91d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350228767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1350228767 |
| Directory | /workspace/4.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1068804082 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 130325779 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:36:48 PM PST 24 |
| Finished | Feb 04 12:36:53 PM PST 24 |
| Peak memory | 200376 kb |
| Host | smart-27208cc1-4b4e-436f-b633-848ad77b0354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068804082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa me_csr_outstanding.1068804082 |
| Directory | /workspace/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3576515306 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 904863738 ps |
| CPU time | 2.83 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:04 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-ab0a1c04-4689-49f1-9f28-0f275896e22f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576515306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err .3576515306 |
| Directory | /workspace/4.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3889905332 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 109499418 ps |
| CPU time | 0.89 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:02 PM PST 24 |
| Peak memory | 200404 kb |
| Host | smart-4887cf22-ed3c-45dc-b969-7186cd07b717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889905332 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3889905332 |
| Directory | /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2958788473 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 58107544 ps |
| CPU time | 0.72 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200392 kb |
| Host | smart-98ab968b-0e21-4251-8c66-c31f7e275710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958788473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2958788473 |
| Directory | /workspace/5.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2308523934 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 213611428 ps |
| CPU time | 1.48 seconds |
| Started | Feb 04 12:36:49 PM PST 24 |
| Finished | Feb 04 12:36:55 PM PST 24 |
| Peak memory | 200572 kb |
| Host | smart-e53675e2-f1a2-4252-a381-53a520ec89f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308523934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa me_csr_outstanding.2308523934 |
| Directory | /workspace/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2005483953 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 338745713 ps |
| CPU time | 2.25 seconds |
| Started | Feb 04 12:36:51 PM PST 24 |
| Finished | Feb 04 12:37:01 PM PST 24 |
| Peak memory | 200624 kb |
| Host | smart-3f7ec9e3-e8e7-44cd-a2f3-402a3b79fda5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005483953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2005483953 |
| Directory | /workspace/5.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2489590547 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 877953646 ps |
| CPU time | 2.88 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:07 PM PST 24 |
| Peak memory | 200504 kb |
| Host | smart-17e5019f-f1e2-41d8-bcd9-a01d137c3437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489590547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err .2489590547 |
| Directory | /workspace/5.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2565194704 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 127274775 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200492 kb |
| Host | smart-9f01868f-9712-49be-994d-079e4b2fdec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565194704 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2565194704 |
| Directory | /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.657603264 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 57827674 ps |
| CPU time | 0.72 seconds |
| Started | Feb 04 12:36:49 PM PST 24 |
| Finished | Feb 04 12:36:54 PM PST 24 |
| Peak memory | 200344 kb |
| Host | smart-9daee463-8453-4b19-9986-9da64f31af03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657603264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.657603264 |
| Directory | /workspace/6.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3395328688 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 131621933 ps |
| CPU time | 1.01 seconds |
| Started | Feb 04 12:36:54 PM PST 24 |
| Finished | Feb 04 12:37:02 PM PST 24 |
| Peak memory | 200336 kb |
| Host | smart-d4e41114-e41e-4040-9f07-617bc7b7289d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395328688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa me_csr_outstanding.3395328688 |
| Directory | /workspace/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.842554097 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 186996606 ps |
| CPU time | 2.62 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:07 PM PST 24 |
| Peak memory | 200556 kb |
| Host | smart-75843c64-134a-487f-823f-14d6ccd9e0db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842554097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.842554097 |
| Directory | /workspace/6.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2469526414 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 176360444 ps |
| CPU time | 1.62 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:01 PM PST 24 |
| Peak memory | 208804 kb |
| Host | smart-a76759a4-964c-419f-88af-1553693b09f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469526414 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2469526414 |
| Directory | /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1127957411 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 78497263 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:36:52 PM PST 24 |
| Finished | Feb 04 12:37:01 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-1910b588-41ab-443a-b1c1-2601da4ccefd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127957411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1127957411 |
| Directory | /workspace/7.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3188657875 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 218736810 ps |
| CPU time | 1.44 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:02 PM PST 24 |
| Peak memory | 200564 kb |
| Host | smart-73c89b36-0816-4d9d-af5e-24f4e5b5f345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188657875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa me_csr_outstanding.3188657875 |
| Directory | /workspace/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4067363437 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 364775686 ps |
| CPU time | 2.21 seconds |
| Started | Feb 04 12:36:46 PM PST 24 |
| Finished | Feb 04 12:36:52 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-494a8491-4a4e-4f5e-8cdd-858f2682bef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067363437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4067363437 |
| Directory | /workspace/7.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2895056016 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 96483685 ps |
| CPU time | 0.85 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-9759a5be-c6af-47c4-a390-44fcfe6e1eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895056016 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2895056016 |
| Directory | /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3721145309 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 66738234 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:02 PM PST 24 |
| Peak memory | 200372 kb |
| Host | smart-4b498d06-776b-4382-9cfc-ea87da7baf45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721145309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3721145309 |
| Directory | /workspace/8.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4238616687 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 108333137 ps |
| CPU time | 1.33 seconds |
| Started | Feb 04 12:36:59 PM PST 24 |
| Finished | Feb 04 12:37:09 PM PST 24 |
| Peak memory | 200584 kb |
| Host | smart-165b63bf-117b-4e97-a356-1767bfcc5513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238616687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa me_csr_outstanding.4238616687 |
| Directory | /workspace/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1913312103 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 507953155 ps |
| CPU time | 1.85 seconds |
| Started | Feb 04 12:36:50 PM PST 24 |
| Finished | Feb 04 12:36:58 PM PST 24 |
| Peak memory | 200776 kb |
| Host | smart-b02a80a9-2c9b-4201-baff-e7fc66f9a4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913312103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err .1913312103 |
| Directory | /workspace/8.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.204469130 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 121900347 ps |
| CPU time | 1.02 seconds |
| Started | Feb 04 12:36:53 PM PST 24 |
| Finished | Feb 04 12:37:02 PM PST 24 |
| Peak memory | 200380 kb |
| Host | smart-96db0a38-0a85-4b75-ab82-cff00197f0f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204469130 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.204469130 |
| Directory | /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4161027382 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 61860495 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:05 PM PST 24 |
| Peak memory | 200356 kb |
| Host | smart-3034689d-4473-49a6-afd0-3b4f6b70d1fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161027382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4161027382 |
| Directory | /workspace/9.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.763638352 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 114996662 ps |
| CPU time | 1.22 seconds |
| Started | Feb 04 12:36:59 PM PST 24 |
| Finished | Feb 04 12:37:09 PM PST 24 |
| Peak memory | 200584 kb |
| Host | smart-6c3ff76c-6098-45d9-8668-957eda64d080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763638352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam e_csr_outstanding.763638352 |
| Directory | /workspace/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1755786942 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 119536058 ps |
| CPU time | 1.59 seconds |
| Started | Feb 04 12:36:55 PM PST 24 |
| Finished | Feb 04 12:37:06 PM PST 24 |
| Peak memory | 208772 kb |
| Host | smart-e1c688cd-2a8f-4aaa-9f29-9f94795ed1ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755786942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1755786942 |
| Directory | /workspace/9.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/default/0.rstmgr_alert_test.447250826 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 61454493 ps |
| CPU time | 0.68 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-7402b09f-4c2a-44f6-a10c-acd46e6ad998 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447250826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.447250826 |
| Directory | /workspace/0.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2441785941 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2186958642 ps |
| CPU time | 7.91 seconds |
| Started | Feb 04 12:51:57 PM PST 24 |
| Finished | Feb 04 12:52:09 PM PST 24 |
| Peak memory | 221020 kb |
| Host | smart-407c73b8-fdc5-4137-a7f4-cbd49d75a41d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2441785941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2441785941 |
| Directory | /workspace/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1964639479 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 244126039 ps |
| CPU time | 1.08 seconds |
| Started | Feb 04 12:52:02 PM PST 24 |
| Finished | Feb 04 12:52:06 PM PST 24 |
| Peak memory | 217308 kb |
| Host | smart-afe65128-61c4-46ce-97fd-6bd74fe672c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964639479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1964639479 |
| Directory | /workspace/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/0.rstmgr_reset.3415506917 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 806956450 ps |
| CPU time | 4.64 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:05 PM PST 24 |
| Peak memory | 200148 kb |
| Host | smart-45d133ce-3cd3-48cf-8332-b08a3b95d2be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415506917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3415506917 |
| Directory | /workspace/0.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sec_cm.4046395590 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 9084277017 ps |
| CPU time | 14.05 seconds |
| Started | Feb 04 12:51:57 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 216888 kb |
| Host | smart-292cd9fd-2092-40f7-bb1c-11d983354ef5 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046395590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4046395590 |
| Directory | /workspace/0.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2559464476 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 180621800 ps |
| CPU time | 1.15 seconds |
| Started | Feb 04 12:51:58 PM PST 24 |
| Finished | Feb 04 12:52:02 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-89ea1355-e0b2-4e81-bcf8-73dddd8b221e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559464476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2559464476 |
| Directory | /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/0.rstmgr_smoke.3035565006 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 110655930 ps |
| CPU time | 1.11 seconds |
| Started | Feb 04 12:52:03 PM PST 24 |
| Finished | Feb 04 12:52:07 PM PST 24 |
| Peak memory | 200208 kb |
| Host | smart-f5bcbc4a-7bd8-48d1-bd27-c7b8393bfaf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035565006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3035565006 |
| Directory | /workspace/0.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/0.rstmgr_stress_all.3631059977 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4999775806 ps |
| CPU time | 23.09 seconds |
| Started | Feb 04 12:52:01 PM PST 24 |
| Finished | Feb 04 12:52:28 PM PST 24 |
| Peak memory | 200192 kb |
| Host | smart-17c8af45-9da7-4779-9bae-5eb4e8711e16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631059977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3631059977 |
| Directory | /workspace/0.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sw_rst.375806912 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 140199592 ps |
| CPU time | 1.61 seconds |
| Started | Feb 04 12:51:55 PM PST 24 |
| Finished | Feb 04 12:51:58 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-73eb021f-c6a9-49a7-b1e5-f71bb079f52b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375806912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.375806912 |
| Directory | /workspace/0.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3181392358 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 186067578 ps |
| CPU time | 1.31 seconds |
| Started | Feb 04 12:51:51 PM PST 24 |
| Finished | Feb 04 12:51:54 PM PST 24 |
| Peak memory | 200016 kb |
| Host | smart-62c677ec-1d01-4fbf-81a9-c99c7a2356df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3181392358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3181392358 |
| Directory | /workspace/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/1.rstmgr_alert_test.3163330861 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 59415600 ps |
| CPU time | 0.7 seconds |
| Started | Feb 04 12:52:03 PM PST 24 |
| Finished | Feb 04 12:52:06 PM PST 24 |
| Peak memory | 200004 kb |
| Host | smart-f4ffafc8-ad9a-472a-93e1-9eed37d5788d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163330861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3163330861 |
| Directory | /workspace/1.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3904681427 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2345473035 ps |
| CPU time | 7.71 seconds |
| Started | Feb 04 12:52:18 PM PST 24 |
| Finished | Feb 04 12:52:28 PM PST 24 |
| Peak memory | 217724 kb |
| Host | smart-be416bec-6204-4569-b1be-395fad35db0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904681427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3904681427 |
| Directory | /workspace/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1707089732 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 244325263 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:23 PM PST 24 |
| Peak memory | 217360 kb |
| Host | smart-443702a9-5cc6-4e29-899d-561f7ad9a681 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707089732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1707089732 |
| Directory | /workspace/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/1.rstmgr_por_stretcher.2076511589 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 169070742 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199652 kb |
| Host | smart-7b7bc09e-81fd-45ec-b78a-7fba01709da7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076511589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2076511589 |
| Directory | /workspace/1.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/1.rstmgr_reset.1080902883 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1441759668 ps |
| CPU time | 6.14 seconds |
| Started | Feb 04 12:53:29 PM PST 24 |
| Finished | Feb 04 12:53:38 PM PST 24 |
| Peak memory | 198716 kb |
| Host | smart-09343952-9351-4e34-bb63-4b2c56fcd568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080902883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1080902883 |
| Directory | /workspace/1.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/1.rstmgr_smoke.923518152 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 188398095 ps |
| CPU time | 1.27 seconds |
| Started | Feb 04 12:52:08 PM PST 24 |
| Finished | Feb 04 12:52:15 PM PST 24 |
| Peak memory | 200252 kb |
| Host | smart-7de53732-a626-4853-9848-0985d90e19e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923518152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.923518152 |
| Directory | /workspace/1.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/1.rstmgr_stress_all.1259240048 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6249130377 ps |
| CPU time | 25.81 seconds |
| Started | Feb 04 12:51:59 PM PST 24 |
| Finished | Feb 04 12:52:29 PM PST 24 |
| Peak memory | 200364 kb |
| Host | smart-1fbf9eaf-57bc-4e80-9e39-aff286425b3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259240048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1259240048 |
| Directory | /workspace/1.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sw_rst.508716417 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 154623028 ps |
| CPU time | 1.87 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:02 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-5804ef15-6bc7-4dad-89b9-945dee5b11ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508716417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.508716417 |
| Directory | /workspace/1.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2056079606 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 77864950 ps |
| CPU time | 0.86 seconds |
| Started | Feb 04 12:51:53 PM PST 24 |
| Finished | Feb 04 12:51:55 PM PST 24 |
| Peak memory | 200016 kb |
| Host | smart-1f3cafca-384e-41de-9219-fb18ffcb621b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056079606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2056079606 |
| Directory | /workspace/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/10.rstmgr_alert_test.680337726 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 84078889 ps |
| CPU time | 0.79 seconds |
| Started | Feb 04 12:52:22 PM PST 24 |
| Finished | Feb 04 12:52:26 PM PST 24 |
| Peak memory | 199856 kb |
| Host | smart-6492e5b3-5e9b-4dcc-aa5d-7c94a3e41aca |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680337726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.680337726 |
| Directory | /workspace/10.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1705244392 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2182969595 ps |
| CPU time | 8.6 seconds |
| Started | Feb 04 12:52:16 PM PST 24 |
| Finished | Feb 04 12:52:26 PM PST 24 |
| Peak memory | 218340 kb |
| Host | smart-d8f7295f-5bae-4d5a-b178-65a14040c726 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705244392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1705244392 |
| Directory | /workspace/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/10.rstmgr_por_stretcher.3090190814 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 179740641 ps |
| CPU time | 0.82 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 199812 kb |
| Host | smart-ad8ca568-64d7-4fe4-beab-15a56fbcad1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090190814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3090190814 |
| Directory | /workspace/10.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/10.rstmgr_reset.1099935143 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1320381152 ps |
| CPU time | 5.22 seconds |
| Started | Feb 04 12:52:19 PM PST 24 |
| Finished | Feb 04 12:52:27 PM PST 24 |
| Peak memory | 200236 kb |
| Host | smart-97d61fd3-1935-4ad9-99b8-2d07f2651cae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1099935143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1099935143 |
| Directory | /workspace/10.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2027351662 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 96361556 ps |
| CPU time | 1 seconds |
| Started | Feb 04 12:52:04 PM PST 24 |
| Finished | Feb 04 12:52:07 PM PST 24 |
| Peak memory | 200032 kb |
| Host | smart-3032f1d2-ebe9-4872-b53e-2cfa0fe3ad44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027351662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2027351662 |
| Directory | /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/10.rstmgr_smoke.1146816260 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 261316647 ps |
| CPU time | 1.43 seconds |
| Started | Feb 04 12:52:18 PM PST 24 |
| Finished | Feb 04 12:52:21 PM PST 24 |
| Peak memory | 200092 kb |
| Host | smart-78ccc7a8-d108-4901-8e4c-a6225da12bf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146816260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1146816260 |
| Directory | /workspace/10.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/10.rstmgr_stress_all.2518042336 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 5474498931 ps |
| CPU time | 18.33 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:41 PM PST 24 |
| Peak memory | 200284 kb |
| Host | smart-e3ed294d-bee7-44c0-b464-2313c0ff2b5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518042336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2518042336 |
| Directory | /workspace/10.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sw_rst.511883019 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 269036995 ps |
| CPU time | 1.88 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:25 PM PST 24 |
| Peak memory | 200032 kb |
| Host | smart-bdd13115-2d98-4fe7-9258-eb2cece45000 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511883019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.511883019 |
| Directory | /workspace/10.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.914534162 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 125414044 ps |
| CPU time | 1.08 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 200020 kb |
| Host | smart-6c997850-54f6-4275-862d-98a4736c8940 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914534162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.914534162 |
| Directory | /workspace/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/11.rstmgr_alert_test.3429142979 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 78278638 ps |
| CPU time | 0.76 seconds |
| Started | Feb 04 12:52:17 PM PST 24 |
| Finished | Feb 04 12:52:20 PM PST 24 |
| Peak memory | 199804 kb |
| Host | smart-4d17cafd-f11b-4777-80cd-aa95d8b83bb9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429142979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3429142979 |
| Directory | /workspace/11.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3873192394 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1226626765 ps |
| CPU time | 5.75 seconds |
| Started | Feb 04 12:52:18 PM PST 24 |
| Finished | Feb 04 12:52:26 PM PST 24 |
| Peak memory | 217912 kb |
| Host | smart-1c233b1a-78d6-478d-b6f9-564cf480f7f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873192394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3873192394 |
| Directory | /workspace/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.559532873 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 243241088 ps |
| CPU time | 1.09 seconds |
| Started | Feb 04 12:52:18 PM PST 24 |
| Finished | Feb 04 12:52:21 PM PST 24 |
| Peak memory | 217344 kb |
| Host | smart-7cad12ff-5e29-4f85-ab39-f2732bae71e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559532873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.559532873 |
| Directory | /workspace/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/11.rstmgr_por_stretcher.242149364 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 161114441 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:52:18 PM PST 24 |
| Finished | Feb 04 12:52:20 PM PST 24 |
| Peak memory | 199836 kb |
| Host | smart-14c82c66-0647-4938-913b-0548276c181d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242149364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.242149364 |
| Directory | /workspace/11.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/11.rstmgr_reset.29836902 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1286174597 ps |
| CPU time | 5.11 seconds |
| Started | Feb 04 12:52:00 PM PST 24 |
| Finished | Feb 04 12:52:10 PM PST 24 |
| Peak memory | 200180 kb |
| Host | smart-a2afa643-4dd6-4317-9b3b-30dd1ea340d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29836902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.29836902 |
| Directory | /workspace/11.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.4273275892 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 151915863 ps |
| CPU time | 1.13 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 200048 kb |
| Host | smart-a7875191-1f60-4952-b4c3-3f8b22e4c269 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273275892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.4273275892 |
| Directory | /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/11.rstmgr_smoke.2029489411 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 122073998 ps |
| CPU time | 1.19 seconds |
| Started | Feb 04 12:52:18 PM PST 24 |
| Finished | Feb 04 12:52:21 PM PST 24 |
| Peak memory | 200164 kb |
| Host | smart-7b910bc6-0c25-41c0-8d61-7c77fda2e5c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029489411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2029489411 |
| Directory | /workspace/11.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/11.rstmgr_stress_all.3687474861 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12285338931 ps |
| CPU time | 47.43 seconds |
| Started | Feb 04 12:52:27 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 200236 kb |
| Host | smart-3a226d74-cfe4-4a43-b980-dcb36bf26755 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687474861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3687474861 |
| Directory | /workspace/11.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sw_rst.1939775148 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 125942857 ps |
| CPU time | 1.59 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:25 PM PST 24 |
| Peak memory | 199964 kb |
| Host | smart-a000d2e3-f97c-4e3e-9209-8a607d7f8395 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939775148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1939775148 |
| Directory | /workspace/11.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2196584460 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 192367713 ps |
| CPU time | 1.24 seconds |
| Started | Feb 04 12:52:09 PM PST 24 |
| Finished | Feb 04 12:52:15 PM PST 24 |
| Peak memory | 199996 kb |
| Host | smart-ee9077ce-a450-45ff-8087-baf3c5f0f14d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196584460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2196584460 |
| Directory | /workspace/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/12.rstmgr_alert_test.2019918496 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 77272403 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 199812 kb |
| Host | smart-226fcf8c-b58d-4b26-95d0-3e2f1c445d32 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019918496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2019918496 |
| Directory | /workspace/12.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2720217313 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1877498318 ps |
| CPU time | 6.89 seconds |
| Started | Feb 04 12:52:23 PM PST 24 |
| Finished | Feb 04 12:52:38 PM PST 24 |
| Peak memory | 216804 kb |
| Host | smart-9ee9a6c9-a755-4f35-9b7f-6de85a6295f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720217313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2720217313 |
| Directory | /workspace/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2386158518 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 244249940 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:52:14 PM PST 24 |
| Finished | Feb 04 12:52:17 PM PST 24 |
| Peak memory | 217320 kb |
| Host | smart-86c77801-f456-468b-8fd0-1830bb0e9b70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386158518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2386158518 |
| Directory | /workspace/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/12.rstmgr_por_stretcher.2488596696 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 185651785 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:52:26 PM PST 24 |
| Finished | Feb 04 12:52:32 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-156a901b-8479-4ff2-9da7-7ffb4c01190d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488596696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2488596696 |
| Directory | /workspace/12.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/12.rstmgr_reset.3978370911 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1075033360 ps |
| CPU time | 4.95 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:29 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-06525d54-becd-42dc-b43f-6fd7c25764bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978370911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3978370911 |
| Directory | /workspace/12.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2937996486 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 144276313 ps |
| CPU time | 1.08 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:25 PM PST 24 |
| Peak memory | 200048 kb |
| Host | smart-bc2e0731-e94e-4b20-934d-97cb44ab12a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2937996486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2937996486 |
| Directory | /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/12.rstmgr_smoke.2170306202 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 262694942 ps |
| CPU time | 1.43 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:18 PM PST 24 |
| Peak memory | 200076 kb |
| Host | smart-2f331413-89f0-4678-80c8-e9071d5b7f8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2170306202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2170306202 |
| Directory | /workspace/12.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/12.rstmgr_stress_all.1648669676 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1631504565 ps |
| CPU time | 6.08 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:30 PM PST 24 |
| Peak memory | 200264 kb |
| Host | smart-8657d26e-a469-426e-8147-23dce36321fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648669676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1648669676 |
| Directory | /workspace/12.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sw_rst.2572711272 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 122981256 ps |
| CPU time | 1.56 seconds |
| Started | Feb 04 12:52:19 PM PST 24 |
| Finished | Feb 04 12:52:22 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-68686f4c-03f9-44bc-b492-ab0c2a421300 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572711272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2572711272 |
| Directory | /workspace/12.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.553547637 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 173698362 ps |
| CPU time | 1.1 seconds |
| Started | Feb 04 12:52:18 PM PST 24 |
| Finished | Feb 04 12:52:21 PM PST 24 |
| Peak memory | 200008 kb |
| Host | smart-576d62cb-df76-418a-afe3-e0e04af96168 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553547637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.553547637 |
| Directory | /workspace/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/13.rstmgr_alert_test.2033423845 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 57452846 ps |
| CPU time | 0.76 seconds |
| Started | Feb 04 12:52:22 PM PST 24 |
| Finished | Feb 04 12:52:25 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-40969e64-57b1-4366-99db-54560c4646f3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033423845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2033423845 |
| Directory | /workspace/13.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1318582283 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2355083422 ps |
| CPU time | 7.6 seconds |
| Started | Feb 04 12:52:22 PM PST 24 |
| Finished | Feb 04 12:52:33 PM PST 24 |
| Peak memory | 217612 kb |
| Host | smart-65a71731-6d3d-4f51-a212-779f107825d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1318582283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1318582283 |
| Directory | /workspace/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2744137979 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 248107548 ps |
| CPU time | 1.04 seconds |
| Started | Feb 04 12:52:22 PM PST 24 |
| Finished | Feb 04 12:52:25 PM PST 24 |
| Peak memory | 216472 kb |
| Host | smart-3930561a-1dab-4a8d-acf0-b9c52a94bbcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744137979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2744137979 |
| Directory | /workspace/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/13.rstmgr_por_stretcher.2727458304 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 213530790 ps |
| CPU time | 0.88 seconds |
| Started | Feb 04 12:52:14 PM PST 24 |
| Finished | Feb 04 12:52:17 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-e0f828fe-20e1-4902-8afb-34925ea9eed2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2727458304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2727458304 |
| Directory | /workspace/13.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/13.rstmgr_reset.1183763151 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 769988990 ps |
| CPU time | 3.86 seconds |
| Started | Feb 04 12:52:17 PM PST 24 |
| Finished | Feb 04 12:52:23 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-59952fa5-84e1-4095-9984-438740dbc9ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183763151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1183763151 |
| Directory | /workspace/13.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.198512052 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 183078133 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 199936 kb |
| Host | smart-b544e439-c814-4163-b9f2-ebead6a02bd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198512052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.198512052 |
| Directory | /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/13.rstmgr_smoke.798939167 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 120523383 ps |
| CPU time | 1.11 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 200152 kb |
| Host | smart-e5f0d0ac-4a9a-4134-a876-4792e9d63b83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798939167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.798939167 |
| Directory | /workspace/13.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/13.rstmgr_stress_all.3800295915 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2371380322 ps |
| CPU time | 8.92 seconds |
| Started | Feb 04 12:52:22 PM PST 24 |
| Finished | Feb 04 12:52:38 PM PST 24 |
| Peak memory | 200300 kb |
| Host | smart-4da7c96a-56e3-4c1b-8018-b721112d0ce6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800295915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3800295915 |
| Directory | /workspace/13.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sw_rst.2724395938 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 447789503 ps |
| CPU time | 2.29 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:25 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-6ecd3b8e-88c0-4034-9bc9-ff5ec00353eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724395938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2724395938 |
| Directory | /workspace/13.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2712376929 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 153871508 ps |
| CPU time | 1.27 seconds |
| Started | Feb 04 12:52:14 PM PST 24 |
| Finished | Feb 04 12:52:17 PM PST 24 |
| Peak memory | 199924 kb |
| Host | smart-cc8748a3-f1b3-4b8d-bdef-870d18563515 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712376929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2712376929 |
| Directory | /workspace/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/14.rstmgr_alert_test.476423298 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 62775052 ps |
| CPU time | 0.74 seconds |
| Started | Feb 04 12:52:19 PM PST 24 |
| Finished | Feb 04 12:52:22 PM PST 24 |
| Peak memory | 199808 kb |
| Host | smart-bf79fd76-2c12-4965-a317-721ed221e71a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476423298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.476423298 |
| Directory | /workspace/14.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.272954601 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1859582065 ps |
| CPU time | 6.88 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:23 PM PST 24 |
| Peak memory | 216900 kb |
| Host | smart-a11369a5-6a4e-4a86-b6bb-39bb04efeda8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272954601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.272954601 |
| Directory | /workspace/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1102506760 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 250917104 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 217236 kb |
| Host | smart-5394759c-35ca-4bb9-8399-821bc83d79df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102506760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1102506760 |
| Directory | /workspace/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/14.rstmgr_por_stretcher.3837410599 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 92235675 ps |
| CPU time | 0.72 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:23 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-7edc9579-3ad0-4261-b72c-bc49378807ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837410599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3837410599 |
| Directory | /workspace/14.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/14.rstmgr_reset.1898744132 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1252006472 ps |
| CPU time | 4.87 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:21 PM PST 24 |
| Peak memory | 200140 kb |
| Host | smart-1ad45c07-39f4-491b-8f95-b3c8bc5f7c37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898744132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1898744132 |
| Directory | /workspace/14.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.4074046889 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 104578054 ps |
| CPU time | 1.01 seconds |
| Started | Feb 04 12:52:18 PM PST 24 |
| Finished | Feb 04 12:52:22 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-417187a6-af60-4f5a-8299-5961e152075b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074046889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.4074046889 |
| Directory | /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/14.rstmgr_smoke.1200416709 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 108483731 ps |
| CPU time | 1.16 seconds |
| Started | Feb 04 12:52:22 PM PST 24 |
| Finished | Feb 04 12:52:32 PM PST 24 |
| Peak memory | 200220 kb |
| Host | smart-2f598e70-9546-4d75-b0bc-fccb50b28d34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200416709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1200416709 |
| Directory | /workspace/14.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sw_rst.1634476330 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 136415973 ps |
| CPU time | 1.6 seconds |
| Started | Feb 04 12:52:19 PM PST 24 |
| Finished | Feb 04 12:52:23 PM PST 24 |
| Peak memory | 199988 kb |
| Host | smart-36d096de-a699-4c37-885f-6675349df2bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1634476330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1634476330 |
| Directory | /workspace/14.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.4271050512 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 273697715 ps |
| CPU time | 1.6 seconds |
| Started | Feb 04 12:52:25 PM PST 24 |
| Finished | Feb 04 12:52:33 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-756d945b-c1c3-45af-b10e-d47a3f5c03c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271050512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.4271050512 |
| Directory | /workspace/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/15.rstmgr_alert_test.726601246 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 69155326 ps |
| CPU time | 0.73 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:17 PM PST 24 |
| Peak memory | 199868 kb |
| Host | smart-f291741c-0264-4ce2-be4e-e074f2bb4f03 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726601246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.726601246 |
| Directory | /workspace/15.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3707998139 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1875086986 ps |
| CPU time | 6.5 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:30 PM PST 24 |
| Peak memory | 221964 kb |
| Host | smart-0328a8d9-be77-4281-9d26-7d9622b77fe0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707998139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3707998139 |
| Directory | /workspace/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1797841634 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 244329389 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 217140 kb |
| Host | smart-4e2f3f54-037e-41af-bf84-5dbbb619213a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797841634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1797841634 |
| Directory | /workspace/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/15.rstmgr_por_stretcher.3044581993 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 104369469 ps |
| CPU time | 0.82 seconds |
| Started | Feb 04 12:52:25 PM PST 24 |
| Finished | Feb 04 12:52:32 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-4a656936-f7cc-4c54-b614-95a7bd040aa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044581993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3044581993 |
| Directory | /workspace/15.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/15.rstmgr_reset.2130955691 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 961588436 ps |
| CPU time | 4.79 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:28 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-2fa3bdf5-f6ee-4803-a2ec-e5412ea24aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2130955691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2130955691 |
| Directory | /workspace/15.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.131180538 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 149612384 ps |
| CPU time | 1.18 seconds |
| Started | Feb 04 12:52:16 PM PST 24 |
| Finished | Feb 04 12:52:19 PM PST 24 |
| Peak memory | 199984 kb |
| Host | smart-06e5ccc3-adfb-4d88-8312-83f649564e9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=131180538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.131180538 |
| Directory | /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/15.rstmgr_smoke.3534728189 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 123231220 ps |
| CPU time | 1.18 seconds |
| Started | Feb 04 12:52:22 PM PST 24 |
| Finished | Feb 04 12:52:25 PM PST 24 |
| Peak memory | 200192 kb |
| Host | smart-f855ca05-b710-4b73-a87f-fe98f72f6a37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534728189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3534728189 |
| Directory | /workspace/15.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/15.rstmgr_stress_all.2210501939 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 17035425936 ps |
| CPU time | 55.17 seconds |
| Started | Feb 04 12:52:19 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-d0023edd-ac81-4792-8e88-a37c8022f2d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210501939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2210501939 |
| Directory | /workspace/15.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sw_rst.1227719360 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 293482902 ps |
| CPU time | 1.85 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:26 PM PST 24 |
| Peak memory | 200008 kb |
| Host | smart-954c8ef4-d9a2-4c60-8b5e-78d1b38cc70b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227719360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1227719360 |
| Directory | /workspace/15.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2953682434 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 257498535 ps |
| CPU time | 1.49 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 200092 kb |
| Host | smart-a7e0f0ac-3858-402b-9c72-6e166a08fc97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2953682434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2953682434 |
| Directory | /workspace/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/16.rstmgr_alert_test.1614386042 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 64827851 ps |
| CPU time | 0.71 seconds |
| Started | Feb 04 12:52:47 PM PST 24 |
| Finished | Feb 04 12:52:48 PM PST 24 |
| Peak memory | 199924 kb |
| Host | smart-849002b4-af8b-4917-a2ab-37f487157868 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614386042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1614386042 |
| Directory | /workspace/16.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.191940496 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2180132256 ps |
| CPU time | 7.96 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:49 PM PST 24 |
| Peak memory | 217492 kb |
| Host | smart-974dbd88-87d8-4cdf-9d1a-de1e14f4da09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191940496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.191940496 |
| Directory | /workspace/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1840363349 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 245248605 ps |
| CPU time | 1.13 seconds |
| Started | Feb 04 12:52:42 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 217172 kb |
| Host | smart-d7ef184d-e8d3-4089-9fd1-f4924e515cdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840363349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1840363349 |
| Directory | /workspace/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/16.rstmgr_por_stretcher.3417854714 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 84992964 ps |
| CPU time | 0.75 seconds |
| Started | Feb 04 12:52:22 PM PST 24 |
| Finished | Feb 04 12:52:26 PM PST 24 |
| Peak memory | 199856 kb |
| Host | smart-c234045c-59b3-4d3f-ab87-d75b78d1d268 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417854714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3417854714 |
| Directory | /workspace/16.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/16.rstmgr_reset.3304548954 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1100662142 ps |
| CPU time | 4.73 seconds |
| Started | Feb 04 12:52:17 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 200148 kb |
| Host | smart-d240dc89-6c3f-4ccf-8796-2b1ef90da771 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304548954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3304548954 |
| Directory | /workspace/16.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1985911089 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 163206193 ps |
| CPU time | 1.26 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:41 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-82003510-9bc4-4b51-8f00-702b09885e6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985911089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1985911089 |
| Directory | /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/16.rstmgr_smoke.4170621016 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 114166361 ps |
| CPU time | 1.23 seconds |
| Started | Feb 04 12:52:21 PM PST 24 |
| Finished | Feb 04 12:52:25 PM PST 24 |
| Peak memory | 200148 kb |
| Host | smart-41b4af0a-7d5b-4bf4-a03f-21b966f064a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170621016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4170621016 |
| Directory | /workspace/16.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/16.rstmgr_stress_all.2720123487 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1202587623 ps |
| CPU time | 5.84 seconds |
| Started | Feb 04 12:52:37 PM PST 24 |
| Finished | Feb 04 12:52:44 PM PST 24 |
| Peak memory | 200148 kb |
| Host | smart-d5e83777-bdb7-46bf-a739-99377d7b2b65 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720123487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2720123487 |
| Directory | /workspace/16.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sw_rst.1609067681 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 260916956 ps |
| CPU time | 1.76 seconds |
| Started | Feb 04 12:52:34 PM PST 24 |
| Finished | Feb 04 12:52:38 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-fcc9687d-36d1-4e9f-9971-cd28fa1dafdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609067681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1609067681 |
| Directory | /workspace/16.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1142818951 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 287862521 ps |
| CPU time | 1.52 seconds |
| Started | Feb 04 12:52:39 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-86a87709-9dd5-4a60-abe9-245674559a69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142818951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1142818951 |
| Directory | /workspace/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/17.rstmgr_alert_test.3228532673 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 73446925 ps |
| CPU time | 0.8 seconds |
| Started | Feb 04 12:52:37 PM PST 24 |
| Finished | Feb 04 12:52:39 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-2c7f3336-06ea-4667-9f40-9ec25a5bd3de |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228532673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3228532673 |
| Directory | /workspace/17.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1726527844 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2365767203 ps |
| CPU time | 8.12 seconds |
| Started | Feb 04 12:52:41 PM PST 24 |
| Finished | Feb 04 12:52:50 PM PST 24 |
| Peak memory | 221968 kb |
| Host | smart-8c7d6e77-0e01-4580-ba88-ad0ec35a02d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726527844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1726527844 |
| Directory | /workspace/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1652625241 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 244372083 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:52:34 PM PST 24 |
| Finished | Feb 04 12:52:36 PM PST 24 |
| Peak memory | 217388 kb |
| Host | smart-84db3d70-2068-4e20-b570-b6696898d831 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652625241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1652625241 |
| Directory | /workspace/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/17.rstmgr_por_stretcher.1156181128 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 97319012 ps |
| CPU time | 0.75 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:41 PM PST 24 |
| Peak memory | 199888 kb |
| Host | smart-dea3cbce-2eee-46f4-a87e-b2c4e2eed858 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156181128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1156181128 |
| Directory | /workspace/17.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/17.rstmgr_reset.4242641135 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1515376252 ps |
| CPU time | 5.44 seconds |
| Started | Feb 04 12:52:33 PM PST 24 |
| Finished | Feb 04 12:52:39 PM PST 24 |
| Peak memory | 200080 kb |
| Host | smart-f6a3f75f-333a-4b71-8b19-f2a635a39589 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242641135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4242641135 |
| Directory | /workspace/17.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2464827427 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 109774554 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-c299a252-1cdd-406f-a085-bf8bc06dcf36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464827427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2464827427 |
| Directory | /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/17.rstmgr_smoke.1254657384 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 118990458 ps |
| CPU time | 1.13 seconds |
| Started | Feb 04 12:52:36 PM PST 24 |
| Finished | Feb 04 12:52:38 PM PST 24 |
| Peak memory | 200164 kb |
| Host | smart-25d2671c-a3dd-4822-8f34-434138d83f79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254657384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1254657384 |
| Directory | /workspace/17.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/17.rstmgr_stress_all.1881502022 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 9582111535 ps |
| CPU time | 35.84 seconds |
| Started | Feb 04 12:52:42 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 200284 kb |
| Host | smart-dad59f18-a5e3-47d7-b7ca-ca6604742e1b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881502022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1881502022 |
| Directory | /workspace/17.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.395311848 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 119031980 ps |
| CPU time | 1.03 seconds |
| Started | Feb 04 12:52:42 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 199972 kb |
| Host | smart-1754a26b-c202-45e4-9105-f2df296973df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=395311848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.395311848 |
| Directory | /workspace/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/18.rstmgr_alert_test.3511271339 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 84064435 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:52:36 PM PST 24 |
| Finished | Feb 04 12:52:39 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-e6a9025c-564a-4c31-825f-a88264c6888f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511271339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3511271339 |
| Directory | /workspace/18.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3998788389 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1220753156 ps |
| CPU time | 5.66 seconds |
| Started | Feb 04 12:52:34 PM PST 24 |
| Finished | Feb 04 12:52:41 PM PST 24 |
| Peak memory | 217904 kb |
| Host | smart-f5862fb0-716c-4261-9f67-d6e899bc3503 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998788389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3998788389 |
| Directory | /workspace/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1874005594 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 245208390 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:52:39 PM PST 24 |
| Finished | Feb 04 12:52:41 PM PST 24 |
| Peak memory | 217356 kb |
| Host | smart-be1b80b3-a188-4039-95f6-bdf2bf8933de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1874005594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1874005594 |
| Directory | /workspace/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/18.rstmgr_por_stretcher.4058020121 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 168697012 ps |
| CPU time | 0.9 seconds |
| Started | Feb 04 12:52:44 PM PST 24 |
| Finished | Feb 04 12:52:46 PM PST 24 |
| Peak memory | 199860 kb |
| Host | smart-55883a22-f704-414e-ba8e-c47282cb55a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058020121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.4058020121 |
| Directory | /workspace/18.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/18.rstmgr_reset.1052387116 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2126010568 ps |
| CPU time | 7.62 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:49 PM PST 24 |
| Peak memory | 200128 kb |
| Host | smart-6e8304f5-3e76-4903-8bbf-30447adcd73a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052387116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1052387116 |
| Directory | /workspace/18.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3105642333 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 107315519 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:52:39 PM PST 24 |
| Finished | Feb 04 12:52:42 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-53aec2bf-b51a-49bf-ba2d-e3553a7be396 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105642333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3105642333 |
| Directory | /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/18.rstmgr_smoke.2475561024 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 236204341 ps |
| CPU time | 1.45 seconds |
| Started | Feb 04 12:52:34 PM PST 24 |
| Finished | Feb 04 12:52:37 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-77f37d5d-0e41-4eb4-a8bb-457e7f90c65c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475561024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2475561024 |
| Directory | /workspace/18.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/18.rstmgr_stress_all.1314423850 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1644617436 ps |
| CPU time | 6.27 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:45 PM PST 24 |
| Peak memory | 200248 kb |
| Host | smart-728dc541-6ed1-48c2-a036-4bae9aee9ee0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314423850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1314423850 |
| Directory | /workspace/18.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sw_rst.481321127 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 539077418 ps |
| CPU time | 2.88 seconds |
| Started | Feb 04 12:52:39 PM PST 24 |
| Finished | Feb 04 12:52:44 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-d63ea2e4-656d-42e6-bb10-6b645e96bfdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481321127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.481321127 |
| Directory | /workspace/18.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3909924756 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 90707448 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-b3718170-a7b8-4c45-9611-fe1b5d5ab6c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909924756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3909924756 |
| Directory | /workspace/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/19.rstmgr_alert_test.3549360639 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 83572153 ps |
| CPU time | 0.82 seconds |
| Started | Feb 04 12:52:36 PM PST 24 |
| Finished | Feb 04 12:52:39 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-4f2277fc-b688-4ea8-9d88-3ecc05fafd77 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549360639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3549360639 |
| Directory | /workspace/19.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1397985983 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1233581277 ps |
| CPU time | 5.95 seconds |
| Started | Feb 04 12:52:42 PM PST 24 |
| Finished | Feb 04 12:52:49 PM PST 24 |
| Peak memory | 216980 kb |
| Host | smart-cae81065-d299-4c54-8649-1c64ff49502a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397985983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1397985983 |
| Directory | /workspace/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3002629677 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 244948268 ps |
| CPU time | 1.16 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 217384 kb |
| Host | smart-a07f332d-4426-41ad-aa9c-452c19dd8a9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002629677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3002629677 |
| Directory | /workspace/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/19.rstmgr_por_stretcher.3102121337 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 191356664 ps |
| CPU time | 0.86 seconds |
| Started | Feb 04 12:52:44 PM PST 24 |
| Finished | Feb 04 12:52:46 PM PST 24 |
| Peak memory | 199732 kb |
| Host | smart-ff5cc280-5282-4b48-a4f6-30305de76e05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102121337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3102121337 |
| Directory | /workspace/19.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/19.rstmgr_reset.391361519 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1556249885 ps |
| CPU time | 5.62 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:47 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-1ed4fb6b-f581-4d80-a3bc-527ac317cf28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391361519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.391361519 |
| Directory | /workspace/19.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3829585047 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 184318286 ps |
| CPU time | 1.2 seconds |
| Started | Feb 04 12:52:36 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 199932 kb |
| Host | smart-b6828f94-5e79-4bc9-a80e-0f027657bb40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829585047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3829585047 |
| Directory | /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/19.rstmgr_smoke.850838322 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 253488864 ps |
| CPU time | 1.66 seconds |
| Started | Feb 04 12:52:39 PM PST 24 |
| Finished | Feb 04 12:52:42 PM PST 24 |
| Peak memory | 200216 kb |
| Host | smart-b27398a5-57d0-4a3d-b258-a70308b87a3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850838322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.850838322 |
| Directory | /workspace/19.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/19.rstmgr_stress_all.3504104932 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2628515207 ps |
| CPU time | 8.57 seconds |
| Started | Feb 04 12:52:44 PM PST 24 |
| Finished | Feb 04 12:52:54 PM PST 24 |
| Peak memory | 200140 kb |
| Host | smart-85d9027d-ae8d-4042-99e4-bb168dbd8362 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504104932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3504104932 |
| Directory | /workspace/19.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sw_rst.2836171848 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 135941612 ps |
| CPU time | 1.61 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-f37338ea-df64-4b33-8ddb-42b0084f6acb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836171848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2836171848 |
| Directory | /workspace/19.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2317207428 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 120733651 ps |
| CPU time | 0.94 seconds |
| Started | Feb 04 12:52:41 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 200008 kb |
| Host | smart-9f2276d5-2806-4a99-8ccf-c76c5376f8e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317207428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2317207428 |
| Directory | /workspace/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/2.rstmgr_alert_test.3519898573 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 86563586 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:51:53 PM PST 24 |
| Finished | Feb 04 12:51:56 PM PST 24 |
| Peak memory | 199764 kb |
| Host | smart-225d1c03-fca7-4b34-af5d-aedbfd67c791 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519898573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3519898573 |
| Directory | /workspace/2.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.792794191 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2363251114 ps |
| CPU time | 8.53 seconds |
| Started | Feb 04 12:51:59 PM PST 24 |
| Finished | Feb 04 12:52:13 PM PST 24 |
| Peak memory | 217748 kb |
| Host | smart-f99d3e9f-4e72-41da-91d1-59b23eaeb305 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792794191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.792794191 |
| Directory | /workspace/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2281748423 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 243815142 ps |
| CPU time | 1.21 seconds |
| Started | Feb 04 12:52:07 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 217468 kb |
| Host | smart-542bbd90-65a4-4ce8-895e-ca2c2afcea3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281748423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2281748423 |
| Directory | /workspace/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/2.rstmgr_por_stretcher.3969854075 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 175446826 ps |
| CPU time | 0.85 seconds |
| Started | Feb 04 12:51:58 PM PST 24 |
| Finished | Feb 04 12:52:03 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-2bfd9c26-3440-4c75-9400-484d76160243 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969854075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3969854075 |
| Directory | /workspace/2.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/2.rstmgr_reset.4058141266 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1833593415 ps |
| CPU time | 7.08 seconds |
| Started | Feb 04 12:52:09 PM PST 24 |
| Finished | Feb 04 12:52:20 PM PST 24 |
| Peak memory | 200272 kb |
| Host | smart-a27d34cd-9355-48e4-89b7-75983568c453 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058141266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.4058141266 |
| Directory | /workspace/2.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sec_cm.3513299194 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 16833741091 ps |
| CPU time | 24.97 seconds |
| Started | Feb 04 12:51:53 PM PST 24 |
| Finished | Feb 04 12:52:20 PM PST 24 |
| Peak memory | 217904 kb |
| Host | smart-98471a74-3f7c-4a2a-842f-336887ed20f0 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513299194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3513299194 |
| Directory | /workspace/2.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.97384750 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 188332476 ps |
| CPU time | 1.34 seconds |
| Started | Feb 04 12:52:02 PM PST 24 |
| Finished | Feb 04 12:52:07 PM PST 24 |
| Peak memory | 200020 kb |
| Host | smart-a767a082-8ce8-4c95-b278-583b1b0594fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97384750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.97384750 |
| Directory | /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/2.rstmgr_smoke.2204666872 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 247360590 ps |
| CPU time | 1.4 seconds |
| Started | Feb 04 12:52:04 PM PST 24 |
| Finished | Feb 04 12:52:07 PM PST 24 |
| Peak memory | 200204 kb |
| Host | smart-31d66755-4eb5-440f-8053-38874a0f9a89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204666872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2204666872 |
| Directory | /workspace/2.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/2.rstmgr_stress_all.3753413779 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 9906483957 ps |
| CPU time | 37.07 seconds |
| Started | Feb 04 12:52:04 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 200252 kb |
| Host | smart-067866a3-345f-4afe-887e-530760d0c504 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753413779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3753413779 |
| Directory | /workspace/2.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sw_rst.50399241 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 374958863 ps |
| CPU time | 2.43 seconds |
| Started | Feb 04 12:52:02 PM PST 24 |
| Finished | Feb 04 12:52:08 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-036744ae-ef92-4a05-b9b0-e534986c8df6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50399241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.50399241 |
| Directory | /workspace/2.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2704947530 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 152533815 ps |
| CPU time | 1.2 seconds |
| Started | Feb 04 12:51:57 PM PST 24 |
| Finished | Feb 04 12:52:01 PM PST 24 |
| Peak memory | 200192 kb |
| Host | smart-0e0fb5f2-3f35-4aad-be44-7d9f31499fd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704947530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2704947530 |
| Directory | /workspace/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/20.rstmgr_alert_test.4159303823 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 71032975 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:52:36 PM PST 24 |
| Finished | Feb 04 12:52:38 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-c52ac3a0-a92f-48ef-b0b7-3a588b56e7f1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159303823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.4159303823 |
| Directory | /workspace/20.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3941994113 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 244364624 ps |
| CPU time | 1.04 seconds |
| Started | Feb 04 12:52:45 PM PST 24 |
| Finished | Feb 04 12:52:47 PM PST 24 |
| Peak memory | 217200 kb |
| Host | smart-c2265949-488d-49f1-9723-de49df191eb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941994113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3941994113 |
| Directory | /workspace/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/20.rstmgr_por_stretcher.134666297 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 102247338 ps |
| CPU time | 0.76 seconds |
| Started | Feb 04 12:52:37 PM PST 24 |
| Finished | Feb 04 12:52:39 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-cf119149-ba16-4ad5-8f9b-84ed395031c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=134666297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.134666297 |
| Directory | /workspace/20.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/20.rstmgr_reset.3355985523 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1713537974 ps |
| CPU time | 7.32 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:47 PM PST 24 |
| Peak memory | 200140 kb |
| Host | smart-0476bdf6-a446-49dc-b1c5-1dde4d3b84b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355985523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3355985523 |
| Directory | /workspace/20.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3624177447 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 184691841 ps |
| CPU time | 1.16 seconds |
| Started | Feb 04 12:52:48 PM PST 24 |
| Finished | Feb 04 12:52:50 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-2e4bb337-b5c0-4b46-a016-fd96b40bce83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3624177447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3624177447 |
| Directory | /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/20.rstmgr_smoke.3709435215 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 116281092 ps |
| CPU time | 1.15 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 200188 kb |
| Host | smart-e8182703-c075-40b7-81b7-eca26c071aca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3709435215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3709435215 |
| Directory | /workspace/20.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/20.rstmgr_stress_all.279223994 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2411262594 ps |
| CPU time | 11.89 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:53 PM PST 24 |
| Peak memory | 200212 kb |
| Host | smart-4b09ed9f-7f11-4e54-b014-9366114c455e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279223994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.279223994 |
| Directory | /workspace/20.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sw_rst.1555780066 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 292992502 ps |
| CPU time | 2.04 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-2b91931e-05ec-46f4-8831-493fb5a2066e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1555780066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1555780066 |
| Directory | /workspace/20.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2156341676 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 109790700 ps |
| CPU time | 0.99 seconds |
| Started | Feb 04 12:52:37 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 199900 kb |
| Host | smart-74f51010-1ab3-4d23-9273-048aeeed5fe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156341676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2156341676 |
| Directory | /workspace/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/21.rstmgr_alert_test.625956756 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 75492593 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:52:41 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 199908 kb |
| Host | smart-b11e4419-6855-41e4-9da0-6e54865cb03d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625956756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.625956756 |
| Directory | /workspace/21.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1203913742 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1224297156 ps |
| CPU time | 5.69 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:47 PM PST 24 |
| Peak memory | 216472 kb |
| Host | smart-fd6e488b-0a00-4d62-bf7b-3306343b9caf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1203913742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1203913742 |
| Directory | /workspace/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.715979828 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 247073444 ps |
| CPU time | 1.1 seconds |
| Started | Feb 04 12:52:48 PM PST 24 |
| Finished | Feb 04 12:52:50 PM PST 24 |
| Peak memory | 217328 kb |
| Host | smart-37ca4542-2454-447f-98e8-bb607344231f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715979828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.715979828 |
| Directory | /workspace/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/21.rstmgr_por_stretcher.4101534972 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 201413880 ps |
| CPU time | 0.93 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 199736 kb |
| Host | smart-a190fbb7-a3dc-47b0-ae84-6d7e7c0a06bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101534972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.4101534972 |
| Directory | /workspace/21.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/21.rstmgr_reset.622223230 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1499747485 ps |
| CPU time | 6.48 seconds |
| Started | Feb 04 12:52:37 PM PST 24 |
| Finished | Feb 04 12:52:45 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-030cfec1-6d5d-41a6-8f1d-8f4365434c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622223230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.622223230 |
| Directory | /workspace/21.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.101380861 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 104490375 ps |
| CPU time | 1.03 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-37236d79-839d-46e7-b40d-5678ebc1c60d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101380861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.101380861 |
| Directory | /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/21.rstmgr_smoke.1901327341 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 119525033 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:52:37 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-a1064f52-c200-4506-84ce-72c845fa63ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901327341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1901327341 |
| Directory | /workspace/21.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/21.rstmgr_stress_all.2515130074 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 4288656394 ps |
| CPU time | 17.21 seconds |
| Started | Feb 04 12:52:48 PM PST 24 |
| Finished | Feb 04 12:53:06 PM PST 24 |
| Peak memory | 200308 kb |
| Host | smart-930238df-c425-475d-8fec-35b119c9fa2b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515130074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2515130074 |
| Directory | /workspace/21.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sw_rst.696581994 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 362245753 ps |
| CPU time | 2.49 seconds |
| Started | Feb 04 12:52:39 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-c2b6c95a-c013-4b63-8e73-36b6c207d6d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696581994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.696581994 |
| Directory | /workspace/21.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1721712780 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 201908260 ps |
| CPU time | 1.28 seconds |
| Started | Feb 04 12:52:42 PM PST 24 |
| Finished | Feb 04 12:52:44 PM PST 24 |
| Peak memory | 200008 kb |
| Host | smart-b4f751fd-2a30-4b23-bd93-3b6ad48963ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1721712780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1721712780 |
| Directory | /workspace/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/22.rstmgr_alert_test.1002693967 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 88987216 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:52:42 PM PST 24 |
| Finished | Feb 04 12:52:44 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-5747de4e-f465-41b9-92cc-1aac7cfe00f0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002693967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1002693967 |
| Directory | /workspace/22.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.234493048 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1221508668 ps |
| CPU time | 5.62 seconds |
| Started | Feb 04 12:52:39 PM PST 24 |
| Finished | Feb 04 12:52:47 PM PST 24 |
| Peak memory | 216816 kb |
| Host | smart-1e516783-1a60-4c59-93f8-7b0f8bf817d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234493048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.234493048 |
| Directory | /workspace/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2601539580 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 244399083 ps |
| CPU time | 1.1 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 217328 kb |
| Host | smart-74e880b7-db63-4783-9ed2-a592181d3561 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601539580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2601539580 |
| Directory | /workspace/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/22.rstmgr_por_stretcher.2966359662 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 221238467 ps |
| CPU time | 0.94 seconds |
| Started | Feb 04 12:52:38 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-b6367dc3-8807-4966-ad39-5df3da36c9d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2966359662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2966359662 |
| Directory | /workspace/22.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/22.rstmgr_reset.1940592505 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 796504251 ps |
| CPU time | 4.13 seconds |
| Started | Feb 04 12:52:39 PM PST 24 |
| Finished | Feb 04 12:52:45 PM PST 24 |
| Peak memory | 200168 kb |
| Host | smart-c555b5ff-a3fd-4325-af17-dbd6838be0b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940592505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1940592505 |
| Directory | /workspace/22.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3418001938 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 111109164 ps |
| CPU time | 0.98 seconds |
| Started | Feb 04 12:52:51 PM PST 24 |
| Finished | Feb 04 12:52:53 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-a36ac923-63a5-49ec-8266-9d88e25dfd69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418001938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3418001938 |
| Directory | /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/22.rstmgr_smoke.756746300 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 222750011 ps |
| CPU time | 1.45 seconds |
| Started | Feb 04 12:52:48 PM PST 24 |
| Finished | Feb 04 12:52:51 PM PST 24 |
| Peak memory | 200188 kb |
| Host | smart-e8e5cd0d-2e07-4275-b114-8490609f37ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756746300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.756746300 |
| Directory | /workspace/22.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/22.rstmgr_stress_all.3934314934 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 4105178921 ps |
| CPU time | 18.41 seconds |
| Started | Feb 04 12:52:44 PM PST 24 |
| Finished | Feb 04 12:53:04 PM PST 24 |
| Peak memory | 200304 kb |
| Host | smart-cc2806a3-e4cb-4b16-987b-67a8e7e0cfd0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934314934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3934314934 |
| Directory | /workspace/22.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sw_rst.2690861809 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 141361999 ps |
| CPU time | 1.72 seconds |
| Started | Feb 04 12:52:37 PM PST 24 |
| Finished | Feb 04 12:52:40 PM PST 24 |
| Peak memory | 199924 kb |
| Host | smart-efb0d9c4-e7a4-4b4e-a1c5-3504f5d38a00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2690861809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2690861809 |
| Directory | /workspace/22.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.939336520 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 152333097 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 200008 kb |
| Host | smart-895a91c3-f084-4a3d-99f1-c0b0d5a73f94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939336520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.939336520 |
| Directory | /workspace/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/23.rstmgr_alert_test.1187131713 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 64413290 ps |
| CPU time | 0.72 seconds |
| Started | Feb 04 12:53:13 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 199836 kb |
| Host | smart-ecdea5bc-b590-425b-a45d-14d55e243afa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187131713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1187131713 |
| Directory | /workspace/23.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.211282703 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1224117791 ps |
| CPU time | 5.89 seconds |
| Started | Feb 04 12:52:48 PM PST 24 |
| Finished | Feb 04 12:52:54 PM PST 24 |
| Peak memory | 217388 kb |
| Host | smart-52cdee52-a684-4d96-a7bc-b26e7d4480c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211282703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.211282703 |
| Directory | /workspace/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3729075464 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 244232630 ps |
| CPU time | 1.26 seconds |
| Started | Feb 04 12:53:13 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 217360 kb |
| Host | smart-5f0b097b-813a-4079-9e01-91e5f047fba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3729075464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3729075464 |
| Directory | /workspace/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/23.rstmgr_por_stretcher.1460221837 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 171283154 ps |
| CPU time | 0.94 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:43 PM PST 24 |
| Peak memory | 199888 kb |
| Host | smart-b3e1215d-f6f7-4ec9-a5b7-c8cd27832569 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460221837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1460221837 |
| Directory | /workspace/23.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/23.rstmgr_reset.3653497591 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 781492186 ps |
| CPU time | 4.28 seconds |
| Started | Feb 04 12:52:40 PM PST 24 |
| Finished | Feb 04 12:52:46 PM PST 24 |
| Peak memory | 200100 kb |
| Host | smart-ab428e14-2567-4ace-9dff-8e9d4bb279c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653497591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3653497591 |
| Directory | /workspace/23.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2711653230 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 172948682 ps |
| CPU time | 1.28 seconds |
| Started | Feb 04 12:52:50 PM PST 24 |
| Finished | Feb 04 12:52:52 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-7314913f-0fcc-489e-a5b3-88354d0848b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711653230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2711653230 |
| Directory | /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/23.rstmgr_smoke.2176291867 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 206621753 ps |
| CPU time | 1.44 seconds |
| Started | Feb 04 12:52:42 PM PST 24 |
| Finished | Feb 04 12:52:44 PM PST 24 |
| Peak memory | 200168 kb |
| Host | smart-35628453-0bf6-4fd8-8dc2-c77945b64f6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2176291867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2176291867 |
| Directory | /workspace/23.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/23.rstmgr_stress_all.2973278691 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 6125204957 ps |
| CPU time | 21.06 seconds |
| Started | Feb 04 12:53:14 PM PST 24 |
| Finished | Feb 04 12:53:36 PM PST 24 |
| Peak memory | 200308 kb |
| Host | smart-752bd21f-daf0-4831-b68a-652871a71b7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973278691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2973278691 |
| Directory | /workspace/23.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sw_rst.101631874 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 148119252 ps |
| CPU time | 1.72 seconds |
| Started | Feb 04 12:52:51 PM PST 24 |
| Finished | Feb 04 12:52:54 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-3d78df0a-0d85-498b-8eae-4b8f5a658a67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101631874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.101631874 |
| Directory | /workspace/23.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3424396751 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 88989719 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:52:50 PM PST 24 |
| Finished | Feb 04 12:52:52 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-99942e1e-ac73-410f-9edd-49c2c63e6703 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424396751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3424396751 |
| Directory | /workspace/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/24.rstmgr_alert_test.2802626859 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 82526411 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 199904 kb |
| Host | smart-0dc0e02f-eed5-4f06-81e0-9e4541b48304 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802626859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2802626859 |
| Directory | /workspace/24.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1534273424 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1891790380 ps |
| CPU time | 7.46 seconds |
| Started | Feb 04 12:53:19 PM PST 24 |
| Finished | Feb 04 12:53:29 PM PST 24 |
| Peak memory | 218352 kb |
| Host | smart-db445d8a-fba4-4608-97d5-1b5fca1ae72b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534273424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1534273424 |
| Directory | /workspace/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1889505310 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 244197363 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 217156 kb |
| Host | smart-a985f316-ba14-4ade-b64b-bc9839f009cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889505310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1889505310 |
| Directory | /workspace/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/24.rstmgr_por_stretcher.1836404316 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 183318660 ps |
| CPU time | 0.92 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 199884 kb |
| Host | smart-6a32f4ad-cc98-4684-af9e-98646ec53422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1836404316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1836404316 |
| Directory | /workspace/24.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/24.rstmgr_reset.2444679554 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1941710010 ps |
| CPU time | 6.94 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:27 PM PST 24 |
| Peak memory | 200260 kb |
| Host | smart-c71316a8-4bde-4520-be4f-fa60eece5153 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444679554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2444679554 |
| Directory | /workspace/24.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3954292748 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 113454288 ps |
| CPU time | 1.02 seconds |
| Started | Feb 04 12:53:15 PM PST 24 |
| Finished | Feb 04 12:53:18 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-bae57102-7255-45ed-a173-88b8be9f4c13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954292748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3954292748 |
| Directory | /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/24.rstmgr_smoke.4212896376 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 195649873 ps |
| CPU time | 1.38 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 200104 kb |
| Host | smart-201398df-e506-4c41-8aae-59f55bea53ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212896376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4212896376 |
| Directory | /workspace/24.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/24.rstmgr_stress_all.2898208444 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5397578698 ps |
| CPU time | 24.87 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:42 PM PST 24 |
| Peak memory | 200324 kb |
| Host | smart-79e2e2da-44fb-4136-8f63-fd6b78fe0285 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898208444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2898208444 |
| Directory | /workspace/24.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sw_rst.2025462664 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 320949050 ps |
| CPU time | 2.1 seconds |
| Started | Feb 04 12:53:15 PM PST 24 |
| Finished | Feb 04 12:53:18 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-3a7413f7-a56f-4a36-bd44-923cd47277dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025462664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2025462664 |
| Directory | /workspace/24.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.316999375 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 201459042 ps |
| CPU time | 1.17 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-be5d9f2c-d6b6-44aa-94d4-932450534d01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316999375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.316999375 |
| Directory | /workspace/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/25.rstmgr_alert_test.3094839250 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 82315074 ps |
| CPU time | 0.85 seconds |
| Started | Feb 04 12:53:13 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 199808 kb |
| Host | smart-2447482d-01cc-4473-bcf4-e155a1f4c036 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094839250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3094839250 |
| Directory | /workspace/25.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.124037021 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1894667633 ps |
| CPU time | 6.71 seconds |
| Started | Feb 04 12:53:14 PM PST 24 |
| Finished | Feb 04 12:53:22 PM PST 24 |
| Peak memory | 221760 kb |
| Host | smart-a56e2f70-b1dc-40ef-ac43-c5a0ce1ced2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124037021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.124037021 |
| Directory | /workspace/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3490683657 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 243374220 ps |
| CPU time | 1.13 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:18 PM PST 24 |
| Peak memory | 217380 kb |
| Host | smart-9d6e59cb-443f-46c7-8dba-b8d8ae1a9b36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490683657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3490683657 |
| Directory | /workspace/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/25.rstmgr_por_stretcher.732417806 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 179734605 ps |
| CPU time | 0.87 seconds |
| Started | Feb 04 12:53:10 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 199864 kb |
| Host | smart-4580cf52-4995-4bc3-9264-04f452287c4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=732417806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.732417806 |
| Directory | /workspace/25.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/25.rstmgr_reset.2645655515 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2191641069 ps |
| CPU time | 8.14 seconds |
| Started | Feb 04 12:53:13 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 200276 kb |
| Host | smart-52056b17-7ebd-47c3-bc82-ed84643f4f9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645655515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2645655515 |
| Directory | /workspace/25.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1856180225 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 174407803 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:53:15 PM PST 24 |
| Finished | Feb 04 12:53:17 PM PST 24 |
| Peak memory | 199900 kb |
| Host | smart-7a487ac9-58a5-47fe-a37c-ecf1a8a250a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856180225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1856180225 |
| Directory | /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/25.rstmgr_smoke.2171393969 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 249528627 ps |
| CPU time | 1.43 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 200176 kb |
| Host | smart-65df99d9-2a0d-4559-9652-cdae140a5f33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2171393969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2171393969 |
| Directory | /workspace/25.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/25.rstmgr_stress_all.606924773 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 7811086302 ps |
| CPU time | 25.12 seconds |
| Started | Feb 04 12:53:11 PM PST 24 |
| Finished | Feb 04 12:53:40 PM PST 24 |
| Peak memory | 200308 kb |
| Host | smart-43349336-94f5-49a2-896b-af395ad52873 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606924773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.606924773 |
| Directory | /workspace/25.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sw_rst.1220692281 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 114655885 ps |
| CPU time | 1.42 seconds |
| Started | Feb 04 12:53:22 PM PST 24 |
| Finished | Feb 04 12:53:27 PM PST 24 |
| Peak memory | 199972 kb |
| Host | smart-6b1a0de3-8088-4203-a3e6-ce3ca0f5f0ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220692281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1220692281 |
| Directory | /workspace/25.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3963627883 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 109191421 ps |
| CPU time | 0.94 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 199904 kb |
| Host | smart-c9be51fa-79cb-49c6-b5de-8c41859d82aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963627883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3963627883 |
| Directory | /workspace/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/26.rstmgr_alert_test.514449128 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 64240676 ps |
| CPU time | 0.72 seconds |
| Started | Feb 04 12:53:10 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 199884 kb |
| Host | smart-1061c66b-142a-4240-a22f-a397e2ba4297 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514449128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.514449128 |
| Directory | /workspace/26.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1656868917 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1230741896 ps |
| CPU time | 5.82 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:24 PM PST 24 |
| Peak memory | 221404 kb |
| Host | smart-20542973-d976-4c83-ad57-7d37c6b3bd71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1656868917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1656868917 |
| Directory | /workspace/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.4105135669 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 244363643 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 217360 kb |
| Host | smart-e53b88a2-9daf-437f-83b3-7a891cf670d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105135669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.4105135669 |
| Directory | /workspace/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/26.rstmgr_por_stretcher.3293562176 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 192235281 ps |
| CPU time | 0.88 seconds |
| Started | Feb 04 12:53:09 PM PST 24 |
| Finished | Feb 04 12:53:15 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-5912c108-8d0b-4e70-b17c-9b81c4027418 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293562176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3293562176 |
| Directory | /workspace/26.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/26.rstmgr_reset.2062320319 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1232423354 ps |
| CPU time | 5.1 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 200260 kb |
| Host | smart-135f83f7-f47f-4cf5-a378-21d2978efd35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062320319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2062320319 |
| Directory | /workspace/26.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2123036077 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 106652131 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-1fa8cbe0-cbb6-405a-b81b-3dd04def57a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123036077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2123036077 |
| Directory | /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/26.rstmgr_smoke.2975924898 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 256821093 ps |
| CPU time | 1.47 seconds |
| Started | Feb 04 12:53:14 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-d951ef32-e563-412c-b65d-b689942dd838 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2975924898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2975924898 |
| Directory | /workspace/26.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/26.rstmgr_stress_all.360182319 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3232347357 ps |
| CPU time | 14.36 seconds |
| Started | Feb 04 12:53:11 PM PST 24 |
| Finished | Feb 04 12:53:29 PM PST 24 |
| Peak memory | 200328 kb |
| Host | smart-df244b27-1300-4e6a-8ead-904aa7ba93f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360182319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.360182319 |
| Directory | /workspace/26.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sw_rst.1768226938 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 139855564 ps |
| CPU time | 1.7 seconds |
| Started | Feb 04 12:53:23 PM PST 24 |
| Finished | Feb 04 12:53:28 PM PST 24 |
| Peak memory | 199972 kb |
| Host | smart-bc70ff56-a51e-404e-8cd5-97a13ea0c92f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768226938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1768226938 |
| Directory | /workspace/26.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.805160823 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 182248858 ps |
| CPU time | 1.26 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-9261cc64-387d-4185-856c-5ada1bf62ffa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805160823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.805160823 |
| Directory | /workspace/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/27.rstmgr_alert_test.3125412162 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 73646609 ps |
| CPU time | 0.74 seconds |
| Started | Feb 04 12:53:22 PM PST 24 |
| Finished | Feb 04 12:53:27 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-b007c8b9-f60c-40b7-89da-2c468fe90402 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125412162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3125412162 |
| Directory | /workspace/27.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.415395835 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 244315250 ps |
| CPU time | 1.1 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 217228 kb |
| Host | smart-a8aa2bef-6eff-4292-bfbd-9913acaecc29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415395835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.415395835 |
| Directory | /workspace/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/27.rstmgr_por_stretcher.201021344 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 75573947 ps |
| CPU time | 0.7 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 199696 kb |
| Host | smart-2e2ed19b-3b67-4d77-930a-008de1bdb26a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=201021344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.201021344 |
| Directory | /workspace/27.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/27.rstmgr_reset.1639649886 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 809875112 ps |
| CPU time | 4.44 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 200260 kb |
| Host | smart-1f9266aa-fa97-4691-93f6-04d0810bc363 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639649886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1639649886 |
| Directory | /workspace/27.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1762525475 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 156819470 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:53:14 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-f0009c28-dd04-430b-b86a-e01de78a69db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762525475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1762525475 |
| Directory | /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/27.rstmgr_smoke.651541069 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 128207261 ps |
| CPU time | 1.28 seconds |
| Started | Feb 04 12:53:13 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 200092 kb |
| Host | smart-30d02592-92df-4315-b8d7-ef2f02aeb552 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651541069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.651541069 |
| Directory | /workspace/27.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/27.rstmgr_stress_all.3826235312 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3265888451 ps |
| CPU time | 14.79 seconds |
| Started | Feb 04 12:53:13 PM PST 24 |
| Finished | Feb 04 12:53:30 PM PST 24 |
| Peak memory | 200216 kb |
| Host | smart-8a248edd-e754-4297-9587-89e897ed6cd7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826235312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3826235312 |
| Directory | /workspace/27.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sw_rst.2462362040 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 123406885 ps |
| CPU time | 1.5 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-7ad306ca-2229-40ea-9faf-f4bf3f935164 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2462362040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2462362040 |
| Directory | /workspace/27.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3841194851 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 154788047 ps |
| CPU time | 1.23 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:24 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-1ad1dbda-c114-44d5-8dd1-6e77ba39deb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841194851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3841194851 |
| Directory | /workspace/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3432951529 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1219620459 ps |
| CPU time | 5.78 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:26 PM PST 24 |
| Peak memory | 218444 kb |
| Host | smart-f8919d54-c316-4e78-a558-199303b00c06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3432951529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3432951529 |
| Directory | /workspace/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2352301047 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 246707299 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:53:19 PM PST 24 |
| Finished | Feb 04 12:53:22 PM PST 24 |
| Peak memory | 217288 kb |
| Host | smart-ab622cd1-7458-4ea3-96cb-4fbbdc3bbe37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352301047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2352301047 |
| Directory | /workspace/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/28.rstmgr_por_stretcher.2416133062 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 149374784 ps |
| CPU time | 0.78 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-041018a4-8bba-42f3-a7aa-f717d05f0ab1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416133062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2416133062 |
| Directory | /workspace/28.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/28.rstmgr_reset.686963553 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1398426460 ps |
| CPU time | 6.04 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:26 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-1a491d2d-ce20-47eb-86d1-e8d9c589d3d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686963553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.686963553 |
| Directory | /workspace/28.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.357085920 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 152899570 ps |
| CPU time | 1.19 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 199968 kb |
| Host | smart-68cb506d-c1b1-4f0e-b936-54200f425012 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357085920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.357085920 |
| Directory | /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/28.rstmgr_smoke.2794525951 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 253121942 ps |
| CPU time | 1.43 seconds |
| Started | Feb 04 12:53:15 PM PST 24 |
| Finished | Feb 04 12:53:17 PM PST 24 |
| Peak memory | 200068 kb |
| Host | smart-f25dbba7-a6d8-40ba-8c4e-bb0f908c6838 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794525951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2794525951 |
| Directory | /workspace/28.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/28.rstmgr_stress_all.604276418 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 97999570 ps |
| CPU time | 0.86 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:18 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-d2555c0a-cf00-4e77-8d3d-16097f52f93b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604276418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.604276418 |
| Directory | /workspace/28.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sw_rst.818827783 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 294747964 ps |
| CPU time | 1.93 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:22 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-eabd9ab3-4f17-400f-947d-ef20da123f41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818827783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.818827783 |
| Directory | /workspace/28.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1971380505 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 138996442 ps |
| CPU time | 1.18 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-43ace23a-2175-4567-b604-30be0697d7d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971380505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1971380505 |
| Directory | /workspace/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/29.rstmgr_alert_test.1785865811 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 75360421 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:53:21 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-550009ac-7262-41d7-b209-7a2a7920bfa7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785865811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1785865811 |
| Directory | /workspace/29.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2835624381 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1217880013 ps |
| CPU time | 6.13 seconds |
| Started | Feb 04 12:53:15 PM PST 24 |
| Finished | Feb 04 12:53:24 PM PST 24 |
| Peak memory | 217288 kb |
| Host | smart-8a54e8f3-5101-44a7-92fb-80616adbddb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2835624381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2835624381 |
| Directory | /workspace/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.209321600 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 244536538 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:53:12 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 217128 kb |
| Host | smart-d1ee4bc8-7fa2-4d1b-958f-223ec266fdb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209321600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.209321600 |
| Directory | /workspace/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/29.rstmgr_por_stretcher.2497472915 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 117821366 ps |
| CPU time | 0.76 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:21 PM PST 24 |
| Peak memory | 199752 kb |
| Host | smart-211e9ec3-9955-4156-9969-40e0de3cf140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497472915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2497472915 |
| Directory | /workspace/29.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/29.rstmgr_reset.2797163156 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1486799880 ps |
| CPU time | 6.7 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 200260 kb |
| Host | smart-c9e7f96f-53d0-4e36-aaf5-4bafd4adc124 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797163156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2797163156 |
| Directory | /workspace/29.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4211043598 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 172945147 ps |
| CPU time | 1.23 seconds |
| Started | Feb 04 12:53:11 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-49598827-20f0-4734-bcdb-66066b100069 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211043598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4211043598 |
| Directory | /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/29.rstmgr_smoke.3883180607 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 187704356 ps |
| CPU time | 1.33 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:21 PM PST 24 |
| Peak memory | 200096 kb |
| Host | smart-b7673f07-18f5-4efb-8876-bf87a2d16f14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883180607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3883180607 |
| Directory | /workspace/29.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/29.rstmgr_stress_all.3960476387 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1858128385 ps |
| CPU time | 9.15 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:31 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-adb759cb-8835-4fd2-a55c-69048742763f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960476387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3960476387 |
| Directory | /workspace/29.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sw_rst.1374729073 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 140538293 ps |
| CPU time | 1.78 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:20 PM PST 24 |
| Peak memory | 200028 kb |
| Host | smart-14506f58-c30b-452c-95d7-e613b0a86577 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374729073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1374729073 |
| Directory | /workspace/29.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1709613085 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 89783728 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:53:15 PM PST 24 |
| Finished | Feb 04 12:53:18 PM PST 24 |
| Peak memory | 199996 kb |
| Host | smart-4ddd42cf-02f8-4d63-ad5f-aaa362a07b75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709613085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1709613085 |
| Directory | /workspace/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/3.rstmgr_alert_test.3146235099 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 68565847 ps |
| CPU time | 0.74 seconds |
| Started | Feb 04 12:51:55 PM PST 24 |
| Finished | Feb 04 12:51:57 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-b5de33fb-e99a-4b6c-bef4-097a10bf0ec1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146235099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3146235099 |
| Directory | /workspace/3.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.167751295 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1227415050 ps |
| CPU time | 6.18 seconds |
| Started | Feb 04 12:52:02 PM PST 24 |
| Finished | Feb 04 12:52:12 PM PST 24 |
| Peak memory | 221428 kb |
| Host | smart-512f21c5-9f4e-4981-8ed4-89a998e3a5e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167751295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.167751295 |
| Directory | /workspace/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3869740228 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 245696499 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:51:57 PM PST 24 |
| Finished | Feb 04 12:52:01 PM PST 24 |
| Peak memory | 217184 kb |
| Host | smart-d4df5107-137b-43cc-9b50-8e339b541755 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869740228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3869740228 |
| Directory | /workspace/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/3.rstmgr_por_stretcher.1222238831 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 188906605 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:51:52 PM PST 24 |
| Finished | Feb 04 12:51:55 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-793d0105-1fd7-4b48-a157-f512c21f7e99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222238831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1222238831 |
| Directory | /workspace/3.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/3.rstmgr_reset.765192223 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1772052072 ps |
| CPU time | 6.84 seconds |
| Started | Feb 04 12:51:56 PM PST 24 |
| Finished | Feb 04 12:52:05 PM PST 24 |
| Peak memory | 200188 kb |
| Host | smart-c8db81e7-c7e6-49ec-9bd8-3f15d6fd58d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=765192223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.765192223 |
| Directory | /workspace/3.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sec_cm.3297374038 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 8291674649 ps |
| CPU time | 14.45 seconds |
| Started | Feb 04 12:51:55 PM PST 24 |
| Finished | Feb 04 12:52:12 PM PST 24 |
| Peak memory | 216812 kb |
| Host | smart-43c2253f-a23f-4aaf-af38-caf7ffee9c43 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297374038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3297374038 |
| Directory | /workspace/3.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1253006669 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 106609970 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:51:55 PM PST 24 |
| Finished | Feb 04 12:51:57 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-dc047452-6d86-4aff-93aa-6b0a27bdc630 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253006669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1253006669 |
| Directory | /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/3.rstmgr_smoke.413854460 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 264082125 ps |
| CPU time | 1.48 seconds |
| Started | Feb 04 12:52:02 PM PST 24 |
| Finished | Feb 04 12:52:07 PM PST 24 |
| Peak memory | 200164 kb |
| Host | smart-d47cd9ee-a939-4caf-9c1f-0dcea2e8ac52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=413854460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.413854460 |
| Directory | /workspace/3.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/3.rstmgr_stress_all.93080501 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4109236556 ps |
| CPU time | 18.32 seconds |
| Started | Feb 04 12:51:55 PM PST 24 |
| Finished | Feb 04 12:52:16 PM PST 24 |
| Peak memory | 200196 kb |
| Host | smart-e5177517-27b8-4786-83f2-9aca38d79048 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93080501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.93080501 |
| Directory | /workspace/3.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sw_rst.215389217 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 353154961 ps |
| CPU time | 2.52 seconds |
| Started | Feb 04 12:52:09 PM PST 24 |
| Finished | Feb 04 12:52:16 PM PST 24 |
| Peak memory | 199948 kb |
| Host | smart-fb5d80c8-7c06-4a51-a053-eb8d3b48230e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215389217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.215389217 |
| Directory | /workspace/3.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1753589926 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 207076773 ps |
| CPU time | 1.59 seconds |
| Started | Feb 04 12:52:01 PM PST 24 |
| Finished | Feb 04 12:52:07 PM PST 24 |
| Peak memory | 200004 kb |
| Host | smart-60f8a1bb-b4e8-4ead-a947-8b4bd8febdb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753589926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1753589926 |
| Directory | /workspace/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/30.rstmgr_alert_test.3636782438 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 86899973 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:20 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-93113e9d-8892-4f45-b8dd-34c118d8f4d5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636782438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3636782438 |
| Directory | /workspace/30.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2906567885 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1229119408 ps |
| CPU time | 5.39 seconds |
| Started | Feb 04 12:53:25 PM PST 24 |
| Finished | Feb 04 12:53:35 PM PST 24 |
| Peak memory | 217276 kb |
| Host | smart-f15cf7e9-6729-466e-9fc5-0ee2e97041de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2906567885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2906567885 |
| Directory | /workspace/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3662570297 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 244110431 ps |
| CPU time | 1.15 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:21 PM PST 24 |
| Peak memory | 217380 kb |
| Host | smart-df943546-5fc2-4b1c-af4e-dd406b2266cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662570297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3662570297 |
| Directory | /workspace/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/30.rstmgr_por_stretcher.347587564 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 217483477 ps |
| CPU time | 0.9 seconds |
| Started | Feb 04 12:53:21 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-5d71f55f-e25d-4d64-8f36-30e2c34fcde8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347587564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.347587564 |
| Directory | /workspace/30.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/30.rstmgr_reset.3855020192 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1725087063 ps |
| CPU time | 6.95 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:29 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-28241bfb-2224-4158-83c8-d405bcd3f17c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855020192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3855020192 |
| Directory | /workspace/30.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1457010293 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 105532562 ps |
| CPU time | 0.94 seconds |
| Started | Feb 04 12:53:25 PM PST 24 |
| Finished | Feb 04 12:53:31 PM PST 24 |
| Peak memory | 199948 kb |
| Host | smart-d3be95e5-2c3c-4b60-8ea4-a1ebab2cae4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457010293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1457010293 |
| Directory | /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/30.rstmgr_smoke.60438504 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 114233994 ps |
| CPU time | 1.16 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:21 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-be11e9b6-4e78-4912-bffc-c9ca26ccb070 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60438504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.60438504 |
| Directory | /workspace/30.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/30.rstmgr_stress_all.3936192822 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 222698802 ps |
| CPU time | 1.24 seconds |
| Started | Feb 04 12:53:15 PM PST 24 |
| Finished | Feb 04 12:53:18 PM PST 24 |
| Peak memory | 199984 kb |
| Host | smart-b9b47e5c-ea95-4448-ba10-adff8fff7926 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936192822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3936192822 |
| Directory | /workspace/30.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sw_rst.2961732098 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 361818975 ps |
| CPU time | 2.27 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:21 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-683cb1d0-61da-42eb-be32-7713ff931cae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961732098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2961732098 |
| Directory | /workspace/30.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3352683112 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 86151520 ps |
| CPU time | 0.83 seconds |
| Started | Feb 04 12:53:13 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 199868 kb |
| Host | smart-7a616c65-5b1b-4292-98a3-beec2f41698a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352683112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3352683112 |
| Directory | /workspace/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/31.rstmgr_alert_test.1840331900 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 82158012 ps |
| CPU time | 0.78 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-c99a8756-bebe-4f66-86fc-0d8c1ff5868b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840331900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1840331900 |
| Directory | /workspace/31.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3052669562 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1225750977 ps |
| CPU time | 5.78 seconds |
| Started | Feb 04 12:53:25 PM PST 24 |
| Finished | Feb 04 12:53:35 PM PST 24 |
| Peak memory | 221220 kb |
| Host | smart-3c4215de-caff-42b5-9f28-7b70767b72cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3052669562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3052669562 |
| Directory | /workspace/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1986595859 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 245957814 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:53:25 PM PST 24 |
| Finished | Feb 04 12:53:31 PM PST 24 |
| Peak memory | 217188 kb |
| Host | smart-a0e383b8-5583-485c-81c7-5ff477461b49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986595859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1986595859 |
| Directory | /workspace/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/31.rstmgr_por_stretcher.4164794745 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 105232053 ps |
| CPU time | 0.73 seconds |
| Started | Feb 04 12:53:14 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-99b91d33-82cb-4f9f-b7f4-cb52674e051a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164794745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.4164794745 |
| Directory | /workspace/31.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/31.rstmgr_reset.3557623232 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1522992848 ps |
| CPU time | 6.23 seconds |
| Started | Feb 04 12:53:18 PM PST 24 |
| Finished | Feb 04 12:53:27 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-239e95c4-83ad-4e8e-bbea-3e04a3545dec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557623232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3557623232 |
| Directory | /workspace/31.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2961916862 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 152698773 ps |
| CPU time | 1.11 seconds |
| Started | Feb 04 12:53:21 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-1a64d3a4-a584-469c-9bf6-9a2c3b73a2d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961916862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2961916862 |
| Directory | /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/31.rstmgr_smoke.2688835703 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 187165487 ps |
| CPU time | 1.37 seconds |
| Started | Feb 04 12:53:15 PM PST 24 |
| Finished | Feb 04 12:53:18 PM PST 24 |
| Peak memory | 200196 kb |
| Host | smart-b6a7feae-b4df-4f41-b12d-fee7eda1182e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688835703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2688835703 |
| Directory | /workspace/31.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/31.rstmgr_stress_all.2000899098 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1547003558 ps |
| CPU time | 5.79 seconds |
| Started | Feb 04 12:53:25 PM PST 24 |
| Finished | Feb 04 12:53:35 PM PST 24 |
| Peak memory | 200176 kb |
| Host | smart-42fce6c5-8d59-4341-ba1c-28722f0eb2d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000899098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2000899098 |
| Directory | /workspace/31.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sw_rst.1765379348 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 341792077 ps |
| CPU time | 2.02 seconds |
| Started | Feb 04 12:53:19 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 200092 kb |
| Host | smart-c68b85e6-7879-42b7-a449-eb190e61b47f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765379348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1765379348 |
| Directory | /workspace/31.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3605842157 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 162989579 ps |
| CPU time | 1.08 seconds |
| Started | Feb 04 12:53:18 PM PST 24 |
| Finished | Feb 04 12:53:22 PM PST 24 |
| Peak memory | 200028 kb |
| Host | smart-794e1680-fd2c-4c91-8363-8115d91551d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605842157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3605842157 |
| Directory | /workspace/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/32.rstmgr_alert_test.990491786 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 77575906 ps |
| CPU time | 0.79 seconds |
| Started | Feb 04 12:53:25 PM PST 24 |
| Finished | Feb 04 12:53:31 PM PST 24 |
| Peak memory | 199812 kb |
| Host | smart-9ae0269d-1add-4b2f-91e9-c34d63df45e8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990491786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.990491786 |
| Directory | /workspace/32.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.37858877 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2161589176 ps |
| CPU time | 7.64 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:30 PM PST 24 |
| Peak memory | 222028 kb |
| Host | smart-046d9e38-a275-445d-bb32-fa0b585caaea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37858877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.37858877 |
| Directory | /workspace/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1641612372 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 248153523 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:53:25 PM PST 24 |
| Finished | Feb 04 12:53:31 PM PST 24 |
| Peak memory | 217292 kb |
| Host | smart-fe134f5c-ce84-4648-853d-181c448ccfcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641612372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1641612372 |
| Directory | /workspace/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/32.rstmgr_por_stretcher.1077938543 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 188652307 ps |
| CPU time | 0.89 seconds |
| Started | Feb 04 12:53:21 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-447d94b4-f000-433f-a032-c3a84a51ada8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077938543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1077938543 |
| Directory | /workspace/32.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/32.rstmgr_reset.3258647580 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1184332113 ps |
| CPU time | 4.92 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 200132 kb |
| Host | smart-9f07282b-5fea-4779-af41-d0152a296bb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3258647580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3258647580 |
| Directory | /workspace/32.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.4261446636 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 176525021 ps |
| CPU time | 1.13 seconds |
| Started | Feb 04 12:53:22 PM PST 24 |
| Finished | Feb 04 12:53:26 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-4037e3ed-0bd3-42e4-958d-9c1543f791fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261446636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.4261446636 |
| Directory | /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/32.rstmgr_smoke.4166044087 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 209707250 ps |
| CPU time | 1.39 seconds |
| Started | Feb 04 12:53:25 PM PST 24 |
| Finished | Feb 04 12:53:31 PM PST 24 |
| Peak memory | 200120 kb |
| Host | smart-ae4e3b0c-b47d-4535-8906-24c444641e88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166044087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.4166044087 |
| Directory | /workspace/32.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sw_rst.1922244490 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 524575583 ps |
| CPU time | 2.72 seconds |
| Started | Feb 04 12:53:22 PM PST 24 |
| Finished | Feb 04 12:53:28 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-2fa80f8e-2caf-44fc-8ee5-5be5aebd7ee8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1922244490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1922244490 |
| Directory | /workspace/32.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1990554085 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 62980302 ps |
| CPU time | 0.82 seconds |
| Started | Feb 04 12:53:22 PM PST 24 |
| Finished | Feb 04 12:53:26 PM PST 24 |
| Peak memory | 200016 kb |
| Host | smart-826beb15-cfc2-4f57-81ee-0d98acb02778 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990554085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1990554085 |
| Directory | /workspace/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/33.rstmgr_alert_test.2275018539 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 62485787 ps |
| CPU time | 0.72 seconds |
| Started | Feb 04 12:53:19 PM PST 24 |
| Finished | Feb 04 12:53:22 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-649b3591-52cd-497a-9f4d-dfd1e2b6e44d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275018539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2275018539 |
| Directory | /workspace/33.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2819289257 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1895751424 ps |
| CPU time | 7.33 seconds |
| Started | Feb 04 12:53:14 PM PST 24 |
| Finished | Feb 04 12:53:22 PM PST 24 |
| Peak memory | 217236 kb |
| Host | smart-51f84be6-3af9-47be-8f22-9a31196c9e63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819289257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2819289257 |
| Directory | /workspace/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3548926796 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 244708893 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:21 PM PST 24 |
| Peak memory | 217284 kb |
| Host | smart-28696eaf-10f6-4217-9bb1-54adf46fce56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548926796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3548926796 |
| Directory | /workspace/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/33.rstmgr_por_stretcher.3217733490 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 157400104 ps |
| CPU time | 0.85 seconds |
| Started | Feb 04 12:53:21 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-9e5b7b27-6304-4087-ac10-6ba883c7c1d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217733490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3217733490 |
| Directory | /workspace/33.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/33.rstmgr_reset.1091944941 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 688700992 ps |
| CPU time | 3.95 seconds |
| Started | Feb 04 12:53:19 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-e9c9570a-fc9e-4359-9d5d-a4e7ceda3d20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091944941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1091944941 |
| Directory | /workspace/33.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2497256192 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 105191481 ps |
| CPU time | 1.09 seconds |
| Started | Feb 04 12:53:19 PM PST 24 |
| Finished | Feb 04 12:53:22 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-1217c4ab-68b2-44b0-8cd7-adef181336a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497256192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2497256192 |
| Directory | /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/33.rstmgr_smoke.1315407413 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 257333498 ps |
| CPU time | 1.51 seconds |
| Started | Feb 04 12:53:22 PM PST 24 |
| Finished | Feb 04 12:53:27 PM PST 24 |
| Peak memory | 200196 kb |
| Host | smart-36b70de5-f104-493a-9083-3b2854d5733f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315407413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1315407413 |
| Directory | /workspace/33.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/33.rstmgr_stress_all.2726506754 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 4814646880 ps |
| CPU time | 20.37 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:40 PM PST 24 |
| Peak memory | 200188 kb |
| Host | smart-9b0226ff-f35b-4853-86ec-b015abd551bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726506754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2726506754 |
| Directory | /workspace/33.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sw_rst.1448624943 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 142112531 ps |
| CPU time | 1.78 seconds |
| Started | Feb 04 12:53:19 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 200084 kb |
| Host | smart-b7712e2b-d674-4684-ad37-95ea2b07d148 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448624943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1448624943 |
| Directory | /workspace/33.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2307475048 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 68480403 ps |
| CPU time | 0.75 seconds |
| Started | Feb 04 12:53:14 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-7fc62b5d-3918-41a0-874f-013220399fcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307475048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2307475048 |
| Directory | /workspace/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/34.rstmgr_alert_test.1855294317 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 77081645 ps |
| CPU time | 0.78 seconds |
| Started | Feb 04 12:53:19 PM PST 24 |
| Finished | Feb 04 12:53:22 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-290489f7-7c55-4575-8157-ff6fae754938 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855294317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1855294317 |
| Directory | /workspace/34.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3109253295 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 246316928 ps |
| CPU time | 1.04 seconds |
| Started | Feb 04 12:53:14 PM PST 24 |
| Finished | Feb 04 12:53:16 PM PST 24 |
| Peak memory | 217360 kb |
| Host | smart-a83cdace-c801-4cce-a8f8-abfcdd93d649 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109253295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3109253295 |
| Directory | /workspace/34.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/34.rstmgr_por_stretcher.2371320408 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 99902000 ps |
| CPU time | 0.79 seconds |
| Started | Feb 04 12:53:18 PM PST 24 |
| Finished | Feb 04 12:53:22 PM PST 24 |
| Peak memory | 199884 kb |
| Host | smart-c83ecc68-527a-4674-811a-e40ba4856e57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2371320408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2371320408 |
| Directory | /workspace/34.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/34.rstmgr_reset.375648326 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1058786186 ps |
| CPU time | 5 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:27 PM PST 24 |
| Peak memory | 200292 kb |
| Host | smart-36f6076f-c1cf-455f-bf95-cf4a085f64b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375648326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.375648326 |
| Directory | /workspace/34.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1865435643 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 111787470 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:20 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-b01d96f0-9930-43f8-9624-e96e6a3dc631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865435643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1865435643 |
| Directory | /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/34.rstmgr_smoke.3994410241 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 124323865 ps |
| CPU time | 1.15 seconds |
| Started | Feb 04 12:53:21 PM PST 24 |
| Finished | Feb 04 12:53:25 PM PST 24 |
| Peak memory | 200224 kb |
| Host | smart-735fd001-bd3c-4b03-88a0-d4901b1cb8ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994410241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3994410241 |
| Directory | /workspace/34.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/34.rstmgr_stress_all.582092978 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1795995932 ps |
| CPU time | 8.31 seconds |
| Started | Feb 04 12:53:19 PM PST 24 |
| Finished | Feb 04 12:53:30 PM PST 24 |
| Peak memory | 200264 kb |
| Host | smart-8e48eb33-3a92-4cec-b891-dc8b1cf7d4cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582092978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.582092978 |
| Directory | /workspace/34.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sw_rst.2868224778 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 154406073 ps |
| CPU time | 1.86 seconds |
| Started | Feb 04 12:53:18 PM PST 24 |
| Finished | Feb 04 12:53:23 PM PST 24 |
| Peak memory | 200088 kb |
| Host | smart-16f168ee-5084-4ac4-b3b0-72848d654d0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868224778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2868224778 |
| Directory | /workspace/34.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.739782078 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 158987090 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 199956 kb |
| Host | smart-adf4315a-95c8-47de-9b52-0b438ab9988f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739782078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.739782078 |
| Directory | /workspace/34.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/35.rstmgr_alert_test.2883393686 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 60867096 ps |
| CPU time | 0.73 seconds |
| Started | Feb 04 12:53:25 PM PST 24 |
| Finished | Feb 04 12:53:31 PM PST 24 |
| Peak memory | 199808 kb |
| Host | smart-e662d90d-ec4f-463f-8c13-7e2168015763 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883393686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2883393686 |
| Directory | /workspace/35.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.996867297 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1906664091 ps |
| CPU time | 6.95 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:26 PM PST 24 |
| Peak memory | 217264 kb |
| Host | smart-d0c13345-57a8-4f9e-9819-f05abd79cf4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996867297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.996867297 |
| Directory | /workspace/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2298526015 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 243997643 ps |
| CPU time | 1.13 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:21 PM PST 24 |
| Peak memory | 217260 kb |
| Host | smart-9901f042-a139-4813-ac06-40b191d72310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298526015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2298526015 |
| Directory | /workspace/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/35.rstmgr_por_stretcher.4054967335 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 180193169 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:53:21 PM PST 24 |
| Finished | Feb 04 12:53:24 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-db61063a-a0b9-4eae-9875-28101c377b92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054967335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.4054967335 |
| Directory | /workspace/35.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/35.rstmgr_reset.1678162477 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2062221916 ps |
| CPU time | 7.28 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:28 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-a95c6f8c-8774-49b9-8ddd-df4c545f75c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678162477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1678162477 |
| Directory | /workspace/35.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.531995132 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 153862260 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:17 PM PST 24 |
| Finished | Feb 04 12:53:20 PM PST 24 |
| Peak memory | 200028 kb |
| Host | smart-4fcd2a78-b147-463d-8360-3217e3405b50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=531995132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.531995132 |
| Directory | /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/35.rstmgr_smoke.867225037 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 113082166 ps |
| CPU time | 1.19 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:19 PM PST 24 |
| Peak memory | 200124 kb |
| Host | smart-6832812d-14af-4fcc-a453-247ac77d7c79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=867225037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.867225037 |
| Directory | /workspace/35.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/35.rstmgr_stress_all.295498033 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 8478267641 ps |
| CPU time | 30.16 seconds |
| Started | Feb 04 12:53:16 PM PST 24 |
| Finished | Feb 04 12:53:48 PM PST 24 |
| Peak memory | 200300 kb |
| Host | smart-b60fcc07-014c-4837-96b4-254e35b3534c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295498033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.295498033 |
| Directory | /workspace/35.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sw_rst.1752152229 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 146746165 ps |
| CPU time | 1.95 seconds |
| Started | Feb 04 12:53:14 PM PST 24 |
| Finished | Feb 04 12:53:17 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-960bec9e-a6b8-4aaf-a656-9e95682cde01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752152229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1752152229 |
| Directory | /workspace/35.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2307425278 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 193731654 ps |
| CPU time | 1.33 seconds |
| Started | Feb 04 12:53:21 PM PST 24 |
| Finished | Feb 04 12:53:26 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-3ff3daf6-c3fe-4619-9249-096e57c4ceca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307425278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2307425278 |
| Directory | /workspace/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/36.rstmgr_alert_test.935806642 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 63147812 ps |
| CPU time | 0.72 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:49 PM PST 24 |
| Peak memory | 199856 kb |
| Host | smart-9eaed0c3-21be-4a43-a826-9196489bbaba |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935806642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.935806642 |
| Directory | /workspace/36.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1682516213 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1885426155 ps |
| CPU time | 7.05 seconds |
| Started | Feb 04 12:53:38 PM PST 24 |
| Finished | Feb 04 12:53:46 PM PST 24 |
| Peak memory | 218228 kb |
| Host | smart-cfc61c3b-7c79-4128-9e61-eb870fadecfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682516213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1682516213 |
| Directory | /workspace/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3563786372 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 245329804 ps |
| CPU time | 1.08 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:53:41 PM PST 24 |
| Peak memory | 217356 kb |
| Host | smart-227156fe-32d5-4edc-ade2-ec11ddd7dfb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3563786372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3563786372 |
| Directory | /workspace/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/36.rstmgr_por_stretcher.1152513097 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 149985759 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:53:37 PM PST 24 |
| Finished | Feb 04 12:53:39 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-348cd5d9-5c4a-4775-ae32-04833caafab3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152513097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1152513097 |
| Directory | /workspace/36.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/36.rstmgr_reset.2351458723 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1373118274 ps |
| CPU time | 5.5 seconds |
| Started | Feb 04 12:53:36 PM PST 24 |
| Finished | Feb 04 12:53:43 PM PST 24 |
| Peak memory | 200268 kb |
| Host | smart-38567f74-fc73-4a6f-b5d7-35ca9fa95484 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351458723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2351458723 |
| Directory | /workspace/36.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2340564310 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 105788532 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:40 PM PST 24 |
| Finished | Feb 04 12:53:42 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-67b17c17-c552-4c48-950d-30ee49429ecb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340564310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2340564310 |
| Directory | /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/36.rstmgr_smoke.2424319437 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 247023237 ps |
| CPU time | 1.36 seconds |
| Started | Feb 04 12:53:38 PM PST 24 |
| Finished | Feb 04 12:53:41 PM PST 24 |
| Peak memory | 200192 kb |
| Host | smart-fd029d4a-c3a4-4293-8583-b6f6ccc254d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424319437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2424319437 |
| Directory | /workspace/36.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/36.rstmgr_stress_all.311592515 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 6532798146 ps |
| CPU time | 23.4 seconds |
| Started | Feb 04 12:53:38 PM PST 24 |
| Finished | Feb 04 12:54:03 PM PST 24 |
| Peak memory | 200344 kb |
| Host | smart-21d68391-9d8f-4ecc-a13f-3d01e9c93e0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311592515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.311592515 |
| Directory | /workspace/36.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sw_rst.218009969 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 122283523 ps |
| CPU time | 1.65 seconds |
| Started | Feb 04 12:53:31 PM PST 24 |
| Finished | Feb 04 12:53:38 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-ef8e6568-65df-4d16-bb6c-941151c43ce2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=218009969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.218009969 |
| Directory | /workspace/36.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3298562139 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 102196605 ps |
| CPU time | 0.93 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:53:42 PM PST 24 |
| Peak memory | 199992 kb |
| Host | smart-edefbc48-fce6-4eb3-9c0e-6f8660784aad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298562139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3298562139 |
| Directory | /workspace/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/37.rstmgr_alert_test.1925330979 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 85114659 ps |
| CPU time | 0.82 seconds |
| Started | Feb 04 12:53:45 PM PST 24 |
| Finished | Feb 04 12:53:48 PM PST 24 |
| Peak memory | 199900 kb |
| Host | smart-7dad2fb9-11fc-4df4-9f0b-b5b137518125 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925330979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1925330979 |
| Directory | /workspace/37.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2732112983 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1892422698 ps |
| CPU time | 7.86 seconds |
| Started | Feb 04 12:53:41 PM PST 24 |
| Finished | Feb 04 12:53:50 PM PST 24 |
| Peak memory | 220916 kb |
| Host | smart-3ceabfb4-dffc-4050-b90c-8b5a5b044f57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732112983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2732112983 |
| Directory | /workspace/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3169013139 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 244618162 ps |
| CPU time | 1.15 seconds |
| Started | Feb 04 12:53:30 PM PST 24 |
| Finished | Feb 04 12:53:33 PM PST 24 |
| Peak memory | 217236 kb |
| Host | smart-1173d7c1-5574-416f-8ced-2dd3aa761304 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3169013139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3169013139 |
| Directory | /workspace/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/37.rstmgr_por_stretcher.3660732472 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 201779212 ps |
| CPU time | 0.87 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:53:41 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-bb98a199-9fc2-487d-b1c1-5632cd38bbeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660732472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3660732472 |
| Directory | /workspace/37.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/37.rstmgr_reset.14587423 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1325882184 ps |
| CPU time | 5.13 seconds |
| Started | Feb 04 12:53:44 PM PST 24 |
| Finished | Feb 04 12:53:51 PM PST 24 |
| Peak memory | 200284 kb |
| Host | smart-7bf99a45-0659-419f-8107-87b36905751a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14587423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.14587423 |
| Directory | /workspace/37.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3924967639 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 106947388 ps |
| CPU time | 0.97 seconds |
| Started | Feb 04 12:53:40 PM PST 24 |
| Finished | Feb 04 12:53:42 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-016c082d-6cd9-4c98-a1ad-9ce8db596dea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924967639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3924967639 |
| Directory | /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/37.rstmgr_smoke.1979287906 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 124330628 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:53:40 PM PST 24 |
| Finished | Feb 04 12:53:42 PM PST 24 |
| Peak memory | 200112 kb |
| Host | smart-57b13761-1f28-4ce1-97e1-15bf0051bf75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1979287906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1979287906 |
| Directory | /workspace/37.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/37.rstmgr_stress_all.736463993 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 8949858233 ps |
| CPU time | 30.69 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:54:11 PM PST 24 |
| Peak memory | 200324 kb |
| Host | smart-6116fbf6-433d-484e-8685-4365a7d88cfc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736463993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.736463993 |
| Directory | /workspace/37.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sw_rst.1454854758 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 441110514 ps |
| CPU time | 2.94 seconds |
| Started | Feb 04 12:53:42 PM PST 24 |
| Finished | Feb 04 12:53:46 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-02c3bc60-30aa-4bd9-a41e-aadd72786069 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454854758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1454854758 |
| Directory | /workspace/37.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.417579636 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 135367235 ps |
| CPU time | 1.24 seconds |
| Started | Feb 04 12:53:41 PM PST 24 |
| Finished | Feb 04 12:53:43 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-0ca2123f-53ad-492d-a794-86e08f4f0732 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417579636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.417579636 |
| Directory | /workspace/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/38.rstmgr_alert_test.2827321505 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 57868125 ps |
| CPU time | 0.7 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:48 PM PST 24 |
| Peak memory | 199908 kb |
| Host | smart-927cea5e-fcd9-4742-ab7c-8b23fafb0f1a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827321505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2827321505 |
| Directory | /workspace/38.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1362715622 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1878877014 ps |
| CPU time | 7.05 seconds |
| Started | Feb 04 12:53:45 PM PST 24 |
| Finished | Feb 04 12:53:54 PM PST 24 |
| Peak memory | 221936 kb |
| Host | smart-c8b64efc-3c42-4a07-ba87-718377f25715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362715622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1362715622 |
| Directory | /workspace/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1874246037 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 244453733 ps |
| CPU time | 1.15 seconds |
| Started | Feb 04 12:53:48 PM PST 24 |
| Finished | Feb 04 12:53:52 PM PST 24 |
| Peak memory | 217212 kb |
| Host | smart-eeb4675c-7346-4597-9c00-54de4c7e0ff9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1874246037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1874246037 |
| Directory | /workspace/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/38.rstmgr_por_stretcher.669994138 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 215273766 ps |
| CPU time | 0.85 seconds |
| Started | Feb 04 12:53:49 PM PST 24 |
| Finished | Feb 04 12:53:52 PM PST 24 |
| Peak memory | 199868 kb |
| Host | smart-019205e6-591f-4f48-8cb6-5b9d8ceb4940 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669994138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.669994138 |
| Directory | /workspace/38.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/38.rstmgr_reset.1876583925 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1959209570 ps |
| CPU time | 7.48 seconds |
| Started | Feb 04 12:53:44 PM PST 24 |
| Finished | Feb 04 12:53:54 PM PST 24 |
| Peak memory | 200276 kb |
| Host | smart-84d72fc4-89d5-4f03-8e8f-67587d1cf6e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876583925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1876583925 |
| Directory | /workspace/38.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.4140753412 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 96204735 ps |
| CPU time | 0.95 seconds |
| Started | Feb 04 12:53:49 PM PST 24 |
| Finished | Feb 04 12:53:53 PM PST 24 |
| Peak memory | 200068 kb |
| Host | smart-7e67874b-121e-4506-8d26-f1f777ca01ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140753412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.4140753412 |
| Directory | /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/38.rstmgr_smoke.1616085412 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 117500050 ps |
| CPU time | 1.09 seconds |
| Started | Feb 04 12:53:43 PM PST 24 |
| Finished | Feb 04 12:53:45 PM PST 24 |
| Peak memory | 200216 kb |
| Host | smart-7a310fb3-e74a-456d-9426-951e310e2e4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616085412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1616085412 |
| Directory | /workspace/38.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/38.rstmgr_stress_all.647576823 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 9364404897 ps |
| CPU time | 32.34 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:54:21 PM PST 24 |
| Peak memory | 200292 kb |
| Host | smart-7b6241d9-330d-497a-88b4-8e449e562412 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647576823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.647576823 |
| Directory | /workspace/38.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sw_rst.1335555225 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 262150310 ps |
| CPU time | 1.77 seconds |
| Started | Feb 04 12:53:40 PM PST 24 |
| Finished | Feb 04 12:53:43 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-a384e546-5e29-485a-a6f7-840c3cb7fee8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335555225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1335555225 |
| Directory | /workspace/38.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3181202274 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 77078906 ps |
| CPU time | 0.76 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:48 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-37a6ad92-29c9-47ea-aa27-63e66f12e2c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3181202274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3181202274 |
| Directory | /workspace/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/39.rstmgr_alert_test.745221478 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 68818188 ps |
| CPU time | 0.73 seconds |
| Started | Feb 04 12:53:54 PM PST 24 |
| Finished | Feb 04 12:54:00 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-dac17534-2998-4ddc-a6b9-ce22e26a06b5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745221478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.745221478 |
| Directory | /workspace/39.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3170147935 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2365127964 ps |
| CPU time | 7.93 seconds |
| Started | Feb 04 12:53:47 PM PST 24 |
| Finished | Feb 04 12:53:58 PM PST 24 |
| Peak memory | 217944 kb |
| Host | smart-09461c89-5d5a-49fd-b81b-d99375d9efea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170147935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3170147935 |
| Directory | /workspace/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2778493002 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 244149790 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:55 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 217300 kb |
| Host | smart-ee407c9d-6c43-4e6a-b428-89f4a9c73d3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2778493002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2778493002 |
| Directory | /workspace/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/39.rstmgr_por_stretcher.1148416429 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 126865810 ps |
| CPU time | 0.79 seconds |
| Started | Feb 04 12:53:55 PM PST 24 |
| Finished | Feb 04 12:54:00 PM PST 24 |
| Peak memory | 199644 kb |
| Host | smart-7817de6a-e5f7-489f-95e8-4f130c84a8c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148416429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1148416429 |
| Directory | /workspace/39.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/39.rstmgr_reset.341451704 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 811656104 ps |
| CPU time | 3.93 seconds |
| Started | Feb 04 12:53:53 PM PST 24 |
| Finished | Feb 04 12:54:03 PM PST 24 |
| Peak memory | 200236 kb |
| Host | smart-a0e7bc25-e6ba-42a4-85d4-167452622fce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=341451704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.341451704 |
| Directory | /workspace/39.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2977053534 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 173534769 ps |
| CPU time | 1.14 seconds |
| Started | Feb 04 12:53:54 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 200020 kb |
| Host | smart-4fadbe2b-0419-4220-9e49-2aa36954389a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977053534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2977053534 |
| Directory | /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/39.rstmgr_smoke.2765738536 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 197786909 ps |
| CPU time | 1.27 seconds |
| Started | Feb 04 12:53:45 PM PST 24 |
| Finished | Feb 04 12:53:48 PM PST 24 |
| Peak memory | 200192 kb |
| Host | smart-52e1d78b-4a45-4b3a-bd6f-18ac22be4e31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765738536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2765738536 |
| Directory | /workspace/39.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/39.rstmgr_stress_all.2502403647 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 191274092 ps |
| CPU time | 1.45 seconds |
| Started | Feb 04 12:53:52 PM PST 24 |
| Finished | Feb 04 12:54:00 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-91b0257f-fa1a-4e6b-88a0-5acebe27ef96 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502403647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2502403647 |
| Directory | /workspace/39.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sw_rst.2811928037 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 127773117 ps |
| CPU time | 1.5 seconds |
| Started | Feb 04 12:53:54 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-a52822f8-bb63-405a-8743-f9ec610d970d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811928037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2811928037 |
| Directory | /workspace/39.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1683507845 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 223870919 ps |
| CPU time | 1.35 seconds |
| Started | Feb 04 12:53:55 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199908 kb |
| Host | smart-9f157b94-49da-4506-a04e-48f073945aac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683507845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1683507845 |
| Directory | /workspace/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/4.rstmgr_alert_test.2427479915 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 84370581 ps |
| CPU time | 0.75 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199664 kb |
| Host | smart-00d13a03-7828-45e8-8b4a-0f41263c64b0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427479915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2427479915 |
| Directory | /workspace/4.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1614276990 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1224160416 ps |
| CPU time | 5.43 seconds |
| Started | Feb 04 12:51:58 PM PST 24 |
| Finished | Feb 04 12:52:07 PM PST 24 |
| Peak memory | 217900 kb |
| Host | smart-3c8007c2-20fd-4a06-adf6-c5be5f518a3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614276990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1614276990 |
| Directory | /workspace/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2056900620 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 244569202 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:51:55 PM PST 24 |
| Finished | Feb 04 12:51:58 PM PST 24 |
| Peak memory | 217272 kb |
| Host | smart-18f013e5-e593-4e5a-ba4b-d5d40c2329e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056900620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2056900620 |
| Directory | /workspace/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/4.rstmgr_por_stretcher.2860645489 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 104654364 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:52:13 PM PST 24 |
| Finished | Feb 04 12:52:16 PM PST 24 |
| Peak memory | 199944 kb |
| Host | smart-6bf97694-e01e-4bc2-b5d3-7abd0cd380c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860645489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2860645489 |
| Directory | /workspace/4.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/4.rstmgr_reset.1551982321 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1598624967 ps |
| CPU time | 6.18 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 200308 kb |
| Host | smart-aafad798-cfaa-44ff-ad2e-78d3c0e496c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551982321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1551982321 |
| Directory | /workspace/4.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sec_cm.3048783854 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8310548337 ps |
| CPU time | 12.83 seconds |
| Started | Feb 04 12:51:57 PM PST 24 |
| Finished | Feb 04 12:52:13 PM PST 24 |
| Peak memory | 216860 kb |
| Host | smart-8a3c6765-cc22-44ba-b7d3-ba7c22916b88 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048783854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3048783854 |
| Directory | /workspace/4.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2140456901 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 109776674 ps |
| CPU time | 0.99 seconds |
| Started | Feb 04 12:51:58 PM PST 24 |
| Finished | Feb 04 12:52:02 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-ab5aa5b6-1d15-4060-b925-499e8c740118 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140456901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2140456901 |
| Directory | /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/4.rstmgr_smoke.3031102151 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 111161621 ps |
| CPU time | 1.12 seconds |
| Started | Feb 04 12:51:56 PM PST 24 |
| Finished | Feb 04 12:52:00 PM PST 24 |
| Peak memory | 200140 kb |
| Host | smart-e6e22a7d-bbab-40e4-8d9c-de811bbffbd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031102151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3031102151 |
| Directory | /workspace/4.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/4.rstmgr_stress_all.1728316165 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2479255279 ps |
| CPU time | 9.33 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:09 PM PST 24 |
| Peak memory | 199848 kb |
| Host | smart-e17353d3-5ed4-4aee-a716-f8a0d2ddf1a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728316165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1728316165 |
| Directory | /workspace/4.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sw_rst.2204427079 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 413283038 ps |
| CPU time | 2.15 seconds |
| Started | Feb 04 12:51:58 PM PST 24 |
| Finished | Feb 04 12:52:03 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-fa2f5ee8-2cb0-4dd8-8987-4583373fac0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204427079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2204427079 |
| Directory | /workspace/4.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.105271253 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 96749459 ps |
| CPU time | 0.88 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:19 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-af159610-6b23-473e-96fa-abeb597f57d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105271253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.105271253 |
| Directory | /workspace/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/40.rstmgr_alert_test.2765827937 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 83825981 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:53:35 PM PST 24 |
| Finished | Feb 04 12:53:38 PM PST 24 |
| Peak memory | 199516 kb |
| Host | smart-7318d8a3-8a35-4fe4-bf5f-aa825c60ce0d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765827937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2765827937 |
| Directory | /workspace/40.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2563209399 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2176597090 ps |
| CPU time | 7.44 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:53:47 PM PST 24 |
| Peak memory | 217304 kb |
| Host | smart-b373633d-9375-4ad2-aade-2fa6573f8895 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2563209399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2563209399 |
| Directory | /workspace/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.807945777 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 245358738 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:53:58 PM PST 24 |
| Finished | Feb 04 12:54:02 PM PST 24 |
| Peak memory | 217228 kb |
| Host | smart-47c13687-5797-486f-995e-5748b2bcfa8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807945777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.807945777 |
| Directory | /workspace/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/40.rstmgr_por_stretcher.357903738 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 72646767 ps |
| CPU time | 0.69 seconds |
| Started | Feb 04 12:53:48 PM PST 24 |
| Finished | Feb 04 12:53:52 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-ed39ffb9-4317-48e4-9b1e-f002f67cfcee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357903738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.357903738 |
| Directory | /workspace/40.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/40.rstmgr_reset.2699818393 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1035423939 ps |
| CPU time | 4.98 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:05 PM PST 24 |
| Peak memory | 200244 kb |
| Host | smart-2d4425fb-55da-4032-95c2-c70e84e82d23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2699818393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2699818393 |
| Directory | /workspace/40.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.675748701 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 101121492 ps |
| CPU time | 1.09 seconds |
| Started | Feb 04 12:53:50 PM PST 24 |
| Finished | Feb 04 12:53:53 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-4316d936-512b-4885-b9d8-8486b616536d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=675748701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.675748701 |
| Directory | /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/40.rstmgr_smoke.3226196577 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 204912041 ps |
| CPU time | 1.33 seconds |
| Started | Feb 04 12:53:49 PM PST 24 |
| Finished | Feb 04 12:53:53 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-4da9e09a-f31c-46b1-8fec-8714f99c8d20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226196577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3226196577 |
| Directory | /workspace/40.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/40.rstmgr_stress_all.1189150164 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1248786674 ps |
| CPU time | 6.05 seconds |
| Started | Feb 04 12:53:58 PM PST 24 |
| Finished | Feb 04 12:54:08 PM PST 24 |
| Peak memory | 200228 kb |
| Host | smart-c803abd4-03f6-477f-a8b6-281154ece000 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189150164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1189150164 |
| Directory | /workspace/40.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sw_rst.3685262445 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 142247225 ps |
| CPU time | 1.77 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:02 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-6872bda8-9641-4b24-a36e-ac7003a2a22a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685262445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3685262445 |
| Directory | /workspace/40.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2236677185 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 195911036 ps |
| CPU time | 1.24 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-f852aea1-9dd7-493a-9373-b33ec25f15b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236677185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2236677185 |
| Directory | /workspace/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/41.rstmgr_alert_test.1234857031 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 62947396 ps |
| CPU time | 0.73 seconds |
| Started | Feb 04 12:53:37 PM PST 24 |
| Finished | Feb 04 12:53:39 PM PST 24 |
| Peak memory | 199792 kb |
| Host | smart-63e33c52-421d-4e91-b16e-5ff25fe5524b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234857031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1234857031 |
| Directory | /workspace/41.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3496581464 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1899841252 ps |
| CPU time | 6.89 seconds |
| Started | Feb 04 12:53:38 PM PST 24 |
| Finished | Feb 04 12:53:46 PM PST 24 |
| Peak memory | 220940 kb |
| Host | smart-5616a2e3-70f5-4f21-b3df-8b6b202fa757 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3496581464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3496581464 |
| Directory | /workspace/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.660923168 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 245036090 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:58 PM PST 24 |
| Finished | Feb 04 12:54:03 PM PST 24 |
| Peak memory | 217280 kb |
| Host | smart-1655abdd-94f7-4b37-8d55-59826f531562 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660923168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.660923168 |
| Directory | /workspace/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/41.rstmgr_por_stretcher.1347448987 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 78484994 ps |
| CPU time | 0.73 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:00 PM PST 24 |
| Peak memory | 199860 kb |
| Host | smart-c9a2134f-f616-4f4f-b4fd-933017602b92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1347448987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1347448987 |
| Directory | /workspace/41.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/41.rstmgr_reset.3732945615 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1622919093 ps |
| CPU time | 6.57 seconds |
| Started | Feb 04 12:53:36 PM PST 24 |
| Finished | Feb 04 12:53:44 PM PST 24 |
| Peak memory | 200260 kb |
| Host | smart-7cd0b918-97ff-4a13-985f-1c5aadad8ca4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732945615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3732945615 |
| Directory | /workspace/41.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4004860138 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 139330102 ps |
| CPU time | 1.2 seconds |
| Started | Feb 04 12:53:40 PM PST 24 |
| Finished | Feb 04 12:53:43 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-e014dc68-77f4-4127-aeaa-0faf12d008e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004860138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4004860138 |
| Directory | /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/41.rstmgr_smoke.2524665068 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 254282315 ps |
| CPU time | 1.52 seconds |
| Started | Feb 04 12:53:40 PM PST 24 |
| Finished | Feb 04 12:53:43 PM PST 24 |
| Peak memory | 200252 kb |
| Host | smart-d64f0e49-a80c-4366-9b54-2a58d4801e25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524665068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2524665068 |
| Directory | /workspace/41.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/41.rstmgr_stress_all.3583001873 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 430281697 ps |
| CPU time | 2.21 seconds |
| Started | Feb 04 12:53:37 PM PST 24 |
| Finished | Feb 04 12:53:41 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-c290760f-e036-4db4-b683-88b0a5d20e0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583001873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3583001873 |
| Directory | /workspace/41.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sw_rst.2621382484 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 368331583 ps |
| CPU time | 2 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:51 PM PST 24 |
| Peak memory | 199972 kb |
| Host | smart-3164e904-da62-403e-a978-e4ac37c59c26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2621382484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2621382484 |
| Directory | /workspace/41.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1486565316 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 194193901 ps |
| CPU time | 1.2 seconds |
| Started | Feb 04 12:53:37 PM PST 24 |
| Finished | Feb 04 12:53:39 PM PST 24 |
| Peak memory | 200028 kb |
| Host | smart-90743af8-a154-44b9-b44e-d6c204d3ccd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486565316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1486565316 |
| Directory | /workspace/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/42.rstmgr_alert_test.3368784268 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 80907684 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:49 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-96e5d70e-c6cc-47e2-815b-9875443b7b56 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368784268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3368784268 |
| Directory | /workspace/42.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1355847601 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1226998719 ps |
| CPU time | 5.71 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:53:47 PM PST 24 |
| Peak memory | 216808 kb |
| Host | smart-a8892561-60e7-47cd-b9b1-7d5c4bed22b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355847601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1355847601 |
| Directory | /workspace/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.899482274 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 243943191 ps |
| CPU time | 1.13 seconds |
| Started | Feb 04 12:53:47 PM PST 24 |
| Finished | Feb 04 12:53:50 PM PST 24 |
| Peak memory | 217284 kb |
| Host | smart-5250e41d-bc62-4750-8cf2-8660f1048c97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899482274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.899482274 |
| Directory | /workspace/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/42.rstmgr_por_stretcher.3499685689 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 132899704 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:53:40 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-df4c721b-b8a4-499c-9c43-5ad0e80d2c14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499685689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3499685689 |
| Directory | /workspace/42.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/42.rstmgr_reset.2219107732 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1561366681 ps |
| CPU time | 5.8 seconds |
| Started | Feb 04 12:53:44 PM PST 24 |
| Finished | Feb 04 12:53:52 PM PST 24 |
| Peak memory | 200232 kb |
| Host | smart-b503c68f-df70-4746-bafc-d2019419a1f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219107732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2219107732 |
| Directory | /workspace/42.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2913510984 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 101954131 ps |
| CPU time | 0.92 seconds |
| Started | Feb 04 12:53:44 PM PST 24 |
| Finished | Feb 04 12:53:46 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-9f7f631b-4333-42f1-b43d-6dc1a46a3b53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913510984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2913510984 |
| Directory | /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/42.rstmgr_smoke.2509620444 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 191119175 ps |
| CPU time | 1.29 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:53:41 PM PST 24 |
| Peak memory | 200192 kb |
| Host | smart-2bddc674-e8c0-4c21-adb9-74b11830dc74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2509620444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2509620444 |
| Directory | /workspace/42.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/42.rstmgr_stress_all.2343432183 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2651138670 ps |
| CPU time | 11.56 seconds |
| Started | Feb 04 12:53:45 PM PST 24 |
| Finished | Feb 04 12:53:58 PM PST 24 |
| Peak memory | 200328 kb |
| Host | smart-6f80e5ce-e564-4089-a5d1-2f87867d187f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343432183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2343432183 |
| Directory | /workspace/42.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sw_rst.4235337135 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 274864540 ps |
| CPU time | 1.86 seconds |
| Started | Feb 04 12:53:42 PM PST 24 |
| Finished | Feb 04 12:53:45 PM PST 24 |
| Peak memory | 200080 kb |
| Host | smart-2b9c548b-3b6f-4180-a70d-85b597f967fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235337135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.4235337135 |
| Directory | /workspace/42.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3634415436 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 92776111 ps |
| CPU time | 0.9 seconds |
| Started | Feb 04 12:53:40 PM PST 24 |
| Finished | Feb 04 12:53:42 PM PST 24 |
| Peak memory | 200036 kb |
| Host | smart-d619dc08-2218-4e0b-91ff-54e577fed83f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3634415436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3634415436 |
| Directory | /workspace/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/43.rstmgr_alert_test.1580180112 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 93614829 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199868 kb |
| Host | smart-1f864be7-f3be-49f5-a91e-3db55ca3a067 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580180112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1580180112 |
| Directory | /workspace/43.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1844290036 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1223376394 ps |
| CPU time | 5.51 seconds |
| Started | Feb 04 12:53:52 PM PST 24 |
| Finished | Feb 04 12:54:04 PM PST 24 |
| Peak memory | 218304 kb |
| Host | smart-3cee0029-e96d-4865-a7e9-11fe33608035 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844290036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1844290036 |
| Directory | /workspace/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.54207809 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 244281020 ps |
| CPU time | 1.09 seconds |
| Started | Feb 04 12:53:54 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 217356 kb |
| Host | smart-e0150a97-5d1f-46b2-b1f6-c0f4c1afb0e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54207809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.54207809 |
| Directory | /workspace/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/43.rstmgr_por_stretcher.1290267343 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 196398479 ps |
| CPU time | 0.92 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:48 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-c601479a-d444-4d31-8606-e29b88208e58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290267343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1290267343 |
| Directory | /workspace/43.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/43.rstmgr_reset.954672995 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1333324111 ps |
| CPU time | 5.34 seconds |
| Started | Feb 04 12:53:47 PM PST 24 |
| Finished | Feb 04 12:53:54 PM PST 24 |
| Peak memory | 200164 kb |
| Host | smart-784de085-c896-4528-b21b-cbc9af166502 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954672995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.954672995 |
| Directory | /workspace/43.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3031503130 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 169990101 ps |
| CPU time | 1.17 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:49 PM PST 24 |
| Peak memory | 200004 kb |
| Host | smart-3e271ed2-7862-471e-bdfd-2a9d026a66b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031503130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3031503130 |
| Directory | /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/43.rstmgr_smoke.566860212 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 194364534 ps |
| CPU time | 1.41 seconds |
| Started | Feb 04 12:53:47 PM PST 24 |
| Finished | Feb 04 12:53:51 PM PST 24 |
| Peak memory | 200100 kb |
| Host | smart-bb2c5467-db69-4833-a743-39bb047735e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566860212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.566860212 |
| Directory | /workspace/43.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/43.rstmgr_stress_all.1689244185 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2097712555 ps |
| CPU time | 9.36 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:57 PM PST 24 |
| Peak memory | 200280 kb |
| Host | smart-88b50e53-82c7-4f41-9a2f-4555c5bbb18b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689244185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1689244185 |
| Directory | /workspace/43.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sw_rst.854711157 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 524990882 ps |
| CPU time | 2.53 seconds |
| Started | Feb 04 12:53:48 PM PST 24 |
| Finished | Feb 04 12:53:54 PM PST 24 |
| Peak memory | 200080 kb |
| Host | smart-a1b2a135-6d98-4fe6-8b36-46367841439f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854711157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.854711157 |
| Directory | /workspace/43.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.733837816 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 157105865 ps |
| CPU time | 1.09 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199976 kb |
| Host | smart-a0760cf4-4868-4fcc-9f27-aa9ca238dcf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733837816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.733837816 |
| Directory | /workspace/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/44.rstmgr_alert_test.1670857055 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 57331049 ps |
| CPU time | 0.82 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199868 kb |
| Host | smart-60bf9cf3-5937-4948-953e-fed731ddd986 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670857055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1670857055 |
| Directory | /workspace/44.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.436955230 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1903467142 ps |
| CPU time | 7.95 seconds |
| Started | Feb 04 12:53:55 PM PST 24 |
| Finished | Feb 04 12:54:07 PM PST 24 |
| Peak memory | 217204 kb |
| Host | smart-b4ace38e-f490-492d-b625-7ed9ec2dbb47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436955230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.436955230 |
| Directory | /workspace/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3050746616 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 244031493 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:53:54 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 217264 kb |
| Host | smart-c1bdab0a-0da4-4918-9419-ac9be0c445cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050746616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3050746616 |
| Directory | /workspace/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/44.rstmgr_por_stretcher.2495421047 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 156530987 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:53:47 PM PST 24 |
| Finished | Feb 04 12:53:50 PM PST 24 |
| Peak memory | 199836 kb |
| Host | smart-8f8d1666-a787-42e3-be94-d4c095ca4363 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2495421047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2495421047 |
| Directory | /workspace/44.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/44.rstmgr_reset.2738873410 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1783501041 ps |
| CPU time | 6.81 seconds |
| Started | Feb 04 12:53:47 PM PST 24 |
| Finished | Feb 04 12:53:57 PM PST 24 |
| Peak memory | 200204 kb |
| Host | smart-362c5296-ce24-4af7-9023-4115d0af2931 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2738873410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2738873410 |
| Directory | /workspace/44.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4109482545 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 94742601 ps |
| CPU time | 0.96 seconds |
| Started | Feb 04 12:53:56 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199624 kb |
| Host | smart-d3ae9ab1-8ae9-49dc-85b6-7f6e10a312a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109482545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.4109482545 |
| Directory | /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/44.rstmgr_smoke.234668359 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 250526699 ps |
| CPU time | 1.52 seconds |
| Started | Feb 04 12:53:48 PM PST 24 |
| Finished | Feb 04 12:53:53 PM PST 24 |
| Peak memory | 200144 kb |
| Host | smart-0120b5f4-1e2f-4d3f-83e6-688170263219 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234668359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.234668359 |
| Directory | /workspace/44.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/44.rstmgr_stress_all.1966760872 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3391138076 ps |
| CPU time | 15.45 seconds |
| Started | Feb 04 12:53:54 PM PST 24 |
| Finished | Feb 04 12:54:15 PM PST 24 |
| Peak memory | 200288 kb |
| Host | smart-aa788279-2f06-4eef-b6b5-f69481a61a9f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966760872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1966760872 |
| Directory | /workspace/44.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sw_rst.1024255350 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 115536561 ps |
| CPU time | 1.45 seconds |
| Started | Feb 04 12:53:56 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199532 kb |
| Host | smart-b62ff0fa-7406-4d5f-963b-7dc8fba78e12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024255350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1024255350 |
| Directory | /workspace/44.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1101938930 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 255861401 ps |
| CPU time | 1.63 seconds |
| Started | Feb 04 12:53:47 PM PST 24 |
| Finished | Feb 04 12:53:52 PM PST 24 |
| Peak memory | 199972 kb |
| Host | smart-356dd018-85b7-4316-a58f-9833b03620bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101938930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1101938930 |
| Directory | /workspace/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/45.rstmgr_alert_test.1802893687 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 84527105 ps |
| CPU time | 0.81 seconds |
| Started | Feb 04 12:53:50 PM PST 24 |
| Finished | Feb 04 12:53:53 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-95c6ec75-6902-4d47-b2f4-91893bb11dfb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802893687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1802893687 |
| Directory | /workspace/45.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.512454100 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1218416386 ps |
| CPU time | 5.7 seconds |
| Started | Feb 04 12:53:52 PM PST 24 |
| Finished | Feb 04 12:54:04 PM PST 24 |
| Peak memory | 216728 kb |
| Host | smart-5658ecb0-fd2a-4237-8cfb-66b2c13bcc8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512454100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.512454100 |
| Directory | /workspace/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2676406557 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 244875128 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 217256 kb |
| Host | smart-137848db-e8b2-45c4-bb32-227db2e83ce9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2676406557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2676406557 |
| Directory | /workspace/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/45.rstmgr_por_stretcher.1314714406 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 169031717 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:53:49 PM PST 24 |
| Finished | Feb 04 12:53:53 PM PST 24 |
| Peak memory | 199696 kb |
| Host | smart-f9254b2f-8bfd-4c71-8f8e-0b384894d3cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314714406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1314714406 |
| Directory | /workspace/45.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/45.rstmgr_reset.4243376390 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 853868084 ps |
| CPU time | 4.3 seconds |
| Started | Feb 04 12:53:58 PM PST 24 |
| Finished | Feb 04 12:54:05 PM PST 24 |
| Peak memory | 200164 kb |
| Host | smart-6ad736c3-e4fb-46f6-ae34-452c9a05f5f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243376390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.4243376390 |
| Directory | /workspace/45.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3945711852 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 178487734 ps |
| CPU time | 1.25 seconds |
| Started | Feb 04 12:53:59 PM PST 24 |
| Finished | Feb 04 12:54:04 PM PST 24 |
| Peak memory | 200016 kb |
| Host | smart-2883f969-877f-4ea8-9d08-1f259470317d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945711852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3945711852 |
| Directory | /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/45.rstmgr_smoke.1431014268 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 119367738 ps |
| CPU time | 1.2 seconds |
| Started | Feb 04 12:53:56 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-3946aab5-802d-4c2c-907e-1fe8b73cd5a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431014268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1431014268 |
| Directory | /workspace/45.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/45.rstmgr_stress_all.2484274171 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 246536039 ps |
| CPU time | 1.46 seconds |
| Started | Feb 04 12:54:00 PM PST 24 |
| Finished | Feb 04 12:54:04 PM PST 24 |
| Peak memory | 199868 kb |
| Host | smart-70d5bcb0-a9a6-4c94-a55a-fc83ecc27b0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484274171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2484274171 |
| Directory | /workspace/45.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sw_rst.701089502 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 430324069 ps |
| CPU time | 2.34 seconds |
| Started | Feb 04 12:53:58 PM PST 24 |
| Finished | Feb 04 12:54:05 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-af0db2e0-6683-4d85-946c-afbabb836bcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701089502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.701089502 |
| Directory | /workspace/45.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1130777264 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 109572744 ps |
| CPU time | 0.88 seconds |
| Started | Feb 04 12:53:50 PM PST 24 |
| Finished | Feb 04 12:53:53 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-416e9f86-4342-43a7-a560-263ea7f7f2f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130777264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1130777264 |
| Directory | /workspace/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/46.rstmgr_alert_test.2750490166 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 96405898 ps |
| CPU time | 0.83 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:53:40 PM PST 24 |
| Peak memory | 199908 kb |
| Host | smart-92213f95-869e-4825-96c3-b418c6296f8f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750490166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2750490166 |
| Directory | /workspace/46.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4126077296 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2361348839 ps |
| CPU time | 8.02 seconds |
| Started | Feb 04 12:53:37 PM PST 24 |
| Finished | Feb 04 12:53:46 PM PST 24 |
| Peak memory | 217928 kb |
| Host | smart-b5e8e8d5-a3b0-4e13-a290-3b64fbbd0bc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126077296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4126077296 |
| Directory | /workspace/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2705439443 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 245325066 ps |
| CPU time | 1.04 seconds |
| Started | Feb 04 12:53:38 PM PST 24 |
| Finished | Feb 04 12:53:41 PM PST 24 |
| Peak memory | 217352 kb |
| Host | smart-f3ca1eef-4649-49a5-ac35-8eb5b7f6ed58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705439443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2705439443 |
| Directory | /workspace/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/46.rstmgr_por_stretcher.1357509162 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 126655388 ps |
| CPU time | 0.79 seconds |
| Started | Feb 04 12:53:30 PM PST 24 |
| Finished | Feb 04 12:53:32 PM PST 24 |
| Peak memory | 199860 kb |
| Host | smart-d751bcff-879d-472a-9756-3ed104d907e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357509162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1357509162 |
| Directory | /workspace/46.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/46.rstmgr_reset.3600418456 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2091182418 ps |
| CPU time | 7.71 seconds |
| Started | Feb 04 12:53:41 PM PST 24 |
| Finished | Feb 04 12:53:50 PM PST 24 |
| Peak memory | 200104 kb |
| Host | smart-1d43716e-2d12-4ed6-ad6c-a14faa5ae0ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600418456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3600418456 |
| Directory | /workspace/46.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3998692786 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 101166041 ps |
| CPU time | 0.92 seconds |
| Started | Feb 04 12:53:36 PM PST 24 |
| Finished | Feb 04 12:53:38 PM PST 24 |
| Peak memory | 199988 kb |
| Host | smart-53fc2b96-13b2-465a-9c89-9befe1a029cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998692786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3998692786 |
| Directory | /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/46.rstmgr_smoke.568683450 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 111998697 ps |
| CPU time | 1.13 seconds |
| Started | Feb 04 12:53:39 PM PST 24 |
| Finished | Feb 04 12:53:41 PM PST 24 |
| Peak memory | 200224 kb |
| Host | smart-dfbe1032-ccf0-465b-987b-4e2f958cafb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568683450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.568683450 |
| Directory | /workspace/46.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/46.rstmgr_stress_all.3911138521 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 15808239097 ps |
| CPU time | 55.78 seconds |
| Started | Feb 04 12:53:35 PM PST 24 |
| Finished | Feb 04 12:54:33 PM PST 24 |
| Peak memory | 200316 kb |
| Host | smart-2aec435e-5401-4c1a-b84c-d5ac91905336 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911138521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3911138521 |
| Directory | /workspace/46.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sw_rst.908302248 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 150825083 ps |
| CPU time | 1.85 seconds |
| Started | Feb 04 12:53:43 PM PST 24 |
| Finished | Feb 04 12:53:46 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-0aefca3f-7602-4a19-86af-9fb1d2b29851 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908302248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.908302248 |
| Directory | /workspace/46.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.618992427 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 187333656 ps |
| CPU time | 1.24 seconds |
| Started | Feb 04 12:53:35 PM PST 24 |
| Finished | Feb 04 12:53:38 PM PST 24 |
| Peak memory | 199736 kb |
| Host | smart-e6aa97fa-2749-4e45-9e98-455fe700f5f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618992427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.618992427 |
| Directory | /workspace/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/47.rstmgr_alert_test.2766451248 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 73399776 ps |
| CPU time | 0.75 seconds |
| Started | Feb 04 12:53:40 PM PST 24 |
| Finished | Feb 04 12:53:42 PM PST 24 |
| Peak memory | 199924 kb |
| Host | smart-97007032-a3d0-4171-96fe-3a5f8a1b135f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766451248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2766451248 |
| Directory | /workspace/47.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2535211723 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1882552130 ps |
| CPU time | 7.37 seconds |
| Started | Feb 04 12:53:44 PM PST 24 |
| Finished | Feb 04 12:53:54 PM PST 24 |
| Peak memory | 221372 kb |
| Host | smart-9420f26e-e79a-4069-baa9-48188a5a40e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2535211723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2535211723 |
| Directory | /workspace/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2553654490 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 243533958 ps |
| CPU time | 1.04 seconds |
| Started | Feb 04 12:53:48 PM PST 24 |
| Finished | Feb 04 12:53:52 PM PST 24 |
| Peak memory | 217368 kb |
| Host | smart-7c0a7de4-2559-4cf2-8ea4-8880198c2bcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2553654490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2553654490 |
| Directory | /workspace/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/47.rstmgr_por_stretcher.2684551993 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 106522277 ps |
| CPU time | 0.72 seconds |
| Started | Feb 04 12:53:37 PM PST 24 |
| Finished | Feb 04 12:53:39 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-75426740-b041-4367-a997-51ac85900d7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2684551993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2684551993 |
| Directory | /workspace/47.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/47.rstmgr_reset.4069440467 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 850295907 ps |
| CPU time | 4.07 seconds |
| Started | Feb 04 12:53:43 PM PST 24 |
| Finished | Feb 04 12:53:48 PM PST 24 |
| Peak memory | 200276 kb |
| Host | smart-a777af9e-2fd4-4931-a4a5-be0e939a2d9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4069440467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4069440467 |
| Directory | /workspace/47.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2175594891 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 189204295 ps |
| CPU time | 1.15 seconds |
| Started | Feb 04 12:53:44 PM PST 24 |
| Finished | Feb 04 12:53:46 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-8cd24de3-5873-4491-b42b-8a8ea321db9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175594891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2175594891 |
| Directory | /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/47.rstmgr_smoke.4018883155 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 192079507 ps |
| CPU time | 1.26 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:50 PM PST 24 |
| Peak memory | 200104 kb |
| Host | smart-c3d362ca-7431-412a-8271-ce5e3e103fc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018883155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4018883155 |
| Directory | /workspace/47.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/47.rstmgr_stress_all.3890298451 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7056968176 ps |
| CPU time | 32.44 seconds |
| Started | Feb 04 12:53:40 PM PST 24 |
| Finished | Feb 04 12:54:14 PM PST 24 |
| Peak memory | 200328 kb |
| Host | smart-dd305e02-d925-4a7e-bf2a-20470a192dc2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890298451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3890298451 |
| Directory | /workspace/47.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sw_rst.1291882398 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 129374482 ps |
| CPU time | 1.6 seconds |
| Started | Feb 04 12:53:44 PM PST 24 |
| Finished | Feb 04 12:53:48 PM PST 24 |
| Peak memory | 200084 kb |
| Host | smart-1a11b6e8-1a92-4a39-83cf-d9b121661aa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291882398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1291882398 |
| Directory | /workspace/47.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2520163944 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 76154118 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:53:43 PM PST 24 |
| Finished | Feb 04 12:53:45 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-6ebde9a3-73e3-4daf-8a5c-4ecbf71a8e34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520163944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2520163944 |
| Directory | /workspace/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/48.rstmgr_alert_test.422306469 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 74950610 ps |
| CPU time | 0.83 seconds |
| Started | Feb 04 12:53:47 PM PST 24 |
| Finished | Feb 04 12:53:50 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-6863b743-e77d-40e3-bc22-f797970b72c4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422306469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.422306469 |
| Directory | /workspace/48.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1011876090 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1884469836 ps |
| CPU time | 7 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:55 PM PST 24 |
| Peak memory | 217948 kb |
| Host | smart-934c8cc8-1164-4b38-8603-577e04e93d0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011876090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1011876090 |
| Directory | /workspace/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3551261274 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 246497232 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:53:50 PM PST 24 |
| Peak memory | 217284 kb |
| Host | smart-9bf9bcc0-0a7e-4c25-9a82-d060dccee2f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551261274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3551261274 |
| Directory | /workspace/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/48.rstmgr_por_stretcher.945245992 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 133951768 ps |
| CPU time | 0.84 seconds |
| Started | Feb 04 12:53:42 PM PST 24 |
| Finished | Feb 04 12:53:44 PM PST 24 |
| Peak memory | 199884 kb |
| Host | smart-8d0476fb-a57b-4405-9657-08044952f807 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945245992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.945245992 |
| Directory | /workspace/48.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/48.rstmgr_reset.3474177401 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1463991389 ps |
| CPU time | 5.92 seconds |
| Started | Feb 04 12:53:44 PM PST 24 |
| Finished | Feb 04 12:53:52 PM PST 24 |
| Peak memory | 200280 kb |
| Host | smart-53cf7af6-aeaf-4bc3-87e3-222e7619112e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474177401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3474177401 |
| Directory | /workspace/48.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.60671851 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 105153263 ps |
| CPU time | 1.01 seconds |
| Started | Feb 04 12:53:44 PM PST 24 |
| Finished | Feb 04 12:53:48 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-5a00536f-b14b-4bbd-90c1-c4c13336766d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60671851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.60671851 |
| Directory | /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/48.rstmgr_smoke.3435690657 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 186620871 ps |
| CPU time | 1.37 seconds |
| Started | Feb 04 12:53:48 PM PST 24 |
| Finished | Feb 04 12:53:52 PM PST 24 |
| Peak memory | 200236 kb |
| Host | smart-956c632e-b293-4cbf-81f3-07b91c6f5de1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435690657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3435690657 |
| Directory | /workspace/48.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/48.rstmgr_stress_all.1940746044 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 5767169698 ps |
| CPU time | 20.92 seconds |
| Started | Feb 04 12:53:46 PM PST 24 |
| Finished | Feb 04 12:54:08 PM PST 24 |
| Peak memory | 200268 kb |
| Host | smart-d437709b-58f4-45a8-a41b-2bf7ac500021 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940746044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1940746044 |
| Directory | /workspace/48.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sw_rst.433313798 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 139982003 ps |
| CPU time | 1.99 seconds |
| Started | Feb 04 12:53:41 PM PST 24 |
| Finished | Feb 04 12:53:44 PM PST 24 |
| Peak memory | 200084 kb |
| Host | smart-29c93098-02f9-4a4c-9fcd-096a77f7041a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433313798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.433313798 |
| Directory | /workspace/48.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2554192561 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 142150676 ps |
| CPU time | 0.97 seconds |
| Started | Feb 04 12:53:48 PM PST 24 |
| Finished | Feb 04 12:53:52 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-1fcf0c29-93eb-453d-81d9-e5ec31f876b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554192561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2554192561 |
| Directory | /workspace/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/49.rstmgr_alert_test.1612463735 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 60616171 ps |
| CPU time | 0.7 seconds |
| Started | Feb 04 12:53:55 PM PST 24 |
| Finished | Feb 04 12:54:00 PM PST 24 |
| Peak memory | 199836 kb |
| Host | smart-4e0356b3-b00c-4d43-9275-84b58aca976b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612463735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1612463735 |
| Directory | /workspace/49.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2011227689 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2356765461 ps |
| CPU time | 9.31 seconds |
| Started | Feb 04 12:53:48 PM PST 24 |
| Finished | Feb 04 12:54:00 PM PST 24 |
| Peak memory | 221996 kb |
| Host | smart-f7279f9c-d474-4c17-940b-9b4965307305 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011227689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2011227689 |
| Directory | /workspace/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2044942094 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 244030024 ps |
| CPU time | 1.06 seconds |
| Started | Feb 04 12:53:56 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 217216 kb |
| Host | smart-770805e1-5382-46f1-a25d-13ebe541664e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044942094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2044942094 |
| Directory | /workspace/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/49.rstmgr_por_stretcher.236104383 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 173328755 ps |
| CPU time | 0.87 seconds |
| Started | Feb 04 12:53:51 PM PST 24 |
| Finished | Feb 04 12:53:58 PM PST 24 |
| Peak memory | 199792 kb |
| Host | smart-afec0f9c-b0da-45fe-b316-7e42b31582fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236104383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.236104383 |
| Directory | /workspace/49.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/49.rstmgr_reset.3531884805 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1724174751 ps |
| CPU time | 7.05 seconds |
| Started | Feb 04 12:53:53 PM PST 24 |
| Finished | Feb 04 12:54:07 PM PST 24 |
| Peak memory | 200212 kb |
| Host | smart-cc408439-d499-4f99-a6f5-e8270a694d3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531884805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3531884805 |
| Directory | /workspace/49.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3468898239 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 102572152 ps |
| CPU time | 0.99 seconds |
| Started | Feb 04 12:53:52 PM PST 24 |
| Finished | Feb 04 12:53:59 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-34295620-3a2d-4648-ab87-bc5ba819819f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468898239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3468898239 |
| Directory | /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/49.rstmgr_smoke.1708573289 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 200242389 ps |
| CPU time | 1.36 seconds |
| Started | Feb 04 12:53:54 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 200176 kb |
| Host | smart-7f14351f-49e5-4830-a370-7ebf5de170b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708573289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1708573289 |
| Directory | /workspace/49.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/49.rstmgr_stress_all.2489786222 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 18699761785 ps |
| CPU time | 63.55 seconds |
| Started | Feb 04 12:53:47 PM PST 24 |
| Finished | Feb 04 12:54:54 PM PST 24 |
| Peak memory | 200264 kb |
| Host | smart-df389cab-f2d6-4581-a671-586c91b3134d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489786222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2489786222 |
| Directory | /workspace/49.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sw_rst.2681458212 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 118288099 ps |
| CPU time | 1.47 seconds |
| Started | Feb 04 12:53:52 PM PST 24 |
| Finished | Feb 04 12:54:00 PM PST 24 |
| Peak memory | 199932 kb |
| Host | smart-ea880684-3963-4ee6-9b69-a009446906f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681458212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2681458212 |
| Directory | /workspace/49.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1791077257 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 145951086 ps |
| CPU time | 1.01 seconds |
| Started | Feb 04 12:53:56 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199564 kb |
| Host | smart-5835ee73-f0c9-440e-b23a-b48269465764 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1791077257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1791077257 |
| Directory | /workspace/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/5.rstmgr_alert_test.4258128855 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 80689757 ps |
| CPU time | 0.8 seconds |
| Started | Feb 04 12:51:57 PM PST 24 |
| Finished | Feb 04 12:52:01 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-413c3d0d-0af8-4cfc-8e6e-409de1eecba2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258128855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4258128855 |
| Directory | /workspace/5.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.4286188505 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1906548378 ps |
| CPU time | 7.09 seconds |
| Started | Feb 04 12:51:59 PM PST 24 |
| Finished | Feb 04 12:52:11 PM PST 24 |
| Peak memory | 217188 kb |
| Host | smart-8169ca7e-d40a-46fd-a982-46997c49f33d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286188505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4286188505 |
| Directory | /workspace/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2074745378 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 244992113 ps |
| CPU time | 1.07 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 216872 kb |
| Host | smart-817c8484-cdd5-415a-8c41-bd368f4903d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074745378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2074745378 |
| Directory | /workspace/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/5.rstmgr_por_stretcher.2709893446 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 81902148 ps |
| CPU time | 0.75 seconds |
| Started | Feb 04 12:51:59 PM PST 24 |
| Finished | Feb 04 12:52:04 PM PST 24 |
| Peak memory | 199660 kb |
| Host | smart-78db0c43-2e54-44e7-9629-bd6143971c48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709893446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2709893446 |
| Directory | /workspace/5.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/5.rstmgr_reset.1944599615 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 706902562 ps |
| CPU time | 3.8 seconds |
| Started | Feb 04 12:52:03 PM PST 24 |
| Finished | Feb 04 12:52:10 PM PST 24 |
| Peak memory | 200236 kb |
| Host | smart-ab4c36c0-34fc-46f0-bd10-e987b6b34704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944599615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1944599615 |
| Directory | /workspace/5.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3549798505 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 164245248 ps |
| CPU time | 1.19 seconds |
| Started | Feb 04 12:51:59 PM PST 24 |
| Finished | Feb 04 12:52:05 PM PST 24 |
| Peak memory | 200132 kb |
| Host | smart-ef08abb6-d7a4-4928-b3de-6d04e965d2da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549798505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3549798505 |
| Directory | /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/5.rstmgr_smoke.1830442107 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 189700830 ps |
| CPU time | 1.31 seconds |
| Started | Feb 04 12:51:54 PM PST 24 |
| Finished | Feb 04 12:51:57 PM PST 24 |
| Peak memory | 200184 kb |
| Host | smart-a11049a0-362d-4b1f-813f-2970d2423148 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830442107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1830442107 |
| Directory | /workspace/5.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/5.rstmgr_stress_all.1847078759 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3251982104 ps |
| CPU time | 11.32 seconds |
| Started | Feb 04 12:53:29 PM PST 24 |
| Finished | Feb 04 12:53:43 PM PST 24 |
| Peak memory | 198772 kb |
| Host | smart-3393f998-8946-4a3c-b9a3-ab084a7f2fee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847078759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1847078759 |
| Directory | /workspace/5.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sw_rst.2179812834 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 129775882 ps |
| CPU time | 1.55 seconds |
| Started | Feb 04 12:53:57 PM PST 24 |
| Finished | Feb 04 12:54:01 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-d5634e73-60f1-4250-88ec-d92547ed7ebf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179812834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2179812834 |
| Directory | /workspace/5.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.775153926 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 143866593 ps |
| CPU time | 0.96 seconds |
| Started | Feb 04 12:51:57 PM PST 24 |
| Finished | Feb 04 12:52:01 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-88932363-51d9-4db6-9ccd-87639be9ccbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775153926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.775153926 |
| Directory | /workspace/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/6.rstmgr_alert_test.916144665 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 66106128 ps |
| CPU time | 0.7 seconds |
| Started | Feb 04 12:52:09 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 199784 kb |
| Host | smart-5a1deccd-cdf0-4daa-8f04-7794dde956fc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916144665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.916144665 |
| Directory | /workspace/6.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.192930346 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2333053848 ps |
| CPU time | 7.67 seconds |
| Started | Feb 04 12:52:04 PM PST 24 |
| Finished | Feb 04 12:52:13 PM PST 24 |
| Peak memory | 218004 kb |
| Host | smart-ee1fbcad-0182-4c47-8bd6-712879ae285b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192930346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.192930346 |
| Directory | /workspace/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1913771429 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 243867972 ps |
| CPU time | 1.22 seconds |
| Started | Feb 04 12:52:03 PM PST 24 |
| Finished | Feb 04 12:52:07 PM PST 24 |
| Peak memory | 217228 kb |
| Host | smart-92ba0eb4-dbbf-4e0f-b2e1-56121754c1c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913771429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1913771429 |
| Directory | /workspace/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/6.rstmgr_por_stretcher.338235964 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 241864259 ps |
| CPU time | 0.89 seconds |
| Started | Feb 04 12:51:52 PM PST 24 |
| Finished | Feb 04 12:51:55 PM PST 24 |
| Peak memory | 199796 kb |
| Host | smart-184f997c-1c56-41ed-84c5-954afd786ef9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338235964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.338235964 |
| Directory | /workspace/6.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/6.rstmgr_reset.422241756 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2211932795 ps |
| CPU time | 7.98 seconds |
| Started | Feb 04 12:51:51 PM PST 24 |
| Finished | Feb 04 12:52:01 PM PST 24 |
| Peak memory | 200292 kb |
| Host | smart-1bc6d53e-75d1-4d47-9670-4aff5894477f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422241756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.422241756 |
| Directory | /workspace/6.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1339214454 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 154281053 ps |
| CPU time | 1.08 seconds |
| Started | Feb 04 12:52:06 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 200028 kb |
| Host | smart-8d79229b-0db9-481e-add1-80a285c84eac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1339214454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1339214454 |
| Directory | /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/6.rstmgr_smoke.4200805947 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 187792239 ps |
| CPU time | 1.34 seconds |
| Started | Feb 04 12:51:59 PM PST 24 |
| Finished | Feb 04 12:52:04 PM PST 24 |
| Peak memory | 200236 kb |
| Host | smart-9b6ca8ca-33d9-4747-a683-ebf5047a8d55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200805947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4200805947 |
| Directory | /workspace/6.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/6.rstmgr_stress_all.408921932 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2094838001 ps |
| CPU time | 10.31 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:27 PM PST 24 |
| Peak memory | 200292 kb |
| Host | smart-b145097e-72bf-42b3-900c-f4736ccfc8f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408921932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.408921932 |
| Directory | /workspace/6.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sw_rst.1743137126 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 484501092 ps |
| CPU time | 2.77 seconds |
| Started | Feb 04 12:52:16 PM PST 24 |
| Finished | Feb 04 12:52:21 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-36f562e8-7fe3-4dd3-9f54-03c7a9d3b3e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1743137126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1743137126 |
| Directory | /workspace/6.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.768193785 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 151319938 ps |
| CPU time | 1.25 seconds |
| Started | Feb 04 12:52:07 PM PST 24 |
| Finished | Feb 04 12:52:15 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-b2fac775-6082-47ce-a346-75320580daaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768193785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.768193785 |
| Directory | /workspace/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/7.rstmgr_alert_test.1001453712 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 73996650 ps |
| CPU time | 0.85 seconds |
| Started | Feb 04 12:52:16 PM PST 24 |
| Finished | Feb 04 12:52:19 PM PST 24 |
| Peak memory | 199904 kb |
| Host | smart-34dfb88d-6e5c-4ac4-8984-bda41c547708 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001453712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1001453712 |
| Directory | /workspace/7.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.155626436 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2349502944 ps |
| CPU time | 7.96 seconds |
| Started | Feb 04 12:52:12 PM PST 24 |
| Finished | Feb 04 12:52:22 PM PST 24 |
| Peak memory | 217760 kb |
| Host | smart-33a7d419-4061-44dc-bcc5-bdb121023e07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155626436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.155626436 |
| Directory | /workspace/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4154349268 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 244541781 ps |
| CPU time | 1.1 seconds |
| Started | Feb 04 12:52:10 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 217252 kb |
| Host | smart-57b8dc19-a3b4-4056-90eb-15c497a23792 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154349268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4154349268 |
| Directory | /workspace/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/7.rstmgr_por_stretcher.580514020 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 250946212 ps |
| CPU time | 1.05 seconds |
| Started | Feb 04 12:52:10 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-5c38d6f6-ec45-437b-a71c-03a862b818e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580514020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.580514020 |
| Directory | /workspace/7.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/7.rstmgr_reset.2559861300 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 871326414 ps |
| CPU time | 4.32 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:21 PM PST 24 |
| Peak memory | 200136 kb |
| Host | smart-f932f21b-5bb3-44f4-a544-2f408da70d6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559861300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2559861300 |
| Directory | /workspace/7.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2574104556 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 166036728 ps |
| CPU time | 1.18 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:19 PM PST 24 |
| Peak memory | 200020 kb |
| Host | smart-710d2c9a-874d-465c-b910-ea9d1da8d712 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574104556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2574104556 |
| Directory | /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/7.rstmgr_smoke.3072813403 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 246772988 ps |
| CPU time | 1.43 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 200132 kb |
| Host | smart-ca38a84e-f6b3-4063-b234-0a9e2da9caed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072813403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3072813403 |
| Directory | /workspace/7.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/7.rstmgr_stress_all.4010502407 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1212792035 ps |
| CPU time | 4.62 seconds |
| Started | Feb 04 12:52:16 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 200136 kb |
| Host | smart-59605939-3b68-4489-ac84-758a2f5ecc2f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010502407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.4010502407 |
| Directory | /workspace/7.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sw_rst.1102811046 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 135198774 ps |
| CPU time | 1.71 seconds |
| Started | Feb 04 12:52:06 PM PST 24 |
| Finished | Feb 04 12:52:15 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-2073a43d-68d1-4c2a-82a2-76862b52036c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102811046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1102811046 |
| Directory | /workspace/7.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2003522676 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 203787475 ps |
| CPU time | 1.23 seconds |
| Started | Feb 04 12:52:05 PM PST 24 |
| Finished | Feb 04 12:52:13 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-dd4c3413-4605-4edc-92cc-cf4dde8aa73e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003522676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2003522676 |
| Directory | /workspace/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/8.rstmgr_alert_test.784073765 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 84484683 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:52:10 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-62b5af3d-f6bd-45da-a79a-7eb4d72ebf3c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784073765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.784073765 |
| Directory | /workspace/8.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2290180484 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1220078300 ps |
| CPU time | 5.53 seconds |
| Started | Feb 04 12:52:09 PM PST 24 |
| Finished | Feb 04 12:52:19 PM PST 24 |
| Peak memory | 221796 kb |
| Host | smart-6032fc84-66b9-4437-9ed5-f2370edeafb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290180484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2290180484 |
| Directory | /workspace/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3687620099 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 243910913 ps |
| CPU time | 1.12 seconds |
| Started | Feb 04 12:52:05 PM PST 24 |
| Finished | Feb 04 12:52:11 PM PST 24 |
| Peak memory | 217368 kb |
| Host | smart-239aad69-0c85-4022-94ad-9944d72c0413 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687620099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3687620099 |
| Directory | /workspace/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/8.rstmgr_por_stretcher.3732681456 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 114745601 ps |
| CPU time | 0.79 seconds |
| Started | Feb 04 12:52:02 PM PST 24 |
| Finished | Feb 04 12:52:06 PM PST 24 |
| Peak memory | 199888 kb |
| Host | smart-aa2d9ce9-6331-4703-8012-eb63a22b6afd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732681456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3732681456 |
| Directory | /workspace/8.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/8.rstmgr_reset.2462685191 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1330786181 ps |
| CPU time | 5.56 seconds |
| Started | Feb 04 12:52:01 PM PST 24 |
| Finished | Feb 04 12:52:11 PM PST 24 |
| Peak memory | 200240 kb |
| Host | smart-1b48b396-2272-4597-bc85-f230a4c59f86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2462685191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2462685191 |
| Directory | /workspace/8.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3342992517 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 151075932 ps |
| CPU time | 1.13 seconds |
| Started | Feb 04 12:52:10 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 200036 kb |
| Host | smart-adc1c54f-8bcf-4a1b-a6ae-c96abd04783b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342992517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3342992517 |
| Directory | /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/8.rstmgr_smoke.1893678164 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 188272650 ps |
| CPU time | 1.45 seconds |
| Started | Feb 04 12:51:58 PM PST 24 |
| Finished | Feb 04 12:52:02 PM PST 24 |
| Peak memory | 200220 kb |
| Host | smart-82db721e-10d6-4faf-b9a2-e1a55d86e9b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1893678164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1893678164 |
| Directory | /workspace/8.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/8.rstmgr_stress_all.3647267400 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4601943856 ps |
| CPU time | 21.62 seconds |
| Started | Feb 04 12:52:05 PM PST 24 |
| Finished | Feb 04 12:52:34 PM PST 24 |
| Peak memory | 200340 kb |
| Host | smart-37401fc3-ebe5-4045-9ad3-a2587c49cc07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647267400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3647267400 |
| Directory | /workspace/8.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sw_rst.4172353932 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 463238580 ps |
| CPU time | 2.52 seconds |
| Started | Feb 04 12:52:11 PM PST 24 |
| Finished | Feb 04 12:52:16 PM PST 24 |
| Peak memory | 200040 kb |
| Host | smart-49d4e6f0-2f62-4fa9-a4f3-70d42eea45de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172353932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.4172353932 |
| Directory | /workspace/8.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.42437496 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 77864581 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:52:05 PM PST 24 |
| Finished | Feb 04 12:52:13 PM PST 24 |
| Peak memory | 200004 kb |
| Host | smart-31554252-c693-421a-8e82-4b5f0246ac09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42437496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.42437496 |
| Directory | /workspace/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/9.rstmgr_alert_test.2012189924 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 66040046 ps |
| CPU time | 0.74 seconds |
| Started | Feb 04 12:52:10 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 199856 kb |
| Host | smart-3803eca0-34f5-4e0e-911c-02f9ac550ba9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012189924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2012189924 |
| Directory | /workspace/9.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.887020262 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1221619772 ps |
| CPU time | 5.56 seconds |
| Started | Feb 04 12:52:07 PM PST 24 |
| Finished | Feb 04 12:52:19 PM PST 24 |
| Peak memory | 221408 kb |
| Host | smart-bd92cf15-1607-4d18-911d-720f3cd10ce1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=887020262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.887020262 |
| Directory | /workspace/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2241962883 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 244945411 ps |
| CPU time | 1.1 seconds |
| Started | Feb 04 12:52:10 PM PST 24 |
| Finished | Feb 04 12:52:14 PM PST 24 |
| Peak memory | 217352 kb |
| Host | smart-5bb195af-ad8d-41f6-b682-45842977d5c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241962883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2241962883 |
| Directory | /workspace/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/9.rstmgr_por_stretcher.1357591492 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 103740448 ps |
| CPU time | 0.77 seconds |
| Started | Feb 04 12:52:15 PM PST 24 |
| Finished | Feb 04 12:52:17 PM PST 24 |
| Peak memory | 199876 kb |
| Host | smart-6de47356-0012-411c-9f95-7634a2a0f90e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357591492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1357591492 |
| Directory | /workspace/9.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/9.rstmgr_reset.2542345812 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 747535442 ps |
| CPU time | 3.78 seconds |
| Started | Feb 04 12:52:16 PM PST 24 |
| Finished | Feb 04 12:52:22 PM PST 24 |
| Peak memory | 200256 kb |
| Host | smart-d086d56a-993d-4e69-84a7-81930aa1b700 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542345812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2542345812 |
| Directory | /workspace/9.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.194541058 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 178659790 ps |
| CPU time | 1.24 seconds |
| Started | Feb 04 12:52:12 PM PST 24 |
| Finished | Feb 04 12:52:15 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-f41d687e-edfe-4f69-affa-f25eb760d562 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194541058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.194541058 |
| Directory | /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/9.rstmgr_stress_all.628818872 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 8400228861 ps |
| CPU time | 32.36 seconds |
| Started | Feb 04 12:52:06 PM PST 24 |
| Finished | Feb 04 12:52:45 PM PST 24 |
| Peak memory | 200248 kb |
| Host | smart-5cb63369-e2ad-4060-aaae-d4f855b79eb2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628818872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.628818872 |
| Directory | /workspace/9.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sw_rst.891895494 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 144035456 ps |
| CPU time | 1.7 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 200004 kb |
| Host | smart-63694af1-f99f-4c13-9f83-aeee9a6c2081 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891895494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.891895494 |
| Directory | /workspace/9.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3691049870 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 91571015 ps |
| CPU time | 0.9 seconds |
| Started | Feb 04 12:52:20 PM PST 24 |
| Finished | Feb 04 12:52:24 PM PST 24 |
| Peak memory | 199932 kb |
| Host | smart-be92322d-f974-4121-acc9-9500b9d3cad6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691049870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3691049870 |
| Directory | /workspace/9.rstmgr_sw_rst_reset_race/latest |
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