Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8181

1

T2

2

T6

18

T12

82

auto[1]

11054

1

T2

1

T6

83

T8

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6017	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6432	1			T1	1		T2	1		T3	1
reset_info_cp[2]	2925	1			T6	14		T8	1		T11	1
reset_info_cp[4]	3968	1			T6	19		T8	1		T11	1
reset_info_cp[8]	97	1			T6	1		T17	1		T100	1
reset_info_cp[16]	103	1			T12	1		T17	5		T47	1
reset_info_cp[32]	107	1			T16	1		T17	1		T110	1
reset_info_cp[64]	106	1			T6	1		T12	1		T17	2
reset_info_cp[128]	100	1			T12	1		T17	2		T47	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3060	1			T6	18		T12	26		T17	83
reset_info_cp[1]	auto[1]	2752	1			T6	8		T8	1		T11	1
reset_info_cp[2]	auto[0]	957	1			T12	11		T17	47		T18	2
reset_info_cp[2]	auto[1]	1968	1			T6	14		T8	1		T11	1
reset_info_cp[4]	auto[0]	1405	1			T12	21		T17	48		T18	9
reset_info_cp[4]	auto[1]	2563	1			T6	19		T8	1		T11	1
reset_info_cp[8]	auto[0]	44	1			T57	1		T112	2		T39	2
reset_info_cp[8]	auto[1]	53	1			T6	1		T17	1		T100	1
reset_info_cp[16]	auto[0]	39	1			T17	4		T135	1		T115	1
reset_info_cp[16]	auto[1]	64	1			T12	1		T17	1		T47	1
reset_info_cp[32]	auto[0]	44	1			T17	1		T111	1		T135	1
reset_info_cp[32]	auto[1]	63	1			T16	1		T110	1		T47	1
reset_info_cp[64]	auto[0]	41	1			T17	1		T111	1		T57	1
reset_info_cp[64]	auto[1]	65	1			T6	1		T12	1		T17	1
reset_info_cp[128]	auto[0]	33	1			T17	1		T56	1		T112	2
reset_info_cp[128]	auto[1]	67	1			T12	1		T17	1		T47	2