| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.43 | 99.40 | 99.24 | 99.88 | 99.83 | 99.46 | 98.77 |
| T502 | /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3291717990 | Feb 07 12:42:46 PM PST 24 | Feb 07 12:42:53 PM PST 24 | 244033116 ps | ||
| T503 | /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1567374001 | Feb 07 12:41:20 PM PST 24 | Feb 07 12:41:21 PM PST 24 | 117490399 ps | ||
| T504 | /workspace/coverage/default/16.rstmgr_alert_test.1474444150 | Feb 07 12:41:57 PM PST 24 | Feb 07 12:41:59 PM PST 24 | 63828447 ps | ||
| T505 | /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2674939792 | Feb 07 12:41:57 PM PST 24 | Feb 07 12:42:07 PM PST 24 | 1901044080 ps | ||
| T506 | /workspace/coverage/default/43.rstmgr_sw_rst.637518040 | Feb 07 12:42:56 PM PST 24 | Feb 07 12:43:07 PM PST 24 | 133117792 ps | ||
| T507 | /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.18879951 | Feb 07 12:42:51 PM PST 24 | Feb 07 12:43:01 PM PST 24 | 244206086 ps | ||
| T508 | /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2552186217 | Feb 07 12:42:30 PM PST 24 | Feb 07 12:42:32 PM PST 24 | 121455163 ps | ||
| T509 | /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2021991069 | Feb 07 12:42:37 PM PST 24 | Feb 07 12:42:44 PM PST 24 | 1225906349 ps | ||
| T510 | /workspace/coverage/default/22.rstmgr_por_stretcher.3309198402 | Feb 07 12:42:22 PM PST 24 | Feb 07 12:42:24 PM PST 24 | 168237976 ps | ||
| T511 | /workspace/coverage/default/39.rstmgr_reset.1726992572 | Feb 07 12:42:31 PM PST 24 | Feb 07 12:42:38 PM PST 24 | 1332491556 ps | ||
| T512 | /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2296471929 | Feb 07 12:42:16 PM PST 24 | Feb 07 12:42:26 PM PST 24 | 2369805466 ps | ||
| T513 | /workspace/coverage/default/32.rstmgr_smoke.3371058403 | Feb 07 12:42:24 PM PST 24 | Feb 07 12:42:27 PM PST 24 | 127489121 ps | ||
| T514 | /workspace/coverage/default/9.rstmgr_reset.2324018583 | Feb 07 12:41:39 PM PST 24 | Feb 07 12:41:43 PM PST 24 | 752501290 ps | ||
| T515 | /workspace/coverage/default/29.rstmgr_por_stretcher.1893377930 | Feb 07 12:42:28 PM PST 24 | Feb 07 12:42:30 PM PST 24 | 207408004 ps | ||
| T516 | /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.556386468 | Feb 07 12:41:10 PM PST 24 | Feb 07 12:41:19 PM PST 24 | 1889301747 ps | ||
| T517 | /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3924425240 | Feb 07 12:42:52 PM PST 24 | Feb 07 12:43:03 PM PST 24 | 100737620 ps | ||
| T518 | /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2933827335 | Feb 07 12:42:19 PM PST 24 | Feb 07 12:42:21 PM PST 24 | 246125853 ps | ||
| T519 | /workspace/coverage/default/43.rstmgr_stress_all.3043198023 | Feb 07 12:42:50 PM PST 24 | Feb 07 12:43:21 PM PST 24 | 6915835007 ps | ||
| T520 | /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1395231203 | Feb 07 12:42:18 PM PST 24 | Feb 07 12:42:26 PM PST 24 | 1901668129 ps | ||
| T521 | /workspace/coverage/default/1.rstmgr_por_stretcher.2873532136 | Feb 07 12:41:12 PM PST 24 | Feb 07 12:41:14 PM PST 24 | 169231207 ps | ||
| T522 | /workspace/coverage/default/10.rstmgr_stress_all.2477101984 | Feb 07 12:41:38 PM PST 24 | Feb 07 12:42:39 PM PST 24 | 18134015607 ps | ||
| T523 | /workspace/coverage/default/21.rstmgr_reset.2694731931 | Feb 07 12:42:15 PM PST 24 | Feb 07 12:42:19 PM PST 24 | 791368778 ps | ||
| T524 | /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3473816486 | Feb 07 12:41:12 PM PST 24 | Feb 07 12:41:19 PM PST 24 | 1232299470 ps | ||
| T525 | /workspace/coverage/default/21.rstmgr_alert_test.2342468475 | Feb 07 12:42:16 PM PST 24 | Feb 07 12:42:17 PM PST 24 | 80907215 ps | ||
| T526 | /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1006457570 | Feb 07 12:42:14 PM PST 24 | Feb 07 12:42:16 PM PST 24 | 243208302 ps | ||
| T527 | /workspace/coverage/default/38.rstmgr_reset.2577250467 | Feb 07 12:42:36 PM PST 24 | Feb 07 12:42:43 PM PST 24 | 989083137 ps | ||
| T528 | /workspace/coverage/default/41.rstmgr_alert_test.3460315959 | Feb 07 12:42:46 PM PST 24 | Feb 07 12:42:53 PM PST 24 | 61860509 ps | ||
| T529 | /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4061123914 | Feb 07 12:42:20 PM PST 24 | Feb 07 12:42:27 PM PST 24 | 1237157761 ps | ||
| T530 | /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.696568354 | Feb 07 12:41:51 PM PST 24 | Feb 07 12:41:53 PM PST 24 | 105991824 ps | ||
| T531 | /workspace/coverage/default/47.rstmgr_stress_all.4060242127 | Feb 07 12:42:51 PM PST 24 | Feb 07 12:43:09 PM PST 24 | 3561027324 ps | ||
| T532 | /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3934650020 | Feb 07 12:42:28 PM PST 24 | Feb 07 12:42:30 PM PST 24 | 114939840 ps | ||
| T533 | /workspace/coverage/default/32.rstmgr_por_stretcher.3896734311 | Feb 07 12:42:21 PM PST 24 | Feb 07 12:42:23 PM PST 24 | 132610376 ps | ||
| T534 | /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1552148493 | Feb 07 12:41:57 PM PST 24 | Feb 07 12:42:05 PM PST 24 | 1898542018 ps | ||
| T535 | /workspace/coverage/default/30.rstmgr_smoke.3964604123 | Feb 07 12:42:27 PM PST 24 | Feb 07 12:42:29 PM PST 24 | 122071417 ps | ||
| T536 | /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.735365879 | Feb 07 12:42:52 PM PST 24 | Feb 07 12:43:03 PM PST 24 | 96615223 ps | ||
| T537 | /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2207084843 | Feb 07 12:42:48 PM PST 24 | Feb 07 12:42:54 PM PST 24 | 91822976 ps | ||
| T538 | /workspace/coverage/default/28.rstmgr_smoke.869862836 | Feb 07 12:42:14 PM PST 24 | Feb 07 12:42:16 PM PST 24 | 228406161 ps | ||
| T539 | /workspace/coverage/default/14.rstmgr_smoke.1091409612 | Feb 07 12:41:52 PM PST 24 | Feb 07 12:41:55 PM PST 24 | 120940582 ps | ||
| T540 | /workspace/coverage/default/7.rstmgr_sw_rst.3497665840 | Feb 07 12:41:30 PM PST 24 | Feb 07 12:41:33 PM PST 24 | 133656524 ps | ||
| T541 | /workspace/coverage/default/28.rstmgr_sw_rst.178287493 | Feb 07 12:42:14 PM PST 24 | Feb 07 12:42:16 PM PST 24 | 125321250 ps | ||
| T542 | /workspace/coverage/default/17.rstmgr_stress_all.3095054762 | Feb 07 12:41:50 PM PST 24 | Feb 07 12:42:09 PM PST 24 | 3895554923 ps | ||
| T543 | /workspace/coverage/default/36.rstmgr_reset.3564624278 | Feb 07 12:42:24 PM PST 24 | Feb 07 12:42:29 PM PST 24 | 750235428 ps | ||
| T544 | /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3882223808 | Feb 07 12:41:12 PM PST 24 | Feb 07 12:41:15 PM PST 24 | 199327954 ps | ||
| T545 | /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2244916160 | Feb 07 12:42:08 PM PST 24 | Feb 07 12:42:12 PM PST 24 | 281695522 ps | ||
| T546 | /workspace/coverage/default/4.rstmgr_stress_all.1692375417 | Feb 07 12:41:17 PM PST 24 | Feb 07 12:41:26 PM PST 24 | 1841043374 ps | ||
| T547 | /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.4168861249 | Feb 07 12:41:37 PM PST 24 | Feb 07 12:41:39 PM PST 24 | 174942520 ps | ||
| T548 | /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3340790315 | Feb 07 12:42:20 PM PST 24 | Feb 07 12:42:22 PM PST 24 | 245155600 ps | ||
| T549 | /workspace/coverage/default/25.rstmgr_smoke.2276094680 | Feb 07 12:42:12 PM PST 24 | Feb 07 12:42:15 PM PST 24 | 232939350 ps | ||
| T550 | /workspace/coverage/default/3.rstmgr_por_stretcher.2497809958 | Feb 07 12:41:15 PM PST 24 | Feb 07 12:41:17 PM PST 24 | 175958610 ps | ||
| T551 | /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2157319488 | Feb 07 12:42:22 PM PST 24 | Feb 07 12:42:24 PM PST 24 | 105523249 ps | ||
| T552 | /workspace/coverage/default/34.rstmgr_smoke.1730469852 | Feb 07 12:42:19 PM PST 24 | Feb 07 12:42:21 PM PST 24 | 195249386 ps | ||
| T553 | /workspace/coverage/default/27.rstmgr_por_stretcher.1271389682 | Feb 07 12:42:10 PM PST 24 | Feb 07 12:42:13 PM PST 24 | 158279117 ps | ||
| T554 | /workspace/coverage/default/15.rstmgr_alert_test.378515567 | Feb 07 12:42:00 PM PST 24 | Feb 07 12:42:03 PM PST 24 | 96814030 ps | ||
| T555 | /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3314147437 | Feb 07 12:41:31 PM PST 24 | Feb 07 12:41:32 PM PST 24 | 117197720 ps | ||
| T556 | /workspace/coverage/default/30.rstmgr_reset.2002245828 | Feb 07 12:42:25 PM PST 24 | Feb 07 12:42:31 PM PST 24 | 1093924124 ps | ||
| T557 | /workspace/coverage/default/41.rstmgr_smoke.2001200020 | Feb 07 12:42:37 PM PST 24 | Feb 07 12:42:39 PM PST 24 | 249445233 ps | ||
| T558 | /workspace/coverage/default/26.rstmgr_reset.2872917667 | Feb 07 12:42:16 PM PST 24 | Feb 07 12:42:21 PM PST 24 | 1212325309 ps | ||
| T559 | /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3725610283 | Feb 07 12:41:18 PM PST 24 | Feb 07 12:41:20 PM PST 24 | 182574033 ps | ||
| T560 | /workspace/coverage/default/14.rstmgr_stress_all.4204604253 | Feb 07 12:41:54 PM PST 24 | Feb 07 12:42:04 PM PST 24 | 1920996068 ps | ||
| T561 | /workspace/coverage/default/21.rstmgr_sw_rst.3149240345 | Feb 07 12:42:14 PM PST 24 | Feb 07 12:42:17 PM PST 24 | 133165375 ps | ||
| T562 | /workspace/coverage/default/6.rstmgr_sw_rst.1694782786 | Feb 07 12:41:24 PM PST 24 | Feb 07 12:41:27 PM PST 24 | 277413494 ps | ||
| T563 | /workspace/coverage/default/12.rstmgr_sw_rst.1240504442 | Feb 07 12:41:40 PM PST 24 | Feb 07 12:41:43 PM PST 24 | 131867256 ps | ||
| T564 | /workspace/coverage/default/15.rstmgr_sw_rst.1861493853 | Feb 07 12:41:54 PM PST 24 | Feb 07 12:41:56 PM PST 24 | 117748855 ps | ||
| T565 | /workspace/coverage/default/19.rstmgr_stress_all.1942368197 | Feb 07 12:42:06 PM PST 24 | Feb 07 12:42:42 PM PST 24 | 7782680311 ps | ||
| T566 | /workspace/coverage/default/19.rstmgr_sw_rst.3760832412 | Feb 07 12:41:56 PM PST 24 | Feb 07 12:42:00 PM PST 24 | 398495221 ps | ||
| T567 | /workspace/coverage/default/37.rstmgr_reset.433032960 | Feb 07 12:42:27 PM PST 24 | Feb 07 12:42:32 PM PST 24 | 901918070 ps | ||
| T568 | /workspace/coverage/default/33.rstmgr_reset.1304430293 | Feb 07 12:42:26 PM PST 24 | Feb 07 12:42:32 PM PST 24 | 982710126 ps | ||
| T569 | /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2606268175 | Feb 07 12:42:14 PM PST 24 | Feb 07 12:42:15 PM PST 24 | 110912472 ps | ||
| T570 | /workspace/coverage/default/9.rstmgr_alert_test.2304990272 | Feb 07 12:41:36 PM PST 24 | Feb 07 12:41:37 PM PST 24 | 107443363 ps | ||
| T571 | /workspace/coverage/default/9.rstmgr_sw_rst.535246530 | Feb 07 12:41:25 PM PST 24 | Feb 07 12:41:28 PM PST 24 | 300192603 ps | ||
| T572 | /workspace/coverage/default/15.rstmgr_reset.3587173483 | Feb 07 12:41:52 PM PST 24 | Feb 07 12:41:59 PM PST 24 | 1606583251 ps | ||
| T573 | /workspace/coverage/default/18.rstmgr_alert_test.416536972 | Feb 07 12:41:57 PM PST 24 | Feb 07 12:41:59 PM PST 24 | 66905405 ps | ||
| T574 | /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2940003432 | Feb 07 12:42:27 PM PST 24 | Feb 07 12:42:29 PM PST 24 | 244457222 ps | ||
| T575 | /workspace/coverage/default/36.rstmgr_alert_test.1636414401 | Feb 07 12:42:23 PM PST 24 | Feb 07 12:42:25 PM PST 24 | 83773971 ps | ||
| T576 | /workspace/coverage/default/3.rstmgr_smoke.811948859 | Feb 07 12:41:16 PM PST 24 | Feb 07 12:41:19 PM PST 24 | 185617836 ps | ||
| T577 | /workspace/coverage/default/10.rstmgr_smoke.840535734 | Feb 07 12:41:29 PM PST 24 | Feb 07 12:41:31 PM PST 24 | 204325617 ps | ||
| T578 | /workspace/coverage/default/28.rstmgr_stress_all.4292486157 | Feb 07 12:42:25 PM PST 24 | Feb 07 12:42:31 PM PST 24 | 1282699278 ps | ||
| T579 | /workspace/coverage/default/34.rstmgr_stress_all.2467853202 | Feb 07 12:42:29 PM PST 24 | Feb 07 12:42:37 PM PST 24 | 1528505430 ps | ||
| T580 | /workspace/coverage/default/47.rstmgr_por_stretcher.1131685015 | Feb 07 12:42:49 PM PST 24 | Feb 07 12:42:54 PM PST 24 | 102487012 ps | ||
| T581 | /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1373974414 | Feb 07 12:43:07 PM PST 24 | Feb 07 12:43:12 PM PST 24 | 186208646 ps | ||
| T582 | /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2488022180 | Feb 07 12:42:31 PM PST 24 | Feb 07 12:42:37 PM PST 24 | 1219216242 ps | ||
| T583 | /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1491874972 | Feb 07 12:41:20 PM PST 24 | Feb 07 12:41:23 PM PST 24 | 244365070 ps | ||
| T584 | /workspace/coverage/default/24.rstmgr_sw_rst.2013650980 | Feb 07 12:42:21 PM PST 24 | Feb 07 12:42:24 PM PST 24 | 257778861 ps | ||
| T585 | /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3759530872 | Feb 07 12:42:31 PM PST 24 | Feb 07 12:42:34 PM PST 24 | 67606054 ps | ||
| T586 | /workspace/coverage/default/5.rstmgr_alert_test.3072084616 | Feb 07 12:41:27 PM PST 24 | Feb 07 12:41:29 PM PST 24 | 61819079 ps | ||
| T587 | /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.447877689 | Feb 07 12:42:31 PM PST 24 | Feb 07 12:42:33 PM PST 24 | 248533660 ps | ||
| T588 | /workspace/coverage/default/49.rstmgr_alert_test.1537437301 | Feb 07 12:43:07 PM PST 24 | Feb 07 12:43:12 PM PST 24 | 52328872 ps | ||
| T589 | /workspace/coverage/default/33.rstmgr_por_stretcher.3283489410 | Feb 07 12:42:22 PM PST 24 | Feb 07 12:42:23 PM PST 24 | 162367968 ps | ||
| T590 | /workspace/coverage/default/29.rstmgr_reset.1978885660 | Feb 07 12:42:31 PM PST 24 | Feb 07 12:42:37 PM PST 24 | 1530783346 ps | ||
| T591 | /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.472470058 | Feb 07 12:41:39 PM PST 24 | Feb 07 12:41:41 PM PST 24 | 166026545 ps | ||
| T592 | /workspace/coverage/default/22.rstmgr_smoke.3109902249 | Feb 07 12:42:15 PM PST 24 | Feb 07 12:42:18 PM PST 24 | 195361297 ps | ||
| T593 | /workspace/coverage/default/4.rstmgr_por_stretcher.2790841080 | Feb 07 12:41:27 PM PST 24 | Feb 07 12:41:29 PM PST 24 | 163900092 ps | ||
| T594 | /workspace/coverage/default/2.rstmgr_alert_test.878930293 | Feb 07 12:41:13 PM PST 24 | Feb 07 12:41:15 PM PST 24 | 68994904 ps | ||
| T595 | /workspace/coverage/default/28.rstmgr_por_stretcher.3908346137 | Feb 07 12:42:21 PM PST 24 | Feb 07 12:42:23 PM PST 24 | 157190423 ps | ||
| T596 | /workspace/coverage/default/4.rstmgr_smoke.2186153090 | Feb 07 12:41:17 PM PST 24 | Feb 07 12:41:19 PM PST 24 | 114443012 ps | ||
| T597 | /workspace/coverage/default/37.rstmgr_por_stretcher.2403492679 | Feb 07 12:42:26 PM PST 24 | Feb 07 12:42:29 PM PST 24 | 146493364 ps | ||
| T81 | /workspace/coverage/default/1.rstmgr_sec_cm.1592874917 | Feb 07 12:41:10 PM PST 24 | Feb 07 12:41:42 PM PST 24 | 16521706514 ps | ||
| T598 | /workspace/coverage/default/40.rstmgr_reset.852758007 | Feb 07 12:42:34 PM PST 24 | Feb 07 12:42:41 PM PST 24 | 1694702092 ps | ||
| T599 | /workspace/coverage/default/44.rstmgr_alert_test.3561041783 | Feb 07 12:42:52 PM PST 24 | Feb 07 12:43:03 PM PST 24 | 75909220 ps | ||
| T600 | /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1613046715 | Feb 07 12:43:05 PM PST 24 | Feb 07 12:43:11 PM PST 24 | 164365696 ps | ||
| T601 | /workspace/coverage/default/15.rstmgr_por_stretcher.3298613926 | Feb 07 12:41:50 PM PST 24 | Feb 07 12:41:52 PM PST 24 | 127321732 ps | ||
| T602 | /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3043769791 | Feb 07 12:41:56 PM PST 24 | Feb 07 12:41:58 PM PST 24 | 179441024 ps | ||
| T603 | /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2554924578 | Feb 07 12:42:15 PM PST 24 | Feb 07 12:42:17 PM PST 24 | 234789632 ps | ||
| T604 | /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3329893936 | Feb 07 12:42:52 PM PST 24 | Feb 07 12:43:09 PM PST 24 | 1892303779 ps | ||
| T605 | /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.288237313 | Feb 07 12:42:22 PM PST 24 | Feb 07 12:42:24 PM PST 24 | 151915099 ps | ||
| T606 | /workspace/coverage/default/40.rstmgr_por_stretcher.983323559 | Feb 07 12:42:34 PM PST 24 | Feb 07 12:42:35 PM PST 24 | 127280860 ps | ||
| T607 | /workspace/coverage/default/10.rstmgr_alert_test.3714276744 | Feb 07 12:41:38 PM PST 24 | Feb 07 12:41:39 PM PST 24 | 87040109 ps | ||
| T608 | /workspace/coverage/default/40.rstmgr_alert_test.733513496 | Feb 07 12:42:33 PM PST 24 | Feb 07 12:42:35 PM PST 24 | 63331779 ps | ||
| T609 | /workspace/coverage/default/41.rstmgr_por_stretcher.536951456 | Feb 07 12:42:46 PM PST 24 | Feb 07 12:42:53 PM PST 24 | 146655529 ps | ||
| T610 | /workspace/coverage/default/45.rstmgr_sw_rst.3577446453 | Feb 07 12:42:53 PM PST 24 | Feb 07 12:43:06 PM PST 24 | 372668076 ps | ||
| T611 | /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3089935065 | Feb 07 12:41:52 PM PST 24 | Feb 07 12:42:00 PM PST 24 | 1901578441 ps | ||
| T612 | /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3258885942 | Feb 07 12:41:40 PM PST 24 | Feb 07 12:41:49 PM PST 24 | 2175047264 ps | ||
| T613 | /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.640032432 | Feb 07 12:42:46 PM PST 24 | Feb 07 12:42:53 PM PST 24 | 243996896 ps | ||
| T614 | /workspace/coverage/default/36.rstmgr_smoke.3179905283 | Feb 07 12:42:19 PM PST 24 | Feb 07 12:42:21 PM PST 24 | 195285162 ps | ||
| T615 | /workspace/coverage/default/18.rstmgr_sw_rst.4102187753 | Feb 07 12:41:51 PM PST 24 | Feb 07 12:41:54 PM PST 24 | 137159436 ps | ||
| T616 | /workspace/coverage/default/6.rstmgr_alert_test.3942501345 | Feb 07 12:41:22 PM PST 24 | Feb 07 12:41:23 PM PST 24 | 71980667 ps | ||
| T617 | /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3653625861 | Feb 07 12:42:02 PM PST 24 | Feb 07 12:42:04 PM PST 24 | 112278517 ps | ||
| T618 | /workspace/coverage/default/16.rstmgr_stress_all.992013154 | Feb 07 12:41:52 PM PST 24 | Feb 07 12:41:55 PM PST 24 | 229744254 ps | ||
| T619 | /workspace/coverage/default/20.rstmgr_sw_rst.2475065528 | Feb 07 12:41:58 PM PST 24 | Feb 07 12:42:02 PM PST 24 | 379702788 ps | ||
| T620 | /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1224959801 | Feb 07 12:41:21 PM PST 24 | Feb 07 12:41:23 PM PST 24 | 244448047 ps |
| Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2547327458 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1897793432 ps |
| CPU time | 7.92 seconds |
| Started | Feb 07 12:42:11 PM PST 24 |
| Finished | Feb 07 12:42:20 PM PST 24 |
| Peak memory | 217380 kb |
| Host | smart-fca03e39-944f-444f-b850-55c5f79cddcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547327458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2547327458 |
| Directory | /workspace/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/15.rstmgr_stress_all.2241556317 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 13419968144 ps |
| CPU time | 51.3 seconds |
| Started | Feb 07 12:41:51 PM PST 24 |
| Finished | Feb 07 12:42:44 PM PST 24 |
| Peak memory | 200180 kb |
| Host | smart-00c1e181-3fd5-4d57-b895-d2b0328d1404 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241556317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2241556317 |
| Directory | /workspace/15.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sw_rst.2505301141 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 512206152 ps |
| CPU time | 2.6 seconds |
| Started | Feb 07 12:42:58 PM PST 24 |
| Finished | Feb 07 12:43:08 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-5c3545b9-eb2c-4b2a-824a-e686f8f0521b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505301141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2505301141 |
| Directory | /workspace/49.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1857237728 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 124149086 ps |
| CPU time | 1.42 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:14 PM PST 24 |
| Peak memory | 208932 kb |
| Host | smart-525544c6-4b0f-4a39-ab88-39b2886bfa79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857237728 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1857237728 |
| Directory | /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sec_cm.3794775617 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 8383214736 ps |
| CPU time | 12.99 seconds |
| Started | Feb 07 12:41:13 PM PST 24 |
| Finished | Feb 07 12:41:27 PM PST 24 |
| Peak memory | 216940 kb |
| Host | smart-418d4f55-a435-493e-b51c-d62b2d2cf182 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794775617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3794775617 |
| Directory | /workspace/2.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2204989844 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 944996267 ps |
| CPU time | 3.33 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200584 kb |
| Host | smart-32191709-3b38-4d28-9e3e-4bb060092fdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204989844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err .2204989844 |
| Directory | /workspace/6.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/35.rstmgr_alert_test.1117634440 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 73032483 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:42:25 PM PST 24 |
| Finished | Feb 07 12:42:27 PM PST 24 |
| Peak memory | 199864 kb |
| Host | smart-953b1b87-94d8-4f73-9b79-f7c99181c650 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117634440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1117634440 |
| Directory | /workspace/35.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/38.rstmgr_stress_all.3380032131 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 9530699687 ps |
| CPU time | 32.74 seconds |
| Started | Feb 07 12:42:30 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 200164 kb |
| Host | smart-240103c8-26d9-4d4b-bd7f-feeb9ab7a2f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380032131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3380032131 |
| Directory | /workspace/38.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3703268473 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 100693715 ps |
| CPU time | 0.98 seconds |
| Started | Feb 07 12:41:53 PM PST 24 |
| Finished | Feb 07 12:41:55 PM PST 24 |
| Peak memory | 199888 kb |
| Host | smart-367db26c-5b1e-4fbb-be8f-6b956cf19107 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703268473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3703268473 |
| Directory | /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3278903401 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2181223310 ps |
| CPU time | 7.45 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:31 PM PST 24 |
| Peak memory | 216832 kb |
| Host | smart-f3c8d2a5-3cd9-4271-b287-a1c524fde4e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278903401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3278903401 |
| Directory | /workspace/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2936636466 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 92107795 ps |
| CPU time | 1.3 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-aa20b5ea-9169-417e-a438-13109540d873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936636466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2936636466 |
| Directory | /workspace/9.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1443101668 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 785028931 ps |
| CPU time | 2.97 seconds |
| Started | Feb 07 01:07:59 PM PST 24 |
| Finished | Feb 07 01:08:02 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-32da48ff-0bc4-410a-aefc-075d7db4cd3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443101668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err .1443101668 |
| Directory | /workspace/1.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.928600947 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2349216224 ps |
| CPU time | 7.91 seconds |
| Started | Feb 07 12:41:41 PM PST 24 |
| Finished | Feb 07 12:41:50 PM PST 24 |
| Peak memory | 217048 kb |
| Host | smart-0c99205e-bba3-4939-81cc-8157805b393d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928600947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.928600947 |
| Directory | /workspace/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.627999096 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 87196866 ps |
| CPU time | 0.89 seconds |
| Started | Feb 07 01:07:49 PM PST 24 |
| Finished | Feb 07 01:07:51 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-ec4deb42-efb1-45d8-b361-aa0901593363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627999096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.627999096 |
| Directory | /workspace/1.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/default/12.rstmgr_por_stretcher.2173785901 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 210065413 ps |
| CPU time | 0.92 seconds |
| Started | Feb 07 12:41:39 PM PST 24 |
| Finished | Feb 07 12:41:41 PM PST 24 |
| Peak memory | 199748 kb |
| Host | smart-abeceb85-3564-47e0-9cc1-0b5c26baa139 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173785901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2173785901 |
| Directory | /workspace/12.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2757010461 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 244828040 ps |
| CPU time | 1.04 seconds |
| Started | Feb 07 12:41:38 PM PST 24 |
| Finished | Feb 07 12:41:39 PM PST 24 |
| Peak memory | 217180 kb |
| Host | smart-7c427541-2564-450a-b920-35896e4c9daf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2757010461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2757010461 |
| Directory | /workspace/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4260254952 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 788247481 ps |
| CPU time | 2.96 seconds |
| Started | Feb 07 01:08:15 PM PST 24 |
| Finished | Feb 07 01:08:19 PM PST 24 |
| Peak memory | 200672 kb |
| Host | smart-d1e7d5cf-e484-4aec-b7df-78fd31575935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260254952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er r.4260254952 |
| Directory | /workspace/10.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2707150862 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 886452250 ps |
| CPU time | 3.16 seconds |
| Started | Feb 07 01:08:07 PM PST 24 |
| Finished | Feb 07 01:08:11 PM PST 24 |
| Peak memory | 200672 kb |
| Host | smart-076bd6de-4612-4aaa-b038-16648850257a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707150862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er r.2707150862 |
| Directory | /workspace/12.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3051862357 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 123619490 ps |
| CPU time | 1.24 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200460 kb |
| Host | smart-542b61d4-0507-4328-a488-b661b11d6887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051862357 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3051862357 |
| Directory | /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3102418357 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 423872106 ps |
| CPU time | 1.81 seconds |
| Started | Feb 07 01:08:07 PM PST 24 |
| Finished | Feb 07 01:08:10 PM PST 24 |
| Peak memory | 200628 kb |
| Host | smart-f4e2a453-bc5e-4588-b601-5676ac578824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102418357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er r.3102418357 |
| Directory | /workspace/16.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sw_rst.363826759 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 135398120 ps |
| CPU time | 1.65 seconds |
| Started | Feb 07 12:41:55 PM PST 24 |
| Finished | Feb 07 12:41:58 PM PST 24 |
| Peak memory | 200032 kb |
| Host | smart-2cac0f59-c570-4ad3-a825-7e67813fe70e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363826759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.363826759 |
| Directory | /workspace/14.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.599390097 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 428402149 ps |
| CPU time | 2.67 seconds |
| Started | Feb 07 01:08:02 PM PST 24 |
| Finished | Feb 07 01:08:06 PM PST 24 |
| Peak memory | 200584 kb |
| Host | smart-50bb34a5-d2e2-48fc-8a63-280084b4a349 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599390097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.599390097 |
| Directory | /workspace/0.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3342956617 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 271904104 ps |
| CPU time | 3.21 seconds |
| Started | Feb 07 01:07:35 PM PST 24 |
| Finished | Feb 07 01:07:39 PM PST 24 |
| Peak memory | 200660 kb |
| Host | smart-2a0e8fad-900c-428b-8e78-c0f397b90378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342956617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3 342956617 |
| Directory | /workspace/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3486003649 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 139981099 ps |
| CPU time | 0.94 seconds |
| Started | Feb 07 01:07:59 PM PST 24 |
| Finished | Feb 07 01:08:01 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-91cf4486-5ce2-4cf4-91fc-d01f2120c604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486003649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3 486003649 |
| Directory | /workspace/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3671993070 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 104024324 ps |
| CPU time | 0.96 seconds |
| Started | Feb 07 01:08:00 PM PST 24 |
| Finished | Feb 07 01:08:02 PM PST 24 |
| Peak memory | 200524 kb |
| Host | smart-4d1e7e05-b5c9-4311-8e64-40f10d3121af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671993070 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3671993070 |
| Directory | /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.61178256 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 65823392 ps |
| CPU time | 0.72 seconds |
| Started | Feb 07 01:08:00 PM PST 24 |
| Finished | Feb 07 01:08:02 PM PST 24 |
| Peak memory | 200460 kb |
| Host | smart-8baa3918-3554-488e-9cc0-ef6884874c94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61178256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.61178256 |
| Directory | /workspace/0.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3033670839 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 73404152 ps |
| CPU time | 0.92 seconds |
| Started | Feb 07 01:08:00 PM PST 24 |
| Finished | Feb 07 01:08:02 PM PST 24 |
| Peak memory | 200460 kb |
| Host | smart-d615f2a6-5683-4f1e-a1c4-6f03f588e1b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033670839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa me_csr_outstanding.3033670839 |
| Directory | /workspace/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2774094465 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 432744547 ps |
| CPU time | 2.95 seconds |
| Started | Feb 07 01:07:48 PM PST 24 |
| Finished | Feb 07 01:07:51 PM PST 24 |
| Peak memory | 200600 kb |
| Host | smart-2d244c98-4873-48ca-9afe-b6dfd731e780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774094465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2774094465 |
| Directory | /workspace/0.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1837651805 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 890455141 ps |
| CPU time | 3.01 seconds |
| Started | Feb 07 01:07:59 PM PST 24 |
| Finished | Feb 07 01:08:03 PM PST 24 |
| Peak memory | 200644 kb |
| Host | smart-b3336042-c89f-4204-a530-8c80fdaf8097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837651805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err .1837651805 |
| Directory | /workspace/0.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2410923968 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 218412337 ps |
| CPU time | 1.51 seconds |
| Started | Feb 07 01:07:51 PM PST 24 |
| Finished | Feb 07 01:07:54 PM PST 24 |
| Peak memory | 200612 kb |
| Host | smart-d799eb97-d7c1-49af-9fe2-3e27763f2679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410923968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2 410923968 |
| Directory | /workspace/1.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3925004975 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 811540718 ps |
| CPU time | 4.45 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:04 PM PST 24 |
| Peak memory | 200560 kb |
| Host | smart-d4071924-a10d-4813-a502-552127e32fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925004975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3 925004975 |
| Directory | /workspace/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3670406113 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 101290298 ps |
| CPU time | 0.89 seconds |
| Started | Feb 07 01:08:07 PM PST 24 |
| Finished | Feb 07 01:08:09 PM PST 24 |
| Peak memory | 200440 kb |
| Host | smart-cfb10a5d-2b29-4feb-b5d0-071288f068fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670406113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3 670406113 |
| Directory | /workspace/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2280016821 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 119775966 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 01:08:08 PM PST 24 |
| Finished | Feb 07 01:08:10 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-3905f391-ce8a-4a77-ac9c-2e111c2d2e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280016821 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2280016821 |
| Directory | /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3925843969 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 161662429 ps |
| CPU time | 1.15 seconds |
| Started | Feb 07 01:08:02 PM PST 24 |
| Finished | Feb 07 01:08:04 PM PST 24 |
| Peak memory | 200348 kb |
| Host | smart-07ac571a-77f7-43f9-aa5d-02da72097136 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925843969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa me_csr_outstanding.3925843969 |
| Directory | /workspace/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2702802937 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 603701772 ps |
| CPU time | 4.03 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:02 PM PST 24 |
| Peak memory | 216156 kb |
| Host | smart-c69b76a6-c752-45fc-9dc4-2b7154900fb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702802937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2702802937 |
| Directory | /workspace/1.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1550066569 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 123788712 ps |
| CPU time | 1 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200524 kb |
| Host | smart-523e4352-e681-4e05-a6fb-31e19e9d5d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550066569 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1550066569 |
| Directory | /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3004764920 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 65659053 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:11 PM PST 24 |
| Peak memory | 200440 kb |
| Host | smart-50a916cc-a18e-421c-9069-b7e34d174ddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004764920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3004764920 |
| Directory | /workspace/10.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.458210315 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 132498509 ps |
| CPU time | 1.02 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200440 kb |
| Host | smart-1e2e0a87-f1b5-4568-ae07-47baee9ad528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458210315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa me_csr_outstanding.458210315 |
| Directory | /workspace/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3522050405 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 100117798 ps |
| CPU time | 1.31 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200608 kb |
| Host | smart-5c93af9e-e585-4b4b-9af3-ef158c71bfab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522050405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3522050405 |
| Directory | /workspace/10.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.106887618 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 172786207 ps |
| CPU time | 1.78 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 209968 kb |
| Host | smart-cd2cd1bf-a6ed-4337-aa30-a2f570fcaf47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106887618 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.106887618 |
| Directory | /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2768994735 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 70748052 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-e9492f94-55aa-46c2-8754-fbd0fc9a39b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768994735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2768994735 |
| Directory | /workspace/11.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4011200146 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 160495743 ps |
| CPU time | 1.18 seconds |
| Started | Feb 07 01:08:05 PM PST 24 |
| Finished | Feb 07 01:08:07 PM PST 24 |
| Peak memory | 200420 kb |
| Host | smart-75557d8e-8b06-4285-8980-d66463d43f78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011200146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s ame_csr_outstanding.4011200146 |
| Directory | /workspace/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2130995471 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 184537098 ps |
| CPU time | 1.57 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:11 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-bc1ee2df-78d1-465f-80e4-49e84e20e239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130995471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2130995471 |
| Directory | /workspace/11.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1114492579 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 780240656 ps |
| CPU time | 2.8 seconds |
| Started | Feb 07 01:08:08 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200568 kb |
| Host | smart-a1474cd6-8ba5-4860-90cb-dffe50ae4bf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114492579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er r.1114492579 |
| Directory | /workspace/11.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.258107741 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 144690563 ps |
| CPU time | 1.38 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200708 kb |
| Host | smart-62912d82-42fb-4099-8fc8-24b71f8883bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258107741 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.258107741 |
| Directory | /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2760418640 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 62607492 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:11 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-ff9a4476-68fc-4d09-9be7-edb078052c3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760418640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2760418640 |
| Directory | /workspace/12.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1569467413 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 83534409 ps |
| CPU time | 0.96 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-6b1f740b-c29f-4744-82a1-3683b3d357d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569467413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s ame_csr_outstanding.1569467413 |
| Directory | /workspace/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1574988887 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 273081546 ps |
| CPU time | 1.85 seconds |
| Started | Feb 07 01:08:06 PM PST 24 |
| Finished | Feb 07 01:08:09 PM PST 24 |
| Peak memory | 200604 kb |
| Host | smart-d13efbf8-346a-43e1-b189-bfe641a55353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574988887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1574988887 |
| Directory | /workspace/12.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1375710892 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 75828398 ps |
| CPU time | 0.73 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-8d3a0c8b-fadd-443d-8ad7-2f7fcc447686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375710892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1375710892 |
| Directory | /workspace/13.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2736527037 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 189289145 ps |
| CPU time | 1.5 seconds |
| Started | Feb 07 01:08:01 PM PST 24 |
| Finished | Feb 07 01:08:05 PM PST 24 |
| Peak memory | 200604 kb |
| Host | smart-0a996ee8-351a-44d5-bdc2-08bbbb72a00c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736527037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s ame_csr_outstanding.2736527037 |
| Directory | /workspace/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2066051134 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 121289403 ps |
| CPU time | 1.72 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200652 kb |
| Host | smart-499fcda4-8fa9-4a55-be14-b3afae388e88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066051134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2066051134 |
| Directory | /workspace/13.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.542758251 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 449073494 ps |
| CPU time | 1.8 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:14 PM PST 24 |
| Peak memory | 200708 kb |
| Host | smart-183b2b15-5cb2-4c88-a35a-894b794136bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542758251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err .542758251 |
| Directory | /workspace/13.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2149909425 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 168818981 ps |
| CPU time | 1.22 seconds |
| Started | Feb 07 01:08:08 PM PST 24 |
| Finished | Feb 07 01:08:11 PM PST 24 |
| Peak memory | 200480 kb |
| Host | smart-335e19c8-9990-4309-8874-af56a96bb874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149909425 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2149909425 |
| Directory | /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3987522649 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 85162592 ps |
| CPU time | 0.92 seconds |
| Started | Feb 07 01:08:05 PM PST 24 |
| Finished | Feb 07 01:08:07 PM PST 24 |
| Peak memory | 200432 kb |
| Host | smart-cf64cce3-3a08-478c-8706-b6875a359751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987522649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3987522649 |
| Directory | /workspace/14.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3352510994 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 223494547 ps |
| CPU time | 1.51 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200564 kb |
| Host | smart-42bad886-fe01-418c-a73d-611fe923bddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352510994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s ame_csr_outstanding.3352510994 |
| Directory | /workspace/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1257467053 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 214456827 ps |
| CPU time | 1.69 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200648 kb |
| Host | smart-9a40bd41-fa7d-4390-80d7-c2413c6a44b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257467053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1257467053 |
| Directory | /workspace/14.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3102507404 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 884695797 ps |
| CPU time | 3.35 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:14 PM PST 24 |
| Peak memory | 200588 kb |
| Host | smart-70fffe6d-eb76-4809-abc9-6b59743f27af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102507404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er r.3102507404 |
| Directory | /workspace/14.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.249894461 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 123821225 ps |
| CPU time | 1.17 seconds |
| Started | Feb 07 01:08:15 PM PST 24 |
| Finished | Feb 07 01:08:17 PM PST 24 |
| Peak memory | 200508 kb |
| Host | smart-014fa0de-a316-474f-ab89-6ba4306e7415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249894461 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.249894461 |
| Directory | /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.837725579 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 88914341 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 01:08:14 PM PST 24 |
| Finished | Feb 07 01:08:15 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-9f8d659c-c20f-47a5-9ebd-02f470fd145a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837725579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.837725579 |
| Directory | /workspace/15.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3779970388 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 134694650 ps |
| CPU time | 1.26 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:14 PM PST 24 |
| Peak memory | 200672 kb |
| Host | smart-3fd7af40-17be-4849-b040-c13d9c5ba8b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779970388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s ame_csr_outstanding.3779970388 |
| Directory | /workspace/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3883845469 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 300625970 ps |
| CPU time | 2.26 seconds |
| Started | Feb 07 01:08:15 PM PST 24 |
| Finished | Feb 07 01:08:18 PM PST 24 |
| Peak memory | 200696 kb |
| Host | smart-70c159b1-d3fd-4a1e-8d38-d2f3095b376b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883845469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3883845469 |
| Directory | /workspace/15.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.932966478 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 881419553 ps |
| CPU time | 3.23 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:16 PM PST 24 |
| Peak memory | 200648 kb |
| Host | smart-caf7216d-80bd-4eaf-a9f7-3dd2a446752f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932966478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err .932966478 |
| Directory | /workspace/15.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3270469756 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 105480678 ps |
| CPU time | 0.99 seconds |
| Started | Feb 07 01:08:08 PM PST 24 |
| Finished | Feb 07 01:08:10 PM PST 24 |
| Peak memory | 200424 kb |
| Host | smart-a7637698-a781-4a21-9d66-524493f35f2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270469756 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3270469756 |
| Directory | /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3075458574 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 84994995 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 01:08:04 PM PST 24 |
| Finished | Feb 07 01:08:06 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-03608af8-5161-41a6-8e95-ddf444091e40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075458574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3075458574 |
| Directory | /workspace/16.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2265795936 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 95574026 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:14 PM PST 24 |
| Peak memory | 200660 kb |
| Host | smart-d4fddc74-b34e-42e1-b971-686f9a1ac415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265795936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s ame_csr_outstanding.2265795936 |
| Directory | /workspace/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3785724101 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 579734995 ps |
| CPU time | 4.28 seconds |
| Started | Feb 07 01:08:01 PM PST 24 |
| Finished | Feb 07 01:08:08 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-64895d91-a6f4-4216-81db-ce8939675b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785724101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3785724101 |
| Directory | /workspace/16.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.750611275 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 130326702 ps |
| CPU time | 1.49 seconds |
| Started | Feb 07 01:08:15 PM PST 24 |
| Finished | Feb 07 01:08:17 PM PST 24 |
| Peak memory | 210988 kb |
| Host | smart-f77aa223-ec13-4f84-8167-9621b1439342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750611275 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.750611275 |
| Directory | /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.956094817 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 74407606 ps |
| CPU time | 0.77 seconds |
| Started | Feb 07 01:08:08 PM PST 24 |
| Finished | Feb 07 01:08:10 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-4eba9971-9efc-44b4-bf66-1d9be686b3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956094817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.956094817 |
| Directory | /workspace/17.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2548800495 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 256405454 ps |
| CPU time | 1.6 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-7b85fac1-d065-41ba-91d6-c4c9b0e28640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548800495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s ame_csr_outstanding.2548800495 |
| Directory | /workspace/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4219663335 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 304321227 ps |
| CPU time | 2.04 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200704 kb |
| Host | smart-a59e75e6-51a3-4359-b74b-bad2ac9eed9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219663335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4219663335 |
| Directory | /workspace/17.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2128628032 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 425160378 ps |
| CPU time | 1.94 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:14 PM PST 24 |
| Peak memory | 200612 kb |
| Host | smart-9de5168d-bccb-48ef-be57-32259c41c195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128628032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er r.2128628032 |
| Directory | /workspace/17.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3677880686 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 146331126 ps |
| CPU time | 1.19 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-48ad39f5-91c2-4cb3-b47e-bb2dc8484172 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677880686 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3677880686 |
| Directory | /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1159561770 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 58359690 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 01:08:07 PM PST 24 |
| Finished | Feb 07 01:08:08 PM PST 24 |
| Peak memory | 200472 kb |
| Host | smart-062e06d4-8f6c-4984-aaaa-743fe37e91be |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159561770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1159561770 |
| Directory | /workspace/18.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3046422360 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 130735597 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:11 PM PST 24 |
| Peak memory | 200376 kb |
| Host | smart-f1a1d453-812d-4895-9cf7-934df3532008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046422360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s ame_csr_outstanding.3046422360 |
| Directory | /workspace/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3323462594 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 296693720 ps |
| CPU time | 2.34 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:15 PM PST 24 |
| Peak memory | 200648 kb |
| Host | smart-2e34ef24-43db-4304-874d-5b78cba5b90a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323462594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3323462594 |
| Directory | /workspace/18.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.854001303 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 478874650 ps |
| CPU time | 1.89 seconds |
| Started | Feb 07 01:08:01 PM PST 24 |
| Finished | Feb 07 01:08:05 PM PST 24 |
| Peak memory | 200644 kb |
| Host | smart-a6e03ca0-4d06-468d-b014-cc1dacb7d979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854001303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err .854001303 |
| Directory | /workspace/18.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.873491040 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 186862366 ps |
| CPU time | 1.14 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-982e59d9-757b-456a-9453-d1aee8c4c5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873491040 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.873491040 |
| Directory | /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3986788791 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 73036479 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 01:08:08 PM PST 24 |
| Finished | Feb 07 01:08:10 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-cb68a539-8964-4dec-8f1e-d09631ce3aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986788791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3986788791 |
| Directory | /workspace/19.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2195758204 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 132068603 ps |
| CPU time | 1.21 seconds |
| Started | Feb 07 01:08:08 PM PST 24 |
| Finished | Feb 07 01:08:10 PM PST 24 |
| Peak memory | 200652 kb |
| Host | smart-6fdd0af1-5846-4db5-8d5a-d76be19ebdb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195758204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s ame_csr_outstanding.2195758204 |
| Directory | /workspace/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.389852733 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 472877123 ps |
| CPU time | 3.39 seconds |
| Started | Feb 07 01:08:15 PM PST 24 |
| Finished | Feb 07 01:08:19 PM PST 24 |
| Peak memory | 216284 kb |
| Host | smart-dcb1b49e-eb11-46ca-ac44-cbc497f2583a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389852733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.389852733 |
| Directory | /workspace/19.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1057613935 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 488900702 ps |
| CPU time | 1.9 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:14 PM PST 24 |
| Peak memory | 200708 kb |
| Host | smart-b97991a2-91cf-439e-af7c-05ce6deca2eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057613935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er r.1057613935 |
| Directory | /workspace/19.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2170913973 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 210788274 ps |
| CPU time | 1.53 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200680 kb |
| Host | smart-724f0c52-807a-4a00-95c7-8fdd5bfc3513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170913973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2 170913973 |
| Directory | /workspace/2.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1162980924 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 266541144 ps |
| CPU time | 3.35 seconds |
| Started | Feb 07 01:08:02 PM PST 24 |
| Finished | Feb 07 01:08:07 PM PST 24 |
| Peak memory | 200632 kb |
| Host | smart-acf93822-1d1d-4d29-870f-c406dccc1b84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162980924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1 162980924 |
| Directory | /workspace/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4089024279 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 128243882 ps |
| CPU time | 0.87 seconds |
| Started | Feb 07 01:07:59 PM PST 24 |
| Finished | Feb 07 01:08:01 PM PST 24 |
| Peak memory | 200472 kb |
| Host | smart-a1fafe59-d81e-48b6-96e4-5f707f532bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089024279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4 089024279 |
| Directory | /workspace/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2182301995 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 110080755 ps |
| CPU time | 0.98 seconds |
| Started | Feb 07 01:08:08 PM PST 24 |
| Finished | Feb 07 01:08:10 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-c2891f7e-dbff-451b-8e29-42fda3eb87f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182301995 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2182301995 |
| Directory | /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3262519906 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 65657581 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:00 PM PST 24 |
| Peak memory | 200416 kb |
| Host | smart-f2b6edc3-7731-4c6a-8737-fac18409da7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262519906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3262519906 |
| Directory | /workspace/2.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2414952312 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 236617893 ps |
| CPU time | 1.55 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:00 PM PST 24 |
| Peak memory | 200636 kb |
| Host | smart-4312087e-caf0-4ae1-9f51-86821d5df97e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414952312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa me_csr_outstanding.2414952312 |
| Directory | /workspace/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2291524022 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 118034352 ps |
| CPU time | 1.67 seconds |
| Started | Feb 07 01:07:59 PM PST 24 |
| Finished | Feb 07 01:08:01 PM PST 24 |
| Peak memory | 200728 kb |
| Host | smart-dee3cc7e-7c19-4e47-b515-d172aaeea6d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291524022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2291524022 |
| Directory | /workspace/2.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1416408103 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 618295529 ps |
| CPU time | 2.16 seconds |
| Started | Feb 07 01:07:59 PM PST 24 |
| Finished | Feb 07 01:08:02 PM PST 24 |
| Peak memory | 200632 kb |
| Host | smart-4faa7cff-8b5f-4dcb-a5b8-6966fb1ccdec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416408103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err .1416408103 |
| Directory | /workspace/2.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1281104198 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 351700211 ps |
| CPU time | 2.42 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:01 PM PST 24 |
| Peak memory | 200604 kb |
| Host | smart-2d5f799a-279b-4397-8b5b-69b7de21a9ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281104198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1 281104198 |
| Directory | /workspace/3.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.15208883 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1197374620 ps |
| CPU time | 5.4 seconds |
| Started | Feb 07 01:08:08 PM PST 24 |
| Finished | Feb 07 01:08:15 PM PST 24 |
| Peak memory | 200604 kb |
| Host | smart-a0b1f95f-2ea5-4ace-9d55-be8b58fdf49d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15208883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.15208883 |
| Directory | /workspace/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4076581738 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 140955004 ps |
| CPU time | 0.9 seconds |
| Started | Feb 07 01:08:05 PM PST 24 |
| Finished | Feb 07 01:08:07 PM PST 24 |
| Peak memory | 200440 kb |
| Host | smart-1ab13702-b349-44c5-b72c-5bb3434e1f6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076581738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4 076581738 |
| Directory | /workspace/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1615594148 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 146247533 ps |
| CPU time | 1.02 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:07:59 PM PST 24 |
| Peak memory | 200524 kb |
| Host | smart-96ec896c-0f59-4385-84c6-26b2260b4e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615594148 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1615594148 |
| Directory | /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1701207336 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 65063794 ps |
| CPU time | 0.77 seconds |
| Started | Feb 07 01:08:02 PM PST 24 |
| Finished | Feb 07 01:08:04 PM PST 24 |
| Peak memory | 200364 kb |
| Host | smart-2efe1cfc-f8c2-46b3-ac6d-eee21a2f3140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701207336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1701207336 |
| Directory | /workspace/3.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2552125714 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 90907564 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 01:07:54 PM PST 24 |
| Finished | Feb 07 01:07:55 PM PST 24 |
| Peak memory | 200652 kb |
| Host | smart-c4419483-4755-4c73-b0a2-cc212f9d89ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552125714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa me_csr_outstanding.2552125714 |
| Directory | /workspace/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4172370507 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 283816191 ps |
| CPU time | 2.37 seconds |
| Started | Feb 07 01:08:02 PM PST 24 |
| Finished | Feb 07 01:08:06 PM PST 24 |
| Peak memory | 200584 kb |
| Host | smart-f2d13593-e5bb-4df1-a69d-837864198305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172370507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.4172370507 |
| Directory | /workspace/3.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3830521518 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 418700135 ps |
| CPU time | 1.76 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:01 PM PST 24 |
| Peak memory | 200600 kb |
| Host | smart-b863e46f-bdc8-46b7-97ed-2b000af70cf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830521518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err .3830521518 |
| Directory | /workspace/3.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2119444680 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 201872275 ps |
| CPU time | 1.46 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:01 PM PST 24 |
| Peak memory | 200580 kb |
| Host | smart-03359d8d-baf5-4f09-9810-25a61ccdb48d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119444680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2 119444680 |
| Directory | /workspace/4.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1609881402 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1576469403 ps |
| CPU time | 8.14 seconds |
| Started | Feb 07 01:07:56 PM PST 24 |
| Finished | Feb 07 01:08:05 PM PST 24 |
| Peak memory | 200564 kb |
| Host | smart-1e8d9c52-4977-46e9-9fd0-9316a3ab9285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609881402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1 609881402 |
| Directory | /workspace/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1794723481 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 143740994 ps |
| CPU time | 0.91 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:00 PM PST 24 |
| Peak memory | 200320 kb |
| Host | smart-554960eb-af18-421c-ba0b-690f6d2c8e6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794723481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1 794723481 |
| Directory | /workspace/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.520259576 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 96988300 ps |
| CPU time | 1.03 seconds |
| Started | Feb 07 01:08:00 PM PST 24 |
| Finished | Feb 07 01:08:02 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-3a8a160e-1b01-4485-93d6-adb3690aef39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520259576 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.520259576 |
| Directory | /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1047218146 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 61791038 ps |
| CPU time | 0.79 seconds |
| Started | Feb 07 01:08:05 PM PST 24 |
| Finished | Feb 07 01:08:06 PM PST 24 |
| Peak memory | 200424 kb |
| Host | smart-34a7c077-6999-44d8-b3b6-3df0132088bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047218146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1047218146 |
| Directory | /workspace/4.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3228576025 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 236541782 ps |
| CPU time | 1.57 seconds |
| Started | Feb 07 01:08:00 PM PST 24 |
| Finished | Feb 07 01:08:03 PM PST 24 |
| Peak memory | 200628 kb |
| Host | smart-b2576a64-cb50-43b8-9c46-6cd836c152bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228576025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa me_csr_outstanding.3228576025 |
| Directory | /workspace/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.4179168454 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 235582034 ps |
| CPU time | 1.81 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:01 PM PST 24 |
| Peak memory | 200668 kb |
| Host | smart-ad64ea5d-c68f-447c-9d1d-5c53cb0aa19d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179168454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.4179168454 |
| Directory | /workspace/4.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.94925961 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 483943065 ps |
| CPU time | 1.98 seconds |
| Started | Feb 07 01:08:02 PM PST 24 |
| Finished | Feb 07 01:08:05 PM PST 24 |
| Peak memory | 200632 kb |
| Host | smart-f0084fb9-8c33-46c6-9a3d-1ab1792d7afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94925961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.94925961 |
| Directory | /workspace/4.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.260463326 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 128367650 ps |
| CPU time | 1 seconds |
| Started | Feb 07 01:08:07 PM PST 24 |
| Finished | Feb 07 01:08:09 PM PST 24 |
| Peak memory | 200512 kb |
| Host | smart-d5ccd5d2-5ce6-4b6c-8339-2c2ab12500f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260463326 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.260463326 |
| Directory | /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2693595692 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 55734142 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 01:07:54 PM PST 24 |
| Finished | Feb 07 01:07:55 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-2242c931-d368-4c8c-8681-5519f6a0d6a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693595692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2693595692 |
| Directory | /workspace/5.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3493508223 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 255693142 ps |
| CPU time | 1.67 seconds |
| Started | Feb 07 01:08:01 PM PST 24 |
| Finished | Feb 07 01:08:04 PM PST 24 |
| Peak memory | 200712 kb |
| Host | smart-116c9c38-9c7e-4141-8e99-ec43cdb3d2b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493508223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa me_csr_outstanding.3493508223 |
| Directory | /workspace/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1415677485 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 200622534 ps |
| CPU time | 1.8 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:00 PM PST 24 |
| Peak memory | 208904 kb |
| Host | smart-8897ef71-4d02-4d78-8f3c-0a47f5f5deb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415677485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1415677485 |
| Directory | /workspace/5.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1346737339 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 441907224 ps |
| CPU time | 1.83 seconds |
| Started | Feb 07 01:08:01 PM PST 24 |
| Finished | Feb 07 01:08:05 PM PST 24 |
| Peak memory | 200604 kb |
| Host | smart-6d34d1ed-b68e-4296-af3f-a7601346a846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346737339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err .1346737339 |
| Directory | /workspace/5.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2285464927 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 233123481 ps |
| CPU time | 1.44 seconds |
| Started | Feb 07 01:08:02 PM PST 24 |
| Finished | Feb 07 01:08:05 PM PST 24 |
| Peak memory | 200432 kb |
| Host | smart-81b9502c-e0a7-4876-8f75-81fff208ac53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285464927 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2285464927 |
| Directory | /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1889572912 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 70532900 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 01:07:55 PM PST 24 |
| Finished | Feb 07 01:07:56 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-1fbf92c8-e139-473a-9698-680f7b7928de |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889572912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1889572912 |
| Directory | /workspace/6.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3520433914 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 81531610 ps |
| CPU time | 0.93 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:00 PM PST 24 |
| Peak memory | 200420 kb |
| Host | smart-384b6f6b-1793-4553-8d58-435f7162b6f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520433914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa me_csr_outstanding.3520433914 |
| Directory | /workspace/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2900613785 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 122791743 ps |
| CPU time | 1.73 seconds |
| Started | Feb 07 01:08:07 PM PST 24 |
| Finished | Feb 07 01:08:09 PM PST 24 |
| Peak memory | 200728 kb |
| Host | smart-bb7fa5bd-36d1-4ce0-bb64-b237292ca7a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900613785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2900613785 |
| Directory | /workspace/6.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2583166604 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 62196686 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 01:08:02 PM PST 24 |
| Finished | Feb 07 01:08:04 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-91664e6e-5447-4c7f-82a5-734d53f1091f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583166604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2583166604 |
| Directory | /workspace/7.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.454731665 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 183738305 ps |
| CPU time | 1.43 seconds |
| Started | Feb 07 01:08:00 PM PST 24 |
| Finished | Feb 07 01:08:03 PM PST 24 |
| Peak memory | 200580 kb |
| Host | smart-d6397973-b1a8-4280-bb82-92ea360dba64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454731665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam e_csr_outstanding.454731665 |
| Directory | /workspace/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.27205466 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 502536362 ps |
| CPU time | 3.4 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:02 PM PST 24 |
| Peak memory | 200624 kb |
| Host | smart-11bc6412-7dc2-4c75-ae9e-e4eb9f394bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.27205466 |
| Directory | /workspace/7.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2785955031 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 486498140 ps |
| CPU time | 2.04 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200560 kb |
| Host | smart-8f599235-4335-4a5c-b5cd-e3547b0f444a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785955031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err .2785955031 |
| Directory | /workspace/7.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1206633599 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 140992212 ps |
| CPU time | 1.38 seconds |
| Started | Feb 07 01:08:02 PM PST 24 |
| Finished | Feb 07 01:08:05 PM PST 24 |
| Peak memory | 208684 kb |
| Host | smart-31c5a8ff-64df-4c55-a7e5-d1bcd2a018d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206633599 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1206633599 |
| Directory | /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3580123372 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 71525794 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:00 PM PST 24 |
| Peak memory | 200464 kb |
| Host | smart-0055fb1c-24ab-40f2-8149-e2dc529d81c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580123372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3580123372 |
| Directory | /workspace/8.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.381953543 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 128944610 ps |
| CPU time | 1.24 seconds |
| Started | Feb 07 01:07:59 PM PST 24 |
| Finished | Feb 07 01:08:01 PM PST 24 |
| Peak memory | 200648 kb |
| Host | smart-254303f7-e4f0-4882-a9a2-f7c0b1d42c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381953543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam e_csr_outstanding.381953543 |
| Directory | /workspace/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3212130575 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 386248490 ps |
| CPU time | 2.76 seconds |
| Started | Feb 07 01:08:09 PM PST 24 |
| Finished | Feb 07 01:08:13 PM PST 24 |
| Peak memory | 200640 kb |
| Host | smart-ff64288d-4900-493b-8689-84ab2b35c87b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212130575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3212130575 |
| Directory | /workspace/8.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3596607516 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 411664066 ps |
| CPU time | 1.84 seconds |
| Started | Feb 07 01:07:58 PM PST 24 |
| Finished | Feb 07 01:08:00 PM PST 24 |
| Peak memory | 200636 kb |
| Host | smart-8ecb9c0a-e0d3-46c6-9bee-10fb006289de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596607516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err .3596607516 |
| Directory | /workspace/8.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.697178975 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 98661898 ps |
| CPU time | 0.84 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:14 PM PST 24 |
| Peak memory | 200508 kb |
| Host | smart-8bd7a410-66f2-48d9-85b9-6a58d65fd5e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697178975 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.697178975 |
| Directory | /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2406778188 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 64405060 ps |
| CPU time | 0.72 seconds |
| Started | Feb 07 01:08:10 PM PST 24 |
| Finished | Feb 07 01:08:12 PM PST 24 |
| Peak memory | 200408 kb |
| Host | smart-fc5dbeee-aa67-4aa3-9599-f87beb26f5cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406778188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2406778188 |
| Directory | /workspace/9.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3753907114 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 147244305 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:14 PM PST 24 |
| Peak memory | 200480 kb |
| Host | smart-ff6dc107-f681-4b54-bf2e-382aa9341796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753907114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa me_csr_outstanding.3753907114 |
| Directory | /workspace/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2596421571 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 495196018 ps |
| CPU time | 2.05 seconds |
| Started | Feb 07 01:08:11 PM PST 24 |
| Finished | Feb 07 01:08:15 PM PST 24 |
| Peak memory | 200660 kb |
| Host | smart-01afc384-6407-49cc-b5bf-840a5177b227 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596421571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err .2596421571 |
| Directory | /workspace/9.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rstmgr_alert_test.2323581913 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 70362556 ps |
| CPU time | 0.7 seconds |
| Started | Feb 07 12:41:11 PM PST 24 |
| Finished | Feb 07 12:41:14 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-9932946e-c4b8-4a2b-a099-fd7781e0cc4a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323581913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2323581913 |
| Directory | /workspace/0.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2597725794 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2158506672 ps |
| CPU time | 7.79 seconds |
| Started | Feb 07 12:41:10 PM PST 24 |
| Finished | Feb 07 12:41:19 PM PST 24 |
| Peak memory | 216852 kb |
| Host | smart-46697678-2ddd-48f1-8091-7e5f0a2f4ec7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597725794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2597725794 |
| Directory | /workspace/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.698348631 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 243704347 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 12:41:10 PM PST 24 |
| Finished | Feb 07 12:41:12 PM PST 24 |
| Peak memory | 217204 kb |
| Host | smart-0b87da6f-2178-4e06-9de0-8c26056e3a94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698348631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.698348631 |
| Directory | /workspace/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/0.rstmgr_por_stretcher.1576362216 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 167857299 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:41:08 PM PST 24 |
| Finished | Feb 07 12:41:10 PM PST 24 |
| Peak memory | 199700 kb |
| Host | smart-9b521cf9-4645-4200-b2ec-6b6880d925b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576362216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1576362216 |
| Directory | /workspace/0.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/0.rstmgr_reset.678011017 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1957718174 ps |
| CPU time | 7.21 seconds |
| Started | Feb 07 12:41:09 PM PST 24 |
| Finished | Feb 07 12:41:18 PM PST 24 |
| Peak memory | 200244 kb |
| Host | smart-5712c423-f389-4f08-acda-fd4656dcd823 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=678011017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.678011017 |
| Directory | /workspace/0.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sec_cm.54889533 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 16507912269 ps |
| CPU time | 26.16 seconds |
| Started | Feb 07 12:41:11 PM PST 24 |
| Finished | Feb 07 12:41:38 PM PST 24 |
| Peak memory | 217920 kb |
| Host | smart-6d3840bc-92f1-4f67-8c2d-2e3af8902875 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54889533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.54889533 |
| Directory | /workspace/0.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.49753370 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 149438675 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 12:41:09 PM PST 24 |
| Finished | Feb 07 12:41:11 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-c5ac985c-d977-4314-8837-0012127885c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49753370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.49753370 |
| Directory | /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/0.rstmgr_smoke.3328124761 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 113400453 ps |
| CPU time | 1.18 seconds |
| Started | Feb 07 12:41:10 PM PST 24 |
| Finished | Feb 07 12:41:13 PM PST 24 |
| Peak memory | 200180 kb |
| Host | smart-59a4c1d0-b2b4-432d-8471-f907a0e018f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328124761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3328124761 |
| Directory | /workspace/0.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/0.rstmgr_stress_all.2470956798 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 6175794899 ps |
| CPU time | 26.29 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:40 PM PST 24 |
| Peak memory | 200200 kb |
| Host | smart-4d8c5c4f-601f-452f-9bbb-8a8ff119b61a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470956798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2470956798 |
| Directory | /workspace/0.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sw_rst.2898772475 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 256751045 ps |
| CPU time | 1.72 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:16 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-1a6beb90-2b41-4e61-9204-de6c81e6f7f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898772475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2898772475 |
| Directory | /workspace/0.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3128317537 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 164988675 ps |
| CPU time | 1.19 seconds |
| Started | Feb 07 12:41:10 PM PST 24 |
| Finished | Feb 07 12:41:12 PM PST 24 |
| Peak memory | 200008 kb |
| Host | smart-70825485-d6b2-498c-8bba-491a5dc75298 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128317537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3128317537 |
| Directory | /workspace/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/1.rstmgr_alert_test.885387673 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 73441418 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:15 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-26827cc0-931a-4d69-95c0-8d39e7bc3d75 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885387673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.885387673 |
| Directory | /workspace/1.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.556386468 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1889301747 ps |
| CPU time | 7.21 seconds |
| Started | Feb 07 12:41:10 PM PST 24 |
| Finished | Feb 07 12:41:19 PM PST 24 |
| Peak memory | 216788 kb |
| Host | smart-d01f9456-58a4-4cef-9fd3-b73f89f8c51e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556386468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.556386468 |
| Directory | /workspace/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1933065463 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 244609559 ps |
| CPU time | 1.03 seconds |
| Started | Feb 07 12:41:11 PM PST 24 |
| Finished | Feb 07 12:41:13 PM PST 24 |
| Peak memory | 217320 kb |
| Host | smart-3da2bbe8-ca2d-4fea-b2ea-ec81b5d52c33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933065463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1933065463 |
| Directory | /workspace/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/1.rstmgr_por_stretcher.2873532136 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 169231207 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:14 PM PST 24 |
| Peak memory | 199780 kb |
| Host | smart-31c6afdc-a71e-4ce4-a49c-d0cb8a5b3624 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873532136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2873532136 |
| Directory | /workspace/1.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/1.rstmgr_reset.1479133267 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1456216519 ps |
| CPU time | 6.44 seconds |
| Started | Feb 07 12:41:11 PM PST 24 |
| Finished | Feb 07 12:41:18 PM PST 24 |
| Peak memory | 200160 kb |
| Host | smart-f79cddfd-ff3e-4d70-b1c5-c0b33f23405b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479133267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1479133267 |
| Directory | /workspace/1.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sec_cm.1592874917 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 16521706514 ps |
| CPU time | 30.4 seconds |
| Started | Feb 07 12:41:10 PM PST 24 |
| Finished | Feb 07 12:41:42 PM PST 24 |
| Peak memory | 217988 kb |
| Host | smart-03c515db-b0e0-460d-bfb9-f0591587b624 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592874917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1592874917 |
| Directory | /workspace/1.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2021524754 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 95996376 ps |
| CPU time | 0.94 seconds |
| Started | Feb 07 12:41:14 PM PST 24 |
| Finished | Feb 07 12:41:16 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-42f87328-a7be-45ca-94d6-9f712a87b62b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2021524754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2021524754 |
| Directory | /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/1.rstmgr_smoke.3613230262 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 205526246 ps |
| CPU time | 1.36 seconds |
| Started | Feb 07 12:41:10 PM PST 24 |
| Finished | Feb 07 12:41:13 PM PST 24 |
| Peak memory | 200036 kb |
| Host | smart-bd8ac1fe-00d0-4495-9780-22209eedfbf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3613230262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3613230262 |
| Directory | /workspace/1.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/1.rstmgr_stress_all.3193413083 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 928569971 ps |
| CPU time | 4.62 seconds |
| Started | Feb 07 12:41:11 PM PST 24 |
| Finished | Feb 07 12:41:17 PM PST 24 |
| Peak memory | 200264 kb |
| Host | smart-a907d15e-ccad-46b4-a88a-06b6813d2a5d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193413083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3193413083 |
| Directory | /workspace/1.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sw_rst.1826041486 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 142874710 ps |
| CPU time | 1.79 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:16 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-5091a7b0-8162-4adb-ad67-9124fab32db5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826041486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1826041486 |
| Directory | /workspace/1.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3335670263 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 160113465 ps |
| CPU time | 1.22 seconds |
| Started | Feb 07 12:41:10 PM PST 24 |
| Finished | Feb 07 12:41:13 PM PST 24 |
| Peak memory | 200032 kb |
| Host | smart-c3917d03-ed94-45f5-8469-7be7535b93c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335670263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3335670263 |
| Directory | /workspace/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/10.rstmgr_alert_test.3714276744 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 87040109 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 12:41:38 PM PST 24 |
| Finished | Feb 07 12:41:39 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-f3a18093-b8c4-4bd0-940e-131a81fd1467 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714276744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3714276744 |
| Directory | /workspace/10.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.747119270 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2169128383 ps |
| CPU time | 8.1 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:50 PM PST 24 |
| Peak memory | 217960 kb |
| Host | smart-d0bb96cd-6ad2-4dc3-a22f-8760efed80c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747119270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.747119270 |
| Directory | /workspace/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.461884994 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 243499593 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:41:39 PM PST 24 |
| Finished | Feb 07 12:41:41 PM PST 24 |
| Peak memory | 217208 kb |
| Host | smart-622010c3-0f60-4b76-b6c2-e53134d03465 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461884994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.461884994 |
| Directory | /workspace/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/10.rstmgr_por_stretcher.33166340 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 105330738 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:41:30 PM PST 24 |
| Finished | Feb 07 12:41:32 PM PST 24 |
| Peak memory | 199700 kb |
| Host | smart-1496bdef-d7b3-458b-898a-6bed9fd47985 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33166340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.33166340 |
| Directory | /workspace/10.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/10.rstmgr_reset.2456176032 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1694338204 ps |
| CPU time | 6.54 seconds |
| Started | Feb 07 12:41:27 PM PST 24 |
| Finished | Feb 07 12:41:35 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-2ccfdf90-be33-4178-833e-02f1d563ba82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456176032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2456176032 |
| Directory | /workspace/10.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1219015425 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 119734244 ps |
| CPU time | 0.99 seconds |
| Started | Feb 07 12:41:37 PM PST 24 |
| Finished | Feb 07 12:41:39 PM PST 24 |
| Peak memory | 199924 kb |
| Host | smart-56e6d78b-62a3-488c-8ec0-83ffa18c4cc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1219015425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1219015425 |
| Directory | /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/10.rstmgr_smoke.840535734 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 204325617 ps |
| CPU time | 1.32 seconds |
| Started | Feb 07 12:41:29 PM PST 24 |
| Finished | Feb 07 12:41:31 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-eb405f1a-05b4-4877-986c-7b465f55218e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840535734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.840535734 |
| Directory | /workspace/10.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/10.rstmgr_stress_all.2477101984 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 18134015607 ps |
| CPU time | 60.55 seconds |
| Started | Feb 07 12:41:38 PM PST 24 |
| Finished | Feb 07 12:42:39 PM PST 24 |
| Peak memory | 200240 kb |
| Host | smart-d4ad47da-563c-4c1b-baad-4a1962a4cfb3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477101984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2477101984 |
| Directory | /workspace/10.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sw_rst.3220764133 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 304663449 ps |
| CPU time | 1.91 seconds |
| Started | Feb 07 12:41:34 PM PST 24 |
| Finished | Feb 07 12:41:37 PM PST 24 |
| Peak memory | 200048 kb |
| Host | smart-3e8a73d7-2050-4a5e-af01-b1194548be5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220764133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3220764133 |
| Directory | /workspace/10.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1059893319 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 76157813 ps |
| CPU time | 0.79 seconds |
| Started | Feb 07 12:41:39 PM PST 24 |
| Finished | Feb 07 12:41:41 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-230635e1-2d3a-4b57-9b2e-70d5bdc8a826 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059893319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1059893319 |
| Directory | /workspace/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/11.rstmgr_alert_test.3776819736 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 69701136 ps |
| CPU time | 0.72 seconds |
| Started | Feb 07 12:41:37 PM PST 24 |
| Finished | Feb 07 12:41:39 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-882e3b61-72cf-4660-a6fc-45551702167c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776819736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3776819736 |
| Directory | /workspace/11.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1595229353 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 243732807 ps |
| CPU time | 1.07 seconds |
| Started | Feb 07 12:41:38 PM PST 24 |
| Finished | Feb 07 12:41:40 PM PST 24 |
| Peak memory | 217108 kb |
| Host | smart-c4520d2d-7bfe-4fd8-a69a-ccfd17b8ce1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1595229353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1595229353 |
| Directory | /workspace/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/11.rstmgr_por_stretcher.4006602994 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 173241261 ps |
| CPU time | 0.9 seconds |
| Started | Feb 07 12:41:41 PM PST 24 |
| Finished | Feb 07 12:41:43 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-225b56b4-30e6-4985-8b25-f98feda5d257 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4006602994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.4006602994 |
| Directory | /workspace/11.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/11.rstmgr_reset.621226645 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1525956948 ps |
| CPU time | 5.99 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:47 PM PST 24 |
| Peak memory | 200088 kb |
| Host | smart-58cf309d-7e78-4178-9337-2a3a0a111162 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621226645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.621226645 |
| Directory | /workspace/11.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.4168861249 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 174942520 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:41:37 PM PST 24 |
| Finished | Feb 07 12:41:39 PM PST 24 |
| Peak memory | 199948 kb |
| Host | smart-036c8343-da54-477f-a4bd-afcb1a4f38bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4168861249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.4168861249 |
| Directory | /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/11.rstmgr_smoke.1040654726 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 105582035 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 12:41:37 PM PST 24 |
| Finished | Feb 07 12:41:39 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-420efae4-4363-4fae-804d-7cd36ec04943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040654726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1040654726 |
| Directory | /workspace/11.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/11.rstmgr_stress_all.3195070147 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 373960435 ps |
| CPU time | 1.8 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:43 PM PST 24 |
| Peak memory | 200096 kb |
| Host | smart-a45e4cdf-6f41-4dd8-b698-714a29316443 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195070147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3195070147 |
| Directory | /workspace/11.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sw_rst.1161265993 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 255791752 ps |
| CPU time | 1.83 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:43 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-be9acffb-5df0-4375-98e5-4104324b93fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1161265993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1161265993 |
| Directory | /workspace/11.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.899939586 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 129027905 ps |
| CPU time | 1.02 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:42 PM PST 24 |
| Peak memory | 199972 kb |
| Host | smart-62fa540b-6d17-4d84-9443-417601472cdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899939586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.899939586 |
| Directory | /workspace/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/12.rstmgr_alert_test.89006154 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 97248227 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:41:39 PM PST 24 |
| Finished | Feb 07 12:41:41 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-7114186e-bb92-4484-ab8d-df18bb268156 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89006154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.89006154 |
| Directory | /workspace/12.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.195551807 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1232500161 ps |
| CPU time | 5.48 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:47 PM PST 24 |
| Peak memory | 216752 kb |
| Host | smart-313220b6-b255-44c3-b9df-0daa2d93b2c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195551807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.195551807 |
| Directory | /workspace/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/12.rstmgr_reset.1934598337 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 799157845 ps |
| CPU time | 3.84 seconds |
| Started | Feb 07 12:41:38 PM PST 24 |
| Finished | Feb 07 12:41:43 PM PST 24 |
| Peak memory | 200124 kb |
| Host | smart-6577004b-b65a-43f1-a58e-74d6d95d5613 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934598337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1934598337 |
| Directory | /workspace/12.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2744672613 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 98232779 ps |
| CPU time | 0.99 seconds |
| Started | Feb 07 12:41:38 PM PST 24 |
| Finished | Feb 07 12:41:40 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-34868b9c-db03-4b65-976d-345a7bea297b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744672613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2744672613 |
| Directory | /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/12.rstmgr_smoke.2080522510 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 205323421 ps |
| CPU time | 1.29 seconds |
| Started | Feb 07 12:41:38 PM PST 24 |
| Finished | Feb 07 12:41:40 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-ee7b67c0-7be2-4d86-8769-f930a15db921 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080522510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2080522510 |
| Directory | /workspace/12.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/12.rstmgr_stress_all.958718740 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 231989597 ps |
| CPU time | 1.54 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:43 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-8113deec-3c17-4ff3-95db-db232f402e90 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958718740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.958718740 |
| Directory | /workspace/12.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sw_rst.1240504442 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 131867256 ps |
| CPU time | 1.64 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:43 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-558a485b-4282-4e3c-9ebc-d6d58d1bbbdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240504442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1240504442 |
| Directory | /workspace/12.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2632794071 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 142400822 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:42 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-c7729f14-cd3d-4d34-b962-d4c37b97a8b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632794071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2632794071 |
| Directory | /workspace/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/13.rstmgr_alert_test.307883586 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 84579037 ps |
| CPU time | 0.83 seconds |
| Started | Feb 07 12:41:53 PM PST 24 |
| Finished | Feb 07 12:41:55 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-2cd3c4c5-767f-496c-bb25-e562db25a714 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307883586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.307883586 |
| Directory | /workspace/13.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1529669448 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2363513963 ps |
| CPU time | 8.44 seconds |
| Started | Feb 07 12:41:49 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 222024 kb |
| Host | smart-c4c1df4b-baaf-4dc1-90d2-e4f148893c11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529669448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1529669448 |
| Directory | /workspace/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1117492297 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 244571509 ps |
| CPU time | 1.06 seconds |
| Started | Feb 07 12:41:49 PM PST 24 |
| Finished | Feb 07 12:41:50 PM PST 24 |
| Peak memory | 217244 kb |
| Host | smart-c0f0ea00-2e32-4089-a437-51001e4d8bab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117492297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1117492297 |
| Directory | /workspace/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/13.rstmgr_por_stretcher.1229336001 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 143443417 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:41:41 PM PST 24 |
| Finished | Feb 07 12:41:43 PM PST 24 |
| Peak memory | 199720 kb |
| Host | smart-2c335034-f3b8-4c71-a7fc-aa4b749f5f0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229336001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1229336001 |
| Directory | /workspace/13.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/13.rstmgr_reset.3728672038 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 860460391 ps |
| CPU time | 4.65 seconds |
| Started | Feb 07 12:41:48 PM PST 24 |
| Finished | Feb 07 12:41:53 PM PST 24 |
| Peak memory | 200124 kb |
| Host | smart-0ae71828-becd-4c0d-8b11-62685f043f62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728672038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3728672038 |
| Directory | /workspace/13.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2627643873 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 148198312 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:41:54 PM PST 24 |
| Finished | Feb 07 12:41:57 PM PST 24 |
| Peak memory | 200032 kb |
| Host | smart-2f89c246-786b-460e-8888-141f7b8ccdb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627643873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2627643873 |
| Directory | /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/13.rstmgr_smoke.925724037 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 193735987 ps |
| CPU time | 1.43 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:42 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-602313eb-d657-4284-987d-6bb6c05a145a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925724037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.925724037 |
| Directory | /workspace/13.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/13.rstmgr_stress_all.2427783843 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 121113155 ps |
| CPU time | 1.01 seconds |
| Started | Feb 07 12:41:53 PM PST 24 |
| Finished | Feb 07 12:41:55 PM PST 24 |
| Peak memory | 199876 kb |
| Host | smart-99ced977-c868-49ec-adc4-5b6a40dbdd8e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427783843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2427783843 |
| Directory | /workspace/13.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sw_rst.594482017 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 149528270 ps |
| CPU time | 1.87 seconds |
| Started | Feb 07 12:41:51 PM PST 24 |
| Finished | Feb 07 12:41:53 PM PST 24 |
| Peak memory | 200096 kb |
| Host | smart-c24b2348-7a6b-4149-9dc2-2537619413fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594482017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.594482017 |
| Directory | /workspace/13.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1014709648 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 201456388 ps |
| CPU time | 1.37 seconds |
| Started | Feb 07 12:41:48 PM PST 24 |
| Finished | Feb 07 12:41:51 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-7af23232-6553-4ea5-b303-7eca9ad7f292 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014709648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1014709648 |
| Directory | /workspace/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/14.rstmgr_alert_test.3743767284 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 58664046 ps |
| CPU time | 0.71 seconds |
| Started | Feb 07 12:41:52 PM PST 24 |
| Finished | Feb 07 12:41:53 PM PST 24 |
| Peak memory | 199888 kb |
| Host | smart-aea365a0-edd9-4139-99c0-b7c024988aff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743767284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3743767284 |
| Directory | /workspace/14.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.963742223 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1227505315 ps |
| CPU time | 5.51 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:42:04 PM PST 24 |
| Peak memory | 217896 kb |
| Host | smart-5bc4c6fa-2d63-45e8-a181-73b3103ddded |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963742223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.963742223 |
| Directory | /workspace/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2105418283 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 244737866 ps |
| CPU time | 1.06 seconds |
| Started | Feb 07 12:41:53 PM PST 24 |
| Finished | Feb 07 12:41:56 PM PST 24 |
| Peak memory | 217276 kb |
| Host | smart-9a355bb3-d0e6-4517-8c7e-86009c45f1ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105418283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2105418283 |
| Directory | /workspace/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/14.rstmgr_por_stretcher.1399003283 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 159071703 ps |
| CPU time | 0.88 seconds |
| Started | Feb 07 12:41:49 PM PST 24 |
| Finished | Feb 07 12:41:50 PM PST 24 |
| Peak memory | 199732 kb |
| Host | smart-40d69af1-d592-4f3c-a108-02eebbf6f631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399003283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1399003283 |
| Directory | /workspace/14.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/14.rstmgr_reset.1527286380 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2167303868 ps |
| CPU time | 7.81 seconds |
| Started | Feb 07 12:41:49 PM PST 24 |
| Finished | Feb 07 12:41:58 PM PST 24 |
| Peak memory | 200208 kb |
| Host | smart-df01af8e-cbd7-44be-a15a-02bbad499f2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527286380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1527286380 |
| Directory | /workspace/14.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.696568354 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 105991824 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:41:51 PM PST 24 |
| Finished | Feb 07 12:41:53 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-6d48ab10-5ab2-42e9-81c4-8c90c490f713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696568354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.696568354 |
| Directory | /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/14.rstmgr_smoke.1091409612 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 120940582 ps |
| CPU time | 1.2 seconds |
| Started | Feb 07 12:41:52 PM PST 24 |
| Finished | Feb 07 12:41:55 PM PST 24 |
| Peak memory | 200168 kb |
| Host | smart-dc733acd-6cda-4e0a-94c7-b9047d37acb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091409612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1091409612 |
| Directory | /workspace/14.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/14.rstmgr_stress_all.4204604253 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1920996068 ps |
| CPU time | 8.95 seconds |
| Started | Feb 07 12:41:54 PM PST 24 |
| Finished | Feb 07 12:42:04 PM PST 24 |
| Peak memory | 200216 kb |
| Host | smart-e1cec355-cbe2-4386-8a65-5bd1bd5f041f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204604253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.4204604253 |
| Directory | /workspace/14.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1742241138 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 189661478 ps |
| CPU time | 1.27 seconds |
| Started | Feb 07 12:41:49 PM PST 24 |
| Finished | Feb 07 12:41:51 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-625a800e-3e26-4987-a004-906dd4c3bc89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742241138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1742241138 |
| Directory | /workspace/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/15.rstmgr_alert_test.378515567 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 96814030 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 12:42:00 PM PST 24 |
| Finished | Feb 07 12:42:03 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-3d5257b6-5412-4120-a871-5daff0981c7a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378515567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.378515567 |
| Directory | /workspace/15.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1178058783 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1228922833 ps |
| CPU time | 5.8 seconds |
| Started | Feb 07 12:41:54 PM PST 24 |
| Finished | Feb 07 12:42:01 PM PST 24 |
| Peak memory | 221276 kb |
| Host | smart-997515b5-9e10-4053-a5ef-695df23d84f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178058783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1178058783 |
| Directory | /workspace/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.915451911 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 244658958 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:41:48 PM PST 24 |
| Finished | Feb 07 12:41:50 PM PST 24 |
| Peak memory | 217120 kb |
| Host | smart-fdb64b6f-f814-436c-95cb-56da467f32cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915451911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.915451911 |
| Directory | /workspace/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/15.rstmgr_por_stretcher.3298613926 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 127321732 ps |
| CPU time | 0.77 seconds |
| Started | Feb 07 12:41:50 PM PST 24 |
| Finished | Feb 07 12:41:52 PM PST 24 |
| Peak memory | 199712 kb |
| Host | smart-1abd4791-c374-444d-851c-bcf88e8b0039 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298613926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3298613926 |
| Directory | /workspace/15.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/15.rstmgr_reset.3587173483 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1606583251 ps |
| CPU time | 5.96 seconds |
| Started | Feb 07 12:41:52 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 200112 kb |
| Host | smart-772df7a4-6e87-437f-bf51-457f886882e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3587173483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3587173483 |
| Directory | /workspace/15.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/15.rstmgr_smoke.2120625318 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 121317324 ps |
| CPU time | 1.23 seconds |
| Started | Feb 07 12:41:50 PM PST 24 |
| Finished | Feb 07 12:41:53 PM PST 24 |
| Peak memory | 200136 kb |
| Host | smart-64e90686-b6d6-465c-8e69-dbb27ed99c9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120625318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2120625318 |
| Directory | /workspace/15.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sw_rst.1861493853 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 117748855 ps |
| CPU time | 1.45 seconds |
| Started | Feb 07 12:41:54 PM PST 24 |
| Finished | Feb 07 12:41:56 PM PST 24 |
| Peak memory | 199984 kb |
| Host | smart-16aedb67-0122-4d7a-9395-ec9976821413 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861493853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1861493853 |
| Directory | /workspace/15.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3618271709 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 87908208 ps |
| CPU time | 0.88 seconds |
| Started | Feb 07 12:41:55 PM PST 24 |
| Finished | Feb 07 12:41:57 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-e16f189b-ee9e-4091-878b-a5b9335343e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618271709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3618271709 |
| Directory | /workspace/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/16.rstmgr_alert_test.1474444150 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 63828447 ps |
| CPU time | 0.71 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-52eb4102-4f24-4edc-b4c3-7927f35cf59c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474444150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1474444150 |
| Directory | /workspace/16.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3089935065 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1901578441 ps |
| CPU time | 7 seconds |
| Started | Feb 07 12:41:52 PM PST 24 |
| Finished | Feb 07 12:42:00 PM PST 24 |
| Peak memory | 216304 kb |
| Host | smart-a3f70cd0-7581-4bf6-b802-1b48e3b88ade |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089935065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3089935065 |
| Directory | /workspace/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.965357294 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 244402769 ps |
| CPU time | 1.24 seconds |
| Started | Feb 07 12:42:01 PM PST 24 |
| Finished | Feb 07 12:42:04 PM PST 24 |
| Peak memory | 217132 kb |
| Host | smart-25a60deb-fb59-454e-aecf-4c51fd4a3be0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965357294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.965357294 |
| Directory | /workspace/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/16.rstmgr_por_stretcher.4017353213 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 179108812 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:41:53 PM PST 24 |
| Finished | Feb 07 12:41:55 PM PST 24 |
| Peak memory | 199900 kb |
| Host | smart-5f293329-e735-41f7-9454-414a15c6a7c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017353213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4017353213 |
| Directory | /workspace/16.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/16.rstmgr_reset.3267026067 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1950428407 ps |
| CPU time | 7.04 seconds |
| Started | Feb 07 12:41:52 PM PST 24 |
| Finished | Feb 07 12:42:00 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-07d2ec01-35bf-4cd2-83bb-b5395bc79d8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267026067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3267026067 |
| Directory | /workspace/16.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3441950740 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 97115284 ps |
| CPU time | 1.06 seconds |
| Started | Feb 07 12:41:54 PM PST 24 |
| Finished | Feb 07 12:41:56 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-f9a75922-e4af-4c99-9311-a924f2cbebb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3441950740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3441950740 |
| Directory | /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/16.rstmgr_smoke.4198449451 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 254068035 ps |
| CPU time | 1.43 seconds |
| Started | Feb 07 12:41:56 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 200156 kb |
| Host | smart-4eb39a7a-a5d1-4598-9375-1e0e5bf127d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198449451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4198449451 |
| Directory | /workspace/16.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/16.rstmgr_stress_all.992013154 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 229744254 ps |
| CPU time | 1.51 seconds |
| Started | Feb 07 12:41:52 PM PST 24 |
| Finished | Feb 07 12:41:55 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-276c1007-cdec-4592-9efa-3e6628c55986 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992013154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.992013154 |
| Directory | /workspace/16.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sw_rst.519146938 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 451657703 ps |
| CPU time | 2.32 seconds |
| Started | Feb 07 12:41:54 PM PST 24 |
| Finished | Feb 07 12:41:58 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-d5dee0c1-b8a7-42a5-8ae5-c61dd882428b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519146938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.519146938 |
| Directory | /workspace/16.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2979523481 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 114355577 ps |
| CPU time | 0.86 seconds |
| Started | Feb 07 12:41:54 PM PST 24 |
| Finished | Feb 07 12:41:56 PM PST 24 |
| Peak memory | 199872 kb |
| Host | smart-212e0868-5847-48f8-95a5-dfd5300a4caa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979523481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2979523481 |
| Directory | /workspace/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/17.rstmgr_alert_test.845486165 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 69782842 ps |
| CPU time | 0.77 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:41:58 PM PST 24 |
| Peak memory | 199848 kb |
| Host | smart-8b6d7440-3adb-4f74-a57e-16b948222f42 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845486165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.845486165 |
| Directory | /workspace/17.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2674939792 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1901044080 ps |
| CPU time | 7.43 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:42:07 PM PST 24 |
| Peak memory | 217188 kb |
| Host | smart-3c8e6ce6-f7a4-4d98-b6cc-4a24dff8e940 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2674939792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2674939792 |
| Directory | /workspace/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.165313510 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 245108023 ps |
| CPU time | 1.07 seconds |
| Started | Feb 07 12:41:52 PM PST 24 |
| Finished | Feb 07 12:41:54 PM PST 24 |
| Peak memory | 217296 kb |
| Host | smart-ba4968d6-12d3-4ea0-bfa4-544dd528131a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165313510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.165313510 |
| Directory | /workspace/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/17.rstmgr_por_stretcher.1974813237 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 183282009 ps |
| CPU time | 0.83 seconds |
| Started | Feb 07 12:41:49 PM PST 24 |
| Finished | Feb 07 12:41:50 PM PST 24 |
| Peak memory | 199736 kb |
| Host | smart-97407f47-44e6-40fb-81e8-dce2db54dd9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974813237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1974813237 |
| Directory | /workspace/17.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/17.rstmgr_reset.461777613 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1895417311 ps |
| CPU time | 6.9 seconds |
| Started | Feb 07 12:41:49 PM PST 24 |
| Finished | Feb 07 12:41:57 PM PST 24 |
| Peak memory | 200100 kb |
| Host | smart-10b26014-6f82-4fb3-a04e-4dc77e379f90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461777613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.461777613 |
| Directory | /workspace/17.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3021666532 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 103456004 ps |
| CPU time | 0.92 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 199944 kb |
| Host | smart-c75f9171-c881-4278-bfd3-9170e1933eb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021666532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3021666532 |
| Directory | /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/17.rstmgr_smoke.2868894124 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 247486613 ps |
| CPU time | 1.62 seconds |
| Started | Feb 07 12:41:50 PM PST 24 |
| Finished | Feb 07 12:41:53 PM PST 24 |
| Peak memory | 200036 kb |
| Host | smart-0f22ecc2-29cb-4021-a493-6e5ff3942177 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868894124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2868894124 |
| Directory | /workspace/17.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/17.rstmgr_stress_all.3095054762 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3895554923 ps |
| CPU time | 17.86 seconds |
| Started | Feb 07 12:41:50 PM PST 24 |
| Finished | Feb 07 12:42:09 PM PST 24 |
| Peak memory | 200180 kb |
| Host | smart-ba79f51d-e022-4c1b-bbf9-a97534cdddbd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095054762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3095054762 |
| Directory | /workspace/17.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sw_rst.508039852 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 149499626 ps |
| CPU time | 1.9 seconds |
| Started | Feb 07 12:41:51 PM PST 24 |
| Finished | Feb 07 12:41:54 PM PST 24 |
| Peak memory | 199956 kb |
| Host | smart-bbe18713-818d-4e99-b728-e62fee818d61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508039852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.508039852 |
| Directory | /workspace/17.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.175355732 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 87445048 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:41:56 PM PST 24 |
| Finished | Feb 07 12:41:58 PM PST 24 |
| Peak memory | 199904 kb |
| Host | smart-7f9955bc-f8dd-4711-ab24-d013a11ce253 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175355732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.175355732 |
| Directory | /workspace/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/18.rstmgr_alert_test.416536972 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 66905405 ps |
| CPU time | 0.69 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 199760 kb |
| Host | smart-f8514a79-13fd-4400-a686-df15606e9067 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416536972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.416536972 |
| Directory | /workspace/18.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.151073575 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1233376310 ps |
| CPU time | 5.63 seconds |
| Started | Feb 07 12:41:54 PM PST 24 |
| Finished | Feb 07 12:42:01 PM PST 24 |
| Peak memory | 221912 kb |
| Host | smart-15366d59-0a2c-4853-98ff-46d3d99c000f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151073575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.151073575 |
| Directory | /workspace/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2607838300 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 243986176 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 12:41:54 PM PST 24 |
| Finished | Feb 07 12:41:56 PM PST 24 |
| Peak memory | 217212 kb |
| Host | smart-5133ed4d-84fc-421d-959c-d051d4fd17f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607838300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2607838300 |
| Directory | /workspace/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/18.rstmgr_por_stretcher.689544323 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 175785377 ps |
| CPU time | 0.88 seconds |
| Started | Feb 07 12:42:01 PM PST 24 |
| Finished | Feb 07 12:42:03 PM PST 24 |
| Peak memory | 199752 kb |
| Host | smart-6c999cb2-cbfa-4118-983c-caff714919a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689544323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.689544323 |
| Directory | /workspace/18.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/18.rstmgr_reset.371983706 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 917947072 ps |
| CPU time | 4.66 seconds |
| Started | Feb 07 12:41:53 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 200216 kb |
| Host | smart-d61a7c76-48a2-475c-90cf-de46b5af237d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371983706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.371983706 |
| Directory | /workspace/18.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3231606815 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 108027850 ps |
| CPU time | 0.97 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 199944 kb |
| Host | smart-a01e3c24-1ca8-4b2b-9880-1c15de27c69e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231606815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3231606815 |
| Directory | /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/18.rstmgr_smoke.1452060467 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 227579427 ps |
| CPU time | 1.53 seconds |
| Started | Feb 07 12:41:53 PM PST 24 |
| Finished | Feb 07 12:41:56 PM PST 24 |
| Peak memory | 200156 kb |
| Host | smart-e98b1dd3-0164-4171-9fb8-62b60b9d9aaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452060467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1452060467 |
| Directory | /workspace/18.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/18.rstmgr_stress_all.2090958862 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 5827784133 ps |
| CPU time | 26.02 seconds |
| Started | Feb 07 12:41:50 PM PST 24 |
| Finished | Feb 07 12:42:17 PM PST 24 |
| Peak memory | 200116 kb |
| Host | smart-3289a930-ea33-4dcb-a846-58be0f3ec955 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090958862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2090958862 |
| Directory | /workspace/18.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sw_rst.4102187753 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 137159436 ps |
| CPU time | 1.86 seconds |
| Started | Feb 07 12:41:51 PM PST 24 |
| Finished | Feb 07 12:41:54 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-73100eb8-d71e-43b9-b401-71b47cdf9bb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102187753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.4102187753 |
| Directory | /workspace/18.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.11264674 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 119332965 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:41:52 PM PST 24 |
| Finished | Feb 07 12:41:54 PM PST 24 |
| Peak memory | 199956 kb |
| Host | smart-93902ddb-75eb-47ab-8977-8a17a468bb45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11264674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.11264674 |
| Directory | /workspace/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/19.rstmgr_alert_test.1198488683 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 68693297 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-8167db35-b582-4de7-8d66-2eb044fc6bf1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198488683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1198488683 |
| Directory | /workspace/19.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1552148493 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1898542018 ps |
| CPU time | 7.23 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:42:05 PM PST 24 |
| Peak memory | 221480 kb |
| Host | smart-9ec09ea2-614d-4ef5-b97d-5f48a1219aea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552148493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1552148493 |
| Directory | /workspace/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1348185231 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 245030196 ps |
| CPU time | 1.03 seconds |
| Started | Feb 07 12:41:56 PM PST 24 |
| Finished | Feb 07 12:41:58 PM PST 24 |
| Peak memory | 217228 kb |
| Host | smart-3768e080-41b6-43f6-91b8-b4f7661b9e49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348185231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1348185231 |
| Directory | /workspace/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/19.rstmgr_por_stretcher.4191583384 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 112446407 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:41:58 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-80dd6bcd-7f93-4b5b-8470-e12d8569feb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191583384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.4191583384 |
| Directory | /workspace/19.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/19.rstmgr_reset.3958292209 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1778718789 ps |
| CPU time | 6.31 seconds |
| Started | Feb 07 12:41:55 PM PST 24 |
| Finished | Feb 07 12:42:02 PM PST 24 |
| Peak memory | 200092 kb |
| Host | smart-98a2dfc6-668b-4078-8829-b3a5b990b023 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3958292209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3958292209 |
| Directory | /workspace/19.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3043769791 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 179441024 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 12:41:56 PM PST 24 |
| Finished | Feb 07 12:41:58 PM PST 24 |
| Peak memory | 199936 kb |
| Host | smart-911cc41e-2ada-4785-a2f1-ae02b0d68ed7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3043769791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3043769791 |
| Directory | /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/19.rstmgr_smoke.1471298888 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 192782384 ps |
| CPU time | 1.33 seconds |
| Started | Feb 07 12:41:55 PM PST 24 |
| Finished | Feb 07 12:41:57 PM PST 24 |
| Peak memory | 200176 kb |
| Host | smart-44b42fd1-1edf-48ac-b453-9519539b2d6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471298888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1471298888 |
| Directory | /workspace/19.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/19.rstmgr_stress_all.1942368197 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 7782680311 ps |
| CPU time | 34.67 seconds |
| Started | Feb 07 12:42:06 PM PST 24 |
| Finished | Feb 07 12:42:42 PM PST 24 |
| Peak memory | 200180 kb |
| Host | smart-b7830ad8-e4db-4a15-abbe-313aafd0a5a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942368197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1942368197 |
| Directory | /workspace/19.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sw_rst.3760832412 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 398495221 ps |
| CPU time | 2.12 seconds |
| Started | Feb 07 12:41:56 PM PST 24 |
| Finished | Feb 07 12:42:00 PM PST 24 |
| Peak memory | 200020 kb |
| Host | smart-8dc1eb4d-29fb-4f2c-9df1-c76b7d00d079 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760832412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3760832412 |
| Directory | /workspace/19.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3653625861 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 112278517 ps |
| CPU time | 0.91 seconds |
| Started | Feb 07 12:42:02 PM PST 24 |
| Finished | Feb 07 12:42:04 PM PST 24 |
| Peak memory | 199956 kb |
| Host | smart-d7319843-a80b-4c42-b91e-939863c5d697 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653625861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3653625861 |
| Directory | /workspace/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/2.rstmgr_alert_test.878930293 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 68994904 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:41:13 PM PST 24 |
| Finished | Feb 07 12:41:15 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-1d5960ee-6cdc-4915-86cb-7ec57f45c9bc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878930293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.878930293 |
| Directory | /workspace/2.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3473816486 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1232299470 ps |
| CPU time | 5.39 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:19 PM PST 24 |
| Peak memory | 217544 kb |
| Host | smart-62dc2ac5-44b7-436e-a191-79d52dfecc25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473816486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3473816486 |
| Directory | /workspace/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3449267143 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 243860164 ps |
| CPU time | 1.18 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:15 PM PST 24 |
| Peak memory | 217128 kb |
| Host | smart-d9b92a45-0b9a-4bb3-949c-eaf0bcc426c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449267143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3449267143 |
| Directory | /workspace/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/2.rstmgr_por_stretcher.3312454394 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 230902030 ps |
| CPU time | 0.94 seconds |
| Started | Feb 07 12:41:10 PM PST 24 |
| Finished | Feb 07 12:41:12 PM PST 24 |
| Peak memory | 199732 kb |
| Host | smart-7f2cb9ee-7e17-46c2-a0e7-078ae0b2fe61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3312454394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3312454394 |
| Directory | /workspace/2.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/2.rstmgr_reset.52965741 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1094411316 ps |
| CPU time | 5.3 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:19 PM PST 24 |
| Peak memory | 200188 kb |
| Host | smart-84934d0a-d785-48a5-8169-0815603b67ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52965741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.52965741 |
| Directory | /workspace/2.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1102288805 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 151773507 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:41:04 PM PST 24 |
| Finished | Feb 07 12:41:07 PM PST 24 |
| Peak memory | 199944 kb |
| Host | smart-ef28ec92-a9be-4ec5-8aed-47431bbc5c70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102288805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1102288805 |
| Directory | /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/2.rstmgr_smoke.3393217109 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 201541397 ps |
| CPU time | 1.3 seconds |
| Started | Feb 07 12:41:08 PM PST 24 |
| Finished | Feb 07 12:41:10 PM PST 24 |
| Peak memory | 200000 kb |
| Host | smart-8b958fff-18da-4c3f-acd1-d0794eb80957 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393217109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3393217109 |
| Directory | /workspace/2.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/2.rstmgr_stress_all.3366926255 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4936120431 ps |
| CPU time | 23.88 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:38 PM PST 24 |
| Peak memory | 200180 kb |
| Host | smart-c0021879-d5b2-4de5-8baf-1454160757db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366926255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3366926255 |
| Directory | /workspace/2.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sw_rst.668155752 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 524817451 ps |
| CPU time | 2.98 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:17 PM PST 24 |
| Peak memory | 199964 kb |
| Host | smart-0a16a089-5021-4ae0-b4c2-6ea23980d480 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668155752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.668155752 |
| Directory | /workspace/2.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3882223808 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 199327954 ps |
| CPU time | 1.25 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:15 PM PST 24 |
| Peak memory | 199992 kb |
| Host | smart-b8a12676-7b5f-41bd-8893-49c364fb78af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882223808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3882223808 |
| Directory | /workspace/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/20.rstmgr_alert_test.111710567 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 102277374 ps |
| CPU time | 0.93 seconds |
| Started | Feb 07 12:42:07 PM PST 24 |
| Finished | Feb 07 12:42:08 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-a92022f2-fd98-4e5a-8756-d3caee63df9f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111710567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.111710567 |
| Directory | /workspace/20.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2253158247 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 243820907 ps |
| CPU time | 1.06 seconds |
| Started | Feb 07 12:42:11 PM PST 24 |
| Finished | Feb 07 12:42:13 PM PST 24 |
| Peak memory | 217376 kb |
| Host | smart-fce5e319-aa33-4ef2-b242-cc9b69775e85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253158247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2253158247 |
| Directory | /workspace/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/20.rstmgr_por_stretcher.3320977455 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 154695051 ps |
| CPU time | 0.79 seconds |
| Started | Feb 07 12:42:08 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-76720547-2026-4df1-9d8f-3ceccd55406a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320977455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3320977455 |
| Directory | /workspace/20.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/20.rstmgr_reset.449513560 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1281792976 ps |
| CPU time | 4.79 seconds |
| Started | Feb 07 12:42:05 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 200184 kb |
| Host | smart-cc934653-849a-494e-a840-122a2a5dc0e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=449513560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.449513560 |
| Directory | /workspace/20.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1167168533 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 104285050 ps |
| CPU time | 0.96 seconds |
| Started | Feb 07 12:41:59 PM PST 24 |
| Finished | Feb 07 12:42:01 PM PST 24 |
| Peak memory | 199992 kb |
| Host | smart-6f214f23-6742-486e-9fa2-e38616b4e0ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167168533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1167168533 |
| Directory | /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/20.rstmgr_smoke.1111749984 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 117942083 ps |
| CPU time | 1.15 seconds |
| Started | Feb 07 12:41:57 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 200156 kb |
| Host | smart-aa892aeb-6139-4292-b4cb-2d5206e34965 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111749984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1111749984 |
| Directory | /workspace/20.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/20.rstmgr_stress_all.4204283579 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 6690209681 ps |
| CPU time | 25.79 seconds |
| Started | Feb 07 12:42:03 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 200244 kb |
| Host | smart-724f30e0-3302-44b1-83d4-802b916bcbce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204283579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4204283579 |
| Directory | /workspace/20.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sw_rst.2475065528 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 379702788 ps |
| CPU time | 2.1 seconds |
| Started | Feb 07 12:41:58 PM PST 24 |
| Finished | Feb 07 12:42:02 PM PST 24 |
| Peak memory | 199996 kb |
| Host | smart-75f3a3d2-df2b-437e-a09c-13cab58d303e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475065528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2475065528 |
| Directory | /workspace/20.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2071660814 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 95689727 ps |
| CPU time | 0.92 seconds |
| Started | Feb 07 12:42:03 PM PST 24 |
| Finished | Feb 07 12:42:04 PM PST 24 |
| Peak memory | 199952 kb |
| Host | smart-249d8648-a679-4d1b-ba49-e00823a512a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071660814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2071660814 |
| Directory | /workspace/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/21.rstmgr_alert_test.2342468475 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 80907215 ps |
| CPU time | 0.74 seconds |
| Started | Feb 07 12:42:16 PM PST 24 |
| Finished | Feb 07 12:42:17 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-f7f3c276-e6d0-4cc4-bbe7-bd3bbd1466a8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342468475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2342468475 |
| Directory | /workspace/21.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2085630900 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2196427105 ps |
| CPU time | 7.63 seconds |
| Started | Feb 07 12:42:15 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 220964 kb |
| Host | smart-5ba2c7fa-524c-4ae1-85fe-891c0aafb931 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085630900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2085630900 |
| Directory | /workspace/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3404029955 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 244570214 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:42:17 PM PST 24 |
| Finished | Feb 07 12:42:19 PM PST 24 |
| Peak memory | 217192 kb |
| Host | smart-bd7cd9b7-6b46-4b68-99d7-fe7bca210b69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404029955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3404029955 |
| Directory | /workspace/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/21.rstmgr_por_stretcher.4197169043 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 139691185 ps |
| CPU time | 0.79 seconds |
| Started | Feb 07 12:42:01 PM PST 24 |
| Finished | Feb 07 12:42:03 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-844816b0-41bb-42ad-9b4f-d7c772ced6f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197169043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.4197169043 |
| Directory | /workspace/21.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/21.rstmgr_reset.2694731931 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 791368778 ps |
| CPU time | 3.66 seconds |
| Started | Feb 07 12:42:15 PM PST 24 |
| Finished | Feb 07 12:42:19 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-d1d37294-7e23-4ee3-87f6-ca97bb666da8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694731931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2694731931 |
| Directory | /workspace/21.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1011746933 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 178818695 ps |
| CPU time | 1.29 seconds |
| Started | Feb 07 12:42:07 PM PST 24 |
| Finished | Feb 07 12:42:09 PM PST 24 |
| Peak memory | 199988 kb |
| Host | smart-8eb7d8a7-da05-4eb6-963e-7fcb5971e688 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011746933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1011746933 |
| Directory | /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/21.rstmgr_smoke.3026789444 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 244988954 ps |
| CPU time | 1.49 seconds |
| Started | Feb 07 12:42:05 PM PST 24 |
| Finished | Feb 07 12:42:08 PM PST 24 |
| Peak memory | 200132 kb |
| Host | smart-59401f96-8cde-45a9-abb4-422aad963e15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026789444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3026789444 |
| Directory | /workspace/21.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/21.rstmgr_stress_all.3257170421 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 8610192892 ps |
| CPU time | 30.62 seconds |
| Started | Feb 07 12:42:15 PM PST 24 |
| Finished | Feb 07 12:42:46 PM PST 24 |
| Peak memory | 200144 kb |
| Host | smart-063dfb4a-f4d9-424e-a405-933417f7e066 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257170421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3257170421 |
| Directory | /workspace/21.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sw_rst.3149240345 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 133165375 ps |
| CPU time | 1.66 seconds |
| Started | Feb 07 12:42:14 PM PST 24 |
| Finished | Feb 07 12:42:17 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-81e16deb-3092-4832-ba85-b9d07e047618 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149240345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3149240345 |
| Directory | /workspace/21.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2244916160 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 281695522 ps |
| CPU time | 1.52 seconds |
| Started | Feb 07 12:42:08 PM PST 24 |
| Finished | Feb 07 12:42:12 PM PST 24 |
| Peak memory | 200184 kb |
| Host | smart-e16a6b3e-70e4-4dc5-84c0-d3ef5f1bd3b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244916160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2244916160 |
| Directory | /workspace/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/22.rstmgr_alert_test.964169576 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 75279369 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:42:15 PM PST 24 |
| Finished | Feb 07 12:42:16 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-04aab1c1-413f-4bab-a3c3-a795608fe244 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964169576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.964169576 |
| Directory | /workspace/22.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1675651966 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1228949922 ps |
| CPU time | 5.84 seconds |
| Started | Feb 07 12:42:12 PM PST 24 |
| Finished | Feb 07 12:42:19 PM PST 24 |
| Peak memory | 221680 kb |
| Host | smart-aeef51d6-6d57-4f2c-bf7e-92c457f61c51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675651966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1675651966 |
| Directory | /workspace/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1932640554 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 244279997 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:42:08 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 217292 kb |
| Host | smart-6543d461-189e-4d3f-88ee-bde7fe8c090a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932640554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1932640554 |
| Directory | /workspace/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/22.rstmgr_por_stretcher.3309198402 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 168237976 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-683befc6-a5af-4a86-be2d-d44301bf51e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309198402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3309198402 |
| Directory | /workspace/22.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/22.rstmgr_reset.392073897 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1513716361 ps |
| CPU time | 5.72 seconds |
| Started | Feb 07 12:42:16 PM PST 24 |
| Finished | Feb 07 12:42:22 PM PST 24 |
| Peak memory | 200148 kb |
| Host | smart-fa59be07-80d7-4280-aa93-106b804e7d5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392073897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.392073897 |
| Directory | /workspace/22.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3161303557 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 173402818 ps |
| CPU time | 1.17 seconds |
| Started | Feb 07 12:41:50 PM PST 24 |
| Finished | Feb 07 12:41:52 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-75c9d7e6-691c-4f63-928d-4f04fff959c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3161303557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3161303557 |
| Directory | /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/22.rstmgr_smoke.3109902249 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 195361297 ps |
| CPU time | 1.29 seconds |
| Started | Feb 07 12:42:15 PM PST 24 |
| Finished | Feb 07 12:42:18 PM PST 24 |
| Peak memory | 200088 kb |
| Host | smart-f9340109-e6cf-4196-8370-a8016128585a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109902249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3109902249 |
| Directory | /workspace/22.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/22.rstmgr_stress_all.1464390187 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 11519499156 ps |
| CPU time | 44.51 seconds |
| Started | Feb 07 12:42:09 PM PST 24 |
| Finished | Feb 07 12:42:55 PM PST 24 |
| Peak memory | 200272 kb |
| Host | smart-22e992a9-dd7f-44fd-832a-6382cd40adb6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464390187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1464390187 |
| Directory | /workspace/22.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sw_rst.1167354927 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 116403409 ps |
| CPU time | 1.41 seconds |
| Started | Feb 07 12:42:08 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-f547d70f-4e69-4dc7-b79c-91b2afc1c096 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167354927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1167354927 |
| Directory | /workspace/22.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3829107423 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 275706833 ps |
| CPU time | 1.46 seconds |
| Started | Feb 07 12:42:15 PM PST 24 |
| Finished | Feb 07 12:42:18 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-a0e9394f-d48e-4e66-9a2c-4910df313661 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829107423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3829107423 |
| Directory | /workspace/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/23.rstmgr_alert_test.3674554907 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 99317784 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 12:42:08 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 199576 kb |
| Host | smart-91381198-2e35-4dc8-9ff4-c0067fe21d57 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674554907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3674554907 |
| Directory | /workspace/23.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2296471929 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2369805466 ps |
| CPU time | 8.77 seconds |
| Started | Feb 07 12:42:16 PM PST 24 |
| Finished | Feb 07 12:42:26 PM PST 24 |
| Peak memory | 217132 kb |
| Host | smart-9209694f-1cc6-43f7-ae2d-30057116a3fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2296471929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2296471929 |
| Directory | /workspace/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1911531385 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 243834109 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:42:05 PM PST 24 |
| Finished | Feb 07 12:42:06 PM PST 24 |
| Peak memory | 217232 kb |
| Host | smart-5b6f0027-6646-4b57-acb8-52f46752f401 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1911531385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1911531385 |
| Directory | /workspace/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/23.rstmgr_por_stretcher.2758353526 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 88958008 ps |
| CPU time | 0.71 seconds |
| Started | Feb 07 12:42:23 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 199716 kb |
| Host | smart-c57853b1-3ba4-4ae2-a9db-97bd52b423c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758353526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2758353526 |
| Directory | /workspace/23.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/23.rstmgr_reset.554393779 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1590496112 ps |
| CPU time | 6.15 seconds |
| Started | Feb 07 12:42:08 PM PST 24 |
| Finished | Feb 07 12:42:16 PM PST 24 |
| Peak memory | 199876 kb |
| Host | smart-dcddf6e7-f69b-4491-8983-0cbeb7dba289 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=554393779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.554393779 |
| Directory | /workspace/23.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1886630890 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 97785844 ps |
| CPU time | 0.95 seconds |
| Started | Feb 07 12:42:15 PM PST 24 |
| Finished | Feb 07 12:42:17 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-ab63d308-3e43-47af-9fb0-67255937501f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886630890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1886630890 |
| Directory | /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/23.rstmgr_smoke.1297171333 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 247785697 ps |
| CPU time | 1.5 seconds |
| Started | Feb 07 12:42:18 PM PST 24 |
| Finished | Feb 07 12:42:21 PM PST 24 |
| Peak memory | 200176 kb |
| Host | smart-110c3aec-5f5f-4921-9b3a-f8b51fcd687e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297171333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1297171333 |
| Directory | /workspace/23.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/23.rstmgr_stress_all.729573152 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 359740545 ps |
| CPU time | 1.71 seconds |
| Started | Feb 07 12:42:11 PM PST 24 |
| Finished | Feb 07 12:42:14 PM PST 24 |
| Peak memory | 200212 kb |
| Host | smart-bf159007-9ed2-44ed-b0f1-e0b2ca379e6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729573152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.729573152 |
| Directory | /workspace/23.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sw_rst.3688254695 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 349200594 ps |
| CPU time | 2.04 seconds |
| Started | Feb 07 12:42:01 PM PST 24 |
| Finished | Feb 07 12:42:05 PM PST 24 |
| Peak memory | 199992 kb |
| Host | smart-2b9b0d2b-052b-4b36-966f-03aa2d4347ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688254695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3688254695 |
| Directory | /workspace/23.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1188348542 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 113483214 ps |
| CPU time | 1.01 seconds |
| Started | Feb 07 12:42:08 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 199984 kb |
| Host | smart-eb147cf0-5601-4752-97e0-dd82da8736fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188348542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1188348542 |
| Directory | /workspace/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/24.rstmgr_alert_test.912736360 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 91498360 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:42:09 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-991f1620-2955-495c-a535-2ffe536fd8cf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912736360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.912736360 |
| Directory | /workspace/24.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3735679889 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1881496214 ps |
| CPU time | 7.44 seconds |
| Started | Feb 07 12:42:09 PM PST 24 |
| Finished | Feb 07 12:42:18 PM PST 24 |
| Peak memory | 217248 kb |
| Host | smart-c527af9d-a0aa-4ddb-a282-97fc9724048e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735679889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3735679889 |
| Directory | /workspace/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3446826287 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 244784931 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:42:12 PM PST 24 |
| Finished | Feb 07 12:42:14 PM PST 24 |
| Peak memory | 217156 kb |
| Host | smart-aa736a0e-a041-40e9-b581-71d9ce1f2d50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446826287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3446826287 |
| Directory | /workspace/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/24.rstmgr_por_stretcher.3288218744 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 152328412 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:42:09 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-43119ca6-584d-4f2a-afdb-757211219cc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288218744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3288218744 |
| Directory | /workspace/24.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/24.rstmgr_reset.1594931480 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1908000354 ps |
| CPU time | 7.58 seconds |
| Started | Feb 07 12:42:09 PM PST 24 |
| Finished | Feb 07 12:42:18 PM PST 24 |
| Peak memory | 200264 kb |
| Host | smart-136738b0-9883-4c37-9909-453711293fc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594931480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1594931480 |
| Directory | /workspace/24.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.689932101 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 110533870 ps |
| CPU time | 0.97 seconds |
| Started | Feb 07 12:42:18 PM PST 24 |
| Finished | Feb 07 12:42:20 PM PST 24 |
| Peak memory | 199744 kb |
| Host | smart-0c802b35-3333-4892-a294-e514f0d38ef0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689932101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.689932101 |
| Directory | /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/24.rstmgr_smoke.2423360236 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 244327241 ps |
| CPU time | 1.55 seconds |
| Started | Feb 07 12:42:02 PM PST 24 |
| Finished | Feb 07 12:42:05 PM PST 24 |
| Peak memory | 200084 kb |
| Host | smart-fd9baffe-a813-4bb9-aa01-a4c920678069 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423360236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2423360236 |
| Directory | /workspace/24.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/24.rstmgr_stress_all.1023648057 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 5612499149 ps |
| CPU time | 23.62 seconds |
| Started | Feb 07 12:42:21 PM PST 24 |
| Finished | Feb 07 12:42:46 PM PST 24 |
| Peak memory | 200272 kb |
| Host | smart-e64ec19c-f565-4c6b-898e-d111a68901b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023648057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1023648057 |
| Directory | /workspace/24.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sw_rst.2013650980 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 257778861 ps |
| CPU time | 1.66 seconds |
| Started | Feb 07 12:42:21 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 199996 kb |
| Host | smart-03a24980-7281-48bb-93a4-684bb7c9e6c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013650980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2013650980 |
| Directory | /workspace/24.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1911172347 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 169698568 ps |
| CPU time | 1.38 seconds |
| Started | Feb 07 12:42:13 PM PST 24 |
| Finished | Feb 07 12:42:15 PM PST 24 |
| Peak memory | 200120 kb |
| Host | smart-70c8894b-aed8-4526-936d-2c63a2894d29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1911172347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1911172347 |
| Directory | /workspace/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/25.rstmgr_alert_test.3415403988 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 68537980 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:42:21 PM PST 24 |
| Finished | Feb 07 12:42:22 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-13470a65-9d04-47d6-862a-b3049840e85e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415403988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3415403988 |
| Directory | /workspace/25.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2260112128 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1231280865 ps |
| CPU time | 5.36 seconds |
| Started | Feb 07 12:42:17 PM PST 24 |
| Finished | Feb 07 12:42:23 PM PST 24 |
| Peak memory | 229640 kb |
| Host | smart-8395077a-7a5d-4f0f-9efc-22a099ece7b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260112128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2260112128 |
| Directory | /workspace/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1006457570 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 243208302 ps |
| CPU time | 1.08 seconds |
| Started | Feb 07 12:42:14 PM PST 24 |
| Finished | Feb 07 12:42:16 PM PST 24 |
| Peak memory | 217252 kb |
| Host | smart-35280783-0d19-45d6-87d2-10b2fdc61984 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006457570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1006457570 |
| Directory | /workspace/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/25.rstmgr_por_stretcher.1257822561 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 225615701 ps |
| CPU time | 0.98 seconds |
| Started | Feb 07 12:42:09 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 199900 kb |
| Host | smart-c8508640-ac13-46a5-b0f5-1167d24d2679 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257822561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1257822561 |
| Directory | /workspace/25.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/25.rstmgr_reset.653824639 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1590075750 ps |
| CPU time | 6.16 seconds |
| Started | Feb 07 12:42:07 PM PST 24 |
| Finished | Feb 07 12:42:14 PM PST 24 |
| Peak memory | 200216 kb |
| Host | smart-5a2660a2-5129-4822-992e-f4cba1b86805 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653824639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.653824639 |
| Directory | /workspace/25.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1566912255 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 94946264 ps |
| CPU time | 0.97 seconds |
| Started | Feb 07 12:42:04 PM PST 24 |
| Finished | Feb 07 12:42:06 PM PST 24 |
| Peak memory | 199976 kb |
| Host | smart-5aeb2f5d-c069-4340-abd3-0d758135f647 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566912255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1566912255 |
| Directory | /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/25.rstmgr_smoke.2276094680 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 232939350 ps |
| CPU time | 1.55 seconds |
| Started | Feb 07 12:42:12 PM PST 24 |
| Finished | Feb 07 12:42:15 PM PST 24 |
| Peak memory | 199964 kb |
| Host | smart-3401c88d-e881-488c-bf4a-f40f4cbbc1a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276094680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2276094680 |
| Directory | /workspace/25.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/25.rstmgr_stress_all.1700844153 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 7400625981 ps |
| CPU time | 30.85 seconds |
| Started | Feb 07 12:42:14 PM PST 24 |
| Finished | Feb 07 12:42:45 PM PST 24 |
| Peak memory | 200148 kb |
| Host | smart-c67803c8-b6ae-4b65-9bda-5a3a9c017210 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700844153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1700844153 |
| Directory | /workspace/25.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sw_rst.2724309763 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 127573899 ps |
| CPU time | 1.56 seconds |
| Started | Feb 07 12:42:11 PM PST 24 |
| Finished | Feb 07 12:42:14 PM PST 24 |
| Peak memory | 200084 kb |
| Host | smart-692db354-ebdf-4e24-af26-48681344fa6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724309763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2724309763 |
| Directory | /workspace/25.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3539672863 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 84648228 ps |
| CPU time | 0.83 seconds |
| Started | Feb 07 12:42:18 PM PST 24 |
| Finished | Feb 07 12:42:20 PM PST 24 |
| Peak memory | 199980 kb |
| Host | smart-0bf92a20-d9aa-41cb-989b-a4a9c513d283 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539672863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3539672863 |
| Directory | /workspace/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/26.rstmgr_alert_test.3387193106 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 58695257 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:42:11 PM PST 24 |
| Finished | Feb 07 12:42:13 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-df2d6fe3-3c94-48a1-9276-ec95db76cee0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387193106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3387193106 |
| Directory | /workspace/26.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.233924431 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1890679890 ps |
| CPU time | 7.43 seconds |
| Started | Feb 07 12:42:16 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 217332 kb |
| Host | smart-04f42446-651e-451d-bd39-b29f027591b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233924431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.233924431 |
| Directory | /workspace/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3368400225 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 243330984 ps |
| CPU time | 1.14 seconds |
| Started | Feb 07 12:42:08 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 217232 kb |
| Host | smart-abd7dca5-2841-414f-9ad6-88f899685fa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368400225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3368400225 |
| Directory | /workspace/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/26.rstmgr_por_stretcher.3532165448 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 165039523 ps |
| CPU time | 0.84 seconds |
| Started | Feb 07 12:42:07 PM PST 24 |
| Finished | Feb 07 12:42:10 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-7d8f1c9d-fd7a-4e93-8b7f-c5f4629397b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532165448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3532165448 |
| Directory | /workspace/26.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/26.rstmgr_reset.2872917667 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1212325309 ps |
| CPU time | 4.69 seconds |
| Started | Feb 07 12:42:16 PM PST 24 |
| Finished | Feb 07 12:42:21 PM PST 24 |
| Peak memory | 200292 kb |
| Host | smart-846b6e21-8a3b-4326-a523-1d0581dfc369 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872917667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2872917667 |
| Directory | /workspace/26.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2099404200 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 109163618 ps |
| CPU time | 0.99 seconds |
| Started | Feb 07 12:42:18 PM PST 24 |
| Finished | Feb 07 12:42:20 PM PST 24 |
| Peak memory | 199700 kb |
| Host | smart-5d9da0ea-1c9c-4b2d-a239-d488c0a6bc2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099404200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2099404200 |
| Directory | /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/26.rstmgr_smoke.3718355587 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 119779328 ps |
| CPU time | 1.18 seconds |
| Started | Feb 07 12:42:14 PM PST 24 |
| Finished | Feb 07 12:42:16 PM PST 24 |
| Peak memory | 200080 kb |
| Host | smart-5d2eac0b-7d01-4597-aa4c-b6804b2b0d37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718355587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3718355587 |
| Directory | /workspace/26.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/26.rstmgr_stress_all.940163077 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4649702163 ps |
| CPU time | 20.85 seconds |
| Started | Feb 07 12:42:23 PM PST 24 |
| Finished | Feb 07 12:42:45 PM PST 24 |
| Peak memory | 200208 kb |
| Host | smart-fb9b7882-86ea-4254-894f-a8f30975392d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940163077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.940163077 |
| Directory | /workspace/26.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sw_rst.4034320570 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 268907265 ps |
| CPU time | 1.87 seconds |
| Started | Feb 07 12:42:16 PM PST 24 |
| Finished | Feb 07 12:42:19 PM PST 24 |
| Peak memory | 200068 kb |
| Host | smart-6b980293-7329-4926-980f-037f3cfeb2d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4034320570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4034320570 |
| Directory | /workspace/26.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1686447245 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 100943467 ps |
| CPU time | 0.86 seconds |
| Started | Feb 07 12:42:18 PM PST 24 |
| Finished | Feb 07 12:42:20 PM PST 24 |
| Peak memory | 199976 kb |
| Host | smart-c42a9331-6cea-4c2f-88d8-eca2b5eceb16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686447245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1686447245 |
| Directory | /workspace/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/27.rstmgr_alert_test.1127886771 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 81911549 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 12:42:14 PM PST 24 |
| Finished | Feb 07 12:42:16 PM PST 24 |
| Peak memory | 199908 kb |
| Host | smart-f27a8b1f-b7be-456f-898d-d26bfec3a3ab |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127886771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1127886771 |
| Directory | /workspace/27.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.4090460402 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1225490321 ps |
| CPU time | 5.83 seconds |
| Started | Feb 07 12:42:05 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 221372 kb |
| Host | smart-5deee0c4-25c5-4b43-af34-efb9186413d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090460402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.4090460402 |
| Directory | /workspace/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.432104479 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 243775084 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:42:12 PM PST 24 |
| Finished | Feb 07 12:42:14 PM PST 24 |
| Peak memory | 217264 kb |
| Host | smart-647d6eb9-4f51-46ab-9898-241b03420155 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432104479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.432104479 |
| Directory | /workspace/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/27.rstmgr_por_stretcher.1271389682 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 158279117 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 12:42:10 PM PST 24 |
| Finished | Feb 07 12:42:13 PM PST 24 |
| Peak memory | 199900 kb |
| Host | smart-a0e9ef29-7cb4-470b-99b9-db2ac4ce646b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1271389682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1271389682 |
| Directory | /workspace/27.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/27.rstmgr_reset.2533903819 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1287382325 ps |
| CPU time | 5.02 seconds |
| Started | Feb 07 12:42:16 PM PST 24 |
| Finished | Feb 07 12:42:22 PM PST 24 |
| Peak memory | 200100 kb |
| Host | smart-63cec178-4900-4bb5-8cd0-334982c41a6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533903819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2533903819 |
| Directory | /workspace/27.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2024081688 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 101951012 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:42:10 PM PST 24 |
| Finished | Feb 07 12:42:13 PM PST 24 |
| Peak memory | 199988 kb |
| Host | smart-7c2edaa8-383a-4c1b-a755-31c06a436c34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024081688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2024081688 |
| Directory | /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/27.rstmgr_smoke.366976506 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 112192895 ps |
| CPU time | 1.21 seconds |
| Started | Feb 07 12:42:18 PM PST 24 |
| Finished | Feb 07 12:42:20 PM PST 24 |
| Peak memory | 200084 kb |
| Host | smart-49a903ab-014d-4b38-8198-5f5d817d9aa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366976506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.366976506 |
| Directory | /workspace/27.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/27.rstmgr_stress_all.76240423 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3038843512 ps |
| CPU time | 11.58 seconds |
| Started | Feb 07 12:42:18 PM PST 24 |
| Finished | Feb 07 12:42:30 PM PST 24 |
| Peak memory | 200300 kb |
| Host | smart-997bc386-b24c-4ba0-8b40-1898c247fb94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76240423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.76240423 |
| Directory | /workspace/27.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sw_rst.3018658387 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 124287214 ps |
| CPU time | 1.48 seconds |
| Started | Feb 07 12:42:07 PM PST 24 |
| Finished | Feb 07 12:42:09 PM PST 24 |
| Peak memory | 200020 kb |
| Host | smart-2141e2dc-c617-4b0d-83ef-63a5a005a596 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018658387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3018658387 |
| Directory | /workspace/27.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2554924578 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 234789632 ps |
| CPU time | 1.28 seconds |
| Started | Feb 07 12:42:15 PM PST 24 |
| Finished | Feb 07 12:42:17 PM PST 24 |
| Peak memory | 199888 kb |
| Host | smart-180c1a96-5bda-4e90-af9f-60d44165c26c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554924578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2554924578 |
| Directory | /workspace/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/28.rstmgr_alert_test.3452125018 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 68901456 ps |
| CPU time | 0.72 seconds |
| Started | Feb 07 12:42:25 PM PST 24 |
| Finished | Feb 07 12:42:28 PM PST 24 |
| Peak memory | 199876 kb |
| Host | smart-d095eb4f-c3d9-4d18-ba2f-eae10b479cfa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452125018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3452125018 |
| Directory | /workspace/28.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4061123914 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1237157761 ps |
| CPU time | 5.59 seconds |
| Started | Feb 07 12:42:20 PM PST 24 |
| Finished | Feb 07 12:42:27 PM PST 24 |
| Peak memory | 216752 kb |
| Host | smart-2c3672ae-944b-4e41-9110-bf8eba7bd2bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061123914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4061123914 |
| Directory | /workspace/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2933827335 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 246125853 ps |
| CPU time | 1.03 seconds |
| Started | Feb 07 12:42:19 PM PST 24 |
| Finished | Feb 07 12:42:21 PM PST 24 |
| Peak memory | 217284 kb |
| Host | smart-eee31d5a-1f59-48b1-a6cc-bcfb913829f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933827335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2933827335 |
| Directory | /workspace/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/28.rstmgr_por_stretcher.3908346137 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 157190423 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:42:21 PM PST 24 |
| Finished | Feb 07 12:42:23 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-a4447032-9fa7-4936-8580-53e2c326c466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908346137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3908346137 |
| Directory | /workspace/28.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/28.rstmgr_reset.294669659 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1593957211 ps |
| CPU time | 6.69 seconds |
| Started | Feb 07 12:42:12 PM PST 24 |
| Finished | Feb 07 12:42:20 PM PST 24 |
| Peak memory | 200324 kb |
| Host | smart-d6369c8f-d901-4e74-83a7-04a77baa9e2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294669659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.294669659 |
| Directory | /workspace/28.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.288237313 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 151915099 ps |
| CPU time | 1.06 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-bc81dfa3-786c-4a7c-8d4e-f4369fde3601 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288237313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.288237313 |
| Directory | /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/28.rstmgr_smoke.869862836 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 228406161 ps |
| CPU time | 1.39 seconds |
| Started | Feb 07 12:42:14 PM PST 24 |
| Finished | Feb 07 12:42:16 PM PST 24 |
| Peak memory | 200048 kb |
| Host | smart-def790cd-d835-4ce4-8f75-d9312fc52fc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=869862836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.869862836 |
| Directory | /workspace/28.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/28.rstmgr_stress_all.4292486157 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1282699278 ps |
| CPU time | 5.61 seconds |
| Started | Feb 07 12:42:25 PM PST 24 |
| Finished | Feb 07 12:42:31 PM PST 24 |
| Peak memory | 200196 kb |
| Host | smart-72a68a45-f7a6-4090-bc99-84c00b3e975a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292486157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.4292486157 |
| Directory | /workspace/28.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sw_rst.178287493 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 125321250 ps |
| CPU time | 1.45 seconds |
| Started | Feb 07 12:42:14 PM PST 24 |
| Finished | Feb 07 12:42:16 PM PST 24 |
| Peak memory | 200048 kb |
| Host | smart-6f1548ad-071f-45b6-b737-7e421214df4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178287493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.178287493 |
| Directory | /workspace/28.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3085953518 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 158280846 ps |
| CPU time | 1.17 seconds |
| Started | Feb 07 12:42:33 PM PST 24 |
| Finished | Feb 07 12:42:35 PM PST 24 |
| Peak memory | 199976 kb |
| Host | smart-a8c9ad55-2d3b-4cd8-949a-f6fdc82b02ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085953518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3085953518 |
| Directory | /workspace/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/29.rstmgr_alert_test.2180961364 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 70858523 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:42:26 PM PST 24 |
| Finished | Feb 07 12:42:28 PM PST 24 |
| Peak memory | 199864 kb |
| Host | smart-f14cc9c4-1528-4069-9d9c-79be8909537d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180961364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2180961364 |
| Directory | /workspace/29.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.4156638288 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 243874661 ps |
| CPU time | 1.07 seconds |
| Started | Feb 07 12:42:25 PM PST 24 |
| Finished | Feb 07 12:42:27 PM PST 24 |
| Peak memory | 217144 kb |
| Host | smart-04728217-9426-4963-b370-f28c8466cb27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156638288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.4156638288 |
| Directory | /workspace/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/29.rstmgr_por_stretcher.1893377930 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 207408004 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 12:42:28 PM PST 24 |
| Finished | Feb 07 12:42:30 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-10b68e3c-2344-4b9b-935f-3eea211f7b46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1893377930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1893377930 |
| Directory | /workspace/29.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/29.rstmgr_reset.1978885660 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1530783346 ps |
| CPU time | 5.3 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:37 PM PST 24 |
| Peak memory | 200144 kb |
| Host | smart-efd0cfd0-39bb-4e38-83ae-6648912a1cda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978885660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1978885660 |
| Directory | /workspace/29.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4014812735 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 185250327 ps |
| CPU time | 1.18 seconds |
| Started | Feb 07 12:42:29 PM PST 24 |
| Finished | Feb 07 12:42:32 PM PST 24 |
| Peak memory | 199828 kb |
| Host | smart-c15e7414-3a75-4bcc-98ed-0b6fbc54601e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014812735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4014812735 |
| Directory | /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/29.rstmgr_smoke.2850576937 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 251662059 ps |
| CPU time | 1.39 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-337df74b-820f-434b-8d6b-b0ad2a81cc6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2850576937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2850576937 |
| Directory | /workspace/29.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/29.rstmgr_stress_all.171025467 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2438375590 ps |
| CPU time | 9.57 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:33 PM PST 24 |
| Peak memory | 200236 kb |
| Host | smart-837da351-cd78-4bed-acd7-229468a40384 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171025467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.171025467 |
| Directory | /workspace/29.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sw_rst.2586687087 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 135573018 ps |
| CPU time | 1.57 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 199952 kb |
| Host | smart-47486a66-6466-4e9e-bc7a-a43446c1d5c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586687087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2586687087 |
| Directory | /workspace/29.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.91133144 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 233747971 ps |
| CPU time | 1.33 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 199884 kb |
| Host | smart-fdabd094-50fe-4445-9f4b-27741f17e735 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91133144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.91133144 |
| Directory | /workspace/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/3.rstmgr_alert_test.251342571 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 62449942 ps |
| CPU time | 0.72 seconds |
| Started | Feb 07 12:41:13 PM PST 24 |
| Finished | Feb 07 12:41:15 PM PST 24 |
| Peak memory | 199716 kb |
| Host | smart-abfd78f5-9795-43db-b88f-881520177363 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251342571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.251342571 |
| Directory | /workspace/3.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.754870269 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2366086919 ps |
| CPU time | 8.64 seconds |
| Started | Feb 07 12:41:16 PM PST 24 |
| Finished | Feb 07 12:41:25 PM PST 24 |
| Peak memory | 217812 kb |
| Host | smart-9198752c-01ac-4be7-b4e7-5a91d843b978 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754870269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.754870269 |
| Directory | /workspace/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3929529173 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 243791815 ps |
| CPU time | 1.07 seconds |
| Started | Feb 07 12:41:13 PM PST 24 |
| Finished | Feb 07 12:41:15 PM PST 24 |
| Peak memory | 217168 kb |
| Host | smart-f7dd3fdd-a8b1-49b7-8c0c-2677f79d4366 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929529173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3929529173 |
| Directory | /workspace/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/3.rstmgr_por_stretcher.2497809958 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 175958610 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:41:15 PM PST 24 |
| Finished | Feb 07 12:41:17 PM PST 24 |
| Peak memory | 199704 kb |
| Host | smart-bc9b5151-e941-46cf-82a4-8866a3b5a761 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497809958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2497809958 |
| Directory | /workspace/3.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/3.rstmgr_reset.3208153269 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1658754612 ps |
| CPU time | 6.28 seconds |
| Started | Feb 07 12:41:06 PM PST 24 |
| Finished | Feb 07 12:41:13 PM PST 24 |
| Peak memory | 200112 kb |
| Host | smart-f203b33a-b5ec-451e-bf80-e83d0b9fdced |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208153269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3208153269 |
| Directory | /workspace/3.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sec_cm.880700598 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 8286808264 ps |
| CPU time | 16.82 seconds |
| Started | Feb 07 12:41:09 PM PST 24 |
| Finished | Feb 07 12:41:27 PM PST 24 |
| Peak memory | 217700 kb |
| Host | smart-b897796a-0682-44a8-9728-b38249fa5183 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880700598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.880700598 |
| Directory | /workspace/3.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3940189534 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 115281922 ps |
| CPU time | 1.01 seconds |
| Started | Feb 07 12:41:08 PM PST 24 |
| Finished | Feb 07 12:41:10 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-6538a450-9668-4630-9d4f-34fc6a6ba3e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940189534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3940189534 |
| Directory | /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/3.rstmgr_smoke.811948859 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 185617836 ps |
| CPU time | 1.29 seconds |
| Started | Feb 07 12:41:16 PM PST 24 |
| Finished | Feb 07 12:41:19 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-c20839e2-86c7-4206-a761-8434862e2f31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811948859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.811948859 |
| Directory | /workspace/3.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/3.rstmgr_stress_all.1557476780 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3834262102 ps |
| CPU time | 17.27 seconds |
| Started | Feb 07 12:41:13 PM PST 24 |
| Finished | Feb 07 12:41:32 PM PST 24 |
| Peak memory | 200220 kb |
| Host | smart-f936604b-94eb-48bb-a33b-ffa34126e558 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557476780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1557476780 |
| Directory | /workspace/3.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sw_rst.4039865693 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 124414556 ps |
| CPU time | 1.59 seconds |
| Started | Feb 07 12:41:07 PM PST 24 |
| Finished | Feb 07 12:41:10 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-613d91bc-c49e-47eb-927b-ab1a113e7892 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4039865693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4039865693 |
| Directory | /workspace/3.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1112345887 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 281319472 ps |
| CPU time | 1.47 seconds |
| Started | Feb 07 12:41:12 PM PST 24 |
| Finished | Feb 07 12:41:15 PM PST 24 |
| Peak memory | 199540 kb |
| Host | smart-ca39e392-cb9e-42eb-b521-86e4641b31d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112345887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1112345887 |
| Directory | /workspace/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/30.rstmgr_alert_test.928798741 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 76789517 ps |
| CPU time | 0.77 seconds |
| Started | Feb 07 12:42:23 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 199720 kb |
| Host | smart-ab08ccfe-c014-4cd5-b8aa-8221ad55ed61 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928798741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.928798741 |
| Directory | /workspace/30.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1697206184 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2366219121 ps |
| CPU time | 9.08 seconds |
| Started | Feb 07 12:42:27 PM PST 24 |
| Finished | Feb 07 12:42:37 PM PST 24 |
| Peak memory | 217872 kb |
| Host | smart-7e49f724-fe95-4f9c-a322-87baf9bb6d8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697206184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1697206184 |
| Directory | /workspace/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2940003432 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 244457222 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:42:27 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 217236 kb |
| Host | smart-a6783cc7-41ec-4f6c-8eee-bb32e424493b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940003432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2940003432 |
| Directory | /workspace/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/30.rstmgr_por_stretcher.773834988 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 90652551 ps |
| CPU time | 0.71 seconds |
| Started | Feb 07 12:42:17 PM PST 24 |
| Finished | Feb 07 12:42:19 PM PST 24 |
| Peak memory | 199720 kb |
| Host | smart-d982bfde-15a7-4b3c-9706-c89ddf33675d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773834988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.773834988 |
| Directory | /workspace/30.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/30.rstmgr_reset.2002245828 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1093924124 ps |
| CPU time | 4.9 seconds |
| Started | Feb 07 12:42:25 PM PST 24 |
| Finished | Feb 07 12:42:31 PM PST 24 |
| Peak memory | 200116 kb |
| Host | smart-b1f1a634-9fd5-4c65-a519-91544770a65f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002245828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2002245828 |
| Directory | /workspace/30.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.490727086 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 102736862 ps |
| CPU time | 0.89 seconds |
| Started | Feb 07 12:42:24 PM PST 24 |
| Finished | Feb 07 12:42:26 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-f49128c5-850f-4efd-838e-68b5bc75e894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490727086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.490727086 |
| Directory | /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/30.rstmgr_smoke.3964604123 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 122071417 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 12:42:27 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 199744 kb |
| Host | smart-5de8ef97-a7ad-4451-81f4-5abe639f51b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964604123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3964604123 |
| Directory | /workspace/30.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/30.rstmgr_stress_all.566685583 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 11603623815 ps |
| CPU time | 37.51 seconds |
| Started | Feb 07 12:42:25 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 200264 kb |
| Host | smart-d68f98d3-86a0-4e7a-a343-b230bcfdfda5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566685583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.566685583 |
| Directory | /workspace/30.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sw_rst.2899617576 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 443488232 ps |
| CPU time | 2.4 seconds |
| Started | Feb 07 12:42:29 PM PST 24 |
| Finished | Feb 07 12:42:33 PM PST 24 |
| Peak memory | 200040 kb |
| Host | smart-72477d4a-372c-4e00-87a8-8b5c222ac26b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899617576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2899617576 |
| Directory | /workspace/30.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3661512887 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 118439482 ps |
| CPU time | 0.97 seconds |
| Started | Feb 07 12:42:26 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 199884 kb |
| Host | smart-74413b82-961f-42dc-a48e-fd901e7745c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3661512887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3661512887 |
| Directory | /workspace/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/31.rstmgr_alert_test.4037737079 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 73233491 ps |
| CPU time | 0.7 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-fdc2435b-4ca6-4687-9896-69d37ecbef84 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037737079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.4037737079 |
| Directory | /workspace/31.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2330083814 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1216297920 ps |
| CPU time | 5.45 seconds |
| Started | Feb 07 12:42:20 PM PST 24 |
| Finished | Feb 07 12:42:26 PM PST 24 |
| Peak memory | 218372 kb |
| Host | smart-798b7d21-0762-406d-b4e5-761bfd33b7e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330083814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2330083814 |
| Directory | /workspace/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.447877689 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 248533660 ps |
| CPU time | 1.02 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:33 PM PST 24 |
| Peak memory | 217288 kb |
| Host | smart-9dddda9c-4711-46f7-a15a-abd1d1543e55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447877689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.447877689 |
| Directory | /workspace/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/31.rstmgr_por_stretcher.3641959035 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 208280276 ps |
| CPU time | 0.91 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:33 PM PST 24 |
| Peak memory | 199752 kb |
| Host | smart-a2e15f57-310b-43e2-b803-9a06c0549365 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641959035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3641959035 |
| Directory | /workspace/31.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/31.rstmgr_reset.4049981255 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1865756480 ps |
| CPU time | 7.03 seconds |
| Started | Feb 07 12:42:19 PM PST 24 |
| Finished | Feb 07 12:42:26 PM PST 24 |
| Peak memory | 200020 kb |
| Host | smart-9cfa5f9a-8958-4c4c-b1a4-699f97a1a13a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4049981255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4049981255 |
| Directory | /workspace/31.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2092572855 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 140449119 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:42:19 PM PST 24 |
| Finished | Feb 07 12:42:21 PM PST 24 |
| Peak memory | 200028 kb |
| Host | smart-0293331b-dbb7-41d4-9c7a-ec70b6ace190 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092572855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2092572855 |
| Directory | /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/31.rstmgr_smoke.641529806 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 192192123 ps |
| CPU time | 1.35 seconds |
| Started | Feb 07 12:42:13 PM PST 24 |
| Finished | Feb 07 12:42:15 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-e404bda3-487b-4ddd-bc1d-720f70799ba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641529806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.641529806 |
| Directory | /workspace/31.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/31.rstmgr_stress_all.1158138729 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 202482300 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 199944 kb |
| Host | smart-47b56537-8dde-4efe-a2b2-0b4f90ccaae2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158138729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1158138729 |
| Directory | /workspace/31.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sw_rst.1359741506 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 260580016 ps |
| CPU time | 1.87 seconds |
| Started | Feb 07 12:42:24 PM PST 24 |
| Finished | Feb 07 12:42:27 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-05bd7367-6fdf-46e2-91db-1bf3f3f93f15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1359741506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1359741506 |
| Directory | /workspace/31.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2606268175 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 110912472 ps |
| CPU time | 0.84 seconds |
| Started | Feb 07 12:42:14 PM PST 24 |
| Finished | Feb 07 12:42:15 PM PST 24 |
| Peak memory | 199888 kb |
| Host | smart-ff6a11e1-5cae-456a-be42-fe052ccdeca7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606268175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2606268175 |
| Directory | /workspace/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/32.rstmgr_alert_test.1741787731 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 95949425 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-8893c45f-67db-476f-a877-fc16fe9aa3f4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741787731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1741787731 |
| Directory | /workspace/32.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.543638160 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1233574288 ps |
| CPU time | 5.48 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:28 PM PST 24 |
| Peak memory | 217276 kb |
| Host | smart-11084e22-1245-4d15-b838-37bcd8758799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543638160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.543638160 |
| Directory | /workspace/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3340790315 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 245155600 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:42:20 PM PST 24 |
| Finished | Feb 07 12:42:22 PM PST 24 |
| Peak memory | 217280 kb |
| Host | smart-9224b2a5-2c88-45f5-a703-c65ef7f2c3c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340790315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3340790315 |
| Directory | /workspace/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/32.rstmgr_por_stretcher.3896734311 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 132610376 ps |
| CPU time | 0.74 seconds |
| Started | Feb 07 12:42:21 PM PST 24 |
| Finished | Feb 07 12:42:23 PM PST 24 |
| Peak memory | 199812 kb |
| Host | smart-4e242525-e9ee-4975-a02f-2ea030e8c00c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896734311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3896734311 |
| Directory | /workspace/32.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/32.rstmgr_reset.438105069 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1533954819 ps |
| CPU time | 5.79 seconds |
| Started | Feb 07 12:42:21 PM PST 24 |
| Finished | Feb 07 12:42:28 PM PST 24 |
| Peak memory | 200116 kb |
| Host | smart-270765d0-90b0-4b41-9cc3-eb243908bbab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438105069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.438105069 |
| Directory | /workspace/32.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.601032616 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 105326045 ps |
| CPU time | 1.01 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 199952 kb |
| Host | smart-6f07d014-5476-4fcb-8eab-62a27ba2d762 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601032616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.601032616 |
| Directory | /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/32.rstmgr_smoke.3371058403 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 127489121 ps |
| CPU time | 1.08 seconds |
| Started | Feb 07 12:42:24 PM PST 24 |
| Finished | Feb 07 12:42:27 PM PST 24 |
| Peak memory | 200184 kb |
| Host | smart-367bfe4c-99dc-4941-8ebc-07c972113276 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371058403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3371058403 |
| Directory | /workspace/32.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/32.rstmgr_stress_all.1589751855 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4545021320 ps |
| CPU time | 16.23 seconds |
| Started | Feb 07 12:42:32 PM PST 24 |
| Finished | Feb 07 12:42:50 PM PST 24 |
| Peak memory | 200264 kb |
| Host | smart-7efe52ea-65b1-408f-8faf-2a414326b98b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589751855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1589751855 |
| Directory | /workspace/32.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sw_rst.1574163531 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 262526189 ps |
| CPU time | 1.84 seconds |
| Started | Feb 07 12:42:32 PM PST 24 |
| Finished | Feb 07 12:42:35 PM PST 24 |
| Peak memory | 200044 kb |
| Host | smart-d84cb113-d185-4033-bb1c-979df37fb108 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574163531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1574163531 |
| Directory | /workspace/32.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1919359750 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 141361370 ps |
| CPU time | 1.24 seconds |
| Started | Feb 07 12:42:20 PM PST 24 |
| Finished | Feb 07 12:42:23 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-ad72d653-070f-42cd-b6ba-dc218e5b4e50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919359750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1919359750 |
| Directory | /workspace/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/33.rstmgr_alert_test.2455118681 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 69987612 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 199836 kb |
| Host | smart-08dd435b-7342-4f3d-85e8-cf32edcc8d53 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455118681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2455118681 |
| Directory | /workspace/33.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2488022180 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1219216242 ps |
| CPU time | 5.57 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:37 PM PST 24 |
| Peak memory | 217128 kb |
| Host | smart-f2569bde-d75f-408c-a15b-65bd33ae5189 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488022180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2488022180 |
| Directory | /workspace/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1926534768 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 244275265 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 12:42:28 PM PST 24 |
| Finished | Feb 07 12:42:31 PM PST 24 |
| Peak memory | 217324 kb |
| Host | smart-f460c425-23ec-4ec3-90e4-b6f089d421cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926534768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1926534768 |
| Directory | /workspace/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/33.rstmgr_por_stretcher.3283489410 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 162367968 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:23 PM PST 24 |
| Peak memory | 199748 kb |
| Host | smart-eb78411f-c4fd-4a59-859c-8218ce387a3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283489410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3283489410 |
| Directory | /workspace/33.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/33.rstmgr_reset.1304430293 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 982710126 ps |
| CPU time | 5.28 seconds |
| Started | Feb 07 12:42:26 PM PST 24 |
| Finished | Feb 07 12:42:32 PM PST 24 |
| Peak memory | 200248 kb |
| Host | smart-387d49e0-4b4c-4613-b9ec-961381e898e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304430293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1304430293 |
| Directory | /workspace/33.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2157319488 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 105523249 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-f9778cf9-8af9-4e95-bf13-4e3e299b6274 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157319488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2157319488 |
| Directory | /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/33.rstmgr_smoke.3068583670 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 110535647 ps |
| CPU time | 1.15 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-15a4594b-1107-4fea-9ebb-25a174370878 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068583670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3068583670 |
| Directory | /workspace/33.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/33.rstmgr_stress_all.2169217503 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15895332520 ps |
| CPU time | 51.26 seconds |
| Started | Feb 07 12:42:28 PM PST 24 |
| Finished | Feb 07 12:43:21 PM PST 24 |
| Peak memory | 200304 kb |
| Host | smart-63da2b25-95db-40f0-bf1a-f84b434b5052 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169217503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2169217503 |
| Directory | /workspace/33.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sw_rst.3616003907 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 125871668 ps |
| CPU time | 1.58 seconds |
| Started | Feb 07 12:42:15 PM PST 24 |
| Finished | Feb 07 12:42:18 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-437b7f6e-d351-4548-8ea2-e0d7bc86ad63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3616003907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3616003907 |
| Directory | /workspace/33.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3700458939 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 90118105 ps |
| CPU time | 0.93 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 199884 kb |
| Host | smart-841afecb-d964-44ad-bb2e-5bf834e38bf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700458939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3700458939 |
| Directory | /workspace/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/34.rstmgr_alert_test.3816429214 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 64782664 ps |
| CPU time | 0.74 seconds |
| Started | Feb 07 12:42:26 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 199872 kb |
| Host | smart-04d2b59e-3b2a-40c2-b308-88872aca609c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816429214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3816429214 |
| Directory | /workspace/34.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1204296510 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1225911283 ps |
| CPU time | 5.58 seconds |
| Started | Feb 07 12:42:19 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 217868 kb |
| Host | smart-2052a411-05f2-4b5f-95bb-5775f69e3ad1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204296510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1204296510 |
| Directory | /workspace/34.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3261857326 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 244452037 ps |
| CPU time | 1.02 seconds |
| Started | Feb 07 12:42:30 PM PST 24 |
| Finished | Feb 07 12:42:32 PM PST 24 |
| Peak memory | 217316 kb |
| Host | smart-2d104ce0-4bb5-4593-b649-061957b99bab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3261857326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3261857326 |
| Directory | /workspace/34.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/34.rstmgr_por_stretcher.1706444363 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 218986428 ps |
| CPU time | 0.95 seconds |
| Started | Feb 07 12:42:21 PM PST 24 |
| Finished | Feb 07 12:42:23 PM PST 24 |
| Peak memory | 199800 kb |
| Host | smart-1097fecb-35bb-4082-ba48-f1c7bec473c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706444363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1706444363 |
| Directory | /workspace/34.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/34.rstmgr_reset.436737854 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 724587944 ps |
| CPU time | 3.82 seconds |
| Started | Feb 07 12:42:24 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 200220 kb |
| Host | smart-85cf25eb-252d-45e1-bf0f-fead45f7d490 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436737854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.436737854 |
| Directory | /workspace/34.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3966033048 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 99078402 ps |
| CPU time | 0.92 seconds |
| Started | Feb 07 12:42:17 PM PST 24 |
| Finished | Feb 07 12:42:19 PM PST 24 |
| Peak memory | 199976 kb |
| Host | smart-5a4f0bfd-9c96-4bba-a0c7-5821c74a5898 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966033048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3966033048 |
| Directory | /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/34.rstmgr_smoke.1730469852 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 195249386 ps |
| CPU time | 1.35 seconds |
| Started | Feb 07 12:42:19 PM PST 24 |
| Finished | Feb 07 12:42:21 PM PST 24 |
| Peak memory | 200016 kb |
| Host | smart-6415b691-76d2-45a5-bade-424e502eeed8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730469852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1730469852 |
| Directory | /workspace/34.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/34.rstmgr_stress_all.2467853202 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1528505430 ps |
| CPU time | 6.64 seconds |
| Started | Feb 07 12:42:29 PM PST 24 |
| Finished | Feb 07 12:42:37 PM PST 24 |
| Peak memory | 200236 kb |
| Host | smart-5ea46a92-a7ad-4c1d-981c-57048f6b95b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467853202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2467853202 |
| Directory | /workspace/34.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sw_rst.3524357126 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 300986258 ps |
| CPU time | 2.02 seconds |
| Started | Feb 07 12:42:17 PM PST 24 |
| Finished | Feb 07 12:42:20 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-6389e580-20b5-439b-9312-31a3cb6bdc21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524357126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3524357126 |
| Directory | /workspace/34.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3934650020 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 114939840 ps |
| CPU time | 0.88 seconds |
| Started | Feb 07 12:42:28 PM PST 24 |
| Finished | Feb 07 12:42:30 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-55166464-9253-47e8-88e7-e4d7110db67b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934650020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3934650020 |
| Directory | /workspace/34.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3980254432 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1890301769 ps |
| CPU time | 6.94 seconds |
| Started | Feb 07 12:42:29 PM PST 24 |
| Finished | Feb 07 12:42:37 PM PST 24 |
| Peak memory | 220736 kb |
| Host | smart-c899aae3-1983-4a7e-89de-6eaffbab60c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980254432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3980254432 |
| Directory | /workspace/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1444108761 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 243447712 ps |
| CPU time | 1.04 seconds |
| Started | Feb 07 12:42:26 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 217276 kb |
| Host | smart-fc2c0a5e-5cf8-4099-ab9f-8a4aab6912d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1444108761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1444108761 |
| Directory | /workspace/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/35.rstmgr_por_stretcher.752379596 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 204911182 ps |
| CPU time | 0.88 seconds |
| Started | Feb 07 12:42:25 PM PST 24 |
| Finished | Feb 07 12:42:27 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-42262c69-e0ae-4a43-8e61-a4b77a5f5d50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752379596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.752379596 |
| Directory | /workspace/35.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/35.rstmgr_reset.783608953 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1508260801 ps |
| CPU time | 6.46 seconds |
| Started | Feb 07 12:42:27 PM PST 24 |
| Finished | Feb 07 12:42:35 PM PST 24 |
| Peak memory | 200124 kb |
| Host | smart-8d766e2c-a580-48c1-865b-b7c6970f7cf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783608953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.783608953 |
| Directory | /workspace/35.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.843590104 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 185360446 ps |
| CPU time | 1.18 seconds |
| Started | Feb 07 12:42:29 PM PST 24 |
| Finished | Feb 07 12:42:32 PM PST 24 |
| Peak memory | 199888 kb |
| Host | smart-436818e2-cac1-401a-a1ef-b66d1e2c955a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843590104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.843590104 |
| Directory | /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/35.rstmgr_smoke.2141963179 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 124700128 ps |
| CPU time | 1.14 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-3fb8e7ca-e518-432b-93ef-0534725e020f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141963179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2141963179 |
| Directory | /workspace/35.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/35.rstmgr_stress_all.631582762 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2769516165 ps |
| CPU time | 10.51 seconds |
| Started | Feb 07 12:42:30 PM PST 24 |
| Finished | Feb 07 12:42:42 PM PST 24 |
| Peak memory | 200292 kb |
| Host | smart-cfa6e210-1e18-490b-93f1-33da7d28d4a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631582762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.631582762 |
| Directory | /workspace/35.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sw_rst.2339152499 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 391498197 ps |
| CPU time | 2.04 seconds |
| Started | Feb 07 12:42:18 PM PST 24 |
| Finished | Feb 07 12:42:21 PM PST 24 |
| Peak memory | 200016 kb |
| Host | smart-0bd608f9-6b5a-4e43-bfa2-4517079c4ac8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2339152499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2339152499 |
| Directory | /workspace/35.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2688297351 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 64696689 ps |
| CPU time | 0.71 seconds |
| Started | Feb 07 12:42:27 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 199732 kb |
| Host | smart-a10cca74-b455-4e79-8da3-630ebd5fdfc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688297351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2688297351 |
| Directory | /workspace/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/36.rstmgr_alert_test.1636414401 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 83773971 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:42:23 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-c39f3651-58fd-4851-aadc-ebc25c466feb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636414401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1636414401 |
| Directory | /workspace/36.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1395231203 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1901668129 ps |
| CPU time | 6.98 seconds |
| Started | Feb 07 12:42:18 PM PST 24 |
| Finished | Feb 07 12:42:26 PM PST 24 |
| Peak memory | 217804 kb |
| Host | smart-1c2ca0c3-8050-4f20-8d36-6bc1958c4c44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395231203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1395231203 |
| Directory | /workspace/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1910907445 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 244279833 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:42:21 PM PST 24 |
| Finished | Feb 07 12:42:23 PM PST 24 |
| Peak memory | 217280 kb |
| Host | smart-9a7e4f56-3dec-4d8d-9c27-cbdc72ae4b62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910907445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1910907445 |
| Directory | /workspace/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/36.rstmgr_por_stretcher.3652131440 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 106736754 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:42:26 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 199752 kb |
| Host | smart-b652357b-e184-4a12-a787-c2b341902402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652131440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3652131440 |
| Directory | /workspace/36.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/36.rstmgr_reset.3564624278 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 750235428 ps |
| CPU time | 3.78 seconds |
| Started | Feb 07 12:42:24 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 200224 kb |
| Host | smart-6fd089e6-bbf5-402d-9795-660db12a5d32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564624278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3564624278 |
| Directory | /workspace/36.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2685592120 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 185831432 ps |
| CPU time | 1.15 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:25 PM PST 24 |
| Peak memory | 200004 kb |
| Host | smart-21c1d4aa-b67d-4c1b-8033-809c324f1bfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685592120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2685592120 |
| Directory | /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/36.rstmgr_smoke.3179905283 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 195285162 ps |
| CPU time | 1.4 seconds |
| Started | Feb 07 12:42:19 PM PST 24 |
| Finished | Feb 07 12:42:21 PM PST 24 |
| Peak memory | 200128 kb |
| Host | smart-b2829602-49a9-493e-8c67-54371119dcbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3179905283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3179905283 |
| Directory | /workspace/36.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/36.rstmgr_stress_all.2415371624 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 3901234488 ps |
| CPU time | 17.35 seconds |
| Started | Feb 07 12:42:26 PM PST 24 |
| Finished | Feb 07 12:42:45 PM PST 24 |
| Peak memory | 200200 kb |
| Host | smart-26ae68ba-15e7-43f0-819e-fb4b3a4db36b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415371624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2415371624 |
| Directory | /workspace/36.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sw_rst.3598313179 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 311948066 ps |
| CPU time | 1.98 seconds |
| Started | Feb 07 12:42:26 PM PST 24 |
| Finished | Feb 07 12:42:30 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-c826df56-4c88-413e-b43e-3db347cf67f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598313179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3598313179 |
| Directory | /workspace/36.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1938602841 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 100458057 ps |
| CPU time | 0.9 seconds |
| Started | Feb 07 12:42:22 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 199976 kb |
| Host | smart-fbdfb036-96b0-4680-aa79-bd798dde4c68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938602841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1938602841 |
| Directory | /workspace/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/37.rstmgr_alert_test.4061961220 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 74995444 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:42:28 PM PST 24 |
| Finished | Feb 07 12:42:30 PM PST 24 |
| Peak memory | 199872 kb |
| Host | smart-7e58cc46-2069-49e2-92ce-034c86b385d9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061961220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4061961220 |
| Directory | /workspace/37.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.637271187 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1221036107 ps |
| CPU time | 5.57 seconds |
| Started | Feb 07 12:42:33 PM PST 24 |
| Finished | Feb 07 12:42:40 PM PST 24 |
| Peak memory | 221908 kb |
| Host | smart-8bcc3706-3c96-4ddf-9571-f1830fa314c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637271187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.637271187 |
| Directory | /workspace/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1203347733 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 244786621 ps |
| CPU time | 1.08 seconds |
| Started | Feb 07 12:42:46 PM PST 24 |
| Finished | Feb 07 12:42:53 PM PST 24 |
| Peak memory | 217280 kb |
| Host | smart-2ef58edd-bb5b-49b6-b119-e20b88ddc291 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1203347733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1203347733 |
| Directory | /workspace/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/37.rstmgr_por_stretcher.2403492679 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 146493364 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 12:42:26 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 199752 kb |
| Host | smart-8a0b714d-50aa-4456-9f45-327baa3d47d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403492679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2403492679 |
| Directory | /workspace/37.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/37.rstmgr_reset.433032960 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 901918070 ps |
| CPU time | 4.33 seconds |
| Started | Feb 07 12:42:27 PM PST 24 |
| Finished | Feb 07 12:42:32 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-46698850-b49e-4a64-82ec-bdaa56643271 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433032960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.433032960 |
| Directory | /workspace/37.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1110516528 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 98247874 ps |
| CPU time | 0.92 seconds |
| Started | Feb 07 12:42:29 PM PST 24 |
| Finished | Feb 07 12:42:32 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-f6ccf636-7bc9-40a3-99ce-24704d3c0f8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110516528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1110516528 |
| Directory | /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/37.rstmgr_smoke.3626661676 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 194783833 ps |
| CPU time | 1.33 seconds |
| Started | Feb 07 12:42:21 PM PST 24 |
| Finished | Feb 07 12:42:23 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-00ae5228-4052-494c-8309-3f7146371f09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626661676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3626661676 |
| Directory | /workspace/37.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/37.rstmgr_stress_all.1973329003 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1617832888 ps |
| CPU time | 5.98 seconds |
| Started | Feb 07 12:42:39 PM PST 24 |
| Finished | Feb 07 12:42:47 PM PST 24 |
| Peak memory | 200196 kb |
| Host | smart-7e916bc6-62f9-4cc0-9e44-c45962ef46fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973329003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1973329003 |
| Directory | /workspace/37.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sw_rst.3749698061 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 338574549 ps |
| CPU time | 2.34 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:34 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-c2fcf35c-3143-4dcf-8c5f-f681109b9a27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749698061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3749698061 |
| Directory | /workspace/37.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2552186217 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 121455163 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:42:30 PM PST 24 |
| Finished | Feb 07 12:42:32 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-3c51544b-f1c2-4889-8582-567aebbd58b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2552186217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2552186217 |
| Directory | /workspace/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/38.rstmgr_alert_test.2822202353 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 70870545 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:42:33 PM PST 24 |
| Finished | Feb 07 12:42:35 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-8b1f628c-7077-42dc-a754-59bf7db79abb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822202353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2822202353 |
| Directory | /workspace/38.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3054988217 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1220533994 ps |
| CPU time | 5.85 seconds |
| Started | Feb 07 12:42:27 PM PST 24 |
| Finished | Feb 07 12:42:34 PM PST 24 |
| Peak memory | 216452 kb |
| Host | smart-5515fd5d-b33c-4d95-b716-486fc4e504a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3054988217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3054988217 |
| Directory | /workspace/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3856298136 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 244538732 ps |
| CPU time | 1.06 seconds |
| Started | Feb 07 12:42:36 PM PST 24 |
| Finished | Feb 07 12:42:39 PM PST 24 |
| Peak memory | 217140 kb |
| Host | smart-785f5dec-9272-450b-861e-2c63b7eb3e26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856298136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3856298136 |
| Directory | /workspace/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/38.rstmgr_por_stretcher.2765628046 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 128831276 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:33 PM PST 24 |
| Peak memory | 199808 kb |
| Host | smart-f58546d3-36ac-4ed4-95c2-0ee29d1e75f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765628046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2765628046 |
| Directory | /workspace/38.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/38.rstmgr_reset.2577250467 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 989083137 ps |
| CPU time | 5.02 seconds |
| Started | Feb 07 12:42:36 PM PST 24 |
| Finished | Feb 07 12:42:43 PM PST 24 |
| Peak memory | 200124 kb |
| Host | smart-dc57f4ce-14af-47d7-a657-a98ffbe44448 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2577250467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2577250467 |
| Directory | /workspace/38.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2863004065 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 164908179 ps |
| CPU time | 1.22 seconds |
| Started | Feb 07 12:42:36 PM PST 24 |
| Finished | Feb 07 12:42:39 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-ef0af67a-482e-48d3-9458-c974d128571d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863004065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2863004065 |
| Directory | /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/38.rstmgr_smoke.2259876540 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 196414685 ps |
| CPU time | 1.33 seconds |
| Started | Feb 07 12:42:38 PM PST 24 |
| Finished | Feb 07 12:42:40 PM PST 24 |
| Peak memory | 200112 kb |
| Host | smart-eff08efb-0b90-460e-b44b-579f8904e9f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259876540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2259876540 |
| Directory | /workspace/38.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sw_rst.4237202376 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 121036830 ps |
| CPU time | 1.57 seconds |
| Started | Feb 07 12:42:46 PM PST 24 |
| Finished | Feb 07 12:42:54 PM PST 24 |
| Peak memory | 199980 kb |
| Host | smart-7392a510-7867-4cbb-a1f9-72f300616fa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237202376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4237202376 |
| Directory | /workspace/38.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.173028745 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 73619301 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 12:42:46 PM PST 24 |
| Finished | Feb 07 12:42:53 PM PST 24 |
| Peak memory | 199900 kb |
| Host | smart-81ddf711-76f5-4f55-b1ca-ef923bee0d42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173028745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.173028745 |
| Directory | /workspace/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/39.rstmgr_alert_test.3487443554 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 97690281 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 12:42:38 PM PST 24 |
| Finished | Feb 07 12:42:39 PM PST 24 |
| Peak memory | 199816 kb |
| Host | smart-ba2bf797-5f81-4eea-8187-d1b3f3d3401d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487443554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3487443554 |
| Directory | /workspace/39.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.964201026 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1889329279 ps |
| CPU time | 7.15 seconds |
| Started | Feb 07 12:42:45 PM PST 24 |
| Finished | Feb 07 12:42:53 PM PST 24 |
| Peak memory | 221840 kb |
| Host | smart-b16d0b0e-80c4-4233-8502-80d81bb687ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964201026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.964201026 |
| Directory | /workspace/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.640032432 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 243996896 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:42:46 PM PST 24 |
| Finished | Feb 07 12:42:53 PM PST 24 |
| Peak memory | 217300 kb |
| Host | smart-621e4573-b9e7-4751-afdc-060f18ad81f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640032432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.640032432 |
| Directory | /workspace/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/39.rstmgr_por_stretcher.88436857 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 116813667 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:33 PM PST 24 |
| Peak memory | 199820 kb |
| Host | smart-303e05c2-a014-4e8f-ab5a-1034f7a2a9e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88436857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.88436857 |
| Directory | /workspace/39.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/39.rstmgr_reset.1726992572 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1332491556 ps |
| CPU time | 6.03 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:38 PM PST 24 |
| Peak memory | 200232 kb |
| Host | smart-937932b6-3562-4899-b6a3-570a9d38dc93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726992572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1726992572 |
| Directory | /workspace/39.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3299447689 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 109480644 ps |
| CPU time | 0.97 seconds |
| Started | Feb 07 12:42:35 PM PST 24 |
| Finished | Feb 07 12:42:37 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-a1ed459d-01e3-48c0-8a23-266864b3b380 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299447689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3299447689 |
| Directory | /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/39.rstmgr_smoke.2400873958 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 195400131 ps |
| CPU time | 1.46 seconds |
| Started | Feb 07 12:42:45 PM PST 24 |
| Finished | Feb 07 12:42:48 PM PST 24 |
| Peak memory | 200048 kb |
| Host | smart-ecd9e778-07e9-4ce0-95f7-58822101386d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400873958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2400873958 |
| Directory | /workspace/39.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/39.rstmgr_stress_all.1521488056 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 4213229207 ps |
| CPU time | 14.94 seconds |
| Started | Feb 07 12:42:33 PM PST 24 |
| Finished | Feb 07 12:42:49 PM PST 24 |
| Peak memory | 200252 kb |
| Host | smart-b0c6f4ad-8453-4d90-9441-3e9566ee6a28 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521488056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1521488056 |
| Directory | /workspace/39.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sw_rst.3172101679 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 125202649 ps |
| CPU time | 1.57 seconds |
| Started | Feb 07 12:42:34 PM PST 24 |
| Finished | Feb 07 12:42:36 PM PST 24 |
| Peak memory | 199976 kb |
| Host | smart-399d0ec4-88c1-4a1c-8cbd-8c5675b0d3ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172101679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3172101679 |
| Directory | /workspace/39.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3489891876 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 163789340 ps |
| CPU time | 1.39 seconds |
| Started | Feb 07 12:42:34 PM PST 24 |
| Finished | Feb 07 12:42:36 PM PST 24 |
| Peak memory | 200212 kb |
| Host | smart-5559b866-ad78-4097-b586-fbb7c97d733e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489891876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3489891876 |
| Directory | /workspace/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/4.rstmgr_alert_test.1561619654 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 87196693 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 12:41:23 PM PST 24 |
| Finished | Feb 07 12:41:24 PM PST 24 |
| Peak memory | 199740 kb |
| Host | smart-f4f625f1-0422-4427-87f1-9bb10659d0f3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561619654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1561619654 |
| Directory | /workspace/4.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1381445019 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1227795619 ps |
| CPU time | 5.78 seconds |
| Started | Feb 07 12:41:17 PM PST 24 |
| Finished | Feb 07 12:41:23 PM PST 24 |
| Peak memory | 216708 kb |
| Host | smart-57152bf0-2421-45b0-9b05-1d578cc4bc84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1381445019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1381445019 |
| Directory | /workspace/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1224959801 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 244448047 ps |
| CPU time | 1.16 seconds |
| Started | Feb 07 12:41:21 PM PST 24 |
| Finished | Feb 07 12:41:23 PM PST 24 |
| Peak memory | 217244 kb |
| Host | smart-a2925928-be01-4799-a922-ace27973087e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224959801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1224959801 |
| Directory | /workspace/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/4.rstmgr_por_stretcher.2790841080 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 163900092 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:41:27 PM PST 24 |
| Finished | Feb 07 12:41:29 PM PST 24 |
| Peak memory | 199840 kb |
| Host | smart-c3e97b11-2855-425c-aedc-503c4796a6cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790841080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2790841080 |
| Directory | /workspace/4.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/4.rstmgr_reset.4290057617 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 903540469 ps |
| CPU time | 4.3 seconds |
| Started | Feb 07 12:41:17 PM PST 24 |
| Finished | Feb 07 12:41:22 PM PST 24 |
| Peak memory | 200124 kb |
| Host | smart-28e7204a-9e9c-4657-98cf-5e26fa3f11ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290057617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4290057617 |
| Directory | /workspace/4.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sec_cm.3047133499 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 8395314044 ps |
| CPU time | 12.98 seconds |
| Started | Feb 07 12:41:19 PM PST 24 |
| Finished | Feb 07 12:41:33 PM PST 24 |
| Peak memory | 220916 kb |
| Host | smart-be6766f2-0e77-463b-8447-111e8a0521af |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047133499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3047133499 |
| Directory | /workspace/4.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3725610283 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 182574033 ps |
| CPU time | 1.19 seconds |
| Started | Feb 07 12:41:18 PM PST 24 |
| Finished | Feb 07 12:41:20 PM PST 24 |
| Peak memory | 199972 kb |
| Host | smart-55025ef9-59d8-461b-83b6-bc06d22c84ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725610283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3725610283 |
| Directory | /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/4.rstmgr_smoke.2186153090 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 114443012 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 12:41:17 PM PST 24 |
| Finished | Feb 07 12:41:19 PM PST 24 |
| Peak memory | 200028 kb |
| Host | smart-ebe5c0a0-109f-4462-9ae9-99f8fe4d5d25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186153090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2186153090 |
| Directory | /workspace/4.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/4.rstmgr_stress_all.1692375417 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1841043374 ps |
| CPU time | 8.19 seconds |
| Started | Feb 07 12:41:17 PM PST 24 |
| Finished | Feb 07 12:41:26 PM PST 24 |
| Peak memory | 200144 kb |
| Host | smart-c4d5f9fb-6468-4ca9-a12f-dcca928877e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692375417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1692375417 |
| Directory | /workspace/4.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sw_rst.1333078910 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 307619937 ps |
| CPU time | 2.07 seconds |
| Started | Feb 07 12:41:16 PM PST 24 |
| Finished | Feb 07 12:41:19 PM PST 24 |
| Peak memory | 199952 kb |
| Host | smart-18755dd3-cdba-4f60-bc30-c9f35eeaeb56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1333078910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1333078910 |
| Directory | /workspace/4.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2561208892 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 217415259 ps |
| CPU time | 1.34 seconds |
| Started | Feb 07 12:41:26 PM PST 24 |
| Finished | Feb 07 12:41:28 PM PST 24 |
| Peak memory | 199952 kb |
| Host | smart-92c24471-91bd-47ee-9eb1-1b916ee34f2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2561208892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2561208892 |
| Directory | /workspace/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/40.rstmgr_alert_test.733513496 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 63331779 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:42:33 PM PST 24 |
| Finished | Feb 07 12:42:35 PM PST 24 |
| Peak memory | 199864 kb |
| Host | smart-d6ebebc5-145b-4e8a-b5cb-fe4ff9a5ca1d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733513496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.733513496 |
| Directory | /workspace/40.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2021991069 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1225906349 ps |
| CPU time | 6.06 seconds |
| Started | Feb 07 12:42:37 PM PST 24 |
| Finished | Feb 07 12:42:44 PM PST 24 |
| Peak memory | 221928 kb |
| Host | smart-32377b92-8173-47d2-9752-2f554bb88d80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2021991069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2021991069 |
| Directory | /workspace/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3881954577 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 244617161 ps |
| CPU time | 1.18 seconds |
| Started | Feb 07 12:42:45 PM PST 24 |
| Finished | Feb 07 12:42:48 PM PST 24 |
| Peak memory | 216868 kb |
| Host | smart-139ce342-1480-4e08-8d9c-3b195ca43b98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881954577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3881954577 |
| Directory | /workspace/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/40.rstmgr_por_stretcher.983323559 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 127280860 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:42:34 PM PST 24 |
| Finished | Feb 07 12:42:35 PM PST 24 |
| Peak memory | 199776 kb |
| Host | smart-329d4286-e93e-41b7-bbf3-0afd7313eda4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983323559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.983323559 |
| Directory | /workspace/40.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/40.rstmgr_reset.852758007 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1694702092 ps |
| CPU time | 5.89 seconds |
| Started | Feb 07 12:42:34 PM PST 24 |
| Finished | Feb 07 12:42:41 PM PST 24 |
| Peak memory | 200168 kb |
| Host | smart-60a0613c-6366-4008-8370-01da54cab647 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852758007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.852758007 |
| Directory | /workspace/40.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1927293032 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 186691695 ps |
| CPU time | 1.15 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:34 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-ead14ca7-87fd-473a-8180-b51e66248785 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927293032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1927293032 |
| Directory | /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/40.rstmgr_smoke.3592702667 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 120896775 ps |
| CPU time | 1.14 seconds |
| Started | Feb 07 12:42:39 PM PST 24 |
| Finished | Feb 07 12:42:42 PM PST 24 |
| Peak memory | 200164 kb |
| Host | smart-3cc08643-b5da-4ab0-8822-476ac5831e1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592702667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3592702667 |
| Directory | /workspace/40.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/40.rstmgr_stress_all.4206524653 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3013062906 ps |
| CPU time | 15.21 seconds |
| Started | Feb 07 12:42:36 PM PST 24 |
| Finished | Feb 07 12:42:52 PM PST 24 |
| Peak memory | 200208 kb |
| Host | smart-da5a4a91-b86c-4060-b732-7812e5101029 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206524653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4206524653 |
| Directory | /workspace/40.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sw_rst.2323550640 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 266329948 ps |
| CPU time | 1.79 seconds |
| Started | Feb 07 12:42:29 PM PST 24 |
| Finished | Feb 07 12:42:32 PM PST 24 |
| Peak memory | 200008 kb |
| Host | smart-356a4140-fee1-42df-bfbe-f033cc7b2ff8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323550640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2323550640 |
| Directory | /workspace/40.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3759530872 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 67606054 ps |
| CPU time | 0.73 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:34 PM PST 24 |
| Peak memory | 199868 kb |
| Host | smart-e224cacf-f3ac-407d-a67d-162e7fb6015d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3759530872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3759530872 |
| Directory | /workspace/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/41.rstmgr_alert_test.3460315959 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 61860509 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:42:46 PM PST 24 |
| Finished | Feb 07 12:42:53 PM PST 24 |
| Peak memory | 199664 kb |
| Host | smart-ec26bb34-abf1-4e44-b52f-df8c9e6a055b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460315959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3460315959 |
| Directory | /workspace/41.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.291341381 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1227340229 ps |
| CPU time | 5.66 seconds |
| Started | Feb 07 12:42:45 PM PST 24 |
| Finished | Feb 07 12:42:52 PM PST 24 |
| Peak memory | 217220 kb |
| Host | smart-de8c9362-9358-47ae-aafc-d141e8cf1c1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=291341381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.291341381 |
| Directory | /workspace/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3291717990 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 244033116 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 12:42:46 PM PST 24 |
| Finished | Feb 07 12:42:53 PM PST 24 |
| Peak memory | 217280 kb |
| Host | smart-e0aca7e5-23d7-4ff8-ba71-817d0619f7cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291717990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3291717990 |
| Directory | /workspace/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/41.rstmgr_por_stretcher.536951456 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 146655529 ps |
| CPU time | 0.84 seconds |
| Started | Feb 07 12:42:46 PM PST 24 |
| Finished | Feb 07 12:42:53 PM PST 24 |
| Peak memory | 199740 kb |
| Host | smart-2bbe7ef0-3564-41d6-a51a-8c8ab2fa0d6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536951456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.536951456 |
| Directory | /workspace/41.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/41.rstmgr_reset.3682359895 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1668831304 ps |
| CPU time | 6.19 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:38 PM PST 24 |
| Peak memory | 200212 kb |
| Host | smart-3e5bc641-27f3-442c-a155-39e1b8b39477 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682359895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3682359895 |
| Directory | /workspace/41.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1645126643 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 95577561 ps |
| CPU time | 1.01 seconds |
| Started | Feb 07 12:42:38 PM PST 24 |
| Finished | Feb 07 12:42:40 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-0d7bec44-d840-42a9-a975-4d498762061e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645126643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1645126643 |
| Directory | /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/41.rstmgr_smoke.2001200020 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 249445233 ps |
| CPU time | 1.47 seconds |
| Started | Feb 07 12:42:37 PM PST 24 |
| Finished | Feb 07 12:42:39 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-5749a581-7670-4969-919b-ca1c1da27086 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001200020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2001200020 |
| Directory | /workspace/41.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/41.rstmgr_stress_all.2199085287 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2574133946 ps |
| CPU time | 11.82 seconds |
| Started | Feb 07 12:42:28 PM PST 24 |
| Finished | Feb 07 12:42:41 PM PST 24 |
| Peak memory | 200268 kb |
| Host | smart-691ffb40-7854-4c92-aad5-670ea9bdc4da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199085287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2199085287 |
| Directory | /workspace/41.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sw_rst.2555782080 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 132492206 ps |
| CPU time | 1.91 seconds |
| Started | Feb 07 12:42:38 PM PST 24 |
| Finished | Feb 07 12:42:41 PM PST 24 |
| Peak memory | 199972 kb |
| Host | smart-34b441dd-d42c-49a7-958c-27737286ac55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555782080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2555782080 |
| Directory | /workspace/41.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1893031905 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 106905786 ps |
| CPU time | 0.87 seconds |
| Started | Feb 07 12:42:35 PM PST 24 |
| Finished | Feb 07 12:42:37 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-ec4c5dc7-7d43-4761-9f42-1dd6e72de6e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1893031905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1893031905 |
| Directory | /workspace/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/42.rstmgr_alert_test.1899682670 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 89614247 ps |
| CPU time | 0.83 seconds |
| Started | Feb 07 12:42:35 PM PST 24 |
| Finished | Feb 07 12:42:37 PM PST 24 |
| Peak memory | 199848 kb |
| Host | smart-3b9c4d5d-d906-43e7-bc5f-08201b512e1c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899682670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1899682670 |
| Directory | /workspace/42.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.865668665 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1223463035 ps |
| CPU time | 5.38 seconds |
| Started | Feb 07 12:42:35 PM PST 24 |
| Finished | Feb 07 12:42:41 PM PST 24 |
| Peak memory | 217696 kb |
| Host | smart-4d677465-287f-4af3-a4bc-f0acc0e3bfab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865668665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.865668665 |
| Directory | /workspace/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.518929033 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 244655464 ps |
| CPU time | 1.19 seconds |
| Started | Feb 07 12:42:34 PM PST 24 |
| Finished | Feb 07 12:42:36 PM PST 24 |
| Peak memory | 217296 kb |
| Host | smart-03ef8f8c-db4c-422b-a23c-6950352b6aed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=518929033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.518929033 |
| Directory | /workspace/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/42.rstmgr_por_stretcher.391789398 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 95484717 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:42:37 PM PST 24 |
| Finished | Feb 07 12:42:39 PM PST 24 |
| Peak memory | 199800 kb |
| Host | smart-1590499c-0968-4465-87f3-c0d364d22052 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391789398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.391789398 |
| Directory | /workspace/42.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/42.rstmgr_reset.3905233091 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1710960313 ps |
| CPU time | 6.62 seconds |
| Started | Feb 07 12:42:31 PM PST 24 |
| Finished | Feb 07 12:42:38 PM PST 24 |
| Peak memory | 200112 kb |
| Host | smart-52df0a68-aa36-4485-9c0b-dd7139e45de3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905233091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3905233091 |
| Directory | /workspace/42.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3626277017 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 192028785 ps |
| CPU time | 1.26 seconds |
| Started | Feb 07 12:42:45 PM PST 24 |
| Finished | Feb 07 12:42:48 PM PST 24 |
| Peak memory | 199424 kb |
| Host | smart-e78e1d19-4a5b-4643-a059-dd46abaa3586 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626277017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3626277017 |
| Directory | /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/42.rstmgr_smoke.3452131572 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 105581251 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 12:42:46 PM PST 24 |
| Finished | Feb 07 12:42:53 PM PST 24 |
| Peak memory | 200020 kb |
| Host | smart-c5beddfa-c5eb-4418-a5d7-e0ee70f9ae69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452131572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3452131572 |
| Directory | /workspace/42.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/42.rstmgr_stress_all.4136817091 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5888613629 ps |
| CPU time | 26.56 seconds |
| Started | Feb 07 12:42:34 PM PST 24 |
| Finished | Feb 07 12:43:01 PM PST 24 |
| Peak memory | 200252 kb |
| Host | smart-ff34a713-f7b4-4bf2-9584-4c44bc4d44c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136817091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4136817091 |
| Directory | /workspace/42.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sw_rst.1197225886 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 140737037 ps |
| CPU time | 1.79 seconds |
| Started | Feb 07 12:42:37 PM PST 24 |
| Finished | Feb 07 12:42:40 PM PST 24 |
| Peak memory | 200040 kb |
| Host | smart-3263d21e-5582-4a5c-a2eb-0a15255e62f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1197225886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1197225886 |
| Directory | /workspace/42.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.821051431 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 71908562 ps |
| CPU time | 0.79 seconds |
| Started | Feb 07 12:42:45 PM PST 24 |
| Finished | Feb 07 12:42:47 PM PST 24 |
| Peak memory | 199848 kb |
| Host | smart-ecef1517-0eea-4398-817e-1e5bdb5a26ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821051431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.821051431 |
| Directory | /workspace/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/43.rstmgr_alert_test.907929654 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 77571112 ps |
| CPU time | 0.77 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:05 PM PST 24 |
| Peak memory | 199724 kb |
| Host | smart-9e52585f-a880-4e52-828a-77e721f823ed |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907929654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.907929654 |
| Directory | /workspace/43.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2153442899 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1216410420 ps |
| CPU time | 5.7 seconds |
| Started | Feb 07 12:42:50 PM PST 24 |
| Finished | Feb 07 12:42:59 PM PST 24 |
| Peak memory | 216728 kb |
| Host | smart-85d34443-212a-44cd-94ee-c1d65e8a278d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153442899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2153442899 |
| Directory | /workspace/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4138603067 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 244819152 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:03 PM PST 24 |
| Peak memory | 217368 kb |
| Host | smart-aeb447a9-4f47-4de9-8472-a0b64fcc4b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138603067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4138603067 |
| Directory | /workspace/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/43.rstmgr_por_stretcher.354330676 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 218450988 ps |
| CPU time | 0.93 seconds |
| Started | Feb 07 12:42:34 PM PST 24 |
| Finished | Feb 07 12:42:36 PM PST 24 |
| Peak memory | 199856 kb |
| Host | smart-d6e91ea5-e597-43ed-b5ab-989452730fd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354330676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.354330676 |
| Directory | /workspace/43.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/43.rstmgr_reset.2826861109 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1604087871 ps |
| CPU time | 7.06 seconds |
| Started | Feb 07 12:42:50 PM PST 24 |
| Finished | Feb 07 12:43:00 PM PST 24 |
| Peak memory | 200216 kb |
| Host | smart-65666370-49a0-4ade-a25e-945281f3ec21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826861109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2826861109 |
| Directory | /workspace/43.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3924425240 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 100737620 ps |
| CPU time | 1.04 seconds |
| Started | Feb 07 12:42:52 PM PST 24 |
| Finished | Feb 07 12:43:03 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-323256f8-af58-40b7-ac20-89d014b8b40e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924425240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3924425240 |
| Directory | /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/43.rstmgr_smoke.2782577534 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 253121131 ps |
| CPU time | 1.46 seconds |
| Started | Feb 07 12:42:32 PM PST 24 |
| Finished | Feb 07 12:42:35 PM PST 24 |
| Peak memory | 200144 kb |
| Host | smart-07d8eda2-9b39-4be8-93f8-47f969069383 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782577534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2782577534 |
| Directory | /workspace/43.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/43.rstmgr_stress_all.3043198023 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 6915835007 ps |
| CPU time | 27.73 seconds |
| Started | Feb 07 12:42:50 PM PST 24 |
| Finished | Feb 07 12:43:21 PM PST 24 |
| Peak memory | 200308 kb |
| Host | smart-44e52052-f1a8-4d4e-ae30-632a52359b87 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043198023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3043198023 |
| Directory | /workspace/43.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sw_rst.637518040 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 133117792 ps |
| CPU time | 1.71 seconds |
| Started | Feb 07 12:42:56 PM PST 24 |
| Finished | Feb 07 12:43:07 PM PST 24 |
| Peak memory | 199948 kb |
| Host | smart-66e7bce7-3c82-44fb-9812-d09f250a25da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637518040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.637518040 |
| Directory | /workspace/43.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2207084843 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 91822976 ps |
| CPU time | 0.9 seconds |
| Started | Feb 07 12:42:48 PM PST 24 |
| Finished | Feb 07 12:42:54 PM PST 24 |
| Peak memory | 199968 kb |
| Host | smart-5d1d0383-3300-4c37-b6df-3aff57d50673 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207084843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2207084843 |
| Directory | /workspace/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/44.rstmgr_alert_test.3561041783 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 75909220 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:42:52 PM PST 24 |
| Finished | Feb 07 12:43:03 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-0c37404d-2dde-47da-911a-cd2221566fbb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561041783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3561041783 |
| Directory | /workspace/44.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3653333842 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1232008124 ps |
| CPU time | 5.75 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:07 PM PST 24 |
| Peak memory | 221892 kb |
| Host | smart-9838fe4f-6b1e-4e8f-8e11-f0ea3931c6af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653333842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3653333842 |
| Directory | /workspace/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.18879951 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 244206086 ps |
| CPU time | 1.16 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:01 PM PST 24 |
| Peak memory | 217256 kb |
| Host | smart-cc9874c4-bedb-4b8f-9011-52ba8d495b0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18879951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.18879951 |
| Directory | /workspace/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/44.rstmgr_por_stretcher.3233060877 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 206375569 ps |
| CPU time | 0.93 seconds |
| Started | Feb 07 12:42:54 PM PST 24 |
| Finished | Feb 07 12:43:05 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-7ffa9a2a-bf55-4b99-84d7-6696af777b0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233060877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3233060877 |
| Directory | /workspace/44.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/44.rstmgr_reset.2184179294 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2156553169 ps |
| CPU time | 7.33 seconds |
| Started | Feb 07 12:42:48 PM PST 24 |
| Finished | Feb 07 12:43:00 PM PST 24 |
| Peak memory | 200144 kb |
| Host | smart-75b4b9b2-f303-46a5-a7f8-59ac37975e15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2184179294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2184179294 |
| Directory | /workspace/44.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.735365879 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 96615223 ps |
| CPU time | 0.95 seconds |
| Started | Feb 07 12:42:52 PM PST 24 |
| Finished | Feb 07 12:43:03 PM PST 24 |
| Peak memory | 200032 kb |
| Host | smart-06d11637-cce1-4029-b825-25d08e184fc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735365879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.735365879 |
| Directory | /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/44.rstmgr_smoke.353758991 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 203033083 ps |
| CPU time | 1.36 seconds |
| Started | Feb 07 12:42:49 PM PST 24 |
| Finished | Feb 07 12:42:55 PM PST 24 |
| Peak memory | 200176 kb |
| Host | smart-6334618d-a286-4bc6-8ba0-38c85443a531 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353758991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.353758991 |
| Directory | /workspace/44.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/44.rstmgr_stress_all.461648784 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2542349732 ps |
| CPU time | 12.96 seconds |
| Started | Feb 07 12:42:52 PM PST 24 |
| Finished | Feb 07 12:43:15 PM PST 24 |
| Peak memory | 200288 kb |
| Host | smart-072aaaeb-ab31-4f68-abcf-81190654ea42 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461648784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.461648784 |
| Directory | /workspace/44.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sw_rst.2924417428 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 135233790 ps |
| CPU time | 1.53 seconds |
| Started | Feb 07 12:42:45 PM PST 24 |
| Finished | Feb 07 12:42:52 PM PST 24 |
| Peak memory | 200048 kb |
| Host | smart-786eeafd-0a9d-4ba0-9b8a-ba395e944459 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924417428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2924417428 |
| Directory | /workspace/44.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1379165729 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 170698602 ps |
| CPU time | 1.38 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 200232 kb |
| Host | smart-5a719178-bc79-4662-8d05-ad496a8cf5c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379165729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1379165729 |
| Directory | /workspace/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/45.rstmgr_alert_test.4267409938 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 87944420 ps |
| CPU time | 0.77 seconds |
| Started | Feb 07 12:43:01 PM PST 24 |
| Finished | Feb 07 12:43:06 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-d4d6701b-5539-41ad-995c-b3a10e05698f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267409938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4267409938 |
| Directory | /workspace/45.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3329893936 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1892303779 ps |
| CPU time | 6.71 seconds |
| Started | Feb 07 12:42:52 PM PST 24 |
| Finished | Feb 07 12:43:09 PM PST 24 |
| Peak memory | 220776 kb |
| Host | smart-c9bddfd6-2592-4503-82a5-24db5e749b77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329893936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3329893936 |
| Directory | /workspace/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.467029263 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 243735202 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:42:48 PM PST 24 |
| Finished | Feb 07 12:42:54 PM PST 24 |
| Peak memory | 217224 kb |
| Host | smart-3e948d38-c0d2-496d-a25c-d19ff9da24c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467029263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.467029263 |
| Directory | /workspace/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/45.rstmgr_por_stretcher.2573852250 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 98650382 ps |
| CPU time | 0.73 seconds |
| Started | Feb 07 12:42:52 PM PST 24 |
| Finished | Feb 07 12:43:03 PM PST 24 |
| Peak memory | 199732 kb |
| Host | smart-94d916cc-5759-4f95-afdc-4d5745d8cfbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573852250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2573852250 |
| Directory | /workspace/45.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/45.rstmgr_reset.2660066996 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1446709146 ps |
| CPU time | 5.86 seconds |
| Started | Feb 07 12:42:54 PM PST 24 |
| Finished | Feb 07 12:43:10 PM PST 24 |
| Peak memory | 200104 kb |
| Host | smart-f20c1165-f86a-42eb-9966-22b2f3d3246a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660066996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2660066996 |
| Directory | /workspace/45.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1414970148 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 149453677 ps |
| CPU time | 1.14 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:42:55 PM PST 24 |
| Peak memory | 199440 kb |
| Host | smart-4b0e125f-d2f3-429d-967d-8149f8f2ad21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414970148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1414970148 |
| Directory | /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/45.rstmgr_smoke.76592969 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 258123183 ps |
| CPU time | 1.42 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:01 PM PST 24 |
| Peak memory | 200152 kb |
| Host | smart-26157c89-d7a9-470a-8e78-d8031e15a959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76592969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.76592969 |
| Directory | /workspace/45.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/45.rstmgr_stress_all.3246949259 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 6756341607 ps |
| CPU time | 25.9 seconds |
| Started | Feb 07 12:42:56 PM PST 24 |
| Finished | Feb 07 12:43:31 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-f1802cec-d798-4115-8485-8e93f51fd6c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246949259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3246949259 |
| Directory | /workspace/45.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sw_rst.3577446453 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 372668076 ps |
| CPU time | 2.1 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:06 PM PST 24 |
| Peak memory | 199924 kb |
| Host | smart-f3b6964f-b2cd-4c43-9b02-8e80b018ecc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577446453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3577446453 |
| Directory | /workspace/45.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.4088624518 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 90107727 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 12:42:55 PM PST 24 |
| Finished | Feb 07 12:43:06 PM PST 24 |
| Peak memory | 199904 kb |
| Host | smart-7ca74e6c-8465-4b29-809a-4c6491278081 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4088624518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4088624518 |
| Directory | /workspace/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/46.rstmgr_alert_test.2116686632 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 75868060 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:42:50 PM PST 24 |
| Finished | Feb 07 12:42:54 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-3100cec0-ca03-4343-96af-2d03f8685d87 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116686632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2116686632 |
| Directory | /workspace/46.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4096792560 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2362386802 ps |
| CPU time | 8.03 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:02 PM PST 24 |
| Peak memory | 221524 kb |
| Host | smart-de130147-465d-4e24-ac3e-0fc7c8e70d3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096792560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4096792560 |
| Directory | /workspace/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.392778231 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 244620095 ps |
| CPU time | 1 seconds |
| Started | Feb 07 12:43:00 PM PST 24 |
| Finished | Feb 07 12:43:06 PM PST 24 |
| Peak memory | 217276 kb |
| Host | smart-9e9a39f3-e0af-4eab-8633-9c0e29455e19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392778231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.392778231 |
| Directory | /workspace/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/46.rstmgr_por_stretcher.7605409 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 188708070 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 12:42:56 PM PST 24 |
| Finished | Feb 07 12:43:06 PM PST 24 |
| Peak memory | 199656 kb |
| Host | smart-9cb3c08a-ebdd-4d20-b279-26148198d40e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7605409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.7605409 |
| Directory | /workspace/46.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/46.rstmgr_reset.4216928602 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1796538210 ps |
| CPU time | 8.3 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:10 PM PST 24 |
| Peak memory | 200168 kb |
| Host | smart-eb677848-1477-4523-a97e-d1e2f5a494d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216928602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.4216928602 |
| Directory | /workspace/46.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3248160836 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 113782292 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:42:48 PM PST 24 |
| Finished | Feb 07 12:42:54 PM PST 24 |
| Peak memory | 199992 kb |
| Host | smart-9fa14ef1-c772-4db2-b283-f3a5a85e8c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248160836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3248160836 |
| Directory | /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/46.rstmgr_smoke.2144194125 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 116654101 ps |
| CPU time | 1.25 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:05 PM PST 24 |
| Peak memory | 200132 kb |
| Host | smart-46c210a5-7e16-48c4-8c0e-09035c607add |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144194125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2144194125 |
| Directory | /workspace/46.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/46.rstmgr_stress_all.2392043740 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4640951974 ps |
| CPU time | 15.54 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:17 PM PST 24 |
| Peak memory | 200220 kb |
| Host | smart-dd11357f-f0dd-4ed6-8cd4-00290f52ae7f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392043740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2392043740 |
| Directory | /workspace/46.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sw_rst.1993494247 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 364366046 ps |
| CPU time | 2.19 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:42:57 PM PST 24 |
| Peak memory | 199980 kb |
| Host | smart-325e9fa4-fab3-4703-91c6-2f42664f1b39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993494247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1993494247 |
| Directory | /workspace/46.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2779096898 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 68624415 ps |
| CPU time | 0.77 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 200004 kb |
| Host | smart-7d991e19-5097-4798-a668-3139b4e5763d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779096898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2779096898 |
| Directory | /workspace/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/47.rstmgr_alert_test.2945006326 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 83155644 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:42:56 PM PST 24 |
| Finished | Feb 07 12:43:06 PM PST 24 |
| Peak memory | 199796 kb |
| Host | smart-aa62bf34-1352-4987-b5c4-bb42535652cf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945006326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2945006326 |
| Directory | /workspace/47.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2203928918 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1227291177 ps |
| CPU time | 5.64 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:09 PM PST 24 |
| Peak memory | 217876 kb |
| Host | smart-ca73b923-5a8b-4340-b504-4805a8076abf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203928918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2203928918 |
| Directory | /workspace/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2819469679 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 244615391 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:42:47 PM PST 24 |
| Finished | Feb 07 12:42:54 PM PST 24 |
| Peak memory | 217304 kb |
| Host | smart-e9c0900e-a7bd-456c-8a87-8d956b10b8c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819469679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2819469679 |
| Directory | /workspace/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/47.rstmgr_por_stretcher.1131685015 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 102487012 ps |
| CPU time | 0.73 seconds |
| Started | Feb 07 12:42:49 PM PST 24 |
| Finished | Feb 07 12:42:54 PM PST 24 |
| Peak memory | 199808 kb |
| Host | smart-4421b032-147e-4792-a694-6d5770ec2a92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131685015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1131685015 |
| Directory | /workspace/47.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/47.rstmgr_reset.1235210990 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 849212211 ps |
| CPU time | 4.45 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:00 PM PST 24 |
| Peak memory | 200220 kb |
| Host | smart-89422b0f-f27f-42d9-8c46-99b5905a09be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235210990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1235210990 |
| Directory | /workspace/47.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1325864309 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 172150454 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 12:42:47 PM PST 24 |
| Finished | Feb 07 12:42:54 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-9c0c3544-03fb-4748-9e8c-2b52e7966e4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1325864309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1325864309 |
| Directory | /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/47.rstmgr_smoke.3064375773 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 241330720 ps |
| CPU time | 1.4 seconds |
| Started | Feb 07 12:43:01 PM PST 24 |
| Finished | Feb 07 12:43:07 PM PST 24 |
| Peak memory | 200108 kb |
| Host | smart-04a04ba2-874b-4c45-9c0e-357bf47ba898 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064375773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3064375773 |
| Directory | /workspace/47.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/47.rstmgr_stress_all.4060242127 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 3561027324 ps |
| CPU time | 14.71 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:09 PM PST 24 |
| Peak memory | 200272 kb |
| Host | smart-4b019145-3e7d-42c9-9525-510a76363dcb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060242127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4060242127 |
| Directory | /workspace/47.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sw_rst.2549294900 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 352608462 ps |
| CPU time | 2.36 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:06 PM PST 24 |
| Peak memory | 199972 kb |
| Host | smart-0f4bf44c-13c8-4509-80fd-0f3f38704f57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2549294900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2549294900 |
| Directory | /workspace/47.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1920006689 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 173606959 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-edb9b79a-15eb-4d70-8fc5-6764d3a134cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920006689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1920006689 |
| Directory | /workspace/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/48.rstmgr_alert_test.2016093791 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 74153889 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 199872 kb |
| Host | smart-b59d6c96-cb38-485c-a950-d655620a23fc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016093791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2016093791 |
| Directory | /workspace/48.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2381245078 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1896216041 ps |
| CPU time | 6.98 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:10 PM PST 24 |
| Peak memory | 220816 kb |
| Host | smart-e44d7127-313f-490f-a113-c0b55fefcf04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2381245078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2381245078 |
| Directory | /workspace/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.498157036 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 244743268 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 217380 kb |
| Host | smart-c037a99d-732b-431d-a501-f2c990af3b89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=498157036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.498157036 |
| Directory | /workspace/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/48.rstmgr_por_stretcher.1977057637 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 132659009 ps |
| CPU time | 0.84 seconds |
| Started | Feb 07 12:42:50 PM PST 24 |
| Finished | Feb 07 12:42:55 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-28951b2d-e955-4d6d-9e6f-1ad61251af87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1977057637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1977057637 |
| Directory | /workspace/48.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/48.rstmgr_reset.1677377067 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1256448056 ps |
| CPU time | 5.09 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:07 PM PST 24 |
| Peak memory | 200204 kb |
| Host | smart-e30f014f-dd09-4069-841a-ce13ecc499f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1677377067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1677377067 |
| Directory | /workspace/48.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.676998177 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 168778876 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 199840 kb |
| Host | smart-bf815937-f745-4f85-bb48-e16eb1fcf089 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676998177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.676998177 |
| Directory | /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/48.rstmgr_smoke.3946747436 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 115277460 ps |
| CPU time | 1.23 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-40839d31-bca8-4dad-9403-e84f479f8a20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946747436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3946747436 |
| Directory | /workspace/48.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/48.rstmgr_stress_all.1373446753 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 14384477119 ps |
| CPU time | 54.37 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:56 PM PST 24 |
| Peak memory | 200252 kb |
| Host | smart-73f5eafd-8fb1-43dd-89f2-46cf68d3d63a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373446753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1373446753 |
| Directory | /workspace/48.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sw_rst.1136159914 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 310292271 ps |
| CPU time | 2.24 seconds |
| Started | Feb 07 12:42:51 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 200004 kb |
| Host | smart-da6ecb73-e50c-419c-9368-4145ee9ba6c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136159914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1136159914 |
| Directory | /workspace/48.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2903199379 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 215735713 ps |
| CPU time | 1.23 seconds |
| Started | Feb 07 12:42:54 PM PST 24 |
| Finished | Feb 07 12:43:06 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-79696b1d-7419-4bdf-b2a6-a0eae564aed1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903199379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2903199379 |
| Directory | /workspace/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/49.rstmgr_alert_test.1537437301 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 52328872 ps |
| CPU time | 0.66 seconds |
| Started | Feb 07 12:43:07 PM PST 24 |
| Finished | Feb 07 12:43:12 PM PST 24 |
| Peak memory | 199944 kb |
| Host | smart-7e87d99c-403c-4166-aaa1-c658795925a1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537437301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1537437301 |
| Directory | /workspace/49.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1502084351 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1892505199 ps |
| CPU time | 6.94 seconds |
| Started | Feb 07 12:43:00 PM PST 24 |
| Finished | Feb 07 12:43:12 PM PST 24 |
| Peak memory | 216748 kb |
| Host | smart-1663f87c-9489-454c-9ed5-c707d1eaca60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502084351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1502084351 |
| Directory | /workspace/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1023400920 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 244165025 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 12:43:04 PM PST 24 |
| Finished | Feb 07 12:43:11 PM PST 24 |
| Peak memory | 217324 kb |
| Host | smart-8f493529-1001-41cc-a346-2b6d4e365e58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023400920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1023400920 |
| Directory | /workspace/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/49.rstmgr_por_stretcher.780863175 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 162532407 ps |
| CPU time | 0.83 seconds |
| Started | Feb 07 12:42:53 PM PST 24 |
| Finished | Feb 07 12:43:04 PM PST 24 |
| Peak memory | 199932 kb |
| Host | smart-f135c55a-3055-4602-ae4d-55517ad64bc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780863175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.780863175 |
| Directory | /workspace/49.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/49.rstmgr_reset.3277138134 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 901952954 ps |
| CPU time | 4.47 seconds |
| Started | Feb 07 12:43:14 PM PST 24 |
| Finished | Feb 07 12:43:19 PM PST 24 |
| Peak memory | 200268 kb |
| Host | smart-48038ade-a112-430d-80dd-bef7449ad9a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277138134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3277138134 |
| Directory | /workspace/49.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1373974414 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 186208646 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 12:43:07 PM PST 24 |
| Finished | Feb 07 12:43:12 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-5cc31d23-2af0-4d6a-8b06-39557fdcf7b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373974414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1373974414 |
| Directory | /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/49.rstmgr_smoke.4023453066 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 192111711 ps |
| CPU time | 1.42 seconds |
| Started | Feb 07 12:42:54 PM PST 24 |
| Finished | Feb 07 12:43:05 PM PST 24 |
| Peak memory | 200264 kb |
| Host | smart-4b741a11-823f-4fc9-83fe-36788ca67d2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023453066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.4023453066 |
| Directory | /workspace/49.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/49.rstmgr_stress_all.4094033317 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1290787921 ps |
| CPU time | 6 seconds |
| Started | Feb 07 12:42:59 PM PST 24 |
| Finished | Feb 07 12:43:11 PM PST 24 |
| Peak memory | 200220 kb |
| Host | smart-e0d51296-8ef9-40c8-8495-d9c74b5b15f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094033317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.4094033317 |
| Directory | /workspace/49.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1613046715 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 164365696 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:43:05 PM PST 24 |
| Finished | Feb 07 12:43:11 PM PST 24 |
| Peak memory | 200012 kb |
| Host | smart-57c1d6a7-887b-442c-94ae-da7d33b68672 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613046715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1613046715 |
| Directory | /workspace/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/5.rstmgr_alert_test.3072084616 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 61819079 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:41:27 PM PST 24 |
| Finished | Feb 07 12:41:29 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-53b88ffe-a1da-4168-916e-a4003d904fb8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072084616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3072084616 |
| Directory | /workspace/5.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.297212139 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1892663247 ps |
| CPU time | 7.09 seconds |
| Started | Feb 07 12:41:20 PM PST 24 |
| Finished | Feb 07 12:41:27 PM PST 24 |
| Peak memory | 217268 kb |
| Host | smart-daac94c0-fbdb-4c8f-948e-438df108a074 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=297212139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.297212139 |
| Directory | /workspace/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1491874972 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 244365070 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:41:20 PM PST 24 |
| Finished | Feb 07 12:41:23 PM PST 24 |
| Peak memory | 217240 kb |
| Host | smart-bf147ebf-03f1-44ab-a22a-9519ed74d7ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491874972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1491874972 |
| Directory | /workspace/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/5.rstmgr_por_stretcher.1854198111 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 208863220 ps |
| CPU time | 0.87 seconds |
| Started | Feb 07 12:41:26 PM PST 24 |
| Finished | Feb 07 12:41:27 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-3a842b88-df98-44eb-b948-1880155de8ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854198111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1854198111 |
| Directory | /workspace/5.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/5.rstmgr_reset.330435843 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1848495732 ps |
| CPU time | 7.11 seconds |
| Started | Feb 07 12:41:18 PM PST 24 |
| Finished | Feb 07 12:41:26 PM PST 24 |
| Peak memory | 200120 kb |
| Host | smart-424d4434-77eb-4f74-942d-52c2a3951e7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330435843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.330435843 |
| Directory | /workspace/5.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1468077864 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 103370843 ps |
| CPU time | 0.95 seconds |
| Started | Feb 07 12:41:18 PM PST 24 |
| Finished | Feb 07 12:41:20 PM PST 24 |
| Peak memory | 199888 kb |
| Host | smart-d71087e0-e568-4292-a389-55fab68e3468 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1468077864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1468077864 |
| Directory | /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/5.rstmgr_smoke.3784297531 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 118874993 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 12:41:20 PM PST 24 |
| Finished | Feb 07 12:41:23 PM PST 24 |
| Peak memory | 200148 kb |
| Host | smart-583745c0-b4c2-41ae-83f0-b4e5941641e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784297531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3784297531 |
| Directory | /workspace/5.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/5.rstmgr_stress_all.3931363456 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4571100162 ps |
| CPU time | 19.62 seconds |
| Started | Feb 07 12:41:16 PM PST 24 |
| Finished | Feb 07 12:41:37 PM PST 24 |
| Peak memory | 200208 kb |
| Host | smart-3988f72e-7459-48b0-af57-a5e941723f84 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931363456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3931363456 |
| Directory | /workspace/5.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sw_rst.3055705374 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 138037529 ps |
| CPU time | 1.7 seconds |
| Started | Feb 07 12:41:18 PM PST 24 |
| Finished | Feb 07 12:41:21 PM PST 24 |
| Peak memory | 200008 kb |
| Host | smart-7c81dd52-25c8-48fd-8372-7f8c68c5f301 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055705374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3055705374 |
| Directory | /workspace/5.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1567374001 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 117490399 ps |
| CPU time | 0.93 seconds |
| Started | Feb 07 12:41:20 PM PST 24 |
| Finished | Feb 07 12:41:21 PM PST 24 |
| Peak memory | 199876 kb |
| Host | smart-81f0edcd-bdb1-4afd-820a-5066ab795926 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1567374001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1567374001 |
| Directory | /workspace/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/6.rstmgr_alert_test.3942501345 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 71980667 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:41:22 PM PST 24 |
| Finished | Feb 07 12:41:23 PM PST 24 |
| Peak memory | 199812 kb |
| Host | smart-4e434350-8c06-43e2-a9a0-8f9e53829465 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942501345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3942501345 |
| Directory | /workspace/6.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.780533009 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2180099065 ps |
| CPU time | 7.58 seconds |
| Started | Feb 07 12:41:24 PM PST 24 |
| Finished | Feb 07 12:41:32 PM PST 24 |
| Peak memory | 217792 kb |
| Host | smart-d480d7b6-d55b-4e88-a4e8-548f6194a55b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780533009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.780533009 |
| Directory | /workspace/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1798055622 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 244190138 ps |
| CPU time | 1.05 seconds |
| Started | Feb 07 12:41:22 PM PST 24 |
| Finished | Feb 07 12:41:24 PM PST 24 |
| Peak memory | 217288 kb |
| Host | smart-34ab20be-9edb-458e-947e-861ac86e1d04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798055622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1798055622 |
| Directory | /workspace/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/6.rstmgr_por_stretcher.3953038579 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 113075758 ps |
| CPU time | 0.75 seconds |
| Started | Feb 07 12:41:20 PM PST 24 |
| Finished | Feb 07 12:41:21 PM PST 24 |
| Peak memory | 199748 kb |
| Host | smart-f7e713e6-ff37-4b71-bdce-49c0661de947 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953038579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3953038579 |
| Directory | /workspace/6.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/6.rstmgr_reset.3393588749 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1539371069 ps |
| CPU time | 6.04 seconds |
| Started | Feb 07 12:41:24 PM PST 24 |
| Finished | Feb 07 12:41:31 PM PST 24 |
| Peak memory | 200188 kb |
| Host | smart-469148fb-6120-4a57-bb11-2ea6395adbe4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393588749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3393588749 |
| Directory | /workspace/6.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.560772038 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 144404815 ps |
| CPU time | 1.08 seconds |
| Started | Feb 07 12:41:20 PM PST 24 |
| Finished | Feb 07 12:41:23 PM PST 24 |
| Peak memory | 199968 kb |
| Host | smart-c3a28fdd-6741-411c-80ee-d60409874c0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560772038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.560772038 |
| Directory | /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/6.rstmgr_smoke.1237502859 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 202234236 ps |
| CPU time | 1.46 seconds |
| Started | Feb 07 12:41:27 PM PST 24 |
| Finished | Feb 07 12:41:29 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-76aa33d1-2866-4a1c-a9a7-0b7cd2b26233 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237502859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1237502859 |
| Directory | /workspace/6.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/6.rstmgr_stress_all.2074442793 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 8960649324 ps |
| CPU time | 29.52 seconds |
| Started | Feb 07 12:41:24 PM PST 24 |
| Finished | Feb 07 12:41:54 PM PST 24 |
| Peak memory | 200128 kb |
| Host | smart-bf47cce6-9c5f-4512-8e1a-dd9f9dcbbae1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074442793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2074442793 |
| Directory | /workspace/6.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sw_rst.1694782786 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 277413494 ps |
| CPU time | 1.95 seconds |
| Started | Feb 07 12:41:24 PM PST 24 |
| Finished | Feb 07 12:41:27 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-3e2ede05-e6b1-4604-9f8e-c16f2220b4c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694782786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1694782786 |
| Directory | /workspace/6.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.903705452 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 141237339 ps |
| CPU time | 1.02 seconds |
| Started | Feb 07 12:41:25 PM PST 24 |
| Finished | Feb 07 12:41:27 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-bce8b46a-0473-4998-bf6f-d1fa631ff0b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903705452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.903705452 |
| Directory | /workspace/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/7.rstmgr_alert_test.2911756937 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 75609449 ps |
| CPU time | 0.73 seconds |
| Started | Feb 07 12:41:25 PM PST 24 |
| Finished | Feb 07 12:41:27 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-069e533c-d37a-4d0f-a339-877c416a6288 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911756937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2911756937 |
| Directory | /workspace/7.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2817432486 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1889634975 ps |
| CPU time | 7.14 seconds |
| Started | Feb 07 12:41:31 PM PST 24 |
| Finished | Feb 07 12:41:39 PM PST 24 |
| Peak memory | 221840 kb |
| Host | smart-75e8928b-d61b-45ba-a3fc-8b01431e5816 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817432486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2817432486 |
| Directory | /workspace/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1408665746 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 244830759 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 12:41:27 PM PST 24 |
| Finished | Feb 07 12:41:29 PM PST 24 |
| Peak memory | 217296 kb |
| Host | smart-20f47158-b995-4f23-b06a-e4fd0aebbbe2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408665746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1408665746 |
| Directory | /workspace/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/7.rstmgr_por_stretcher.4154787323 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 147123581 ps |
| CPU time | 0.74 seconds |
| Started | Feb 07 12:41:26 PM PST 24 |
| Finished | Feb 07 12:41:27 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-04adda09-0150-408f-a74d-def5898e8f08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154787323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.4154787323 |
| Directory | /workspace/7.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/7.rstmgr_reset.3823857127 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 751110686 ps |
| CPU time | 3.76 seconds |
| Started | Feb 07 12:41:28 PM PST 24 |
| Finished | Feb 07 12:41:32 PM PST 24 |
| Peak memory | 200116 kb |
| Host | smart-a9fc3124-71a3-4d38-8469-cf231921557c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823857127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3823857127 |
| Directory | /workspace/7.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3222129639 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 108068638 ps |
| CPU time | 1.03 seconds |
| Started | Feb 07 12:41:30 PM PST 24 |
| Finished | Feb 07 12:41:31 PM PST 24 |
| Peak memory | 199992 kb |
| Host | smart-0cc87a98-4316-47c9-9fa8-3dbd1592e2d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222129639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3222129639 |
| Directory | /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/7.rstmgr_smoke.1417007174 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 110949664 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 12:41:32 PM PST 24 |
| Finished | Feb 07 12:41:34 PM PST 24 |
| Peak memory | 200168 kb |
| Host | smart-eafc6fc6-d8b5-4b2f-b2da-91baff09c700 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417007174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1417007174 |
| Directory | /workspace/7.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/7.rstmgr_stress_all.3085157646 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 6889802726 ps |
| CPU time | 25.4 seconds |
| Started | Feb 07 12:41:28 PM PST 24 |
| Finished | Feb 07 12:41:54 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-ac01c39f-8fff-4264-a5e1-da200c9d64b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085157646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3085157646 |
| Directory | /workspace/7.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sw_rst.3497665840 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 133656524 ps |
| CPU time | 1.7 seconds |
| Started | Feb 07 12:41:30 PM PST 24 |
| Finished | Feb 07 12:41:33 PM PST 24 |
| Peak memory | 200096 kb |
| Host | smart-cb5d3470-648c-4bee-965a-c5cfd6b43b32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497665840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3497665840 |
| Directory | /workspace/7.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3314147437 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 117197720 ps |
| CPU time | 0.97 seconds |
| Started | Feb 07 12:41:31 PM PST 24 |
| Finished | Feb 07 12:41:32 PM PST 24 |
| Peak memory | 199964 kb |
| Host | smart-64e57f2a-dac6-49d3-b0fe-2e5b716a6375 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314147437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3314147437 |
| Directory | /workspace/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/8.rstmgr_alert_test.2236533890 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 70107305 ps |
| CPU time | 0.74 seconds |
| Started | Feb 07 12:41:36 PM PST 24 |
| Finished | Feb 07 12:41:38 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-cc7d8373-8850-40a9-a899-e5c448373c8e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236533890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2236533890 |
| Directory | /workspace/8.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4200749497 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1882174920 ps |
| CPU time | 6.65 seconds |
| Started | Feb 07 12:41:30 PM PST 24 |
| Finished | Feb 07 12:41:37 PM PST 24 |
| Peak memory | 217232 kb |
| Host | smart-001bfeef-a56d-40a6-9dee-44820e3e2c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200749497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4200749497 |
| Directory | /workspace/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2094414660 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 245409823 ps |
| CPU time | 1.07 seconds |
| Started | Feb 07 12:41:36 PM PST 24 |
| Finished | Feb 07 12:41:39 PM PST 24 |
| Peak memory | 217192 kb |
| Host | smart-71e5d9c9-0536-48de-aa69-1e1eee7d59b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2094414660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2094414660 |
| Directory | /workspace/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/8.rstmgr_por_stretcher.3973118396 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 134538331 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 12:41:29 PM PST 24 |
| Finished | Feb 07 12:41:30 PM PST 24 |
| Peak memory | 199756 kb |
| Host | smart-f9881253-1974-4169-9c89-0a98e50a02c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973118396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3973118396 |
| Directory | /workspace/8.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/8.rstmgr_reset.1984496137 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1047491006 ps |
| CPU time | 4.98 seconds |
| Started | Feb 07 12:41:36 PM PST 24 |
| Finished | Feb 07 12:41:42 PM PST 24 |
| Peak memory | 200100 kb |
| Host | smart-197ea249-3a61-4fc6-a485-b8ed5ff07fe5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1984496137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1984496137 |
| Directory | /workspace/8.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.472470058 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 166026545 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 12:41:39 PM PST 24 |
| Finished | Feb 07 12:41:41 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-8e1d6eae-ffe6-4b84-8574-2ac9b5419304 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472470058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.472470058 |
| Directory | /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/8.rstmgr_smoke.2160479060 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 260327395 ps |
| CPU time | 1.46 seconds |
| Started | Feb 07 12:41:25 PM PST 24 |
| Finished | Feb 07 12:41:28 PM PST 24 |
| Peak memory | 200076 kb |
| Host | smart-6c8382ff-333d-43a0-904b-be56e18c3bdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160479060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2160479060 |
| Directory | /workspace/8.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/8.rstmgr_stress_all.3861886444 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4297723730 ps |
| CPU time | 21.18 seconds |
| Started | Feb 07 12:41:39 PM PST 24 |
| Finished | Feb 07 12:42:01 PM PST 24 |
| Peak memory | 200136 kb |
| Host | smart-db99de58-b582-4f16-b47c-0b10e2b2d1c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861886444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3861886444 |
| Directory | /workspace/8.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sw_rst.648969170 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 362038851 ps |
| CPU time | 2.06 seconds |
| Started | Feb 07 12:41:30 PM PST 24 |
| Finished | Feb 07 12:41:33 PM PST 24 |
| Peak memory | 199952 kb |
| Host | smart-3acc6921-c31f-4d81-8e12-d354f71354cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648969170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.648969170 |
| Directory | /workspace/8.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3869183395 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 105613495 ps |
| CPU time | 0.87 seconds |
| Started | Feb 07 12:41:25 PM PST 24 |
| Finished | Feb 07 12:41:26 PM PST 24 |
| Peak memory | 199876 kb |
| Host | smart-9ad95c9e-5e8e-434c-a24d-3b76da3b497e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869183395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3869183395 |
| Directory | /workspace/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/9.rstmgr_alert_test.2304990272 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 107443363 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:41:36 PM PST 24 |
| Finished | Feb 07 12:41:37 PM PST 24 |
| Peak memory | 199728 kb |
| Host | smart-8894cf9a-0d84-4889-9e60-bb42d4fe4734 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304990272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2304990272 |
| Directory | /workspace/9.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3258885942 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2175047264 ps |
| CPU time | 7.9 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:49 PM PST 24 |
| Peak memory | 217264 kb |
| Host | smart-335f7f4a-6876-4213-91e6-eaf03da51422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3258885942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3258885942 |
| Directory | /workspace/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3341306609 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 244068381 ps |
| CPU time | 1.1 seconds |
| Started | Feb 07 12:41:40 PM PST 24 |
| Finished | Feb 07 12:41:42 PM PST 24 |
| Peak memory | 217188 kb |
| Host | smart-1011a0ef-03d2-4cb5-9b03-63c49c534df7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341306609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3341306609 |
| Directory | /workspace/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/9.rstmgr_por_stretcher.4004850060 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 110655981 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:41:28 PM PST 24 |
| Finished | Feb 07 12:41:29 PM PST 24 |
| Peak memory | 199736 kb |
| Host | smart-0ec1f574-672a-4937-9a68-f7e4c37a0a31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004850060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4004850060 |
| Directory | /workspace/9.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/9.rstmgr_reset.2324018583 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 752501290 ps |
| CPU time | 3.67 seconds |
| Started | Feb 07 12:41:39 PM PST 24 |
| Finished | Feb 07 12:41:43 PM PST 24 |
| Peak memory | 200108 kb |
| Host | smart-a84e316d-cfd0-4142-9872-67900b8159de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324018583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2324018583 |
| Directory | /workspace/9.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.844861831 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 104989663 ps |
| CPU time | 0.94 seconds |
| Started | Feb 07 12:41:36 PM PST 24 |
| Finished | Feb 07 12:41:37 PM PST 24 |
| Peak memory | 199848 kb |
| Host | smart-08c6f91b-805f-4261-be17-fa93ebedb224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844861831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.844861831 |
| Directory | /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/9.rstmgr_smoke.2587646145 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 252704001 ps |
| CPU time | 1.42 seconds |
| Started | Feb 07 12:41:37 PM PST 24 |
| Finished | Feb 07 12:41:39 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-a2721e3b-2c91-4877-8044-00a721a3b5e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587646145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2587646145 |
| Directory | /workspace/9.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/9.rstmgr_stress_all.4201336679 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 932837737 ps |
| CPU time | 3.83 seconds |
| Started | Feb 07 12:41:28 PM PST 24 |
| Finished | Feb 07 12:41:33 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-fcde08e2-27d4-4c4c-beda-c7e5904ee2f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201336679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.4201336679 |
| Directory | /workspace/9.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sw_rst.535246530 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 300192603 ps |
| CPU time | 1.83 seconds |
| Started | Feb 07 12:41:25 PM PST 24 |
| Finished | Feb 07 12:41:28 PM PST 24 |
| Peak memory | 199876 kb |
| Host | smart-8437435d-234a-435f-8ef3-95a19640edee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535246530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.535246530 |
| Directory | /workspace/9.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2299144411 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 146413605 ps |
| CPU time | 1.21 seconds |
| Started | Feb 07 12:41:29 PM PST 24 |
| Finished | Feb 07 12:41:31 PM PST 24 |
| Peak memory | 199992 kb |
| Host | smart-f4dfb578-ce54-4137-9e8e-0a76044d323c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299144411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2299144411 |
| Directory | /workspace/9.rstmgr_sw_rst_reset_race/latest |
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