Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_info_cp 8 0 8 100.00 100 1 1 0


Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
capture_cross 16 0 16 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7836 1 T1 7 T2 105 T3 17
auto[1] 11034 1 T1 1 T2 108 T3 84



Summary for Variable reset_info_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for reset_info_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5884 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] 6343 1 T1 1 T2 69 T3 27
reset_info_cp[2] 2890 1 T2 31 T3 16 T4 34
reset_info_cp[4] 3807 1 T2 53 T3 18 T4 43
reset_info_cp[8] 124 1 T2 2 T3 1 T4 1
reset_info_cp[16] 113 1 T3 1 T4 3 T61 1
reset_info_cp[32] 105 1 T2 1 T3 3 T4 1
reset_info_cp[64] 112 1 T4 2 T7 1 T8 1
reset_info_cp[128] 112 1 T1 2 T2 1 T3 1



Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for capture_cross

Bins
reset_info_cpenable_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] auto[0] 2974 1 T2 27 T3 17 T4 46
reset_info_cp[1] auto[1] 2749 1 T2 41 T3 9 T4 35
reset_info_cp[2] auto[0] 853 1 T2 13 T4 12 T7 3
reset_info_cp[2] auto[1] 2037 1 T2 18 T3 16 T4 22
reset_info_cp[4] auto[0] 1299 1 T2 28 T4 24 T7 8
reset_info_cp[4] auto[1] 2508 1 T2 25 T3 18 T4 19
reset_info_cp[8] auto[0] 57 1 T2 2 T8 1 T61 2
reset_info_cp[8] auto[1] 67 1 T3 1 T4 1 T9 1
reset_info_cp[16] auto[0] 54 1 T61 1 T63 1 T28 2
reset_info_cp[16] auto[1] 59 1 T3 1 T4 3 T56 1
reset_info_cp[32] auto[0] 39 1 T2 1 T4 1 T62 1
reset_info_cp[32] auto[1] 66 1 T3 3 T10 1 T98 1
reset_info_cp[64] auto[0] 48 1 T4 1 T8 1 T61 1
reset_info_cp[64] auto[1] 64 1 T4 1 T7 1 T56 1
reset_info_cp[128] auto[0] 47 1 T1 2 T4 2 T7 1
reset_info_cp[128] auto[1] 65 1 T2 1 T3 1 T4 2

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