Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8029

1

T1

7

T2

103

T3

17

auto[1]

10841

1

T1

1

T2

110

T3

84

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5884	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6343	1			T1	1		T2	69		T3	27
reset_info_cp[2]	2890	1			T2	31		T3	16		T4	34
reset_info_cp[4]	3807	1			T2	53		T3	18		T4	43
reset_info_cp[8]	124	1			T2	2		T3	1		T4	1
reset_info_cp[16]	113	1			T3	1		T4	3		T61	1
reset_info_cp[32]	105	1			T2	1		T3	3		T4	1
reset_info_cp[64]	112	1			T4	2		T7	1		T8	1
reset_info_cp[128]	112	1			T1	2		T2	1		T3	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2987	1			T2	28		T3	17		T4	47
reset_info_cp[1]	auto[1]	2736	1			T2	40		T3	9		T4	34
reset_info_cp[2]	auto[0]	937	1			T2	15		T4	16		T7	3
reset_info_cp[2]	auto[1]	1953	1			T2	16		T3	16		T4	18
reset_info_cp[4]	auto[0]	1359	1			T2	27		T4	22		T7	8
reset_info_cp[4]	auto[1]	2448	1			T2	26		T3	18		T4	21
reset_info_cp[8]	auto[0]	62	1			T10	1		T61	2		T62	1
reset_info_cp[8]	auto[1]	62	1			T2	2		T3	1		T4	1
reset_info_cp[16]	auto[0]	53	1			T4	2		T61	1		T63	1
reset_info_cp[16]	auto[1]	60	1			T3	1		T4	1		T56	1
reset_info_cp[32]	auto[0]	42	1			T4	1		T62	1		T24	1
reset_info_cp[32]	auto[1]	63	1			T2	1		T3	3		T10	1
reset_info_cp[64]	auto[0]	46	1			T4	1		T8	1		T61	1
reset_info_cp[64]	auto[1]	66	1			T4	1		T7	1		T56	1
reset_info_cp[128]	auto[0]	54	1			T1	2		T4	3		T7	1
reset_info_cp[128]	auto[1]	58	1			T2	1		T3	1		T4	1