Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T533 /workspace/coverage/default/1.rstmgr_reset.82249392 Feb 18 12:51:07 PM PST 24 Feb 18 12:51:15 PM PST 24 1777756338 ps
T534 /workspace/coverage/default/29.rstmgr_alert_test.2177749389 Feb 18 12:52:15 PM PST 24 Feb 18 12:52:21 PM PST 24 75407490 ps
T535 /workspace/coverage/default/15.rstmgr_alert_test.2833440205 Feb 18 12:51:41 PM PST 24 Feb 18 12:51:46 PM PST 24 65580537 ps
T536 /workspace/coverage/default/44.rstmgr_por_stretcher.2176765916 Feb 18 12:52:27 PM PST 24 Feb 18 12:52:30 PM PST 24 209565893 ps
T537 /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3591918147 Feb 18 12:51:18 PM PST 24 Feb 18 12:51:23 PM PST 24 243074208 ps
T76 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1495450858 Feb 18 01:23:39 PM PST 24 Feb 18 01:23:41 PM PST 24 138232321 ps
T77 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1081852159 Feb 18 01:23:49 PM PST 24 Feb 18 01:23:51 PM PST 24 486030655 ps
T78 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2423731550 Feb 18 01:23:34 PM PST 24 Feb 18 01:23:35 PM PST 24 73372543 ps
T79 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.442405541 Feb 18 01:23:18 PM PST 24 Feb 18 01:23:20 PM PST 24 75277194 ps
T80 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3569959013 Feb 18 01:23:26 PM PST 24 Feb 18 01:23:30 PM PST 24 880880156 ps
T81 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2011064742 Feb 18 01:23:35 PM PST 24 Feb 18 01:23:39 PM PST 24 265375146 ps
T82 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3047287681 Feb 18 01:23:41 PM PST 24 Feb 18 01:23:46 PM PST 24 539374723 ps
T83 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3264677224 Feb 18 01:23:25 PM PST 24 Feb 18 01:23:28 PM PST 24 180624341 ps
T123 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.430130026 Feb 18 01:23:42 PM PST 24 Feb 18 01:23:44 PM PST 24 126195847 ps
T124 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.822752450 Feb 18 01:23:33 PM PST 24 Feb 18 01:23:35 PM PST 24 121409293 ps
T100 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.198556078 Feb 18 01:23:18 PM PST 24 Feb 18 01:23:22 PM PST 24 254815634 ps
T101 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.490235209 Feb 18 01:23:29 PM PST 24 Feb 18 01:23:34 PM PST 24 776489473 ps
T102 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.983350064 Feb 18 01:23:43 PM PST 24 Feb 18 01:23:47 PM PST 24 504368600 ps
T538 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3867099480 Feb 18 01:23:18 PM PST 24 Feb 18 01:23:20 PM PST 24 235696614 ps
T105 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1066434052 Feb 18 01:22:50 PM PST 24 Feb 18 01:22:52 PM PST 24 477658166 ps
T103 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3104996394 Feb 18 01:23:31 PM PST 24 Feb 18 01:23:36 PM PST 24 615242521 ps
T539 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1857687628 Feb 18 01:23:23 PM PST 24 Feb 18 01:23:24 PM PST 24 74576884 ps
T104 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1324295834 Feb 18 01:23:35 PM PST 24 Feb 18 01:23:39 PM PST 24 263615076 ps
T106 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3232815355 Feb 18 01:23:51 PM PST 24 Feb 18 01:23:54 PM PST 24 182109010 ps
T540 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3645096302 Feb 18 01:23:50 PM PST 24 Feb 18 01:23:55 PM PST 24 603403583 ps
T541 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2350787224 Feb 18 01:23:06 PM PST 24 Feb 18 01:23:09 PM PST 24 151236542 ps
T134 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3324656217 Feb 18 01:23:34 PM PST 24 Feb 18 01:23:40 PM PST 24 632698280 ps
T145 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1662140625 Feb 18 01:22:50 PM PST 24 Feb 18 01:22:53 PM PST 24 785154447 ps
T542 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3989551701 Feb 18 01:23:17 PM PST 24 Feb 18 01:23:21 PM PST 24 447318484 ps
T125 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4062706103 Feb 18 01:23:25 PM PST 24 Feb 18 01:23:27 PM PST 24 110037687 ps
T543 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.172497676 Feb 18 01:23:10 PM PST 24 Feb 18 01:23:17 PM PST 24 489701574 ps
T126 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.647331565 Feb 18 01:24:03 PM PST 24 Feb 18 01:24:05 PM PST 24 112774665 ps
T127 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2133803695 Feb 18 01:23:23 PM PST 24 Feb 18 01:23:25 PM PST 24 73453676 ps
T544 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1030807655 Feb 18 01:22:56 PM PST 24 Feb 18 01:23:04 PM PST 24 491374407 ps
T545 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2624527928 Feb 18 01:23:40 PM PST 24 Feb 18 01:23:43 PM PST 24 287495127 ps
T128 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.799999955 Feb 18 01:23:49 PM PST 24 Feb 18 01:23:50 PM PST 24 85120355 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3008687711 Feb 18 01:22:56 PM PST 24 Feb 18 01:23:01 PM PST 24 175499411 ps
T129 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3072452886 Feb 18 01:23:42 PM PST 24 Feb 18 01:23:43 PM PST 24 60479991 ps
T130 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.892882952 Feb 18 01:23:32 PM PST 24 Feb 18 01:23:36 PM PST 24 892537904 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1718495107 Feb 18 01:22:54 PM PST 24 Feb 18 01:22:57 PM PST 24 205541197 ps
T548 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1966282784 Feb 18 01:23:44 PM PST 24 Feb 18 01:23:46 PM PST 24 94731074 ps
T144 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1151569998 Feb 18 01:23:23 PM PST 24 Feb 18 01:23:26 PM PST 24 412905093 ps
T549 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.541137153 Feb 18 01:22:50 PM PST 24 Feb 18 01:22:55 PM PST 24 804611588 ps
T146 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2834213224 Feb 18 01:23:18 PM PST 24 Feb 18 01:23:21 PM PST 24 463997880 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.439208475 Feb 18 01:23:16 PM PST 24 Feb 18 01:23:18 PM PST 24 272692107 ps
T551 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.641926192 Feb 18 01:23:54 PM PST 24 Feb 18 01:23:57 PM PST 24 178499710 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.803404582 Feb 18 01:23:35 PM PST 24 Feb 18 01:23:39 PM PST 24 395374292 ps
T553 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3240935734 Feb 18 01:23:28 PM PST 24 Feb 18 01:23:29 PM PST 24 134986545 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2825630186 Feb 18 01:23:06 PM PST 24 Feb 18 01:23:08 PM PST 24 78206349 ps
T555 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1953880573 Feb 18 01:23:29 PM PST 24 Feb 18 01:23:31 PM PST 24 164239709 ps
T147 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2695906552 Feb 18 01:23:17 PM PST 24 Feb 18 01:23:20 PM PST 24 864586064 ps
T556 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1663396399 Feb 18 01:23:26 PM PST 24 Feb 18 01:23:28 PM PST 24 230982024 ps
T557 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1867291813 Feb 18 01:23:07 PM PST 24 Feb 18 01:23:11 PM PST 24 578252293 ps
T558 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2170992697 Feb 18 01:22:45 PM PST 24 Feb 18 01:22:50 PM PST 24 517416113 ps
T559 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3298803792 Feb 18 01:23:09 PM PST 24 Feb 18 01:23:11 PM PST 24 70746099 ps
T133 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2924429831 Feb 18 01:23:30 PM PST 24 Feb 18 01:23:33 PM PST 24 423574272 ps
T560 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3417460699 Feb 18 01:22:49 PM PST 24 Feb 18 01:22:51 PM PST 24 125397559 ps
T561 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.212198294 Feb 18 01:23:17 PM PST 24 Feb 18 01:23:18 PM PST 24 93442112 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.302683340 Feb 18 01:23:25 PM PST 24 Feb 18 01:23:27 PM PST 24 65369959 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.761295092 Feb 18 01:23:33 PM PST 24 Feb 18 01:23:34 PM PST 24 72027724 ps
T131 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.818538311 Feb 18 01:23:00 PM PST 24 Feb 18 01:23:05 PM PST 24 915744370 ps
T564 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1119426734 Feb 18 01:23:33 PM PST 24 Feb 18 01:23:35 PM PST 24 59240339 ps
T565 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3718558641 Feb 18 01:23:51 PM PST 24 Feb 18 01:23:53 PM PST 24 239111607 ps
T566 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2232190042 Feb 18 01:23:36 PM PST 24 Feb 18 01:23:39 PM PST 24 211983274 ps
T567 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1302131173 Feb 18 01:24:00 PM PST 24 Feb 18 01:24:02 PM PST 24 87147360 ps
T568 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1111340892 Feb 18 01:23:51 PM PST 24 Feb 18 01:23:54 PM PST 24 892494605 ps
T569 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3906840143 Feb 18 01:23:00 PM PST 24 Feb 18 01:23:02 PM PST 24 69914781 ps
T570 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1479148671 Feb 18 01:23:41 PM PST 24 Feb 18 01:23:44 PM PST 24 912035054 ps
T571 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.524296423 Feb 18 01:23:35 PM PST 24 Feb 18 01:23:38 PM PST 24 270237482 ps
T572 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.780334288 Feb 18 01:23:51 PM PST 24 Feb 18 01:23:52 PM PST 24 70284507 ps
T573 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3112582281 Feb 18 01:22:56 PM PST 24 Feb 18 01:23:00 PM PST 24 240917024 ps
T574 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3423748128 Feb 18 01:23:29 PM PST 24 Feb 18 01:23:31 PM PST 24 62157102 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3632471266 Feb 18 01:22:56 PM PST 24 Feb 18 01:22:59 PM PST 24 110620545 ps
T576 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3792995393 Feb 18 01:23:35 PM PST 24 Feb 18 01:23:38 PM PST 24 88956737 ps
T577 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1417597287 Feb 18 01:23:32 PM PST 24 Feb 18 01:23:35 PM PST 24 274738987 ps
T578 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2423856786 Feb 18 01:22:51 PM PST 24 Feb 18 01:22:53 PM PST 24 65457021 ps
T579 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1823025526 Feb 18 01:22:58 PM PST 24 Feb 18 01:23:02 PM PST 24 75199804 ps
T580 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1564645112 Feb 18 01:23:23 PM PST 24 Feb 18 01:23:25 PM PST 24 87535589 ps
T581 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1186791265 Feb 18 01:23:50 PM PST 24 Feb 18 01:23:52 PM PST 24 130743970 ps
T582 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1810387201 Feb 18 01:24:01 PM PST 24 Feb 18 01:24:03 PM PST 24 475068227 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3662088995 Feb 18 01:23:09 PM PST 24 Feb 18 01:23:12 PM PST 24 142739373 ps
T584 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2071207556 Feb 18 01:23:25 PM PST 24 Feb 18 01:23:28 PM PST 24 160858868 ps
T585 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3464394748 Feb 18 01:23:23 PM PST 24 Feb 18 01:23:26 PM PST 24 100413660 ps
T586 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1150813009 Feb 18 01:23:32 PM PST 24 Feb 18 01:23:35 PM PST 24 261823601 ps
T587 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3088700721 Feb 18 01:23:42 PM PST 24 Feb 18 01:23:45 PM PST 24 491162318 ps
T588 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2029819780 Feb 18 01:23:39 PM PST 24 Feb 18 01:23:43 PM PST 24 504699549 ps
T589 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2508421295 Feb 18 01:22:49 PM PST 24 Feb 18 01:22:52 PM PST 24 216858879 ps
T590 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3805599393 Feb 18 01:23:42 PM PST 24 Feb 18 01:23:43 PM PST 24 57163325 ps
T591 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3546492168 Feb 18 01:23:19 PM PST 24 Feb 18 01:23:25 PM PST 24 1177293094 ps
T592 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3238661794 Feb 18 01:23:33 PM PST 24 Feb 18 01:23:38 PM PST 24 576166162 ps
T593 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.494284246 Feb 18 01:23:16 PM PST 24 Feb 18 01:23:23 PM PST 24 1186954431 ps
T594 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1110987027 Feb 18 01:23:16 PM PST 24 Feb 18 01:23:18 PM PST 24 84410290 ps
T595 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2872719763 Feb 18 01:23:29 PM PST 24 Feb 18 01:23:33 PM PST 24 425787767 ps
T596 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1644912192 Feb 18 01:22:56 PM PST 24 Feb 18 01:23:01 PM PST 24 206735842 ps
T597 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1248765748 Feb 18 01:23:32 PM PST 24 Feb 18 01:23:34 PM PST 24 459500302 ps
T598 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2280277510 Feb 18 01:23:34 PM PST 24 Feb 18 01:23:36 PM PST 24 61366948 ps
T148 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1542673875 Feb 18 01:23:23 PM PST 24 Feb 18 01:23:26 PM PST 24 424326125 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.919121099 Feb 18 01:22:49 PM PST 24 Feb 18 01:22:52 PM PST 24 170481783 ps
T600 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1623148803 Feb 18 01:23:24 PM PST 24 Feb 18 01:23:26 PM PST 24 227496431 ps
T601 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2778695270 Feb 18 01:23:35 PM PST 24 Feb 18 01:23:39 PM PST 24 452954637 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.868775633 Feb 18 01:23:24 PM PST 24 Feb 18 01:23:25 PM PST 24 60400663 ps
T603 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2094292815 Feb 18 01:23:49 PM PST 24 Feb 18 01:23:52 PM PST 24 308608585 ps
T604 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2225740554 Feb 18 01:23:41 PM PST 24 Feb 18 01:23:42 PM PST 24 80787992 ps
T605 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4067398026 Feb 18 01:23:25 PM PST 24 Feb 18 01:23:29 PM PST 24 459525144 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.489083640 Feb 18 01:23:49 PM PST 24 Feb 18 01:23:52 PM PST 24 272822184 ps
T607 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3430254377 Feb 18 01:23:36 PM PST 24 Feb 18 01:23:39 PM PST 24 128152610 ps
T608 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1782382526 Feb 18 01:23:42 PM PST 24 Feb 18 01:23:44 PM PST 24 446946810 ps
T609 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1233497529 Feb 18 01:23:29 PM PST 24 Feb 18 01:23:31 PM PST 24 69949783 ps
T610 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3259786819 Feb 18 01:23:49 PM PST 24 Feb 18 01:23:50 PM PST 24 62610412 ps
T611 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2748919754 Feb 18 01:24:00 PM PST 24 Feb 18 01:24:05 PM PST 24 629202942 ps
T612 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3956016637 Feb 18 01:23:40 PM PST 24 Feb 18 01:23:41 PM PST 24 72615772 ps
T613 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1827583697 Feb 18 01:23:41 PM PST 24 Feb 18 01:23:44 PM PST 24 501750738 ps
T614 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1142979800 Feb 18 01:23:23 PM PST 24 Feb 18 01:23:27 PM PST 24 426202258 ps
T615 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3636831182 Feb 18 01:23:30 PM PST 24 Feb 18 01:23:32 PM PST 24 135076016 ps
T616 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4286347545 Feb 18 01:23:59 PM PST 24 Feb 18 01:24:01 PM PST 24 194898658 ps
T617 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.78217152 Feb 18 01:23:29 PM PST 24 Feb 18 01:23:33 PM PST 24 177656823 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4059690380 Feb 18 01:22:49 PM PST 24 Feb 18 01:22:51 PM PST 24 80457086 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3074670248 Feb 18 01:23:25 PM PST 24 Feb 18 01:23:27 PM PST 24 83525999 ps
T132 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.762796770 Feb 18 01:23:36 PM PST 24 Feb 18 01:23:40 PM PST 24 898289168 ps
T620 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.860653601 Feb 18 01:23:50 PM PST 24 Feb 18 01:23:51 PM PST 24 62779446 ps

Test location /workspace/coverage/default/17.rstmgr_stress_all.2870564922
Short name T4
Test name
Test status
Simulation time 6439161246 ps
CPU time 26.08 seconds
Started Feb 18 12:51:44 PM PST 24
Finished Feb 18 12:52:15 PM PST 24
Peak memory 200784 kb
Host smart-59a6b979-5679-4dba-970b-7def627f546a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870564922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2870564922
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1222950617
Short name T75
Test name
Test status
Simulation time 326773459 ps
CPU time 2.15 seconds
Started Feb 18 12:52:17 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 200508 kb
Host smart-05382f0c-92a0-4c45-9bbf-a819ed22098a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222950617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1222950617
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.251270014
Short name T9
Test name
Test status
Simulation time 1234080388 ps
CPU time 5.64 seconds
Started Feb 18 12:51:34 PM PST 24
Finished Feb 18 12:51:40 PM PST 24
Peak memory 217828 kb
Host smart-df42b284-c90a-47f1-91ed-f527454e61f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251270014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.251270014
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.198556078
Short name T100
Test name
Test status
Simulation time 254815634 ps
CPU time 3.17 seconds
Started Feb 18 01:23:18 PM PST 24
Finished Feb 18 01:23:22 PM PST 24
Peak memory 208424 kb
Host smart-c611ced0-a645-4b73-923f-8c3d6103e24b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198556078 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.198556078
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.4068115255
Short name T84
Test name
Test status
Simulation time 17984842222 ps
CPU time 26.75 seconds
Started Feb 18 12:51:12 PM PST 24
Finished Feb 18 12:51:41 PM PST 24
Peak memory 218552 kb
Host smart-cb223366-f4e3-42a8-bd83-c626ce1dd068
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068115255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4068115255
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3569959013
Short name T80
Test name
Test status
Simulation time 880880156 ps
CPU time 3.17 seconds
Started Feb 18 01:23:26 PM PST 24
Finished Feb 18 01:23:30 PM PST 24
Peak memory 200228 kb
Host smart-fe00f78a-9ba3-4f31-88dc-51666f22f29a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569959013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3569959013
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3832914963
Short name T98
Test name
Test status
Simulation time 13984771422 ps
CPU time 47.89 seconds
Started Feb 18 12:51:33 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 200892 kb
Host smart-788fc829-0a20-4c20-bbad-cce5240c95ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832914963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3832914963
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3394799450
Short name T6
Test name
Test status
Simulation time 160116869 ps
CPU time 1.19 seconds
Started Feb 18 12:51:44 PM PST 24
Finished Feb 18 12:51:50 PM PST 24
Peak memory 200452 kb
Host smart-d0bc242a-0a58-4cc0-8bb9-a89a42fa3c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394799450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3394799450
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2566273952
Short name T32
Test name
Test status
Simulation time 2370084033 ps
CPU time 9.27 seconds
Started Feb 18 12:52:30 PM PST 24
Finished Feb 18 12:52:42 PM PST 24
Peak memory 218616 kb
Host smart-a3eb55ce-7a1b-4b1f-bb17-7b1525e194c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566273952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2566273952
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2718336404
Short name T22
Test name
Test status
Simulation time 62446247 ps
CPU time 0.75 seconds
Started Feb 18 12:51:09 PM PST 24
Finished Feb 18 12:51:12 PM PST 24
Peak memory 200420 kb
Host smart-e08b556a-dda5-4d0f-aa88-d7d14ab5f188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718336404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2718336404
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.892882952
Short name T130
Test name
Test status
Simulation time 892537904 ps
CPU time 3.11 seconds
Started Feb 18 01:23:32 PM PST 24
Finished Feb 18 01:23:36 PM PST 24
Peak memory 200200 kb
Host smart-bd426c2f-5c53-42e9-b0f9-3c9f18a91f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892882952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.892882952
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1646590559
Short name T30
Test name
Test status
Simulation time 2170092419 ps
CPU time 8.63 seconds
Started Feb 18 12:52:26 PM PST 24
Finished Feb 18 12:52:37 PM PST 24
Peak memory 222276 kb
Host smart-5b6304e9-2d38-4034-b02e-601eb23e61ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646590559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1646590559
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3104996394
Short name T103
Test name
Test status
Simulation time 615242521 ps
CPU time 3.7 seconds
Started Feb 18 01:23:31 PM PST 24
Finished Feb 18 01:23:36 PM PST 24
Peak memory 200212 kb
Host smart-d2fae81a-b7a6-4914-bbda-01d1f978c333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104996394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3104996394
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2656175221
Short name T1
Test name
Test status
Simulation time 124659312 ps
CPU time 0.95 seconds
Started Feb 18 12:51:07 PM PST 24
Finished Feb 18 12:51:10 PM PST 24
Peak memory 200392 kb
Host smart-03d06ab3-10a6-4162-99cb-51b168d24342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656175221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2656175221
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.490235209
Short name T101
Test name
Test status
Simulation time 776489473 ps
CPU time 3.03 seconds
Started Feb 18 01:23:29 PM PST 24
Finished Feb 18 01:23:34 PM PST 24
Peak memory 200180 kb
Host smart-8f175fe6-58d3-4ed2-9596-d3b796694e32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490235209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
490235209
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2423731550
Short name T78
Test name
Test status
Simulation time 73372543 ps
CPU time 0.77 seconds
Started Feb 18 01:23:34 PM PST 24
Finished Feb 18 01:23:35 PM PST 24
Peak memory 199976 kb
Host smart-4fa7bf33-6c74-4333-84d1-655a9902c211
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423731550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2423731550
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1581894820
Short name T21
Test name
Test status
Simulation time 209607483 ps
CPU time 0.94 seconds
Started Feb 18 12:51:33 PM PST 24
Finished Feb 18 12:51:35 PM PST 24
Peak memory 200328 kb
Host smart-687cbcb5-e050-401f-961c-d69f4c101d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581894820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1581894820
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2924429831
Short name T133
Test name
Test status
Simulation time 423574272 ps
CPU time 1.95 seconds
Started Feb 18 01:23:30 PM PST 24
Finished Feb 18 01:23:33 PM PST 24
Peak memory 200200 kb
Host smart-9c5ac2f5-97d5-4784-8461-431d8b8ff796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924429831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2924429831
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2135619790
Short name T28
Test name
Test status
Simulation time 6148710525 ps
CPU time 29.12 seconds
Started Feb 18 12:51:13 PM PST 24
Finished Feb 18 12:51:45 PM PST 24
Peak memory 200860 kb
Host smart-2956dd23-b849-4565-8816-1f5e2739d16f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135619790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2135619790
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2508421295
Short name T589
Test name
Test status
Simulation time 216858879 ps
CPU time 1.56 seconds
Started Feb 18 01:22:49 PM PST 24
Finished Feb 18 01:22:52 PM PST 24
Peak memory 200156 kb
Host smart-209aa106-a5c3-4f0e-aaa1-6d5b6c92d8a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508421295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
508421295
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.541137153
Short name T549
Test name
Test status
Simulation time 804611588 ps
CPU time 4.49 seconds
Started Feb 18 01:22:50 PM PST 24
Finished Feb 18 01:22:55 PM PST 24
Peak memory 200140 kb
Host smart-9db4798d-b4e1-4573-916d-cde338f6f683
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541137153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.541137153
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3417460699
Short name T560
Test name
Test status
Simulation time 125397559 ps
CPU time 0.84 seconds
Started Feb 18 01:22:49 PM PST 24
Finished Feb 18 01:22:51 PM PST 24
Peak memory 199896 kb
Host smart-53297754-11db-4535-832c-5e40ca0e2616
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417460699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
417460699
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1718495107
Short name T547
Test name
Test status
Simulation time 205541197 ps
CPU time 1.55 seconds
Started Feb 18 01:22:54 PM PST 24
Finished Feb 18 01:22:57 PM PST 24
Peak memory 200120 kb
Host smart-2748ea3e-bd32-4f40-91db-11be651cbabd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718495107 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1718495107
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2423856786
Short name T578
Test name
Test status
Simulation time 65457021 ps
CPU time 0.76 seconds
Started Feb 18 01:22:51 PM PST 24
Finished Feb 18 01:22:53 PM PST 24
Peak memory 199872 kb
Host smart-c8588662-1b28-4974-ab51-f40c9a3f75b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423856786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2423856786
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4059690380
Short name T618
Test name
Test status
Simulation time 80457086 ps
CPU time 0.95 seconds
Started Feb 18 01:22:49 PM PST 24
Finished Feb 18 01:22:51 PM PST 24
Peak memory 200040 kb
Host smart-05117471-5fb6-40ff-9653-e0f61b9d8633
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059690380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.4059690380
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2170992697
Short name T558
Test name
Test status
Simulation time 517416113 ps
CPU time 3.65 seconds
Started Feb 18 01:22:45 PM PST 24
Finished Feb 18 01:22:50 PM PST 24
Peak memory 200188 kb
Host smart-bfe41636-8dcf-4368-9703-90be5047f528
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170992697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2170992697
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1066434052
Short name T105
Test name
Test status
Simulation time 477658166 ps
CPU time 1.85 seconds
Started Feb 18 01:22:50 PM PST 24
Finished Feb 18 01:22:52 PM PST 24
Peak memory 200128 kb
Host smart-90d0a292-e914-407b-a99d-95070d9bce69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066434052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1066434052
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1644912192
Short name T596
Test name
Test status
Simulation time 206735842 ps
CPU time 1.53 seconds
Started Feb 18 01:22:56 PM PST 24
Finished Feb 18 01:23:01 PM PST 24
Peak memory 200068 kb
Host smart-1a62ab60-b734-4698-a4c4-9e1e25f83108
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644912192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
644912192
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1030807655
Short name T544
Test name
Test status
Simulation time 491374407 ps
CPU time 5.72 seconds
Started Feb 18 01:22:56 PM PST 24
Finished Feb 18 01:23:04 PM PST 24
Peak memory 200216 kb
Host smart-f11d4137-21ff-4d2c-a55c-4d6e7ca0d2f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030807655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
030807655
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3632471266
Short name T575
Test name
Test status
Simulation time 110620545 ps
CPU time 0.81 seconds
Started Feb 18 01:22:56 PM PST 24
Finished Feb 18 01:22:59 PM PST 24
Peak memory 199940 kb
Host smart-c6a4b9c1-3f4a-4799-ad2c-43c604610b11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632471266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
632471266
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3008687711
Short name T546
Test name
Test status
Simulation time 175499411 ps
CPU time 2.17 seconds
Started Feb 18 01:22:56 PM PST 24
Finished Feb 18 01:23:01 PM PST 24
Peak memory 208412 kb
Host smart-560e9ad2-e353-4904-8e11-a84c547344e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008687711 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3008687711
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3906840143
Short name T569
Test name
Test status
Simulation time 69914781 ps
CPU time 0.79 seconds
Started Feb 18 01:23:00 PM PST 24
Finished Feb 18 01:23:02 PM PST 24
Peak memory 199988 kb
Host smart-7fee2305-1026-423e-843c-b8a2162b6b49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906840143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3906840143
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1823025526
Short name T579
Test name
Test status
Simulation time 75199804 ps
CPU time 0.97 seconds
Started Feb 18 01:22:58 PM PST 24
Finished Feb 18 01:23:02 PM PST 24
Peak memory 200032 kb
Host smart-656ee146-2d05-4353-9ffc-9487aff6efff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823025526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1823025526
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.919121099
Short name T599
Test name
Test status
Simulation time 170481783 ps
CPU time 2.29 seconds
Started Feb 18 01:22:49 PM PST 24
Finished Feb 18 01:22:52 PM PST 24
Peak memory 200216 kb
Host smart-a5538c2a-f058-4b98-beaa-5e730b2f03a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919121099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.919121099
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1662140625
Short name T145
Test name
Test status
Simulation time 785154447 ps
CPU time 2.76 seconds
Started Feb 18 01:22:50 PM PST 24
Finished Feb 18 01:22:53 PM PST 24
Peak memory 200260 kb
Host smart-4dde663b-1a75-45bc-a39a-e475f2732255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662140625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1662140625
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3324656217
Short name T134
Test name
Test status
Simulation time 632698280 ps
CPU time 4.08 seconds
Started Feb 18 01:23:34 PM PST 24
Finished Feb 18 01:23:40 PM PST 24
Peak memory 208536 kb
Host smart-1b82623b-4607-47d1-b1db-6d295a014415
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324656217 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3324656217
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2280277510
Short name T598
Test name
Test status
Simulation time 61366948 ps
CPU time 0.75 seconds
Started Feb 18 01:23:34 PM PST 24
Finished Feb 18 01:23:36 PM PST 24
Peak memory 199980 kb
Host smart-ac595353-f68c-4070-9c86-63b517f37240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280277510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2280277510
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.761295092
Short name T563
Test name
Test status
Simulation time 72027724 ps
CPU time 0.93 seconds
Started Feb 18 01:23:33 PM PST 24
Finished Feb 18 01:23:34 PM PST 24
Peak memory 199880 kb
Host smart-68615f8b-6d2d-468d-a4b6-51664e0b2da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761295092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.761295092
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1248765748
Short name T597
Test name
Test status
Simulation time 459500302 ps
CPU time 1.8 seconds
Started Feb 18 01:23:32 PM PST 24
Finished Feb 18 01:23:34 PM PST 24
Peak memory 200268 kb
Host smart-795d964b-3765-4a26-99da-ce0f67de70e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248765748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1248765748
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1324295834
Short name T104
Test name
Test status
Simulation time 263615076 ps
CPU time 1.73 seconds
Started Feb 18 01:23:35 PM PST 24
Finished Feb 18 01:23:39 PM PST 24
Peak memory 208360 kb
Host smart-c655581e-b223-4f8f-a34e-912511f88942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324295834 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1324295834
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.822752450
Short name T124
Test name
Test status
Simulation time 121409293 ps
CPU time 1.03 seconds
Started Feb 18 01:23:33 PM PST 24
Finished Feb 18 01:23:35 PM PST 24
Peak memory 200012 kb
Host smart-48ea513e-ea68-481f-8481-d226714a6a17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822752450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.822752450
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3430254377
Short name T607
Test name
Test status
Simulation time 128152610 ps
CPU time 1.72 seconds
Started Feb 18 01:23:36 PM PST 24
Finished Feb 18 01:23:39 PM PST 24
Peak memory 200244 kb
Host smart-7d3da980-5b4c-4ba7-a861-2f8431899162
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430254377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3430254377
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1150813009
Short name T586
Test name
Test status
Simulation time 261823601 ps
CPU time 2.15 seconds
Started Feb 18 01:23:32 PM PST 24
Finished Feb 18 01:23:35 PM PST 24
Peak memory 208524 kb
Host smart-3bce15e9-7544-4002-bf16-8a868eac6e30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150813009 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1150813009
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1119426734
Short name T564
Test name
Test status
Simulation time 59240339 ps
CPU time 0.76 seconds
Started Feb 18 01:23:33 PM PST 24
Finished Feb 18 01:23:35 PM PST 24
Peak memory 199992 kb
Host smart-ee80308b-5cd5-40b6-892c-f2cd581df685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119426734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1119426734
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3792995393
Short name T576
Test name
Test status
Simulation time 88956737 ps
CPU time 1.03 seconds
Started Feb 18 01:23:35 PM PST 24
Finished Feb 18 01:23:38 PM PST 24
Peak memory 200024 kb
Host smart-3c7f0ec2-acc5-42bf-b382-f40a0caa1241
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792995393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3792995393
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3238661794
Short name T592
Test name
Test status
Simulation time 576166162 ps
CPU time 4.11 seconds
Started Feb 18 01:23:33 PM PST 24
Finished Feb 18 01:23:38 PM PST 24
Peak memory 200212 kb
Host smart-a5c8120e-835f-41a4-bf61-55ff7c13ca48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238661794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3238661794
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.762796770
Short name T132
Test name
Test status
Simulation time 898289168 ps
CPU time 2.86 seconds
Started Feb 18 01:23:36 PM PST 24
Finished Feb 18 01:23:40 PM PST 24
Peak memory 200228 kb
Host smart-e52ace8c-bfd4-4f75-8625-8197f30f0476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762796770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.762796770
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2624527928
Short name T545
Test name
Test status
Simulation time 287495127 ps
CPU time 1.94 seconds
Started Feb 18 01:23:40 PM PST 24
Finished Feb 18 01:23:43 PM PST 24
Peak memory 208576 kb
Host smart-eb552bb5-9e01-4d42-8ec7-dcfc26d0b006
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624527928 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2624527928
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3956016637
Short name T612
Test name
Test status
Simulation time 72615772 ps
CPU time 0.83 seconds
Started Feb 18 01:23:40 PM PST 24
Finished Feb 18 01:23:41 PM PST 24
Peak memory 199908 kb
Host smart-799bab25-e8ce-4d1f-a93f-89ab18e607dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956016637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3956016637
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1495450858
Short name T76
Test name
Test status
Simulation time 138232321 ps
CPU time 1.31 seconds
Started Feb 18 01:23:39 PM PST 24
Finished Feb 18 01:23:41 PM PST 24
Peak memory 200244 kb
Host smart-807d7db0-713e-4759-a4eb-61440aaf9ca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495450858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1495450858
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1417597287
Short name T577
Test name
Test status
Simulation time 274738987 ps
CPU time 2.02 seconds
Started Feb 18 01:23:32 PM PST 24
Finished Feb 18 01:23:35 PM PST 24
Peak memory 200248 kb
Host smart-0749d2a8-c956-4bc7-8375-e065ab34618e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417597287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1417597287
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2778695270
Short name T601
Test name
Test status
Simulation time 452954637 ps
CPU time 1.65 seconds
Started Feb 18 01:23:35 PM PST 24
Finished Feb 18 01:23:39 PM PST 24
Peak memory 200224 kb
Host smart-0c6f8911-cbd2-4aa2-8b9c-c2c0cc4c6c32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778695270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2778695270
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2029819780
Short name T588
Test name
Test status
Simulation time 504699549 ps
CPU time 3.07 seconds
Started Feb 18 01:23:39 PM PST 24
Finished Feb 18 01:23:43 PM PST 24
Peak memory 200264 kb
Host smart-39a39897-0119-4b73-b20d-d834362a755a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029819780 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2029819780
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3805599393
Short name T590
Test name
Test status
Simulation time 57163325 ps
CPU time 0.73 seconds
Started Feb 18 01:23:42 PM PST 24
Finished Feb 18 01:23:43 PM PST 24
Peak memory 199828 kb
Host smart-d8f3dca2-b0fc-431e-a044-c9e207339fd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805599393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3805599393
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.430130026
Short name T123
Test name
Test status
Simulation time 126195847 ps
CPU time 1 seconds
Started Feb 18 01:23:42 PM PST 24
Finished Feb 18 01:23:44 PM PST 24
Peak memory 199940 kb
Host smart-184fbba4-c09f-4281-a78c-cb2296923ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430130026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.430130026
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1966282784
Short name T548
Test name
Test status
Simulation time 94731074 ps
CPU time 1.24 seconds
Started Feb 18 01:23:44 PM PST 24
Finished Feb 18 01:23:46 PM PST 24
Peak memory 199992 kb
Host smart-3eeeab84-e2d7-46f6-b6a5-972b45792de3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966282784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1966282784
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1782382526
Short name T608
Test name
Test status
Simulation time 446946810 ps
CPU time 1.65 seconds
Started Feb 18 01:23:42 PM PST 24
Finished Feb 18 01:23:44 PM PST 24
Peak memory 200128 kb
Host smart-d2fd3147-745f-4265-852b-f9cd547569b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782382526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1782382526
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.983350064
Short name T102
Test name
Test status
Simulation time 504368600 ps
CPU time 3.37 seconds
Started Feb 18 01:23:43 PM PST 24
Finished Feb 18 01:23:47 PM PST 24
Peak memory 216712 kb
Host smart-0c8fc8ae-e921-4fa4-b05a-453533f6ea96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983350064 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.983350064
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3072452886
Short name T129
Test name
Test status
Simulation time 60479991 ps
CPU time 0.75 seconds
Started Feb 18 01:23:42 PM PST 24
Finished Feb 18 01:23:43 PM PST 24
Peak memory 199900 kb
Host smart-5bee381a-9707-4b41-b1f9-5624d4f8b10f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072452886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3072452886
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2225740554
Short name T604
Test name
Test status
Simulation time 80787992 ps
CPU time 0.92 seconds
Started Feb 18 01:23:41 PM PST 24
Finished Feb 18 01:23:42 PM PST 24
Peak memory 200032 kb
Host smart-06c06164-4bfc-49ba-acf7-26cb37c96cba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225740554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2225740554
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3088700721
Short name T587
Test name
Test status
Simulation time 491162318 ps
CPU time 2.92 seconds
Started Feb 18 01:23:42 PM PST 24
Finished Feb 18 01:23:45 PM PST 24
Peak memory 208436 kb
Host smart-ce4be367-08b0-40f5-919b-f3c485dc5761
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088700721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3088700721
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1827583697
Short name T613
Test name
Test status
Simulation time 501750738 ps
CPU time 2.12 seconds
Started Feb 18 01:23:41 PM PST 24
Finished Feb 18 01:23:44 PM PST 24
Peak memory 200188 kb
Host smart-23f512e2-f9cb-49b2-8eae-5d0933241ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827583697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1827583697
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3645096302
Short name T540
Test name
Test status
Simulation time 603403583 ps
CPU time 3.86 seconds
Started Feb 18 01:23:50 PM PST 24
Finished Feb 18 01:23:55 PM PST 24
Peak memory 211244 kb
Host smart-4631935b-2312-4810-9fcd-8f924f91ba8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645096302 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3645096302
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.780334288
Short name T572
Test name
Test status
Simulation time 70284507 ps
CPU time 0.78 seconds
Started Feb 18 01:23:51 PM PST 24
Finished Feb 18 01:23:52 PM PST 24
Peak memory 199976 kb
Host smart-18b93935-2bbc-42c8-939c-187f01abf390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780334288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.780334288
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1186791265
Short name T581
Test name
Test status
Simulation time 130743970 ps
CPU time 1.21 seconds
Started Feb 18 01:23:50 PM PST 24
Finished Feb 18 01:23:52 PM PST 24
Peak memory 200276 kb
Host smart-c64f7328-bb3a-48a4-962b-0f829eeddb4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186791265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1186791265
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3047287681
Short name T82
Test name
Test status
Simulation time 539374723 ps
CPU time 3.71 seconds
Started Feb 18 01:23:41 PM PST 24
Finished Feb 18 01:23:46 PM PST 24
Peak memory 200236 kb
Host smart-fafd6a0f-fffe-4a9c-8ed4-7a3e3ce60478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047287681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3047287681
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1479148671
Short name T570
Test name
Test status
Simulation time 912035054 ps
CPU time 2.62 seconds
Started Feb 18 01:23:41 PM PST 24
Finished Feb 18 01:23:44 PM PST 24
Peak memory 200256 kb
Host smart-1351f053-2d53-4a54-be6e-083201d331a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479148671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1479148671
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2094292815
Short name T603
Test name
Test status
Simulation time 308608585 ps
CPU time 2.18 seconds
Started Feb 18 01:23:49 PM PST 24
Finished Feb 18 01:23:52 PM PST 24
Peak memory 209268 kb
Host smart-76a8c606-b80e-4d52-b70c-12ed8b627930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094292815 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2094292815
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.860653601
Short name T620
Test name
Test status
Simulation time 62779446 ps
CPU time 0.72 seconds
Started Feb 18 01:23:50 PM PST 24
Finished Feb 18 01:23:51 PM PST 24
Peak memory 199976 kb
Host smart-48900298-6a26-4454-a0c5-fa41ae1ff405
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860653601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.860653601
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3718558641
Short name T565
Test name
Test status
Simulation time 239111607 ps
CPU time 1.49 seconds
Started Feb 18 01:23:51 PM PST 24
Finished Feb 18 01:23:53 PM PST 24
Peak memory 200208 kb
Host smart-cd101136-7dbb-4675-882c-a632623a646f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718558641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3718558641
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3232815355
Short name T106
Test name
Test status
Simulation time 182109010 ps
CPU time 2.45 seconds
Started Feb 18 01:23:51 PM PST 24
Finished Feb 18 01:23:54 PM PST 24
Peak memory 200284 kb
Host smart-73512d81-4033-41db-9ece-5ee02e6058c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232815355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3232815355
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1111340892
Short name T568
Test name
Test status
Simulation time 892494605 ps
CPU time 2.9 seconds
Started Feb 18 01:23:51 PM PST 24
Finished Feb 18 01:23:54 PM PST 24
Peak memory 200224 kb
Host smart-f72d5849-b76c-4f8a-83a1-d22163d31539
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111340892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1111340892
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.641926192
Short name T551
Test name
Test status
Simulation time 178499710 ps
CPU time 1.95 seconds
Started Feb 18 01:23:54 PM PST 24
Finished Feb 18 01:23:57 PM PST 24
Peak memory 208520 kb
Host smart-4a882059-a996-4d7b-830f-7e6127703b0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641926192 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.641926192
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3259786819
Short name T610
Test name
Test status
Simulation time 62610412 ps
CPU time 0.76 seconds
Started Feb 18 01:23:49 PM PST 24
Finished Feb 18 01:23:50 PM PST 24
Peak memory 199976 kb
Host smart-89dd9033-4c12-4af2-acab-bcb3469d5f45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259786819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3259786819
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.799999955
Short name T128
Test name
Test status
Simulation time 85120355 ps
CPU time 0.93 seconds
Started Feb 18 01:23:49 PM PST 24
Finished Feb 18 01:23:50 PM PST 24
Peak memory 200028 kb
Host smart-e53ae076-d3a5-4411-b465-060f7945865d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799999955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.799999955
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.489083640
Short name T606
Test name
Test status
Simulation time 272822184 ps
CPU time 2.05 seconds
Started Feb 18 01:23:49 PM PST 24
Finished Feb 18 01:23:52 PM PST 24
Peak memory 200176 kb
Host smart-82655c27-b99d-4962-b397-789d647e7ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489083640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.489083640
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1081852159
Short name T77
Test name
Test status
Simulation time 486030655 ps
CPU time 2 seconds
Started Feb 18 01:23:49 PM PST 24
Finished Feb 18 01:23:51 PM PST 24
Peak memory 200268 kb
Host smart-e01f07c9-4774-4abf-9086-85aa651a0d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081852159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1081852159
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2748919754
Short name T611
Test name
Test status
Simulation time 629202942 ps
CPU time 3.71 seconds
Started Feb 18 01:24:00 PM PST 24
Finished Feb 18 01:24:05 PM PST 24
Peak memory 200292 kb
Host smart-b67d3c4e-a994-41b2-a3eb-026546f75d8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748919754 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2748919754
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1302131173
Short name T567
Test name
Test status
Simulation time 87147360 ps
CPU time 0.88 seconds
Started Feb 18 01:24:00 PM PST 24
Finished Feb 18 01:24:02 PM PST 24
Peak memory 199876 kb
Host smart-100d8557-7830-4581-b250-3e3c9f0c090a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302131173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1302131173
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.647331565
Short name T126
Test name
Test status
Simulation time 112774665 ps
CPU time 1.3 seconds
Started Feb 18 01:24:03 PM PST 24
Finished Feb 18 01:24:05 PM PST 24
Peak memory 200240 kb
Host smart-b58cbd91-73a7-4fc7-aa53-e54dacc292b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647331565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.647331565
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4286347545
Short name T616
Test name
Test status
Simulation time 194898658 ps
CPU time 1.65 seconds
Started Feb 18 01:23:59 PM PST 24
Finished Feb 18 01:24:01 PM PST 24
Peak memory 200108 kb
Host smart-2b7133d8-d8db-4f1b-9faa-e12aaac797bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286347545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4286347545
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1810387201
Short name T582
Test name
Test status
Simulation time 475068227 ps
CPU time 1.97 seconds
Started Feb 18 01:24:01 PM PST 24
Finished Feb 18 01:24:03 PM PST 24
Peak memory 200144 kb
Host smart-775049ac-3fdd-4b5b-b21f-ababb8f45a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810387201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1810387201
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2350787224
Short name T541
Test name
Test status
Simulation time 151236542 ps
CPU time 1.92 seconds
Started Feb 18 01:23:06 PM PST 24
Finished Feb 18 01:23:09 PM PST 24
Peak memory 200228 kb
Host smart-c14789de-6dd1-44b9-8e4a-35ef3da78624
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350787224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
350787224
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.172497676
Short name T543
Test name
Test status
Simulation time 489701574 ps
CPU time 6.01 seconds
Started Feb 18 01:23:10 PM PST 24
Finished Feb 18 01:23:17 PM PST 24
Peak memory 200128 kb
Host smart-53154442-1ccc-4a16-8ee8-3d6e2afec341
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172497676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.172497676
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3662088995
Short name T583
Test name
Test status
Simulation time 142739373 ps
CPU time 0.92 seconds
Started Feb 18 01:23:09 PM PST 24
Finished Feb 18 01:23:12 PM PST 24
Peak memory 199960 kb
Host smart-000a7905-47db-4dd9-adc2-d884486a48a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662088995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
662088995
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1867291813
Short name T557
Test name
Test status
Simulation time 578252293 ps
CPU time 3.24 seconds
Started Feb 18 01:23:07 PM PST 24
Finished Feb 18 01:23:11 PM PST 24
Peak memory 211288 kb
Host smart-c4e9eb0b-e5c1-4743-9801-65dcd5368821
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867291813 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1867291813
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3298803792
Short name T559
Test name
Test status
Simulation time 70746099 ps
CPU time 0.77 seconds
Started Feb 18 01:23:09 PM PST 24
Finished Feb 18 01:23:11 PM PST 24
Peak memory 199968 kb
Host smart-d0d488cc-8662-4071-b1a8-602ebe9989d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298803792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3298803792
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2825630186
Short name T554
Test name
Test status
Simulation time 78206349 ps
CPU time 0.92 seconds
Started Feb 18 01:23:06 PM PST 24
Finished Feb 18 01:23:08 PM PST 24
Peak memory 199964 kb
Host smart-1cd87b2f-4bb6-4830-be03-cc04acd57664
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825630186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2825630186
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3112582281
Short name T573
Test name
Test status
Simulation time 240917024 ps
CPU time 1.89 seconds
Started Feb 18 01:22:56 PM PST 24
Finished Feb 18 01:23:00 PM PST 24
Peak memory 200236 kb
Host smart-47a3cb84-61fa-42e5-bc16-7092c0f23fc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112582281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3112582281
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.818538311
Short name T131
Test name
Test status
Simulation time 915744370 ps
CPU time 3.31 seconds
Started Feb 18 01:23:00 PM PST 24
Finished Feb 18 01:23:05 PM PST 24
Peak memory 200292 kb
Host smart-592574ac-a478-4bfa-929c-ae38fa376ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818538311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
818538311
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3867099480
Short name T538
Test name
Test status
Simulation time 235696614 ps
CPU time 1.61 seconds
Started Feb 18 01:23:18 PM PST 24
Finished Feb 18 01:23:20 PM PST 24
Peak memory 200160 kb
Host smart-e7239cbf-0994-4016-9500-d7a88202a53f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867099480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
867099480
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.494284246
Short name T593
Test name
Test status
Simulation time 1186954431 ps
CPU time 5.69 seconds
Started Feb 18 01:23:16 PM PST 24
Finished Feb 18 01:23:23 PM PST 24
Peak memory 200156 kb
Host smart-76650470-4b59-49cf-8c9d-4409e53e1cc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494284246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.494284246
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.212198294
Short name T561
Test name
Test status
Simulation time 93442112 ps
CPU time 0.76 seconds
Started Feb 18 01:23:17 PM PST 24
Finished Feb 18 01:23:18 PM PST 24
Peak memory 199892 kb
Host smart-0f3bda00-a152-4077-8072-fcefe4aae4bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212198294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.212198294
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1110987027
Short name T594
Test name
Test status
Simulation time 84410290 ps
CPU time 0.82 seconds
Started Feb 18 01:23:16 PM PST 24
Finished Feb 18 01:23:18 PM PST 24
Peak memory 199988 kb
Host smart-2c9f8aed-eca8-4e4f-b7bc-e5a6fc1ead52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110987027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1110987027
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.442405541
Short name T79
Test name
Test status
Simulation time 75277194 ps
CPU time 0.97 seconds
Started Feb 18 01:23:18 PM PST 24
Finished Feb 18 01:23:20 PM PST 24
Peak memory 200024 kb
Host smart-37d61f0e-a194-429e-829a-f625eaf8a919
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442405541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.442405541
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3989551701
Short name T542
Test name
Test status
Simulation time 447318484 ps
CPU time 2.94 seconds
Started Feb 18 01:23:17 PM PST 24
Finished Feb 18 01:23:21 PM PST 24
Peak memory 200140 kb
Host smart-726e6b42-f5b0-42dc-b04c-dc2b853129c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989551701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3989551701
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2695906552
Short name T147
Test name
Test status
Simulation time 864586064 ps
CPU time 2.78 seconds
Started Feb 18 01:23:17 PM PST 24
Finished Feb 18 01:23:20 PM PST 24
Peak memory 200228 kb
Host smart-de35e181-1a24-4037-9fd5-2eb1e7dbf13b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695906552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2695906552
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4067398026
Short name T605
Test name
Test status
Simulation time 459525144 ps
CPU time 2.57 seconds
Started Feb 18 01:23:25 PM PST 24
Finished Feb 18 01:23:29 PM PST 24
Peak memory 200060 kb
Host smart-199d11d3-2355-4838-94cf-c1b456f7bf42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067398026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.4
067398026
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3546492168
Short name T591
Test name
Test status
Simulation time 1177293094 ps
CPU time 5.29 seconds
Started Feb 18 01:23:19 PM PST 24
Finished Feb 18 01:23:25 PM PST 24
Peak memory 200144 kb
Host smart-ac07d437-6c55-4272-b11f-bec943a6c3ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546492168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
546492168
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1564645112
Short name T580
Test name
Test status
Simulation time 87535589 ps
CPU time 0.76 seconds
Started Feb 18 01:23:23 PM PST 24
Finished Feb 18 01:23:25 PM PST 24
Peak memory 199952 kb
Host smart-57525a7d-d5ff-42b5-a639-b3e7e7ed1800
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564645112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
564645112
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.803404582
Short name T552
Test name
Test status
Simulation time 395374292 ps
CPU time 2.56 seconds
Started Feb 18 01:23:35 PM PST 24
Finished Feb 18 01:23:39 PM PST 24
Peak memory 208496 kb
Host smart-1f87582f-99b0-42b0-876a-30fe65690e07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803404582 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.803404582
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.868775633
Short name T602
Test name
Test status
Simulation time 60400663 ps
CPU time 0.73 seconds
Started Feb 18 01:23:24 PM PST 24
Finished Feb 18 01:23:25 PM PST 24
Peak memory 199984 kb
Host smart-26068b6e-267d-40e4-81a0-a82087e1283c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868775633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.868775633
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3074670248
Short name T619
Test name
Test status
Simulation time 83525999 ps
CPU time 0.92 seconds
Started Feb 18 01:23:25 PM PST 24
Finished Feb 18 01:23:27 PM PST 24
Peak memory 200020 kb
Host smart-4c6425eb-0eb4-48f1-83c7-848138c642c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074670248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3074670248
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.439208475
Short name T550
Test name
Test status
Simulation time 272692107 ps
CPU time 2.1 seconds
Started Feb 18 01:23:16 PM PST 24
Finished Feb 18 01:23:18 PM PST 24
Peak memory 200188 kb
Host smart-72485ef8-4d13-40b2-9cdd-bed98f374378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439208475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.439208475
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2834213224
Short name T146
Test name
Test status
Simulation time 463997880 ps
CPU time 1.97 seconds
Started Feb 18 01:23:18 PM PST 24
Finished Feb 18 01:23:21 PM PST 24
Peak memory 200244 kb
Host smart-f7c3f3f4-e602-4b74-acc1-7871dcd9c1da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834213224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2834213224
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1142979800
Short name T614
Test name
Test status
Simulation time 426202258 ps
CPU time 2.66 seconds
Started Feb 18 01:23:23 PM PST 24
Finished Feb 18 01:23:27 PM PST 24
Peak memory 208500 kb
Host smart-39b7ba4f-1d2d-4b23-9682-03929a9e2f69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142979800 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1142979800
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2133803695
Short name T127
Test name
Test status
Simulation time 73453676 ps
CPU time 0.81 seconds
Started Feb 18 01:23:23 PM PST 24
Finished Feb 18 01:23:25 PM PST 24
Peak memory 199988 kb
Host smart-127e4ccd-78b7-4db9-8d5b-c6644ecc813f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133803695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2133803695
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3240935734
Short name T553
Test name
Test status
Simulation time 134986545 ps
CPU time 1.27 seconds
Started Feb 18 01:23:28 PM PST 24
Finished Feb 18 01:23:29 PM PST 24
Peak memory 200224 kb
Host smart-86356a86-4d5d-47f7-8f89-6e733f2a97fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240935734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3240935734
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3264677224
Short name T83
Test name
Test status
Simulation time 180624341 ps
CPU time 2.5 seconds
Started Feb 18 01:23:25 PM PST 24
Finished Feb 18 01:23:28 PM PST 24
Peak memory 216192 kb
Host smart-9228a55c-feb1-4693-9064-38646f001cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264677224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3264677224
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1542673875
Short name T148
Test name
Test status
Simulation time 424326125 ps
CPU time 1.67 seconds
Started Feb 18 01:23:23 PM PST 24
Finished Feb 18 01:23:26 PM PST 24
Peak memory 200232 kb
Host smart-4803a78a-c18c-473f-a2a4-ba0cbfe66bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542673875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1542673875
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1953880573
Short name T555
Test name
Test status
Simulation time 164239709 ps
CPU time 1.83 seconds
Started Feb 18 01:23:29 PM PST 24
Finished Feb 18 01:23:31 PM PST 24
Peak memory 208508 kb
Host smart-6ebbe14a-b3b2-4e1c-a9a6-92ed3f041e83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953880573 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1953880573
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1857687628
Short name T539
Test name
Test status
Simulation time 74576884 ps
CPU time 0.77 seconds
Started Feb 18 01:23:23 PM PST 24
Finished Feb 18 01:23:24 PM PST 24
Peak memory 199912 kb
Host smart-ddbd5063-ce82-4cdf-8a7d-0986808a49d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857687628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1857687628
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1663396399
Short name T556
Test name
Test status
Simulation time 230982024 ps
CPU time 1.52 seconds
Started Feb 18 01:23:26 PM PST 24
Finished Feb 18 01:23:28 PM PST 24
Peak memory 200264 kb
Host smart-40e5325d-6917-4528-95a8-4cc450fa42e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663396399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1663396399
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1623148803
Short name T600
Test name
Test status
Simulation time 227496431 ps
CPU time 1.76 seconds
Started Feb 18 01:23:24 PM PST 24
Finished Feb 18 01:23:26 PM PST 24
Peak memory 200168 kb
Host smart-5bb4292f-84ee-4989-a288-bf915e9f6798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623148803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1623148803
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1151569998
Short name T144
Test name
Test status
Simulation time 412905093 ps
CPU time 1.85 seconds
Started Feb 18 01:23:23 PM PST 24
Finished Feb 18 01:23:26 PM PST 24
Peak memory 200208 kb
Host smart-f333bf3d-b5bd-40a0-a402-082f04d89255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151569998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1151569998
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2011064742
Short name T81
Test name
Test status
Simulation time 265375146 ps
CPU time 1.9 seconds
Started Feb 18 01:23:35 PM PST 24
Finished Feb 18 01:23:39 PM PST 24
Peak memory 208808 kb
Host smart-68000421-d0e3-48a2-b0fa-25c0b61d1b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011064742 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2011064742
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.302683340
Short name T562
Test name
Test status
Simulation time 65369959 ps
CPU time 0.73 seconds
Started Feb 18 01:23:25 PM PST 24
Finished Feb 18 01:23:27 PM PST 24
Peak memory 199868 kb
Host smart-ca0e3d2d-7a5c-488c-98a9-1b4ef65ba1b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302683340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.302683340
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3636831182
Short name T615
Test name
Test status
Simulation time 135076016 ps
CPU time 1.04 seconds
Started Feb 18 01:23:30 PM PST 24
Finished Feb 18 01:23:32 PM PST 24
Peak memory 200020 kb
Host smart-25db1896-20dc-4929-a593-8f53cf61e069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636831182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3636831182
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3464394748
Short name T585
Test name
Test status
Simulation time 100413660 ps
CPU time 1.21 seconds
Started Feb 18 01:23:23 PM PST 24
Finished Feb 18 01:23:26 PM PST 24
Peak memory 200184 kb
Host smart-6a948b15-57ad-4951-8101-1cac37e6f090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464394748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3464394748
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2071207556
Short name T584
Test name
Test status
Simulation time 160858868 ps
CPU time 1.92 seconds
Started Feb 18 01:23:25 PM PST 24
Finished Feb 18 01:23:28 PM PST 24
Peak memory 208484 kb
Host smart-101fd1ce-abba-49fb-b70f-114f42550481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071207556 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2071207556
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3423748128
Short name T574
Test name
Test status
Simulation time 62157102 ps
CPU time 0.79 seconds
Started Feb 18 01:23:29 PM PST 24
Finished Feb 18 01:23:31 PM PST 24
Peak memory 199968 kb
Host smart-b48bd652-d211-4ff5-8ebc-aea5f31a6b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423748128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3423748128
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4062706103
Short name T125
Test name
Test status
Simulation time 110037687 ps
CPU time 0.96 seconds
Started Feb 18 01:23:25 PM PST 24
Finished Feb 18 01:23:27 PM PST 24
Peak memory 200036 kb
Host smart-1f6600a3-6b92-42df-a57b-2d4a4d4f5550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062706103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4062706103
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.78217152
Short name T617
Test name
Test status
Simulation time 177656823 ps
CPU time 2.33 seconds
Started Feb 18 01:23:29 PM PST 24
Finished Feb 18 01:23:33 PM PST 24
Peak memory 208368 kb
Host smart-ab48228a-20af-4454-ab2d-32b43be35436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78217152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.78217152
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2232190042
Short name T566
Test name
Test status
Simulation time 211983274 ps
CPU time 1.59 seconds
Started Feb 18 01:23:36 PM PST 24
Finished Feb 18 01:23:39 PM PST 24
Peak memory 209536 kb
Host smart-b327dd94-58bb-4fde-ae0c-087d9d872050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232190042 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2232190042
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1233497529
Short name T609
Test name
Test status
Simulation time 69949783 ps
CPU time 0.75 seconds
Started Feb 18 01:23:29 PM PST 24
Finished Feb 18 01:23:31 PM PST 24
Peak memory 199968 kb
Host smart-ec873904-f29b-4540-a50a-69264bcbd974
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233497529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1233497529
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.524296423
Short name T571
Test name
Test status
Simulation time 270237482 ps
CPU time 1.76 seconds
Started Feb 18 01:23:35 PM PST 24
Finished Feb 18 01:23:38 PM PST 24
Peak memory 200260 kb
Host smart-9d78448e-9672-49e9-8d8e-61150753b9c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524296423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.524296423
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2872719763
Short name T595
Test name
Test status
Simulation time 425787767 ps
CPU time 2.91 seconds
Started Feb 18 01:23:29 PM PST 24
Finished Feb 18 01:23:33 PM PST 24
Peak memory 200224 kb
Host smart-80b16da3-749b-4893-8e89-abe0a94593b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872719763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2872719763
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1096481708
Short name T33
Test name
Test status
Simulation time 1895750632 ps
CPU time 7.27 seconds
Started Feb 18 12:51:13 PM PST 24
Finished Feb 18 12:51:24 PM PST 24
Peak memory 221308 kb
Host smart-7e8cf4d5-4ee3-451d-b7bf-2b5abfd1146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096481708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1096481708
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.153186718
Short name T416
Test name
Test status
Simulation time 243782854 ps
CPU time 1.11 seconds
Started Feb 18 12:51:14 PM PST 24
Finished Feb 18 12:51:19 PM PST 24
Peak memory 217740 kb
Host smart-173f0de2-63d4-4030-8c3f-89c52038e275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153186718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.153186718
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3171280495
Short name T491
Test name
Test status
Simulation time 227375481 ps
CPU time 0.96 seconds
Started Feb 18 12:51:08 PM PST 24
Finished Feb 18 12:51:11 PM PST 24
Peak memory 199724 kb
Host smart-1c7890db-73bf-434b-b6c9-7c54bf91defe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171280495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3171280495
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2050773822
Short name T296
Test name
Test status
Simulation time 1376159958 ps
CPU time 5.65 seconds
Started Feb 18 12:51:14 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 200692 kb
Host smart-7ec24f56-03b8-4200-be79-949e54fb5be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050773822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2050773822
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1762032102
Short name T497
Test name
Test status
Simulation time 168330176 ps
CPU time 1.12 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 200436 kb
Host smart-6849aac4-4ead-4f01-8b94-05dcaf9d0992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762032102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1762032102
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3877445256
Short name T382
Test name
Test status
Simulation time 217201435 ps
CPU time 1.36 seconds
Started Feb 18 12:51:07 PM PST 24
Finished Feb 18 12:51:10 PM PST 24
Peak memory 200720 kb
Host smart-6ce438b6-a375-4ab2-94bc-8796d607489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877445256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3877445256
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1407793251
Short name T481
Test name
Test status
Simulation time 12553298934 ps
CPU time 47.44 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:52:09 PM PST 24
Peak memory 200924 kb
Host smart-9a3a6058-e2ec-41b4-b5b9-f1d7a0cf18f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407793251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1407793251
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.581420759
Short name T73
Test name
Test status
Simulation time 372319014 ps
CPU time 2.44 seconds
Started Feb 18 12:51:16 PM PST 24
Finished Feb 18 12:51:22 PM PST 24
Peak memory 200480 kb
Host smart-7408ce05-368a-4b8a-87a5-af63016e61d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581420759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.581420759
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2078697148
Short name T195
Test name
Test status
Simulation time 127073325 ps
CPU time 0.96 seconds
Started Feb 18 12:51:12 PM PST 24
Finished Feb 18 12:51:15 PM PST 24
Peak memory 200500 kb
Host smart-add186aa-0b42-4959-bf97-06da6f739c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078697148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2078697148
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3604027769
Short name T159
Test name
Test status
Simulation time 68911518 ps
CPU time 0.8 seconds
Started Feb 18 12:51:13 PM PST 24
Finished Feb 18 12:51:16 PM PST 24
Peak memory 200384 kb
Host smart-9806375e-19ba-4c5b-b9ce-912e4170f541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604027769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3604027769
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.27581528
Short name T38
Test name
Test status
Simulation time 1228661493 ps
CPU time 6.85 seconds
Started Feb 18 12:51:08 PM PST 24
Finished Feb 18 12:51:17 PM PST 24
Peak memory 217880 kb
Host smart-131d716c-f399-45e4-94e9-7449209ab777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27581528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.27581528
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3591918147
Short name T537
Test name
Test status
Simulation time 243074208 ps
CPU time 1.1 seconds
Started Feb 18 12:51:18 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 217736 kb
Host smart-7f4eda47-afd0-46c1-9db3-cd4bf627f3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591918147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3591918147
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1806935633
Short name T437
Test name
Test status
Simulation time 176784117 ps
CPU time 0.82 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 200236 kb
Host smart-8fd50f3c-3860-4d1c-982b-58c63e0276b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806935633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1806935633
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.82249392
Short name T533
Test name
Test status
Simulation time 1777756338 ps
CPU time 6.28 seconds
Started Feb 18 12:51:07 PM PST 24
Finished Feb 18 12:51:15 PM PST 24
Peak memory 200812 kb
Host smart-2030e3f4-d239-4f5f-8b1c-d5babeb6c691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82249392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.82249392
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3222220073
Short name T89
Test name
Test status
Simulation time 26460941062 ps
CPU time 43.44 seconds
Started Feb 18 12:51:07 PM PST 24
Finished Feb 18 12:51:53 PM PST 24
Peak memory 218396 kb
Host smart-177d7964-75f7-4e7f-ada6-e86be2ef03d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222220073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3222220073
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3790873208
Short name T277
Test name
Test status
Simulation time 102860984 ps
CPU time 1.03 seconds
Started Feb 18 12:51:09 PM PST 24
Finished Feb 18 12:51:12 PM PST 24
Peak memory 200556 kb
Host smart-f89f346c-5db4-427c-9841-7b67c3c59a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790873208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3790873208
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.975957294
Short name T468
Test name
Test status
Simulation time 107534897 ps
CPU time 1.16 seconds
Started Feb 18 12:51:13 PM PST 24
Finished Feb 18 12:51:16 PM PST 24
Peak memory 200684 kb
Host smart-7c3c1c4b-9c95-4ead-ac12-51cf8db834fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975957294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.975957294
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3257932676
Short name T191
Test name
Test status
Simulation time 7792049952 ps
CPU time 30.88 seconds
Started Feb 18 12:51:17 PM PST 24
Finished Feb 18 12:51:51 PM PST 24
Peak memory 200860 kb
Host smart-417e7b06-0d7f-4079-9cae-0d0d03d43f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257932676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3257932676
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3046008237
Short name T438
Test name
Test status
Simulation time 346500830 ps
CPU time 2.12 seconds
Started Feb 18 12:51:06 PM PST 24
Finished Feb 18 12:51:10 PM PST 24
Peak memory 200488 kb
Host smart-94b6e598-8417-47eb-8101-8f05cd661e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046008237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3046008237
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1633525313
Short name T167
Test name
Test status
Simulation time 65699343 ps
CPU time 0.71 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:31 PM PST 24
Peak memory 200408 kb
Host smart-a267615d-73f6-42c0-bf2e-f7652115f0e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633525313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1633525313
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1080146834
Short name T366
Test name
Test status
Simulation time 1221752163 ps
CPU time 5.71 seconds
Started Feb 18 12:51:27 PM PST 24
Finished Feb 18 12:51:35 PM PST 24
Peak memory 217820 kb
Host smart-5c50c538-999a-49ac-b7c9-204b4e0eed44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080146834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1080146834
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1718193566
Short name T245
Test name
Test status
Simulation time 244124928 ps
CPU time 1.14 seconds
Started Feb 18 12:51:27 PM PST 24
Finished Feb 18 12:51:30 PM PST 24
Peak memory 217844 kb
Host smart-48b6140d-532e-40e3-9441-fc4bb36cfb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718193566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1718193566
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3242109492
Short name T249
Test name
Test status
Simulation time 219995288 ps
CPU time 0.89 seconds
Started Feb 18 12:51:23 PM PST 24
Finished Feb 18 12:51:27 PM PST 24
Peak memory 200156 kb
Host smart-5d019669-d7b1-4760-ac09-c5c2e1d069fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242109492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3242109492
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.288514146
Short name T347
Test name
Test status
Simulation time 897450542 ps
CPU time 4.17 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:35 PM PST 24
Peak memory 200776 kb
Host smart-eb5c7026-0ed6-4278-89b9-0ef13308ce4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288514146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.288514146
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2574581494
Short name T531
Test name
Test status
Simulation time 146231225 ps
CPU time 1.14 seconds
Started Feb 18 12:51:27 PM PST 24
Finished Feb 18 12:51:30 PM PST 24
Peak memory 200460 kb
Host smart-c083405a-82ae-4750-83bd-c30c4793e826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574581494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2574581494
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2810507711
Short name T161
Test name
Test status
Simulation time 120987976 ps
CPU time 1.16 seconds
Started Feb 18 12:51:26 PM PST 24
Finished Feb 18 12:51:29 PM PST 24
Peak memory 200692 kb
Host smart-ac48c35e-9008-4871-ad71-68003519cd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810507711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2810507711
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2331091139
Short name T305
Test name
Test status
Simulation time 6510425246 ps
CPU time 22.74 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:53 PM PST 24
Peak memory 200788 kb
Host smart-fe2fc4b9-72bf-4571-bad7-b917390b06b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331091139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2331091139
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1442392404
Short name T27
Test name
Test status
Simulation time 408866627 ps
CPU time 2.34 seconds
Started Feb 18 12:51:24 PM PST 24
Finished Feb 18 12:51:29 PM PST 24
Peak memory 200496 kb
Host smart-3c9151ba-681f-4ef1-ac63-861336036ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442392404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1442392404
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.76200842
Short name T170
Test name
Test status
Simulation time 161497335 ps
CPU time 1.06 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:31 PM PST 24
Peak memory 200432 kb
Host smart-b3f462bc-1a5a-4761-853b-80dcc2f80083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76200842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.76200842
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.556765882
Short name T525
Test name
Test status
Simulation time 88445064 ps
CPU time 0.88 seconds
Started Feb 18 12:51:33 PM PST 24
Finished Feb 18 12:51:35 PM PST 24
Peak memory 200404 kb
Host smart-dd748644-71ce-49e4-a41f-6b1efedb22e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556765882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.556765882
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1056329765
Short name T413
Test name
Test status
Simulation time 1226170740 ps
CPU time 5.93 seconds
Started Feb 18 12:51:30 PM PST 24
Finished Feb 18 12:51:38 PM PST 24
Peak memory 217336 kb
Host smart-d858d244-6621-47bc-93fa-3cef29d80b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056329765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1056329765
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.599174947
Short name T155
Test name
Test status
Simulation time 243191480 ps
CPU time 1.12 seconds
Started Feb 18 12:51:35 PM PST 24
Finished Feb 18 12:51:37 PM PST 24
Peak memory 217760 kb
Host smart-022ef030-cb1c-414c-a455-0f8e012dd1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599174947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.599174947
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.312785958
Short name T276
Test name
Test status
Simulation time 214159972 ps
CPU time 0.89 seconds
Started Feb 18 12:51:29 PM PST 24
Finished Feb 18 12:51:32 PM PST 24
Peak memory 200312 kb
Host smart-52f4e028-c3d5-4f71-b21b-d93dc5f767c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312785958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.312785958
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1087047977
Short name T226
Test name
Test status
Simulation time 1728094347 ps
CPU time 6.7 seconds
Started Feb 18 12:51:25 PM PST 24
Finished Feb 18 12:51:34 PM PST 24
Peak memory 200740 kb
Host smart-1e1e012a-f04e-4991-9c1b-1f430e306087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087047977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1087047977
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1938857871
Short name T295
Test name
Test status
Simulation time 147357146 ps
CPU time 1.08 seconds
Started Feb 18 12:51:32 PM PST 24
Finished Feb 18 12:51:35 PM PST 24
Peak memory 200532 kb
Host smart-03ed9427-3631-48d0-9d51-5efc9709adc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938857871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1938857871
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.4046694655
Short name T221
Test name
Test status
Simulation time 120277807 ps
CPU time 1.14 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:31 PM PST 24
Peak memory 200724 kb
Host smart-c39a256e-0c93-46e2-9d52-a63259ddd2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046694655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.4046694655
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2774080838
Short name T263
Test name
Test status
Simulation time 4488646381 ps
CPU time 19.36 seconds
Started Feb 18 12:51:36 PM PST 24
Finished Feb 18 12:51:57 PM PST 24
Peak memory 200860 kb
Host smart-44fa6d5e-917d-4594-ac9c-5abcea65cd86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774080838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2774080838
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1557906527
Short name T337
Test name
Test status
Simulation time 326901820 ps
CPU time 2.25 seconds
Started Feb 18 12:51:27 PM PST 24
Finished Feb 18 12:51:31 PM PST 24
Peak memory 200464 kb
Host smart-dccde78f-e877-45c3-9c1f-b4a56d9620e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557906527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1557906527
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2711911057
Short name T205
Test name
Test status
Simulation time 246610166 ps
CPU time 1.46 seconds
Started Feb 18 12:51:24 PM PST 24
Finished Feb 18 12:51:28 PM PST 24
Peak memory 200728 kb
Host smart-d2d7c257-b9be-4793-9238-1eb840a346d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711911057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2711911057
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1248007877
Short name T229
Test name
Test status
Simulation time 74581160 ps
CPU time 0.77 seconds
Started Feb 18 12:51:32 PM PST 24
Finished Feb 18 12:51:33 PM PST 24
Peak memory 200320 kb
Host smart-f407d690-18db-4b93-a382-34140b03c416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248007877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1248007877
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1403350824
Short name T257
Test name
Test status
Simulation time 1214290556 ps
CPU time 5.34 seconds
Started Feb 18 12:51:37 PM PST 24
Finished Feb 18 12:51:44 PM PST 24
Peak memory 221940 kb
Host smart-4c76f1eb-9cdf-43b2-8305-c2478744da6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403350824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1403350824
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1681228521
Short name T392
Test name
Test status
Simulation time 244124456 ps
CPU time 1.13 seconds
Started Feb 18 12:51:30 PM PST 24
Finished Feb 18 12:51:33 PM PST 24
Peak memory 217868 kb
Host smart-f290daa3-4bf8-4a0e-ac26-765a103d08bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681228521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1681228521
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3170779862
Short name T193
Test name
Test status
Simulation time 107124517 ps
CPU time 0.75 seconds
Started Feb 18 12:51:37 PM PST 24
Finished Feb 18 12:51:38 PM PST 24
Peak memory 200308 kb
Host smart-005ce8f0-752f-46d9-9792-455fd2a38fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170779862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3170779862
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3989213245
Short name T386
Test name
Test status
Simulation time 1608419695 ps
CPU time 6.7 seconds
Started Feb 18 12:51:34 PM PST 24
Finished Feb 18 12:51:41 PM PST 24
Peak memory 200640 kb
Host smart-e7d9aab0-94ca-4cf9-8ef7-92026a32b0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989213245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3989213245
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1796126219
Short name T354
Test name
Test status
Simulation time 100038074 ps
CPU time 1 seconds
Started Feb 18 12:51:35 PM PST 24
Finished Feb 18 12:51:37 PM PST 24
Peak memory 200452 kb
Host smart-c2df1330-0a6b-47f4-89cf-a55af5e1f466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796126219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1796126219
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1043990447
Short name T181
Test name
Test status
Simulation time 111359810 ps
CPU time 1.2 seconds
Started Feb 18 12:51:33 PM PST 24
Finished Feb 18 12:51:35 PM PST 24
Peak memory 200684 kb
Host smart-59a58f05-dfab-4eea-9f24-8e68c40e9b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043990447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1043990447
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1702969501
Short name T310
Test name
Test status
Simulation time 129816128 ps
CPU time 1.68 seconds
Started Feb 18 12:51:31 PM PST 24
Finished Feb 18 12:51:34 PM PST 24
Peak memory 200432 kb
Host smart-6af33b20-138e-4ae5-abc8-094a9e5ab532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702969501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1702969501
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1616112223
Short name T199
Test name
Test status
Simulation time 231246784 ps
CPU time 1.37 seconds
Started Feb 18 12:51:38 PM PST 24
Finished Feb 18 12:51:40 PM PST 24
Peak memory 200536 kb
Host smart-ddd06546-b9d6-407b-8684-4d673850241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616112223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1616112223
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2609822797
Short name T158
Test name
Test status
Simulation time 68899773 ps
CPU time 0.77 seconds
Started Feb 18 12:51:37 PM PST 24
Finished Feb 18 12:51:39 PM PST 24
Peak memory 200408 kb
Host smart-8e78bfb4-afe7-454c-adda-4ba00f62d33d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609822797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2609822797
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.765501241
Short name T54
Test name
Test status
Simulation time 245238555 ps
CPU time 1.09 seconds
Started Feb 18 12:51:38 PM PST 24
Finished Feb 18 12:51:41 PM PST 24
Peak memory 216896 kb
Host smart-da7f3ca6-ed9d-4dd1-b1b0-0e672cf4ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765501241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.765501241
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2061363457
Short name T285
Test name
Test status
Simulation time 175942354 ps
CPU time 0.89 seconds
Started Feb 18 12:51:29 PM PST 24
Finished Feb 18 12:51:32 PM PST 24
Peak memory 200320 kb
Host smart-48242e21-d76c-4512-ab20-ede02d5adeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061363457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2061363457
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3917263744
Short name T530
Test name
Test status
Simulation time 1411158110 ps
CPU time 6.05 seconds
Started Feb 18 12:51:34 PM PST 24
Finished Feb 18 12:51:42 PM PST 24
Peak memory 200780 kb
Host smart-736f64a7-babf-4821-b7e9-2d9c8507a84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917263744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3917263744
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1595194575
Short name T208
Test name
Test status
Simulation time 144873221 ps
CPU time 1.18 seconds
Started Feb 18 12:51:38 PM PST 24
Finished Feb 18 12:51:41 PM PST 24
Peak memory 200460 kb
Host smart-f30d8832-908f-403f-b99f-eb380ba2c0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595194575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1595194575
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1876641940
Short name T351
Test name
Test status
Simulation time 262906751 ps
CPU time 1.42 seconds
Started Feb 18 12:51:30 PM PST 24
Finished Feb 18 12:51:33 PM PST 24
Peak memory 200632 kb
Host smart-05a302ed-50e9-42c0-9ba8-020fe2e9c218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876641940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1876641940
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3328594730
Short name T358
Test name
Test status
Simulation time 3023676430 ps
CPU time 13 seconds
Started Feb 18 12:51:33 PM PST 24
Finished Feb 18 12:51:47 PM PST 24
Peak memory 200896 kb
Host smart-46fbbcfc-db22-4cc9-99e6-9148dc6f5330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328594730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3328594730
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.613115086
Short name T342
Test name
Test status
Simulation time 142486207 ps
CPU time 1.74 seconds
Started Feb 18 12:51:30 PM PST 24
Finished Feb 18 12:51:33 PM PST 24
Peak memory 200544 kb
Host smart-2ec609c5-8785-4c00-bc6a-359ccb3ab99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613115086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.613115086
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2167332349
Short name T520
Test name
Test status
Simulation time 76033791 ps
CPU time 0.85 seconds
Started Feb 18 12:51:38 PM PST 24
Finished Feb 18 12:51:40 PM PST 24
Peak memory 200540 kb
Host smart-ef9840f1-0022-4024-b329-8173f88875c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167332349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2167332349
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1293366264
Short name T169
Test name
Test status
Simulation time 82608635 ps
CPU time 0.81 seconds
Started Feb 18 12:51:31 PM PST 24
Finished Feb 18 12:51:33 PM PST 24
Peak memory 200396 kb
Host smart-2f4b2ca2-c185-4b0d-98c7-84564e884f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293366264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1293366264
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1198159727
Short name T446
Test name
Test status
Simulation time 1230617835 ps
CPU time 6.14 seconds
Started Feb 18 12:51:33 PM PST 24
Finished Feb 18 12:51:41 PM PST 24
Peak memory 217820 kb
Host smart-40d3de51-16ba-430f-80f8-8445bdb38a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198159727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1198159727
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.4039463285
Short name T372
Test name
Test status
Simulation time 244041066 ps
CPU time 1.08 seconds
Started Feb 18 12:51:33 PM PST 24
Finished Feb 18 12:51:36 PM PST 24
Peak memory 217856 kb
Host smart-ec09aecf-6319-4ee7-898c-05a564c91efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039463285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.4039463285
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3630530975
Short name T411
Test name
Test status
Simulation time 746085348 ps
CPU time 4.41 seconds
Started Feb 18 12:51:32 PM PST 24
Finished Feb 18 12:51:38 PM PST 24
Peak memory 200740 kb
Host smart-65df8b83-048f-441e-9a0f-2e56b4affb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630530975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3630530975
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1472002088
Short name T511
Test name
Test status
Simulation time 105240281 ps
CPU time 0.98 seconds
Started Feb 18 12:51:32 PM PST 24
Finished Feb 18 12:51:34 PM PST 24
Peak memory 200520 kb
Host smart-db8d3c59-b201-4137-8737-6016c05587b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472002088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1472002088
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.4204111125
Short name T185
Test name
Test status
Simulation time 125199451 ps
CPU time 1.13 seconds
Started Feb 18 12:51:30 PM PST 24
Finished Feb 18 12:51:33 PM PST 24
Peak memory 200684 kb
Host smart-00f4ab57-64c7-4bbe-ba0b-0ecc69621de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204111125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4204111125
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.4174511468
Short name T93
Test name
Test status
Simulation time 1295957881 ps
CPU time 6.23 seconds
Started Feb 18 12:51:31 PM PST 24
Finished Feb 18 12:51:39 PM PST 24
Peak memory 200740 kb
Host smart-3762fa7f-217c-4b2b-8ad2-d86b66e298c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174511468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.4174511468
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3592022246
Short name T373
Test name
Test status
Simulation time 336192934 ps
CPU time 2.12 seconds
Started Feb 18 12:51:34 PM PST 24
Finished Feb 18 12:51:38 PM PST 24
Peak memory 200460 kb
Host smart-a1fc7d1d-0c31-4578-aa9d-fd77464bd3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592022246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3592022246
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3435377397
Short name T429
Test name
Test status
Simulation time 171249821 ps
CPU time 1.11 seconds
Started Feb 18 12:51:37 PM PST 24
Finished Feb 18 12:51:39 PM PST 24
Peak memory 200504 kb
Host smart-52370f12-b624-4a4c-a2bf-19f8fe81b00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435377397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3435377397
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2833440205
Short name T535
Test name
Test status
Simulation time 65580537 ps
CPU time 0.76 seconds
Started Feb 18 12:51:41 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 200396 kb
Host smart-9ce8ad81-ade8-4f5e-ae62-221a419310e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833440205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2833440205
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.711867473
Short name T67
Test name
Test status
Simulation time 1219254508 ps
CPU time 5.83 seconds
Started Feb 18 12:51:39 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 219012 kb
Host smart-d1f8fe12-72de-4733-a8e7-9e37a6258947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711867473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.711867473
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3189914426
Short name T427
Test name
Test status
Simulation time 243903917 ps
CPU time 1.19 seconds
Started Feb 18 12:51:41 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 217788 kb
Host smart-d0996c64-2315-4609-98dd-36f7da37ae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189914426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3189914426
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2720409851
Short name T306
Test name
Test status
Simulation time 183990979 ps
CPU time 0.9 seconds
Started Feb 18 12:51:42 PM PST 24
Finished Feb 18 12:51:47 PM PST 24
Peak memory 200300 kb
Host smart-f156317b-652d-4b18-8385-a8f65f55b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720409851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2720409851
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.4164170898
Short name T328
Test name
Test status
Simulation time 1356781938 ps
CPU time 5.52 seconds
Started Feb 18 12:51:40 PM PST 24
Finished Feb 18 12:51:50 PM PST 24
Peak memory 200756 kb
Host smart-9f6853ba-2364-4869-80d1-b230ac02b7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164170898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.4164170898
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1015395536
Short name T166
Test name
Test status
Simulation time 111700937 ps
CPU time 1.02 seconds
Started Feb 18 12:51:42 PM PST 24
Finished Feb 18 12:51:47 PM PST 24
Peak memory 200444 kb
Host smart-15f06c70-4c27-44b0-8977-ce36800ef023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015395536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1015395536
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1160345737
Short name T220
Test name
Test status
Simulation time 227525614 ps
CPU time 1.49 seconds
Started Feb 18 12:51:41 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 200436 kb
Host smart-27c33743-bfd9-4daa-a7e0-89aa3ef736db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160345737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1160345737
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3982160591
Short name T96
Test name
Test status
Simulation time 1585332780 ps
CPU time 6.19 seconds
Started Feb 18 12:51:45 PM PST 24
Finished Feb 18 12:51:56 PM PST 24
Peak memory 200784 kb
Host smart-2f3bb740-1918-4e98-a1c8-e29515cb7587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982160591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3982160591
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.422965181
Short name T156
Test name
Test status
Simulation time 362777986 ps
CPU time 2.52 seconds
Started Feb 18 12:51:43 PM PST 24
Finished Feb 18 12:51:49 PM PST 24
Peak memory 200380 kb
Host smart-3763fcee-f298-4ca0-a1ce-8da2e92360f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422965181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.422965181
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3567094895
Short name T164
Test name
Test status
Simulation time 143457359 ps
CPU time 1.25 seconds
Started Feb 18 12:51:42 PM PST 24
Finished Feb 18 12:51:47 PM PST 24
Peak memory 200508 kb
Host smart-eaaf2e2c-a772-4b4e-b718-bbf2f354c50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567094895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3567094895
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.550884871
Short name T72
Test name
Test status
Simulation time 70568329 ps
CPU time 0.73 seconds
Started Feb 18 12:51:43 PM PST 24
Finished Feb 18 12:51:49 PM PST 24
Peak memory 200408 kb
Host smart-693d012b-4a7d-4249-ac05-56e0ee129063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550884871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.550884871
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.410017587
Short name T339
Test name
Test status
Simulation time 2160292083 ps
CPU time 7.96 seconds
Started Feb 18 12:51:43 PM PST 24
Finished Feb 18 12:51:55 PM PST 24
Peak memory 218104 kb
Host smart-7798c680-695f-4ca5-ae4e-51c7213dc65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410017587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.410017587
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3292579928
Short name T272
Test name
Test status
Simulation time 244823209 ps
CPU time 1.08 seconds
Started Feb 18 12:51:39 PM PST 24
Finished Feb 18 12:51:42 PM PST 24
Peak memory 217732 kb
Host smart-7f720866-9291-4c77-b2ed-33bdb8301ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292579928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3292579928
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2303457749
Short name T273
Test name
Test status
Simulation time 181283070 ps
CPU time 0.83 seconds
Started Feb 18 12:51:40 PM PST 24
Finished Feb 18 12:51:44 PM PST 24
Peak memory 200284 kb
Host smart-fb7e208b-5b4e-48c9-b47a-f9004668fe8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303457749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2303457749
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3378841628
Short name T419
Test name
Test status
Simulation time 1285453296 ps
CPU time 4.9 seconds
Started Feb 18 12:51:38 PM PST 24
Finished Feb 18 12:51:44 PM PST 24
Peak memory 200748 kb
Host smart-ea53241b-91e3-4bf4-8f78-c64ca62ef15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378841628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3378841628
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2048356812
Short name T401
Test name
Test status
Simulation time 195106410 ps
CPU time 1.35 seconds
Started Feb 18 12:51:42 PM PST 24
Finished Feb 18 12:51:47 PM PST 24
Peak memory 200672 kb
Host smart-5c3c6a80-2552-4c10-b61f-e30018ae8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048356812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2048356812
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1259574432
Short name T365
Test name
Test status
Simulation time 796819116 ps
CPU time 3.54 seconds
Started Feb 18 12:51:43 PM PST 24
Finished Feb 18 12:51:50 PM PST 24
Peak memory 200676 kb
Host smart-3d3b19b2-8818-4cad-aab5-c814b3e070a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259574432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1259574432
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1068620240
Short name T322
Test name
Test status
Simulation time 402484500 ps
CPU time 2.19 seconds
Started Feb 18 12:51:40 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 200496 kb
Host smart-ded12a3e-f8f2-4f3e-bd9e-ad6b12c37e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068620240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1068620240
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.353544505
Short name T200
Test name
Test status
Simulation time 267374575 ps
CPU time 1.47 seconds
Started Feb 18 12:51:41 PM PST 24
Finished Feb 18 12:51:47 PM PST 24
Peak memory 200492 kb
Host smart-a97fb1f9-f3c6-45e7-b393-a0d4fd240486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353544505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.353544505
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1601728688
Short name T188
Test name
Test status
Simulation time 64941521 ps
CPU time 0.73 seconds
Started Feb 18 12:51:40 PM PST 24
Finished Feb 18 12:51:45 PM PST 24
Peak memory 200388 kb
Host smart-ad5d35ca-a6f4-48ae-a6ea-a99f5f839b9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601728688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1601728688
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3809398789
Short name T512
Test name
Test status
Simulation time 1899165965 ps
CPU time 7 seconds
Started Feb 18 12:51:38 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 218436 kb
Host smart-8bff900b-d6fa-4d84-8f38-ab5ca13931fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809398789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3809398789
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1710154154
Short name T303
Test name
Test status
Simulation time 244784821 ps
CPU time 1.06 seconds
Started Feb 18 12:51:40 PM PST 24
Finished Feb 18 12:51:44 PM PST 24
Peak memory 217848 kb
Host smart-ef69f149-1086-49f0-ae15-e1416f171ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710154154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1710154154
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3763332674
Short name T203
Test name
Test status
Simulation time 165283443 ps
CPU time 0.87 seconds
Started Feb 18 12:51:42 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 200308 kb
Host smart-935e875b-9e02-45b4-adc2-9fe103d0a3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763332674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3763332674
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3858885484
Short name T115
Test name
Test status
Simulation time 866488064 ps
CPU time 4.41 seconds
Started Feb 18 12:51:43 PM PST 24
Finished Feb 18 12:51:51 PM PST 24
Peak memory 200800 kb
Host smart-19a06c6f-99c8-45b7-8f94-2e0cd2ee0c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858885484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3858885484
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.858767336
Short name T177
Test name
Test status
Simulation time 148750000 ps
CPU time 1.17 seconds
Started Feb 18 12:51:44 PM PST 24
Finished Feb 18 12:51:50 PM PST 24
Peak memory 200420 kb
Host smart-9be60e76-a95e-401d-b6aa-e1a605f7b509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858767336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.858767336
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1913862250
Short name T258
Test name
Test status
Simulation time 121484169 ps
CPU time 1.24 seconds
Started Feb 18 12:51:41 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 200672 kb
Host smart-ae1fe07b-5241-4186-83fa-a86426c7647e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913862250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1913862250
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1159317796
Short name T207
Test name
Test status
Simulation time 330250300 ps
CPU time 2.43 seconds
Started Feb 18 12:51:39 PM PST 24
Finished Feb 18 12:51:45 PM PST 24
Peak memory 200488 kb
Host smart-02ec6672-910c-47c5-ba6e-9fa2c7e43f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159317796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1159317796
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.379517899
Short name T61
Test name
Test status
Simulation time 194365716 ps
CPU time 1.17 seconds
Started Feb 18 12:51:41 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 200484 kb
Host smart-646ba601-5950-4a24-b089-6b65313fd5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379517899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.379517899
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.27278070
Short name T265
Test name
Test status
Simulation time 83662715 ps
CPU time 0.87 seconds
Started Feb 18 12:51:54 PM PST 24
Finished Feb 18 12:52:02 PM PST 24
Peak memory 200420 kb
Host smart-32439ff2-dba8-4326-a929-74ce9669086b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27278070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.27278070
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.63996617
Short name T49
Test name
Test status
Simulation time 2356390656 ps
CPU time 10.1 seconds
Started Feb 18 12:51:44 PM PST 24
Finished Feb 18 12:51:59 PM PST 24
Peak memory 218656 kb
Host smart-21b8a537-734a-455f-bcf5-0bdb5add3b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63996617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.63996617
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3627068854
Short name T374
Test name
Test status
Simulation time 244152505 ps
CPU time 1.15 seconds
Started Feb 18 12:51:48 PM PST 24
Finished Feb 18 12:51:53 PM PST 24
Peak memory 217812 kb
Host smart-fa0bc95f-5246-40da-b0f8-8be27bf710f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627068854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3627068854
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.948288437
Short name T353
Test name
Test status
Simulation time 155539555 ps
CPU time 0.86 seconds
Started Feb 18 12:51:40 PM PST 24
Finished Feb 18 12:51:45 PM PST 24
Peak memory 199960 kb
Host smart-1d4c4367-b623-4210-a62d-bfb86acc3379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948288437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.948288437
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.326592827
Short name T109
Test name
Test status
Simulation time 1248209718 ps
CPU time 5.09 seconds
Started Feb 18 12:51:39 PM PST 24
Finished Feb 18 12:51:47 PM PST 24
Peak memory 200756 kb
Host smart-1506c0ca-2bac-4dd5-a2ed-df1d522a89bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326592827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.326592827
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3271682916
Short name T160
Test name
Test status
Simulation time 152239495 ps
CPU time 1.09 seconds
Started Feb 18 12:51:41 PM PST 24
Finished Feb 18 12:51:46 PM PST 24
Peak memory 200496 kb
Host smart-606e652c-43f1-4abd-bb12-1616d26bde4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271682916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3271682916
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.357154062
Short name T422
Test name
Test status
Simulation time 249499903 ps
CPU time 1.43 seconds
Started Feb 18 12:51:39 PM PST 24
Finished Feb 18 12:51:43 PM PST 24
Peak memory 200680 kb
Host smart-fb6e27a0-ab0b-4388-86cc-c3557b5433aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357154062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.357154062
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3495172211
Short name T56
Test name
Test status
Simulation time 7512790960 ps
CPU time 29.76 seconds
Started Feb 18 12:51:52 PM PST 24
Finished Feb 18 12:52:29 PM PST 24
Peak memory 200860 kb
Host smart-26a07638-0b86-41fc-a230-fa1dc210eda3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495172211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3495172211
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1846064243
Short name T194
Test name
Test status
Simulation time 497241776 ps
CPU time 2.58 seconds
Started Feb 18 12:51:41 PM PST 24
Finished Feb 18 12:51:48 PM PST 24
Peak memory 200468 kb
Host smart-117a0400-eaba-4e34-b4f7-b687989dd7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846064243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1846064243
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1549465774
Short name T388
Test name
Test status
Simulation time 156939138 ps
CPU time 1.14 seconds
Started Feb 18 12:51:40 PM PST 24
Finished Feb 18 12:51:45 PM PST 24
Peak memory 200448 kb
Host smart-917262d4-9530-4ae0-b661-9615b1e2beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549465774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1549465774
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2237143035
Short name T217
Test name
Test status
Simulation time 69150677 ps
CPU time 0.73 seconds
Started Feb 18 12:51:51 PM PST 24
Finished Feb 18 12:51:58 PM PST 24
Peak memory 200416 kb
Host smart-53729cfa-e2e0-452c-99d7-bf282866341c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237143035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2237143035
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1424068299
Short name T52
Test name
Test status
Simulation time 1889621991 ps
CPU time 7.57 seconds
Started Feb 18 12:51:53 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 222568 kb
Host smart-264ac80b-7d68-41b9-8052-637d503a79bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424068299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1424068299
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3422107294
Short name T368
Test name
Test status
Simulation time 243706531 ps
CPU time 1.23 seconds
Started Feb 18 12:51:54 PM PST 24
Finished Feb 18 12:52:02 PM PST 24
Peak memory 217784 kb
Host smart-b39c9d9c-bb8f-433b-8120-5004c045df37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422107294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3422107294
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2825130366
Short name T237
Test name
Test status
Simulation time 121733532 ps
CPU time 0.82 seconds
Started Feb 18 12:51:50 PM PST 24
Finished Feb 18 12:51:57 PM PST 24
Peak memory 200328 kb
Host smart-723d675b-ec4c-431c-881d-a470488f861f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825130366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2825130366
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.4270415523
Short name T522
Test name
Test status
Simulation time 831747516 ps
CPU time 4.14 seconds
Started Feb 18 12:51:55 PM PST 24
Finished Feb 18 12:52:06 PM PST 24
Peak memory 200756 kb
Host smart-1693f440-f228-44b6-abbe-b2ad964be344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270415523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.4270415523
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.605277052
Short name T206
Test name
Test status
Simulation time 102493632 ps
CPU time 1.03 seconds
Started Feb 18 12:51:49 PM PST 24
Finished Feb 18 12:51:55 PM PST 24
Peak memory 200492 kb
Host smart-a9ed2554-bb8e-4398-af2b-be12659e443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605277052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.605277052
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3211519794
Short name T430
Test name
Test status
Simulation time 194998641 ps
CPU time 1.47 seconds
Started Feb 18 12:51:54 PM PST 24
Finished Feb 18 12:52:03 PM PST 24
Peak memory 200728 kb
Host smart-65356f14-3977-4185-87e3-a29be2140f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211519794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3211519794
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2677469113
Short name T112
Test name
Test status
Simulation time 6248256442 ps
CPU time 21.39 seconds
Started Feb 18 12:51:47 PM PST 24
Finished Feb 18 12:52:12 PM PST 24
Peak memory 200860 kb
Host smart-d844bb05-4adc-4474-99a5-c679450a7236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677469113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2677469113
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1322376310
Short name T341
Test name
Test status
Simulation time 119315890 ps
CPU time 1.52 seconds
Started Feb 18 12:51:49 PM PST 24
Finished Feb 18 12:51:55 PM PST 24
Peak memory 200400 kb
Host smart-18b50f3c-1765-4a9a-8481-f9584296f6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322376310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1322376310
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1325060383
Short name T448
Test name
Test status
Simulation time 97412049 ps
CPU time 0.95 seconds
Started Feb 18 12:51:54 PM PST 24
Finished Feb 18 12:52:02 PM PST 24
Peak memory 200512 kb
Host smart-99318db5-2d06-4e4c-8ef9-ff7ae0263e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325060383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1325060383
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1217712292
Short name T297
Test name
Test status
Simulation time 62996846 ps
CPU time 0.72 seconds
Started Feb 18 12:51:07 PM PST 24
Finished Feb 18 12:51:10 PM PST 24
Peak memory 200300 kb
Host smart-fc211566-7e89-4da7-b4c8-1aa77262d48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217712292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1217712292
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3713571337
Short name T60
Test name
Test status
Simulation time 2190681434 ps
CPU time 8.24 seconds
Started Feb 18 12:51:09 PM PST 24
Finished Feb 18 12:51:19 PM PST 24
Peak memory 222556 kb
Host smart-b5a800c6-522a-438f-a7a0-59baa7853749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713571337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3713571337
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2791438058
Short name T211
Test name
Test status
Simulation time 244584369 ps
CPU time 1.05 seconds
Started Feb 18 12:51:18 PM PST 24
Finished Feb 18 12:51:22 PM PST 24
Peak memory 217752 kb
Host smart-f41f1db2-c1dc-4b4f-adfb-52ddb53384aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791438058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2791438058
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2844933401
Short name T15
Test name
Test status
Simulation time 123370249 ps
CPU time 0.76 seconds
Started Feb 18 12:51:06 PM PST 24
Finished Feb 18 12:51:08 PM PST 24
Peak memory 200288 kb
Host smart-1c3714fe-bc29-4ab1-93fb-a5caf197d74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844933401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2844933401
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1064447697
Short name T281
Test name
Test status
Simulation time 1388756316 ps
CPU time 5.99 seconds
Started Feb 18 12:51:09 PM PST 24
Finished Feb 18 12:51:17 PM PST 24
Peak memory 200748 kb
Host smart-d3700ebb-277e-492f-840d-53a9f2dee1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064447697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1064447697
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1701621127
Short name T88
Test name
Test status
Simulation time 8329008972 ps
CPU time 13.42 seconds
Started Feb 18 12:51:18 PM PST 24
Finished Feb 18 12:51:35 PM PST 24
Peak memory 218404 kb
Host smart-9e0f6343-70db-49b0-b3eb-2d4f37f792c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701621127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1701621127
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1162971509
Short name T462
Test name
Test status
Simulation time 166873080 ps
CPU time 1.12 seconds
Started Feb 18 12:51:08 PM PST 24
Finished Feb 18 12:51:11 PM PST 24
Peak memory 200556 kb
Host smart-36f5513b-da3e-4a4c-9f10-0e0bbbf811e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162971509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1162971509
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1907108708
Short name T168
Test name
Test status
Simulation time 199202696 ps
CPU time 1.33 seconds
Started Feb 18 12:51:09 PM PST 24
Finished Feb 18 12:51:12 PM PST 24
Peak memory 200668 kb
Host smart-80417e09-ec27-4174-8d45-e3539e198428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907108708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1907108708
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3699905637
Short name T143
Test name
Test status
Simulation time 474694810 ps
CPU time 2.87 seconds
Started Feb 18 12:51:07 PM PST 24
Finished Feb 18 12:51:12 PM PST 24
Peak memory 200488 kb
Host smart-50e49bee-9aba-4eb2-85e0-c42cb358151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699905637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3699905637
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3044936902
Short name T331
Test name
Test status
Simulation time 215873512 ps
CPU time 1.34 seconds
Started Feb 18 12:51:11 PM PST 24
Finished Feb 18 12:51:14 PM PST 24
Peak memory 200476 kb
Host smart-4f5aa84e-b7c0-45e5-b602-c8c1f5b1b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044936902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3044936902
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1720168665
Short name T456
Test name
Test status
Simulation time 70564779 ps
CPU time 0.78 seconds
Started Feb 18 12:51:47 PM PST 24
Finished Feb 18 12:51:52 PM PST 24
Peak memory 200436 kb
Host smart-64d018bf-2efb-4ccd-af14-fca25fd2e70d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720168665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1720168665
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.4092645666
Short name T51
Test name
Test status
Simulation time 1892787445 ps
CPU time 7.81 seconds
Started Feb 18 12:51:47 PM PST 24
Finished Feb 18 12:51:59 PM PST 24
Peak memory 218524 kb
Host smart-ac507993-3912-4d30-8df6-1e547bd73193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092645666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.4092645666
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3123402105
Short name T174
Test name
Test status
Simulation time 245329841 ps
CPU time 1.08 seconds
Started Feb 18 12:51:54 PM PST 24
Finished Feb 18 12:52:03 PM PST 24
Peak memory 217812 kb
Host smart-181a7994-c78d-4023-a50f-2cedcb15d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123402105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3123402105
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2005692336
Short name T467
Test name
Test status
Simulation time 202499749 ps
CPU time 0.88 seconds
Started Feb 18 12:51:53 PM PST 24
Finished Feb 18 12:52:01 PM PST 24
Peak memory 200308 kb
Host smart-0b2e70d1-b126-4942-a4ea-2d271131de8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005692336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2005692336
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2616091376
Short name T139
Test name
Test status
Simulation time 1394467963 ps
CPU time 5.62 seconds
Started Feb 18 12:51:50 PM PST 24
Finished Feb 18 12:52:02 PM PST 24
Peak memory 200704 kb
Host smart-d526f59f-5cca-4b5c-8a39-c805f9427fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616091376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2616091376
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2001978970
Short name T163
Test name
Test status
Simulation time 176441012 ps
CPU time 1.15 seconds
Started Feb 18 12:51:51 PM PST 24
Finished Feb 18 12:51:59 PM PST 24
Peak memory 200552 kb
Host smart-fc134084-d661-4c57-8737-fcdb3ebef9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001978970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2001978970
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2784814017
Short name T298
Test name
Test status
Simulation time 128702591 ps
CPU time 1.25 seconds
Started Feb 18 12:51:51 PM PST 24
Finished Feb 18 12:51:59 PM PST 24
Peak memory 200736 kb
Host smart-555c5bd8-19f3-4246-bf6f-f23d2cbaf865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784814017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2784814017
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2863372518
Short name T117
Test name
Test status
Simulation time 6953579074 ps
CPU time 28.7 seconds
Started Feb 18 12:51:56 PM PST 24
Finished Feb 18 12:52:31 PM PST 24
Peak memory 200868 kb
Host smart-8d5afae6-abbf-4e94-ad30-87b4e1f1290d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863372518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2863372518
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1197381197
Short name T308
Test name
Test status
Simulation time 467527439 ps
CPU time 2.67 seconds
Started Feb 18 12:51:54 PM PST 24
Finished Feb 18 12:52:04 PM PST 24
Peak memory 200476 kb
Host smart-4ff9d4ac-74cc-4291-b58b-e7de2c9c7f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197381197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1197381197
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2218269509
Short name T346
Test name
Test status
Simulation time 134030992 ps
CPU time 1.11 seconds
Started Feb 18 12:51:49 PM PST 24
Finished Feb 18 12:51:55 PM PST 24
Peak memory 200444 kb
Host smart-886f280b-5247-4f8a-86fa-945c964933b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218269509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2218269509
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.715443463
Short name T348
Test name
Test status
Simulation time 66280928 ps
CPU time 0.77 seconds
Started Feb 18 12:51:51 PM PST 24
Finished Feb 18 12:51:58 PM PST 24
Peak memory 200468 kb
Host smart-f2ceb1d3-f8a2-4652-99c9-d0c43eff9ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715443463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.715443463
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3147820034
Short name T501
Test name
Test status
Simulation time 2345051277 ps
CPU time 8.23 seconds
Started Feb 18 12:51:50 PM PST 24
Finished Feb 18 12:52:05 PM PST 24
Peak memory 218392 kb
Host smart-ec307473-306c-4922-a095-e39646c48ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147820034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3147820034
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3947942560
Short name T470
Test name
Test status
Simulation time 244330683 ps
CPU time 1.06 seconds
Started Feb 18 12:51:51 PM PST 24
Finished Feb 18 12:51:58 PM PST 24
Peak memory 217720 kb
Host smart-948c50d5-c38c-4997-a4d1-5601979bf1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947942560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3947942560
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2598601927
Short name T360
Test name
Test status
Simulation time 96286216 ps
CPU time 0.71 seconds
Started Feb 18 12:51:53 PM PST 24
Finished Feb 18 12:52:00 PM PST 24
Peak memory 200304 kb
Host smart-4ec16a3f-781a-4cd1-96a6-ca31e0126eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598601927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2598601927
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3710852255
Short name T107
Test name
Test status
Simulation time 891876714 ps
CPU time 4.55 seconds
Started Feb 18 12:51:54 PM PST 24
Finished Feb 18 12:52:06 PM PST 24
Peak memory 200768 kb
Host smart-271aa617-d7c8-4b05-83f0-7dbc4f351059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710852255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3710852255
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.664094454
Short name T223
Test name
Test status
Simulation time 174572557 ps
CPU time 1.24 seconds
Started Feb 18 12:51:50 PM PST 24
Finished Feb 18 12:51:58 PM PST 24
Peak memory 200508 kb
Host smart-623efde8-ddc3-411a-9301-83056fb5aabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664094454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.664094454
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.220650069
Short name T529
Test name
Test status
Simulation time 126406844 ps
CPU time 1.25 seconds
Started Feb 18 12:51:56 PM PST 24
Finished Feb 18 12:52:03 PM PST 24
Peak memory 200676 kb
Host smart-65732a6d-797e-4cb5-a203-a505a4d0b982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220650069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.220650069
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2366770697
Short name T291
Test name
Test status
Simulation time 1082586423 ps
CPU time 5.56 seconds
Started Feb 18 12:51:56 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200752 kb
Host smart-066b494c-49b9-48ec-8082-6c29ad3e381e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366770697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2366770697
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2050279116
Short name T492
Test name
Test status
Simulation time 244619872 ps
CPU time 1.74 seconds
Started Feb 18 12:51:49 PM PST 24
Finished Feb 18 12:51:55 PM PST 24
Peak memory 200380 kb
Host smart-3eb89e8f-2337-4940-a003-1c5092f8d1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050279116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2050279116
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.552911248
Short name T62
Test name
Test status
Simulation time 175536590 ps
CPU time 1.15 seconds
Started Feb 18 12:51:53 PM PST 24
Finished Feb 18 12:52:01 PM PST 24
Peak memory 200500 kb
Host smart-a811603f-98c7-4c23-a879-f190d9f37106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552911248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.552911248
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1184367435
Short name T335
Test name
Test status
Simulation time 58533941 ps
CPU time 0.73 seconds
Started Feb 18 12:51:50 PM PST 24
Finished Feb 18 12:51:57 PM PST 24
Peak memory 200336 kb
Host smart-139ca923-d522-4fcd-a277-95cd9aed6bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184367435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1184367435
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1014309775
Short name T486
Test name
Test status
Simulation time 1886296002 ps
CPU time 7.67 seconds
Started Feb 18 12:51:53 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 222520 kb
Host smart-a591e012-86b1-416a-8964-7b6abaab48af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014309775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1014309775
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1293644519
Short name T179
Test name
Test status
Simulation time 244736646 ps
CPU time 1.07 seconds
Started Feb 18 12:51:56 PM PST 24
Finished Feb 18 12:52:03 PM PST 24
Peak memory 217864 kb
Host smart-f95583d4-b2be-48c9-ba17-10e8c008dfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293644519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1293644519
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2109112182
Short name T406
Test name
Test status
Simulation time 180610113 ps
CPU time 0.84 seconds
Started Feb 18 12:51:53 PM PST 24
Finished Feb 18 12:52:01 PM PST 24
Peak memory 200260 kb
Host smart-9da70fe0-14d1-4a8a-8b8e-5214df703a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109112182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2109112182
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.4178893510
Short name T412
Test name
Test status
Simulation time 970698372 ps
CPU time 5.07 seconds
Started Feb 18 12:51:50 PM PST 24
Finished Feb 18 12:52:02 PM PST 24
Peak memory 200672 kb
Host smart-a79ecd45-0d95-4ad9-b072-937387df0a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178893510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.4178893510
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2383040975
Short name T526
Test name
Test status
Simulation time 144901052 ps
CPU time 1.21 seconds
Started Feb 18 12:51:51 PM PST 24
Finished Feb 18 12:51:59 PM PST 24
Peak memory 200524 kb
Host smart-04e9475e-4979-45e8-b0f9-c05283e852d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383040975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2383040975
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.999850001
Short name T333
Test name
Test status
Simulation time 253950124 ps
CPU time 1.52 seconds
Started Feb 18 12:51:49 PM PST 24
Finished Feb 18 12:51:55 PM PST 24
Peak memory 200684 kb
Host smart-c06df470-ba25-470a-a800-ef79bcd64d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999850001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.999850001
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3823574016
Short name T398
Test name
Test status
Simulation time 12009630089 ps
CPU time 45.62 seconds
Started Feb 18 12:51:53 PM PST 24
Finished Feb 18 12:52:45 PM PST 24
Peak memory 200860 kb
Host smart-5df1f849-0df6-411b-86d9-a122f466ae3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823574016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3823574016
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.280494581
Short name T415
Test name
Test status
Simulation time 142791812 ps
CPU time 1.88 seconds
Started Feb 18 12:51:51 PM PST 24
Finished Feb 18 12:52:00 PM PST 24
Peak memory 200520 kb
Host smart-449a9a48-ad18-40d0-b5f1-05f93f9485a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280494581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.280494581
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.67127177
Short name T248
Test name
Test status
Simulation time 229417600 ps
CPU time 1.43 seconds
Started Feb 18 12:51:50 PM PST 24
Finished Feb 18 12:51:58 PM PST 24
Peak memory 200500 kb
Host smart-0218c33a-8c12-4743-886d-a2734fbe5124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67127177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.67127177
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3487526695
Short name T110
Test name
Test status
Simulation time 81356281 ps
CPU time 0.78 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:12 PM PST 24
Peak memory 200320 kb
Host smart-1962473d-40ae-4081-aec5-6a29f5c8514b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487526695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3487526695
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.228192048
Short name T39
Test name
Test status
Simulation time 1231322952 ps
CPU time 5.97 seconds
Started Feb 18 12:52:00 PM PST 24
Finished Feb 18 12:52:11 PM PST 24
Peak memory 221472 kb
Host smart-a8c98948-f0c0-4352-8a42-b99c000765a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228192048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.228192048
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2220984138
Short name T222
Test name
Test status
Simulation time 243498258 ps
CPU time 1.08 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:07 PM PST 24
Peak memory 217848 kb
Host smart-1815af32-6ae5-4b86-8d7c-daaea3f81075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220984138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2220984138
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3158397251
Short name T266
Test name
Test status
Simulation time 107274450 ps
CPU time 0.83 seconds
Started Feb 18 12:51:52 PM PST 24
Finished Feb 18 12:52:00 PM PST 24
Peak memory 200284 kb
Host smart-287cb477-6d86-4c13-9a09-0991f80c6630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158397251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3158397251
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.733459750
Short name T8
Test name
Test status
Simulation time 1687667854 ps
CPU time 6.36 seconds
Started Feb 18 12:52:01 PM PST 24
Finished Feb 18 12:52:11 PM PST 24
Peak memory 200788 kb
Host smart-b5d9f432-db2d-4b12-8ee5-6d07440e1866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733459750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.733459750
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1841041905
Short name T407
Test name
Test status
Simulation time 109408379 ps
CPU time 1.05 seconds
Started Feb 18 12:52:01 PM PST 24
Finished Feb 18 12:52:06 PM PST 24
Peak memory 200440 kb
Host smart-14658260-87c0-4275-b07f-b90cda23b376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841041905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1841041905
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2920271101
Short name T142
Test name
Test status
Simulation time 244736678 ps
CPU time 1.49 seconds
Started Feb 18 12:51:49 PM PST 24
Finished Feb 18 12:51:55 PM PST 24
Peak memory 200656 kb
Host smart-faa9afe5-2145-4e4d-9d96-bb9f647b6e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920271101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2920271101
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3183855510
Short name T234
Test name
Test status
Simulation time 1349875482 ps
CPU time 7.33 seconds
Started Feb 18 12:52:06 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 200760 kb
Host smart-516566dc-5276-4683-b3a1-a34e0de32698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183855510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3183855510
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1833824890
Short name T216
Test name
Test status
Simulation time 292369467 ps
CPU time 1.89 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:09 PM PST 24
Peak memory 200472 kb
Host smart-96b27c35-4864-46aa-a0fe-9aca4572166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833824890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1833824890
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3244988679
Short name T70
Test name
Test status
Simulation time 199164339 ps
CPU time 1.29 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:10 PM PST 24
Peak memory 200416 kb
Host smart-5cec466c-5316-47cc-b0d7-06c305bfeea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244988679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3244988679
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1498241613
Short name T95
Test name
Test status
Simulation time 76409848 ps
CPU time 0.93 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200376 kb
Host smart-1c450406-d975-451d-a83f-6f1f06cc41aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498241613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1498241613
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3998348670
Short name T477
Test name
Test status
Simulation time 1220368986 ps
CPU time 5.54 seconds
Started Feb 18 12:52:04 PM PST 24
Finished Feb 18 12:52:15 PM PST 24
Peak memory 217308 kb
Host smart-f96ea0b4-4444-4e97-bb7c-63a5d927888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998348670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3998348670
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.53031953
Short name T186
Test name
Test status
Simulation time 244703591 ps
CPU time 1.04 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 217840 kb
Host smart-5bf8ba0d-5fba-4d57-8f6f-147342363e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53031953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.53031953
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.321061980
Short name T12
Test name
Test status
Simulation time 80163257 ps
CPU time 0.74 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:09 PM PST 24
Peak memory 200224 kb
Host smart-22f1067a-716f-47bc-9f22-56d5d742a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321061980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.321061980
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.4084992982
Short name T521
Test name
Test status
Simulation time 1081421548 ps
CPU time 5.03 seconds
Started Feb 18 12:52:07 PM PST 24
Finished Feb 18 12:52:19 PM PST 24
Peak memory 200800 kb
Host smart-91848dc4-0cd1-463b-9f6f-83d9b1799cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084992982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.4084992982
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.984494807
Short name T469
Test name
Test status
Simulation time 177790597 ps
CPU time 1.17 seconds
Started Feb 18 12:52:00 PM PST 24
Finished Feb 18 12:52:06 PM PST 24
Peak memory 200400 kb
Host smart-dbaf43d5-072e-48a3-b35b-793884a67098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984494807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.984494807
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2453819875
Short name T282
Test name
Test status
Simulation time 249749419 ps
CPU time 1.49 seconds
Started Feb 18 12:51:58 PM PST 24
Finished Feb 18 12:52:05 PM PST 24
Peak memory 200728 kb
Host smart-b412fab9-f422-4532-8f64-86a4ac6d50eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453819875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2453819875
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3443458656
Short name T381
Test name
Test status
Simulation time 12375164417 ps
CPU time 46.32 seconds
Started Feb 18 12:52:04 PM PST 24
Finished Feb 18 12:52:56 PM PST 24
Peak memory 200864 kb
Host smart-a3edc2ff-ad21-49d5-ab94-31486d861e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443458656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3443458656
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.520741264
Short name T325
Test name
Test status
Simulation time 116458249 ps
CPU time 1.5 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:10 PM PST 24
Peak memory 200520 kb
Host smart-dfcf06ed-a3e4-4d06-b867-e52e11ba4a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520741264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.520741264
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.54529435
Short name T410
Test name
Test status
Simulation time 111859825 ps
CPU time 0.98 seconds
Started Feb 18 12:52:01 PM PST 24
Finished Feb 18 12:52:06 PM PST 24
Peak memory 200496 kb
Host smart-8ff3b1c6-d0b1-4b8b-b48c-f2951c282fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54529435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.54529435
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1658639997
Short name T344
Test name
Test status
Simulation time 69622571 ps
CPU time 0.81 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200432 kb
Host smart-cd4f35fc-9c99-4e4a-a2ab-478ecdc8c449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658639997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1658639997
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.587072076
Short name T57
Test name
Test status
Simulation time 2359388788 ps
CPU time 7.89 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:14 PM PST 24
Peak memory 221832 kb
Host smart-a8679367-c0ef-4416-b376-ada2425d0e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587072076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.587072076
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4234735334
Short name T197
Test name
Test status
Simulation time 245248193 ps
CPU time 1.07 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:09 PM PST 24
Peak memory 217912 kb
Host smart-82791ca9-6eb9-4891-9cb4-50306c350440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234735334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4234735334
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3541344447
Short name T329
Test name
Test status
Simulation time 80077048 ps
CPU time 0.73 seconds
Started Feb 18 12:52:06 PM PST 24
Finished Feb 18 12:52:14 PM PST 24
Peak memory 200328 kb
Host smart-6a1b1cd3-4675-4982-9a55-659276acb3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541344447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3541344447
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1248027428
Short name T359
Test name
Test status
Simulation time 1683919774 ps
CPU time 6.32 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:12 PM PST 24
Peak memory 200652 kb
Host smart-7a614ef5-2c14-4440-a155-63629fb2f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248027428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1248027428
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2211423903
Short name T230
Test name
Test status
Simulation time 147998058 ps
CPU time 1.07 seconds
Started Feb 18 12:52:04 PM PST 24
Finished Feb 18 12:52:12 PM PST 24
Peak memory 200532 kb
Host smart-8699df2a-4180-4cd1-8055-a8dbf186f316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211423903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2211423903
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1762666288
Short name T45
Test name
Test status
Simulation time 196332925 ps
CPU time 1.37 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200716 kb
Host smart-b4122148-4428-4a28-8a92-e4be07c740e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762666288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1762666288
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2700967121
Short name T209
Test name
Test status
Simulation time 3945151064 ps
CPU time 15.51 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 200848 kb
Host smart-92aba3ed-6af4-416f-a769-d33d3933d49b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700967121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2700967121
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3453292807
Short name T286
Test name
Test status
Simulation time 417410368 ps
CPU time 2.34 seconds
Started Feb 18 12:52:06 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200508 kb
Host smart-3cd6c3ad-f7f8-4e06-b9b0-7ae55f8c2916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453292807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3453292807
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1256890213
Short name T472
Test name
Test status
Simulation time 76077978 ps
CPU time 0.82 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200484 kb
Host smart-e2da5499-030f-46e2-8ee3-feea71982c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256890213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1256890213
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2872875355
Short name T349
Test name
Test status
Simulation time 66993179 ps
CPU time 0.76 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:09 PM PST 24
Peak memory 200408 kb
Host smart-2c44f60f-ee11-4041-83c1-d48619a7f8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872875355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2872875355
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.643458194
Short name T37
Test name
Test status
Simulation time 1230280763 ps
CPU time 5.88 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:11 PM PST 24
Peak memory 218472 kb
Host smart-d5aa43a8-4545-4ec6-b366-2e1553057be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643458194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.643458194
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1507794153
Short name T408
Test name
Test status
Simulation time 247958049 ps
CPU time 1.13 seconds
Started Feb 18 12:51:59 PM PST 24
Finished Feb 18 12:52:05 PM PST 24
Peak memory 217796 kb
Host smart-cf45f8f5-2d3c-4dc9-a8d1-a7b167f26d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507794153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1507794153
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3499687283
Short name T444
Test name
Test status
Simulation time 149360779 ps
CPU time 0.8 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200364 kb
Host smart-aaea4c3f-f25d-4980-8cf0-f2979704f961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499687283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3499687283
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3500839367
Short name T397
Test name
Test status
Simulation time 865500805 ps
CPU time 4.63 seconds
Started Feb 18 12:52:00 PM PST 24
Finished Feb 18 12:52:09 PM PST 24
Peak memory 200724 kb
Host smart-c7affcc7-9966-4949-8a13-e9e41291d2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500839367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3500839367
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2074830743
Short name T153
Test name
Test status
Simulation time 154446543 ps
CPU time 1.08 seconds
Started Feb 18 12:52:01 PM PST 24
Finished Feb 18 12:52:06 PM PST 24
Peak memory 200512 kb
Host smart-fca4a5ab-87e1-48d4-aded-6f0c9bc80d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074830743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2074830743
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.4213559213
Short name T471
Test name
Test status
Simulation time 203027405 ps
CPU time 1.4 seconds
Started Feb 18 12:52:04 PM PST 24
Finished Feb 18 12:52:12 PM PST 24
Peak memory 200628 kb
Host smart-fd7bcba7-f21c-4b48-9f2f-53427209da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213559213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4213559213
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2677586008
Short name T120
Test name
Test status
Simulation time 6448006226 ps
CPU time 24.4 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:34 PM PST 24
Peak memory 200844 kb
Host smart-fde1e4a5-f6b3-415c-94c1-674947079c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677586008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2677586008
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1804225135
Short name T157
Test name
Test status
Simulation time 135780019 ps
CPU time 1.68 seconds
Started Feb 18 12:52:01 PM PST 24
Finished Feb 18 12:52:07 PM PST 24
Peak memory 200488 kb
Host smart-ebf41744-82b8-44b8-8eed-5e0b63574a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804225135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1804225135
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.4235006977
Short name T463
Test name
Test status
Simulation time 229024308 ps
CPU time 1.37 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:07 PM PST 24
Peak memory 200392 kb
Host smart-2976b2fc-742e-40d5-9142-78f06831d0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235006977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.4235006977
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.4131886787
Short name T483
Test name
Test status
Simulation time 68031546 ps
CPU time 0.77 seconds
Started Feb 18 12:52:04 PM PST 24
Finished Feb 18 12:52:12 PM PST 24
Peak memory 200328 kb
Host smart-8a122b3c-0696-4dac-916f-e7b698b365ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131886787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.4131886787
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.56969281
Short name T3
Test name
Test status
Simulation time 2364094395 ps
CPU time 7.54 seconds
Started Feb 18 12:52:12 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 218244 kb
Host smart-864ffd52-1574-4114-a3ef-da308b108726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56969281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.56969281
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.839485624
Short name T94
Test name
Test status
Simulation time 244065370 ps
CPU time 1.09 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:13 PM PST 24
Peak memory 217812 kb
Host smart-893948c4-76d6-486b-915b-80b22e59024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839485624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.839485624
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.550212413
Short name T274
Test name
Test status
Simulation time 170540543 ps
CPU time 0.79 seconds
Started Feb 18 12:52:04 PM PST 24
Finished Feb 18 12:52:11 PM PST 24
Peak memory 200332 kb
Host smart-957c4fc0-6008-4d86-bf0d-0a7d3ec777e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550212413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.550212413
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1592102075
Short name T121
Test name
Test status
Simulation time 1573843608 ps
CPU time 7.02 seconds
Started Feb 18 12:52:04 PM PST 24
Finished Feb 18 12:52:18 PM PST 24
Peak memory 200752 kb
Host smart-26604d3c-6066-40c3-8db1-5a9abc2f1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592102075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1592102075
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2393928487
Short name T363
Test name
Test status
Simulation time 91582184 ps
CPU time 0.97 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 200552 kb
Host smart-c183b7d6-c490-44f0-afdc-457d2d953f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393928487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2393928487
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3521687375
Short name T508
Test name
Test status
Simulation time 112872881 ps
CPU time 1.17 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:07 PM PST 24
Peak memory 200692 kb
Host smart-486a01f6-b73a-486e-ae40-32c0ad340ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521687375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3521687375
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2993650370
Short name T424
Test name
Test status
Simulation time 5903166955 ps
CPU time 21.25 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:42 PM PST 24
Peak memory 200496 kb
Host smart-a47b038b-0670-49e3-a8ea-f74020808bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993650370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2993650370
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.354667426
Short name T409
Test name
Test status
Simulation time 496608321 ps
CPU time 2.39 seconds
Started Feb 18 12:52:12 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 200408 kb
Host smart-6da08db6-03ae-4117-8367-8b4e74009593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354667426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.354667426
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1370869576
Short name T190
Test name
Test status
Simulation time 117274499 ps
CPU time 0.92 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:13 PM PST 24
Peak memory 200520 kb
Host smart-fab7f84b-5abd-4e5f-81e4-9966585bfa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370869576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1370869576
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.531294656
Short name T87
Test name
Test status
Simulation time 77480235 ps
CPU time 0.8 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 200436 kb
Host smart-5a47861a-e3db-4a31-8523-14bcc8bed9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531294656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.531294656
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3039286238
Short name T58
Test name
Test status
Simulation time 1892175405 ps
CPU time 7.25 seconds
Started Feb 18 12:52:08 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 217992 kb
Host smart-c2c98913-7639-4401-8e9e-13a82de05043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039286238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3039286238
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.36909891
Short name T242
Test name
Test status
Simulation time 246204225 ps
CPU time 1.02 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:07 PM PST 24
Peak memory 217796 kb
Host smart-1efb78d5-7689-46ac-94b9-1a3ea7da872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36909891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.36909891
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1874746331
Short name T19
Test name
Test status
Simulation time 258077679 ps
CPU time 0.99 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200312 kb
Host smart-0a6928e8-db4c-4398-aa9a-1b32d39c8452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874746331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1874746331
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3834987756
Short name T532
Test name
Test status
Simulation time 1578510609 ps
CPU time 5.78 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 200656 kb
Host smart-ece58b43-804d-4f94-8573-e82cfa771214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834987756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3834987756
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2631180439
Short name T473
Test name
Test status
Simulation time 175689368 ps
CPU time 1.22 seconds
Started Feb 18 12:52:10 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 200588 kb
Host smart-6cf0eaac-0f23-4474-a962-ccad1c51c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631180439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2631180439
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.254187695
Short name T218
Test name
Test status
Simulation time 230332468 ps
CPU time 1.48 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:14 PM PST 24
Peak memory 200688 kb
Host smart-c69ef4c9-6231-4901-8017-6ca2736e92ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254187695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.254187695
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.775936604
Short name T355
Test name
Test status
Simulation time 900583814 ps
CPU time 4.43 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 200660 kb
Host smart-c7bc9148-cf10-4cf0-88d7-ed196cbcc4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775936604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.775936604
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.90716354
Short name T455
Test name
Test status
Simulation time 122817357 ps
CPU time 1.52 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200476 kb
Host smart-df6f5330-a427-48eb-89e4-6bfba8105dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90716354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.90716354
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.564504565
Short name T227
Test name
Test status
Simulation time 143901558 ps
CPU time 1.11 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:18 PM PST 24
Peak memory 200416 kb
Host smart-906c293a-920f-49db-a119-ae82ece550a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564504565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.564504565
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2177749389
Short name T534
Test name
Test status
Simulation time 75407490 ps
CPU time 0.76 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 200432 kb
Host smart-08cf8afe-9fce-4ef0-be9a-15e2ea3b655f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177749389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2177749389
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3190703089
Short name T364
Test name
Test status
Simulation time 1229425574 ps
CPU time 5.92 seconds
Started Feb 18 12:52:10 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 222116 kb
Host smart-335f58f4-c29d-4bd1-9087-59eeb894b13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190703089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3190703089
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.970777265
Short name T502
Test name
Test status
Simulation time 244616543 ps
CPU time 1.06 seconds
Started Feb 18 12:52:10 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 217884 kb
Host smart-01b8cc5c-c430-48d0-aefe-771cfbfbac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970777265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.970777265
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1993980409
Short name T17
Test name
Test status
Simulation time 158782796 ps
CPU time 0.82 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200364 kb
Host smart-4ad50253-f4d7-4d80-84f9-c057acb7b5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993980409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1993980409
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3845459980
Short name T119
Test name
Test status
Simulation time 862156925 ps
CPU time 4.4 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 200764 kb
Host smart-cbac5598-6c09-446a-94a0-dfb4d53edb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845459980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3845459980
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3293380723
Short name T91
Test name
Test status
Simulation time 149620545 ps
CPU time 1.04 seconds
Started Feb 18 12:52:09 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200540 kb
Host smart-d54e35bb-7455-4324-bcc2-55397aa2e78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293380723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3293380723
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.4100991096
Short name T460
Test name
Test status
Simulation time 118208321 ps
CPU time 1.19 seconds
Started Feb 18 12:52:10 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 200760 kb
Host smart-94e2fb86-29fb-444d-af0b-4ea1684a8e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100991096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.4100991096
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2994764966
Short name T466
Test name
Test status
Simulation time 3377273968 ps
CPU time 14.5 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:27 PM PST 24
Peak memory 200840 kb
Host smart-2106aafe-7336-4a58-8861-dd9bb8c8af9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994764966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2994764966
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.250145767
Short name T187
Test name
Test status
Simulation time 114528150 ps
CPU time 1.55 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:14 PM PST 24
Peak memory 200488 kb
Host smart-8c7c7ab7-1785-4ada-9e5a-bbde90f02530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250145767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.250145767
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3585817881
Short name T464
Test name
Test status
Simulation time 236832584 ps
CPU time 1.4 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:14 PM PST 24
Peak memory 200520 kb
Host smart-e16855fa-ec37-4939-a835-7e6e52ee2494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585817881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3585817881
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2949065388
Short name T393
Test name
Test status
Simulation time 71610115 ps
CPU time 0.82 seconds
Started Feb 18 12:51:10 PM PST 24
Finished Feb 18 12:51:13 PM PST 24
Peak memory 200396 kb
Host smart-c2b1c6a4-cba5-4aaf-a3f8-f7f55836b2d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949065388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2949065388
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1050165421
Short name T330
Test name
Test status
Simulation time 1218621628 ps
CPU time 5.8 seconds
Started Feb 18 12:51:07 PM PST 24
Finished Feb 18 12:51:15 PM PST 24
Peak memory 221688 kb
Host smart-14f30d84-0b54-412b-823b-9cfc502fc1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050165421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1050165421
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1206300477
Short name T268
Test name
Test status
Simulation time 243948405 ps
CPU time 1.2 seconds
Started Feb 18 12:51:06 PM PST 24
Finished Feb 18 12:51:09 PM PST 24
Peak memory 217736 kb
Host smart-9d1b06b4-d4eb-4189-b8b4-c17976e0cd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206300477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1206300477
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.764556790
Short name T18
Test name
Test status
Simulation time 141201698 ps
CPU time 0.82 seconds
Started Feb 18 12:51:09 PM PST 24
Finished Feb 18 12:51:12 PM PST 24
Peak memory 200320 kb
Host smart-bc743395-11a8-40fb-a39e-ec5c53f435a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764556790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.764556790
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2681732321
Short name T253
Test name
Test status
Simulation time 1111170769 ps
CPU time 5.01 seconds
Started Feb 18 12:51:09 PM PST 24
Finished Feb 18 12:51:15 PM PST 24
Peak memory 200748 kb
Host smart-4752bc13-c7b1-4639-a277-fc6c87b457fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681732321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2681732321
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.934852707
Short name T85
Test name
Test status
Simulation time 8404982751 ps
CPU time 13.76 seconds
Started Feb 18 12:51:14 PM PST 24
Finished Feb 18 12:51:31 PM PST 24
Peak memory 218344 kb
Host smart-55222491-e443-4092-a734-0a683657599e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934852707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.934852707
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3112275877
Short name T513
Test name
Test status
Simulation time 180898190 ps
CPU time 1.16 seconds
Started Feb 18 12:51:14 PM PST 24
Finished Feb 18 12:51:18 PM PST 24
Peak memory 200520 kb
Host smart-ca92fb41-4925-463f-9aba-2c01bc289903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112275877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3112275877
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3031547680
Short name T327
Test name
Test status
Simulation time 190357470 ps
CPU time 1.39 seconds
Started Feb 18 12:51:08 PM PST 24
Finished Feb 18 12:51:11 PM PST 24
Peak memory 200104 kb
Host smart-68513071-7119-4062-9eb1-cbf5ce15aa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031547680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3031547680
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2919312193
Short name T219
Test name
Test status
Simulation time 3868179909 ps
CPU time 13.71 seconds
Started Feb 18 12:51:12 PM PST 24
Finished Feb 18 12:51:28 PM PST 24
Peak memory 200020 kb
Host smart-eda38ac8-52f7-42fa-9683-c9cd6b8c9157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919312193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2919312193
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2516710384
Short name T345
Test name
Test status
Simulation time 417946447 ps
CPU time 2.21 seconds
Started Feb 18 12:51:18 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 200404 kb
Host smart-79d1102d-7f74-461b-9944-1a681c6013c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516710384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2516710384
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2694891924
Short name T46
Test name
Test status
Simulation time 118195103 ps
CPU time 1.1 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:24 PM PST 24
Peak memory 200516 kb
Host smart-f5ab7795-fa06-4f4e-84fa-cc34989bae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694891924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2694891924
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1545611093
Short name T210
Test name
Test status
Simulation time 69233403 ps
CPU time 0.73 seconds
Started Feb 18 12:52:08 PM PST 24
Finished Feb 18 12:52:15 PM PST 24
Peak memory 200416 kb
Host smart-81ec0617-de39-42d2-8347-ad93565f5372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545611093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1545611093
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1802039417
Short name T402
Test name
Test status
Simulation time 1908917391 ps
CPU time 7.35 seconds
Started Feb 18 12:52:12 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 217360 kb
Host smart-94507fb4-a210-40f0-9a92-159e011b387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802039417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1802039417
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.4125452707
Short name T443
Test name
Test status
Simulation time 244024569 ps
CPU time 1.07 seconds
Started Feb 18 12:52:08 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 217864 kb
Host smart-cecd3f14-4bf7-4e87-b90f-e337b5ddd090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125452707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.4125452707
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.266019787
Short name T280
Test name
Test status
Simulation time 153443777 ps
CPU time 0.84 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:09 PM PST 24
Peak memory 200316 kb
Host smart-49856366-b834-4c75-9888-72b903801ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266019787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.266019787
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.247860869
Short name T10
Test name
Test status
Simulation time 1931078443 ps
CPU time 6.93 seconds
Started Feb 18 12:52:12 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 200664 kb
Host smart-24783c82-ad97-43ea-beff-121a0de11ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247860869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.247860869
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.56033889
Short name T111
Test name
Test status
Simulation time 106164413 ps
CPU time 0.96 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 200052 kb
Host smart-7bd1ee7c-782c-41e7-a54e-36a46cf38233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56033889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.56033889
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.780333877
Short name T317
Test name
Test status
Simulation time 110574769 ps
CPU time 1.18 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 200748 kb
Host smart-7675ca08-a558-45cc-b7e0-f9779cce4bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780333877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.780333877
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1424906098
Short name T122
Test name
Test status
Simulation time 2082503743 ps
CPU time 11.44 seconds
Started Feb 18 12:52:09 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200756 kb
Host smart-9061eb44-db84-471f-8457-23f74695fc39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424906098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1424906098
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1491651288
Short name T379
Test name
Test status
Simulation time 435609499 ps
CPU time 2.38 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 200404 kb
Host smart-129882db-c7f9-4719-9275-ff2049455901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491651288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1491651288
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1588000081
Short name T489
Test name
Test status
Simulation time 158483939 ps
CPU time 1.25 seconds
Started Feb 18 12:52:04 PM PST 24
Finished Feb 18 12:52:12 PM PST 24
Peak memory 200428 kb
Host smart-69cedc8a-d85d-4eb3-b405-45e6e90825ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588000081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1588000081
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1008907017
Short name T233
Test name
Test status
Simulation time 62531101 ps
CPU time 0.77 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:18 PM PST 24
Peak memory 200428 kb
Host smart-b87467cc-8c37-41b9-9278-219b701679b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008907017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1008907017
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2904734182
Short name T527
Test name
Test status
Simulation time 1888135753 ps
CPU time 6.99 seconds
Started Feb 18 12:52:25 PM PST 24
Finished Feb 18 12:52:35 PM PST 24
Peak memory 222544 kb
Host smart-1384c1b0-ce52-4b46-bbf0-fe6c90d2207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904734182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2904734182
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1751898652
Short name T428
Test name
Test status
Simulation time 244204093 ps
CPU time 1.1 seconds
Started Feb 18 12:52:17 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 217724 kb
Host smart-ac259bb2-9f6b-412d-95b4-f24b52bde23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751898652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1751898652
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2434007866
Short name T307
Test name
Test status
Simulation time 94112986 ps
CPU time 0.75 seconds
Started Feb 18 12:52:02 PM PST 24
Finished Feb 18 12:52:06 PM PST 24
Peak memory 200156 kb
Host smart-84f0a208-5162-48e1-9cbb-cf9debd292f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434007866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2434007866
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.400743964
Short name T500
Test name
Test status
Simulation time 673712403 ps
CPU time 3.72 seconds
Started Feb 18 12:52:05 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200740 kb
Host smart-82beb97d-908b-4783-970b-913d204f36e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400743964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.400743964
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2572174873
Short name T350
Test name
Test status
Simulation time 106533216 ps
CPU time 1 seconds
Started Feb 18 12:52:08 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200544 kb
Host smart-ad0dbbb1-9ade-4872-94a5-64f699423c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572174873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2572174873
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.14378166
Short name T352
Test name
Test status
Simulation time 121407904 ps
CPU time 1.29 seconds
Started Feb 18 12:52:03 PM PST 24
Finished Feb 18 12:52:08 PM PST 24
Peak memory 200584 kb
Host smart-c3079128-a0cf-4a79-a150-6e8c6a2c4d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14378166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.14378166
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1196759388
Short name T465
Test name
Test status
Simulation time 3763141455 ps
CPU time 14.36 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:35 PM PST 24
Peak memory 200896 kb
Host smart-4d1bd6ae-fc70-42b5-99c2-da0c656749ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196759388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1196759388
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1291095151
Short name T270
Test name
Test status
Simulation time 340440685 ps
CPU time 2.3 seconds
Started Feb 18 12:52:10 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 200536 kb
Host smart-454905c5-d114-4236-81ed-079ec54116c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291095151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1291095151
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3492870951
Short name T435
Test name
Test status
Simulation time 69325263 ps
CPU time 0.81 seconds
Started Feb 18 12:52:10 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200516 kb
Host smart-bc9022db-3c26-42ee-9ff0-ffae3f976de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492870951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3492870951
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1966290625
Short name T184
Test name
Test status
Simulation time 77659553 ps
CPU time 0.77 seconds
Started Feb 18 12:52:08 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200384 kb
Host smart-4f5e1768-d23c-4eea-9032-5050526a46c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966290625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1966290625
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.4249277394
Short name T50
Test name
Test status
Simulation time 1228256789 ps
CPU time 6.37 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 217936 kb
Host smart-ebccdd47-0c63-45f2-b80c-5f8e3773303f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249277394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4249277394
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2577208193
Short name T152
Test name
Test status
Simulation time 244284300 ps
CPU time 1.11 seconds
Started Feb 18 12:52:12 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 217876 kb
Host smart-46199fd1-a980-483e-a021-5dc03b3d9c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577208193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2577208193
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1549461691
Short name T20
Test name
Test status
Simulation time 146069890 ps
CPU time 0.84 seconds
Started Feb 18 12:52:13 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 200128 kb
Host smart-87887704-332e-4d4d-8336-5caae4bf52e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549461691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1549461691
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1386426299
Short name T7
Test name
Test status
Simulation time 1455545503 ps
CPU time 5.34 seconds
Started Feb 18 12:52:08 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 200768 kb
Host smart-06b580aa-7d3a-469b-938c-03fff38168fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386426299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1386426299
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2621517934
Short name T29
Test name
Test status
Simulation time 106986677 ps
CPU time 1.03 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 200536 kb
Host smart-3183539a-5cf7-483f-bfe2-5cff38b901bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621517934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2621517934
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3398037800
Short name T236
Test name
Test status
Simulation time 195578572 ps
CPU time 1.41 seconds
Started Feb 18 12:52:19 PM PST 24
Finished Feb 18 12:52:24 PM PST 24
Peak memory 200732 kb
Host smart-4a3e4ff6-035b-44db-af91-a994b181139f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398037800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3398037800
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3794973732
Short name T367
Test name
Test status
Simulation time 11529129781 ps
CPU time 36.7 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:54 PM PST 24
Peak memory 200840 kb
Host smart-ee55bafd-629a-4625-8eab-a9c9236f0589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794973732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3794973732
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.550332667
Short name T204
Test name
Test status
Simulation time 340119040 ps
CPU time 2.19 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:31 PM PST 24
Peak memory 200536 kb
Host smart-497ab893-0200-46a1-ae12-0e455e86ef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550332667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.550332667
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.4244160530
Short name T71
Test name
Test status
Simulation time 96649989 ps
CPU time 0.99 seconds
Started Feb 18 12:52:09 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200536 kb
Host smart-479f58e1-642a-4185-a0a1-4f42ad27ad98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244160530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.4244160530
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2459066863
Short name T484
Test name
Test status
Simulation time 73730813 ps
CPU time 0.77 seconds
Started Feb 18 12:52:12 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 200428 kb
Host smart-9e93eac8-73e5-4a51-b569-b46a7af09bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459066863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2459066863
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2517135817
Short name T35
Test name
Test status
Simulation time 1226961846 ps
CPU time 5.68 seconds
Started Feb 18 12:52:12 PM PST 24
Finished Feb 18 12:52:24 PM PST 24
Peak memory 222540 kb
Host smart-c0a7bfc2-a0e0-409f-85d6-61f67614b553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517135817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2517135817
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.884225026
Short name T294
Test name
Test status
Simulation time 244494929 ps
CPU time 1.13 seconds
Started Feb 18 12:52:13 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 217452 kb
Host smart-03dc74aa-e25e-480c-93bb-c2e19ceb8a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884225026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.884225026
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2489455820
Short name T196
Test name
Test status
Simulation time 86497349 ps
CPU time 0.74 seconds
Started Feb 18 12:52:10 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200320 kb
Host smart-db6b0f99-5d95-486a-a436-73756b610fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489455820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2489455820
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.798113465
Short name T137
Test name
Test status
Simulation time 1749743696 ps
CPU time 7 seconds
Started Feb 18 12:52:08 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 200776 kb
Host smart-c81a38a5-e6b3-48b7-b0c4-8875b82b3906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798113465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.798113465
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.257802271
Short name T452
Test name
Test status
Simulation time 144238261 ps
CPU time 1.1 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 200528 kb
Host smart-16545aa7-e726-4c35-a126-4a10f9c635a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257802271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.257802271
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1674332250
Short name T380
Test name
Test status
Simulation time 207991091 ps
CPU time 1.56 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 200712 kb
Host smart-bc93437b-fcb6-443b-8117-b65072867ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674332250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1674332250
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1119149529
Short name T114
Test name
Test status
Simulation time 5249322943 ps
CPU time 22.75 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:39 PM PST 24
Peak memory 200912 kb
Host smart-7dd895ce-a979-4bb8-b7c0-c943866329a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119149529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1119149529
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3434192377
Short name T231
Test name
Test status
Simulation time 124442109 ps
CPU time 1.67 seconds
Started Feb 18 12:52:09 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 200500 kb
Host smart-578dedc3-05bb-4aa5-b029-b2cdb5cb66ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434192377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3434192377
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.687099592
Short name T519
Test name
Test status
Simulation time 168663009 ps
CPU time 1.44 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:18 PM PST 24
Peak memory 200700 kb
Host smart-4aaf285e-b212-4ee9-a463-200b622b7cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687099592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.687099592
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1043014617
Short name T449
Test name
Test status
Simulation time 72488087 ps
CPU time 0.75 seconds
Started Feb 18 12:52:07 PM PST 24
Finished Feb 18 12:52:14 PM PST 24
Peak memory 200408 kb
Host smart-8522aac4-2ebe-487f-935e-dd13e2c624c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043014617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1043014617
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2630724510
Short name T514
Test name
Test status
Simulation time 1215253337 ps
CPU time 5.58 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 217428 kb
Host smart-bc954e99-620e-43ca-b6e3-f95fd8728ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630724510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2630724510
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.964568935
Short name T214
Test name
Test status
Simulation time 244899785 ps
CPU time 1.05 seconds
Started Feb 18 12:52:12 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 217868 kb
Host smart-dfb3b8e1-705b-41d1-a7d8-62813360c8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964568935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.964568935
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3265128851
Short name T278
Test name
Test status
Simulation time 115109985 ps
CPU time 0.74 seconds
Started Feb 18 12:52:06 PM PST 24
Finished Feb 18 12:52:14 PM PST 24
Peak memory 200280 kb
Host smart-97e0699e-eb05-45cb-ac9b-6a3c1c47b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265128851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3265128851
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1272455356
Short name T361
Test name
Test status
Simulation time 933905918 ps
CPU time 4.1 seconds
Started Feb 18 12:52:07 PM PST 24
Finished Feb 18 12:52:18 PM PST 24
Peak memory 200720 kb
Host smart-21c82166-5da2-4924-85be-54c4492534aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272455356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1272455356
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.266843859
Short name T44
Test name
Test status
Simulation time 108034689 ps
CPU time 0.97 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:31 PM PST 24
Peak memory 200524 kb
Host smart-c7d27dd0-90ba-448d-8243-950f46513de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266843859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.266843859
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2869876440
Short name T225
Test name
Test status
Simulation time 121660943 ps
CPU time 1.19 seconds
Started Feb 18 12:52:09 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200672 kb
Host smart-e5aaa1c3-d9fd-40dc-9bdd-b7856e283bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869876440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2869876440
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2714243487
Short name T420
Test name
Test status
Simulation time 12091538402 ps
CPU time 39.96 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:56 PM PST 24
Peak memory 200840 kb
Host smart-b49a821e-4742-4260-9174-1b9f5048d0a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714243487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2714243487
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1306717728
Short name T323
Test name
Test status
Simulation time 493459225 ps
CPU time 2.7 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 200524 kb
Host smart-06c33566-3812-434a-a972-62ffd21ecde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306717728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1306717728
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3254601255
Short name T528
Test name
Test status
Simulation time 88076271 ps
CPU time 0.79 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 200508 kb
Host smart-2b3bc1f2-848a-4716-8b3a-9d9e213e4d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254601255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3254601255
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3118608027
Short name T288
Test name
Test status
Simulation time 78319510 ps
CPU time 0.73 seconds
Started Feb 18 12:52:13 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 200380 kb
Host smart-ea142397-2a2a-48f9-a328-d4d68a4a12a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118608027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3118608027
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.21187263
Short name T524
Test name
Test status
Simulation time 1893750232 ps
CPU time 7.1 seconds
Started Feb 18 12:52:11 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 217960 kb
Host smart-c85e924a-787a-42b6-b17b-bd3175539346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21187263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.21187263
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.386359458
Short name T92
Test name
Test status
Simulation time 243859686 ps
CPU time 1.07 seconds
Started Feb 18 12:52:16 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 217728 kb
Host smart-99f20dd0-60e2-4980-af89-fcca68c20525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386359458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.386359458
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.208276925
Short name T485
Test name
Test status
Simulation time 155443122 ps
CPU time 0.85 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 200308 kb
Host smart-04ffdca3-875d-4ce8-b964-a018981fc1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208276925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.208276925
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2396950608
Short name T332
Test name
Test status
Simulation time 1883132799 ps
CPU time 6.99 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:37 PM PST 24
Peak memory 200764 kb
Host smart-4f1e8550-26b7-4b53-8e25-e12d6c41c925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396950608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2396950608
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4161027680
Short name T432
Test name
Test status
Simulation time 97116979 ps
CPU time 0.99 seconds
Started Feb 18 12:52:09 PM PST 24
Finished Feb 18 12:52:16 PM PST 24
Peak memory 200548 kb
Host smart-04e2aa7a-60c2-4dc3-b6bb-b7d618b9ebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161027680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4161027680
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.148150216
Short name T384
Test name
Test status
Simulation time 118621373 ps
CPU time 1.2 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:31 PM PST 24
Peak memory 200680 kb
Host smart-b89b624d-064b-4296-bf4f-aac065fc323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148150216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.148150216
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1457520287
Short name T240
Test name
Test status
Simulation time 2027384026 ps
CPU time 8.54 seconds
Started Feb 18 12:52:13 PM PST 24
Finished Feb 18 12:52:27 PM PST 24
Peak memory 200688 kb
Host smart-2f5a284f-5584-46c8-97c4-6d3879866adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457520287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1457520287
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2682221451
Short name T90
Test name
Test status
Simulation time 244830365 ps
CPU time 1.83 seconds
Started Feb 18 12:52:13 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 200300 kb
Host smart-789be1a4-237e-4675-bc56-ac5b37f94ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682221451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2682221451
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2879061205
Short name T389
Test name
Test status
Simulation time 102327562 ps
CPU time 0.85 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:31 PM PST 24
Peak memory 200520 kb
Host smart-8a86e064-750c-47e9-8027-49f198ffb1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879061205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2879061205
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3201690849
Short name T151
Test name
Test status
Simulation time 77578972 ps
CPU time 0.84 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 200320 kb
Host smart-50cbcf15-b1f4-459c-abe5-8735cd6a9ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201690849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3201690849
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4164664571
Short name T461
Test name
Test status
Simulation time 1224626185 ps
CPU time 6.17 seconds
Started Feb 18 12:52:18 PM PST 24
Finished Feb 18 12:52:29 PM PST 24
Peak memory 222456 kb
Host smart-8728a235-999a-4c5e-8ea3-624158544efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164664571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4164664571
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2900464579
Short name T357
Test name
Test status
Simulation time 244704689 ps
CPU time 1.15 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 217844 kb
Host smart-443a61aa-2c7b-459f-8e20-c1e9cb79524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900464579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2900464579
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1292798128
Short name T255
Test name
Test status
Simulation time 161205822 ps
CPU time 0.89 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 200312 kb
Host smart-7d9cacd8-e3f3-4f41-8967-168e27a49337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292798128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1292798128
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.460767128
Short name T498
Test name
Test status
Simulation time 1598200727 ps
CPU time 6.43 seconds
Started Feb 18 12:52:18 PM PST 24
Finished Feb 18 12:52:29 PM PST 24
Peak memory 200764 kb
Host smart-7ecc6a21-e793-4c51-92fe-e39c05b212ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460767128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.460767128
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1893266734
Short name T43
Test name
Test status
Simulation time 140956713 ps
CPU time 1.16 seconds
Started Feb 18 12:52:19 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 200532 kb
Host smart-f03f8e94-a52d-4d9c-8e13-fa529abc92df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893266734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1893266734
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3140240230
Short name T290
Test name
Test status
Simulation time 202873145 ps
CPU time 1.39 seconds
Started Feb 18 12:52:24 PM PST 24
Finished Feb 18 12:52:27 PM PST 24
Peak memory 200696 kb
Host smart-bf5f7c18-1a1f-431e-9b59-03414ab15a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140240230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3140240230
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1798876115
Short name T304
Test name
Test status
Simulation time 7834843832 ps
CPU time 30.5 seconds
Started Feb 18 12:52:17 PM PST 24
Finished Feb 18 12:52:53 PM PST 24
Peak memory 200920 kb
Host smart-32e380df-95aa-449f-90ae-599dda222945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798876115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1798876115
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2304509621
Short name T55
Test name
Test status
Simulation time 116320575 ps
CPU time 1.41 seconds
Started Feb 18 12:52:17 PM PST 24
Finished Feb 18 12:52:24 PM PST 24
Peak memory 200492 kb
Host smart-702edb7d-dfc2-4891-8987-59b6b0f9b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304509621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2304509621
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2865501781
Short name T369
Test name
Test status
Simulation time 222453139 ps
CPU time 1.22 seconds
Started Feb 18 12:52:13 PM PST 24
Finished Feb 18 12:52:20 PM PST 24
Peak memory 200500 kb
Host smart-8e7821c9-f6ec-4d0a-a078-4f9a59c4fc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865501781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2865501781
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.295846870
Short name T269
Test name
Test status
Simulation time 74862834 ps
CPU time 0.8 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 200420 kb
Host smart-0dbd2bba-c049-41ac-b4c1-d5436241c35a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295846870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.295846870
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1399752774
Short name T475
Test name
Test status
Simulation time 1899579466 ps
CPU time 7.46 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:32 PM PST 24
Peak memory 222032 kb
Host smart-18669c84-9a8c-40aa-b0b8-03f8ea4b6fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399752774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1399752774
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.614315903
Short name T64
Test name
Test status
Simulation time 243906157 ps
CPU time 1.08 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:21 PM PST 24
Peak memory 217820 kb
Host smart-e348129b-9699-4c26-a06e-76b4affea12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614315903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.614315903
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2415029815
Short name T423
Test name
Test status
Simulation time 136443142 ps
CPU time 0.85 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 200340 kb
Host smart-9c235849-4833-4db7-b615-9fd41bc22276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415029815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2415029815
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1110678786
Short name T439
Test name
Test status
Simulation time 913546727 ps
CPU time 4.86 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:29 PM PST 24
Peak memory 200772 kb
Host smart-de0c41dd-1a3b-4a89-a9d5-500805cdc3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110678786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1110678786
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1119479965
Short name T517
Test name
Test status
Simulation time 108159791 ps
CPU time 1.02 seconds
Started Feb 18 12:52:16 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 200524 kb
Host smart-348dff7e-0c0e-4691-b9a6-ff26d05df08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119479965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1119479965
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2642024739
Short name T417
Test name
Test status
Simulation time 251232980 ps
CPU time 1.57 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 200716 kb
Host smart-7d7b53bb-76d2-4fe1-bb6c-325250403acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642024739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2642024739
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4140661285
Short name T113
Test name
Test status
Simulation time 5492947553 ps
CPU time 18.7 seconds
Started Feb 18 12:52:17 PM PST 24
Finished Feb 18 12:52:41 PM PST 24
Peak memory 200884 kb
Host smart-07ded113-4f83-4cb1-b7ca-d7f47f05c0ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140661285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4140661285
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3378774761
Short name T141
Test name
Test status
Simulation time 314360069 ps
CPU time 1.85 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200512 kb
Host smart-9843caf9-52f8-47e8-ae80-8d396f5ccda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378774761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3378774761
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2710468517
Short name T292
Test name
Test status
Simulation time 120201215 ps
CPU time 1.02 seconds
Started Feb 18 12:52:18 PM PST 24
Finished Feb 18 12:52:24 PM PST 24
Peak memory 200504 kb
Host smart-005ced0d-b262-4979-b537-34c78aad8e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710468517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2710468517
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1911175564
Short name T503
Test name
Test status
Simulation time 56498958 ps
CPU time 0.7 seconds
Started Feb 18 12:52:17 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 200412 kb
Host smart-fae7b332-2e1c-4c32-b939-3af77fc5afc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911175564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1911175564
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.106910827
Short name T440
Test name
Test status
Simulation time 1220754652 ps
CPU time 5.38 seconds
Started Feb 18 12:52:13 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 222528 kb
Host smart-6b97d289-9e59-45a1-b65c-555ffd55b509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106910827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.106910827
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3393010507
Short name T232
Test name
Test status
Simulation time 244411083 ps
CPU time 1.06 seconds
Started Feb 18 12:52:17 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 217764 kb
Host smart-93df466c-37ed-4d7e-9fcf-059edf480180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393010507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3393010507
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3904188826
Short name T13
Test name
Test status
Simulation time 116650895 ps
CPU time 0.79 seconds
Started Feb 18 12:52:16 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 200288 kb
Host smart-0b8eec98-6d3d-405b-8dc9-8a2e8ea982aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904188826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3904188826
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3426710661
Short name T518
Test name
Test status
Simulation time 1558450255 ps
CPU time 6.06 seconds
Started Feb 18 12:52:14 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200744 kb
Host smart-1101b813-6808-4c1f-b807-14dddeae4e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426710661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3426710661
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3754563905
Short name T262
Test name
Test status
Simulation time 103815613 ps
CPU time 0.95 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 200536 kb
Host smart-357dcdde-8e06-4a54-8eef-05f3f55d91f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754563905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3754563905
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3862888232
Short name T140
Test name
Test status
Simulation time 245949518 ps
CPU time 1.38 seconds
Started Feb 18 12:52:16 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 200716 kb
Host smart-7dbb4679-5cac-459b-b99d-d62a4d0396e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862888232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3862888232
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.4028121785
Short name T431
Test name
Test status
Simulation time 12609881836 ps
CPU time 43.67 seconds
Started Feb 18 12:52:24 PM PST 24
Finished Feb 18 12:53:10 PM PST 24
Peak memory 200908 kb
Host smart-e332c59d-33a2-410b-9428-b97190d722ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028121785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.4028121785
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1542701428
Short name T320
Test name
Test status
Simulation time 83069110 ps
CPU time 0.89 seconds
Started Feb 18 12:52:17 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 200508 kb
Host smart-9b008e6c-e7de-433b-ac99-9a6182d8c8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542701428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1542701428
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1593111420
Short name T474
Test name
Test status
Simulation time 86863418 ps
CPU time 0.82 seconds
Started Feb 18 12:52:19 PM PST 24
Finished Feb 18 12:52:24 PM PST 24
Peak memory 200408 kb
Host smart-45f1b6b3-137f-434f-9da5-72d9de0daa84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593111420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1593111420
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2931366562
Short name T31
Test name
Test status
Simulation time 1870249582 ps
CPU time 7.99 seconds
Started Feb 18 12:52:16 PM PST 24
Finished Feb 18 12:52:29 PM PST 24
Peak memory 217396 kb
Host smart-58b3c444-58ae-4b28-a869-7bbe85aef037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931366562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2931366562
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.489835545
Short name T289
Test name
Test status
Simulation time 244857551 ps
CPU time 1.02 seconds
Started Feb 18 12:52:18 PM PST 24
Finished Feb 18 12:52:24 PM PST 24
Peak memory 217724 kb
Host smart-6d5e14e8-27d1-468b-8859-39aae23144e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489835545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.489835545
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.895270381
Short name T343
Test name
Test status
Simulation time 94072332 ps
CPU time 0.77 seconds
Started Feb 18 12:52:18 PM PST 24
Finished Feb 18 12:52:24 PM PST 24
Peak memory 200308 kb
Host smart-465816be-8390-4e82-b003-aaaf0dff8497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895270381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.895270381
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1129295866
Short name T387
Test name
Test status
Simulation time 1280835096 ps
CPU time 5.19 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200784 kb
Host smart-383211a8-31d6-4c7a-a725-bf02fc530a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129295866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1129295866
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3768119374
Short name T172
Test name
Test status
Simulation time 151414311 ps
CPU time 1.11 seconds
Started Feb 18 12:52:18 PM PST 24
Finished Feb 18 12:52:24 PM PST 24
Peak memory 200456 kb
Host smart-8d42f7f5-94a6-4834-bbe9-776aa8d9e76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768119374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3768119374
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.585330436
Short name T362
Test name
Test status
Simulation time 259154357 ps
CPU time 1.55 seconds
Started Feb 18 12:52:18 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 200684 kb
Host smart-5528f33e-e489-49ce-b5bd-8674c1cd26a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585330436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.585330436
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2151572713
Short name T69
Test name
Test status
Simulation time 1742160649 ps
CPU time 6.78 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:28 PM PST 24
Peak memory 200700 kb
Host smart-6e81e847-eb85-4d75-a851-71c22240d841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151572713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2151572713
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2265020474
Short name T458
Test name
Test status
Simulation time 262068343 ps
CPU time 1.82 seconds
Started Feb 18 12:52:26 PM PST 24
Finished Feb 18 12:52:30 PM PST 24
Peak memory 200532 kb
Host smart-0ca8c872-20cc-4024-a4e1-b5ff0a380441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265020474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2265020474
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4270708384
Short name T235
Test name
Test status
Simulation time 214620802 ps
CPU time 1.35 seconds
Started Feb 18 12:52:17 PM PST 24
Finished Feb 18 12:52:24 PM PST 24
Peak memory 200492 kb
Host smart-e80e736d-a5bf-446e-8272-8288e069a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270708384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4270708384
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1763431383
Short name T171
Test name
Test status
Simulation time 68654655 ps
CPU time 0.76 seconds
Started Feb 18 12:51:16 PM PST 24
Finished Feb 18 12:51:21 PM PST 24
Peak memory 200316 kb
Host smart-ea83f6bb-641c-483c-bfa7-8bf45818395f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763431383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1763431383
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3437819458
Short name T182
Test name
Test status
Simulation time 2368714703 ps
CPU time 8.61 seconds
Started Feb 18 12:51:09 PM PST 24
Finished Feb 18 12:51:20 PM PST 24
Peak memory 222640 kb
Host smart-1a1757ae-7c6f-42a1-be0c-c98b07f49221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437819458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3437819458
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3685636298
Short name T496
Test name
Test status
Simulation time 243996910 ps
CPU time 1.13 seconds
Started Feb 18 12:51:25 PM PST 24
Finished Feb 18 12:51:28 PM PST 24
Peak memory 217752 kb
Host smart-cbb64eeb-1aa1-44ca-8d10-fd01a0d28fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685636298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3685636298
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4056720140
Short name T16
Test name
Test status
Simulation time 151614470 ps
CPU time 0.82 seconds
Started Feb 18 12:51:16 PM PST 24
Finished Feb 18 12:51:21 PM PST 24
Peak memory 200168 kb
Host smart-b454b45c-eac7-48a3-8992-02527d819988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056720140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4056720140
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2908993628
Short name T441
Test name
Test status
Simulation time 1243581510 ps
CPU time 5.55 seconds
Started Feb 18 12:51:21 PM PST 24
Finished Feb 18 12:51:31 PM PST 24
Peak memory 200728 kb
Host smart-9bbc0a24-9a0a-4c44-a1cc-53599012f01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908993628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2908993628
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2256145947
Short name T86
Test name
Test status
Simulation time 8331101906 ps
CPU time 13.33 seconds
Started Feb 18 12:51:20 PM PST 24
Finished Feb 18 12:51:37 PM PST 24
Peak memory 217348 kb
Host smart-988aa6f2-1f7c-41ab-8733-94d843653e95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256145947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2256145947
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1048121009
Short name T241
Test name
Test status
Simulation time 189738680 ps
CPU time 1.21 seconds
Started Feb 18 12:51:16 PM PST 24
Finished Feb 18 12:51:22 PM PST 24
Peak memory 200512 kb
Host smart-e357d26e-8a6e-496f-8023-b5aaa9f24fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048121009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1048121009
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2872500992
Short name T318
Test name
Test status
Simulation time 261195272 ps
CPU time 1.51 seconds
Started Feb 18 12:51:14 PM PST 24
Finished Feb 18 12:51:20 PM PST 24
Peak memory 200600 kb
Host smart-79f548da-c57d-4dac-845a-8b861b3be72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872500992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2872500992
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1917152357
Short name T383
Test name
Test status
Simulation time 5086446701 ps
CPU time 17.5 seconds
Started Feb 18 12:51:14 PM PST 24
Finished Feb 18 12:51:35 PM PST 24
Peak memory 200780 kb
Host smart-a589c3ce-1f7b-495f-af89-2c9c93ab2b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917152357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1917152357
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3832287919
Short name T254
Test name
Test status
Simulation time 402987327 ps
CPU time 2.27 seconds
Started Feb 18 12:51:14 PM PST 24
Finished Feb 18 12:51:19 PM PST 24
Peak memory 200464 kb
Host smart-31f41765-f221-426c-a464-a5f88d82ec79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832287919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3832287919
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1712157803
Short name T494
Test name
Test status
Simulation time 158666359 ps
CPU time 1.32 seconds
Started Feb 18 12:51:13 PM PST 24
Finished Feb 18 12:51:18 PM PST 24
Peak memory 200688 kb
Host smart-57159d6c-f600-4c3c-8c3c-48ba2baecf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712157803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1712157803
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3394817203
Short name T202
Test name
Test status
Simulation time 76866324 ps
CPU time 0.85 seconds
Started Feb 18 12:52:28 PM PST 24
Finished Feb 18 12:52:31 PM PST 24
Peak memory 200416 kb
Host smart-8fa81aa8-f6b1-4fbd-af02-1c5cdbcc0774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394817203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3394817203
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2714659611
Short name T403
Test name
Test status
Simulation time 1224990207 ps
CPU time 5.82 seconds
Started Feb 18 12:52:26 PM PST 24
Finished Feb 18 12:52:34 PM PST 24
Peak memory 222532 kb
Host smart-abba1849-40e1-4b7e-aefa-656c768eda88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714659611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2714659611
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3149152997
Short name T478
Test name
Test status
Simulation time 244732883 ps
CPU time 1.06 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 217728 kb
Host smart-506cfabd-9c13-481e-bf63-b2be01128292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149152997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3149152997
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1226739017
Short name T14
Test name
Test status
Simulation time 107524407 ps
CPU time 0.75 seconds
Started Feb 18 12:52:16 PM PST 24
Finished Feb 18 12:52:23 PM PST 24
Peak memory 200312 kb
Host smart-be021cd8-b47d-42cf-9ecb-b43e23e183db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226739017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1226739017
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.687143688
Short name T136
Test name
Test status
Simulation time 1739663438 ps
CPU time 7.44 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:32 PM PST 24
Peak memory 200720 kb
Host smart-067ffa20-b4f8-438e-88c7-8060f1cca4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687143688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.687143688
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3174482082
Short name T267
Test name
Test status
Simulation time 103653002 ps
CPU time 0.96 seconds
Started Feb 18 12:52:35 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 200520 kb
Host smart-d0634d7f-fed7-4a8e-99ec-172d4a8406ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174482082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3174482082
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3268757115
Short name T215
Test name
Test status
Simulation time 118073323 ps
CPU time 1.19 seconds
Started Feb 18 12:52:15 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 200736 kb
Host smart-ac99e0d4-563b-4f2a-8f4b-f23835fbafd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268757115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3268757115
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3238723183
Short name T243
Test name
Test status
Simulation time 4580117597 ps
CPU time 19.09 seconds
Started Feb 18 12:52:34 PM PST 24
Finished Feb 18 12:52:55 PM PST 24
Peak memory 200864 kb
Host smart-73519068-9122-4a25-902e-960f43f23af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238723183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3238723183
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1385374377
Short name T334
Test name
Test status
Simulation time 269665124 ps
CPU time 2.03 seconds
Started Feb 18 12:52:23 PM PST 24
Finished Feb 18 12:52:27 PM PST 24
Peak memory 200464 kb
Host smart-40cc2e26-fca0-4d1e-8593-ef4f0ec292c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385374377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1385374377
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.308727936
Short name T40
Test name
Test status
Simulation time 78774251 ps
CPU time 0.78 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 200500 kb
Host smart-b0458910-05b6-457c-85d6-6c3cd73e847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308727936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.308727936
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3361431993
Short name T162
Test name
Test status
Simulation time 68787722 ps
CPU time 0.74 seconds
Started Feb 18 12:52:35 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 200408 kb
Host smart-20a6efd5-0a39-4962-88e7-a5065621cdca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361431993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3361431993
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3194441653
Short name T400
Test name
Test status
Simulation time 1892788406 ps
CPU time 7.08 seconds
Started Feb 18 12:52:21 PM PST 24
Finished Feb 18 12:52:32 PM PST 24
Peak memory 217796 kb
Host smart-dc37c1bb-afea-4341-9619-1c2562ddb711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194441653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3194441653
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.665928148
Short name T213
Test name
Test status
Simulation time 243994022 ps
CPU time 1.16 seconds
Started Feb 18 12:52:34 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 217744 kb
Host smart-a79345de-4f17-4026-af8d-c5ca8afaa957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665928148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.665928148
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2536279241
Short name T279
Test name
Test status
Simulation time 188450329 ps
CPU time 0.87 seconds
Started Feb 18 12:52:35 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 200308 kb
Host smart-e243d61e-8629-4b13-b12b-5391d03683b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536279241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2536279241
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.615874795
Short name T394
Test name
Test status
Simulation time 877948638 ps
CPU time 4.79 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:29 PM PST 24
Peak memory 200668 kb
Host smart-dea62641-efbd-47c5-84fb-c8e7563654b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615874795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.615874795
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1117208674
Short name T65
Test name
Test status
Simulation time 195991370 ps
CPU time 1.15 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:25 PM PST 24
Peak memory 200508 kb
Host smart-93541600-9b70-46c9-a67b-2fac6ef4ba3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117208674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1117208674
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2857293534
Short name T404
Test name
Test status
Simulation time 116734453 ps
CPU time 1.09 seconds
Started Feb 18 12:52:22 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200628 kb
Host smart-3f204b4e-b2aa-4f6c-8577-19134371cfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857293534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2857293534
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3334667124
Short name T421
Test name
Test status
Simulation time 13288385292 ps
CPU time 46.32 seconds
Started Feb 18 12:52:23 PM PST 24
Finished Feb 18 12:53:12 PM PST 24
Peak memory 200904 kb
Host smart-ee6b6060-37c8-45c1-aeab-013a522776d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334667124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3334667124
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3978054151
Short name T150
Test name
Test status
Simulation time 297283762 ps
CPU time 2.19 seconds
Started Feb 18 12:52:26 PM PST 24
Finished Feb 18 12:52:31 PM PST 24
Peak memory 200532 kb
Host smart-3862d10f-d47f-40d6-8ae5-98ae0510f477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978054151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3978054151
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3933191596
Short name T436
Test name
Test status
Simulation time 137609456 ps
CPU time 1.12 seconds
Started Feb 18 12:52:34 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 200288 kb
Host smart-64928428-e3ab-4f85-90f3-edadf67958b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933191596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3933191596
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3541757901
Short name T175
Test name
Test status
Simulation time 70999534 ps
CPU time 0.76 seconds
Started Feb 18 12:52:23 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200384 kb
Host smart-dd87e07c-f67b-484f-8951-d23c06e23dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541757901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3541757901
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.4087437132
Short name T250
Test name
Test status
Simulation time 244166318 ps
CPU time 1.08 seconds
Started Feb 18 12:52:34 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 217860 kb
Host smart-5b7cefaa-067b-4230-8bc8-f04fd19a3e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087437132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.4087437132
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3626513213
Short name T251
Test name
Test status
Simulation time 227656874 ps
CPU time 0.89 seconds
Started Feb 18 12:52:35 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 200308 kb
Host smart-ec501cb3-4bf1-44d6-87b1-380aa32c4033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626513213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3626513213
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.4242522890
Short name T390
Test name
Test status
Simulation time 1766121775 ps
CPU time 6.51 seconds
Started Feb 18 12:52:30 PM PST 24
Finished Feb 18 12:52:40 PM PST 24
Peak memory 200768 kb
Host smart-ed064b35-b577-4871-b6d9-5a9084252385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242522890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.4242522890
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1406034920
Short name T385
Test name
Test status
Simulation time 151122721 ps
CPU time 1.36 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:31 PM PST 24
Peak memory 200512 kb
Host smart-a6d76716-169b-49ea-9d99-137ad66b056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406034920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1406034920
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.46553718
Short name T11
Test name
Test status
Simulation time 117068508 ps
CPU time 1.19 seconds
Started Feb 18 12:52:35 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 200652 kb
Host smart-383079a7-a9e5-45df-987a-c0caf83645d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46553718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.46553718
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1961386998
Short name T138
Test name
Test status
Simulation time 14698972436 ps
CPU time 52.74 seconds
Started Feb 18 12:52:34 PM PST 24
Finished Feb 18 12:53:29 PM PST 24
Peak memory 200684 kb
Host smart-06cd42e4-7459-464c-ac13-95f874c31fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961386998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1961386998
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2516448771
Short name T507
Test name
Test status
Simulation time 309815154 ps
CPU time 2.11 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200492 kb
Host smart-d4cacacc-b191-4f90-b3c8-16e16e838251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516448771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2516448771
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3530606653
Short name T315
Test name
Test status
Simulation time 95330675 ps
CPU time 0.96 seconds
Started Feb 18 12:52:30 PM PST 24
Finished Feb 18 12:52:34 PM PST 24
Peak memory 200552 kb
Host smart-7c557289-92c0-48f9-8aa3-843db7ce0cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530606653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3530606653
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.514370070
Short name T183
Test name
Test status
Simulation time 73957455 ps
CPU time 0.82 seconds
Started Feb 18 12:52:21 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200424 kb
Host smart-735d4caa-d2c4-4df6-ab6d-4388b6118526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514370070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.514370070
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3456497752
Short name T377
Test name
Test status
Simulation time 2183932429 ps
CPU time 8.45 seconds
Started Feb 18 12:52:22 PM PST 24
Finished Feb 18 12:52:33 PM PST 24
Peak memory 218500 kb
Host smart-74b246f1-07c6-4634-a668-5c0ee2c38c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456497752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3456497752
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2174784918
Short name T201
Test name
Test status
Simulation time 243833840 ps
CPU time 1.04 seconds
Started Feb 18 12:52:35 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 217824 kb
Host smart-1216081e-5371-445a-a3f2-ab4670e29d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174784918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2174784918
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1073035340
Short name T287
Test name
Test status
Simulation time 208790218 ps
CPU time 0.86 seconds
Started Feb 18 12:52:22 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200240 kb
Host smart-fb3a95eb-d732-4fcd-ad6a-1f32c4b5bdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073035340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1073035340
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.997767726
Short name T313
Test name
Test status
Simulation time 862543072 ps
CPU time 4.71 seconds
Started Feb 18 12:52:34 PM PST 24
Finished Feb 18 12:52:41 PM PST 24
Peak memory 200780 kb
Host smart-4eae3ea2-6577-471a-b6b8-cd24d47d3992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997767726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.997767726
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3206698156
Short name T479
Test name
Test status
Simulation time 174861022 ps
CPU time 1.14 seconds
Started Feb 18 12:52:20 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200512 kb
Host smart-8e3bf209-c00a-4e05-9bb0-28f358ff46f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206698156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3206698156
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3488445019
Short name T173
Test name
Test status
Simulation time 197831196 ps
CPU time 1.42 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:31 PM PST 24
Peak memory 200664 kb
Host smart-f0ec1470-0dd7-448d-983c-bb04f62a88ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488445019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3488445019
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3783571782
Short name T459
Test name
Test status
Simulation time 8764401948 ps
CPU time 30.48 seconds
Started Feb 18 12:52:21 PM PST 24
Finished Feb 18 12:52:55 PM PST 24
Peak memory 200900 kb
Host smart-c602f199-c2de-4d50-9832-143ce4444b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783571782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3783571782
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1408909750
Short name T74
Test name
Test status
Simulation time 123746716 ps
CPU time 1.47 seconds
Started Feb 18 12:52:34 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 200492 kb
Host smart-b2bfdcf3-daa7-4538-b4c4-0a7e33108233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408909750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1408909750
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3711844877
Short name T189
Test name
Test status
Simulation time 171109940 ps
CPU time 1.26 seconds
Started Feb 18 12:52:28 PM PST 24
Finished Feb 18 12:52:32 PM PST 24
Peak memory 200752 kb
Host smart-6d7f062c-50bc-4f9f-a8be-1d0462f89e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711844877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3711844877
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3136386319
Short name T247
Test name
Test status
Simulation time 64328069 ps
CPU time 0.73 seconds
Started Feb 18 12:52:29 PM PST 24
Finished Feb 18 12:52:34 PM PST 24
Peak memory 200416 kb
Host smart-2f0a5fb8-30a3-42c6-9ba4-89ba8467aeff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136386319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3136386319
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4006500004
Short name T371
Test name
Test status
Simulation time 243497427 ps
CPU time 1.08 seconds
Started Feb 18 12:52:28 PM PST 24
Finished Feb 18 12:52:33 PM PST 24
Peak memory 217756 kb
Host smart-16b30351-82e1-4dcd-8c13-c0f1219970fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006500004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4006500004
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2176765916
Short name T536
Test name
Test status
Simulation time 209565893 ps
CPU time 0.87 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:30 PM PST 24
Peak memory 200288 kb
Host smart-f6dd0fb7-c84f-4883-af43-5b17914f8b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176765916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2176765916
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1352330917
Short name T135
Test name
Test status
Simulation time 1670923612 ps
CPU time 6.3 seconds
Started Feb 18 12:52:35 PM PST 24
Finished Feb 18 12:52:44 PM PST 24
Peak memory 200748 kb
Host smart-22906b20-dc21-4da4-bd63-5596c354014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352330917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1352330917
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3012705286
Short name T453
Test name
Test status
Simulation time 183705143 ps
CPU time 1.16 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:30 PM PST 24
Peak memory 200440 kb
Host smart-e366d00e-94f3-46f2-adf8-b143c0d3f032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012705286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3012705286
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.4104325296
Short name T426
Test name
Test status
Simulation time 116272636 ps
CPU time 1.19 seconds
Started Feb 18 12:52:23 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200632 kb
Host smart-3fb18303-d96b-48e9-98db-88b3c93114a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104325296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.4104325296
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2696095574
Short name T376
Test name
Test status
Simulation time 1414342959 ps
CPU time 7.1 seconds
Started Feb 18 12:52:28 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 200660 kb
Host smart-99e01ab7-4a24-4ebe-98fb-f95cc3fd6995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696095574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2696095574
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.523586091
Short name T192
Test name
Test status
Simulation time 143994895 ps
CPU time 1.77 seconds
Started Feb 18 12:52:30 PM PST 24
Finished Feb 18 12:52:35 PM PST 24
Peak memory 200504 kb
Host smart-f8b901c9-4bc1-442d-99c0-fb7cfcb871d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523586091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.523586091
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2838657963
Short name T391
Test name
Test status
Simulation time 247572547 ps
CPU time 1.3 seconds
Started Feb 18 12:52:22 PM PST 24
Finished Feb 18 12:52:26 PM PST 24
Peak memory 200520 kb
Host smart-ca15b946-e9c2-41f4-9c3f-5ab417b84100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838657963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2838657963
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1448278406
Short name T283
Test name
Test status
Simulation time 68942556 ps
CPU time 0.75 seconds
Started Feb 18 12:52:33 PM PST 24
Finished Feb 18 12:52:36 PM PST 24
Peak memory 200412 kb
Host smart-35002a54-e13d-480e-96bf-416f270084be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448278406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1448278406
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2547023764
Short name T34
Test name
Test status
Simulation time 2366091191 ps
CPU time 8.1 seconds
Started Feb 18 12:52:28 PM PST 24
Finished Feb 18 12:52:40 PM PST 24
Peak memory 222336 kb
Host smart-ef219d4c-0969-4c38-a7f3-183d2bf8901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547023764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2547023764
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2709700722
Short name T5
Test name
Test status
Simulation time 243496452 ps
CPU time 1.07 seconds
Started Feb 18 12:52:29 PM PST 24
Finished Feb 18 12:52:34 PM PST 24
Peak memory 217868 kb
Host smart-a7aacf66-af9d-4ed5-97a3-0c5b5e37748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709700722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2709700722
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2612384837
Short name T301
Test name
Test status
Simulation time 144194742 ps
CPU time 0.81 seconds
Started Feb 18 12:52:29 PM PST 24
Finished Feb 18 12:52:34 PM PST 24
Peak memory 200316 kb
Host smart-8e1c74a4-01fd-45ce-b6b3-c9ee11fc094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612384837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2612384837
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1423614462
Short name T271
Test name
Test status
Simulation time 1201494114 ps
CPU time 5.23 seconds
Started Feb 18 12:52:31 PM PST 24
Finished Feb 18 12:52:39 PM PST 24
Peak memory 200748 kb
Host smart-f4fc3a4a-c168-4d3c-9c85-743e3be5c659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423614462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1423614462
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3084881554
Short name T198
Test name
Test status
Simulation time 176159448 ps
CPU time 1.24 seconds
Started Feb 18 12:52:28 PM PST 24
Finished Feb 18 12:52:33 PM PST 24
Peak memory 200528 kb
Host smart-942badf2-f006-4324-83e7-d39751fdf5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084881554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3084881554
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2203580290
Short name T442
Test name
Test status
Simulation time 265788305 ps
CPU time 1.59 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:32 PM PST 24
Peak memory 200628 kb
Host smart-9d8fb1d6-975b-40c4-875d-c8f925d69d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203580290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2203580290
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.826359713
Short name T264
Test name
Test status
Simulation time 4997575503 ps
CPU time 22.49 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:53 PM PST 24
Peak memory 200876 kb
Host smart-33463380-9bc3-4dd7-b5fc-78fcb43ab196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826359713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.826359713
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1474901483
Short name T356
Test name
Test status
Simulation time 543201786 ps
CPU time 2.87 seconds
Started Feb 18 12:52:29 PM PST 24
Finished Feb 18 12:52:35 PM PST 24
Peak memory 200520 kb
Host smart-5aa855af-99a5-4bed-9174-f6207b244ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474901483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1474901483
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2172317317
Short name T414
Test name
Test status
Simulation time 102194701 ps
CPU time 0.96 seconds
Started Feb 18 12:52:29 PM PST 24
Finished Feb 18 12:52:34 PM PST 24
Peak memory 200500 kb
Host smart-38d00c2d-6a91-4886-a2d6-08a64364e1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172317317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2172317317
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3654439898
Short name T509
Test name
Test status
Simulation time 76988179 ps
CPU time 0.78 seconds
Started Feb 18 12:52:46 PM PST 24
Finished Feb 18 12:52:51 PM PST 24
Peak memory 200412 kb
Host smart-d7102d57-2dd4-4ab5-8425-afc0bbb7ed92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654439898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3654439898
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4092235908
Short name T504
Test name
Test status
Simulation time 1221832005 ps
CPU time 5.95 seconds
Started Feb 18 12:52:30 PM PST 24
Finished Feb 18 12:52:39 PM PST 24
Peak memory 218468 kb
Host smart-6a9bb851-6197-4824-994c-e5acb54956cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092235908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4092235908
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1239247236
Short name T433
Test name
Test status
Simulation time 244624806 ps
CPU time 1.04 seconds
Started Feb 18 12:52:27 PM PST 24
Finished Feb 18 12:52:30 PM PST 24
Peak memory 217856 kb
Host smart-d92a3240-4e00-4f71-8ee8-a13b90989f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239247236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1239247236
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3586520889
Short name T480
Test name
Test status
Simulation time 228236780 ps
CPU time 0.94 seconds
Started Feb 18 12:52:33 PM PST 24
Finished Feb 18 12:52:35 PM PST 24
Peak memory 200324 kb
Host smart-9c66a857-9fcf-443a-9072-1f6bba8c2c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586520889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3586520889
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2547505369
Short name T340
Test name
Test status
Simulation time 1771637040 ps
CPU time 7.54 seconds
Started Feb 18 12:52:28 PM PST 24
Finished Feb 18 12:52:40 PM PST 24
Peak memory 200744 kb
Host smart-36535c05-ac33-41c3-a4bd-5777e0a18e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547505369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2547505369
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.78485947
Short name T425
Test name
Test status
Simulation time 141942433 ps
CPU time 1.14 seconds
Started Feb 18 12:52:30 PM PST 24
Finished Feb 18 12:52:35 PM PST 24
Peak memory 200504 kb
Host smart-196a8338-403d-4d91-9462-185166a4414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78485947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.78485947
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.101922744
Short name T259
Test name
Test status
Simulation time 117652444 ps
CPU time 1.19 seconds
Started Feb 18 12:52:28 PM PST 24
Finished Feb 18 12:52:33 PM PST 24
Peak memory 200712 kb
Host smart-7aae8a2b-1a09-466e-9f40-090711da565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101922744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.101922744
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.644659033
Short name T312
Test name
Test status
Simulation time 427491351 ps
CPU time 2.45 seconds
Started Feb 18 12:52:30 PM PST 24
Finished Feb 18 12:52:36 PM PST 24
Peak memory 200660 kb
Host smart-1d552c53-f468-465f-974d-ecb6f1b5a0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644659033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.644659033
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3645862634
Short name T499
Test name
Test status
Simulation time 462661554 ps
CPU time 2.53 seconds
Started Feb 18 12:52:31 PM PST 24
Finished Feb 18 12:52:36 PM PST 24
Peak memory 200524 kb
Host smart-97d39b07-97c0-4333-8738-be6c1ea1b8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645862634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3645862634
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2371052642
Short name T261
Test name
Test status
Simulation time 151619855 ps
CPU time 1.25 seconds
Started Feb 18 12:52:30 PM PST 24
Finished Feb 18 12:52:34 PM PST 24
Peak memory 200504 kb
Host smart-2110b010-f8d6-4e96-9c8a-d1cee3024969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371052642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2371052642
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.797307309
Short name T316
Test name
Test status
Simulation time 82204000 ps
CPU time 0.8 seconds
Started Feb 18 12:52:43 PM PST 24
Finished Feb 18 12:52:46 PM PST 24
Peak memory 200404 kb
Host smart-db85438c-bcf9-42f8-b539-6ed5eb054cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797307309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.797307309
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.284414849
Short name T66
Test name
Test status
Simulation time 2342498846 ps
CPU time 9.55 seconds
Started Feb 18 12:52:41 PM PST 24
Finished Feb 18 12:52:53 PM PST 24
Peak memory 221792 kb
Host smart-8ec5aa20-b347-413a-a8c5-a137d576dbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284414849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.284414849
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.730592547
Short name T252
Test name
Test status
Simulation time 244276671 ps
CPU time 1.16 seconds
Started Feb 18 12:52:42 PM PST 24
Finished Feb 18 12:52:46 PM PST 24
Peak memory 217888 kb
Host smart-c350da0c-c0f2-4a9b-92e1-eec5552a53a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730592547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.730592547
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3142087362
Short name T293
Test name
Test status
Simulation time 104786925 ps
CPU time 0.82 seconds
Started Feb 18 12:52:44 PM PST 24
Finished Feb 18 12:52:49 PM PST 24
Peak memory 200300 kb
Host smart-b786ee7c-276f-4649-b98b-889e8132e6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142087362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3142087362
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2375373960
Short name T238
Test name
Test status
Simulation time 1278668523 ps
CPU time 5.36 seconds
Started Feb 18 12:52:41 PM PST 24
Finished Feb 18 12:52:48 PM PST 24
Peak memory 200800 kb
Host smart-8fd1213d-f81b-49fb-8bbd-a11aa59865af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375373960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2375373960
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1190059899
Short name T321
Test name
Test status
Simulation time 97940835 ps
CPU time 1.04 seconds
Started Feb 18 12:52:41 PM PST 24
Finished Feb 18 12:52:43 PM PST 24
Peak memory 200536 kb
Host smart-b9a350c1-a083-4ead-bd1f-7051d5993903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190059899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1190059899
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2097961332
Short name T314
Test name
Test status
Simulation time 114790511 ps
CPU time 1.14 seconds
Started Feb 18 12:52:40 PM PST 24
Finished Feb 18 12:52:43 PM PST 24
Peak memory 200692 kb
Host smart-ebde805d-9152-418f-a0e4-99945bade779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097961332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2097961332
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3167437210
Short name T490
Test name
Test status
Simulation time 2407259834 ps
CPU time 10.94 seconds
Started Feb 18 12:52:41 PM PST 24
Finished Feb 18 12:52:53 PM PST 24
Peak memory 200904 kb
Host smart-dfcef21e-4b0a-41a4-9cb7-517e7e93d757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167437210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3167437210
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3210383412
Short name T434
Test name
Test status
Simulation time 139279951 ps
CPU time 1.88 seconds
Started Feb 18 12:52:41 PM PST 24
Finished Feb 18 12:52:44 PM PST 24
Peak memory 200500 kb
Host smart-12703639-b025-4e07-a3d8-4dd646adab51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210383412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3210383412
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3556117930
Short name T246
Test name
Test status
Simulation time 165899403 ps
CPU time 1.21 seconds
Started Feb 18 12:52:43 PM PST 24
Finished Feb 18 12:52:46 PM PST 24
Peak memory 200560 kb
Host smart-d70e4585-ce72-4395-a554-b661a627b215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556117930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3556117930
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.326528268
Short name T482
Test name
Test status
Simulation time 89319163 ps
CPU time 0.92 seconds
Started Feb 18 12:52:44 PM PST 24
Finished Feb 18 12:52:49 PM PST 24
Peak memory 200404 kb
Host smart-6e8a2345-caec-4a59-acae-7d0f87e6b836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326528268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.326528268
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2635801216
Short name T53
Test name
Test status
Simulation time 1895960381 ps
CPU time 7.41 seconds
Started Feb 18 12:52:39 PM PST 24
Finished Feb 18 12:52:47 PM PST 24
Peak memory 221780 kb
Host smart-71b4faa5-aafe-4085-b504-4f53348c7824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635801216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2635801216
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1030349255
Short name T26
Test name
Test status
Simulation time 245166271 ps
CPU time 1.11 seconds
Started Feb 18 12:52:51 PM PST 24
Finished Feb 18 12:52:58 PM PST 24
Peak memory 217852 kb
Host smart-559d8615-3577-4b86-a7b8-6f685af0dd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030349255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1030349255
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1171784715
Short name T319
Test name
Test status
Simulation time 140446677 ps
CPU time 0.79 seconds
Started Feb 18 12:52:39 PM PST 24
Finished Feb 18 12:52:41 PM PST 24
Peak memory 200292 kb
Host smart-01f1839c-da32-4e4f-80f0-893899343521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171784715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1171784715
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2182043674
Short name T505
Test name
Test status
Simulation time 980753691 ps
CPU time 5.08 seconds
Started Feb 18 12:52:43 PM PST 24
Finished Feb 18 12:52:51 PM PST 24
Peak memory 200748 kb
Host smart-94457966-d63c-4144-a66e-a5fbadd7c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182043674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2182043674
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.814128233
Short name T476
Test name
Test status
Simulation time 104490872 ps
CPU time 0.99 seconds
Started Feb 18 12:52:44 PM PST 24
Finished Feb 18 12:52:49 PM PST 24
Peak memory 200512 kb
Host smart-02e0313c-2137-4132-a2c5-acb58e392854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814128233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.814128233
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.697751733
Short name T302
Test name
Test status
Simulation time 124115538 ps
CPU time 1.31 seconds
Started Feb 18 12:52:43 PM PST 24
Finished Feb 18 12:52:47 PM PST 24
Peak memory 200708 kb
Host smart-f5217e51-1174-461c-8ed9-302cade1c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697751733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.697751733
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2858563653
Short name T506
Test name
Test status
Simulation time 2257298301 ps
CPU time 11.07 seconds
Started Feb 18 12:52:45 PM PST 24
Finished Feb 18 12:53:00 PM PST 24
Peak memory 200868 kb
Host smart-455ac88e-d5bb-4bd1-af7d-dc227547e14d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858563653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2858563653
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1924587689
Short name T41
Test name
Test status
Simulation time 301958181 ps
CPU time 2.2 seconds
Started Feb 18 12:52:44 PM PST 24
Finished Feb 18 12:52:50 PM PST 24
Peak memory 200396 kb
Host smart-bf3e5e21-6227-4f8d-b94e-3bcc931d21fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924587689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1924587689
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1048554384
Short name T63
Test name
Test status
Simulation time 194456913 ps
CPU time 1.33 seconds
Started Feb 18 12:52:41 PM PST 24
Finished Feb 18 12:52:44 PM PST 24
Peak memory 200448 kb
Host smart-d636e3f2-686f-47d3-bdc4-12c3ecf487dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048554384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1048554384
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.572956548
Short name T23
Test name
Test status
Simulation time 69527627 ps
CPU time 0.76 seconds
Started Feb 18 12:52:44 PM PST 24
Finished Feb 18 12:52:49 PM PST 24
Peak memory 200340 kb
Host smart-61b6b908-0d5c-4c7b-810f-a3a7a055689c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572956548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.572956548
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2616141745
Short name T68
Test name
Test status
Simulation time 1882962667 ps
CPU time 7.9 seconds
Started Feb 18 12:52:44 PM PST 24
Finished Feb 18 12:52:56 PM PST 24
Peak memory 218020 kb
Host smart-c672cb5f-2a34-44e9-a765-d306d348bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616141745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2616141745
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2707680522
Short name T47
Test name
Test status
Simulation time 257076868 ps
CPU time 1.09 seconds
Started Feb 18 12:52:39 PM PST 24
Finished Feb 18 12:52:41 PM PST 24
Peak memory 217872 kb
Host smart-ba271a4c-db7a-4b26-9c71-ffd8cb3c6960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707680522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2707680522
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.515593807
Short name T487
Test name
Test status
Simulation time 150900740 ps
CPU time 0.86 seconds
Started Feb 18 12:52:41 PM PST 24
Finished Feb 18 12:52:43 PM PST 24
Peak memory 200332 kb
Host smart-853474c6-2bb2-4372-91a2-e05cc86f81d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515593807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.515593807
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.938925377
Short name T118
Test name
Test status
Simulation time 1876952524 ps
CPU time 6.7 seconds
Started Feb 18 12:52:43 PM PST 24
Finished Feb 18 12:52:53 PM PST 24
Peak memory 200688 kb
Host smart-a436e7ed-7908-45cd-aad2-4a045354bea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938925377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.938925377
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.4015717373
Short name T516
Test name
Test status
Simulation time 107358565 ps
CPU time 1.04 seconds
Started Feb 18 12:52:41 PM PST 24
Finished Feb 18 12:52:44 PM PST 24
Peak memory 200548 kb
Host smart-5e9fed84-d6cf-4e98-ab2d-1a234fa3cc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015717373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.4015717373
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1503538976
Short name T178
Test name
Test status
Simulation time 123285657 ps
CPU time 1.2 seconds
Started Feb 18 12:52:45 PM PST 24
Finished Feb 18 12:52:50 PM PST 24
Peak memory 200684 kb
Host smart-f7344680-bd22-42da-8868-d1b976815710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503538976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1503538976
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1823583264
Short name T108
Test name
Test status
Simulation time 1954745460 ps
CPU time 7.83 seconds
Started Feb 18 12:52:42 PM PST 24
Finished Feb 18 12:52:53 PM PST 24
Peak memory 200724 kb
Host smart-a1af66b4-e0d0-4c0c-be71-f9b7ca533ce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823583264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1823583264
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.733732058
Short name T454
Test name
Test status
Simulation time 355165167 ps
CPU time 2.44 seconds
Started Feb 18 12:52:44 PM PST 24
Finished Feb 18 12:52:50 PM PST 24
Peak memory 200496 kb
Host smart-6d2045c6-c0c8-43b4-b01c-090cd4362f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733732058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.733732058
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3517782128
Short name T24
Test name
Test status
Simulation time 231534602 ps
CPU time 1.36 seconds
Started Feb 18 12:52:44 PM PST 24
Finished Feb 18 12:52:50 PM PST 24
Peak memory 200492 kb
Host smart-c8819644-2a2d-4e46-8094-1bbd8e0b4f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517782128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3517782128
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2401704605
Short name T165
Test name
Test status
Simulation time 84067766 ps
CPU time 0.76 seconds
Started Feb 18 12:51:14 PM PST 24
Finished Feb 18 12:51:19 PM PST 24
Peak memory 200408 kb
Host smart-61309232-fdd5-4c5f-a0d9-1af6912c3fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401704605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2401704605
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3708251710
Short name T488
Test name
Test status
Simulation time 2343549844 ps
CPU time 9.31 seconds
Started Feb 18 12:51:16 PM PST 24
Finished Feb 18 12:51:29 PM PST 24
Peak memory 222256 kb
Host smart-24bad9c7-c731-4c58-a584-2ddebb79ec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708251710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3708251710
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.878933025
Short name T228
Test name
Test status
Simulation time 244825899 ps
CPU time 1.11 seconds
Started Feb 18 12:51:21 PM PST 24
Finished Feb 18 12:51:27 PM PST 24
Peak memory 217516 kb
Host smart-3e3c2943-1b08-466a-a2b4-5f3b2ab07532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878933025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.878933025
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3352376891
Short name T275
Test name
Test status
Simulation time 209610609 ps
CPU time 0.94 seconds
Started Feb 18 12:51:16 PM PST 24
Finished Feb 18 12:51:21 PM PST 24
Peak memory 200216 kb
Host smart-c3415559-eed0-4a4b-8a50-aa0e18acf11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352376891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3352376891
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2942648663
Short name T447
Test name
Test status
Simulation time 1356576295 ps
CPU time 5.14 seconds
Started Feb 18 12:51:12 PM PST 24
Finished Feb 18 12:51:20 PM PST 24
Peak memory 199732 kb
Host smart-e81fd4a1-c605-40c6-ac01-e914bae4f0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942648663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2942648663
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4046213330
Short name T309
Test name
Test status
Simulation time 106406529 ps
CPU time 1.03 seconds
Started Feb 18 12:51:21 PM PST 24
Finished Feb 18 12:51:27 PM PST 24
Peak memory 200404 kb
Host smart-3e1a7f5c-b536-49a0-8242-b948c513ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046213330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4046213330
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2331728408
Short name T224
Test name
Test status
Simulation time 117151109 ps
CPU time 1.17 seconds
Started Feb 18 12:51:13 PM PST 24
Finished Feb 18 12:51:17 PM PST 24
Peak memory 200640 kb
Host smart-c583d90c-e2da-4136-98ef-91aa022afecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331728408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2331728408
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3153548993
Short name T445
Test name
Test status
Simulation time 1236701840 ps
CPU time 6.56 seconds
Started Feb 18 12:51:25 PM PST 24
Finished Feb 18 12:51:34 PM PST 24
Peak memory 200796 kb
Host smart-0075f984-d770-436d-b695-dece019c00f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153548993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3153548993
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3704423070
Short name T42
Test name
Test status
Simulation time 145485241 ps
CPU time 1.97 seconds
Started Feb 18 12:51:16 PM PST 24
Finished Feb 18 12:51:22 PM PST 24
Peak memory 200516 kb
Host smart-e577dd54-0da6-4366-864c-2e79a33f67dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704423070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3704423070
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3377627017
Short name T326
Test name
Test status
Simulation time 89073751 ps
CPU time 0.81 seconds
Started Feb 18 12:51:20 PM PST 24
Finished Feb 18 12:51:25 PM PST 24
Peak memory 200396 kb
Host smart-a74adfe6-84d3-493f-86aa-649c48a6356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377627017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3377627017
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2341990341
Short name T25
Test name
Test status
Simulation time 67079578 ps
CPU time 0.7 seconds
Started Feb 18 12:51:25 PM PST 24
Finished Feb 18 12:51:28 PM PST 24
Peak memory 200424 kb
Host smart-0ac4c37b-1665-40da-b621-92927dae6853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341990341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2341990341
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1641210889
Short name T59
Test name
Test status
Simulation time 1223832990 ps
CPU time 6.42 seconds
Started Feb 18 12:51:22 PM PST 24
Finished Feb 18 12:51:32 PM PST 24
Peak memory 218016 kb
Host smart-6bb2ecbc-3993-49da-80f0-5a8f3fd2b919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641210889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1641210889
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2992799854
Short name T396
Test name
Test status
Simulation time 247109846 ps
CPU time 1.02 seconds
Started Feb 18 12:51:21 PM PST 24
Finished Feb 18 12:51:26 PM PST 24
Peak memory 217848 kb
Host smart-d3b3959f-c3ca-4e06-9130-e67de089f4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992799854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2992799854
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2995504709
Short name T336
Test name
Test status
Simulation time 172284144 ps
CPU time 0.82 seconds
Started Feb 18 12:51:20 PM PST 24
Finished Feb 18 12:51:25 PM PST 24
Peak memory 200204 kb
Host smart-f9d99188-add4-4edb-ba9d-f2e5fcefc249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995504709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2995504709
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1091317293
Short name T450
Test name
Test status
Simulation time 1427287350 ps
CPU time 5.85 seconds
Started Feb 18 12:51:10 PM PST 24
Finished Feb 18 12:51:17 PM PST 24
Peak memory 200752 kb
Host smart-2f2617e4-2032-4411-804f-34982d19d5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091317293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1091317293
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1445038288
Short name T97
Test name
Test status
Simulation time 101532023 ps
CPU time 0.96 seconds
Started Feb 18 12:51:20 PM PST 24
Finished Feb 18 12:51:25 PM PST 24
Peak memory 200528 kb
Host smart-92c40d7f-0998-4817-86eb-48a979f2bc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445038288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1445038288
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1624249621
Short name T284
Test name
Test status
Simulation time 113368651 ps
CPU time 1.08 seconds
Started Feb 18 12:51:12 PM PST 24
Finished Feb 18 12:51:14 PM PST 24
Peak memory 200600 kb
Host smart-40d60fb3-cce7-4ea9-b2da-b7993a23a797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624249621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1624249621
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3429918756
Short name T2
Test name
Test status
Simulation time 3607854242 ps
CPU time 16.09 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:38 PM PST 24
Peak memory 200892 kb
Host smart-086ccd43-ebd9-4564-8b8a-bcef110f7e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429918756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3429918756
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1185499380
Short name T299
Test name
Test status
Simulation time 370786201 ps
CPU time 2.39 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:24 PM PST 24
Peak memory 200492 kb
Host smart-47b157c8-a06c-463c-abba-2e6a60956a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185499380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1185499380
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3502378413
Short name T370
Test name
Test status
Simulation time 84565307 ps
CPU time 0.78 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 200412 kb
Host smart-abcaf72f-91c9-4df6-a39a-9c93fdd6af04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502378413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3502378413
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2530670983
Short name T493
Test name
Test status
Simulation time 68238805 ps
CPU time 0.77 seconds
Started Feb 18 12:51:18 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 200324 kb
Host smart-0a494712-87d8-4085-9286-fd36e303eabd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530670983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2530670983
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1004604902
Short name T36
Test name
Test status
Simulation time 1882372391 ps
CPU time 7.47 seconds
Started Feb 18 12:51:27 PM PST 24
Finished Feb 18 12:51:36 PM PST 24
Peak memory 222036 kb
Host smart-69999d57-c660-4234-9ae0-b38a3fc2e5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004604902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1004604902
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2231502061
Short name T375
Test name
Test status
Simulation time 244120654 ps
CPU time 1.13 seconds
Started Feb 18 12:51:22 PM PST 24
Finished Feb 18 12:51:27 PM PST 24
Peak memory 217724 kb
Host smart-42384768-816d-4d9a-bf37-3de642feb9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231502061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2231502061
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3827166193
Short name T300
Test name
Test status
Simulation time 130149148 ps
CPU time 0.78 seconds
Started Feb 18 12:51:22 PM PST 24
Finished Feb 18 12:51:27 PM PST 24
Peak memory 200300 kb
Host smart-2313fa66-cc02-431e-93f5-f0e7b3ca88b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827166193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3827166193
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2358406608
Short name T378
Test name
Test status
Simulation time 1720217902 ps
CPU time 6.74 seconds
Started Feb 18 12:51:22 PM PST 24
Finished Feb 18 12:51:33 PM PST 24
Peak memory 200768 kb
Host smart-5f298165-86b9-4119-9fd2-f7cace9d9f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358406608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2358406608
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.148071095
Short name T523
Test name
Test status
Simulation time 147239698 ps
CPU time 1.15 seconds
Started Feb 18 12:51:17 PM PST 24
Finished Feb 18 12:51:22 PM PST 24
Peak memory 200488 kb
Host smart-bf49b39e-2cbc-42a2-9a67-116b71fcd1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148071095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.148071095
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.164775571
Short name T244
Test name
Test status
Simulation time 113192147 ps
CPU time 1.17 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 200620 kb
Host smart-2b798a07-1644-4d02-9ad0-b2f1c4cad522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164775571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.164775571
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3251899599
Short name T510
Test name
Test status
Simulation time 304789377 ps
CPU time 1.66 seconds
Started Feb 18 12:51:22 PM PST 24
Finished Feb 18 12:51:28 PM PST 24
Peak memory 200500 kb
Host smart-447aaa15-222f-4d4d-ad57-3bfb82256c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251899599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3251899599
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3479437144
Short name T256
Test name
Test status
Simulation time 370984911 ps
CPU time 2.54 seconds
Started Feb 18 12:51:22 PM PST 24
Finished Feb 18 12:51:28 PM PST 24
Peak memory 200464 kb
Host smart-257e0889-221d-4ac6-b4e8-3843c9b652ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479437144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3479437144
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1518047715
Short name T311
Test name
Test status
Simulation time 202200566 ps
CPU time 1.28 seconds
Started Feb 18 12:51:20 PM PST 24
Finished Feb 18 12:51:25 PM PST 24
Peak memory 200500 kb
Host smart-66ee6685-9c2a-4fa2-8782-d9629fd1ea12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518047715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1518047715
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.862783200
Short name T457
Test name
Test status
Simulation time 78246501 ps
CPU time 0.85 seconds
Started Feb 18 12:51:27 PM PST 24
Finished Feb 18 12:51:30 PM PST 24
Peak memory 200420 kb
Host smart-b95fe380-7908-4887-be39-99400cb267fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862783200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.862783200
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.553142266
Short name T395
Test name
Test status
Simulation time 2350917305 ps
CPU time 8.53 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:32 PM PST 24
Peak memory 217768 kb
Host smart-0c5003fd-6e96-46cb-afa6-483c570ae221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553142266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.553142266
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1866059576
Short name T324
Test name
Test status
Simulation time 244445286 ps
CPU time 1.06 seconds
Started Feb 18 12:51:20 PM PST 24
Finished Feb 18 12:51:25 PM PST 24
Peak memory 217848 kb
Host smart-59e32f6c-9ed4-4af2-b78f-c6c5648f532f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866059576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1866059576
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.858018371
Short name T418
Test name
Test status
Simulation time 160864248 ps
CPU time 0.84 seconds
Started Feb 18 12:51:21 PM PST 24
Finished Feb 18 12:51:26 PM PST 24
Peak memory 200232 kb
Host smart-8557fc56-a2dc-4a30-a091-42f5156e4dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858018371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.858018371
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2161558916
Short name T405
Test name
Test status
Simulation time 1027918137 ps
CPU time 4.54 seconds
Started Feb 18 12:51:21 PM PST 24
Finished Feb 18 12:51:30 PM PST 24
Peak memory 200640 kb
Host smart-fe308f50-2323-416b-adee-47c6f5a57339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161558916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2161558916
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3910020705
Short name T239
Test name
Test status
Simulation time 175916414 ps
CPU time 1.19 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:24 PM PST 24
Peak memory 200520 kb
Host smart-0214db83-eb8e-426d-8259-4fdc7a9adeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910020705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3910020705
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2529457067
Short name T176
Test name
Test status
Simulation time 122780070 ps
CPU time 1.23 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 200684 kb
Host smart-d2da142f-7de9-43ed-8425-725b7a14f157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529457067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2529457067
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2496933729
Short name T515
Test name
Test status
Simulation time 1320075076 ps
CPU time 6.81 seconds
Started Feb 18 12:51:23 PM PST 24
Finished Feb 18 12:51:33 PM PST 24
Peak memory 200644 kb
Host smart-06ff65e6-6f73-4c06-9279-5663b609760c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496933729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2496933729
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.847978085
Short name T99
Test name
Test status
Simulation time 147815944 ps
CPU time 1.77 seconds
Started Feb 18 12:51:19 PM PST 24
Finished Feb 18 12:51:24 PM PST 24
Peak memory 200572 kb
Host smart-e361854e-00c5-44f4-bc3e-868016754503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847978085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.847978085
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.4054406833
Short name T338
Test name
Test status
Simulation time 276117458 ps
CPU time 1.51 seconds
Started Feb 18 12:51:18 PM PST 24
Finished Feb 18 12:51:23 PM PST 24
Peak memory 200500 kb
Host smart-2d404814-0620-4bd9-9ee4-b2f2d66ebe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054406833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.4054406833
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.831034472
Short name T260
Test name
Test status
Simulation time 67116931 ps
CPU time 0.76 seconds
Started Feb 18 12:51:27 PM PST 24
Finished Feb 18 12:51:30 PM PST 24
Peak memory 200392 kb
Host smart-8a0dd725-846a-425b-b0ba-49ca040983ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831034472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.831034472
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.997918942
Short name T48
Test name
Test status
Simulation time 1236048762 ps
CPU time 6.01 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:37 PM PST 24
Peak memory 222456 kb
Host smart-d75b2601-1d24-4b2d-952f-502a2ea46e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997918942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.997918942
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2784820726
Short name T495
Test name
Test status
Simulation time 243667631 ps
CPU time 1.05 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:31 PM PST 24
Peak memory 217792 kb
Host smart-c404d169-4464-4276-8dc2-7ad2a7076ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784820726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2784820726
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.4022892007
Short name T180
Test name
Test status
Simulation time 167914646 ps
CPU time 0.86 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:32 PM PST 24
Peak memory 200360 kb
Host smart-2ac3df36-8553-4577-8b1d-71d47b95d92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022892007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4022892007
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3531084351
Short name T399
Test name
Test status
Simulation time 1251544490 ps
CPU time 5.13 seconds
Started Feb 18 12:51:25 PM PST 24
Finished Feb 18 12:51:33 PM PST 24
Peak memory 200672 kb
Host smart-27be51af-3f39-401c-9ba6-244e1ef33f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531084351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3531084351
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3221275754
Short name T154
Test name
Test status
Simulation time 98326826 ps
CPU time 0.94 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:31 PM PST 24
Peak memory 200488 kb
Host smart-89ba427a-6cee-41b6-ab9a-1038d8609b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221275754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3221275754
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2151022906
Short name T149
Test name
Test status
Simulation time 116150468 ps
CPU time 1.17 seconds
Started Feb 18 12:51:24 PM PST 24
Finished Feb 18 12:51:28 PM PST 24
Peak memory 200696 kb
Host smart-13322e37-911c-4ffc-bbfe-d7534a89c228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151022906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2151022906
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2729344774
Short name T116
Test name
Test status
Simulation time 3400261902 ps
CPU time 15.95 seconds
Started Feb 18 12:51:25 PM PST 24
Finished Feb 18 12:51:44 PM PST 24
Peak memory 200872 kb
Host smart-87a892c1-d990-40c2-9b52-b0f6879d588a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729344774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2729344774
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2963696894
Short name T451
Test name
Test status
Simulation time 386818167 ps
CPU time 2.77 seconds
Started Feb 18 12:51:30 PM PST 24
Finished Feb 18 12:51:34 PM PST 24
Peak memory 200492 kb
Host smart-e03aa816-2105-40c1-91b5-5b7c7a2dbc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963696894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2963696894
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1075377674
Short name T212
Test name
Test status
Simulation time 152106486 ps
CPU time 1.15 seconds
Started Feb 18 12:51:28 PM PST 24
Finished Feb 18 12:51:31 PM PST 24
Peak memory 200508 kb
Host smart-41b18e0b-faab-45cc-aa4a-64ab6cde4e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075377674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1075377674
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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