Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8206

1

T3

10

T6

13

T10

7

auto[1]

11302

1

T3

1

T4

4

T6

88

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5997	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6585	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3041	1			T4	1		T6	19		T8	1
reset_info_cp[4]	3972	1			T4	1		T6	19		T8	1
reset_info_cp[8]	108	1			T23	1		T37	1		T42	1
reset_info_cp[16]	108	1			T22	2		T23	1		T25	1
reset_info_cp[32]	110	1			T10	1		T22	4		T23	2
reset_info_cp[64]	93	1			T10	1		T11	1		T22	2
reset_info_cp[128]	114	1			T3	1		T6	1		T10	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3095	1			T6	13		T22	38		T23	72
reset_info_cp[1]	auto[1]	2870	1			T4	1		T6	13		T8	1
reset_info_cp[2]	auto[0]	944	1			T22	21		T23	40		T37	8
reset_info_cp[2]	auto[1]	2097	1			T4	1		T6	19		T8	1
reset_info_cp[4]	auto[0]	1457	1			T22	30		T23	37		T37	6
reset_info_cp[4]	auto[1]	2515	1			T4	1		T6	19		T8	1
reset_info_cp[8]	auto[0]	32	1			T42	1		T135	1		T100	1
reset_info_cp[8]	auto[1]	76	1			T23	1		T37	1		T27	1
reset_info_cp[16]	auto[0]	37	1			T23	1		T37	1		T106	1
reset_info_cp[16]	auto[1]	71	1			T22	2		T25	1		T26	1
reset_info_cp[32]	auto[0]	42	1			T10	1		T22	1		T106	1
reset_info_cp[32]	auto[1]	68	1			T22	3		T23	2		T27	1
reset_info_cp[64]	auto[0]	30	1			T10	1		T22	1		T23	1
reset_info_cp[64]	auto[1]	63	1			T11	1		T22	1		T23	2
reset_info_cp[128]	auto[0]	43	1			T3	1		T10	1		T23	1
reset_info_cp[128]	auto[1]	71	1			T6	1		T27	2		T28	2