| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.44 | 99.40 | 99.31 | 99.88 | 99.83 | 99.46 | 98.77 |
| T542 | /workspace/coverage/default/16.rstmgr_reset.3383916146 | Feb 21 12:36:44 PM PST 24 | Feb 21 12:36:49 PM PST 24 | 834003656 ps | ||
| T543 | /workspace/coverage/default/13.rstmgr_alert_test.2575201048 | Feb 21 12:36:38 PM PST 24 | Feb 21 12:36:41 PM PST 24 | 52979979 ps | ||
| T544 | /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4241694373 | Feb 21 12:36:32 PM PST 24 | Feb 21 12:36:35 PM PST 24 | 161619561 ps | ||
| T545 | /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.338781498 | Feb 21 12:37:27 PM PST 24 | Feb 21 12:37:28 PM PST 24 | 121779644 ps | ||
| T546 | /workspace/coverage/default/17.rstmgr_por_stretcher.4222443910 | Feb 21 12:36:41 PM PST 24 | Feb 21 12:36:43 PM PST 24 | 167901933 ps | ||
| T52 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3091540834 | Feb 21 12:32:56 PM PST 24 | Feb 21 12:32:57 PM PST 24 | 130861994 ps | ||
| T53 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1973620653 | Feb 21 12:33:18 PM PST 24 | Feb 21 12:33:19 PM PST 24 | 97997388 ps | ||
| T57 | /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1388016089 | Feb 21 12:34:21 PM PST 24 | Feb 21 12:34:24 PM PST 24 | 171955946 ps | ||
| T54 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.809672785 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 814795524 ps | ||
| T55 | /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1434940541 | Feb 21 12:33:11 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 80782728 ps | ||
| T58 | /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.330431967 | Feb 21 12:33:09 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 268329410 ps | ||
| T59 | /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.766936601 | Feb 21 12:33:22 PM PST 24 | Feb 21 12:33:25 PM PST 24 | 459075932 ps | ||
| T547 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.651640569 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 115078710 ps | ||
| T109 | /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2413568203 | Feb 21 12:33:16 PM PST 24 | Feb 21 12:33:17 PM PST 24 | 69660192 ps | ||
| T110 | /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2265245542 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:10 PM PST 24 | 83402058 ps | ||
| T111 | /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.403157395 | Feb 21 12:33:32 PM PST 24 | Feb 21 12:33:33 PM PST 24 | 181417005 ps | ||
| T61 | /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3604099717 | Feb 21 12:33:23 PM PST 24 | Feb 21 12:33:26 PM PST 24 | 474068933 ps | ||
| T134 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1458926671 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:13 PM PST 24 | 796250602 ps | ||
| T60 | /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3621555285 | Feb 21 12:33:17 PM PST 24 | Feb 21 12:33:19 PM PST 24 | 179541856 ps | ||
| T112 | /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4063636231 | Feb 21 12:33:19 PM PST 24 | Feb 21 12:33:22 PM PST 24 | 128493218 ps | ||
| T113 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1031657667 | Feb 21 12:33:10 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 68609078 ps | ||
| T62 | /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3597535860 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 488488657 ps | ||
| T114 | /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2470289240 | Feb 21 12:33:09 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 288783687 ps | ||
| T115 | /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3782724942 | Feb 21 12:33:14 PM PST 24 | Feb 21 12:33:15 PM PST 24 | 129400353 ps | ||
| T116 | /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2126424866 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 133741481 ps | ||
| T87 | /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.7337388 | Feb 21 12:33:07 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 162575881 ps | ||
| T88 | /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2919088449 | Feb 21 12:33:24 PM PST 24 | Feb 21 12:33:25 PM PST 24 | 126706492 ps | ||
| T93 | /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3343132951 | Feb 21 12:33:25 PM PST 24 | Feb 21 12:33:28 PM PST 24 | 813279985 ps | ||
| T548 | /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3203598365 | Feb 21 12:33:14 PM PST 24 | Feb 21 12:33:15 PM PST 24 | 64662142 ps | ||
| T549 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3834834574 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 275985375 ps | ||
| T89 | /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1113669921 | Feb 21 12:33:05 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 263289684 ps | ||
| T90 | /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3575165391 | Feb 21 12:33:11 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 202579623 ps | ||
| T550 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2727903644 | Feb 21 12:33:01 PM PST 24 | Feb 21 12:33:03 PM PST 24 | 121948046 ps | ||
| T91 | /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.449351870 | Feb 21 12:33:20 PM PST 24 | Feb 21 12:33:24 PM PST 24 | 912657475 ps | ||
| T92 | /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.477769333 | Feb 21 12:33:09 PM PST 24 | Feb 21 12:33:13 PM PST 24 | 556197494 ps | ||
| T131 | /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2018962529 | Feb 21 12:33:03 PM PST 24 | Feb 21 12:33:06 PM PST 24 | 414233004 ps | ||
| T94 | /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.941737872 | Feb 21 12:33:20 PM PST 24 | Feb 21 12:33:24 PM PST 24 | 654541321 ps | ||
| T551 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2169681919 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:10 PM PST 24 | 65573769 ps | ||
| T126 | /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2753761140 | Feb 21 12:33:16 PM PST 24 | Feb 21 12:33:17 PM PST 24 | 115121223 ps | ||
| T552 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1381007442 | Feb 21 12:33:02 PM PST 24 | Feb 21 12:33:05 PM PST 24 | 98288473 ps | ||
| T118 | /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2232161592 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 501948439 ps | ||
| T553 | /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3267933688 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 213071400 ps | ||
| T117 | /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2411115869 | Feb 21 12:33:11 PM PST 24 | Feb 21 12:33:13 PM PST 24 | 119291284 ps | ||
| T121 | /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.389277051 | Feb 21 12:33:15 PM PST 24 | Feb 21 12:33:18 PM PST 24 | 940450301 ps | ||
| T554 | /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3340464675 | Feb 21 12:33:09 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 88117519 ps | ||
| T555 | /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3875566996 | Feb 21 12:33:13 PM PST 24 | Feb 21 12:33:18 PM PST 24 | 660746876 ps | ||
| T556 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.607768760 | Feb 21 12:33:00 PM PST 24 | Feb 21 12:33:02 PM PST 24 | 190943632 ps | ||
| T557 | /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1083845009 | Feb 21 12:33:09 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 188329895 ps | ||
| T558 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3220275094 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:08 PM PST 24 | 148447232 ps | ||
| T559 | /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4193309977 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:08 PM PST 24 | 111738916 ps | ||
| T560 | /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.311688051 | Feb 21 12:33:15 PM PST 24 | Feb 21 12:33:16 PM PST 24 | 210700978 ps | ||
| T561 | /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3485789157 | Feb 21 12:33:18 PM PST 24 | Feb 21 12:33:20 PM PST 24 | 329499871 ps | ||
| T562 | /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3694324128 | Feb 21 12:33:25 PM PST 24 | Feb 21 12:33:27 PM PST 24 | 490822542 ps | ||
| T119 | /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4046573409 | Feb 21 12:33:04 PM PST 24 | Feb 21 12:33:08 PM PST 24 | 910362772 ps | ||
| T563 | /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1331734262 | Feb 21 12:33:12 PM PST 24 | Feb 21 12:33:13 PM PST 24 | 63783198 ps | ||
| T564 | /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2038426269 | Feb 21 12:33:26 PM PST 24 | Feb 21 12:33:28 PM PST 24 | 152166004 ps | ||
| T565 | /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.53939233 | Feb 21 12:33:13 PM PST 24 | Feb 21 12:33:15 PM PST 24 | 166317964 ps | ||
| T566 | /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.420656031 | Feb 21 12:33:05 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 233957050 ps | ||
| T567 | /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2877597383 | Feb 21 12:33:14 PM PST 24 | Feb 21 12:33:18 PM PST 24 | 490829453 ps | ||
| T568 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1172983955 | Feb 21 12:33:11 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 68659068 ps | ||
| T569 | /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.499147794 | Feb 21 12:34:47 PM PST 24 | Feb 21 12:34:50 PM PST 24 | 115737635 ps | ||
| T132 | /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.675573954 | Feb 21 12:33:04 PM PST 24 | Feb 21 12:33:08 PM PST 24 | 427900270 ps | ||
| T120 | /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2246686924 | Feb 21 12:33:10 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 437957852 ps | ||
| T570 | /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.708465114 | Feb 21 12:33:14 PM PST 24 | Feb 21 12:33:15 PM PST 24 | 146990827 ps | ||
| T571 | /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.441141261 | Feb 21 12:33:04 PM PST 24 | Feb 21 12:33:08 PM PST 24 | 138941400 ps | ||
| T572 | /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.6003379 | Feb 21 12:33:19 PM PST 24 | Feb 21 12:33:21 PM PST 24 | 131414467 ps | ||
| T573 | /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3014861446 | Feb 21 12:33:17 PM PST 24 | Feb 21 12:33:19 PM PST 24 | 124331800 ps | ||
| T574 | /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2369744608 | Feb 21 12:33:11 PM PST 24 | Feb 21 12:33:13 PM PST 24 | 126201001 ps | ||
| T575 | /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3043045052 | Feb 21 12:33:10 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 283786446 ps | ||
| T576 | /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2265753367 | Feb 21 12:33:16 PM PST 24 | Feb 21 12:33:19 PM PST 24 | 183159410 ps | ||
| T577 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2523464148 | Feb 21 12:32:57 PM PST 24 | Feb 21 12:33:03 PM PST 24 | 481456812 ps | ||
| T578 | /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3678937221 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 240857901 ps | ||
| T579 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.865119624 | Feb 21 12:33:00 PM PST 24 | Feb 21 12:33:02 PM PST 24 | 73901284 ps | ||
| T122 | /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2049845952 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 790825231 ps | ||
| T123 | /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1133682868 | Feb 21 12:33:22 PM PST 24 | Feb 21 12:33:26 PM PST 24 | 908998117 ps | ||
| T133 | /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2265133317 | Feb 21 12:33:15 PM PST 24 | Feb 21 12:33:18 PM PST 24 | 492038188 ps | ||
| T580 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4139529343 | Feb 21 12:33:09 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 344168058 ps | ||
| T581 | /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4160071223 | Feb 21 12:33:17 PM PST 24 | Feb 21 12:33:19 PM PST 24 | 170656304 ps | ||
| T582 | /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4018110033 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 893705789 ps | ||
| T583 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.62900984 | Feb 21 12:33:19 PM PST 24 | Feb 21 12:33:24 PM PST 24 | 797406358 ps | ||
| T584 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.553252968 | Feb 21 12:33:12 PM PST 24 | Feb 21 12:33:14 PM PST 24 | 140070854 ps | ||
| T585 | /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3664720618 | Feb 21 12:33:26 PM PST 24 | Feb 21 12:33:27 PM PST 24 | 66148344 ps | ||
| T586 | /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2218670893 | Feb 21 12:33:03 PM PST 24 | Feb 21 12:33:06 PM PST 24 | 117326937 ps | ||
| T587 | /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2279199142 | Feb 21 12:33:10 PM PST 24 | Feb 21 12:33:12 PM PST 24 | 158983408 ps | ||
| T588 | /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.907195084 | Feb 21 12:34:47 PM PST 24 | Feb 21 12:34:51 PM PST 24 | 298780880 ps | ||
| T589 | /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.485291205 | Feb 21 12:33:13 PM PST 24 | Feb 21 12:33:17 PM PST 24 | 886700067 ps | ||
| T590 | /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2321036170 | Feb 21 12:33:15 PM PST 24 | Feb 21 12:33:19 PM PST 24 | 516500544 ps | ||
| T591 | /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3172182706 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 498372528 ps | ||
| T592 | /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.333190950 | Feb 21 12:33:21 PM PST 24 | Feb 21 12:33:23 PM PST 24 | 105278861 ps | ||
| T593 | /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1942449041 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 69032622 ps | ||
| T594 | /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2811611101 | Feb 21 12:33:09 PM PST 24 | Feb 21 12:33:10 PM PST 24 | 77081390 ps | ||
| T595 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.472814749 | Feb 21 12:32:59 PM PST 24 | Feb 21 12:33:01 PM PST 24 | 61777135 ps | ||
| T596 | /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1946135715 | Feb 21 12:33:01 PM PST 24 | Feb 21 12:33:04 PM PST 24 | 121165186 ps | ||
| T99 | /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1675900876 | Feb 21 12:33:07 PM PST 24 | Feb 21 12:33:09 PM PST 24 | 84327357 ps | ||
| T597 | /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2339351594 | Feb 21 12:33:32 PM PST 24 | Feb 21 12:33:33 PM PST 24 | 57702454 ps | ||
| T598 | /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.194617440 | Feb 21 12:33:18 PM PST 24 | Feb 21 12:33:19 PM PST 24 | 67070326 ps | ||
| T124 | /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1398461608 | Feb 21 12:33:19 PM PST 24 | Feb 21 12:33:23 PM PST 24 | 923961293 ps | ||
| T599 | /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.459094280 | Feb 21 12:33:20 PM PST 24 | Feb 21 12:33:22 PM PST 24 | 206250729 ps | ||
| T600 | /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3091295808 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 171534021 ps | ||
| T601 | /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3610095830 | Feb 21 12:33:17 PM PST 24 | Feb 21 12:33:19 PM PST 24 | 228708842 ps | ||
| T602 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.953694595 | Feb 21 12:33:09 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 196981783 ps | ||
| T603 | /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4005702277 | Feb 21 12:34:47 PM PST 24 | Feb 21 12:34:49 PM PST 24 | 61314385 ps | ||
| T604 | /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1583716414 | Feb 21 12:33:00 PM PST 24 | Feb 21 12:33:03 PM PST 24 | 117790120 ps | ||
| T605 | /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1038714056 | Feb 21 12:33:04 PM PST 24 | Feb 21 12:33:07 PM PST 24 | 206665923 ps | ||
| T125 | /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2963641242 | Feb 21 12:33:19 PM PST 24 | Feb 21 12:33:23 PM PST 24 | 792577551 ps | ||
| T606 | /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3292886539 | Feb 21 12:33:18 PM PST 24 | Feb 21 12:33:19 PM PST 24 | 59236097 ps | ||
| T607 | /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1052532804 | Feb 21 12:33:19 PM PST 24 | Feb 21 12:33:21 PM PST 24 | 71909621 ps | ||
| T608 | /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4260457404 | Feb 21 12:33:06 PM PST 24 | Feb 21 12:33:08 PM PST 24 | 67069739 ps | ||
| T609 | /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3818401521 | Feb 21 12:33:10 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 90536154 ps | ||
| T610 | /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.624774009 | Feb 21 12:33:24 PM PST 24 | Feb 21 12:33:25 PM PST 24 | 87120435 ps | ||
| T611 | /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3711781439 | Feb 21 12:33:24 PM PST 24 | Feb 21 12:33:25 PM PST 24 | 73532971 ps | ||
| T612 | /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1457426091 | Feb 21 12:33:12 PM PST 24 | Feb 21 12:33:16 PM PST 24 | 554699194 ps | ||
| T613 | /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.13756056 | Feb 21 12:33:03 PM PST 24 | Feb 21 12:33:06 PM PST 24 | 82202187 ps | ||
| T614 | /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3954157641 | Feb 21 12:33:24 PM PST 24 | Feb 21 12:33:27 PM PST 24 | 259026016 ps | ||
| T615 | /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1443691035 | Feb 21 12:33:22 PM PST 24 | Feb 21 12:33:24 PM PST 24 | 161655324 ps | ||
| T616 | /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3430601374 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 424834213 ps | ||
| T617 | /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.822142786 | Feb 21 12:33:01 PM PST 24 | Feb 21 12:33:04 PM PST 24 | 159147496 ps | ||
| T618 | /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2544946407 | Feb 21 12:33:09 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 135620156 ps | ||
| T619 | /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2398178261 | Feb 21 12:34:47 PM PST 24 | Feb 21 12:34:51 PM PST 24 | 98191683 ps | ||
| T620 | /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4146450182 | Feb 21 12:33:08 PM PST 24 | Feb 21 12:33:11 PM PST 24 | 206123809 ps |
| Test location | /workspace/coverage/default/32.rstmgr_smoke.3944173012 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 233332455 ps |
| CPU time | 1.38 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:18 PM PST 24 |
| Peak memory | 200672 kb |
| Host | smart-45a519c3-c9fe-4ea0-96ec-9ee66537015c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944173012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3944173012 |
| Directory | /workspace/32.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/10.rstmgr_stress_all.1823302911 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14806104710 ps |
| CPU time | 44.82 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:37:24 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-c1ee82de-2c12-455c-ae4a-ed95910468f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823302911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1823302911 |
| Directory | /workspace/10.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.330431967 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 268329410 ps |
| CPU time | 2.31 seconds |
| Started | Feb 21 12:33:09 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 200124 kb |
| Host | smart-fe4a5e96-a747-41e4-b797-fa43615c4a87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330431967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.330431967 |
| Directory | /workspace/8.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sw_rst.2518030563 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 310081830 ps |
| CPU time | 2 seconds |
| Started | Feb 21 12:37:12 PM PST 24 |
| Finished | Feb 21 12:37:15 PM PST 24 |
| Peak memory | 200568 kb |
| Host | smart-29a5308c-8bda-4328-a454-ca0667d2d5f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2518030563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2518030563 |
| Directory | /workspace/28.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sec_cm.2491296778 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 8301647038 ps |
| CPU time | 14.62 seconds |
| Started | Feb 21 12:36:46 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 218396 kb |
| Host | smart-173322e7-4f65-48c5-aa34-b61199ac5c5f |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491296778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2491296778 |
| Directory | /workspace/4.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3495996620 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1892290801 ps |
| CPU time | 6.66 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:37:32 PM PST 24 |
| Peak memory | 217848 kb |
| Host | smart-d38f32f7-7055-4dfe-8c96-a23ac0174c24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495996620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3495996620 |
| Directory | /workspace/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.766936601 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 459075932 ps |
| CPU time | 1.74 seconds |
| Started | Feb 21 12:33:22 PM PST 24 |
| Finished | Feb 21 12:33:25 PM PST 24 |
| Peak memory | 200040 kb |
| Host | smart-20a1701e-5580-4b95-8dc3-ba72a9f48482 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766936601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err .766936601 |
| Directory | /workspace/15.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/32.rstmgr_stress_all.780943036 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 7559928131 ps |
| CPU time | 32.87 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:38:01 PM PST 24 |
| Peak memory | 200812 kb |
| Host | smart-3357b49e-7d18-4cd8-8652-8611fd43ab0e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780943036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.780943036 |
| Directory | /workspace/32.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3421266836 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 160743591 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 12:36:29 PM PST 24 |
| Finished | Feb 21 12:36:34 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-c585d83c-a9fd-4a66-8baa-45537e0dd0e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421266836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3421266836 |
| Directory | /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.389277051 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 940450301 ps |
| CPU time | 3.34 seconds |
| Started | Feb 21 12:33:15 PM PST 24 |
| Finished | Feb 21 12:33:18 PM PST 24 |
| Peak memory | 200152 kb |
| Host | smart-f6ed6943-4a39-4c07-b58f-7dd4b18bbec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389277051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err .389277051 |
| Directory | /workspace/14.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/19.rstmgr_alert_test.1724998599 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 85950365 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:36:54 PM PST 24 |
| Peak memory | 200476 kb |
| Host | smart-8adf39f7-3939-4f63-a414-58ebac494d06 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724998599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1724998599 |
| Directory | /workspace/19.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2814842857 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1232787216 ps |
| CPU time | 5.39 seconds |
| Started | Feb 21 12:37:00 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 218476 kb |
| Host | smart-f1aa888b-3d23-459c-bb3b-ff3f6e645540 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814842857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2814842857 |
| Directory | /workspace/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1312451439 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 226329013 ps |
| CPU time | 1.34 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200400 kb |
| Host | smart-7b97d1f9-7ea6-4c29-a061-955cc9f0f699 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312451439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1312451439 |
| Directory | /workspace/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.449351870 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 912657475 ps |
| CPU time | 3.51 seconds |
| Started | Feb 21 12:33:20 PM PST 24 |
| Finished | Feb 21 12:33:24 PM PST 24 |
| Peak memory | 200076 kb |
| Host | smart-ad88138f-ed3e-4f27-926f-93cfb43e4490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449351870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err .449351870 |
| Directory | /workspace/16.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.4046573409 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 910362772 ps |
| CPU time | 3.27 seconds |
| Started | Feb 21 12:33:04 PM PST 24 |
| Finished | Feb 21 12:33:08 PM PST 24 |
| Peak memory | 200092 kb |
| Host | smart-77687df5-3a4d-4b32-8474-0ff33056807a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046573409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err .4046573409 |
| Directory | /workspace/8.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1593987814 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1226823537 ps |
| CPU time | 5.45 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 218572 kb |
| Host | smart-76db3929-a28c-4205-86b3-053b6b0584ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1593987814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1593987814 |
| Directory | /workspace/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.477769333 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 556197494 ps |
| CPU time | 3.66 seconds |
| Started | Feb 21 12:33:09 PM PST 24 |
| Finished | Feb 21 12:33:13 PM PST 24 |
| Peak memory | 200036 kb |
| Host | smart-aac31172-3755-4b3d-a796-b8396dab8208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477769333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.477769333 |
| Directory | /workspace/11.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2126424866 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 133741481 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 200100 kb |
| Host | smart-6815bd8e-ce35-4df2-9f3e-62710f8abf96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126424866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa me_csr_outstanding.2126424866 |
| Directory | /workspace/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.rstmgr_por_stretcher.509568954 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 86616282 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200300 kb |
| Host | smart-1a44ce51-45fc-4694-b928-d0b0fca8bed0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509568954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.509568954 |
| Directory | /workspace/1.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1133682868 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 908998117 ps |
| CPU time | 3.27 seconds |
| Started | Feb 21 12:33:22 PM PST 24 |
| Finished | Feb 21 12:33:26 PM PST 24 |
| Peak memory | 200176 kb |
| Host | smart-dff82055-4b25-4c15-bd76-2603921888dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133682868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er r.1133682868 |
| Directory | /workspace/18.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.822142786 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 159147496 ps |
| CPU time | 1.83 seconds |
| Started | Feb 21 12:33:01 PM PST 24 |
| Finished | Feb 21 12:33:04 PM PST 24 |
| Peak memory | 200108 kb |
| Host | smart-f5634066-d65f-45d4-895d-cbd131ce841e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822142786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.822142786 |
| Directory | /workspace/0.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2523464148 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 481456812 ps |
| CPU time | 5.47 seconds |
| Started | Feb 21 12:32:57 PM PST 24 |
| Finished | Feb 21 12:33:03 PM PST 24 |
| Peak memory | 200060 kb |
| Host | smart-28df8666-0217-4cc5-8375-4050261dedff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523464148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2 523464148 |
| Directory | /workspace/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3091540834 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 130861994 ps |
| CPU time | 0.89 seconds |
| Started | Feb 21 12:32:56 PM PST 24 |
| Finished | Feb 21 12:32:57 PM PST 24 |
| Peak memory | 199844 kb |
| Host | smart-a55e4d26-607f-4301-a672-48f62eb3ec74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091540834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3 091540834 |
| Directory | /workspace/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.953694595 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 196981783 ps |
| CPU time | 1.39 seconds |
| Started | Feb 21 12:33:09 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 199964 kb |
| Host | smart-b5aa40c3-5140-4172-b131-27704092cc1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953694595 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.953694595 |
| Directory | /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.472814749 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 61777135 ps |
| CPU time | 0.83 seconds |
| Started | Feb 21 12:32:59 PM PST 24 |
| Finished | Feb 21 12:33:01 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-1fec0fd6-06b7-434f-a352-3d568828fd2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472814749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.472814749 |
| Directory | /workspace/0.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3340464675 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 88117519 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:33:09 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 199876 kb |
| Host | smart-5b54a1f6-4db1-4672-8b74-67291d3ff7fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340464675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa me_csr_outstanding.3340464675 |
| Directory | /workspace/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1583716414 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 117790120 ps |
| CPU time | 1.47 seconds |
| Started | Feb 21 12:33:00 PM PST 24 |
| Finished | Feb 21 12:33:03 PM PST 24 |
| Peak memory | 200112 kb |
| Host | smart-19c562f0-b313-44e8-b35a-f1028b55e343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583716414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1583716414 |
| Directory | /workspace/0.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.675573954 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 427900270 ps |
| CPU time | 1.71 seconds |
| Started | Feb 21 12:33:04 PM PST 24 |
| Finished | Feb 21 12:33:08 PM PST 24 |
| Peak memory | 200080 kb |
| Host | smart-a491dc96-23fe-4c9c-9b13-9d86e4c6c3af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675573954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err. 675573954 |
| Directory | /workspace/0.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1381007442 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 98288473 ps |
| CPU time | 1.3 seconds |
| Started | Feb 21 12:33:02 PM PST 24 |
| Finished | Feb 21 12:33:05 PM PST 24 |
| Peak memory | 200316 kb |
| Host | smart-38f6a8c3-05e6-4852-a887-abde293236af |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381007442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1 381007442 |
| Directory | /workspace/1.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.809672785 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 814795524 ps |
| CPU time | 4.64 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-5007dc0a-d157-473a-b3d8-068f3bf8f82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809672785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.809672785 |
| Directory | /workspace/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.553252968 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 140070854 ps |
| CPU time | 0.91 seconds |
| Started | Feb 21 12:33:12 PM PST 24 |
| Finished | Feb 21 12:33:14 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-ef535e30-20dc-4b75-8d39-b67342d48054 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553252968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.553252968 |
| Directory | /workspace/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2279199142 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 158983408 ps |
| CPU time | 1.44 seconds |
| Started | Feb 21 12:33:10 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 208316 kb |
| Host | smart-82a38430-b26e-4416-8f76-19d4940a508d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279199142 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2279199142 |
| Directory | /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1172983955 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 68659068 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:33:11 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 199680 kb |
| Host | smart-4e906cac-2a21-4d2c-9962-7c4448eef5ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172983955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1172983955 |
| Directory | /workspace/1.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1113669921 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 263289684 ps |
| CPU time | 2.17 seconds |
| Started | Feb 21 12:33:05 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 200124 kb |
| Host | smart-51faa78c-9b7b-41ab-b9dc-f4e47812ad87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113669921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1113669921 |
| Directory | /workspace/1.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2232161592 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 501948439 ps |
| CPU time | 1.89 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 200100 kb |
| Host | smart-6e856d76-e955-4084-96aa-5bc11ffe640f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232161592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err .2232161592 |
| Directory | /workspace/1.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.7337388 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 162575881 ps |
| CPU time | 1.44 seconds |
| Started | Feb 21 12:33:07 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 208284 kb |
| Host | smart-5a40da91-c2d5-4395-8d84-dc55bfb9a50b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7337388 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.7337388 |
| Directory | /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.13756056 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 82202187 ps |
| CPU time | 0.83 seconds |
| Started | Feb 21 12:33:03 PM PST 24 |
| Finished | Feb 21 12:33:06 PM PST 24 |
| Peak memory | 199804 kb |
| Host | smart-95a4c692-b15c-47cb-ada5-69383c8496cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13756056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.13756056 |
| Directory | /workspace/10.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1052532804 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 71909621 ps |
| CPU time | 1 seconds |
| Started | Feb 21 12:33:19 PM PST 24 |
| Finished | Feb 21 12:33:21 PM PST 24 |
| Peak memory | 199908 kb |
| Host | smart-7829062b-c684-4464-9bf2-f9b028c7b25d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052532804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s ame_csr_outstanding.1052532804 |
| Directory | /workspace/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4146450182 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 206123809 ps |
| CPU time | 1.62 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-9d941d80-f8b0-41ea-b6e0-50ddf37b8662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146450182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.4146450182 |
| Directory | /workspace/10.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3343132951 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 813279985 ps |
| CPU time | 2.77 seconds |
| Started | Feb 21 12:33:25 PM PST 24 |
| Finished | Feb 21 12:33:28 PM PST 24 |
| Peak memory | 200152 kb |
| Host | smart-97c7f47a-5469-4739-af5e-372c942675e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343132951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er r.3343132951 |
| Directory | /workspace/10.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.6003379 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 131414467 ps |
| CPU time | 1.25 seconds |
| Started | Feb 21 12:33:19 PM PST 24 |
| Finished | Feb 21 12:33:21 PM PST 24 |
| Peak memory | 215500 kb |
| Host | smart-1fad07d5-2768-4d67-a09c-78fa5e5c003a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6003379 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.6003379 |
| Directory | /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3711781439 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 73532971 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:33:24 PM PST 24 |
| Finished | Feb 21 12:33:25 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-a52dadca-9754-4fcc-b7ad-039e2cec1c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711781439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3711781439 |
| Directory | /workspace/11.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.403157395 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 181417005 ps |
| CPU time | 1.33 seconds |
| Started | Feb 21 12:33:32 PM PST 24 |
| Finished | Feb 21 12:33:33 PM PST 24 |
| Peak memory | 200096 kb |
| Host | smart-9b174274-5ac9-4f29-905f-2dc0eb8b7457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403157395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa me_csr_outstanding.403157395 |
| Directory | /workspace/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3694324128 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 490822542 ps |
| CPU time | 1.86 seconds |
| Started | Feb 21 12:33:25 PM PST 24 |
| Finished | Feb 21 12:33:27 PM PST 24 |
| Peak memory | 200136 kb |
| Host | smart-67c21473-4738-4049-91a8-966ae51bf359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694324128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er r.3694324128 |
| Directory | /workspace/11.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1443691035 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 161655324 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:33:22 PM PST 24 |
| Finished | Feb 21 12:33:24 PM PST 24 |
| Peak memory | 199936 kb |
| Host | smart-ce1cf658-efa9-4fa5-8ef0-7244d3735d39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443691035 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1443691035 |
| Directory | /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1331734262 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 63783198 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:33:12 PM PST 24 |
| Finished | Feb 21 12:33:13 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-4130226f-759c-403b-8c73-902f371de833 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331734262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1331734262 |
| Directory | /workspace/12.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2470289240 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 288783687 ps |
| CPU time | 1.69 seconds |
| Started | Feb 21 12:33:09 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 200084 kb |
| Host | smart-2ca5993c-4a53-441c-9ae8-69a45facce01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470289240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s ame_csr_outstanding.2470289240 |
| Directory | /workspace/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1388016089 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 171955946 ps |
| CPU time | 1.54 seconds |
| Started | Feb 21 12:34:21 PM PST 24 |
| Finished | Feb 21 12:34:24 PM PST 24 |
| Peak memory | 198712 kb |
| Host | smart-de450b29-f04b-4fe3-9754-24346cc3f54d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388016089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1388016089 |
| Directory | /workspace/12.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2265133317 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 492038188 ps |
| CPU time | 1.8 seconds |
| Started | Feb 21 12:33:15 PM PST 24 |
| Finished | Feb 21 12:33:18 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-e4c56d77-78b4-4e0d-a8fd-454ab65cdb0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265133317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er r.2265133317 |
| Directory | /workspace/12.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.53939233 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 166317964 ps |
| CPU time | 1.45 seconds |
| Started | Feb 21 12:33:13 PM PST 24 |
| Finished | Feb 21 12:33:15 PM PST 24 |
| Peak memory | 208444 kb |
| Host | smart-51936bf8-c429-446f-ace5-656a9b3353ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53939233 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.53939233 |
| Directory | /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1675900876 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 84327357 ps |
| CPU time | 0.81 seconds |
| Started | Feb 21 12:33:07 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 199820 kb |
| Host | smart-e50e5c9b-c6a6-440a-880a-89fb622f3da3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675900876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1675900876 |
| Directory | /workspace/13.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2411115869 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 119291284 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:33:11 PM PST 24 |
| Finished | Feb 21 12:33:13 PM PST 24 |
| Peak memory | 199984 kb |
| Host | smart-08bc43fb-d4dd-4e55-8004-de45f214776e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411115869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s ame_csr_outstanding.2411115869 |
| Directory | /workspace/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3678937221 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 240857901 ps |
| CPU time | 1.92 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 200104 kb |
| Host | smart-7b42c4c2-1aa3-41c0-a981-4180d94b1411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678937221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3678937221 |
| Directory | /workspace/13.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4018110033 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 893705789 ps |
| CPU time | 3.24 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-81ac6603-f6ba-443b-8ae6-505b0e296411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018110033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er r.4018110033 |
| Directory | /workspace/13.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1038714056 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 206665923 ps |
| CPU time | 1.27 seconds |
| Started | Feb 21 12:33:04 PM PST 24 |
| Finished | Feb 21 12:33:07 PM PST 24 |
| Peak memory | 199920 kb |
| Host | smart-c525a145-f097-43e0-830a-12cb6b24ba5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038714056 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1038714056 |
| Directory | /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.624774009 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 87120435 ps |
| CPU time | 0.87 seconds |
| Started | Feb 21 12:33:24 PM PST 24 |
| Finished | Feb 21 12:33:25 PM PST 24 |
| Peak memory | 199908 kb |
| Host | smart-53de82c1-0020-4a58-a765-a283d59aaabd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624774009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.624774009 |
| Directory | /workspace/14.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3610095830 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 228708842 ps |
| CPU time | 1.46 seconds |
| Started | Feb 21 12:33:17 PM PST 24 |
| Finished | Feb 21 12:33:19 PM PST 24 |
| Peak memory | 200096 kb |
| Host | smart-b44dc8ef-4d6c-4a13-af06-4526743c6f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610095830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s ame_csr_outstanding.3610095830 |
| Directory | /workspace/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3954157641 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 259026016 ps |
| CPU time | 2.01 seconds |
| Started | Feb 21 12:33:24 PM PST 24 |
| Finished | Feb 21 12:33:27 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-87188a4b-d900-4288-ac77-50a181a697b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954157641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3954157641 |
| Directory | /workspace/14.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4193309977 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 111738916 ps |
| CPU time | 0.89 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:08 PM PST 24 |
| Peak memory | 199936 kb |
| Host | smart-6c405ee8-40b2-475a-adb1-b3ad82ed1c3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193309977 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.4193309977 |
| Directory | /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3292886539 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 59236097 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:33:18 PM PST 24 |
| Finished | Feb 21 12:33:19 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-df21608b-2e43-4ec1-86bd-4d29217dfc20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292886539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3292886539 |
| Directory | /workspace/15.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2398178261 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 98191683 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 12:34:47 PM PST 24 |
| Finished | Feb 21 12:34:51 PM PST 24 |
| Peak memory | 200020 kb |
| Host | smart-f9b23fd6-37be-41c5-b1fd-705a4f7bc17a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398178261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s ame_csr_outstanding.2398178261 |
| Directory | /workspace/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.907195084 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 298780880 ps |
| CPU time | 2.03 seconds |
| Started | Feb 21 12:34:47 PM PST 24 |
| Finished | Feb 21 12:34:51 PM PST 24 |
| Peak memory | 199988 kb |
| Host | smart-c016e6c2-8f50-4784-92f1-cdce4571caaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907195084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.907195084 |
| Directory | /workspace/15.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3621555285 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 179541856 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 12:33:17 PM PST 24 |
| Finished | Feb 21 12:33:19 PM PST 24 |
| Peak memory | 199932 kb |
| Host | smart-133c1be8-78ce-469a-a69d-c936c86252d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621555285 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3621555285 |
| Directory | /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.194617440 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 67070326 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:33:18 PM PST 24 |
| Finished | Feb 21 12:33:19 PM PST 24 |
| Peak memory | 199824 kb |
| Host | smart-0fd9b1dc-aa93-41fe-873f-a5aa66a8a509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194617440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.194617440 |
| Directory | /workspace/16.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3782724942 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 129400353 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:33:14 PM PST 24 |
| Finished | Feb 21 12:33:15 PM PST 24 |
| Peak memory | 199820 kb |
| Host | smart-8f4a937a-0fa0-4c3b-a3aa-c9a251cb0a1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782724942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s ame_csr_outstanding.3782724942 |
| Directory | /workspace/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.941737872 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 654541321 ps |
| CPU time | 3.92 seconds |
| Started | Feb 21 12:33:20 PM PST 24 |
| Finished | Feb 21 12:33:24 PM PST 24 |
| Peak memory | 200004 kb |
| Host | smart-1488703b-8084-4bb2-b4f3-6e2f79314863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941737872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.941737872 |
| Directory | /workspace/16.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2919088449 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 126706492 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 12:33:24 PM PST 24 |
| Finished | Feb 21 12:33:25 PM PST 24 |
| Peak memory | 199904 kb |
| Host | smart-2159c165-fbdb-4e76-8cbc-e2e4c803297d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919088449 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2919088449 |
| Directory | /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4005702277 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 61314385 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:34:47 PM PST 24 |
| Finished | Feb 21 12:34:49 PM PST 24 |
| Peak memory | 199744 kb |
| Host | smart-e7527d48-3e77-4ee1-83cd-178add2e221c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005702277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.4005702277 |
| Directory | /workspace/17.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.333190950 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 105278861 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 12:33:21 PM PST 24 |
| Finished | Feb 21 12:33:23 PM PST 24 |
| Peak memory | 200156 kb |
| Host | smart-42bce096-3926-47aa-9fbf-d43e12d1330c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333190950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa me_csr_outstanding.333190950 |
| Directory | /workspace/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3875566996 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 660746876 ps |
| CPU time | 4.08 seconds |
| Started | Feb 21 12:33:13 PM PST 24 |
| Finished | Feb 21 12:33:18 PM PST 24 |
| Peak memory | 200228 kb |
| Host | smart-83243fed-8064-4314-b352-bbde1c46bb17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875566996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3875566996 |
| Directory | /workspace/17.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.485291205 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 886700067 ps |
| CPU time | 3 seconds |
| Started | Feb 21 12:33:13 PM PST 24 |
| Finished | Feb 21 12:33:17 PM PST 24 |
| Peak memory | 200228 kb |
| Host | smart-86cb09dc-77c6-42b3-b6a5-05130faf958d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485291205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err .485291205 |
| Directory | /workspace/17.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.499147794 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 115737635 ps |
| CPU time | 1.14 seconds |
| Started | Feb 21 12:34:47 PM PST 24 |
| Finished | Feb 21 12:34:50 PM PST 24 |
| Peak memory | 199812 kb |
| Host | smart-ca593d40-6a7b-4f8e-9d1c-3b0832639134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499147794 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.499147794 |
| Directory | /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2339351594 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 57702454 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:33:32 PM PST 24 |
| Finished | Feb 21 12:33:33 PM PST 24 |
| Peak memory | 199896 kb |
| Host | smart-2bcb2d8b-c09f-47b0-b59b-48d842175934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339351594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2339351594 |
| Directory | /workspace/18.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.708465114 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 146990827 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:33:14 PM PST 24 |
| Finished | Feb 21 12:33:15 PM PST 24 |
| Peak memory | 199900 kb |
| Host | smart-64a6b41e-6636-40d0-8319-ca4eb40b3a92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708465114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa me_csr_outstanding.708465114 |
| Directory | /workspace/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3485789157 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 329499871 ps |
| CPU time | 2.47 seconds |
| Started | Feb 21 12:33:18 PM PST 24 |
| Finished | Feb 21 12:33:20 PM PST 24 |
| Peak memory | 200200 kb |
| Host | smart-728bdcb8-62ce-4acb-9e4e-ad8f868aeb65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485789157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3485789157 |
| Directory | /workspace/18.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.459094280 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 206250729 ps |
| CPU time | 1.31 seconds |
| Started | Feb 21 12:33:20 PM PST 24 |
| Finished | Feb 21 12:33:22 PM PST 24 |
| Peak memory | 199932 kb |
| Host | smart-1462235d-a588-4c68-8f2d-e54a29ef3584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459094280 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.459094280 |
| Directory | /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3664720618 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 66148344 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:33:26 PM PST 24 |
| Finished | Feb 21 12:33:27 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-5ec2ab01-35e7-4987-87c3-0e6bd805f9d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664720618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3664720618 |
| Directory | /workspace/19.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4063636231 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 128493218 ps |
| CPU time | 1.34 seconds |
| Started | Feb 21 12:33:19 PM PST 24 |
| Finished | Feb 21 12:33:22 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-06d001ba-8171-48a5-8672-ff2537103162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063636231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s ame_csr_outstanding.4063636231 |
| Directory | /workspace/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2265753367 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 183159410 ps |
| CPU time | 2.32 seconds |
| Started | Feb 21 12:33:16 PM PST 24 |
| Finished | Feb 21 12:33:19 PM PST 24 |
| Peak memory | 200168 kb |
| Host | smart-84dae509-bcdd-4dc8-a9b7-282a2437bbfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265753367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2265753367 |
| Directory | /workspace/19.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1398461608 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 923961293 ps |
| CPU time | 2.88 seconds |
| Started | Feb 21 12:33:19 PM PST 24 |
| Finished | Feb 21 12:33:23 PM PST 24 |
| Peak memory | 200072 kb |
| Host | smart-0d1978f2-503b-4c0b-853d-ffee968b1685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398461608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er r.1398461608 |
| Directory | /workspace/19.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.651640569 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 115078710 ps |
| CPU time | 1.26 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 200016 kb |
| Host | smart-38cfe636-74a8-4883-82b8-ea43dc3667e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651640569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.651640569 |
| Directory | /workspace/2.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1458926671 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 796250602 ps |
| CPU time | 4.27 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:13 PM PST 24 |
| Peak memory | 200120 kb |
| Host | smart-6de596c8-cc2c-4958-bcbf-7ae455f53482 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458926671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1 458926671 |
| Directory | /workspace/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3818401521 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 90536154 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:33:10 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 199788 kb |
| Host | smart-ecb28dd3-6e94-4ef1-aabe-76bfe01bcda2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818401521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3 818401521 |
| Directory | /workspace/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.607768760 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 190943632 ps |
| CPU time | 1.16 seconds |
| Started | Feb 21 12:33:00 PM PST 24 |
| Finished | Feb 21 12:33:02 PM PST 24 |
| Peak memory | 199944 kb |
| Host | smart-17292368-d499-4fd7-bacd-66a5f48093d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607768760 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.607768760 |
| Directory | /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1031657667 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 68609078 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:33:10 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 199704 kb |
| Host | smart-980dd6b7-616c-4c8a-96a1-a1102826a515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031657667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1031657667 |
| Directory | /workspace/2.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.420656031 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 233957050 ps |
| CPU time | 1.52 seconds |
| Started | Feb 21 12:33:05 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 200064 kb |
| Host | smart-51db02dd-f2c9-4763-9b03-aeeca6ee5236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420656031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam e_csr_outstanding.420656031 |
| Directory | /workspace/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3091295808 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 171534021 ps |
| CPU time | 2.28 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-0817e35c-a4f2-4c6f-b0b0-d5eef6507433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091295808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3091295808 |
| Directory | /workspace/2.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2963641242 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 792577551 ps |
| CPU time | 2.76 seconds |
| Started | Feb 21 12:33:19 PM PST 24 |
| Finished | Feb 21 12:33:23 PM PST 24 |
| Peak memory | 200132 kb |
| Host | smart-f8a06ea9-dd4a-4122-9131-0cc43626607a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963641242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err .2963641242 |
| Directory | /workspace/2.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4139529343 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 344168058 ps |
| CPU time | 2.3 seconds |
| Started | Feb 21 12:33:09 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 200052 kb |
| Host | smart-5ae8c2ea-3ffe-4b6c-96f5-53afb49b3d85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139529343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4 139529343 |
| Directory | /workspace/3.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.62900984 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 797406358 ps |
| CPU time | 4.25 seconds |
| Started | Feb 21 12:33:19 PM PST 24 |
| Finished | Feb 21 12:33:24 PM PST 24 |
| Peak memory | 199980 kb |
| Host | smart-14914c30-4598-4d78-af40-b48f49133ec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62900984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.62900984 |
| Directory | /workspace/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2727903644 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 121948046 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 12:33:01 PM PST 24 |
| Finished | Feb 21 12:33:03 PM PST 24 |
| Peak memory | 199808 kb |
| Host | smart-4fe7b2a9-c26d-493c-ab33-9a7e96c77055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727903644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2 727903644 |
| Directory | /workspace/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2544946407 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 135620156 ps |
| CPU time | 1.38 seconds |
| Started | Feb 21 12:33:09 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 208312 kb |
| Host | smart-13d32aea-202a-4109-a387-e866aab53296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544946407 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2544946407 |
| Directory | /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.865119624 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 73901284 ps |
| CPU time | 0.8 seconds |
| Started | Feb 21 12:33:00 PM PST 24 |
| Finished | Feb 21 12:33:02 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-cfa15f10-02c8-4c29-9be6-cd39b4c7cafb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865119624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.865119624 |
| Directory | /workspace/3.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2218670893 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 117326937 ps |
| CPU time | 1.19 seconds |
| Started | Feb 21 12:33:03 PM PST 24 |
| Finished | Feb 21 12:33:06 PM PST 24 |
| Peak memory | 200088 kb |
| Host | smart-f6112404-a2c6-44c7-af56-14046c301146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218670893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa me_csr_outstanding.2218670893 |
| Directory | /workspace/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1083845009 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 188329895 ps |
| CPU time | 2.47 seconds |
| Started | Feb 21 12:33:09 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 200056 kb |
| Host | smart-c7d343c6-8237-424c-ad8b-6d11a23779ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083845009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1083845009 |
| Directory | /workspace/3.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3597535860 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 488488657 ps |
| CPU time | 1.94 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 200196 kb |
| Host | smart-7412e55d-2b5e-44e3-80ee-5e4191682b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597535860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err .3597535860 |
| Directory | /workspace/3.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1973620653 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 97997388 ps |
| CPU time | 1.37 seconds |
| Started | Feb 21 12:33:18 PM PST 24 |
| Finished | Feb 21 12:33:19 PM PST 24 |
| Peak memory | 200080 kb |
| Host | smart-558f9fc9-ab8f-41a7-8628-1b26e0b3d6f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973620653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1 973620653 |
| Directory | /workspace/4.rstmgr_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3834834574 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 275985375 ps |
| CPU time | 3.25 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 200024 kb |
| Host | smart-990ee468-2d4e-4a0d-b101-3a91eaf90bdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834834574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3 834834574 |
| Directory | /workspace/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3220275094 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 148447232 ps |
| CPU time | 0.95 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:08 PM PST 24 |
| Peak memory | 199804 kb |
| Host | smart-f48bdd26-20f2-44e2-91e9-2e4d07ecbb9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220275094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3 220275094 |
| Directory | /workspace/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2038426269 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 152166004 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 12:33:26 PM PST 24 |
| Finished | Feb 21 12:33:28 PM PST 24 |
| Peak memory | 200000 kb |
| Host | smart-44159577-37b7-42dd-b3c2-bc381a7dde6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038426269 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2038426269 |
| Directory | /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2169681919 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 65573769 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:10 PM PST 24 |
| Peak memory | 199840 kb |
| Host | smart-027bd878-2884-44f7-ab20-2041849790fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169681919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2169681919 |
| Directory | /workspace/4.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1946135715 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 121165186 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 12:33:01 PM PST 24 |
| Finished | Feb 21 12:33:04 PM PST 24 |
| Peak memory | 199892 kb |
| Host | smart-b2a05c09-68f6-4e9c-aa9c-e165fbe72bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946135715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa me_csr_outstanding.1946135715 |
| Directory | /workspace/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.441141261 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 138941400 ps |
| CPU time | 1.93 seconds |
| Started | Feb 21 12:33:04 PM PST 24 |
| Finished | Feb 21 12:33:08 PM PST 24 |
| Peak memory | 208336 kb |
| Host | smart-a95deab1-6687-427f-85cf-83b2de5f2346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441141261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.441141261 |
| Directory | /workspace/4.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2018962529 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 414233004 ps |
| CPU time | 1.75 seconds |
| Started | Feb 21 12:33:03 PM PST 24 |
| Finished | Feb 21 12:33:06 PM PST 24 |
| Peak memory | 200068 kb |
| Host | smart-26933ee3-ffa8-456e-9ef7-9a6559a066cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018962529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err .2018962529 |
| Directory | /workspace/4.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4160071223 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 170656304 ps |
| CPU time | 1.57 seconds |
| Started | Feb 21 12:33:17 PM PST 24 |
| Finished | Feb 21 12:33:19 PM PST 24 |
| Peak memory | 200148 kb |
| Host | smart-2f5debda-9f98-46c9-a482-d927ecaf2c79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160071223 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4160071223 |
| Directory | /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1434940541 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 80782728 ps |
| CPU time | 0.81 seconds |
| Started | Feb 21 12:33:11 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-c5898576-0e7c-41fb-9bdb-28ea28ba7d7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434940541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1434940541 |
| Directory | /workspace/5.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3014861446 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 124331800 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 12:33:17 PM PST 24 |
| Finished | Feb 21 12:33:19 PM PST 24 |
| Peak memory | 199876 kb |
| Host | smart-98da5467-aa6f-4502-8f90-2fd163cf1746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014861446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa me_csr_outstanding.3014861446 |
| Directory | /workspace/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2321036170 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 516500544 ps |
| CPU time | 3.45 seconds |
| Started | Feb 21 12:33:15 PM PST 24 |
| Finished | Feb 21 12:33:19 PM PST 24 |
| Peak memory | 199956 kb |
| Host | smart-0fa16d5f-4b8c-4386-a2ed-cd9d2006458f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321036170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2321036170 |
| Directory | /workspace/5.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3172182706 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 498372528 ps |
| CPU time | 1.87 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 200228 kb |
| Host | smart-b665fac8-10ed-45c0-aaba-48f3c71cd20f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172182706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err .3172182706 |
| Directory | /workspace/5.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3267933688 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 213071400 ps |
| CPU time | 1.31 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-2b2c6a48-75c7-4642-b78c-23347c118db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267933688 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3267933688 |
| Directory | /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1942449041 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 69032622 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:09 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-ce079017-dac7-49ea-8e80-c8665e69f45a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942449041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1942449041 |
| Directory | /workspace/6.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3043045052 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 283786446 ps |
| CPU time | 1.59 seconds |
| Started | Feb 21 12:33:10 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 200116 kb |
| Host | smart-e568f1cc-0048-48e4-b039-a4c7e08bbc49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043045052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa me_csr_outstanding.3043045052 |
| Directory | /workspace/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1457426091 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 554699194 ps |
| CPU time | 3.47 seconds |
| Started | Feb 21 12:33:12 PM PST 24 |
| Finished | Feb 21 12:33:16 PM PST 24 |
| Peak memory | 200088 kb |
| Host | smart-5a68bfe3-cc11-4738-8570-9d15e4366f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457426091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1457426091 |
| Directory | /workspace/6.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2246686924 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 437957852 ps |
| CPU time | 1.89 seconds |
| Started | Feb 21 12:33:10 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 200180 kb |
| Host | smart-fcd2dcdb-72cd-4779-b2e7-9a0cbbc0e245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246686924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err .2246686924 |
| Directory | /workspace/6.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.311688051 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 210700978 ps |
| CPU time | 1.23 seconds |
| Started | Feb 21 12:33:15 PM PST 24 |
| Finished | Feb 21 12:33:16 PM PST 24 |
| Peak memory | 199960 kb |
| Host | smart-6bfcc3d5-ee00-4a67-9efd-a4d9c7c33475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311688051 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.311688051 |
| Directory | /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3203598365 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 64662142 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:33:14 PM PST 24 |
| Finished | Feb 21 12:33:15 PM PST 24 |
| Peak memory | 199924 kb |
| Host | smart-de3688a6-b775-4310-9239-9e939ecbf19e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203598365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3203598365 |
| Directory | /workspace/7.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2811611101 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 77081390 ps |
| CPU time | 0.95 seconds |
| Started | Feb 21 12:33:09 PM PST 24 |
| Finished | Feb 21 12:33:10 PM PST 24 |
| Peak memory | 199912 kb |
| Host | smart-9a532e76-5bcf-47d6-8814-0fa1b95b0189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811611101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa me_csr_outstanding.2811611101 |
| Directory | /workspace/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3430601374 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 424834213 ps |
| CPU time | 2.92 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 200040 kb |
| Host | smart-7469f60e-34a6-43e0-bad2-372224551e00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430601374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3430601374 |
| Directory | /workspace/7.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3604099717 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 474068933 ps |
| CPU time | 1.83 seconds |
| Started | Feb 21 12:33:23 PM PST 24 |
| Finished | Feb 21 12:33:26 PM PST 24 |
| Peak memory | 200092 kb |
| Host | smart-78152621-71e6-42e3-ba3c-21eff57fee9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604099717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err .3604099717 |
| Directory | /workspace/7.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2753761140 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 115121223 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:33:16 PM PST 24 |
| Finished | Feb 21 12:33:17 PM PST 24 |
| Peak memory | 199916 kb |
| Host | smart-80d220e0-16cf-4c89-a538-e52cb5861faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753761140 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2753761140 |
| Directory | /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4260457404 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 67069739 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:33:06 PM PST 24 |
| Finished | Feb 21 12:33:08 PM PST 24 |
| Peak memory | 199832 kb |
| Host | smart-8768d8c4-047c-4034-9787-9d3e8b51d7da |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260457404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4260457404 |
| Directory | /workspace/8.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2265245542 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 83402058 ps |
| CPU time | 0.99 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:10 PM PST 24 |
| Peak memory | 199908 kb |
| Host | smart-600740a4-a3f5-48dc-a240-4c0d87530cfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265245542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa me_csr_outstanding.2265245542 |
| Directory | /workspace/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3575165391 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 202579623 ps |
| CPU time | 1.26 seconds |
| Started | Feb 21 12:33:11 PM PST 24 |
| Finished | Feb 21 12:33:12 PM PST 24 |
| Peak memory | 199928 kb |
| Host | smart-68363bda-29a9-4237-8a19-130983dcc3d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575165391 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3575165391 |
| Directory | /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2413568203 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 69660192 ps |
| CPU time | 0.83 seconds |
| Started | Feb 21 12:33:16 PM PST 24 |
| Finished | Feb 21 12:33:17 PM PST 24 |
| Peak memory | 199768 kb |
| Host | smart-1b62401f-1dee-4734-98a0-3a205f0645da |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413568203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2413568203 |
| Directory | /workspace/9.rstmgr_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2369744608 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 126201001 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 12:33:11 PM PST 24 |
| Finished | Feb 21 12:33:13 PM PST 24 |
| Peak memory | 199984 kb |
| Host | smart-b38cc49b-4612-4970-b9b2-2e4559f66b12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369744608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa me_csr_outstanding.2369744608 |
| Directory | /workspace/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2877597383 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 490829453 ps |
| CPU time | 3.28 seconds |
| Started | Feb 21 12:33:14 PM PST 24 |
| Finished | Feb 21 12:33:18 PM PST 24 |
| Peak memory | 200036 kb |
| Host | smart-83827415-f43c-4da2-8def-a4f838eb00f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877597383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2877597383 |
| Directory | /workspace/9.rstmgr_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2049845952 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 790825231 ps |
| CPU time | 2.78 seconds |
| Started | Feb 21 12:33:08 PM PST 24 |
| Finished | Feb 21 12:33:11 PM PST 24 |
| Peak memory | 199988 kb |
| Host | smart-2549bab0-7c6d-49a9-bfd3-6c5236787d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049845952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err .2049845952 |
| Directory | /workspace/9.rstmgr_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rstmgr_alert_test.3951987363 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 64452717 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:36:30 PM PST 24 |
| Finished | Feb 21 12:36:34 PM PST 24 |
| Peak memory | 200476 kb |
| Host | smart-7fa915ff-8277-436d-a458-f3aebc977f1f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951987363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3951987363 |
| Directory | /workspace/0.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.4000071653 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1228466284 ps |
| CPU time | 5.43 seconds |
| Started | Feb 21 12:36:27 PM PST 24 |
| Finished | Feb 21 12:36:33 PM PST 24 |
| Peak memory | 221864 kb |
| Host | smart-cb7aec86-f6cf-431e-be4a-3d7cfe4f75ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000071653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.4000071653 |
| Directory | /workspace/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4140953960 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 244662551 ps |
| CPU time | 1.05 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 217868 kb |
| Host | smart-480362f1-0ee1-4279-a8ce-29430cab030a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140953960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4140953960 |
| Directory | /workspace/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/0.rstmgr_por_stretcher.4231832955 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 152772531 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 200408 kb |
| Host | smart-b3487d8f-3aea-4ac1-87cc-239cb3505dfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231832955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4231832955 |
| Directory | /workspace/0.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/0.rstmgr_reset.1195041564 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 824872066 ps |
| CPU time | 4.13 seconds |
| Started | Feb 21 12:36:16 PM PST 24 |
| Finished | Feb 21 12:36:21 PM PST 24 |
| Peak memory | 200844 kb |
| Host | smart-da979e1f-39c2-43a3-95b3-56fa3eb33589 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195041564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1195041564 |
| Directory | /workspace/0.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sec_cm.4007915422 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 8312094735 ps |
| CPU time | 13.26 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 217388 kb |
| Host | smart-aee8575c-feb3-40c8-8750-50a388ca7ce7 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007915422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4007915422 |
| Directory | /workspace/0.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/0.rstmgr_smoke.1923738873 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 243164368 ps |
| CPU time | 1.63 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-68c34996-4341-44da-b35c-85bf16913935 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923738873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1923738873 |
| Directory | /workspace/0.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/0.rstmgr_stress_all.2193484529 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 984612989 ps |
| CPU time | 4.97 seconds |
| Started | Feb 21 12:36:29 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200740 kb |
| Host | smart-7cf2a81b-e611-4704-8617-246b8fe70399 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193484529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2193484529 |
| Directory | /workspace/0.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sw_rst.2932049260 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 435703517 ps |
| CPU time | 2.36 seconds |
| Started | Feb 21 12:36:30 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 200476 kb |
| Host | smart-5d7e7734-b9d0-456a-98b9-62e7fdf64342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932049260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2932049260 |
| Directory | /workspace/0.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.810822469 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 204041813 ps |
| CPU time | 1.37 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:36:47 PM PST 24 |
| Peak memory | 200460 kb |
| Host | smart-9aeac4a0-0633-4a3c-8f1e-f9d2626d64f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810822469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.810822469 |
| Directory | /workspace/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/1.rstmgr_alert_test.2950452905 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 70611902 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:39 PM PST 24 |
| Peak memory | 200412 kb |
| Host | smart-acc201d8-f4c1-4b13-815d-9e38967c23c8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950452905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2950452905 |
| Directory | /workspace/1.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2493423927 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1235209237 ps |
| CPU time | 5.43 seconds |
| Started | Feb 21 12:36:17 PM PST 24 |
| Finished | Feb 21 12:36:23 PM PST 24 |
| Peak memory | 222444 kb |
| Host | smart-f7922d30-5a4b-46f4-9c32-890fedd85f7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493423927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2493423927 |
| Directory | /workspace/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1142082157 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 245654700 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:36:33 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 217868 kb |
| Host | smart-a27c9d9a-9c43-4ccf-9693-31a1eb16975c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142082157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1142082157 |
| Directory | /workspace/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/1.rstmgr_reset.956958357 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 958080754 ps |
| CPU time | 4.61 seconds |
| Started | Feb 21 12:36:33 PM PST 24 |
| Finished | Feb 21 12:36:45 PM PST 24 |
| Peak memory | 200772 kb |
| Host | smart-6963c245-d84b-4b8b-8212-842abf938ba5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956958357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.956958357 |
| Directory | /workspace/1.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sec_cm.1611647322 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 8306437422 ps |
| CPU time | 13.85 seconds |
| Started | Feb 21 12:36:32 PM PST 24 |
| Finished | Feb 21 12:36:48 PM PST 24 |
| Peak memory | 218400 kb |
| Host | smart-2d720369-d360-490b-8a12-44857c4bdaba |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611647322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1611647322 |
| Directory | /workspace/1.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.733924379 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 95274054 ps |
| CPU time | 0.99 seconds |
| Started | Feb 21 12:36:36 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 200452 kb |
| Host | smart-33f81da6-ef0b-418f-acce-67a50ad463c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733924379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.733924379 |
| Directory | /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/1.rstmgr_smoke.4051807341 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 111066869 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200720 kb |
| Host | smart-c745421d-a614-4f63-9eb6-56c67a3eb425 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051807341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4051807341 |
| Directory | /workspace/1.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/1.rstmgr_stress_all.3267816351 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 8094803707 ps |
| CPU time | 27.74 seconds |
| Started | Feb 21 12:36:23 PM PST 24 |
| Finished | Feb 21 12:36:51 PM PST 24 |
| Peak memory | 200908 kb |
| Host | smart-7a9d0966-f42e-45c7-8063-478dbc2bc5e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267816351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3267816351 |
| Directory | /workspace/1.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sw_rst.910048263 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 376535919 ps |
| CPU time | 2.31 seconds |
| Started | Feb 21 12:36:44 PM PST 24 |
| Finished | Feb 21 12:36:48 PM PST 24 |
| Peak memory | 200652 kb |
| Host | smart-08db6a4a-81bf-4d39-95a0-2e54ad360480 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910048263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.910048263 |
| Directory | /workspace/1.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.345606005 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 72902754 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:36:36 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-4ca2ed7e-9791-4d9e-ad34-1d4557eb6523 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345606005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.345606005 |
| Directory | /workspace/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/10.rstmgr_alert_test.2669818689 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 84897426 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:36:49 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 200492 kb |
| Host | smart-da487016-5669-4cfc-add0-5b405ecdf608 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669818689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2669818689 |
| Directory | /workspace/10.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1541103392 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2372554955 ps |
| CPU time | 7.81 seconds |
| Started | Feb 21 12:36:42 PM PST 24 |
| Finished | Feb 21 12:36:53 PM PST 24 |
| Peak memory | 217792 kb |
| Host | smart-6d9feaa2-5ec2-4a5d-b5c9-6ec5fd8d3022 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1541103392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1541103392 |
| Directory | /workspace/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.810595380 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 246164911 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 217776 kb |
| Host | smart-15f77d20-c348-46bb-af39-4aad298d460d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810595380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.810595380 |
| Directory | /workspace/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/10.rstmgr_por_stretcher.3377815104 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 172329913 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 12:36:32 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 200404 kb |
| Host | smart-f5ce7766-acbc-46f4-9245-e3bc946d5a0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3377815104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3377815104 |
| Directory | /workspace/10.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/10.rstmgr_reset.2532262276 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 832695738 ps |
| CPU time | 3.87 seconds |
| Started | Feb 21 12:36:44 PM PST 24 |
| Finished | Feb 21 12:36:49 PM PST 24 |
| Peak memory | 200704 kb |
| Host | smart-fade4706-4895-4701-8337-f6dbfc26a427 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532262276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2532262276 |
| Directory | /workspace/10.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1179154525 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 182440482 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:36:40 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-2af118fd-8112-44a7-b749-9c3fa9e5f24a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1179154525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1179154525 |
| Directory | /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/10.rstmgr_smoke.4119981493 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 119494923 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 12:36:28 PM PST 24 |
| Finished | Feb 21 12:36:30 PM PST 24 |
| Peak memory | 200680 kb |
| Host | smart-d1aa86bb-8eff-47d9-a18a-ad9bd70bf996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119981493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.4119981493 |
| Directory | /workspace/10.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/10.rstmgr_sw_rst.773538585 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 124744302 ps |
| CPU time | 1.44 seconds |
| Started | Feb 21 12:36:36 PM PST 24 |
| Finished | Feb 21 12:36:43 PM PST 24 |
| Peak memory | 200512 kb |
| Host | smart-bb3a7964-f121-43a5-a788-ee490873ea31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773538585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.773538585 |
| Directory | /workspace/10.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/11.rstmgr_alert_test.1740978201 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 79290395 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:49 PM PST 24 |
| Peak memory | 200432 kb |
| Host | smart-64d77f00-02e2-456d-8790-526f86a8cb4d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740978201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1740978201 |
| Directory | /workspace/11.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.256116383 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1881050093 ps |
| CPU time | 7.15 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:49 PM PST 24 |
| Peak memory | 217928 kb |
| Host | smart-c6c79367-b80a-4d46-9ab4-989f6eea3efe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256116383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.256116383 |
| Directory | /workspace/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.694929726 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 244779783 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:36:52 PM PST 24 |
| Finished | Feb 21 12:36:53 PM PST 24 |
| Peak memory | 217676 kb |
| Host | smart-9f463422-11a0-4b1b-8c53-cc1a86ba977f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694929726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.694929726 |
| Directory | /workspace/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/11.rstmgr_por_stretcher.940889985 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 221942509 ps |
| CPU time | 0.85 seconds |
| Started | Feb 21 12:36:39 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200320 kb |
| Host | smart-536ea3fe-8950-4f49-8076-be4fd637b297 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=940889985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.940889985 |
| Directory | /workspace/11.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/11.rstmgr_reset.3105413746 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 687318915 ps |
| CPU time | 3.6 seconds |
| Started | Feb 21 12:36:47 PM PST 24 |
| Finished | Feb 21 12:36:51 PM PST 24 |
| Peak memory | 200644 kb |
| Host | smart-6beba915-2bef-4de4-ab25-2b37231c2a87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105413746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3105413746 |
| Directory | /workspace/11.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.14661246 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 138785363 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:36:44 PM PST 24 |
| Finished | Feb 21 12:36:46 PM PST 24 |
| Peak memory | 200536 kb |
| Host | smart-67effaf4-8104-43f9-a6ee-8ccd7fad55cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14661246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.14661246 |
| Directory | /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/11.rstmgr_smoke.272542663 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 201940040 ps |
| CPU time | 1.29 seconds |
| Started | Feb 21 12:37:14 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 200652 kb |
| Host | smart-2de59acf-64da-4fdf-9670-560897693d1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272542663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.272542663 |
| Directory | /workspace/11.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/11.rstmgr_stress_all.3638566331 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 9599641813 ps |
| CPU time | 32.45 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 200884 kb |
| Host | smart-18018c10-9c3d-4bde-8629-1d3535b82ae7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638566331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3638566331 |
| Directory | /workspace/11.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sw_rst.1925953623 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 146622734 ps |
| CPU time | 1.82 seconds |
| Started | Feb 21 12:36:50 PM PST 24 |
| Finished | Feb 21 12:36:52 PM PST 24 |
| Peak memory | 200568 kb |
| Host | smart-f1139769-4046-4dd4-98b6-ecce5a232d61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925953623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1925953623 |
| Directory | /workspace/11.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.4038807726 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 97527829 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 12:36:42 PM PST 24 |
| Finished | Feb 21 12:36:46 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-3a2886be-15fd-486a-8665-fe13338c7746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038807726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.4038807726 |
| Directory | /workspace/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/12.rstmgr_alert_test.3702194255 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 65582339 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:36:36 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 200408 kb |
| Host | smart-6bbbc3d2-d4b1-49ad-a87b-0975e66cfb13 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702194255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3702194255 |
| Directory | /workspace/12.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1307938313 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2356933481 ps |
| CPU time | 8 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:57 PM PST 24 |
| Peak memory | 221944 kb |
| Host | smart-384c983d-063e-4073-83c7-35b9e7f66a3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1307938313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1307938313 |
| Directory | /workspace/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4254925613 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 243700383 ps |
| CPU time | 1.05 seconds |
| Started | Feb 21 12:36:42 PM PST 24 |
| Finished | Feb 21 12:36:46 PM PST 24 |
| Peak memory | 218016 kb |
| Host | smart-26eb0daa-9e07-40ed-a0a2-af7b76af7fe7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254925613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4254925613 |
| Directory | /workspace/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/12.rstmgr_por_stretcher.1395469038 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 74035692 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:37:04 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 200296 kb |
| Host | smart-d02d1037-897a-47db-80e0-f4e63aee1b35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395469038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1395469038 |
| Directory | /workspace/12.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/12.rstmgr_reset.3655538299 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1856751101 ps |
| CPU time | 7.7 seconds |
| Started | Feb 21 12:36:41 PM PST 24 |
| Finished | Feb 21 12:36:52 PM PST 24 |
| Peak memory | 200728 kb |
| Host | smart-843dc81c-f3a4-4adc-8fa2-470a5082f8d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655538299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3655538299 |
| Directory | /workspace/12.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3905881745 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 109416543 ps |
| CPU time | 0.96 seconds |
| Started | Feb 21 12:36:33 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 200368 kb |
| Host | smart-0a92a8c2-88cc-4e98-a51a-86fa9f17d755 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905881745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3905881745 |
| Directory | /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/12.rstmgr_smoke.1734551905 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 120398333 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:39 PM PST 24 |
| Peak memory | 200748 kb |
| Host | smart-7143a8b3-8c1d-4d13-96cd-dc809b14bc4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734551905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1734551905 |
| Directory | /workspace/12.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/12.rstmgr_stress_all.1078196754 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 4513228985 ps |
| CPU time | 20.49 seconds |
| Started | Feb 21 12:36:41 PM PST 24 |
| Finished | Feb 21 12:37:02 PM PST 24 |
| Peak memory | 200884 kb |
| Host | smart-ed26314d-de48-4bb5-b279-352ddf9f19d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078196754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1078196754 |
| Directory | /workspace/12.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sw_rst.1479821302 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 452775111 ps |
| CPU time | 2.52 seconds |
| Started | Feb 21 12:37:06 PM PST 24 |
| Finished | Feb 21 12:37:11 PM PST 24 |
| Peak memory | 200608 kb |
| Host | smart-ab353153-56d8-4e6b-8b58-627620b3903b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479821302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1479821302 |
| Directory | /workspace/12.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3137764189 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 89082430 ps |
| CPU time | 0.88 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:57 PM PST 24 |
| Peak memory | 200508 kb |
| Host | smart-7893a051-8e0f-4f24-89bb-678917544358 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137764189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3137764189 |
| Directory | /workspace/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/13.rstmgr_alert_test.2575201048 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 52979979 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:36:41 PM PST 24 |
| Peak memory | 200384 kb |
| Host | smart-62c77e64-c9d9-4b68-8b73-2f18b8c91e59 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575201048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2575201048 |
| Directory | /workspace/13.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.612048864 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1889171816 ps |
| CPU time | 7.31 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:36:53 PM PST 24 |
| Peak memory | 218500 kb |
| Host | smart-8fc38d91-872b-4faa-95d0-394cf5f79159 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612048864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.612048864 |
| Directory | /workspace/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1277260817 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 244708636 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 217964 kb |
| Host | smart-580c345e-1ac6-4617-b8f8-6ef695654f92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277260817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1277260817 |
| Directory | /workspace/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/13.rstmgr_por_stretcher.636904343 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 130448572 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:56 PM PST 24 |
| Peak memory | 200388 kb |
| Host | smart-7038bce3-3dab-4226-8275-b6aa29487dab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636904343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.636904343 |
| Directory | /workspace/13.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/13.rstmgr_reset.3361359262 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 761629948 ps |
| CPU time | 3.76 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:52 PM PST 24 |
| Peak memory | 200784 kb |
| Host | smart-793a5105-26a6-44aa-9d53-3952dc80e95b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3361359262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3361359262 |
| Directory | /workspace/13.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.157496928 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 106659740 ps |
| CPU time | 0.95 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200432 kb |
| Host | smart-1a426187-d84b-4aa8-ba08-d55e6c1b2518 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157496928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.157496928 |
| Directory | /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/13.rstmgr_smoke.1726414995 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 127997617 ps |
| CPU time | 1.16 seconds |
| Started | Feb 21 12:36:46 PM PST 24 |
| Finished | Feb 21 12:36:48 PM PST 24 |
| Peak memory | 200504 kb |
| Host | smart-a65e1fbd-244b-435d-bab5-e5e79e96a3d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726414995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1726414995 |
| Directory | /workspace/13.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/13.rstmgr_stress_all.2651592620 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 7609720336 ps |
| CPU time | 24.36 seconds |
| Started | Feb 21 12:36:52 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200832 kb |
| Host | smart-4274caa5-3b06-441b-a07c-63e7f88f1cd5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651592620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2651592620 |
| Directory | /workspace/13.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sw_rst.3490323520 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 112648854 ps |
| CPU time | 1.47 seconds |
| Started | Feb 21 12:36:44 PM PST 24 |
| Finished | Feb 21 12:36:47 PM PST 24 |
| Peak memory | 200500 kb |
| Host | smart-2d8d705c-5b90-419e-bc1b-2cc98814bb81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490323520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3490323520 |
| Directory | /workspace/13.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3012345766 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 96816013 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200584 kb |
| Host | smart-5cfad73f-6235-4d3f-8168-254b99754bb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012345766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3012345766 |
| Directory | /workspace/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/14.rstmgr_alert_test.2747208015 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 73944817 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-22b35fdc-40b2-4142-bc24-2a28a38ad2d7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747208015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2747208015 |
| Directory | /workspace/14.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2323257144 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1893206878 ps |
| CPU time | 6.59 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 217896 kb |
| Host | smart-cfd346ad-54aa-4505-b4c4-6305ffd3d855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323257144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2323257144 |
| Directory | /workspace/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.448595059 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 243826277 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 12:37:01 PM PST 24 |
| Finished | Feb 21 12:37:04 PM PST 24 |
| Peak memory | 217796 kb |
| Host | smart-4fa52d7f-412c-4e4f-ba71-d6b093e2bd73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448595059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.448595059 |
| Directory | /workspace/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/14.rstmgr_por_stretcher.2670847195 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 144861819 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:36:54 PM PST 24 |
| Finished | Feb 21 12:36:56 PM PST 24 |
| Peak memory | 200280 kb |
| Host | smart-ebb64670-7731-4306-9d51-c95c47c1d727 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670847195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2670847195 |
| Directory | /workspace/14.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/14.rstmgr_reset.2658944643 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2028954931 ps |
| CPU time | 7.42 seconds |
| Started | Feb 21 12:36:52 PM PST 24 |
| Finished | Feb 21 12:37:00 PM PST 24 |
| Peak memory | 200736 kb |
| Host | smart-5aed5af9-8d52-4d5f-b892-d9a7b634b820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658944643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2658944643 |
| Directory | /workspace/14.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2793876459 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 177076382 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 200536 kb |
| Host | smart-348c9c83-d26b-4aea-b54d-062c1461d963 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793876459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2793876459 |
| Directory | /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/14.rstmgr_smoke.1833719701 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 251704266 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 12:36:42 PM PST 24 |
| Finished | Feb 21 12:36:46 PM PST 24 |
| Peak memory | 200628 kb |
| Host | smart-57b49dee-190e-4871-9dec-6dd957eb7fe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833719701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1833719701 |
| Directory | /workspace/14.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/14.rstmgr_stress_all.2628332054 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 204791261 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 12:37:04 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 200512 kb |
| Host | smart-3ab44019-598c-440c-9408-a4319e08f9fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628332054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2628332054 |
| Directory | /workspace/14.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sw_rst.901262704 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 437833818 ps |
| CPU time | 2.54 seconds |
| Started | Feb 21 12:36:45 PM PST 24 |
| Finished | Feb 21 12:36:48 PM PST 24 |
| Peak memory | 200548 kb |
| Host | smart-f6ca231a-5e39-48cc-8756-a15a06f19807 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901262704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.901262704 |
| Directory | /workspace/14.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2814796307 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 180242103 ps |
| CPU time | 1.19 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-6c3ae794-8f08-485f-b26c-758153a57a89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814796307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2814796307 |
| Directory | /workspace/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/15.rstmgr_alert_test.2437051956 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 78154772 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:36:44 PM PST 24 |
| Finished | Feb 21 12:36:46 PM PST 24 |
| Peak memory | 200508 kb |
| Host | smart-a71d9fbf-c68f-475b-9c03-d78b0fd128e0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437051956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2437051956 |
| Directory | /workspace/15.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.4148044821 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2360051241 ps |
| CPU time | 7.78 seconds |
| Started | Feb 21 12:36:52 PM PST 24 |
| Finished | Feb 21 12:37:00 PM PST 24 |
| Peak memory | 217648 kb |
| Host | smart-c1ebc34c-db49-4ab8-8d79-0e6ead07c4c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148044821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4148044821 |
| Directory | /workspace/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.170758859 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 244397776 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 12:36:52 PM PST 24 |
| Finished | Feb 21 12:36:54 PM PST 24 |
| Peak memory | 217824 kb |
| Host | smart-f2e004bd-95ef-4419-84b5-dddb37711622 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170758859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.170758859 |
| Directory | /workspace/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/15.rstmgr_por_stretcher.1573458825 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 90818384 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:36:42 PM PST 24 |
| Finished | Feb 21 12:36:45 PM PST 24 |
| Peak memory | 200300 kb |
| Host | smart-9a25fb43-5585-4c74-babf-86f3886a5cbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1573458825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1573458825 |
| Directory | /workspace/15.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/15.rstmgr_reset.2921909663 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 882618801 ps |
| CPU time | 4.06 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:36:49 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-bb7c1907-d8c1-4858-ac07-467e9cd654b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921909663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2921909663 |
| Directory | /workspace/15.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4091954679 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 184030815 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 12:36:52 PM PST 24 |
| Finished | Feb 21 12:36:54 PM PST 24 |
| Peak memory | 200432 kb |
| Host | smart-a4dac89b-cc53-407e-9456-5926a95a1398 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091954679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4091954679 |
| Directory | /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/15.rstmgr_smoke.4134010463 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 261415419 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200736 kb |
| Host | smart-428a4792-44b5-4b24-82b3-d06c502a5b93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134010463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4134010463 |
| Directory | /workspace/15.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/15.rstmgr_stress_all.2277856385 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1667885781 ps |
| CPU time | 7.28 seconds |
| Started | Feb 21 12:36:52 PM PST 24 |
| Finished | Feb 21 12:37:00 PM PST 24 |
| Peak memory | 200676 kb |
| Host | smart-dfeaa0f5-f48a-455b-9a12-bb11abded9f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277856385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2277856385 |
| Directory | /workspace/15.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sw_rst.3337217237 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 452867015 ps |
| CPU time | 2.52 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:41 PM PST 24 |
| Peak memory | 200480 kb |
| Host | smart-8bacc02d-b6b0-4222-9ccf-a91236194366 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337217237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3337217237 |
| Directory | /workspace/15.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1445067055 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 62191796 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:37:05 PM PST 24 |
| Finished | Feb 21 12:37:07 PM PST 24 |
| Peak memory | 200508 kb |
| Host | smart-9e3d4e4c-0e62-462f-bdf3-7bb150b2b50f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1445067055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1445067055 |
| Directory | /workspace/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/16.rstmgr_alert_test.614379312 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 67992956 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-1c129369-0ea1-4452-b927-c8c5abc7a8ba |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614379312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.614379312 |
| Directory | /workspace/16.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2407730294 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1917166604 ps |
| CPU time | 6.97 seconds |
| Started | Feb 21 12:36:47 PM PST 24 |
| Finished | Feb 21 12:36:54 PM PST 24 |
| Peak memory | 217724 kb |
| Host | smart-fe6c1995-9947-4c28-a374-7eb98fc56ced |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407730294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2407730294 |
| Directory | /workspace/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.841529948 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 244362853 ps |
| CPU time | 1.11 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 217908 kb |
| Host | smart-72b156ea-9eeb-4871-be1f-fc73691c58dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=841529948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.841529948 |
| Directory | /workspace/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/16.rstmgr_por_stretcher.3451596946 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 100999921 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:36:41 PM PST 24 |
| Peak memory | 200212 kb |
| Host | smart-129f433d-067d-412c-9a6d-021bcc4234a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451596946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3451596946 |
| Directory | /workspace/16.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/16.rstmgr_reset.3383916146 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 834003656 ps |
| CPU time | 4 seconds |
| Started | Feb 21 12:36:44 PM PST 24 |
| Finished | Feb 21 12:36:49 PM PST 24 |
| Peak memory | 200688 kb |
| Host | smart-09f5151c-281d-4312-b369-873b3fda8942 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383916146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3383916146 |
| Directory | /workspace/16.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2179347875 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 142356042 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:36:46 PM PST 24 |
| Finished | Feb 21 12:36:47 PM PST 24 |
| Peak memory | 200752 kb |
| Host | smart-a1c500a3-2c59-46a9-ade8-2b02a4da2b1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179347875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2179347875 |
| Directory | /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/16.rstmgr_smoke.2785954737 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 119739201 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200668 kb |
| Host | smart-c382fc2f-78f8-4271-a2a0-ceb1db6d03a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785954737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2785954737 |
| Directory | /workspace/16.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/16.rstmgr_stress_all.1646303113 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 276748136 ps |
| CPU time | 1.56 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200592 kb |
| Host | smart-f2c76321-ac09-4ccb-9cd4-b6139dd81d22 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646303113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1646303113 |
| Directory | /workspace/16.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sw_rst.2826801162 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 121271877 ps |
| CPU time | 1.5 seconds |
| Started | Feb 21 12:36:31 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 200564 kb |
| Host | smart-5fbda8ed-10cf-49d2-b649-7c050399d216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826801162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2826801162 |
| Directory | /workspace/16.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3200615565 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 86525857 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 12:36:52 PM PST 24 |
| Finished | Feb 21 12:36:54 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-7372a9fb-6988-439a-8d8f-285b843275c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200615565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3200615565 |
| Directory | /workspace/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/17.rstmgr_alert_test.3297266495 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 71706705 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 200404 kb |
| Host | smart-ba1a8ac4-720c-4df5-abea-517533b6217a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297266495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3297266495 |
| Directory | /workspace/17.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1578925638 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2339765433 ps |
| CPU time | 7.79 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:36:48 PM PST 24 |
| Peak memory | 217788 kb |
| Host | smart-4ad14e7a-1402-4c6e-b111-c9aabf27ebf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578925638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1578925638 |
| Directory | /workspace/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2921167189 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 244160719 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:37:02 PM PST 24 |
| Finished | Feb 21 12:37:05 PM PST 24 |
| Peak memory | 218196 kb |
| Host | smart-a9717747-7853-43e8-9368-38b15a2abe35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921167189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2921167189 |
| Directory | /workspace/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/17.rstmgr_por_stretcher.4222443910 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 167901933 ps |
| CPU time | 0.81 seconds |
| Started | Feb 21 12:36:41 PM PST 24 |
| Finished | Feb 21 12:36:43 PM PST 24 |
| Peak memory | 200284 kb |
| Host | smart-7662cd8f-fadd-4647-b1c0-d91c39d21df6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222443910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4222443910 |
| Directory | /workspace/17.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/17.rstmgr_reset.213045071 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1065825629 ps |
| CPU time | 4.5 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:40 PM PST 24 |
| Peak memory | 200784 kb |
| Host | smart-dc3292cd-6a94-4231-8bd5-20eb8af1a961 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213045071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.213045071 |
| Directory | /workspace/17.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.4267391135 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 107319016 ps |
| CPU time | 0.95 seconds |
| Started | Feb 21 12:36:49 PM PST 24 |
| Finished | Feb 21 12:36:51 PM PST 24 |
| Peak memory | 200536 kb |
| Host | smart-d0f10f66-0857-4d52-bc46-6ada7f62e086 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4267391135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.4267391135 |
| Directory | /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/17.rstmgr_smoke.2411790805 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 262233725 ps |
| CPU time | 1.53 seconds |
| Started | Feb 21 12:36:44 PM PST 24 |
| Finished | Feb 21 12:36:47 PM PST 24 |
| Peak memory | 200656 kb |
| Host | smart-98661b8e-625b-4b1c-a225-3a9ec38d34ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411790805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2411790805 |
| Directory | /workspace/17.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/17.rstmgr_stress_all.1924634091 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1681168138 ps |
| CPU time | 6.08 seconds |
| Started | Feb 21 12:37:06 PM PST 24 |
| Finished | Feb 21 12:37:14 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-04f541b6-a91a-4409-a338-bd4242253354 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924634091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1924634091 |
| Directory | /workspace/17.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sw_rst.2473184546 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 342364953 ps |
| CPU time | 2.05 seconds |
| Started | Feb 21 12:36:46 PM PST 24 |
| Finished | Feb 21 12:36:48 PM PST 24 |
| Peak memory | 200596 kb |
| Host | smart-4729decf-d179-4bb7-9856-29d171e63e43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473184546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2473184546 |
| Directory | /workspace/17.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.874487164 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 170583756 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 12:36:42 PM PST 24 |
| Finished | Feb 21 12:36:46 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-c651ef36-c994-4698-8308-53039778c79d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874487164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.874487164 |
| Directory | /workspace/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/18.rstmgr_alert_test.1296410943 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 73944296 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:57 PM PST 24 |
| Peak memory | 200472 kb |
| Host | smart-386e3319-8d05-4405-b074-7b2156185a60 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296410943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1296410943 |
| Directory | /workspace/18.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2054827003 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 250115056 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 217916 kb |
| Host | smart-a8af0a42-51c1-44b1-9d9a-98cd6b970970 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054827003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2054827003 |
| Directory | /workspace/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/18.rstmgr_por_stretcher.3935415974 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 114778638 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200296 kb |
| Host | smart-9af0c1c7-76ce-44a7-81fa-cd6fa50d04b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935415974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3935415974 |
| Directory | /workspace/18.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/18.rstmgr_reset.2544574515 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1437043957 ps |
| CPU time | 5.95 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:44 PM PST 24 |
| Peak memory | 200672 kb |
| Host | smart-3c65f729-d055-4d5b-8434-3e4f9d932a26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544574515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2544574515 |
| Directory | /workspace/18.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.482773616 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 176361516 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 12:37:04 PM PST 24 |
| Finished | Feb 21 12:37:10 PM PST 24 |
| Peak memory | 200376 kb |
| Host | smart-338e802b-836f-4763-a64b-f9a8afc2c908 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482773616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.482773616 |
| Directory | /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/18.rstmgr_smoke.2820998228 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 122071924 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:36:49 PM PST 24 |
| Finished | Feb 21 12:36:51 PM PST 24 |
| Peak memory | 200640 kb |
| Host | smart-7982124a-3883-490c-8301-a93d4114f594 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820998228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2820998228 |
| Directory | /workspace/18.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/18.rstmgr_stress_all.3737179339 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4244059478 ps |
| CPU time | 13.47 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200800 kb |
| Host | smart-3cd5437d-4aa4-437d-a9d5-8876964b69de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737179339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3737179339 |
| Directory | /workspace/18.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sw_rst.2286478911 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 363167792 ps |
| CPU time | 1.89 seconds |
| Started | Feb 21 12:36:50 PM PST 24 |
| Finished | Feb 21 12:36:52 PM PST 24 |
| Peak memory | 200488 kb |
| Host | smart-534ebed8-19b2-4292-ab22-e49346149fee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286478911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2286478911 |
| Directory | /workspace/18.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3095864105 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 73370757 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:36:47 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-0680aa46-c01f-449e-a423-3aba51e83263 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3095864105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3095864105 |
| Directory | /workspace/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1739884530 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1224497304 ps |
| CPU time | 5.54 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:05 PM PST 24 |
| Peak memory | 217856 kb |
| Host | smart-f8a432ec-3361-4cb8-ad97-bfa62a857811 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739884530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1739884530 |
| Directory | /workspace/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2852964544 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 244824005 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:57 PM PST 24 |
| Peak memory | 217984 kb |
| Host | smart-2c59d554-c08b-49ef-b12e-5b2690544b0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852964544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2852964544 |
| Directory | /workspace/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/19.rstmgr_por_stretcher.2146028215 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 95396597 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200296 kb |
| Host | smart-6b1ea61c-3077-4b95-8dc1-d53ebb4b9c53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146028215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2146028215 |
| Directory | /workspace/19.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/19.rstmgr_reset.1268143033 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1411915900 ps |
| CPU time | 5.38 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200764 kb |
| Host | smart-e41498fe-6659-4fac-a4f3-28445a9432b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268143033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1268143033 |
| Directory | /workspace/19.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2437840861 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 152833400 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 12:37:04 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-8e0a8b7a-2b70-4e4e-9046-3dbe9588c57f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437840861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2437840861 |
| Directory | /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/19.rstmgr_smoke.2080189437 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 195165228 ps |
| CPU time | 1.34 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-6f6aed5e-8019-4534-accb-448a4689727e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080189437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2080189437 |
| Directory | /workspace/19.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/19.rstmgr_stress_all.1190541234 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2936924023 ps |
| CPU time | 12.55 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:37:08 PM PST 24 |
| Peak memory | 200868 kb |
| Host | smart-1c5d2e3b-fec4-4bd8-873f-9a21346baca3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190541234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1190541234 |
| Directory | /workspace/19.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sw_rst.493547858 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 378066296 ps |
| CPU time | 1.94 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:43 PM PST 24 |
| Peak memory | 200488 kb |
| Host | smart-bb1b8697-4f05-4e07-87fb-539060e31ad0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493547858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.493547858 |
| Directory | /workspace/19.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2670612700 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 194649146 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 12:36:45 PM PST 24 |
| Finished | Feb 21 12:36:47 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-c2a73339-a0e9-43ab-837f-e0266824370a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670612700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2670612700 |
| Directory | /workspace/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/2.rstmgr_alert_test.4247105530 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 63731082 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:36:29 PM PST 24 |
| Finished | Feb 21 12:36:33 PM PST 24 |
| Peak memory | 200392 kb |
| Host | smart-90fb6b32-f242-450d-bffe-ed7059ddaea2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247105530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4247105530 |
| Directory | /workspace/2.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4079376578 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1228531104 ps |
| CPU time | 5.45 seconds |
| Started | Feb 21 12:36:32 PM PST 24 |
| Finished | Feb 21 12:36:44 PM PST 24 |
| Peak memory | 217908 kb |
| Host | smart-67ee903c-91dd-4dec-9058-a631478aa30e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079376578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4079376578 |
| Directory | /workspace/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3561170277 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 244570521 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 217988 kb |
| Host | smart-7a4769c9-6238-4ed2-8d8c-1f7d742967c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561170277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3561170277 |
| Directory | /workspace/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/2.rstmgr_por_stretcher.2500614551 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 128610547 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:36:31 PM PST 24 |
| Finished | Feb 21 12:36:34 PM PST 24 |
| Peak memory | 200324 kb |
| Host | smart-061c6a47-8f0d-49e2-a68d-2f115cc2a3c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500614551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2500614551 |
| Directory | /workspace/2.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/2.rstmgr_reset.816869910 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1577415376 ps |
| CPU time | 6.4 seconds |
| Started | Feb 21 12:36:19 PM PST 24 |
| Finished | Feb 21 12:36:26 PM PST 24 |
| Peak memory | 200736 kb |
| Host | smart-170ce081-960a-445d-b05c-3ff726739b0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816869910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.816869910 |
| Directory | /workspace/2.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sec_cm.1097889077 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 8345140107 ps |
| CPU time | 14.12 seconds |
| Started | Feb 21 12:36:39 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 217496 kb |
| Host | smart-b863d5f9-b7be-48e6-9ad8-4bd24ea0e3f0 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097889077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1097889077 |
| Directory | /workspace/2.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3411177169 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 139833247 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:36:32 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 200432 kb |
| Host | smart-0ef3de7a-8289-45b4-92b6-596853ae743b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411177169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3411177169 |
| Directory | /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/2.rstmgr_smoke.1486119156 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 113482533 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 12:36:36 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 200676 kb |
| Host | smart-3ac4bc92-32ce-4030-8832-80fd5450c660 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486119156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1486119156 |
| Directory | /workspace/2.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/2.rstmgr_stress_all.3402038822 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 4545310612 ps |
| CPU time | 15.33 seconds |
| Started | Feb 21 12:36:26 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200768 kb |
| Host | smart-9e12bda1-26f1-47e9-89cc-88b025ed980c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402038822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3402038822 |
| Directory | /workspace/2.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sw_rst.3467222 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 143452923 ps |
| CPU time | 1.84 seconds |
| Started | Feb 21 12:36:44 PM PST 24 |
| Finished | Feb 21 12:36:48 PM PST 24 |
| Peak memory | 200468 kb |
| Host | smart-adda0bf1-9644-4c91-ba4b-dd46879b3351 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3467222 |
| Directory | /workspace/2.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2241990878 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 101034017 ps |
| CPU time | 0.96 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:36:41 PM PST 24 |
| Peak memory | 200540 kb |
| Host | smart-8e212cfb-4865-43b1-b579-abeb8ffc7a58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241990878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2241990878 |
| Directory | /workspace/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/20.rstmgr_alert_test.1072326444 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 60165659 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 200384 kb |
| Host | smart-eac88dbf-7f85-4d1c-9ffc-ef4d6470be2b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072326444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1072326444 |
| Directory | /workspace/20.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2215473298 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1223164546 ps |
| CPU time | 5.45 seconds |
| Started | Feb 21 12:36:30 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 218496 kb |
| Host | smart-0494bacd-3296-4af4-b4b1-f2758e78bafa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215473298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2215473298 |
| Directory | /workspace/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1573704330 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 243898307 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 217916 kb |
| Host | smart-8928c5a6-d78e-47c9-b459-df5e55ad9544 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1573704330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1573704330 |
| Directory | /workspace/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/20.rstmgr_por_stretcher.4212786765 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 197875245 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:36:47 PM PST 24 |
| Peak memory | 200408 kb |
| Host | smart-a7a155c2-c16d-4b62-b99c-5c650a4ce0c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212786765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4212786765 |
| Directory | /workspace/20.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/20.rstmgr_reset.2070576150 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 864709747 ps |
| CPU time | 3.85 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 200724 kb |
| Host | smart-17047999-5dcf-4de5-8701-5f7de42933e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070576150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2070576150 |
| Directory | /workspace/20.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2468208384 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 143698037 ps |
| CPU time | 1.11 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:39 PM PST 24 |
| Peak memory | 200512 kb |
| Host | smart-910491a5-c2b5-4d30-aa23-2768a6d54c97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468208384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2468208384 |
| Directory | /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/20.rstmgr_smoke.4098453409 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 256373091 ps |
| CPU time | 1.55 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 200576 kb |
| Host | smart-d534c8dd-2212-4d2d-a90b-6932be1b63f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098453409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4098453409 |
| Directory | /workspace/20.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/20.rstmgr_stress_all.2951981434 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 11243712608 ps |
| CPU time | 41.91 seconds |
| Started | Feb 21 12:36:36 PM PST 24 |
| Finished | Feb 21 12:37:20 PM PST 24 |
| Peak memory | 200880 kb |
| Host | smart-9506740d-7a32-4b10-a85a-6c896abd8341 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951981434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2951981434 |
| Directory | /workspace/20.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sw_rst.1136488072 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 137649581 ps |
| CPU time | 1.57 seconds |
| Started | Feb 21 12:37:13 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 200568 kb |
| Host | smart-8db48885-202e-4c1c-8eaa-014b729e87b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136488072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1136488072 |
| Directory | /workspace/20.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3881101818 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 212947332 ps |
| CPU time | 1.25 seconds |
| Started | Feb 21 12:36:49 PM PST 24 |
| Finished | Feb 21 12:36:51 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-be226514-6ed3-4b0a-b335-17df3e4c9fd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881101818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3881101818 |
| Directory | /workspace/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/21.rstmgr_alert_test.2787798123 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 77982405 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-f725491b-c560-4b0d-b09d-ac5a530f388f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787798123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2787798123 |
| Directory | /workspace/21.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2072682610 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2373341589 ps |
| CPU time | 8.51 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:47 PM PST 24 |
| Peak memory | 218612 kb |
| Host | smart-dfe13459-437a-4358-8da2-d697faf1fd41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072682610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2072682610 |
| Directory | /workspace/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2068551463 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 244660496 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:57 PM PST 24 |
| Peak memory | 217980 kb |
| Host | smart-48b1e4b1-ef36-4e50-b5e9-2294a870f934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068551463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2068551463 |
| Directory | /workspace/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/21.rstmgr_por_stretcher.292418186 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 108913617 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:43 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-cb6c94c5-50e4-41ff-8f5c-ed72da1e4404 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292418186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.292418186 |
| Directory | /workspace/21.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/21.rstmgr_reset.3802063034 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 864045411 ps |
| CPU time | 4.41 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:05 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-e0f42002-c17c-4bbf-91df-175dd6fc007a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802063034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3802063034 |
| Directory | /workspace/21.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4057254505 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 141573467 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:36:56 PM PST 24 |
| Finished | Feb 21 12:37:00 PM PST 24 |
| Peak memory | 199748 kb |
| Host | smart-920e6feb-91c2-4378-b022-4c18261d76fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057254505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4057254505 |
| Directory | /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/21.rstmgr_smoke.3531161809 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 113941332 ps |
| CPU time | 1.14 seconds |
| Started | Feb 21 12:37:05 PM PST 24 |
| Finished | Feb 21 12:37:07 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-989a81e7-ee81-4fc8-9d92-95d939cdb7d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531161809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3531161809 |
| Directory | /workspace/21.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/21.rstmgr_stress_all.165926800 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 7256263301 ps |
| CPU time | 26.21 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 200912 kb |
| Host | smart-f5400c93-865c-4ab5-bdb8-6e069f840f83 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165926800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.165926800 |
| Directory | /workspace/21.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sw_rst.4133120916 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 151409794 ps |
| CPU time | 1.88 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:02 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-ea43de12-1cac-4179-a425-d66e939a4a1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133120916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4133120916 |
| Directory | /workspace/21.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.742793413 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 150982338 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 12:37:06 PM PST 24 |
| Finished | Feb 21 12:37:09 PM PST 24 |
| Peak memory | 200416 kb |
| Host | smart-78af4f36-ccc4-410e-9305-675b7308d5e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742793413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.742793413 |
| Directory | /workspace/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/22.rstmgr_alert_test.176697514 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 61321365 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:37:12 PM PST 24 |
| Finished | Feb 21 12:37:13 PM PST 24 |
| Peak memory | 200328 kb |
| Host | smart-085fa66a-baf6-4080-b0b0-dc6f615a8cfd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176697514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.176697514 |
| Directory | /workspace/22.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1121022521 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1223323289 ps |
| CPU time | 5.79 seconds |
| Started | Feb 21 12:37:07 PM PST 24 |
| Finished | Feb 21 12:37:14 PM PST 24 |
| Peak memory | 219044 kb |
| Host | smart-40be3dfb-0073-4cc9-be7a-ecdb4e62babf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121022521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1121022521 |
| Directory | /workspace/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.761354544 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 244415365 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 12:37:04 PM PST 24 |
| Finished | Feb 21 12:37:07 PM PST 24 |
| Peak memory | 218048 kb |
| Host | smart-9b0fcacf-a7d3-4a14-b8a8-f94e124d51f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761354544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.761354544 |
| Directory | /workspace/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/22.rstmgr_por_stretcher.4227356102 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 126275720 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 200316 kb |
| Host | smart-06b7a712-4128-4039-8cf2-7c477df4014e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4227356102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4227356102 |
| Directory | /workspace/22.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/22.rstmgr_reset.2841517043 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 771503637 ps |
| CPU time | 3.59 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:59 PM PST 24 |
| Peak memory | 200804 kb |
| Host | smart-196ac0e5-caa0-4aab-ab85-19340ac35bfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841517043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2841517043 |
| Directory | /workspace/22.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1101550908 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 98619392 ps |
| CPU time | 0.96 seconds |
| Started | Feb 21 12:36:50 PM PST 24 |
| Finished | Feb 21 12:36:51 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-76084c8b-ebe3-4fd4-986f-caba9b78e259 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101550908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1101550908 |
| Directory | /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/22.rstmgr_smoke.2491108789 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 257456177 ps |
| CPU time | 1.41 seconds |
| Started | Feb 21 12:36:51 PM PST 24 |
| Finished | Feb 21 12:36:53 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-2e3fd99a-fb43-43b4-93f5-05d273f6ca99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491108789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2491108789 |
| Directory | /workspace/22.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/22.rstmgr_stress_all.805681135 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1323214993 ps |
| CPU time | 6.59 seconds |
| Started | Feb 21 12:37:06 PM PST 24 |
| Finished | Feb 21 12:37:15 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-e84bdce8-ed8e-47bf-9b36-2e699f4088c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805681135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.805681135 |
| Directory | /workspace/22.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sw_rst.2591012828 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 137358293 ps |
| CPU time | 1.62 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200596 kb |
| Host | smart-045599dd-36b9-4ae4-ab94-75941a136264 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591012828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2591012828 |
| Directory | /workspace/22.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2843516390 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 154481172 ps |
| CPU time | 1.15 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-80096dc1-829a-49b1-95c4-9e65d4bc185a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843516390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2843516390 |
| Directory | /workspace/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/23.rstmgr_alert_test.3284010913 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 81952694 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:36:56 PM PST 24 |
| Finished | Feb 21 12:36:58 PM PST 24 |
| Peak memory | 200412 kb |
| Host | smart-503ac6da-a0e4-4e05-834a-c3ae4e30397e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284010913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3284010913 |
| Directory | /workspace/23.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.9109212 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1892008945 ps |
| CPU time | 6.85 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:11 PM PST 24 |
| Peak memory | 230244 kb |
| Host | smart-082fef25-78fc-4996-b411-5a4802961e15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9109212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.9109212 |
| Directory | /workspace/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1520354553 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 243578627 ps |
| CPU time | 1.11 seconds |
| Started | Feb 21 12:36:56 PM PST 24 |
| Finished | Feb 21 12:36:58 PM PST 24 |
| Peak memory | 217872 kb |
| Host | smart-e241843b-600b-41e6-ab0f-71b9803e6976 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1520354553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1520354553 |
| Directory | /workspace/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/23.rstmgr_por_stretcher.990688086 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 190536945 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:49 PM PST 24 |
| Peak memory | 200380 kb |
| Host | smart-6fc1043e-ad35-4420-9766-d516e9eb166d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=990688086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.990688086 |
| Directory | /workspace/23.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/23.rstmgr_reset.3936007989 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1069789933 ps |
| CPU time | 4.84 seconds |
| Started | Feb 21 12:36:59 PM PST 24 |
| Finished | Feb 21 12:37:05 PM PST 24 |
| Peak memory | 200808 kb |
| Host | smart-7f7440e0-d062-4006-a66b-0e408110edd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936007989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3936007989 |
| Directory | /workspace/23.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1962532954 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 189359101 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:36:59 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 200536 kb |
| Host | smart-8d721a35-52d7-43b6-8956-4457b91a9266 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962532954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1962532954 |
| Directory | /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/23.rstmgr_smoke.2217293095 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 111659198 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:58 PM PST 24 |
| Peak memory | 200752 kb |
| Host | smart-7299d004-49d3-4ede-9c9b-18263fa8b531 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217293095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2217293095 |
| Directory | /workspace/23.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/23.rstmgr_stress_all.536226691 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 8640893590 ps |
| CPU time | 30.53 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200824 kb |
| Host | smart-9a0e0d54-a601-4ece-904a-587035f6dbdf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536226691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.536226691 |
| Directory | /workspace/23.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sw_rst.4009710588 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 541293414 ps |
| CPU time | 2.78 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:03 PM PST 24 |
| Peak memory | 200632 kb |
| Host | smart-5932e1b5-5a57-4978-ba25-2d39d6dd8307 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4009710588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.4009710588 |
| Directory | /workspace/23.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2421116916 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 92316248 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 200464 kb |
| Host | smart-3f40ecb2-4a8f-47f5-95e2-0a4fa2cc2ff7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421116916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2421116916 |
| Directory | /workspace/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/24.rstmgr_alert_test.2057092034 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 61952897 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:37:20 PM PST 24 |
| Finished | Feb 21 12:37:21 PM PST 24 |
| Peak memory | 200472 kb |
| Host | smart-d46ce8db-2dce-4170-b0e2-b229d9db5804 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057092034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2057092034 |
| Directory | /workspace/24.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2736740602 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1893120271 ps |
| CPU time | 7.2 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 217300 kb |
| Host | smart-ab395e07-b576-4e37-9bf3-a8130c91b570 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736740602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2736740602 |
| Directory | /workspace/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1389772137 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 248157764 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:36:54 PM PST 24 |
| Finished | Feb 21 12:36:56 PM PST 24 |
| Peak memory | 217348 kb |
| Host | smart-7f2def2b-0fa4-4a2a-9a78-4061e2657614 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389772137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1389772137 |
| Directory | /workspace/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/24.rstmgr_por_stretcher.3452461935 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 155862097 ps |
| CPU time | 0.81 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:36:46 PM PST 24 |
| Peak memory | 200404 kb |
| Host | smart-fab2eb82-83a1-4a2c-a083-3ca3309f3a95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452461935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3452461935 |
| Directory | /workspace/24.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/24.rstmgr_reset.1487151585 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1689796218 ps |
| CPU time | 6.11 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 200672 kb |
| Host | smart-725cb039-cb82-4063-af67-acd7cd78d830 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487151585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1487151585 |
| Directory | /workspace/24.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1120608522 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 106993860 ps |
| CPU time | 0.94 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:56 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-0794648f-29fa-472d-85ef-e3fe326d9ce6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120608522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1120608522 |
| Directory | /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/24.rstmgr_smoke.57750773 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 201905815 ps |
| CPU time | 1.28 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:57 PM PST 24 |
| Peak memory | 200708 kb |
| Host | smart-940e5920-a0ae-41d8-a2da-4d897574a73a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57750773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.57750773 |
| Directory | /workspace/24.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/24.rstmgr_stress_all.1754548571 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2086458517 ps |
| CPU time | 6.96 seconds |
| Started | Feb 21 12:37:00 PM PST 24 |
| Finished | Feb 21 12:37:08 PM PST 24 |
| Peak memory | 200680 kb |
| Host | smart-4227312c-e801-45bb-af47-f5e592f9b446 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754548571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1754548571 |
| Directory | /workspace/24.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sw_rst.2587827716 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 140987783 ps |
| CPU time | 1.7 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-5d4fc33d-79c8-4916-a6eb-c74ded3ef486 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587827716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2587827716 |
| Directory | /workspace/24.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1741110351 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 129697751 ps |
| CPU time | 0.96 seconds |
| Started | Feb 21 12:36:54 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200512 kb |
| Host | smart-b6fbcf24-50ea-4655-9a8e-c93e35aa614c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1741110351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1741110351 |
| Directory | /workspace/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/25.rstmgr_alert_test.1339527770 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 69075541 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:37:12 PM PST 24 |
| Finished | Feb 21 12:37:13 PM PST 24 |
| Peak memory | 200488 kb |
| Host | smart-9f5736ab-b26e-4d19-b9c8-649164db5dd4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339527770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1339527770 |
| Directory | /workspace/25.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1074130988 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1900963226 ps |
| CPU time | 7 seconds |
| Started | Feb 21 12:36:49 PM PST 24 |
| Finished | Feb 21 12:37:02 PM PST 24 |
| Peak memory | 218016 kb |
| Host | smart-6dbd3598-fef8-4ebe-a9be-b8397204d4bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074130988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1074130988 |
| Directory | /workspace/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1692024185 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 244290805 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 217976 kb |
| Host | smart-51b11958-15d3-4a99-8d67-9be38bc7557c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1692024185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1692024185 |
| Directory | /workspace/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/25.rstmgr_por_stretcher.2676186710 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 119647954 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:37:19 PM PST 24 |
| Finished | Feb 21 12:37:20 PM PST 24 |
| Peak memory | 200300 kb |
| Host | smart-50c9c2e7-1dbc-434d-b6a2-9d4d284abfef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2676186710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2676186710 |
| Directory | /workspace/25.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/25.rstmgr_reset.3435944517 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 990992938 ps |
| CPU time | 4.31 seconds |
| Started | Feb 21 12:37:18 PM PST 24 |
| Finished | Feb 21 12:37:22 PM PST 24 |
| Peak memory | 200680 kb |
| Host | smart-114d7f6a-9b8c-4bd2-921c-110969a38007 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435944517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3435944517 |
| Directory | /workspace/25.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.997963561 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 186244650 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 12:37:05 PM PST 24 |
| Finished | Feb 21 12:37:07 PM PST 24 |
| Peak memory | 200512 kb |
| Host | smart-e981cdac-bfc2-4605-be2f-6d43de9a983f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997963561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.997963561 |
| Directory | /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/25.rstmgr_smoke.3069317169 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 222899855 ps |
| CPU time | 1.4 seconds |
| Started | Feb 21 12:37:00 PM PST 24 |
| Finished | Feb 21 12:37:02 PM PST 24 |
| Peak memory | 200672 kb |
| Host | smart-e79a705e-c4a7-45c0-b138-c217696538a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069317169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3069317169 |
| Directory | /workspace/25.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/25.rstmgr_stress_all.1547622472 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1485964630 ps |
| CPU time | 6.5 seconds |
| Started | Feb 21 12:36:54 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 200772 kb |
| Host | smart-b314078d-4ee7-40c2-91cf-5c130ee9e58b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547622472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1547622472 |
| Directory | /workspace/25.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sw_rst.3745328521 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 467242601 ps |
| CPU time | 2.46 seconds |
| Started | Feb 21 12:37:13 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200508 kb |
| Host | smart-cf401d0e-ae78-45ba-896f-cb04ff32c630 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745328521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3745328521 |
| Directory | /workspace/25.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2015810937 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 140869969 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 12:36:51 PM PST 24 |
| Finished | Feb 21 12:36:53 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-53a7a17a-8c55-4d7f-bb67-f851a58831d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015810937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2015810937 |
| Directory | /workspace/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/26.rstmgr_alert_test.1892850107 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 78747694 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:28 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-578b238f-034d-4da8-aee0-62f0f7455a0c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892850107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1892850107 |
| Directory | /workspace/26.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.872017044 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1892587219 ps |
| CPU time | 7.21 seconds |
| Started | Feb 21 12:37:01 PM PST 24 |
| Finished | Feb 21 12:37:11 PM PST 24 |
| Peak memory | 217420 kb |
| Host | smart-b7c73933-83ae-498a-9fa3-7a0328e34584 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872017044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.872017044 |
| Directory | /workspace/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2264948114 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 244580444 ps |
| CPU time | 1.02 seconds |
| Started | Feb 21 12:37:07 PM PST 24 |
| Finished | Feb 21 12:37:10 PM PST 24 |
| Peak memory | 217860 kb |
| Host | smart-db81bac5-3a7d-437e-a592-d65d35d3a9b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264948114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2264948114 |
| Directory | /workspace/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/26.rstmgr_por_stretcher.3506133680 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 117198203 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:37:09 PM PST 24 |
| Finished | Feb 21 12:37:11 PM PST 24 |
| Peak memory | 200288 kb |
| Host | smart-586de5d2-e748-410d-aea0-7c0bc425b7f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3506133680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3506133680 |
| Directory | /workspace/26.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/26.rstmgr_reset.2268243256 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2088090895 ps |
| CPU time | 7.2 seconds |
| Started | Feb 21 12:37:10 PM PST 24 |
| Finished | Feb 21 12:37:18 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-78ace0e9-b001-4b43-9a9b-21848f292a47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268243256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2268243256 |
| Directory | /workspace/26.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.449723075 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 98039169 ps |
| CPU time | 0.94 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:57 PM PST 24 |
| Peak memory | 200540 kb |
| Host | smart-248a9683-0a6b-43d9-83fa-5e9bb8cc0165 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=449723075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.449723075 |
| Directory | /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/26.rstmgr_smoke.1628579369 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 205409375 ps |
| CPU time | 1.39 seconds |
| Started | Feb 21 12:37:09 PM PST 24 |
| Finished | Feb 21 12:37:12 PM PST 24 |
| Peak memory | 200660 kb |
| Host | smart-546ddb8a-b95a-442f-b64c-500bc72c4287 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628579369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1628579369 |
| Directory | /workspace/26.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/26.rstmgr_stress_all.387450104 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9415735353 ps |
| CPU time | 32.34 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:32 PM PST 24 |
| Peak memory | 200908 kb |
| Host | smart-702b7e2f-52b2-450c-aeaa-6c61594cb56a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387450104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.387450104 |
| Directory | /workspace/26.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sw_rst.3251435713 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 343371169 ps |
| CPU time | 2.1 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:02 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-61ac6a3f-2ad3-4b3f-97b5-a1aaa813cab9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251435713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3251435713 |
| Directory | /workspace/26.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3031300036 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 102859901 ps |
| CPU time | 0.89 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:36:54 PM PST 24 |
| Peak memory | 200432 kb |
| Host | smart-96838ddf-4206-4d47-a176-5cc219da6021 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031300036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3031300036 |
| Directory | /workspace/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/27.rstmgr_alert_test.2732850764 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 75025691 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:22 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-38680c0e-6721-4eb5-853b-dfc548d7c567 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732850764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2732850764 |
| Directory | /workspace/27.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2228751959 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1906872527 ps |
| CPU time | 7.12 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:07 PM PST 24 |
| Peak memory | 217824 kb |
| Host | smart-506668e8-0638-40a6-8f55-fe012bf69fc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228751959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2228751959 |
| Directory | /workspace/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3397946954 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 244864404 ps |
| CPU time | 0.99 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 217864 kb |
| Host | smart-0aadf035-ebfe-4dff-a0ab-a42059ebd8f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397946954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3397946954 |
| Directory | /workspace/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/27.rstmgr_por_stretcher.2640881216 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 177855586 ps |
| CPU time | 0.85 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:57 PM PST 24 |
| Peak memory | 200408 kb |
| Host | smart-4ba8bb40-4a74-4085-9398-f8558f8e4848 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640881216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2640881216 |
| Directory | /workspace/27.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/27.rstmgr_reset.1476239968 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 798997010 ps |
| CPU time | 4.04 seconds |
| Started | Feb 21 12:36:51 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200736 kb |
| Host | smart-0c5f5722-d8e0-4f8a-ab1a-40e4d642448b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476239968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1476239968 |
| Directory | /workspace/27.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3484284184 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 140981189 ps |
| CPU time | 1.02 seconds |
| Started | Feb 21 12:36:51 PM PST 24 |
| Finished | Feb 21 12:36:52 PM PST 24 |
| Peak memory | 200376 kb |
| Host | smart-e59ba0f8-257c-4b03-80de-47a3f94d228d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3484284184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3484284184 |
| Directory | /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/27.rstmgr_smoke.4184978316 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 197025830 ps |
| CPU time | 1.29 seconds |
| Started | Feb 21 12:37:01 PM PST 24 |
| Finished | Feb 21 12:37:03 PM PST 24 |
| Peak memory | 200556 kb |
| Host | smart-6edc1101-0d44-46ad-9c76-26a172855b59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184978316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.4184978316 |
| Directory | /workspace/27.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/27.rstmgr_stress_all.3020490272 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3572635537 ps |
| CPU time | 12.18 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 200920 kb |
| Host | smart-87c9938e-b91b-4fd6-8c87-06e6d1f790fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020490272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3020490272 |
| Directory | /workspace/27.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sw_rst.4111267946 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 467201050 ps |
| CPU time | 2.41 seconds |
| Started | Feb 21 12:37:00 PM PST 24 |
| Finished | Feb 21 12:37:03 PM PST 24 |
| Peak memory | 200612 kb |
| Host | smart-cb2dc8b8-ffd4-4539-85f0-f186ccc69682 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111267946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4111267946 |
| Directory | /workspace/27.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.845404730 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 164065869 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 12:36:56 PM PST 24 |
| Finished | Feb 21 12:37:00 PM PST 24 |
| Peak memory | 199900 kb |
| Host | smart-83ae8dac-e5e2-4d8b-a866-10a7c71e7b77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845404730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.845404730 |
| Directory | /workspace/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/28.rstmgr_alert_test.1038837382 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 79497045 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:37:08 PM PST 24 |
| Finished | Feb 21 12:37:10 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-22a5f665-7fc5-48a5-b312-0f52f5ad1196 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038837382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1038837382 |
| Directory | /workspace/28.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1188371709 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2369974756 ps |
| CPU time | 7.98 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:08 PM PST 24 |
| Peak memory | 218312 kb |
| Host | smart-30d95843-7b72-4608-802e-d3e966cc07a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188371709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1188371709 |
| Directory | /workspace/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.153276220 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 247106625 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:37:03 PM PST 24 |
| Finished | Feb 21 12:37:07 PM PST 24 |
| Peak memory | 217976 kb |
| Host | smart-0caea556-8fb4-424e-b2fd-2aa6fb4c42f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=153276220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.153276220 |
| Directory | /workspace/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/28.rstmgr_por_stretcher.3862167948 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 176872364 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 12:37:10 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200408 kb |
| Host | smart-3468581a-7ed9-49df-a070-f78bab4b1e9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862167948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3862167948 |
| Directory | /workspace/28.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/28.rstmgr_reset.3120616208 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1519552087 ps |
| CPU time | 5.68 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:37:02 PM PST 24 |
| Peak memory | 200660 kb |
| Host | smart-e4031a83-1fac-4a59-90ca-6fbe01856090 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120616208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3120616208 |
| Directory | /workspace/28.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3085247809 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 146733681 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:37:06 PM PST 24 |
| Finished | Feb 21 12:37:09 PM PST 24 |
| Peak memory | 200492 kb |
| Host | smart-40837ea3-2c0d-4b92-a9d7-7a7007c0b10e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085247809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3085247809 |
| Directory | /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/28.rstmgr_smoke.994562136 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 112535409 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:36:57 PM PST 24 |
| Finished | Feb 21 12:37:00 PM PST 24 |
| Peak memory | 200552 kb |
| Host | smart-d83df35d-532f-40db-a8b7-c59e5fbacf21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=994562136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.994562136 |
| Directory | /workspace/28.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/28.rstmgr_stress_all.3444737250 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 6400703056 ps |
| CPU time | 22.34 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:50 PM PST 24 |
| Peak memory | 200884 kb |
| Host | smart-7981b76f-f153-4609-82d9-365efeaf3962 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444737250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3444737250 |
| Directory | /workspace/28.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.595856949 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 73618895 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:37:04 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 200560 kb |
| Host | smart-96ad9fde-e07d-40fa-abe3-38ce0c5a794e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=595856949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.595856949 |
| Directory | /workspace/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/29.rstmgr_alert_test.4107775667 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 72450442 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-f91b2a46-b0f3-4a5d-b696-1136f42cf536 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107775667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.4107775667 |
| Directory | /workspace/29.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.4024682381 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1222824806 ps |
| CPU time | 5.08 seconds |
| Started | Feb 21 12:37:02 PM PST 24 |
| Finished | Feb 21 12:37:09 PM PST 24 |
| Peak memory | 221556 kb |
| Host | smart-950cde10-64ae-4e3d-a491-e208e81f7d8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4024682381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.4024682381 |
| Directory | /workspace/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.707778949 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 243870913 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:37:18 PM PST 24 |
| Finished | Feb 21 12:37:19 PM PST 24 |
| Peak memory | 217856 kb |
| Host | smart-897e101e-babb-4584-9440-24420f0564f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707778949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.707778949 |
| Directory | /workspace/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/29.rstmgr_por_stretcher.1916772759 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 188495544 ps |
| CPU time | 0.85 seconds |
| Started | Feb 21 12:37:12 PM PST 24 |
| Finished | Feb 21 12:37:14 PM PST 24 |
| Peak memory | 200364 kb |
| Host | smart-24d0bb45-247e-4811-83a9-4325e678d3bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1916772759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1916772759 |
| Directory | /workspace/29.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/29.rstmgr_reset.3740996878 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 844749895 ps |
| CPU time | 4.21 seconds |
| Started | Feb 21 12:37:10 PM PST 24 |
| Finished | Feb 21 12:37:15 PM PST 24 |
| Peak memory | 200664 kb |
| Host | smart-266e0034-4ee8-4fdb-9671-e88ffa3ad089 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740996878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3740996878 |
| Directory | /workspace/29.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.777127386 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 138780715 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 12:36:59 PM PST 24 |
| Finished | Feb 21 12:37:02 PM PST 24 |
| Peak memory | 200484 kb |
| Host | smart-e5f21af3-3c72-44eb-a543-9c11c37f3434 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777127386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.777127386 |
| Directory | /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/29.rstmgr_smoke.2219584085 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 120909406 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 12:37:06 PM PST 24 |
| Finished | Feb 21 12:37:10 PM PST 24 |
| Peak memory | 200752 kb |
| Host | smart-5c06d8b9-d1c1-4fd0-878e-4cd1a6d00fb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219584085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2219584085 |
| Directory | /workspace/29.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/29.rstmgr_stress_all.574776422 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1611996535 ps |
| CPU time | 5.74 seconds |
| Started | Feb 21 12:37:12 PM PST 24 |
| Finished | Feb 21 12:37:18 PM PST 24 |
| Peak memory | 200824 kb |
| Host | smart-0ce4230c-4103-4b1d-bdbf-4136d420108e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574776422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.574776422 |
| Directory | /workspace/29.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sw_rst.3172732293 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 129568931 ps |
| CPU time | 1.49 seconds |
| Started | Feb 21 12:37:13 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 200556 kb |
| Host | smart-2d67900e-b5bc-484e-b0cc-e1112ed1f3e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172732293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3172732293 |
| Directory | /workspace/29.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.121794062 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 142150412 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 12:37:00 PM PST 24 |
| Finished | Feb 21 12:37:03 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-aafe761d-7e9c-42dd-9dc2-16cabb387e0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121794062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.121794062 |
| Directory | /workspace/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/3.rstmgr_alert_test.1833324593 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 68497437 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:36:46 PM PST 24 |
| Peak memory | 200440 kb |
| Host | smart-ebae9e03-3b9c-4988-9b30-083696e5ca2d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833324593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1833324593 |
| Directory | /workspace/3.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3862276331 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1882011936 ps |
| CPU time | 6.92 seconds |
| Started | Feb 21 12:36:30 PM PST 24 |
| Finished | Feb 21 12:36:40 PM PST 24 |
| Peak memory | 218416 kb |
| Host | smart-71b93654-866e-4518-b2ba-970e859ee44e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862276331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3862276331 |
| Directory | /workspace/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3747012133 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 243607513 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 12:36:27 PM PST 24 |
| Finished | Feb 21 12:36:28 PM PST 24 |
| Peak memory | 218012 kb |
| Host | smart-88587678-83e9-4b28-890c-21b2a8eef8ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747012133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3747012133 |
| Directory | /workspace/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/3.rstmgr_por_stretcher.3176123720 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 224658253 ps |
| CPU time | 0.96 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:41 PM PST 24 |
| Peak memory | 200328 kb |
| Host | smart-bd085534-4541-42ad-aa08-609b32c85bea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176123720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3176123720 |
| Directory | /workspace/3.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/3.rstmgr_reset.2790154704 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2082347779 ps |
| CPU time | 7.95 seconds |
| Started | Feb 21 12:36:27 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-66f6ff81-2716-4437-9cb6-2ab9e117840e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790154704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2790154704 |
| Directory | /workspace/3.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sec_cm.2785560251 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 16623961581 ps |
| CPU time | 26.59 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:37:07 PM PST 24 |
| Peak memory | 218544 kb |
| Host | smart-7837ace6-7c04-4d3f-80c0-e360fa1d4996 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785560251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2785560251 |
| Directory | /workspace/3.rstmgr_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4241694373 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 161619561 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:36:32 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-c9d9525c-57e6-49aa-a111-157c6587232c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241694373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4241694373 |
| Directory | /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/3.rstmgr_smoke.1935159846 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 121861298 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 12:36:11 PM PST 24 |
| Finished | Feb 21 12:36:13 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-731745b1-6662-40e8-9cde-1e4caa8ab4a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935159846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1935159846 |
| Directory | /workspace/3.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/3.rstmgr_stress_all.1370409136 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 4103693725 ps |
| CPU time | 14.58 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:56 PM PST 24 |
| Peak memory | 200856 kb |
| Host | smart-ebd66e85-fd86-419d-b0df-317f6b9a5fbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370409136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1370409136 |
| Directory | /workspace/3.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sw_rst.1225278523 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 332913731 ps |
| CPU time | 2.25 seconds |
| Started | Feb 21 12:36:32 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 200548 kb |
| Host | smart-29ade759-8020-4d57-8c46-e41dda5623e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225278523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1225278523 |
| Directory | /workspace/3.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.133541176 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 251911761 ps |
| CPU time | 1.45 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:43 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-f6758265-85a2-4bf0-93f7-8233a87b854b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133541176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.133541176 |
| Directory | /workspace/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/30.rstmgr_alert_test.1323128715 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 58997330 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:37:14 PM PST 24 |
| Finished | Feb 21 12:37:15 PM PST 24 |
| Peak memory | 200384 kb |
| Host | smart-5b761cb8-f0ce-41cf-998f-e06457f4ae99 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323128715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1323128715 |
| Directory | /workspace/30.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2734796959 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1234294999 ps |
| CPU time | 6.03 seconds |
| Started | Feb 21 12:37:05 PM PST 24 |
| Finished | Feb 21 12:37:14 PM PST 24 |
| Peak memory | 222616 kb |
| Host | smart-88d7d2da-3a2c-4be7-8555-6769cc683f4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734796959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2734796959 |
| Directory | /workspace/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3476923474 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 244953931 ps |
| CPU time | 1.02 seconds |
| Started | Feb 21 12:37:03 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 217932 kb |
| Host | smart-cc1fe691-ef37-4d44-a628-d208b05229b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3476923474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3476923474 |
| Directory | /workspace/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/30.rstmgr_por_stretcher.1941665325 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 119610779 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200400 kb |
| Host | smart-130b6732-abee-49e1-8a6a-294c757279eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941665325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1941665325 |
| Directory | /workspace/30.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/30.rstmgr_reset.3938302082 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1529218472 ps |
| CPU time | 5.83 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:30 PM PST 24 |
| Peak memory | 200736 kb |
| Host | smart-351dc1cb-222c-4126-b63e-5b15c34a2361 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3938302082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3938302082 |
| Directory | /workspace/30.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.680108139 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 152982632 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 12:37:15 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200420 kb |
| Host | smart-3b85ea78-146b-41bb-abbd-e52446881631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680108139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.680108139 |
| Directory | /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/30.rstmgr_smoke.1188652622 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 119497257 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 12:37:15 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-4983d507-6178-4112-9417-0503524a4612 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188652622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1188652622 |
| Directory | /workspace/30.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/30.rstmgr_stress_all.1035593263 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 3218479944 ps |
| CPU time | 10.81 seconds |
| Started | Feb 21 12:37:17 PM PST 24 |
| Finished | Feb 21 12:37:28 PM PST 24 |
| Peak memory | 200904 kb |
| Host | smart-39305956-5a4f-4b55-b0dd-13115316a277 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035593263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1035593263 |
| Directory | /workspace/30.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sw_rst.1426593259 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 316446791 ps |
| CPU time | 2.01 seconds |
| Started | Feb 21 12:37:04 PM PST 24 |
| Finished | Feb 21 12:37:07 PM PST 24 |
| Peak memory | 200576 kb |
| Host | smart-4a43607c-fedd-48e5-ae99-9c98c8d8c534 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426593259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1426593259 |
| Directory | /workspace/30.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3946063895 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 127984444 ps |
| CPU time | 1 seconds |
| Started | Feb 21 12:37:13 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 200448 kb |
| Host | smart-ca6720d2-9593-42b6-a5d2-befaa1dbbb02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946063895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3946063895 |
| Directory | /workspace/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/31.rstmgr_alert_test.1750179003 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 67610898 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:37:20 PM PST 24 |
| Finished | Feb 21 12:37:21 PM PST 24 |
| Peak memory | 200332 kb |
| Host | smart-11cb7d68-da1a-445b-9370-f972e0523908 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750179003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1750179003 |
| Directory | /workspace/31.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1100313904 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1223625972 ps |
| CPU time | 5.89 seconds |
| Started | Feb 21 12:37:17 PM PST 24 |
| Finished | Feb 21 12:37:23 PM PST 24 |
| Peak memory | 217968 kb |
| Host | smart-f610457d-8d6e-4c93-8db4-d27425355f5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100313904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1100313904 |
| Directory | /workspace/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3993828738 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 244368272 ps |
| CPU time | 1.02 seconds |
| Started | Feb 21 12:37:13 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 217996 kb |
| Host | smart-76320b63-3e93-49e0-9255-ccf7df5b66e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993828738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3993828738 |
| Directory | /workspace/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/31.rstmgr_por_stretcher.3875408034 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 159987788 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 200400 kb |
| Host | smart-d65025d7-c0f9-4169-9c4b-6a4e02dbea80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875408034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3875408034 |
| Directory | /workspace/31.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/31.rstmgr_reset.1746765811 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1824368980 ps |
| CPU time | 6.14 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:30 PM PST 24 |
| Peak memory | 200708 kb |
| Host | smart-56958636-719e-4937-8a7b-e48f284d17a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746765811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1746765811 |
| Directory | /workspace/31.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.4055593344 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 102944212 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:36:58 PM PST 24 |
| Finished | Feb 21 12:37:01 PM PST 24 |
| Peak memory | 200540 kb |
| Host | smart-4307f0b0-cd4f-470e-a54b-74f9f685094b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055593344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.4055593344 |
| Directory | /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/31.rstmgr_smoke.1387245454 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 225583448 ps |
| CPU time | 1.47 seconds |
| Started | Feb 21 12:36:59 PM PST 24 |
| Finished | Feb 21 12:37:03 PM PST 24 |
| Peak memory | 200696 kb |
| Host | smart-4842bef2-72f7-451e-8755-dc8ebf23013d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387245454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1387245454 |
| Directory | /workspace/31.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/31.rstmgr_stress_all.556848153 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 220814404 ps |
| CPU time | 1.33 seconds |
| Started | Feb 21 12:37:06 PM PST 24 |
| Finished | Feb 21 12:37:10 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-59042529-0ef0-4c13-a3ad-a08ca36e0286 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556848153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.556848153 |
| Directory | /workspace/31.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sw_rst.2454418172 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 130656385 ps |
| CPU time | 1.7 seconds |
| Started | Feb 21 12:37:06 PM PST 24 |
| Finished | Feb 21 12:37:11 PM PST 24 |
| Peak memory | 200576 kb |
| Host | smart-b258af99-b96f-47e4-8101-4cb6cc4ba6eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454418172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2454418172 |
| Directory | /workspace/31.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2986424076 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 124456626 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200756 kb |
| Host | smart-cd9a407c-bfeb-4212-b4ad-e0cecf3f4c32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986424076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2986424076 |
| Directory | /workspace/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/32.rstmgr_alert_test.703141005 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 61194039 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:22 PM PST 24 |
| Peak memory | 200396 kb |
| Host | smart-a28d3f57-22b1-474e-a4fc-9bb10e51cefc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703141005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.703141005 |
| Directory | /workspace/32.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1187947856 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2355048968 ps |
| CPU time | 8.21 seconds |
| Started | Feb 21 12:37:08 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 219444 kb |
| Host | smart-893ee010-311f-4d89-b4d9-7ef6784f16f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187947856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1187947856 |
| Directory | /workspace/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.220516896 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 245958254 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 217816 kb |
| Host | smart-621fdf78-145a-4516-88b9-19712b65ee1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220516896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.220516896 |
| Directory | /workspace/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/32.rstmgr_por_stretcher.1647258230 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 163285959 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:37:19 PM PST 24 |
| Finished | Feb 21 12:37:20 PM PST 24 |
| Peak memory | 200364 kb |
| Host | smart-7050fcac-31ae-416d-8856-298a59c6bc61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647258230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1647258230 |
| Directory | /workspace/32.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/32.rstmgr_reset.453334543 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1415254988 ps |
| CPU time | 5.63 seconds |
| Started | Feb 21 12:37:14 PM PST 24 |
| Finished | Feb 21 12:37:21 PM PST 24 |
| Peak memory | 200804 kb |
| Host | smart-7def605b-719a-4495-bed6-17c041aeb889 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=453334543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.453334543 |
| Directory | /workspace/32.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3457815937 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 109993576 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:36:59 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 200484 kb |
| Host | smart-685fee71-5b2a-483d-888d-4892e79e702a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457815937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3457815937 |
| Directory | /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sw_rst.1187128036 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 142317014 ps |
| CPU time | 1.9 seconds |
| Started | Feb 21 12:36:54 PM PST 24 |
| Finished | Feb 21 12:36:56 PM PST 24 |
| Peak memory | 200612 kb |
| Host | smart-53d3df11-3a02-48dd-923a-91ae8ab83ac8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187128036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1187128036 |
| Directory | /workspace/32.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.554849214 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 102486397 ps |
| CPU time | 0.92 seconds |
| Started | Feb 21 12:36:59 PM PST 24 |
| Finished | Feb 21 12:37:03 PM PST 24 |
| Peak memory | 200580 kb |
| Host | smart-7047c365-1720-4ecd-9eac-3a607aecf505 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=554849214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.554849214 |
| Directory | /workspace/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/33.rstmgr_alert_test.2690177362 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 65909514 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:36:55 PM PST 24 |
| Finished | Feb 21 12:36:57 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-febf210f-9796-46f8-a7d8-dff0cdad9592 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690177362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2690177362 |
| Directory | /workspace/33.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1215396581 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1229583022 ps |
| CPU time | 5.14 seconds |
| Started | Feb 21 12:37:20 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 217892 kb |
| Host | smart-25571ebf-456d-48e4-bd1b-be8a9cae5af0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215396581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1215396581 |
| Directory | /workspace/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1158331356 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 244996972 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:37:03 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 217796 kb |
| Host | smart-3dc8c30d-5f2c-43a4-ab3c-4dbf93e7fce3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1158331356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1158331356 |
| Directory | /workspace/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/33.rstmgr_por_stretcher.1674687813 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 188123118 ps |
| CPU time | 0.83 seconds |
| Started | Feb 21 12:37:20 PM PST 24 |
| Finished | Feb 21 12:37:21 PM PST 24 |
| Peak memory | 200296 kb |
| Host | smart-d014372d-6caa-47d1-83f4-2438a23bf628 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674687813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1674687813 |
| Directory | /workspace/33.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/33.rstmgr_reset.3287339325 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 848374612 ps |
| CPU time | 3.84 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:28 PM PST 24 |
| Peak memory | 200708 kb |
| Host | smart-6b878239-b807-4e8c-98c4-53113487756e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287339325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3287339325 |
| Directory | /workspace/33.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1860465339 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 103654372 ps |
| CPU time | 0.93 seconds |
| Started | Feb 21 12:37:17 PM PST 24 |
| Finished | Feb 21 12:37:18 PM PST 24 |
| Peak memory | 200584 kb |
| Host | smart-4c7f2e89-1363-4682-b989-8ca94eb917da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1860465339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1860465339 |
| Directory | /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/33.rstmgr_smoke.2789535483 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 242748098 ps |
| CPU time | 1.41 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:18 PM PST 24 |
| Peak memory | 200760 kb |
| Host | smart-a904d453-555a-4d92-8e44-dca0a92001fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789535483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2789535483 |
| Directory | /workspace/33.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/33.rstmgr_stress_all.3672350911 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2972133863 ps |
| CPU time | 9.37 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:33 PM PST 24 |
| Peak memory | 200916 kb |
| Host | smart-e14a88c5-c3ba-4d92-ab9c-5954927ae2d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672350911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3672350911 |
| Directory | /workspace/33.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sw_rst.2596332730 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 147064222 ps |
| CPU time | 1.79 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:18 PM PST 24 |
| Peak memory | 200836 kb |
| Host | smart-eb8d8af3-dc9c-4795-98c5-697e8f2437d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596332730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2596332730 |
| Directory | /workspace/33.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3688970288 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 200492717 ps |
| CPU time | 1.2 seconds |
| Started | Feb 21 12:37:17 PM PST 24 |
| Finished | Feb 21 12:37:18 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-578c292a-cee7-4b2d-8548-3f12f6912759 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688970288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3688970288 |
| Directory | /workspace/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/34.rstmgr_alert_test.954703304 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 71898894 ps |
| CPU time | 0.8 seconds |
| Started | Feb 21 12:36:54 PM PST 24 |
| Finished | Feb 21 12:36:56 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-6411ebae-34b0-4042-a6cb-d4a4f65bbd35 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954703304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.954703304 |
| Directory | /workspace/34.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3795348763 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2378294599 ps |
| CPU time | 8.84 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 218368 kb |
| Host | smart-014e1a26-000a-4d81-9dd2-dc058f4c1d3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795348763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3795348763 |
| Directory | /workspace/34.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.162766928 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 244441892 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 217988 kb |
| Host | smart-f9d0e320-8347-485b-98a8-982521db7f06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162766928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.162766928 |
| Directory | /workspace/34.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/34.rstmgr_por_stretcher.2447417411 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 126286194 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200404 kb |
| Host | smart-92232dd0-f7d8-4c6e-9589-3deabad8f07d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447417411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2447417411 |
| Directory | /workspace/34.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/34.rstmgr_reset.2444938725 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1668536579 ps |
| CPU time | 6.02 seconds |
| Started | Feb 21 12:37:10 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200844 kb |
| Host | smart-f75554dd-d2da-4fc2-8463-dd2011ce2cee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444938725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2444938725 |
| Directory | /workspace/34.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1637896502 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 147160679 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-bb93d47c-b0d7-4261-b2d1-530a1a00ad1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637896502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1637896502 |
| Directory | /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/34.rstmgr_smoke.1353107473 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 127029486 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:22 PM PST 24 |
| Peak memory | 200672 kb |
| Host | smart-0d6f8d59-24a9-4254-97bc-a246b67e9918 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353107473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1353107473 |
| Directory | /workspace/34.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/34.rstmgr_stress_all.902079875 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2349957314 ps |
| CPU time | 8.6 seconds |
| Started | Feb 21 12:36:53 PM PST 24 |
| Finished | Feb 21 12:37:02 PM PST 24 |
| Peak memory | 200828 kb |
| Host | smart-0609f9ab-e633-494d-aea8-0bc6b5ec3642 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902079875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.902079875 |
| Directory | /workspace/34.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sw_rst.3686184415 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 367869276 ps |
| CPU time | 1.89 seconds |
| Started | Feb 21 12:37:07 PM PST 24 |
| Finished | Feb 21 12:37:10 PM PST 24 |
| Peak memory | 200496 kb |
| Host | smart-34c5757b-545c-4d66-8595-1c372e7aa298 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686184415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3686184415 |
| Directory | /workspace/34.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.168973976 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 227454160 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 12:37:14 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-c8305ccd-3b93-42f9-a890-3d06b6b8e804 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168973976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.168973976 |
| Directory | /workspace/34.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/35.rstmgr_alert_test.77719810 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 67413114 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200488 kb |
| Host | smart-3fa9c70c-8120-4a27-b691-c9eec40abae7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77719810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.77719810 |
| Directory | /workspace/35.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1263966806 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2347546118 ps |
| CPU time | 7.44 seconds |
| Started | Feb 21 12:37:19 PM PST 24 |
| Finished | Feb 21 12:37:27 PM PST 24 |
| Peak memory | 217816 kb |
| Host | smart-fb3249ea-a73c-4d2f-8c29-0bf4aeaf4272 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263966806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1263966806 |
| Directory | /workspace/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2357723811 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 243949456 ps |
| CPU time | 1.02 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 217960 kb |
| Host | smart-61480d28-869d-42af-9392-2f2f907ac9cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357723811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2357723811 |
| Directory | /workspace/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/35.rstmgr_por_stretcher.745596699 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 146991339 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:37:08 PM PST 24 |
| Finished | Feb 21 12:37:10 PM PST 24 |
| Peak memory | 200384 kb |
| Host | smart-2e2784cb-b7e6-4477-8f9b-78ee1c435e68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745596699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.745596699 |
| Directory | /workspace/35.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/35.rstmgr_reset.4009859346 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1495205847 ps |
| CPU time | 5.62 seconds |
| Started | Feb 21 12:37:06 PM PST 24 |
| Finished | Feb 21 12:37:14 PM PST 24 |
| Peak memory | 200764 kb |
| Host | smart-830a2a8a-ccd2-4ea7-8404-6b6f66cd7393 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4009859346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.4009859346 |
| Directory | /workspace/35.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1732875623 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 176160320 ps |
| CPU time | 1.17 seconds |
| Started | Feb 21 12:37:12 PM PST 24 |
| Finished | Feb 21 12:37:14 PM PST 24 |
| Peak memory | 200368 kb |
| Host | smart-0928ef8c-117f-410f-ae15-18f8f32583b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1732875623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1732875623 |
| Directory | /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/35.rstmgr_smoke.331405279 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 120366672 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:37:15 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 200652 kb |
| Host | smart-eb76d6e4-5b52-467d-ba17-f01a50a11838 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=331405279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.331405279 |
| Directory | /workspace/35.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/35.rstmgr_stress_all.1500725220 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 9438605898 ps |
| CPU time | 31.17 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:48 PM PST 24 |
| Peak memory | 200880 kb |
| Host | smart-a4ad58f8-4784-4b69-8e8b-6e104ca919b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500725220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1500725220 |
| Directory | /workspace/35.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sw_rst.2016540330 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 126241632 ps |
| CPU time | 1.54 seconds |
| Started | Feb 21 12:36:59 PM PST 24 |
| Finished | Feb 21 12:37:03 PM PST 24 |
| Peak memory | 200636 kb |
| Host | smart-629e29c8-7ba6-4452-8016-15292a806ad4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016540330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2016540330 |
| Directory | /workspace/35.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3055034112 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 152689061 ps |
| CPU time | 1.15 seconds |
| Started | Feb 21 12:37:26 PM PST 24 |
| Finished | Feb 21 12:37:28 PM PST 24 |
| Peak memory | 200744 kb |
| Host | smart-3249ff6d-8df8-4bb3-a9a5-008c014c0c5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055034112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3055034112 |
| Directory | /workspace/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/36.rstmgr_alert_test.218076686 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 82324309 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:37:01 PM PST 24 |
| Finished | Feb 21 12:37:05 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-227d73a6-18bb-404f-b660-ba4b7eb98d3c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218076686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.218076686 |
| Directory | /workspace/36.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3011589540 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2150962730 ps |
| CPU time | 7.48 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 217640 kb |
| Host | smart-dbbcf98b-f13c-472a-9abb-0a74af790f2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011589540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3011589540 |
| Directory | /workspace/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1063858841 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 244117453 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 217844 kb |
| Host | smart-3ecf39ab-c249-4b74-8bfb-72a908d66a30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063858841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1063858841 |
| Directory | /workspace/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/36.rstmgr_por_stretcher.986834262 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 116533161 ps |
| CPU time | 0.78 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200384 kb |
| Host | smart-34c062c0-6222-45da-bf95-dd54167c0fc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986834262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.986834262 |
| Directory | /workspace/36.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/36.rstmgr_reset.2962797907 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1013779433 ps |
| CPU time | 4.82 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:34 PM PST 24 |
| Peak memory | 200784 kb |
| Host | smart-9f485b24-6790-43d8-8d33-363c8e05855f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962797907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2962797907 |
| Directory | /workspace/36.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.482366462 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 105523494 ps |
| CPU time | 0.94 seconds |
| Started | Feb 21 12:37:26 PM PST 24 |
| Finished | Feb 21 12:37:27 PM PST 24 |
| Peak memory | 200532 kb |
| Host | smart-64ec24fe-d95d-4ed0-b973-4bfbe6b4596a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482366462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.482366462 |
| Directory | /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/36.rstmgr_smoke.3691858464 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 198951727 ps |
| CPU time | 1.36 seconds |
| Started | Feb 21 12:37:16 PM PST 24 |
| Finished | Feb 21 12:37:18 PM PST 24 |
| Peak memory | 200744 kb |
| Host | smart-f21453d9-3f70-414e-86bb-1d34fe74277f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691858464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3691858464 |
| Directory | /workspace/36.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/36.rstmgr_stress_all.3630667887 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4071819344 ps |
| CPU time | 17.33 seconds |
| Started | Feb 21 12:37:01 PM PST 24 |
| Finished | Feb 21 12:37:21 PM PST 24 |
| Peak memory | 200828 kb |
| Host | smart-68c46940-8175-4382-a73c-30f5e078c058 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630667887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3630667887 |
| Directory | /workspace/36.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sw_rst.4174948680 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 144121126 ps |
| CPU time | 1.68 seconds |
| Started | Feb 21 12:37:20 PM PST 24 |
| Finished | Feb 21 12:37:22 PM PST 24 |
| Peak memory | 200568 kb |
| Host | smart-ddc7511f-2915-411d-96ba-2c53d9935772 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174948680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4174948680 |
| Directory | /workspace/36.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3276699231 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 121370998 ps |
| CPU time | 0.91 seconds |
| Started | Feb 21 12:37:09 PM PST 24 |
| Finished | Feb 21 12:37:11 PM PST 24 |
| Peak memory | 200536 kb |
| Host | smart-e9d38f76-d116-49c9-a16f-f13f2a592aad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276699231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3276699231 |
| Directory | /workspace/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/37.rstmgr_alert_test.2806950656 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 71914288 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:37:19 PM PST 24 |
| Finished | Feb 21 12:37:20 PM PST 24 |
| Peak memory | 200432 kb |
| Host | smart-cdc6a1dd-7aa1-4d7e-b457-69576bb20609 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806950656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2806950656 |
| Directory | /workspace/37.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.4217407914 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2371718169 ps |
| CPU time | 8.31 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:37 PM PST 24 |
| Peak memory | 218356 kb |
| Host | smart-ba888c15-7aae-42c7-8bc5-ed54ac7ed3d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217407914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.4217407914 |
| Directory | /workspace/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1378932197 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 244690171 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 217996 kb |
| Host | smart-a13894f3-c9d7-4a03-91bd-3156d4ab82f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1378932197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1378932197 |
| Directory | /workspace/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/37.rstmgr_por_stretcher.861302958 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 187401587 ps |
| CPU time | 0.87 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 200404 kb |
| Host | smart-7e359251-edbf-46be-a001-be1da76aa598 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=861302958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.861302958 |
| Directory | /workspace/37.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/37.rstmgr_reset.332299428 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 891584162 ps |
| CPU time | 4.71 seconds |
| Started | Feb 21 12:37:12 PM PST 24 |
| Finished | Feb 21 12:37:17 PM PST 24 |
| Peak memory | 200804 kb |
| Host | smart-aff17f91-60fb-4302-a510-1729819f083f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332299428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.332299428 |
| Directory | /workspace/37.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2951195240 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 162453235 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:37:18 PM PST 24 |
| Finished | Feb 21 12:37:19 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-f62174fc-2f40-4a93-902a-30480f533621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951195240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2951195240 |
| Directory | /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/37.rstmgr_smoke.1858754130 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 246863720 ps |
| CPU time | 1.49 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:23 PM PST 24 |
| Peak memory | 200588 kb |
| Host | smart-16f51888-8ad0-4fb1-b3f1-f9b0ce5caa38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858754130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1858754130 |
| Directory | /workspace/37.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/37.rstmgr_stress_all.971083864 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 9164469787 ps |
| CPU time | 39.55 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:38:05 PM PST 24 |
| Peak memory | 200944 kb |
| Host | smart-55623b68-ae11-4c49-b74b-7404874fbd57 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971083864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.971083864 |
| Directory | /workspace/37.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sw_rst.1255270432 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 142529376 ps |
| CPU time | 1.77 seconds |
| Started | Feb 21 12:37:12 PM PST 24 |
| Finished | Feb 21 12:37:15 PM PST 24 |
| Peak memory | 200600 kb |
| Host | smart-c62a7824-4e4f-4fd0-8971-2eb53e6b3aac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255270432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1255270432 |
| Directory | /workspace/37.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1408009936 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 157581825 ps |
| CPU time | 0.99 seconds |
| Started | Feb 21 12:37:13 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-1e5b3908-f8b1-4845-abf2-f6a6cb62f955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408009936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1408009936 |
| Directory | /workspace/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/38.rstmgr_alert_test.1223714120 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 84075530 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:37:05 PM PST 24 |
| Finished | Feb 21 12:37:08 PM PST 24 |
| Peak memory | 200476 kb |
| Host | smart-b19bfe5d-1b91-45c9-9351-44acad612d3f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223714120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1223714120 |
| Directory | /workspace/38.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.829295225 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2363641320 ps |
| CPU time | 8.36 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:38 PM PST 24 |
| Peak memory | 218428 kb |
| Host | smart-ca074d62-5bab-4e0d-8465-7256b7086528 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829295225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.829295225 |
| Directory | /workspace/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.265139426 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 245857604 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 217916 kb |
| Host | smart-2b1d14eb-a601-49e5-9d2f-832a964857ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265139426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.265139426 |
| Directory | /workspace/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/38.rstmgr_por_stretcher.2062982378 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 103249772 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-430ceb09-6646-42bd-8c0c-2b97e47761c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062982378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2062982378 |
| Directory | /workspace/38.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/38.rstmgr_reset.4236839169 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1817714278 ps |
| CPU time | 6.08 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200732 kb |
| Host | smart-ee2640ce-3338-4cdc-9336-bf2db47a2fc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4236839169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.4236839169 |
| Directory | /workspace/38.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2188177679 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 175984022 ps |
| CPU time | 1.17 seconds |
| Started | Feb 21 12:37:32 PM PST 24 |
| Finished | Feb 21 12:37:33 PM PST 24 |
| Peak memory | 200496 kb |
| Host | smart-6e8aab90-2800-4ff2-8d4f-239ea22854b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188177679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2188177679 |
| Directory | /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/38.rstmgr_smoke.1125530940 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 118155660 ps |
| CPU time | 1.16 seconds |
| Started | Feb 21 12:37:13 PM PST 24 |
| Finished | Feb 21 12:37:14 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-9f46d647-22e1-4d76-a890-5fa2d3efc130 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125530940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1125530940 |
| Directory | /workspace/38.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/38.rstmgr_stress_all.1314082922 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4533687100 ps |
| CPU time | 15.56 seconds |
| Started | Feb 21 12:37:22 PM PST 24 |
| Finished | Feb 21 12:37:38 PM PST 24 |
| Peak memory | 200796 kb |
| Host | smart-e5c4f327-9f6c-4ce7-8f65-a8b36027dc99 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314082922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1314082922 |
| Directory | /workspace/38.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sw_rst.3081314012 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 143897522 ps |
| CPU time | 1.67 seconds |
| Started | Feb 21 12:37:19 PM PST 24 |
| Finished | Feb 21 12:37:21 PM PST 24 |
| Peak memory | 200520 kb |
| Host | smart-3a575c7a-4e0a-41d1-8248-501d3685f0cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081314012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3081314012 |
| Directory | /workspace/38.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.201888234 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 128147194 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:37:13 PM PST 24 |
| Finished | Feb 21 12:37:14 PM PST 24 |
| Peak memory | 200464 kb |
| Host | smart-9bafa03b-1539-467e-96d2-0c2d4f7b1f6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=201888234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.201888234 |
| Directory | /workspace/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/39.rstmgr_alert_test.679674203 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 92076389 ps |
| CPU time | 0.8 seconds |
| Started | Feb 21 12:37:30 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-ed2cad68-d3f7-454c-b18c-e9fc8fcf557f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679674203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.679674203 |
| Directory | /workspace/39.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3771400861 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1888011322 ps |
| CPU time | 7.44 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:39 PM PST 24 |
| Peak memory | 222492 kb |
| Host | smart-a670e55b-4891-4b20-85fc-59db321c43ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771400861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3771400861 |
| Directory | /workspace/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3229341388 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 244822488 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 217836 kb |
| Host | smart-a64f380b-e6c9-4b50-b96d-5dec8be9a641 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229341388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3229341388 |
| Directory | /workspace/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/39.rstmgr_por_stretcher.450880939 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 102401171 ps |
| CPU time | 0.78 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 200360 kb |
| Host | smart-74d3ce07-0f4c-4614-9ced-a8b89d3284c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450880939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.450880939 |
| Directory | /workspace/39.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/39.rstmgr_reset.3822650252 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 929030022 ps |
| CPU time | 4.45 seconds |
| Started | Feb 21 12:37:20 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 200816 kb |
| Host | smart-51f75d61-c3ce-46a5-87b6-8234fb22002f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3822650252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3822650252 |
| Directory | /workspace/39.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.20050014 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 175953280 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 12:37:32 PM PST 24 |
| Finished | Feb 21 12:37:34 PM PST 24 |
| Peak memory | 200496 kb |
| Host | smart-a9ef53ad-45a3-4870-8716-0a1829876267 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20050014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.20050014 |
| Directory | /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/39.rstmgr_smoke.2815211820 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 262572862 ps |
| CPU time | 1.36 seconds |
| Started | Feb 21 12:37:19 PM PST 24 |
| Finished | Feb 21 12:37:21 PM PST 24 |
| Peak memory | 200648 kb |
| Host | smart-1a29f57f-46d2-444b-96f1-652b8a91b61b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815211820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2815211820 |
| Directory | /workspace/39.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/39.rstmgr_stress_all.4102196197 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 5509578554 ps |
| CPU time | 23.27 seconds |
| Started | Feb 21 12:37:15 PM PST 24 |
| Finished | Feb 21 12:37:39 PM PST 24 |
| Peak memory | 200864 kb |
| Host | smart-8a163c1b-543a-4759-a72f-0181aaa976ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102196197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.4102196197 |
| Directory | /workspace/39.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sw_rst.628959972 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 293290809 ps |
| CPU time | 2 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 200464 kb |
| Host | smart-f1c4631f-0bc9-43cc-a691-157cbca1431c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628959972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.628959972 |
| Directory | /workspace/39.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3802398115 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 140824302 ps |
| CPU time | 0.99 seconds |
| Started | Feb 21 12:37:18 PM PST 24 |
| Finished | Feb 21 12:37:19 PM PST 24 |
| Peak memory | 200460 kb |
| Host | smart-8de5d3f8-befd-480f-a537-2ef7e273fe50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802398115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3802398115 |
| Directory | /workspace/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/4.rstmgr_alert_test.1763787427 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 70706882 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200400 kb |
| Host | smart-71ac59d0-8da7-45b6-b321-f121f603eef1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763787427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1763787427 |
| Directory | /workspace/4.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4028348817 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2364474810 ps |
| CPU time | 7.62 seconds |
| Started | Feb 21 12:36:39 PM PST 24 |
| Finished | Feb 21 12:36:49 PM PST 24 |
| Peak memory | 218544 kb |
| Host | smart-0527b1a4-6066-487d-a5aa-b96be6165ba8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028348817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4028348817 |
| Directory | /workspace/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.57046883 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 244622825 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 217968 kb |
| Host | smart-b8866af2-d622-4ec8-ac09-4b39cb184f5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57046883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.57046883 |
| Directory | /workspace/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/4.rstmgr_por_stretcher.2350654445 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 121206991 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:36:32 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 200248 kb |
| Host | smart-8e497532-8a56-47c5-a2b5-5929cbe7ed38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350654445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2350654445 |
| Directory | /workspace/4.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/4.rstmgr_reset.4119328409 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1622171476 ps |
| CPU time | 6.09 seconds |
| Started | Feb 21 12:36:21 PM PST 24 |
| Finished | Feb 21 12:36:28 PM PST 24 |
| Peak memory | 200764 kb |
| Host | smart-92790098-8f5a-4f42-a1c4-8a1b9355b1c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119328409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4119328409 |
| Directory | /workspace/4.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1058726091 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 179156525 ps |
| CPU time | 1.16 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200456 kb |
| Host | smart-d4e2416f-00c7-491c-bd86-7ca81af6b076 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058726091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1058726091 |
| Directory | /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/4.rstmgr_smoke.2810297887 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 234249280 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 12:36:30 PM PST 24 |
| Finished | Feb 21 12:36:34 PM PST 24 |
| Peak memory | 200704 kb |
| Host | smart-1329eb63-547b-4737-8cfc-7ba60a81dd0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2810297887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2810297887 |
| Directory | /workspace/4.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/4.rstmgr_stress_all.1195968202 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3497356425 ps |
| CPU time | 13.6 seconds |
| Started | Feb 21 12:36:36 PM PST 24 |
| Finished | Feb 21 12:36:51 PM PST 24 |
| Peak memory | 200800 kb |
| Host | smart-b2869dae-59d2-44bb-b300-41e07f98e97c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195968202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1195968202 |
| Directory | /workspace/4.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sw_rst.1804315076 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 132038907 ps |
| CPU time | 1.54 seconds |
| Started | Feb 21 12:36:48 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 200552 kb |
| Host | smart-e72edb1f-8a49-4976-a2b7-a3d7fb258d22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804315076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1804315076 |
| Directory | /workspace/4.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1844323011 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 178320559 ps |
| CPU time | 1.15 seconds |
| Started | Feb 21 12:36:36 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 200500 kb |
| Host | smart-069ce5ba-bbf3-451c-9e5d-c6c4bdb889c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844323011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1844323011 |
| Directory | /workspace/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/40.rstmgr_alert_test.3541637415 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 76731517 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:37:33 PM PST 24 |
| Finished | Feb 21 12:37:34 PM PST 24 |
| Peak memory | 200368 kb |
| Host | smart-8b6df2ba-a30c-44ba-a729-df04c4d11e80 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541637415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3541637415 |
| Directory | /workspace/40.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2567672707 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1218962896 ps |
| CPU time | 5.39 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 218032 kb |
| Host | smart-b91f7e85-8cdc-4449-9205-c7115cbe513c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567672707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2567672707 |
| Directory | /workspace/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1264439294 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 244621642 ps |
| CPU time | 1.11 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 217868 kb |
| Host | smart-972477cc-7e58-49fc-bf25-8770f5c1819e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264439294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1264439294 |
| Directory | /workspace/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/40.rstmgr_por_stretcher.2523932179 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 128621151 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 200272 kb |
| Host | smart-adebc0ad-9d11-4a0d-942e-8c78244eede5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523932179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2523932179 |
| Directory | /workspace/40.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/40.rstmgr_reset.3698413970 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1744677879 ps |
| CPU time | 7.16 seconds |
| Started | Feb 21 12:37:20 PM PST 24 |
| Finished | Feb 21 12:37:27 PM PST 24 |
| Peak memory | 200820 kb |
| Host | smart-6590da50-a00f-4e0b-816c-e1d9cd762b53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698413970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3698413970 |
| Directory | /workspace/40.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4275095004 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 175442219 ps |
| CPU time | 1.11 seconds |
| Started | Feb 21 12:37:17 PM PST 24 |
| Finished | Feb 21 12:37:19 PM PST 24 |
| Peak memory | 200528 kb |
| Host | smart-c4fee4bd-9255-4744-88ef-58e6e1147539 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275095004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4275095004 |
| Directory | /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/40.rstmgr_smoke.3226136836 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 192529333 ps |
| CPU time | 1.31 seconds |
| Started | Feb 21 12:37:19 PM PST 24 |
| Finished | Feb 21 12:37:21 PM PST 24 |
| Peak memory | 200704 kb |
| Host | smart-ad12afb2-bc50-4481-bf4a-8288821366bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226136836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3226136836 |
| Directory | /workspace/40.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/40.rstmgr_stress_all.3838370330 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 7824422162 ps |
| CPU time | 25.23 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:54 PM PST 24 |
| Peak memory | 200860 kb |
| Host | smart-abf0fff1-e3f3-4761-922e-ba8db02f1686 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838370330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3838370330 |
| Directory | /workspace/40.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sw_rst.392734416 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 534032197 ps |
| CPU time | 2.49 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:30 PM PST 24 |
| Peak memory | 200564 kb |
| Host | smart-e6441193-c8d6-4561-a8b0-5f8dd01f8bac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392734416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.392734416 |
| Directory | /workspace/40.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3568991157 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 169398278 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 200680 kb |
| Host | smart-bda1ff72-0a44-4183-89d6-4ff6646639ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3568991157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3568991157 |
| Directory | /workspace/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/41.rstmgr_alert_test.3007142315 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 70905767 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:37:34 PM PST 24 |
| Finished | Feb 21 12:37:35 PM PST 24 |
| Peak memory | 200480 kb |
| Host | smart-1fb9a469-3691-44ef-b33b-49b11cdda067 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007142315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3007142315 |
| Directory | /workspace/41.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.375276538 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 244579515 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:22 PM PST 24 |
| Peak memory | 217960 kb |
| Host | smart-a35d3344-15d9-479a-99c0-e391f3129d65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375276538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.375276538 |
| Directory | /workspace/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/41.rstmgr_por_stretcher.391353288 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 190500577 ps |
| CPU time | 0.83 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 200360 kb |
| Host | smart-1fe691de-024e-4258-b0fe-d0ba6f76ee39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391353288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.391353288 |
| Directory | /workspace/41.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/41.rstmgr_reset.2824558881 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1641665997 ps |
| CPU time | 5.88 seconds |
| Started | Feb 21 12:37:36 PM PST 24 |
| Finished | Feb 21 12:37:42 PM PST 24 |
| Peak memory | 200752 kb |
| Host | smart-9af6dbbd-c24a-4e5d-b826-0c277a69b95e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2824558881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2824558881 |
| Directory | /workspace/41.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2253827768 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 155118180 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:23 PM PST 24 |
| Peak memory | 200404 kb |
| Host | smart-a841a18a-d6ad-418b-93c3-de3be16e284e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253827768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2253827768 |
| Directory | /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/41.rstmgr_smoke.1535854745 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 231620588 ps |
| CPU time | 1.35 seconds |
| Started | Feb 21 12:37:34 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 200716 kb |
| Host | smart-22bd55f6-8c58-442f-ba0f-07be8ad74500 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535854745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1535854745 |
| Directory | /workspace/41.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/41.rstmgr_stress_all.2572709771 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6069493447 ps |
| CPU time | 25.72 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:55 PM PST 24 |
| Peak memory | 200888 kb |
| Host | smart-311c92ed-125d-4370-af99-fd62fc22027e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572709771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2572709771 |
| Directory | /workspace/41.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sw_rst.538039531 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 327451564 ps |
| CPU time | 2.09 seconds |
| Started | Feb 21 12:37:36 PM PST 24 |
| Finished | Feb 21 12:37:38 PM PST 24 |
| Peak memory | 200564 kb |
| Host | smart-41ca8dc0-7090-4e07-828e-2977e13cf043 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=538039531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.538039531 |
| Directory | /workspace/41.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3449521708 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 159026666 ps |
| CPU time | 1.12 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 200496 kb |
| Host | smart-43d0760f-2ef2-4e0e-a81e-14c1d4d5e3cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449521708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3449521708 |
| Directory | /workspace/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/42.rstmgr_alert_test.3248480545 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 93065121 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 199840 kb |
| Host | smart-ded175ed-043a-45f9-9bc1-be9d7a4a5fba |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248480545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3248480545 |
| Directory | /workspace/42.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.537779937 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 244119406 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 217864 kb |
| Host | smart-df66bdca-c50e-4049-8e11-9cfa957fe444 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537779937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.537779937 |
| Directory | /workspace/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/42.rstmgr_por_stretcher.2259873669 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 204242194 ps |
| CPU time | 0.85 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 200348 kb |
| Host | smart-431937e3-dad8-47a4-a01d-65f8b9995a58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259873669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2259873669 |
| Directory | /workspace/42.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/42.rstmgr_reset.1022885078 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 825494179 ps |
| CPU time | 4.29 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:33 PM PST 24 |
| Peak memory | 200804 kb |
| Host | smart-245bc179-b5e4-41a4-9e7e-b58dee3c615f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022885078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1022885078 |
| Directory | /workspace/42.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1166605024 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 94705159 ps |
| CPU time | 0.93 seconds |
| Started | Feb 21 12:37:11 PM PST 24 |
| Finished | Feb 21 12:37:12 PM PST 24 |
| Peak memory | 200404 kb |
| Host | smart-4bb9ec32-d567-475b-9f4e-62bc3433439d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166605024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1166605024 |
| Directory | /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/42.rstmgr_smoke.1134706551 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 248488883 ps |
| CPU time | 1.38 seconds |
| Started | Feb 21 12:37:34 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 200748 kb |
| Host | smart-281db1ba-1b91-4a28-92a3-1cd3d12cb8d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1134706551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1134706551 |
| Directory | /workspace/42.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/42.rstmgr_stress_all.4234105805 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4451100195 ps |
| CPU time | 17.95 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:50 PM PST 24 |
| Peak memory | 200860 kb |
| Host | smart-40a3f11c-e29e-4b54-af4b-8484436ca48f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234105805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4234105805 |
| Directory | /workspace/42.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sw_rst.940782392 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 413909330 ps |
| CPU time | 2.18 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:27 PM PST 24 |
| Peak memory | 200488 kb |
| Host | smart-1f967ea1-ee96-4e66-a6f5-c4c5aba87fdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=940782392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.940782392 |
| Directory | /workspace/42.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1191954363 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 78830988 ps |
| CPU time | 0.78 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:25 PM PST 24 |
| Peak memory | 200484 kb |
| Host | smart-4264717a-a87d-43e6-a0a2-70dd3a6ed6bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191954363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1191954363 |
| Directory | /workspace/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/43.rstmgr_alert_test.405139559 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 63235275 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:37:38 PM PST 24 |
| Finished | Feb 21 12:37:39 PM PST 24 |
| Peak memory | 200484 kb |
| Host | smart-24a09d8d-81e1-4343-be42-754a347bdd98 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405139559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.405139559 |
| Directory | /workspace/43.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2815253188 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2384542716 ps |
| CPU time | 8.08 seconds |
| Started | Feb 21 12:37:35 PM PST 24 |
| Finished | Feb 21 12:37:43 PM PST 24 |
| Peak memory | 219260 kb |
| Host | smart-9f0ac763-1095-4f97-841f-3075edf78e1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815253188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2815253188 |
| Directory | /workspace/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3687584296 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 243152874 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 217920 kb |
| Host | smart-8b38dc25-3b64-420f-9ae7-2fd820b61454 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687584296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3687584296 |
| Directory | /workspace/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/43.rstmgr_por_stretcher.2902884344 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 159863275 ps |
| CPU time | 0.78 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:32 PM PST 24 |
| Peak memory | 200356 kb |
| Host | smart-7f9d729a-73b2-497f-a7a0-98fcd258c735 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902884344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2902884344 |
| Directory | /workspace/43.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/43.rstmgr_reset.412783916 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1148740840 ps |
| CPU time | 4.73 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:33 PM PST 24 |
| Peak memory | 200740 kb |
| Host | smart-fccbc753-3ae9-4b8a-90e3-f329575aa45c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412783916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.412783916 |
| Directory | /workspace/43.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3433670715 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 152326041 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:30 PM PST 24 |
| Peak memory | 199880 kb |
| Host | smart-af9d4298-cb0a-4e3e-8f29-8d881dc31319 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433670715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3433670715 |
| Directory | /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/43.rstmgr_smoke.2040619190 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 262108759 ps |
| CPU time | 1.45 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 200592 kb |
| Host | smart-ad0b7c7d-0c9e-4681-b188-bd997ea9b6c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040619190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2040619190 |
| Directory | /workspace/43.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/43.rstmgr_stress_all.2737642520 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 8060974938 ps |
| CPU time | 29.62 seconds |
| Started | Feb 21 12:37:18 PM PST 24 |
| Finished | Feb 21 12:37:48 PM PST 24 |
| Peak memory | 200756 kb |
| Host | smart-595d0a75-df21-4ad3-9295-a30b6c4cfa34 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737642520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2737642520 |
| Directory | /workspace/43.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sw_rst.33294325 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 309828228 ps |
| CPU time | 2.11 seconds |
| Started | Feb 21 12:37:35 PM PST 24 |
| Finished | Feb 21 12:37:38 PM PST 24 |
| Peak memory | 200468 kb |
| Host | smart-a4a3d62a-a567-4c4b-a082-b03d277ddd04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33294325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.33294325 |
| Directory | /workspace/43.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.49661803 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 93495588 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:22 PM PST 24 |
| Peak memory | 200392 kb |
| Host | smart-e88257b1-2b82-4dd4-8617-4f778aac1231 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49661803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.49661803 |
| Directory | /workspace/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/44.rstmgr_alert_test.3898894789 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 67703314 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 200476 kb |
| Host | smart-092ad7d6-6ab5-4601-aae5-b4fd343c3daf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898894789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3898894789 |
| Directory | /workspace/44.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2687646572 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1232702722 ps |
| CPU time | 5.1 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 217444 kb |
| Host | smart-d6eeaa96-5461-492c-b489-2f91b1caa565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687646572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2687646572 |
| Directory | /workspace/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2597599354 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 244856874 ps |
| CPU time | 1.18 seconds |
| Started | Feb 21 12:37:09 PM PST 24 |
| Finished | Feb 21 12:37:11 PM PST 24 |
| Peak memory | 217900 kb |
| Host | smart-86ee2346-d192-462f-9f8d-b5f22541468f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597599354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2597599354 |
| Directory | /workspace/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/44.rstmgr_por_stretcher.2608292835 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 165030816 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:37:11 PM PST 24 |
| Finished | Feb 21 12:37:13 PM PST 24 |
| Peak memory | 200280 kb |
| Host | smart-957285a1-d111-4e48-963d-7a58b01b84a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608292835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2608292835 |
| Directory | /workspace/44.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/44.rstmgr_reset.68144090 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1250503400 ps |
| CPU time | 5.07 seconds |
| Started | Feb 21 12:37:35 PM PST 24 |
| Finished | Feb 21 12:37:40 PM PST 24 |
| Peak memory | 200612 kb |
| Host | smart-2fdb2cd4-b5ba-4bc6-8f9f-6d20e4a3436b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68144090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.68144090 |
| Directory | /workspace/44.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.900681994 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 103952868 ps |
| CPU time | 0.95 seconds |
| Started | Feb 21 12:37:08 PM PST 24 |
| Finished | Feb 21 12:37:10 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-05a30103-abc5-4980-a0a6-b6c1024ff95e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900681994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.900681994 |
| Directory | /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/44.rstmgr_smoke.2892154615 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 121912636 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 12:37:14 PM PST 24 |
| Finished | Feb 21 12:37:16 PM PST 24 |
| Peak memory | 200672 kb |
| Host | smart-89b61430-135a-4cc3-9c73-3332febe6511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892154615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2892154615 |
| Directory | /workspace/44.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/44.rstmgr_stress_all.2322606972 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 6611334324 ps |
| CPU time | 22.53 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:51 PM PST 24 |
| Peak memory | 200144 kb |
| Host | smart-4d0c46f8-f131-46d3-a3c3-368b7f4c300b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322606972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2322606972 |
| Directory | /workspace/44.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sw_rst.3243798619 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 362900657 ps |
| CPU time | 2.29 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200536 kb |
| Host | smart-ca8cf405-52c3-46b3-9b34-a0d8c5eb5cc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3243798619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3243798619 |
| Directory | /workspace/44.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.376834202 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 75997308 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:37:04 PM PST 24 |
| Finished | Feb 21 12:37:06 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-aad9ac3b-6309-4343-9e47-1b4df97e8c88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376834202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.376834202 |
| Directory | /workspace/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/45.rstmgr_alert_test.204437929 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 71454630 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:22 PM PST 24 |
| Peak memory | 200440 kb |
| Host | smart-ba9eb247-d19d-451e-bec8-a8be92983eb5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204437929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.204437929 |
| Directory | /workspace/45.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2454885145 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1871676015 ps |
| CPU time | 6.71 seconds |
| Started | Feb 21 12:37:22 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 217316 kb |
| Host | smart-134c1d44-0443-4a7e-bd84-f4c1d917d6d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454885145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2454885145 |
| Directory | /workspace/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2028944336 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 244401358 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 218212 kb |
| Host | smart-70892c02-9a24-44a4-baf6-80e117d1d2c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028944336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2028944336 |
| Directory | /workspace/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/45.rstmgr_por_stretcher.1986695876 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 151157181 ps |
| CPU time | 0.81 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:30 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-d921a0ab-8a3a-46f1-ad38-4003e4e451dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986695876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1986695876 |
| Directory | /workspace/45.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/45.rstmgr_reset.2059303865 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 957613380 ps |
| CPU time | 4.84 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:34 PM PST 24 |
| Peak memory | 200848 kb |
| Host | smart-960c4741-6642-4eda-90e3-f9d1858e629f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059303865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2059303865 |
| Directory | /workspace/45.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1760116748 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 106733893 ps |
| CPU time | 0.95 seconds |
| Started | Feb 21 12:37:24 PM PST 24 |
| Finished | Feb 21 12:37:26 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-9fdbe171-8ee1-4cad-8daa-977315355157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760116748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1760116748 |
| Directory | /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/45.rstmgr_smoke.3553180674 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 198827541 ps |
| CPU time | 1.34 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:37:28 PM PST 24 |
| Peak memory | 200748 kb |
| Host | smart-1154e1b3-93a9-4824-92e8-829dcde0ddb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553180674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3553180674 |
| Directory | /workspace/45.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/45.rstmgr_stress_all.1188535084 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4615779045 ps |
| CPU time | 19.83 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:51 PM PST 24 |
| Peak memory | 200948 kb |
| Host | smart-7ab98c86-caae-4aca-bbcd-fc2436180240 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188535084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1188535084 |
| Directory | /workspace/45.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sw_rst.951263688 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 352657198 ps |
| CPU time | 1.88 seconds |
| Started | Feb 21 12:37:30 PM PST 24 |
| Finished | Feb 21 12:37:32 PM PST 24 |
| Peak memory | 200592 kb |
| Host | smart-a3bb67a7-f8cc-4f39-825f-c13bdc3b57e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951263688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.951263688 |
| Directory | /workspace/45.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.156243657 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 196657400 ps |
| CPU time | 1.19 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:23 PM PST 24 |
| Peak memory | 200488 kb |
| Host | smart-44a24c01-f91c-4608-b0b0-212aa25d9361 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156243657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.156243657 |
| Directory | /workspace/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/46.rstmgr_alert_test.2886605999 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 66651511 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 200492 kb |
| Host | smart-03cfaffc-a4d6-4937-beca-8012ac73e6dd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886605999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2886605999 |
| Directory | /workspace/46.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4141337751 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2154792336 ps |
| CPU time | 8.14 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:35 PM PST 24 |
| Peak memory | 222744 kb |
| Host | smart-2726a46c-539b-4e29-be8d-505a613c6280 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141337751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4141337751 |
| Directory | /workspace/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.75584393 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 244822675 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 217860 kb |
| Host | smart-eab172da-89e5-43f3-9354-69c6f935380b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75584393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.75584393 |
| Directory | /workspace/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/46.rstmgr_por_stretcher.300772773 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 197867609 ps |
| CPU time | 0.81 seconds |
| Started | Feb 21 12:37:23 PM PST 24 |
| Finished | Feb 21 12:37:24 PM PST 24 |
| Peak memory | 200384 kb |
| Host | smart-42634336-9a40-4f0f-bf63-0054e184ea7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300772773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.300772773 |
| Directory | /workspace/46.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/46.rstmgr_reset.2798850814 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1475203834 ps |
| CPU time | 5.09 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-6f72d680-10b2-4359-b5a1-769ad6c74825 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798850814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2798850814 |
| Directory | /workspace/46.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2941216440 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 139123484 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200412 kb |
| Host | smart-f61b08d6-2b53-4bf7-8f5e-0c0c84549b04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941216440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2941216440 |
| Directory | /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/46.rstmgr_smoke.123218972 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 256281277 ps |
| CPU time | 1.47 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200800 kb |
| Host | smart-78d97843-988a-495d-9d10-d0401cc9fc40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123218972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.123218972 |
| Directory | /workspace/46.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/46.rstmgr_stress_all.1384209032 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3902100144 ps |
| CPU time | 15.89 seconds |
| Started | Feb 21 12:37:33 PM PST 24 |
| Finished | Feb 21 12:37:49 PM PST 24 |
| Peak memory | 200884 kb |
| Host | smart-d68537dc-9e92-488f-9e51-c53a5b8af54c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384209032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1384209032 |
| Directory | /workspace/46.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sw_rst.677003912 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 403235183 ps |
| CPU time | 2.37 seconds |
| Started | Feb 21 12:37:30 PM PST 24 |
| Finished | Feb 21 12:37:33 PM PST 24 |
| Peak memory | 200564 kb |
| Host | smart-86eb33ff-e618-42ae-af61-f787ec9f4b41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677003912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.677003912 |
| Directory | /workspace/46.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3595563017 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 216110499 ps |
| CPU time | 1.3 seconds |
| Started | Feb 21 12:37:32 PM PST 24 |
| Finished | Feb 21 12:37:34 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-f522eee3-5317-4285-a5c1-846f6dc94e09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595563017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3595563017 |
| Directory | /workspace/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/47.rstmgr_alert_test.3037214163 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 62648082 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:22 PM PST 24 |
| Peak memory | 200464 kb |
| Host | smart-0e282942-6193-4e51-949d-46054e6c0f70 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037214163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3037214163 |
| Directory | /workspace/47.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2417840029 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1229960508 ps |
| CPU time | 5.4 seconds |
| Started | Feb 21 12:37:30 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 222036 kb |
| Host | smart-389194ce-0045-4c35-addb-8f343c0efd0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417840029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2417840029 |
| Directory | /workspace/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3947122311 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 243901759 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 217740 kb |
| Host | smart-de8a4808-0259-4e20-a6b1-b2bf6ee7b79d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947122311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3947122311 |
| Directory | /workspace/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/47.rstmgr_por_stretcher.2018700569 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 165622434 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:37:34 PM PST 24 |
| Finished | Feb 21 12:37:35 PM PST 24 |
| Peak memory | 200364 kb |
| Host | smart-2420e6c0-35b8-403c-ab95-1dec42fc3ec3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018700569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2018700569 |
| Directory | /workspace/47.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/47.rstmgr_reset.3345215594 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 721831486 ps |
| CPU time | 3.48 seconds |
| Started | Feb 21 12:37:30 PM PST 24 |
| Finished | Feb 21 12:37:34 PM PST 24 |
| Peak memory | 200796 kb |
| Host | smart-7f12cde2-e9a6-4960-a105-b272376950d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3345215594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3345215594 |
| Directory | /workspace/47.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.858572022 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 150124507 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:30 PM PST 24 |
| Peak memory | 200468 kb |
| Host | smart-5c88e2dd-c696-4ce5-9688-8ee19454d0db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858572022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.858572022 |
| Directory | /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/47.rstmgr_smoke.2417713827 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 262653529 ps |
| CPU time | 1.43 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200780 kb |
| Host | smart-575c92ad-9ec6-494d-9721-a71acc958979 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417713827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2417713827 |
| Directory | /workspace/47.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/47.rstmgr_stress_all.188120228 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 415692113 ps |
| CPU time | 1.97 seconds |
| Started | Feb 21 12:37:21 PM PST 24 |
| Finished | Feb 21 12:37:24 PM PST 24 |
| Peak memory | 200592 kb |
| Host | smart-68f2bf16-3f47-46a2-ba24-924a5b80b9e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188120228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.188120228 |
| Directory | /workspace/47.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sw_rst.1382069850 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 132701760 ps |
| CPU time | 1.49 seconds |
| Started | Feb 21 12:37:19 PM PST 24 |
| Finished | Feb 21 12:37:20 PM PST 24 |
| Peak memory | 200632 kb |
| Host | smart-4a406d88-6d29-4ada-8588-071fa6ba1874 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382069850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1382069850 |
| Directory | /workspace/47.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.338781498 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 121779644 ps |
| CPU time | 0.91 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:28 PM PST 24 |
| Peak memory | 200496 kb |
| Host | smart-80673929-466c-4e83-8f78-93a2f255621c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338781498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.338781498 |
| Directory | /workspace/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/48.rstmgr_alert_test.2188921309 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 69989656 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 199560 kb |
| Host | smart-4f394f18-d780-45d7-8cd9-2299a6c67c0b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188921309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2188921309 |
| Directory | /workspace/48.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2715048187 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1892095124 ps |
| CPU time | 6.62 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 217308 kb |
| Host | smart-ab2cd2f0-53a1-492d-b1a1-e7f4522e1ee3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715048187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2715048187 |
| Directory | /workspace/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3244536693 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 244484857 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:30 PM PST 24 |
| Peak memory | 217856 kb |
| Host | smart-1e7e4546-e483-4fa8-bd71-32ede0c6c4cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244536693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3244536693 |
| Directory | /workspace/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/48.rstmgr_por_stretcher.2829657935 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 205860329 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:37:27 PM PST 24 |
| Finished | Feb 21 12:37:29 PM PST 24 |
| Peak memory | 200172 kb |
| Host | smart-e27647e1-675d-4f3a-8212-80fbf9cb2ea9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2829657935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2829657935 |
| Directory | /workspace/48.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/48.rstmgr_reset.2961231134 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1210086286 ps |
| CPU time | 4.52 seconds |
| Started | Feb 21 12:37:32 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-5986cbbc-5499-4d02-a6c9-097dc7cdb8a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961231134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2961231134 |
| Directory | /workspace/48.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2892724785 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 146445266 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:32 PM PST 24 |
| Peak memory | 200540 kb |
| Host | smart-a996560e-6e27-4aa6-a4a5-f85a2733cd0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892724785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2892724785 |
| Directory | /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/48.rstmgr_smoke.2935257399 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 121578480 ps |
| CPU time | 1.1 seconds |
| Started | Feb 21 12:37:20 PM PST 24 |
| Finished | Feb 21 12:37:21 PM PST 24 |
| Peak memory | 200584 kb |
| Host | smart-d0969972-b257-423f-a505-d6381ee9be8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935257399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2935257399 |
| Directory | /workspace/48.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/48.rstmgr_stress_all.3714780982 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4585063518 ps |
| CPU time | 14.84 seconds |
| Started | Feb 21 12:37:32 PM PST 24 |
| Finished | Feb 21 12:37:47 PM PST 24 |
| Peak memory | 200900 kb |
| Host | smart-4bfb5958-ddbe-4019-8717-0a07f4109bb6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714780982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3714780982 |
| Directory | /workspace/48.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sw_rst.2677068540 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 352955259 ps |
| CPU time | 2.09 seconds |
| Started | Feb 21 12:37:28 PM PST 24 |
| Finished | Feb 21 12:37:31 PM PST 24 |
| Peak memory | 200480 kb |
| Host | smart-9c64c2b1-8a82-447e-8537-e9a3817bf082 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677068540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2677068540 |
| Directory | /workspace/48.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2133061061 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 151693346 ps |
| CPU time | 1 seconds |
| Started | Feb 21 12:37:18 PM PST 24 |
| Finished | Feb 21 12:37:19 PM PST 24 |
| Peak memory | 200292 kb |
| Host | smart-13fb8e2f-8bc3-4e5c-8da0-f9101d232988 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2133061061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2133061061 |
| Directory | /workspace/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/49.rstmgr_alert_test.1778634546 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 89733875 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:37:30 PM PST 24 |
| Finished | Feb 21 12:37:32 PM PST 24 |
| Peak memory | 200476 kb |
| Host | smart-66ea227e-025e-4ae8-93c0-75fd83106e55 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778634546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1778634546 |
| Directory | /workspace/49.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3815380669 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1226250578 ps |
| CPU time | 5.21 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:37 PM PST 24 |
| Peak memory | 222584 kb |
| Host | smart-e7155845-c23a-45e2-ba34-2673da9da3ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815380669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3815380669 |
| Directory | /workspace/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1464795525 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 243912664 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:33 PM PST 24 |
| Peak memory | 218008 kb |
| Host | smart-5f90d0bb-5265-4cb3-8376-4e72890f4d6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464795525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1464795525 |
| Directory | /workspace/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/49.rstmgr_por_stretcher.4124393741 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 160788627 ps |
| CPU time | 0.8 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:37:27 PM PST 24 |
| Peak memory | 200372 kb |
| Host | smart-0b8feff1-ecc2-4365-9da0-5ae8aeba7402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4124393741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.4124393741 |
| Directory | /workspace/49.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/49.rstmgr_reset.3018715705 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1186864562 ps |
| CPU time | 4.34 seconds |
| Started | Feb 21 12:37:29 PM PST 24 |
| Finished | Feb 21 12:37:34 PM PST 24 |
| Peak memory | 200752 kb |
| Host | smart-ee4a95b2-94d2-4294-9bd1-eba13b8debd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018715705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3018715705 |
| Directory | /workspace/49.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.61502916 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 110239253 ps |
| CPU time | 0.94 seconds |
| Started | Feb 21 12:37:32 PM PST 24 |
| Finished | Feb 21 12:37:34 PM PST 24 |
| Peak memory | 200492 kb |
| Host | smart-24b00dc2-b6fb-468b-968e-8c0e3a4ff938 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61502916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.61502916 |
| Directory | /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/49.rstmgr_smoke.2525276380 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 247833365 ps |
| CPU time | 1.4 seconds |
| Started | Feb 21 12:37:33 PM PST 24 |
| Finished | Feb 21 12:37:34 PM PST 24 |
| Peak memory | 200740 kb |
| Host | smart-c40e5fed-34a2-40c9-873c-ef4a4364d888 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525276380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2525276380 |
| Directory | /workspace/49.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/49.rstmgr_stress_all.2415976580 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 12343343496 ps |
| CPU time | 38.8 seconds |
| Started | Feb 21 12:37:25 PM PST 24 |
| Finished | Feb 21 12:38:04 PM PST 24 |
| Peak memory | 200884 kb |
| Host | smart-e55bd176-5ccd-4312-b9ed-11096c1efc50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415976580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2415976580 |
| Directory | /workspace/49.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sw_rst.4084356608 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 113609546 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 12:37:31 PM PST 24 |
| Finished | Feb 21 12:37:32 PM PST 24 |
| Peak memory | 200548 kb |
| Host | smart-2b56984b-e678-46ab-821f-add5e3e8718c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084356608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.4084356608 |
| Directory | /workspace/49.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1272076931 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 194317066 ps |
| CPU time | 1.16 seconds |
| Started | Feb 21 12:37:34 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 200500 kb |
| Host | smart-f4ed2011-0e8d-42fa-b642-aba99efe6682 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272076931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1272076931 |
| Directory | /workspace/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/5.rstmgr_alert_test.1480218987 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 76781517 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:36:41 PM PST 24 |
| Peak memory | 200304 kb |
| Host | smart-42c9f4c4-51cd-4a5c-a621-35375dcecae4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480218987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1480218987 |
| Directory | /workspace/5.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1498760999 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1894044389 ps |
| CPU time | 7.24 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:43 PM PST 24 |
| Peak memory | 217336 kb |
| Host | smart-c9fab495-b278-4a56-bb6a-28869ba02301 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498760999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1498760999 |
| Directory | /workspace/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1986864792 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 245607010 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:36:39 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 217880 kb |
| Host | smart-288b465e-f534-4cf2-be89-3a77997867ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986864792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1986864792 |
| Directory | /workspace/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/5.rstmgr_por_stretcher.105652952 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 178899534 ps |
| CPU time | 0.92 seconds |
| Started | Feb 21 12:36:33 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-62a079fb-4214-44e4-9746-ec65b2bf598d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105652952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.105652952 |
| Directory | /workspace/5.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/5.rstmgr_reset.154543330 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1485922288 ps |
| CPU time | 5.86 seconds |
| Started | Feb 21 12:36:27 PM PST 24 |
| Finished | Feb 21 12:36:34 PM PST 24 |
| Peak memory | 200732 kb |
| Host | smart-f89c608b-268b-4a97-b288-f38b02c26aa4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154543330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.154543330 |
| Directory | /workspace/5.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3465260182 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 109898532 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:36:23 PM PST 24 |
| Finished | Feb 21 12:36:25 PM PST 24 |
| Peak memory | 200400 kb |
| Host | smart-bc2197a0-816b-45bc-8248-16c6e27889fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465260182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3465260182 |
| Directory | /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/5.rstmgr_smoke.2511165798 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 124732616 ps |
| CPU time | 1.2 seconds |
| Started | Feb 21 12:36:39 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200552 kb |
| Host | smart-56f50f47-9caa-448f-960c-395c6cad60f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511165798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2511165798 |
| Directory | /workspace/5.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/5.rstmgr_stress_all.1089076243 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 6401289613 ps |
| CPU time | 21.88 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:37:07 PM PST 24 |
| Peak memory | 200948 kb |
| Host | smart-53c1d789-1d75-4177-8876-617c2bab68bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089076243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1089076243 |
| Directory | /workspace/5.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sw_rst.1994805096 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 389908066 ps |
| CPU time | 2.05 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:40 PM PST 24 |
| Peak memory | 200524 kb |
| Host | smart-fa5eb7a4-1e49-4c79-aeba-706ac8c4c8ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994805096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1994805096 |
| Directory | /workspace/5.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3438732006 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 117696968 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:36:39 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200572 kb |
| Host | smart-8532f793-d7cd-4346-9475-09935cb13fd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438732006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3438732006 |
| Directory | /workspace/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/6.rstmgr_alert_test.632641324 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 67024779 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 200484 kb |
| Host | smart-113f24d1-492e-4ac4-b47d-ecb051486b9d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632641324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.632641324 |
| Directory | /workspace/6.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3037015355 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1225079829 ps |
| CPU time | 5.46 seconds |
| Started | Feb 21 12:37:01 PM PST 24 |
| Finished | Feb 21 12:37:09 PM PST 24 |
| Peak memory | 222644 kb |
| Host | smart-c30bcb20-36f7-4bc5-a437-e9122cbcaac1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3037015355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3037015355 |
| Directory | /workspace/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2724028091 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 244107778 ps |
| CPU time | 1 seconds |
| Started | Feb 21 12:36:39 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 217764 kb |
| Host | smart-1760a90f-06c6-4165-bdaf-9830bc19f6b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724028091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2724028091 |
| Directory | /workspace/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/6.rstmgr_por_stretcher.2440285123 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 215116277 ps |
| CPU time | 0.95 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 200328 kb |
| Host | smart-31cccc86-8fc4-4c11-bd83-db99246bdfa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440285123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2440285123 |
| Directory | /workspace/6.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/6.rstmgr_reset.2673696618 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2197304540 ps |
| CPU time | 7.66 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:36:48 PM PST 24 |
| Peak memory | 200880 kb |
| Host | smart-7234572d-3b8a-457d-b8e6-c4aed0563797 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673696618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2673696618 |
| Directory | /workspace/6.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1334135297 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 110276443 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:36:32 PM PST 24 |
| Finished | Feb 21 12:36:34 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-59fe4058-f5d1-4fc2-87d6-13824c0fb874 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334135297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1334135297 |
| Directory | /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/6.rstmgr_smoke.1611251115 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 262705642 ps |
| CPU time | 1.58 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:43 PM PST 24 |
| Peak memory | 200644 kb |
| Host | smart-27e411ed-1016-4499-9d07-e21e4e92d2db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611251115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1611251115 |
| Directory | /workspace/6.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/6.rstmgr_stress_all.3194879955 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1825744009 ps |
| CPU time | 8.49 seconds |
| Started | Feb 21 12:36:46 PM PST 24 |
| Finished | Feb 21 12:36:55 PM PST 24 |
| Peak memory | 200708 kb |
| Host | smart-c7550654-a3d9-4bb3-b5bf-97c2350147dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194879955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3194879955 |
| Directory | /workspace/6.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sw_rst.1879749832 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 400703240 ps |
| CPU time | 2.34 seconds |
| Started | Feb 21 12:36:41 PM PST 24 |
| Finished | Feb 21 12:36:44 PM PST 24 |
| Peak memory | 200596 kb |
| Host | smart-a2a52477-ebe3-4680-90e4-4a897e29740f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879749832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1879749832 |
| Directory | /workspace/6.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1557240112 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 106692559 ps |
| CPU time | 0.87 seconds |
| Started | Feb 21 12:36:49 PM PST 24 |
| Finished | Feb 21 12:36:51 PM PST 24 |
| Peak memory | 200572 kb |
| Host | smart-934b71ea-4cb0-4cba-8df2-ea9a6002e89a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1557240112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1557240112 |
| Directory | /workspace/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/7.rstmgr_alert_test.2947414554 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 81955738 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:36:27 PM PST 24 |
| Finished | Feb 21 12:36:28 PM PST 24 |
| Peak memory | 200384 kb |
| Host | smart-8b5832ca-095f-4db1-8def-31726e8a17e7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947414554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2947414554 |
| Directory | /workspace/7.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2072337544 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1230782428 ps |
| CPU time | 5.19 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:43 PM PST 24 |
| Peak memory | 218468 kb |
| Host | smart-719d7711-2287-4aab-816d-f5eb592bfecb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072337544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2072337544 |
| Directory | /workspace/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3058873056 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 244992602 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:37 PM PST 24 |
| Peak memory | 217880 kb |
| Host | smart-d5aa1f20-fa6f-4155-8725-3469963f06ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3058873056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3058873056 |
| Directory | /workspace/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/7.rstmgr_por_stretcher.3329548923 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 199873588 ps |
| CPU time | 0.9 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 200628 kb |
| Host | smart-deeef6fa-541f-4235-a710-b27700e12c53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329548923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3329548923 |
| Directory | /workspace/7.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/7.rstmgr_reset.714202020 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1756676875 ps |
| CPU time | 6.45 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200696 kb |
| Host | smart-01a06dcc-f06a-4942-87d8-f15f775ff509 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714202020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.714202020 |
| Directory | /workspace/7.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3421793412 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 181121006 ps |
| CPU time | 1.14 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 200512 kb |
| Host | smart-06404d04-fc38-4012-abc9-919b46d4a837 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421793412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3421793412 |
| Directory | /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/7.rstmgr_smoke.1060594697 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 189995773 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:48 PM PST 24 |
| Peak memory | 200688 kb |
| Host | smart-5fa1a2eb-53c2-4ae2-95da-ca8452755897 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060594697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1060594697 |
| Directory | /workspace/7.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/7.rstmgr_stress_all.3488295953 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 15823195308 ps |
| CPU time | 49.83 seconds |
| Started | Feb 21 12:36:46 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 200880 kb |
| Host | smart-094a2cd8-914a-414a-b3d9-37bfcfeecf27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488295953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3488295953 |
| Directory | /workspace/7.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sw_rst.1399131018 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 330410644 ps |
| CPU time | 2.1 seconds |
| Started | Feb 21 12:36:33 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 200396 kb |
| Host | smart-73c401b4-6d1d-401d-88a1-218ec3aed84d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399131018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1399131018 |
| Directory | /workspace/7.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1562716691 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 77691334 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:36:38 PM PST 24 |
| Finished | Feb 21 12:36:40 PM PST 24 |
| Peak memory | 200572 kb |
| Host | smart-e1b93722-736b-4acf-996b-2682f045a65f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562716691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1562716691 |
| Directory | /workspace/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/8.rstmgr_alert_test.1040425847 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 76657416 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:36:43 PM PST 24 |
| Finished | Feb 21 12:36:46 PM PST 24 |
| Peak memory | 200500 kb |
| Host | smart-0e7d9d67-d114-4d94-9a63-764e43943e33 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040425847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1040425847 |
| Directory | /workspace/8.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2448049036 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2365296075 ps |
| CPU time | 8.41 seconds |
| Started | Feb 21 12:36:44 PM PST 24 |
| Finished | Feb 21 12:36:54 PM PST 24 |
| Peak memory | 218304 kb |
| Host | smart-0a42d36f-7562-4719-8fb1-9f1cfa6b9f85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448049036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2448049036 |
| Directory | /workspace/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2836767564 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 245194304 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:36:28 PM PST 24 |
| Finished | Feb 21 12:36:29 PM PST 24 |
| Peak memory | 217848 kb |
| Host | smart-35c156a7-4f6f-437b-a271-296f3e797634 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836767564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2836767564 |
| Directory | /workspace/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/8.rstmgr_por_stretcher.2671000264 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 166400966 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 12:36:37 PM PST 24 |
| Finished | Feb 21 12:36:39 PM PST 24 |
| Peak memory | 200292 kb |
| Host | smart-d65ace7c-1a8b-4851-a9ea-32a768b0e9f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671000264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2671000264 |
| Directory | /workspace/8.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/8.rstmgr_reset.2924026811 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1756256363 ps |
| CPU time | 5.99 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200736 kb |
| Host | smart-ec907cdb-92bf-446f-9731-6ae26ce7ee95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924026811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2924026811 |
| Directory | /workspace/8.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.447189901 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 142913604 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:36:40 PM PST 24 |
| Finished | Feb 21 12:36:43 PM PST 24 |
| Peak memory | 200396 kb |
| Host | smart-943a59f3-cad0-454f-babd-9e93eca116ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447189901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.447189901 |
| Directory | /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/8.rstmgr_smoke.265746105 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 193414592 ps |
| CPU time | 1.37 seconds |
| Started | Feb 21 12:36:33 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 200732 kb |
| Host | smart-46b7dfae-c219-4150-a235-2acc8cd07004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265746105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.265746105 |
| Directory | /workspace/8.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/8.rstmgr_stress_all.1186056962 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 13253717025 ps |
| CPU time | 47.94 seconds |
| Started | Feb 21 12:36:47 PM PST 24 |
| Finished | Feb 21 12:37:36 PM PST 24 |
| Peak memory | 200804 kb |
| Host | smart-d30d7d47-335b-403b-bcf9-9cbe0aeb4f5a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186056962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1186056962 |
| Directory | /workspace/8.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sw_rst.2573319875 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 336415821 ps |
| CPU time | 2.16 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 200476 kb |
| Host | smart-eabf5c20-3b94-485e-9f8e-19fe9226c6f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573319875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2573319875 |
| Directory | /workspace/8.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2838438957 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 144367049 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:36:36 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-a494c1d5-d207-4c25-a742-a74b03cf059f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838438957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2838438957 |
| Directory | /workspace/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspace/coverage/default/9.rstmgr_alert_test.456327581 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 62070554 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:36:32 PM PST 24 |
| Finished | Feb 21 12:36:35 PM PST 24 |
| Peak memory | 200428 kb |
| Host | smart-b3794a72-dd0d-44ba-a816-9ac8d7995208 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456327581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.456327581 |
| Directory | /workspace/9.rstmgr_alert_test/latest |
| Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2836937969 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1237296815 ps |
| CPU time | 5.73 seconds |
| Started | Feb 21 12:36:30 PM PST 24 |
| Finished | Feb 21 12:36:38 PM PST 24 |
| Peak memory | 222516 kb |
| Host | smart-a509bbdb-aff5-4cb1-82d5-9f42fad428cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836937969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2836937969 |
| Directory | /workspace/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.159522503 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 244285423 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 217888 kb |
| Host | smart-3b1883dd-5916-4985-97e6-bde79b6bacb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159522503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.159522503 |
| Directory | /workspace/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspace/coverage/default/9.rstmgr_por_stretcher.3953636504 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 199360339 ps |
| CPU time | 0.88 seconds |
| Started | Feb 21 12:36:51 PM PST 24 |
| Finished | Feb 21 12:36:52 PM PST 24 |
| Peak memory | 200348 kb |
| Host | smart-5108dffc-d965-4e46-bd20-8e1874a433f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953636504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3953636504 |
| Directory | /workspace/9.rstmgr_por_stretcher/latest |
| Test location | /workspace/coverage/default/9.rstmgr_reset.111451082 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 723533237 ps |
| CPU time | 3.78 seconds |
| Started | Feb 21 12:36:45 PM PST 24 |
| Finished | Feb 21 12:36:50 PM PST 24 |
| Peak memory | 200736 kb |
| Host | smart-bb710e3e-2042-434c-8a7f-b8e29d7a1123 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111451082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.111451082 |
| Directory | /workspace/9.rstmgr_reset/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3386401906 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 150321894 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:36:51 PM PST 24 |
| Finished | Feb 21 12:36:52 PM PST 24 |
| Peak memory | 200476 kb |
| Host | smart-70ba0753-d6ac-4e60-b74b-ae853538cd3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386401906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3386401906 |
| Directory | /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspace/coverage/default/9.rstmgr_smoke.3404661899 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 197944059 ps |
| CPU time | 1.34 seconds |
| Started | Feb 21 12:36:39 PM PST 24 |
| Finished | Feb 21 12:36:42 PM PST 24 |
| Peak memory | 200660 kb |
| Host | smart-b7de57b1-b4c7-4496-8f65-46eaeeba8372 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404661899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3404661899 |
| Directory | /workspace/9.rstmgr_smoke/latest |
| Test location | /workspace/coverage/default/9.rstmgr_stress_all.1902820400 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 20976986422 ps |
| CPU time | 74.58 seconds |
| Started | Feb 21 12:36:46 PM PST 24 |
| Finished | Feb 21 12:38:01 PM PST 24 |
| Peak memory | 200812 kb |
| Host | smart-b4b9a07a-c3be-4b46-8058-472f59f8bda1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902820400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1902820400 |
| Directory | /workspace/9.rstmgr_stress_all/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sw_rst.479712163 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 321914355 ps |
| CPU time | 2.18 seconds |
| Started | Feb 21 12:36:35 PM PST 24 |
| Finished | Feb 21 12:36:39 PM PST 24 |
| Peak memory | 200524 kb |
| Host | smart-5ef6a7bf-0dd2-42c6-92d1-9bfab2ef5f04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=479712163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.479712163 |
| Directory | /workspace/9.rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3153926526 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 165704805 ps |
| CPU time | 1.3 seconds |
| Started | Feb 21 12:36:34 PM PST 24 |
| Finished | Feb 21 12:36:36 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-1fb0a6ea-fdfb-405c-b73d-8aeb11d18f56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153926526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3153926526 |
| Directory | /workspace/9.rstmgr_sw_rst_reset_race/latest |
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