Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8188

1

T1

3

T3

29

T4

16

auto[1]

11341

1

T1

1

T3

36

T4

85

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6007	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6615	1			T1	1		T2	1		T3	26
reset_info_cp[2]	3010	1			T3	8		T4	16		T8	18
reset_info_cp[4]	3924	1			T3	14		T4	19		T8	20
reset_info_cp[8]	124	1			T4	1		T9	1		T23	3
reset_info_cp[16]	119	1			T39	1		T66	1		T68	1
reset_info_cp[32]	100	1			T7	1		T8	1		T10	1
reset_info_cp[64]	133	1			T8	1		T9	2		T12	2
reset_info_cp[128]	117	1			T8	1		T57	1		T66	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3088	1			T3	9		T4	16		T8	13
reset_info_cp[1]	auto[1]	2907	1			T3	16		T4	10		T8	13
reset_info_cp[2]	auto[0]	968	1			T3	3		T9	19		T73	3
reset_info_cp[2]	auto[1]	2042	1			T3	5		T4	16		T8	18
reset_info_cp[4]	auto[0]	1395	1			T3	5		T9	21		T73	3
reset_info_cp[4]	auto[1]	2529	1			T3	9		T4	19		T8	20
reset_info_cp[8]	auto[0]	47	1			T9	1		T68	1		T129	1
reset_info_cp[8]	auto[1]	77	1			T4	1		T23	3		T61	1
reset_info_cp[16]	auto[0]	48	1			T84	1		T130	1		T91	1
reset_info_cp[16]	auto[1]	71	1			T39	1		T66	1		T68	1
reset_info_cp[32]	auto[0]	32	1			T7	1		T12	1		T65	1
reset_info_cp[32]	auto[1]	68	1			T8	1		T10	1		T23	2
reset_info_cp[64]	auto[0]	44	1			T9	1		T12	2		T57	2
reset_info_cp[64]	auto[1]	89	1			T8	1		T9	1		T39	1
reset_info_cp[128]	auto[0]	41	1			T57	1		T68	2		T84	1
reset_info_cp[128]	auto[1]	76	1			T8	1		T66	1		T68	1