Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T543 /workspace/coverage/default/11.rstmgr_alert_test.674460737 Feb 29 12:46:54 PM PST 24 Feb 29 12:46:55 PM PST 24 72816608 ps
T544 /workspace/coverage/default/31.rstmgr_smoke.1158796971 Feb 29 12:47:15 PM PST 24 Feb 29 12:47:17 PM PST 24 247246982 ps
T545 /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2236449181 Feb 29 12:47:51 PM PST 24 Feb 29 12:47:52 PM PST 24 218456124 ps
T546 /workspace/coverage/default/31.rstmgr_stress_all.1754563054 Feb 29 12:47:29 PM PST 24 Feb 29 12:48:02 PM PST 24 8819103769 ps
T547 /workspace/coverage/default/17.rstmgr_stress_all.2197046746 Feb 29 12:47:07 PM PST 24 Feb 29 12:47:28 PM PST 24 6272416707 ps
T43 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3822601439 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:13 PM PST 24 63403974 ps
T44 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.658617467 Feb 29 12:44:07 PM PST 24 Feb 29 12:44:09 PM PST 24 208244550 ps
T45 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2282438049 Feb 29 12:43:58 PM PST 24 Feb 29 12:44:01 PM PST 24 465288196 ps
T46 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3567664469 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:11 PM PST 24 59824167 ps
T95 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2529973229 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:14 PM PST 24 75785578 ps
T96 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1652904044 Feb 29 12:44:18 PM PST 24 Feb 29 12:44:20 PM PST 24 76451679 ps
T47 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3601468199 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:13 PM PST 24 413947389 ps
T48 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1601232486 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:14 PM PST 24 124911038 ps
T49 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2902512544 Feb 29 12:44:00 PM PST 24 Feb 29 12:44:04 PM PST 24 195576439 ps
T50 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2084903455 Feb 29 12:44:04 PM PST 24 Feb 29 12:44:06 PM PST 24 172500207 ps
T104 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2100346807 Feb 29 12:43:48 PM PST 24 Feb 29 12:43:54 PM PST 24 1164921182 ps
T97 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2921361669 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:15 PM PST 24 225612923 ps
T54 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2161598672 Feb 29 12:44:01 PM PST 24 Feb 29 12:44:04 PM PST 24 416742340 ps
T74 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3717095229 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:13 PM PST 24 113150463 ps
T75 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3655137895 Feb 29 12:44:16 PM PST 24 Feb 29 12:44:18 PM PST 24 115074284 ps
T548 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1232221766 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:11 PM PST 24 61498815 ps
T76 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2696223764 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:17 PM PST 24 418494045 ps
T79 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1322045833 Feb 29 12:43:44 PM PST 24 Feb 29 12:43:46 PM PST 24 497576465 ps
T77 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3747618088 Feb 29 12:44:06 PM PST 24 Feb 29 12:44:08 PM PST 24 225747395 ps
T78 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.603452605 Feb 29 12:44:08 PM PST 24 Feb 29 12:44:10 PM PST 24 231028959 ps
T549 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4125144171 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:11 PM PST 24 109457976 ps
T80 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1691247371 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:14 PM PST 24 167112334 ps
T550 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3335408090 Feb 29 12:44:02 PM PST 24 Feb 29 12:44:03 PM PST 24 86957902 ps
T551 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2021376225 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:12 PM PST 24 217490860 ps
T98 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.835309980 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:11 PM PST 24 82275394 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3979055248 Feb 29 12:44:06 PM PST 24 Feb 29 12:44:09 PM PST 24 223827380 ps
T105 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4105599185 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:27 PM PST 24 383292053 ps
T106 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1559157096 Feb 29 12:44:21 PM PST 24 Feb 29 12:44:23 PM PST 24 122034681 ps
T114 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3077610553 Feb 29 12:44:05 PM PST 24 Feb 29 12:44:09 PM PST 24 458942026 ps
T553 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2973146600 Feb 29 12:44:19 PM PST 24 Feb 29 12:44:21 PM PST 24 131158768 ps
T108 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1424997238 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:28 PM PST 24 904422379 ps
T123 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3503369146 Feb 29 12:44:09 PM PST 24 Feb 29 12:44:11 PM PST 24 429864303 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3031830184 Feb 29 12:44:00 PM PST 24 Feb 29 12:44:02 PM PST 24 100065682 ps
T99 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2853734936 Feb 29 12:44:06 PM PST 24 Feb 29 12:44:08 PM PST 24 100204654 ps
T111 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4162996841 Feb 29 12:44:17 PM PST 24 Feb 29 12:44:22 PM PST 24 938279450 ps
T555 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.782584493 Feb 29 12:44:00 PM PST 24 Feb 29 12:44:03 PM PST 24 276778949 ps
T556 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1369067188 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:13 PM PST 24 182942116 ps
T557 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3038796803 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:13 PM PST 24 118236897 ps
T558 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1455032699 Feb 29 12:43:57 PM PST 24 Feb 29 12:43:58 PM PST 24 141647405 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3268705613 Feb 29 12:44:08 PM PST 24 Feb 29 12:44:11 PM PST 24 266537898 ps
T100 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2983180761 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:12 PM PST 24 245158025 ps
T109 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3336188214 Feb 29 12:44:06 PM PST 24 Feb 29 12:44:10 PM PST 24 937118479 ps
T560 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2757868238 Feb 29 12:44:08 PM PST 24 Feb 29 12:44:11 PM PST 24 465789844 ps
T561 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1756431132 Feb 29 12:44:06 PM PST 24 Feb 29 12:44:08 PM PST 24 111121551 ps
T101 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1422102225 Feb 29 12:44:04 PM PST 24 Feb 29 12:44:06 PM PST 24 61155638 ps
T562 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.393865655 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:13 PM PST 24 129485949 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1219243614 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:12 PM PST 24 127648299 ps
T102 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2396457442 Feb 29 12:43:50 PM PST 24 Feb 29 12:43:51 PM PST 24 85150680 ps
T124 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1852146454 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:15 PM PST 24 1739343888 ps
T125 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3394995863 Feb 29 12:44:16 PM PST 24 Feb 29 12:44:19 PM PST 24 500745528 ps
T103 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4132001508 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:13 PM PST 24 215404111 ps
T107 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1710977630 Feb 29 12:44:15 PM PST 24 Feb 29 12:44:18 PM PST 24 200857453 ps
T564 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1194983535 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:14 PM PST 24 182702841 ps
T565 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2760679272 Feb 29 12:44:09 PM PST 24 Feb 29 12:44:11 PM PST 24 165416496 ps
T126 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.640816904 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:15 PM PST 24 493417680 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1104362511 Feb 29 12:44:06 PM PST 24 Feb 29 12:44:10 PM PST 24 272996600 ps
T567 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.659293701 Feb 29 12:43:48 PM PST 24 Feb 29 12:43:49 PM PST 24 139525583 ps
T112 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2081677521 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:16 PM PST 24 1824961992 ps
T568 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1362104978 Feb 29 12:44:18 PM PST 24 Feb 29 12:44:21 PM PST 24 283243655 ps
T569 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4248436545 Feb 29 12:44:08 PM PST 24 Feb 29 12:44:10 PM PST 24 198238104 ps
T570 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.660310033 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:12 PM PST 24 147781868 ps
T571 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.114714498 Feb 29 12:44:00 PM PST 24 Feb 29 12:44:02 PM PST 24 195905538 ps
T572 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1856819386 Feb 29 12:44:18 PM PST 24 Feb 29 12:44:20 PM PST 24 245784332 ps
T573 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.864614891 Feb 29 12:44:17 PM PST 24 Feb 29 12:44:20 PM PST 24 250189856 ps
T574 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.169199663 Feb 29 12:44:30 PM PST 24 Feb 29 12:44:32 PM PST 24 411199727 ps
T110 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.846974842 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:13 PM PST 24 481291561 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1814322390 Feb 29 12:43:49 PM PST 24 Feb 29 12:43:52 PM PST 24 246372589 ps
T576 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1163880069 Feb 29 12:44:24 PM PST 24 Feb 29 12:44:25 PM PST 24 61736573 ps
T577 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1782182529 Feb 29 12:44:01 PM PST 24 Feb 29 12:44:03 PM PST 24 143281056 ps
T578 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.110792685 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:27 PM PST 24 124118462 ps
T579 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1173919596 Feb 29 12:43:57 PM PST 24 Feb 29 12:43:59 PM PST 24 214955721 ps
T127 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3558692939 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:14 PM PST 24 501836217 ps
T113 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.563908614 Feb 29 12:44:09 PM PST 24 Feb 29 12:44:12 PM PST 24 928490775 ps
T580 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1927441928 Feb 29 12:44:05 PM PST 24 Feb 29 12:44:08 PM PST 24 134541703 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2330812511 Feb 29 12:44:14 PM PST 24 Feb 29 12:44:15 PM PST 24 67781664 ps
T582 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.566709549 Feb 29 12:44:18 PM PST 24 Feb 29 12:44:20 PM PST 24 211275853 ps
T583 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4206946621 Feb 29 12:44:18 PM PST 24 Feb 29 12:44:20 PM PST 24 136324879 ps
T584 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.433207568 Feb 29 12:44:03 PM PST 24 Feb 29 12:44:05 PM PST 24 197649200 ps
T585 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3109560161 Feb 29 12:44:08 PM PST 24 Feb 29 12:44:09 PM PST 24 72369116 ps
T586 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.298634135 Feb 29 12:44:06 PM PST 24 Feb 29 12:44:09 PM PST 24 201736994 ps
T587 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4084946521 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:12 PM PST 24 123617832 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3066161966 Feb 29 12:44:00 PM PST 24 Feb 29 12:44:04 PM PST 24 305031016 ps
T589 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3210711028 Feb 29 12:43:49 PM PST 24 Feb 29 12:43:51 PM PST 24 149453932 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1370892219 Feb 29 12:44:15 PM PST 24 Feb 29 12:44:16 PM PST 24 75653130 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1242125039 Feb 29 12:44:02 PM PST 24 Feb 29 12:44:04 PM PST 24 136109684 ps
T592 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.389018074 Feb 29 12:44:05 PM PST 24 Feb 29 12:44:09 PM PST 24 220280987 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3452002397 Feb 29 12:43:53 PM PST 24 Feb 29 12:43:57 PM PST 24 922078249 ps
T594 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2112323244 Feb 29 12:43:57 PM PST 24 Feb 29 12:43:58 PM PST 24 81077896 ps
T595 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2879219997 Feb 29 12:44:20 PM PST 24 Feb 29 12:44:21 PM PST 24 64283459 ps
T596 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3668418117 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:14 PM PST 24 329666438 ps
T597 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1949453584 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:14 PM PST 24 82108669 ps
T598 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1131471104 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:16 PM PST 24 1037339975 ps
T599 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2270534835 Feb 29 12:44:21 PM PST 24 Feb 29 12:44:22 PM PST 24 82491447 ps
T600 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4004902537 Feb 29 12:43:51 PM PST 24 Feb 29 12:43:52 PM PST 24 94231822 ps
T601 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2644667286 Feb 29 12:44:18 PM PST 24 Feb 29 12:44:21 PM PST 24 438784906 ps
T602 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.615801203 Feb 29 12:44:06 PM PST 24 Feb 29 12:44:08 PM PST 24 133868110 ps
T603 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2688661794 Feb 29 12:44:02 PM PST 24 Feb 29 12:44:04 PM PST 24 223151302 ps
T604 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.552571462 Feb 29 12:44:07 PM PST 24 Feb 29 12:44:12 PM PST 24 552917695 ps
T605 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4139017973 Feb 29 12:43:58 PM PST 24 Feb 29 12:44:01 PM PST 24 245784280 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3951803875 Feb 29 12:43:53 PM PST 24 Feb 29 12:43:55 PM PST 24 513239112 ps
T607 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3893135529 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:12 PM PST 24 77532588 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2458460522 Feb 29 12:44:04 PM PST 24 Feb 29 12:44:06 PM PST 24 80029037 ps
T609 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2029024315 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:14 PM PST 24 59815882 ps
T610 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.955070886 Feb 29 12:44:09 PM PST 24 Feb 29 12:44:15 PM PST 24 1175992265 ps
T611 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1450539015 Feb 29 12:44:24 PM PST 24 Feb 29 12:44:26 PM PST 24 128439936 ps
T612 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.610622747 Feb 29 12:44:36 PM PST 24 Feb 29 12:44:39 PM PST 24 289329869 ps
T613 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4122839960 Feb 29 12:44:17 PM PST 24 Feb 29 12:44:20 PM PST 24 121910269 ps
T88 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1399479436 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:26 PM PST 24 63907921 ps
T614 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.935358831 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:13 PM PST 24 121152186 ps
T615 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4022060446 Feb 29 12:44:04 PM PST 24 Feb 29 12:44:04 PM PST 24 99943460 ps
T616 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1712887493 Feb 29 12:44:05 PM PST 24 Feb 29 12:44:07 PM PST 24 118980985 ps
T617 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3823291278 Feb 29 12:44:04 PM PST 24 Feb 29 12:44:05 PM PST 24 71411334 ps
T618 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.39901564 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:12 PM PST 24 64899415 ps
T619 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3655074132 Feb 29 12:44:34 PM PST 24 Feb 29 12:44:35 PM PST 24 57952379 ps
T620 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2743008226 Feb 29 12:44:05 PM PST 24 Feb 29 12:44:08 PM PST 24 312613673 ps

Test location /workspace/coverage/default/26.rstmgr_stress_all.2764331527
Short name T9
Test name
Test status
Simulation time 7063955135 ps
CPU time 23.24 seconds
Started Feb 29 12:47:23 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 200420 kb
Host smart-4306d6ed-034e-4ab1-afdf-3afd8b7479d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764331527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2764331527
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1673663177
Short name T6
Test name
Test status
Simulation time 139078164 ps
CPU time 1.73 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 200136 kb
Host smart-8325c470-8f86-4136-bb45-b9e3e753f9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673663177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1673663177
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2902512544
Short name T49
Test name
Test status
Simulation time 195576439 ps
CPU time 2.9 seconds
Started Feb 29 12:44:00 PM PST 24
Finished Feb 29 12:44:04 PM PST 24
Peak memory 200120 kb
Host smart-41e7444a-1667-42c1-aed2-4aad99694e01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902512544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2902512544
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1465090653
Short name T51
Test name
Test status
Simulation time 18231801610 ps
CPU time 28.05 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:47:14 PM PST 24
Peak memory 222064 kb
Host smart-c6ccfc7a-bf91-4acb-8013-bb7660d23412
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465090653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1465090653
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4272857065
Short name T8
Test name
Test status
Simulation time 1884466773 ps
CPU time 7.16 seconds
Started Feb 29 12:46:52 PM PST 24
Finished Feb 29 12:47:00 PM PST 24
Peak memory 218548 kb
Host smart-f0e3f6e8-db43-4895-91a1-e76dd30e9c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272857065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4272857065
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3601468199
Short name T47
Test name
Test status
Simulation time 413947389 ps
CPU time 1.93 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 200172 kb
Host smart-dfd00046-f66d-4d33-a8ea-f5e039cd50f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601468199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3601468199
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1053263002
Short name T25
Test name
Test status
Simulation time 2173844113 ps
CPU time 7.87 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:54 PM PST 24
Peak memory 222076 kb
Host smart-1e362dd6-37b1-46fa-96e8-443c895a1fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053263002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1053263002
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.889733765
Short name T84
Test name
Test status
Simulation time 11537087648 ps
CPU time 44.84 seconds
Started Feb 29 12:47:38 PM PST 24
Finished Feb 29 12:48:23 PM PST 24
Peak memory 200424 kb
Host smart-90bc2f89-8ace-4cfb-bd73-c59479b7884d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889733765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.889733765
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.316371669
Short name T156
Test name
Test status
Simulation time 104106828 ps
CPU time 0.99 seconds
Started Feb 29 12:47:08 PM PST 24
Finished Feb 29 12:47:09 PM PST 24
Peak memory 200020 kb
Host smart-a655f9ce-6d1e-4b0c-99c2-9d871763a242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316371669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.316371669
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1999634900
Short name T142
Test name
Test status
Simulation time 82582518 ps
CPU time 0.79 seconds
Started Feb 29 12:46:44 PM PST 24
Finished Feb 29 12:46:45 PM PST 24
Peak memory 199876 kb
Host smart-da2c9081-5bfa-46a1-8933-26def09bab23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999634900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1999634900
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3503369146
Short name T123
Test name
Test status
Simulation time 429864303 ps
CPU time 1.91 seconds
Started Feb 29 12:44:09 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 200104 kb
Host smart-a25c476a-1ed8-4a50-9faf-39a6860e3487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503369146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3503369146
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3587102701
Short name T7
Test name
Test status
Simulation time 161330859 ps
CPU time 1.19 seconds
Started Feb 29 12:46:33 PM PST 24
Finished Feb 29 12:46:34 PM PST 24
Peak memory 200108 kb
Host smart-b7570e87-e9f1-44ca-9921-711cefc943da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587102701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3587102701
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3558692939
Short name T127
Test name
Test status
Simulation time 501836217 ps
CPU time 1.8 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 200072 kb
Host smart-6f8b9b16-f681-445b-842b-6b79158adcb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558692939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3558692939
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1899958291
Short name T23
Test name
Test status
Simulation time 1231405999 ps
CPU time 5.84 seconds
Started Feb 29 12:47:01 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 222080 kb
Host smart-dda3ab90-6dc1-4ae4-940e-c610498ac260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899958291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1899958291
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1559157096
Short name T106
Test name
Test status
Simulation time 122034681 ps
CPU time 1.63 seconds
Started Feb 29 12:44:21 PM PST 24
Finished Feb 29 12:44:23 PM PST 24
Peak memory 200160 kb
Host smart-886c496d-7a9e-4c1f-9603-79b4811d51f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559157096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1559157096
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.563908614
Short name T113
Test name
Test status
Simulation time 928490775 ps
CPU time 2.94 seconds
Started Feb 29 12:44:09 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 200140 kb
Host smart-7982f6fe-54ab-4806-8645-b570f1943469
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563908614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
563908614
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.835309980
Short name T98
Test name
Test status
Simulation time 82275394 ps
CPU time 0.79 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 199776 kb
Host smart-c6b0b743-0cb3-4882-adb1-f1b2251db444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835309980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.835309980
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2616538322
Short name T18
Test name
Test status
Simulation time 230983961 ps
CPU time 0.97 seconds
Started Feb 29 12:46:56 PM PST 24
Finished Feb 29 12:46:57 PM PST 24
Peak memory 199756 kb
Host smart-6bb8f628-85c2-4194-9a2d-6a1d51e54eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616538322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2616538322
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2081677521
Short name T112
Test name
Test status
Simulation time 1824961992 ps
CPU time 4.66 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 200160 kb
Host smart-feecab97-a01d-49c6-85c0-fc63aee3d94b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081677521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2081677521
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3979055248
Short name T552
Test name
Test status
Simulation time 223827380 ps
CPU time 1.54 seconds
Started Feb 29 12:44:06 PM PST 24
Finished Feb 29 12:44:09 PM PST 24
Peak memory 200156 kb
Host smart-1455f167-cb62-403f-8c53-09f1ff841886
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979055248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
979055248
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3268705613
Short name T559
Test name
Test status
Simulation time 266537898 ps
CPU time 3.09 seconds
Started Feb 29 12:44:08 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 200172 kb
Host smart-411780da-6cd5-472b-987f-a8d4a0fa9625
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268705613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
268705613
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4004902537
Short name T600
Test name
Test status
Simulation time 94231822 ps
CPU time 0.87 seconds
Started Feb 29 12:43:51 PM PST 24
Finished Feb 29 12:43:52 PM PST 24
Peak memory 199904 kb
Host smart-933a5a17-ba5e-49fc-8f2c-56ff3e14788f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004902537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.4
004902537
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1455032699
Short name T558
Test name
Test status
Simulation time 141647405 ps
CPU time 1.1 seconds
Started Feb 29 12:43:57 PM PST 24
Finished Feb 29 12:43:58 PM PST 24
Peak memory 199900 kb
Host smart-4ab73010-2844-4c09-9c6d-aabc3e5dd526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455032699 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1455032699
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2112323244
Short name T594
Test name
Test status
Simulation time 81077896 ps
CPU time 0.82 seconds
Started Feb 29 12:43:57 PM PST 24
Finished Feb 29 12:43:58 PM PST 24
Peak memory 199848 kb
Host smart-6f412480-3110-4e99-ba7a-ef0db45116a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112323244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2112323244
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1814322390
Short name T575
Test name
Test status
Simulation time 246372589 ps
CPU time 1.55 seconds
Started Feb 29 12:43:49 PM PST 24
Finished Feb 29 12:43:52 PM PST 24
Peak memory 200160 kb
Host smart-6687cb1c-a219-4e96-94c1-bfe598f6e58f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814322390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1814322390
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3031830184
Short name T554
Test name
Test status
Simulation time 100065682 ps
CPU time 1.36 seconds
Started Feb 29 12:44:00 PM PST 24
Finished Feb 29 12:44:02 PM PST 24
Peak memory 200004 kb
Host smart-7f881be1-607a-43e3-a10f-657888192ade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031830184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3031830184
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1322045833
Short name T79
Test name
Test status
Simulation time 497576465 ps
CPU time 2.03 seconds
Started Feb 29 12:43:44 PM PST 24
Finished Feb 29 12:43:46 PM PST 24
Peak memory 200128 kb
Host smart-9b5446a4-4ef7-4418-8da2-6dfc36cab3a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322045833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1322045833
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2688661794
Short name T603
Test name
Test status
Simulation time 223151302 ps
CPU time 1.63 seconds
Started Feb 29 12:44:02 PM PST 24
Finished Feb 29 12:44:04 PM PST 24
Peak memory 200040 kb
Host smart-e594d944-563a-4d47-90f9-b049526ea1fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688661794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
688661794
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.955070886
Short name T610
Test name
Test status
Simulation time 1175992265 ps
CPU time 5.05 seconds
Started Feb 29 12:44:09 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 200100 kb
Host smart-79f7ad0c-0fcc-45dc-8608-95b4ee0a8c76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955070886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.955070886
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.659293701
Short name T567
Test name
Test status
Simulation time 139525583 ps
CPU time 0.88 seconds
Started Feb 29 12:43:48 PM PST 24
Finished Feb 29 12:43:49 PM PST 24
Peak memory 199976 kb
Host smart-64fc543b-0a12-4603-8610-e551cea99574
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659293701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.659293701
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1756431132
Short name T561
Test name
Test status
Simulation time 111121551 ps
CPU time 1.08 seconds
Started Feb 29 12:44:06 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 199980 kb
Host smart-6f7cc790-3373-40c7-9ba8-47f53aae00dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756431132 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1756431132
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2396457442
Short name T102
Test name
Test status
Simulation time 85150680 ps
CPU time 0.96 seconds
Started Feb 29 12:43:50 PM PST 24
Finished Feb 29 12:43:51 PM PST 24
Peak memory 199832 kb
Host smart-303bb950-05c6-46cb-be7c-3659c44d528e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396457442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2396457442
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3066161966
Short name T588
Test name
Test status
Simulation time 305031016 ps
CPU time 2.08 seconds
Started Feb 29 12:44:00 PM PST 24
Finished Feb 29 12:44:04 PM PST 24
Peak memory 200092 kb
Host smart-d96287b5-e02f-43c6-acf3-36e2b79c8aae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066161966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3066161966
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3452002397
Short name T593
Test name
Test status
Simulation time 922078249 ps
CPU time 3.45 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:57 PM PST 24
Peak memory 200108 kb
Host smart-05ba1155-bd30-49f9-b0d7-6d7369ba5c61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452002397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3452002397
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1219243614
Short name T563
Test name
Test status
Simulation time 127648299 ps
CPU time 1.26 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 200004 kb
Host smart-7bb2e8f8-925e-4bff-a226-96edacb7b80f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219243614 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1219243614
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2879219997
Short name T595
Test name
Test status
Simulation time 64283459 ps
CPU time 0.77 seconds
Started Feb 29 12:44:20 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 199844 kb
Host smart-e4e761dd-c12c-4d49-bb9c-b00cd492e9e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879219997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2879219997
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4122839960
Short name T613
Test name
Test status
Simulation time 121910269 ps
CPU time 1.04 seconds
Started Feb 29 12:44:17 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 199936 kb
Host smart-7ab308c0-a3aa-4bc7-a805-6a1f61af7277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122839960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.4122839960
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4139017973
Short name T605
Test name
Test status
Simulation time 245784280 ps
CPU time 1.83 seconds
Started Feb 29 12:43:58 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 200060 kb
Host smart-07823be8-2896-465e-9281-89df9f3ccbb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139017973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.4139017973
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1424997238
Short name T108
Test name
Test status
Simulation time 904422379 ps
CPU time 2.96 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:28 PM PST 24
Peak memory 200200 kb
Host smart-1228ce00-31b9-4fc7-810b-447de605ed7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424997238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1424997238
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.393865655
Short name T562
Test name
Test status
Simulation time 129485949 ps
CPU time 0.95 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 199960 kb
Host smart-ff797c89-2d9f-465c-935a-7ccf3736ed03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393865655 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.393865655
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3567664469
Short name T46
Test name
Test status
Simulation time 59824167 ps
CPU time 0.71 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 199880 kb
Host smart-6717541c-1919-4f38-9f00-6ff63761fec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567664469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3567664469
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2983180761
Short name T100
Test name
Test status
Simulation time 245158025 ps
CPU time 1.51 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 200160 kb
Host smart-dd6bae69-598e-4bc3-b26e-8dd315d61753
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983180761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2983180761
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.552571462
Short name T604
Test name
Test status
Simulation time 552917695 ps
CPU time 3.49 seconds
Started Feb 29 12:44:07 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 200040 kb
Host smart-8d13962d-c81f-4861-b822-dbdb2b1977a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552571462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.552571462
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3038796803
Short name T557
Test name
Test status
Simulation time 118236897 ps
CPU time 0.87 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 199788 kb
Host smart-8b53ba96-e0f3-4aea-8d81-c4f573e8ccb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038796803 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3038796803
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2458460522
Short name T608
Test name
Test status
Simulation time 80029037 ps
CPU time 0.76 seconds
Started Feb 29 12:44:04 PM PST 24
Finished Feb 29 12:44:06 PM PST 24
Peak memory 199936 kb
Host smart-830a0f7f-de46-4d22-a6df-7e57ea511b05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458460522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2458460522
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.864614891
Short name T573
Test name
Test status
Simulation time 250189856 ps
CPU time 1.49 seconds
Started Feb 29 12:44:17 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 200164 kb
Host smart-42d7e4a8-3763-42ef-b1b0-bf43d61286fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864614891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.864614891
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.610622747
Short name T612
Test name
Test status
Simulation time 289329869 ps
CPU time 2.11 seconds
Started Feb 29 12:44:36 PM PST 24
Finished Feb 29 12:44:39 PM PST 24
Peak memory 200124 kb
Host smart-030d4efa-87b1-40fa-92b8-d308eb3bd7ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610622747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.610622747
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1691247371
Short name T80
Test name
Test status
Simulation time 167112334 ps
CPU time 1.39 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 200216 kb
Host smart-fd49a50e-97be-4d1b-8c89-02c6b9bb62d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691247371 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1691247371
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3822601439
Short name T43
Test name
Test status
Simulation time 63403974 ps
CPU time 0.75 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 199844 kb
Host smart-257ea749-cf7f-4bc8-9e69-571fc4c42415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822601439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3822601439
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1652904044
Short name T96
Test name
Test status
Simulation time 76451679 ps
CPU time 0.94 seconds
Started Feb 29 12:44:18 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 199892 kb
Host smart-1f1fa58c-78e5-4134-b8ec-02cdafac3b91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652904044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1652904044
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1601232486
Short name T48
Test name
Test status
Simulation time 124911038 ps
CPU time 1.57 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 200216 kb
Host smart-47c7aff6-f555-4bb8-b9b3-efddb9a639bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601232486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1601232486
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.169199663
Short name T574
Test name
Test status
Simulation time 411199727 ps
CPU time 1.71 seconds
Started Feb 29 12:44:30 PM PST 24
Finished Feb 29 12:44:32 PM PST 24
Peak memory 200016 kb
Host smart-4a49568b-dfb3-4008-9fb8-ccd3720e1c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169199663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.169199663
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.935358831
Short name T614
Test name
Test status
Simulation time 121152186 ps
CPU time 0.96 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 199992 kb
Host smart-f0fa8661-4fad-4d30-a11e-f3d2fa6cc72b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935358831 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.935358831
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3893135529
Short name T607
Test name
Test status
Simulation time 77532588 ps
CPU time 0.83 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 199936 kb
Host smart-03b868c8-2ff9-474e-879d-b8612ff17405
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893135529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3893135529
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2921361669
Short name T97
Test name
Test status
Simulation time 225612923 ps
CPU time 1.51 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 200012 kb
Host smart-9ed29ea5-240a-432d-9446-b9befa0ba24b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921361669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2921361669
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1927441928
Short name T580
Test name
Test status
Simulation time 134541703 ps
CPU time 1.77 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 208308 kb
Host smart-f66175d6-5685-4578-88cf-440dace531a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927441928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1927441928
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3336188214
Short name T109
Test name
Test status
Simulation time 937118479 ps
CPU time 3.22 seconds
Started Feb 29 12:44:06 PM PST 24
Finished Feb 29 12:44:10 PM PST 24
Peak memory 200140 kb
Host smart-132140c5-68d7-4aa3-ae42-733a64a8888a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336188214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3336188214
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.566709549
Short name T582
Test name
Test status
Simulation time 211275853 ps
CPU time 1.3 seconds
Started Feb 29 12:44:18 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 200032 kb
Host smart-dfff0df4-8d9f-4ead-be72-5bb7a9d9d42c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566709549 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.566709549
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1399479436
Short name T88
Test name
Test status
Simulation time 63907921 ps
CPU time 0.76 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 199916 kb
Host smart-2f46b073-2e27-49e4-a538-8f5aa185d581
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399479436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1399479436
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4132001508
Short name T103
Test name
Test status
Simulation time 215404111 ps
CPU time 1.37 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 200068 kb
Host smart-4e84e009-58bb-4efc-9f4a-f6f1e9d943c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132001508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.4132001508
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.640816904
Short name T126
Test name
Test status
Simulation time 493417680 ps
CPU time 1.83 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 200148 kb
Host smart-63a4f5b0-fa12-4f7d-bc65-ff976a97b5fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640816904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.640816904
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3747618088
Short name T77
Test name
Test status
Simulation time 225747395 ps
CPU time 1.3 seconds
Started Feb 29 12:44:06 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 199940 kb
Host smart-4fdf2dca-1d86-470e-80b6-a5e1ab4bf81e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747618088 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3747618088
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1949453584
Short name T597
Test name
Test status
Simulation time 82108669 ps
CPU time 0.83 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 199820 kb
Host smart-88276eb4-1307-4678-8e29-a2eb6b6f25bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949453584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1949453584
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.660310033
Short name T570
Test name
Test status
Simulation time 147781868 ps
CPU time 1.15 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 199912 kb
Host smart-61f8f351-b0ef-44ee-be6e-55bdc564c33d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660310033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.660310033
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3668418117
Short name T596
Test name
Test status
Simulation time 329666438 ps
CPU time 2.32 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 200036 kb
Host smart-946e6e10-4a38-49ad-bfd4-c181be4e0be0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668418117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3668418117
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1852146454
Short name T124
Test name
Test status
Simulation time 1739343888 ps
CPU time 4.53 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 200068 kb
Host smart-0cc062b2-c569-45c5-86ca-bd0d5cc27975
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852146454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1852146454
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3717095229
Short name T74
Test name
Test status
Simulation time 113150463 ps
CPU time 0.95 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 200212 kb
Host smart-ac65083a-804c-4de5-b9bf-9e544982c9de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717095229 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3717095229
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.39901564
Short name T618
Test name
Test status
Simulation time 64899415 ps
CPU time 0.77 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 200152 kb
Host smart-422375fa-41b6-48b4-bccb-2a5cf7f700f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39901564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.39901564
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.298634135
Short name T586
Test name
Test status
Simulation time 201736994 ps
CPU time 1.47 seconds
Started Feb 29 12:44:06 PM PST 24
Finished Feb 29 12:44:09 PM PST 24
Peak memory 200172 kb
Host smart-92c086b3-bd7a-44c3-a379-3bc4cbdaba8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298634135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.298634135
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2973146600
Short name T553
Test name
Test status
Simulation time 131158768 ps
CPU time 1.69 seconds
Started Feb 29 12:44:19 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 200176 kb
Host smart-8f7487f7-1df2-4d33-afe9-f1e34fbab62d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973146600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2973146600
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1131471104
Short name T598
Test name
Test status
Simulation time 1037339975 ps
CPU time 3.12 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 200184 kb
Host smart-a728be24-aa76-447a-af5c-370113178cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131471104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1131471104
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1782182529
Short name T577
Test name
Test status
Simulation time 143281056 ps
CPU time 1.08 seconds
Started Feb 29 12:44:01 PM PST 24
Finished Feb 29 12:44:03 PM PST 24
Peak memory 199992 kb
Host smart-eca8f9ae-02bc-4b70-b7cc-4169c1ef70d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782182529 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1782182529
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3655074132
Short name T619
Test name
Test status
Simulation time 57952379 ps
CPU time 0.73 seconds
Started Feb 29 12:44:34 PM PST 24
Finished Feb 29 12:44:35 PM PST 24
Peak memory 200156 kb
Host smart-b31735ae-56ce-4238-9c1d-1382ccee1f01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655074132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3655074132
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.433207568
Short name T584
Test name
Test status
Simulation time 197649200 ps
CPU time 1.42 seconds
Started Feb 29 12:44:03 PM PST 24
Finished Feb 29 12:44:05 PM PST 24
Peak memory 200204 kb
Host smart-9bd08c36-a505-4480-aa88-de013ff593ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433207568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.433207568
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1173919596
Short name T579
Test name
Test status
Simulation time 214955721 ps
CPU time 1.74 seconds
Started Feb 29 12:43:57 PM PST 24
Finished Feb 29 12:43:59 PM PST 24
Peak memory 200404 kb
Host smart-152fed24-1459-4fac-b869-9e1cf291c7ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173919596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1173919596
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2644667286
Short name T601
Test name
Test status
Simulation time 438784906 ps
CPU time 1.7 seconds
Started Feb 29 12:44:18 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 200408 kb
Host smart-7fe5c000-8ce2-4db3-bcb8-c6352e2d319a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644667286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2644667286
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2760679272
Short name T565
Test name
Test status
Simulation time 165416496 ps
CPU time 1.14 seconds
Started Feb 29 12:44:09 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 199960 kb
Host smart-ceb3c3f1-5a3d-4b85-b698-6587baf3c287
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760679272 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2760679272
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1163880069
Short name T576
Test name
Test status
Simulation time 61736573 ps
CPU time 0.75 seconds
Started Feb 29 12:44:24 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 199776 kb
Host smart-43ddd2b0-5f1b-4c5e-8145-3151cd8b0cbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163880069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1163880069
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.110792685
Short name T578
Test name
Test status
Simulation time 124118462 ps
CPU time 1.03 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 199920 kb
Host smart-6b5dbbb7-d416-4d6c-a557-310cb7dd95a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110792685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.110792685
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2743008226
Short name T620
Test name
Test status
Simulation time 312613673 ps
CPU time 2.32 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 200376 kb
Host smart-0216c14a-6a01-4e9b-bd5b-46d034bd3d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743008226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2743008226
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2757868238
Short name T560
Test name
Test status
Simulation time 465789844 ps
CPU time 1.82 seconds
Started Feb 29 12:44:08 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 200176 kb
Host smart-41e7fc87-2b2d-4c7e-a7e5-a2cd72cac2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757868238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2757868238
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2282438049
Short name T45
Test name
Test status
Simulation time 465288196 ps
CPU time 2.59 seconds
Started Feb 29 12:43:58 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 200080 kb
Host smart-0a02e2b7-4878-4ab7-918d-cafe0e3f61c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282438049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
282438049
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1104362511
Short name T566
Test name
Test status
Simulation time 272996600 ps
CPU time 3.16 seconds
Started Feb 29 12:44:06 PM PST 24
Finished Feb 29 12:44:10 PM PST 24
Peak memory 200156 kb
Host smart-53226b9a-cf34-4a25-98c5-40ddb26f8e42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104362511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
104362511
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3210711028
Short name T589
Test name
Test status
Simulation time 149453932 ps
CPU time 0.91 seconds
Started Feb 29 12:43:49 PM PST 24
Finished Feb 29 12:43:51 PM PST 24
Peak memory 199816 kb
Host smart-5409c2f0-579e-49dc-96c4-b6d3c872116c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210711028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
210711028
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2084903455
Short name T50
Test name
Test status
Simulation time 172500207 ps
CPU time 1.17 seconds
Started Feb 29 12:44:04 PM PST 24
Finished Feb 29 12:44:06 PM PST 24
Peak memory 199912 kb
Host smart-1ddd122c-f028-4cd7-aa0c-67726b59fd8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084903455 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2084903455
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3109560161
Short name T585
Test name
Test status
Simulation time 72369116 ps
CPU time 0.81 seconds
Started Feb 29 12:44:08 PM PST 24
Finished Feb 29 12:44:09 PM PST 24
Peak memory 199852 kb
Host smart-4f0ad937-f1a9-44ab-8dd1-e17b7e15efaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109560161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3109560161
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2853734936
Short name T99
Test name
Test status
Simulation time 100204654 ps
CPU time 1.19 seconds
Started Feb 29 12:44:06 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 200128 kb
Host smart-3b80d8b6-1c2b-4153-8697-2ccd0e8371a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853734936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2853734936
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.389018074
Short name T592
Test name
Test status
Simulation time 220280987 ps
CPU time 3.09 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:09 PM PST 24
Peak memory 199752 kb
Host smart-ebfb3c1c-522b-4ab3-8d57-8ebeec0042e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389018074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.389018074
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.658617467
Short name T44
Test name
Test status
Simulation time 208244550 ps
CPU time 1.54 seconds
Started Feb 29 12:44:07 PM PST 24
Finished Feb 29 12:44:09 PM PST 24
Peak memory 200156 kb
Host smart-4d5beb85-e609-4187-8406-c0f9f5373101
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658617467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.658617467
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.782584493
Short name T555
Test name
Test status
Simulation time 276778949 ps
CPU time 3.12 seconds
Started Feb 29 12:44:00 PM PST 24
Finished Feb 29 12:44:03 PM PST 24
Peak memory 200096 kb
Host smart-a40111f8-38f1-4174-84db-1592c155c5fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782584493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.782584493
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4125144171
Short name T549
Test name
Test status
Simulation time 109457976 ps
CPU time 0.85 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 199832 kb
Host smart-25529b88-f143-4394-8b4c-5336c3b25fb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125144171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
125144171
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.114714498
Short name T571
Test name
Test status
Simulation time 195905538 ps
CPU time 1.17 seconds
Started Feb 29 12:44:00 PM PST 24
Finished Feb 29 12:44:02 PM PST 24
Peak memory 199892 kb
Host smart-07c79ecf-e522-4e4a-96b1-83428964d4ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114714498 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.114714498
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3335408090
Short name T550
Test name
Test status
Simulation time 86957902 ps
CPU time 0.85 seconds
Started Feb 29 12:44:02 PM PST 24
Finished Feb 29 12:44:03 PM PST 24
Peak memory 199908 kb
Host smart-6f70c9a4-9424-4830-9711-4a5bbbf7e912
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335408090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3335408090
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1242125039
Short name T591
Test name
Test status
Simulation time 136109684 ps
CPU time 1.08 seconds
Started Feb 29 12:44:02 PM PST 24
Finished Feb 29 12:44:04 PM PST 24
Peak memory 199900 kb
Host smart-265dd480-c7cc-41fa-9d04-2658144f91d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242125039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1242125039
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3951803875
Short name T606
Test name
Test status
Simulation time 513239112 ps
CPU time 1.94 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:55 PM PST 24
Peak memory 200060 kb
Host smart-4700a924-6ac8-4d4b-97bc-5cf069ae78d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951803875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3951803875
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2021376225
Short name T551
Test name
Test status
Simulation time 217490860 ps
CPU time 1.53 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 200224 kb
Host smart-08b4fc13-7bd2-47f1-be5c-0aa17d6e4e2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021376225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
021376225
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2100346807
Short name T104
Test name
Test status
Simulation time 1164921182 ps
CPU time 5.36 seconds
Started Feb 29 12:43:48 PM PST 24
Finished Feb 29 12:43:54 PM PST 24
Peak memory 200088 kb
Host smart-add35184-96b0-4a4c-8062-f75e15bf52b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100346807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
100346807
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4022060446
Short name T615
Test name
Test status
Simulation time 99943460 ps
CPU time 0.74 seconds
Started Feb 29 12:44:04 PM PST 24
Finished Feb 29 12:44:04 PM PST 24
Peak memory 199888 kb
Host smart-b710e121-a695-461e-811b-fc696ec238b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022060446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4
022060446
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1194983535
Short name T564
Test name
Test status
Simulation time 182702841 ps
CPU time 1.07 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 199928 kb
Host smart-85d89ff8-c1d6-4631-98c1-35e8d4201036
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194983535 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1194983535
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1422102225
Short name T101
Test name
Test status
Simulation time 61155638 ps
CPU time 0.76 seconds
Started Feb 29 12:44:04 PM PST 24
Finished Feb 29 12:44:06 PM PST 24
Peak memory 199956 kb
Host smart-bb7af0ed-457a-4d53-9390-9687d153f0d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422102225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1422102225
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1370892219
Short name T590
Test name
Test status
Simulation time 75653130 ps
CPU time 0.94 seconds
Started Feb 29 12:44:15 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 199984 kb
Host smart-f5c0a54d-16d3-4fab-beb9-a215e8b05ce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370892219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1370892219
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3077610553
Short name T114
Test name
Test status
Simulation time 458942026 ps
CPU time 3.33 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:09 PM PST 24
Peak memory 199660 kb
Host smart-c2f9b2eb-749d-440e-a596-548237376fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077610553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3077610553
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2161598672
Short name T54
Test name
Test status
Simulation time 416742340 ps
CPU time 1.75 seconds
Started Feb 29 12:44:01 PM PST 24
Finished Feb 29 12:44:04 PM PST 24
Peak memory 200020 kb
Host smart-b1858e7f-ef8b-41d5-a560-bfbd638cfd3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161598672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2161598672
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1369067188
Short name T556
Test name
Test status
Simulation time 182942116 ps
CPU time 1.2 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 199892 kb
Host smart-13a54d1c-2d8b-4463-85c4-0976ca94d566
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369067188 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1369067188
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3823291278
Short name T617
Test name
Test status
Simulation time 71411334 ps
CPU time 0.77 seconds
Started Feb 29 12:44:04 PM PST 24
Finished Feb 29 12:44:05 PM PST 24
Peak memory 199900 kb
Host smart-6be9ba29-bfd6-49e2-b996-cb7ffb4799aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823291278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3823291278
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2270534835
Short name T599
Test name
Test status
Simulation time 82491447 ps
CPU time 0.89 seconds
Started Feb 29 12:44:21 PM PST 24
Finished Feb 29 12:44:22 PM PST 24
Peak memory 199908 kb
Host smart-9bd4ac69-a1f0-463c-8400-17a3c39ce8b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270534835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2270534835
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1362104978
Short name T568
Test name
Test status
Simulation time 283243655 ps
CPU time 2.09 seconds
Started Feb 29 12:44:18 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 200132 kb
Host smart-77a9849f-29ee-4701-b722-cf73b539e6cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362104978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1362104978
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3394995863
Short name T125
Test name
Test status
Simulation time 500745528 ps
CPU time 2.02 seconds
Started Feb 29 12:44:16 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 200076 kb
Host smart-893c1dce-2596-4a4a-92d0-9805de6cda98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394995863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3394995863
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4206946621
Short name T583
Test name
Test status
Simulation time 136324879 ps
CPU time 1.07 seconds
Started Feb 29 12:44:18 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 200020 kb
Host smart-9eac7882-a21d-4910-a0cf-44c64d4b5ed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206946621 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.4206946621
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2029024315
Short name T609
Test name
Test status
Simulation time 59815882 ps
CPU time 0.75 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 199848 kb
Host smart-16c462cd-1b02-4e39-b9ca-d34289ef1114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029024315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2029024315
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.615801203
Short name T602
Test name
Test status
Simulation time 133868110 ps
CPU time 1.05 seconds
Started Feb 29 12:44:06 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 199876 kb
Host smart-24dae35e-ab47-4f72-bea5-8e0bdcb55d13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615801203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.615801203
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1710977630
Short name T107
Test name
Test status
Simulation time 200857453 ps
CPU time 2.88 seconds
Started Feb 29 12:44:15 PM PST 24
Finished Feb 29 12:44:18 PM PST 24
Peak memory 200124 kb
Host smart-8ef7809d-c4b2-4613-92fb-664afe2e876e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710977630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1710977630
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4162996841
Short name T111
Test name
Test status
Simulation time 938279450 ps
CPU time 3.45 seconds
Started Feb 29 12:44:17 PM PST 24
Finished Feb 29 12:44:22 PM PST 24
Peak memory 200152 kb
Host smart-8853156c-e901-4533-8dc1-4652fb00d418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162996841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.4162996841
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1712887493
Short name T616
Test name
Test status
Simulation time 118980985 ps
CPU time 1.16 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:07 PM PST 24
Peak memory 199960 kb
Host smart-184dc0c6-7952-41ed-b72b-ca275bb72192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712887493 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1712887493
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1232221766
Short name T548
Test name
Test status
Simulation time 61498815 ps
CPU time 0.75 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 199784 kb
Host smart-8a500734-a048-41e8-b670-396beded648f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232221766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1232221766
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1856819386
Short name T572
Test name
Test status
Simulation time 245784332 ps
CPU time 1.44 seconds
Started Feb 29 12:44:18 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 200136 kb
Host smart-749f72ec-26ad-4b37-a917-790a56b73573
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856819386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1856819386
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.603452605
Short name T78
Test name
Test status
Simulation time 231028959 ps
CPU time 1.82 seconds
Started Feb 29 12:44:08 PM PST 24
Finished Feb 29 12:44:10 PM PST 24
Peak memory 200060 kb
Host smart-c9c95abe-3eec-459c-b00e-d51048959793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603452605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.603452605
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3655137895
Short name T75
Test name
Test status
Simulation time 115074284 ps
CPU time 1.07 seconds
Started Feb 29 12:44:16 PM PST 24
Finished Feb 29 12:44:18 PM PST 24
Peak memory 199840 kb
Host smart-7979650a-aee6-4420-9d4d-28c98303c066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655137895 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3655137895
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2529973229
Short name T95
Test name
Test status
Simulation time 75785578 ps
CPU time 0.75 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 199900 kb
Host smart-8ae986b6-24b9-4fa9-a565-bfa1999289cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529973229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2529973229
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4248436545
Short name T569
Test name
Test status
Simulation time 198238104 ps
CPU time 1.46 seconds
Started Feb 29 12:44:08 PM PST 24
Finished Feb 29 12:44:10 PM PST 24
Peak memory 200168 kb
Host smart-725a44ad-86dc-44fc-bcf5-1dee05c3bb50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248436545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4248436545
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4105599185
Short name T105
Test name
Test status
Simulation time 383292053 ps
CPU time 3.01 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 208312 kb
Host smart-2df0640b-8316-4d6e-8f09-2f387ba03cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105599185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.4105599185
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.846974842
Short name T110
Test name
Test status
Simulation time 481291561 ps
CPU time 1.79 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 200096 kb
Host smart-92b0f3b6-74d3-4452-a82f-9ef8adebb3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846974842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
846974842
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4084946521
Short name T587
Test name
Test status
Simulation time 123617832 ps
CPU time 1.37 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 199984 kb
Host smart-f380dbd5-7da8-4250-b6ff-2117ca55ea5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084946521 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.4084946521
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2330812511
Short name T581
Test name
Test status
Simulation time 67781664 ps
CPU time 0.82 seconds
Started Feb 29 12:44:14 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 199920 kb
Host smart-7aeda338-79ef-4829-bfa6-81793cf2fc6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330812511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2330812511
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1450539015
Short name T611
Test name
Test status
Simulation time 128439936 ps
CPU time 1.25 seconds
Started Feb 29 12:44:24 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 200120 kb
Host smart-120f3916-a6b8-442d-b348-e182bdcc7a3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450539015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1450539015
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2696223764
Short name T76
Test name
Test status
Simulation time 418494045 ps
CPU time 3.43 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:17 PM PST 24
Peak memory 200164 kb
Host smart-600fb0f1-bdb6-4d12-9883-42660271bbb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696223764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2696223764
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.354632172
Short name T40
Test name
Test status
Simulation time 1887135626 ps
CPU time 6.82 seconds
Started Feb 29 12:46:49 PM PST 24
Finished Feb 29 12:46:56 PM PST 24
Peak memory 222072 kb
Host smart-97c74333-e7b9-4817-9657-62907feb1630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354632172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.354632172
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2016909804
Short name T338
Test name
Test status
Simulation time 245703736 ps
CPU time 1.11 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 217328 kb
Host smart-f5f96173-b3a7-4efb-9728-4c358395091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016909804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2016909804
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3904480869
Short name T230
Test name
Test status
Simulation time 99231970 ps
CPU time 0.75 seconds
Started Feb 29 12:46:43 PM PST 24
Finished Feb 29 12:46:44 PM PST 24
Peak memory 199828 kb
Host smart-e59bb27e-1ca0-4912-982e-54c938d5a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904480869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3904480869
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3423899276
Short name T94
Test name
Test status
Simulation time 895197068 ps
CPU time 4.59 seconds
Started Feb 29 12:46:48 PM PST 24
Finished Feb 29 12:46:53 PM PST 24
Peak memory 200284 kb
Host smart-25fc72f7-060c-400d-b6f2-afa7222dd5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423899276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3423899276
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.949445427
Short name T56
Test name
Test status
Simulation time 16520253602 ps
CPU time 31.54 seconds
Started Feb 29 12:46:31 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 218124 kb
Host smart-e871dc97-cd1e-4ab8-84a9-e154e7e18556
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949445427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.949445427
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4063649
Short name T381
Test name
Test status
Simulation time 143457031 ps
CPU time 1.09 seconds
Started Feb 29 12:46:48 PM PST 24
Finished Feb 29 12:46:49 PM PST 24
Peak memory 200024 kb
Host smart-47cb86eb-68de-4456-958d-745a8c251a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4063649
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2580303141
Short name T524
Test name
Test status
Simulation time 116197512 ps
CPU time 1.2 seconds
Started Feb 29 12:46:50 PM PST 24
Finished Feb 29 12:46:52 PM PST 24
Peak memory 200328 kb
Host smart-0981825c-194c-4439-8960-6cf829e6e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580303141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2580303141
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.222541875
Short name T532
Test name
Test status
Simulation time 3425596165 ps
CPU time 11.51 seconds
Started Feb 29 12:46:55 PM PST 24
Finished Feb 29 12:47:06 PM PST 24
Peak memory 200456 kb
Host smart-f5191af9-8cec-4fc9-bd19-444564dca2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222541875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.222541875
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1668554402
Short name T5
Test name
Test status
Simulation time 111910004 ps
CPU time 1.4 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 200052 kb
Host smart-c2420b46-0d30-48ee-a906-577c1d8c9ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668554402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1668554402
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1621634755
Short name T410
Test name
Test status
Simulation time 75076556 ps
CPU time 0.74 seconds
Started Feb 29 12:46:53 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 199432 kb
Host smart-0372d8a0-10ae-4e8b-98b5-e1bcb55bca68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621634755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1621634755
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.618957535
Short name T451
Test name
Test status
Simulation time 244613045 ps
CPU time 1.04 seconds
Started Feb 29 12:46:50 PM PST 24
Finished Feb 29 12:46:51 PM PST 24
Peak memory 217380 kb
Host smart-b02476b7-9b37-42bd-98b5-a7a18105792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618957535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.618957535
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.166884667
Short name T358
Test name
Test status
Simulation time 150529178 ps
CPU time 0.88 seconds
Started Feb 29 12:46:39 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 199848 kb
Host smart-e4384560-110b-421e-a2df-39d769df83ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166884667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.166884667
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1864534964
Short name T265
Test name
Test status
Simulation time 728913374 ps
CPU time 4.04 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:50 PM PST 24
Peak memory 200352 kb
Host smart-5361d7bd-fa76-400c-9906-ca590cd59bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864534964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1864534964
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.154740140
Short name T52
Test name
Test status
Simulation time 16951623540 ps
CPU time 24.7 seconds
Started Feb 29 12:46:48 PM PST 24
Finished Feb 29 12:47:13 PM PST 24
Peak memory 218136 kb
Host smart-3bcdce19-b086-4c16-81fa-eea492866e9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154740140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.154740140
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.522122060
Short name T371
Test name
Test status
Simulation time 142914483 ps
CPU time 1.12 seconds
Started Feb 29 12:46:44 PM PST 24
Finished Feb 29 12:46:45 PM PST 24
Peak memory 200040 kb
Host smart-a4067bbd-3d0a-4429-b410-0b8808ae2936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522122060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.522122060
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.75799248
Short name T514
Test name
Test status
Simulation time 263781234 ps
CPU time 1.46 seconds
Started Feb 29 12:46:36 PM PST 24
Finished Feb 29 12:46:37 PM PST 24
Peak memory 200296 kb
Host smart-3c7aa07f-2674-44f2-9511-adf07c55ec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75799248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.75799248
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2509611294
Short name T463
Test name
Test status
Simulation time 1961207780 ps
CPU time 6.48 seconds
Started Feb 29 12:46:32 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 200284 kb
Host smart-244a7e66-fcb4-46e8-832b-67f987b32f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509611294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2509611294
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.767731213
Short name T252
Test name
Test status
Simulation time 399904161 ps
CPU time 2.22 seconds
Started Feb 29 12:46:40 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 199976 kb
Host smart-166e978b-f600-4fdc-b889-3516f9aa4762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767731213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.767731213
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1482886502
Short name T57
Test name
Test status
Simulation time 152280632 ps
CPU time 1.17 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 200040 kb
Host smart-daab9118-064f-4ec1-b541-e66285f5c6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482886502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1482886502
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3261802505
Short name T170
Test name
Test status
Simulation time 72653476 ps
CPU time 0.81 seconds
Started Feb 29 12:47:14 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 199936 kb
Host smart-f757b541-6c5d-40a3-a7ec-f482b248ff28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261802505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3261802505
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3710830674
Short name T30
Test name
Test status
Simulation time 1226619888 ps
CPU time 5.42 seconds
Started Feb 29 12:47:01 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 217500 kb
Host smart-611ac8bd-e921-4191-a7e0-57ae8dab18be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710830674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3710830674
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3227362131
Short name T397
Test name
Test status
Simulation time 243609170 ps
CPU time 1.13 seconds
Started Feb 29 12:46:58 PM PST 24
Finished Feb 29 12:46:59 PM PST 24
Peak memory 217304 kb
Host smart-93d8d931-8be9-4f29-b0e4-6b4e46ac153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227362131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3227362131
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1528316644
Short name T192
Test name
Test status
Simulation time 1301170090 ps
CPU time 5.13 seconds
Started Feb 29 12:46:50 PM PST 24
Finished Feb 29 12:46:56 PM PST 24
Peak memory 200264 kb
Host smart-2bc0d757-05a7-4eb5-ae31-51f910f28987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528316644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1528316644
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1089538953
Short name T254
Test name
Test status
Simulation time 98688503 ps
CPU time 1.02 seconds
Started Feb 29 12:46:56 PM PST 24
Finished Feb 29 12:46:57 PM PST 24
Peak memory 200016 kb
Host smart-995fddfb-fcca-44df-a016-9e16acd57d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089538953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1089538953
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1252483338
Short name T219
Test name
Test status
Simulation time 224329121 ps
CPU time 1.42 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:01 PM PST 24
Peak memory 200216 kb
Host smart-aec19dc9-c653-4fae-8d17-fa43af9d505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252483338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1252483338
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.719769312
Short name T464
Test name
Test status
Simulation time 3787470077 ps
CPU time 13.32 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:13 PM PST 24
Peak memory 200360 kb
Host smart-87d040e1-d737-4acd-b41d-0bce8ef07b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719769312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.719769312
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2025034480
Short name T399
Test name
Test status
Simulation time 147359031 ps
CPU time 1.8 seconds
Started Feb 29 12:46:54 PM PST 24
Finished Feb 29 12:46:56 PM PST 24
Peak memory 200080 kb
Host smart-1b4af9f8-f7b4-4802-a3b0-007dee89a93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025034480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2025034480
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3181493710
Short name T449
Test name
Test status
Simulation time 215941577 ps
CPU time 1.31 seconds
Started Feb 29 12:46:48 PM PST 24
Finished Feb 29 12:46:50 PM PST 24
Peak memory 200048 kb
Host smart-d0066c08-3a9f-451b-a6b8-221f912dd308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181493710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3181493710
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.674460737
Short name T543
Test name
Test status
Simulation time 72816608 ps
CPU time 0.73 seconds
Started Feb 29 12:46:54 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 199804 kb
Host smart-9ec5c204-3a33-4c43-b81a-650964964151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674460737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.674460737
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1415399684
Short name T232
Test name
Test status
Simulation time 244912950 ps
CPU time 1.19 seconds
Started Feb 29 12:47:04 PM PST 24
Finished Feb 29 12:47:06 PM PST 24
Peak memory 217336 kb
Host smart-daeb7450-6a46-4a9c-bb01-5c4dd4f1bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415399684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1415399684
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.572388771
Short name T241
Test name
Test status
Simulation time 76481048 ps
CPU time 0.74 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 199900 kb
Host smart-b6e7465a-e497-48c9-baa6-2596e879eb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572388771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.572388771
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1371249415
Short name T531
Test name
Test status
Simulation time 1490219044 ps
CPU time 5.57 seconds
Started Feb 29 12:46:56 PM PST 24
Finished Feb 29 12:47:02 PM PST 24
Peak memory 200360 kb
Host smart-f07266d7-519b-4200-8395-0466f0434d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371249415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1371249415
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1257551202
Short name T362
Test name
Test status
Simulation time 148534664 ps
CPU time 1.09 seconds
Started Feb 29 12:46:55 PM PST 24
Finished Feb 29 12:46:57 PM PST 24
Peak memory 199988 kb
Host smart-1daa57d6-3d3e-4805-9ccd-1ecdbf25ba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257551202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1257551202
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1024854018
Short name T225
Test name
Test status
Simulation time 247954972 ps
CPU time 1.51 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:01 PM PST 24
Peak memory 200284 kb
Host smart-5d11313f-56fe-4354-94b4-04c512667acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024854018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1024854018
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1479174471
Short name T89
Test name
Test status
Simulation time 6657619773 ps
CPU time 28.35 seconds
Started Feb 29 12:46:54 PM PST 24
Finished Feb 29 12:47:22 PM PST 24
Peak memory 200384 kb
Host smart-02815e55-2392-4098-9ae2-5a6803432dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479174471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1479174471
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.722921562
Short name T279
Test name
Test status
Simulation time 151112614 ps
CPU time 1.79 seconds
Started Feb 29 12:47:04 PM PST 24
Finished Feb 29 12:47:06 PM PST 24
Peak memory 200072 kb
Host smart-944e2a8a-5588-45f7-ac57-96d061622da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722921562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.722921562
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1260434804
Short name T224
Test name
Test status
Simulation time 230834187 ps
CPU time 1.34 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 200072 kb
Host smart-36a24841-ef61-42c4-9353-18b02ea5610f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260434804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1260434804
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2651404421
Short name T512
Test name
Test status
Simulation time 69076608 ps
CPU time 0.77 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:00 PM PST 24
Peak memory 199916 kb
Host smart-fad3c7c3-3354-4b07-89f9-1ff79192387f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651404421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2651404421
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.652489881
Short name T4
Test name
Test status
Simulation time 2348586755 ps
CPU time 8.53 seconds
Started Feb 29 12:46:57 PM PST 24
Finished Feb 29 12:47:06 PM PST 24
Peak memory 218796 kb
Host smart-021df70d-980b-42f5-89d9-5ca9c95d1285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652489881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.652489881
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2697466026
Short name T390
Test name
Test status
Simulation time 243356123 ps
CPU time 1.15 seconds
Started Feb 29 12:47:00 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 217440 kb
Host smart-5239257d-81d1-4369-90b7-111f1c20ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697466026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2697466026
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3474700070
Short name T479
Test name
Test status
Simulation time 110123784 ps
CPU time 0.74 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:11 PM PST 24
Peak memory 199904 kb
Host smart-96b021bb-3324-401d-a6c5-747e32f5282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474700070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3474700070
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1699277967
Short name T118
Test name
Test status
Simulation time 1948716174 ps
CPU time 6.82 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 200292 kb
Host smart-8908c3fb-2b01-4c5d-9fe1-554e1a1d5cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699277967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1699277967
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1675303966
Short name T261
Test name
Test status
Simulation time 148748587 ps
CPU time 1.11 seconds
Started Feb 29 12:46:56 PM PST 24
Finished Feb 29 12:46:57 PM PST 24
Peak memory 200012 kb
Host smart-77c5ea57-035c-42f6-a519-1e9ede3beb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675303966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1675303966
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1885232758
Short name T336
Test name
Test status
Simulation time 235152632 ps
CPU time 1.41 seconds
Started Feb 29 12:46:55 PM PST 24
Finished Feb 29 12:46:56 PM PST 24
Peak memory 200200 kb
Host smart-c9d82249-ca37-4b01-9c0d-65a3352f9251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885232758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1885232758
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2293064096
Short name T285
Test name
Test status
Simulation time 5504033561 ps
CPU time 18.81 seconds
Started Feb 29 12:47:10 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 200388 kb
Host smart-61683e63-a597-4961-af31-165663355a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293064096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2293064096
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.445519096
Short name T350
Test name
Test status
Simulation time 143523178 ps
CPU time 1.74 seconds
Started Feb 29 12:47:06 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 200008 kb
Host smart-796ffdcc-f5f6-4209-8cd1-0ed62edd4bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445519096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.445519096
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3280542823
Short name T361
Test name
Test status
Simulation time 87234383 ps
CPU time 0.85 seconds
Started Feb 29 12:47:01 PM PST 24
Finished Feb 29 12:47:02 PM PST 24
Peak memory 200288 kb
Host smart-930f6224-097f-44c6-a41d-a0f865ae5f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280542823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3280542823
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2991684675
Short name T196
Test name
Test status
Simulation time 92230934 ps
CPU time 0.86 seconds
Started Feb 29 12:47:00 PM PST 24
Finished Feb 29 12:47:06 PM PST 24
Peak memory 199892 kb
Host smart-bd62522e-1fa2-42ac-bad7-3e9ca6c14f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991684675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2991684675
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.141894288
Short name T24
Test name
Test status
Simulation time 1227701323 ps
CPU time 5.61 seconds
Started Feb 29 12:46:56 PM PST 24
Finished Feb 29 12:47:02 PM PST 24
Peak memory 217956 kb
Host smart-dbfb33c5-66b0-45a5-896e-4791bdf1bbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141894288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.141894288
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3625742547
Short name T134
Test name
Test status
Simulation time 244441319 ps
CPU time 1.22 seconds
Started Feb 29 12:47:00 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 217308 kb
Host smart-cebd47a4-e664-4069-9589-32a1c568a014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625742547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3625742547
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1153947318
Short name T203
Test name
Test status
Simulation time 97948555 ps
CPU time 0.72 seconds
Started Feb 29 12:47:06 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 199912 kb
Host smart-d7fd918c-efe8-4678-8b90-8f31c26c971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153947318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1153947318
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.4235446870
Short name T413
Test name
Test status
Simulation time 683285066 ps
CPU time 3.61 seconds
Started Feb 29 12:46:58 PM PST 24
Finished Feb 29 12:47:02 PM PST 24
Peak memory 200296 kb
Host smart-805b99fb-ea54-4de1-ad53-541e967d846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235446870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.4235446870
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.831265715
Short name T292
Test name
Test status
Simulation time 101412795 ps
CPU time 0.93 seconds
Started Feb 29 12:47:04 PM PST 24
Finished Feb 29 12:47:05 PM PST 24
Peak memory 200068 kb
Host smart-4c61a65e-6fe7-4d9b-9d29-86a9f5f3930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831265715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.831265715
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2492459681
Short name T312
Test name
Test status
Simulation time 232619194 ps
CPU time 1.46 seconds
Started Feb 29 12:47:05 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 200344 kb
Host smart-ed9d7a2d-41dc-4ec4-a1e7-54359339cd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492459681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2492459681
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.569423405
Short name T237
Test name
Test status
Simulation time 7560475559 ps
CPU time 31.74 seconds
Started Feb 29 12:47:00 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 200348 kb
Host smart-5f058f5b-1832-44b1-8991-a14ddfcfc09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569423405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.569423405
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1899811007
Short name T70
Test name
Test status
Simulation time 264992911 ps
CPU time 1.7 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:01 PM PST 24
Peak memory 200100 kb
Host smart-7f7d63ee-4c22-4ea2-b76b-f07517551d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899811007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1899811007
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1991136804
Short name T416
Test name
Test status
Simulation time 173788318 ps
CPU time 1.17 seconds
Started Feb 29 12:46:54 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 200104 kb
Host smart-3983a724-93a5-41ce-a039-5b0fd2be81ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991136804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1991136804
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.84938506
Short name T35
Test name
Test status
Simulation time 81162296 ps
CPU time 0.78 seconds
Started Feb 29 12:47:04 PM PST 24
Finished Feb 29 12:47:05 PM PST 24
Peak memory 199856 kb
Host smart-efdb05cb-46d6-4865-be5b-428dab4cd2da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84938506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.84938506
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1468182461
Short name T31
Test name
Test status
Simulation time 1224989911 ps
CPU time 5.88 seconds
Started Feb 29 12:47:15 PM PST 24
Finished Feb 29 12:47:22 PM PST 24
Peak memory 221548 kb
Host smart-bef33187-3160-4979-9624-92f7928e68a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468182461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1468182461
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1103453668
Short name T136
Test name
Test status
Simulation time 243902264 ps
CPU time 1.09 seconds
Started Feb 29 12:47:01 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 217332 kb
Host smart-93be4465-f9b3-460d-b6d6-38aaa70b07ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103453668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1103453668
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2845490591
Short name T517
Test name
Test status
Simulation time 232648463 ps
CPU time 1 seconds
Started Feb 29 12:47:02 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 199816 kb
Host smart-3d52013c-d877-43f5-acc4-ff01dba0732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845490591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2845490591
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3528752465
Short name T83
Test name
Test status
Simulation time 1026947559 ps
CPU time 5 seconds
Started Feb 29 12:47:02 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 200480 kb
Host smart-df56294d-a041-44b2-81c3-bb8d1925356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528752465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3528752465
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2401710710
Short name T484
Test name
Test status
Simulation time 120234085 ps
CPU time 1.11 seconds
Started Feb 29 12:46:56 PM PST 24
Finished Feb 29 12:46:58 PM PST 24
Peak memory 200280 kb
Host smart-a03e249f-14e5-4662-a4d3-7ced882e9cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401710710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2401710710
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.732409443
Short name T91
Test name
Test status
Simulation time 6035461054 ps
CPU time 25.95 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:47:14 PM PST 24
Peak memory 200316 kb
Host smart-dcf28baf-b93f-4a05-8356-7d4f2296eb56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732409443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.732409443
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.4104297336
Short name T148
Test name
Test status
Simulation time 311110435 ps
CPU time 2.02 seconds
Started Feb 29 12:47:00 PM PST 24
Finished Feb 29 12:47:04 PM PST 24
Peak memory 200004 kb
Host smart-28c9e055-a5c2-4b09-a8c1-5c42e6e1f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104297336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4104297336
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3765015736
Short name T365
Test name
Test status
Simulation time 271657262 ps
CPU time 1.43 seconds
Started Feb 29 12:47:00 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 200004 kb
Host smart-97737708-38ba-4754-8dc5-aaf317eeaa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765015736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3765015736
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2824961584
Short name T498
Test name
Test status
Simulation time 83286851 ps
CPU time 0.8 seconds
Started Feb 29 12:47:22 PM PST 24
Finished Feb 29 12:47:23 PM PST 24
Peak memory 199948 kb
Host smart-edfd73c7-9dc3-4b26-aca3-801c6e7fda7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824961584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2824961584
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1830301209
Short name T333
Test name
Test status
Simulation time 1875259989 ps
CPU time 6.81 seconds
Started Feb 29 12:47:18 PM PST 24
Finished Feb 29 12:47:25 PM PST 24
Peak memory 216832 kb
Host smart-db31ebbc-522b-49f2-965e-e146f68f2c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830301209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1830301209
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1647732862
Short name T198
Test name
Test status
Simulation time 244525481 ps
CPU time 1.07 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:11 PM PST 24
Peak memory 217416 kb
Host smart-e2be95ea-8184-4614-ba96-9dbd4edb635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647732862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1647732862
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3457004108
Short name T398
Test name
Test status
Simulation time 85776844 ps
CPU time 0.67 seconds
Started Feb 29 12:47:07 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 199908 kb
Host smart-4031bfb1-e359-4c9f-905f-01d0b42f3e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457004108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3457004108
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2618384792
Short name T87
Test name
Test status
Simulation time 1257580251 ps
CPU time 5.23 seconds
Started Feb 29 12:47:28 PM PST 24
Finished Feb 29 12:47:34 PM PST 24
Peak memory 200388 kb
Host smart-6aeede18-e8ed-495a-a39f-70025ff2891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618384792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2618384792
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2783320648
Short name T496
Test name
Test status
Simulation time 100661627 ps
CPU time 1.05 seconds
Started Feb 29 12:46:56 PM PST 24
Finished Feb 29 12:46:58 PM PST 24
Peak memory 200040 kb
Host smart-34060d09-6b79-41ac-b249-38018b06714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783320648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2783320648
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2208643065
Short name T10
Test name
Test status
Simulation time 211898514 ps
CPU time 1.37 seconds
Started Feb 29 12:47:00 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 200532 kb
Host smart-22ea5c54-e389-407d-a445-5d178bdd026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208643065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2208643065
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2545080733
Short name T319
Test name
Test status
Simulation time 5935874282 ps
CPU time 29.42 seconds
Started Feb 29 12:46:55 PM PST 24
Finished Feb 29 12:47:25 PM PST 24
Peak memory 200468 kb
Host smart-963feb88-cda9-42dd-a443-3fe499a07da9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545080733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2545080733
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.737505630
Short name T67
Test name
Test status
Simulation time 304151293 ps
CPU time 1.96 seconds
Started Feb 29 12:47:00 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 200036 kb
Host smart-6226acec-a7bb-442b-9b20-46cdcc898de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737505630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.737505630
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1682855825
Short name T222
Test name
Test status
Simulation time 120649175 ps
CPU time 1.1 seconds
Started Feb 29 12:47:04 PM PST 24
Finished Feb 29 12:47:05 PM PST 24
Peak memory 200036 kb
Host smart-e41c7e62-3eea-4456-9dad-f6a1353404df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682855825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1682855825
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.645972827
Short name T183
Test name
Test status
Simulation time 91321728 ps
CPU time 0.8 seconds
Started Feb 29 12:47:28 PM PST 24
Finished Feb 29 12:47:29 PM PST 24
Peak memory 199968 kb
Host smart-96266f33-224e-4ce4-b6a8-c02b1df7a729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645972827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.645972827
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1296543635
Short name T334
Test name
Test status
Simulation time 1232091137 ps
CPU time 5.95 seconds
Started Feb 29 12:46:50 PM PST 24
Finished Feb 29 12:46:56 PM PST 24
Peak memory 217952 kb
Host smart-4afc9aee-05f2-43f2-8833-bb95231174bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296543635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1296543635
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.4165133755
Short name T525
Test name
Test status
Simulation time 244398035 ps
CPU time 1.05 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:01 PM PST 24
Peak memory 217256 kb
Host smart-9b7a2a71-74c0-4990-a864-0146c086207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165133755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.4165133755
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3918288057
Short name T162
Test name
Test status
Simulation time 210065291 ps
CPU time 0.97 seconds
Started Feb 29 12:47:07 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 199956 kb
Host smart-29a0f3dd-f2fa-4d5a-b4f2-a34ffda9fac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918288057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3918288057
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.956181264
Short name T367
Test name
Test status
Simulation time 2252141824 ps
CPU time 7.41 seconds
Started Feb 29 12:47:00 PM PST 24
Finished Feb 29 12:47:09 PM PST 24
Peak memory 200620 kb
Host smart-1ba0fe5f-d020-4c13-bd5b-b05dd3a54b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956181264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.956181264
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1579402000
Short name T529
Test name
Test status
Simulation time 109871633 ps
CPU time 0.96 seconds
Started Feb 29 12:47:13 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 199980 kb
Host smart-1b51c371-db53-42d8-b78a-61a15389ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579402000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1579402000
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4150555202
Short name T186
Test name
Test status
Simulation time 117772177 ps
CPU time 1.22 seconds
Started Feb 29 12:47:02 PM PST 24
Finished Feb 29 12:47:04 PM PST 24
Peak memory 200264 kb
Host smart-09299f2a-6da2-4659-a9d4-1b621e3f7116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150555202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4150555202
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3918200962
Short name T93
Test name
Test status
Simulation time 8628640393 ps
CPU time 28.93 seconds
Started Feb 29 12:47:03 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 200448 kb
Host smart-6215092a-0cf7-444e-b6db-88e5610c5ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918200962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3918200962
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.274787308
Short name T315
Test name
Test status
Simulation time 108949065 ps
CPU time 1.37 seconds
Started Feb 29 12:47:05 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 200036 kb
Host smart-fcd2f432-b15c-4090-bff8-ee9f0b936d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274787308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.274787308
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1497737135
Short name T424
Test name
Test status
Simulation time 90942058 ps
CPU time 0.82 seconds
Started Feb 29 12:47:08 PM PST 24
Finished Feb 29 12:47:10 PM PST 24
Peak memory 200148 kb
Host smart-3aa302ba-93c9-4a71-acae-7902540cd598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497737135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1497737135
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.59028125
Short name T251
Test name
Test status
Simulation time 66606401 ps
CPU time 0.8 seconds
Started Feb 29 12:47:27 PM PST 24
Finished Feb 29 12:47:28 PM PST 24
Peak memory 199916 kb
Host smart-aebf73e7-ecd0-458f-80bd-28e7d319ecd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59028125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.59028125
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2707821746
Short name T41
Test name
Test status
Simulation time 1231448633 ps
CPU time 5.85 seconds
Started Feb 29 12:47:02 PM PST 24
Finished Feb 29 12:47:09 PM PST 24
Peak memory 221996 kb
Host smart-028701e1-d36c-4d65-9a5b-596d9df1356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707821746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2707821746
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3669243822
Short name T171
Test name
Test status
Simulation time 243375882 ps
CPU time 1.07 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:11 PM PST 24
Peak memory 217196 kb
Host smart-d512a657-4721-43e0-9ac2-35784f21a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669243822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3669243822
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4061983954
Short name T499
Test name
Test status
Simulation time 140488034 ps
CPU time 0.82 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:01 PM PST 24
Peak memory 199848 kb
Host smart-0564e5a8-a731-4e5b-a76f-ad34f8a2a159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061983954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4061983954
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2025926881
Short name T73
Test name
Test status
Simulation time 1818085676 ps
CPU time 7.16 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:47:39 PM PST 24
Peak memory 200296 kb
Host smart-1e37af6f-c815-415e-9443-66752d7eda96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025926881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2025926881
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2225046444
Short name T353
Test name
Test status
Simulation time 164288410 ps
CPU time 1.15 seconds
Started Feb 29 12:46:57 PM PST 24
Finished Feb 29 12:46:59 PM PST 24
Peak memory 200040 kb
Host smart-d1c56ef5-9705-4429-865d-fc3df2c47e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225046444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2225046444
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.728691223
Short name T182
Test name
Test status
Simulation time 110040719 ps
CPU time 1.35 seconds
Started Feb 29 12:47:15 PM PST 24
Finished Feb 29 12:47:17 PM PST 24
Peak memory 200264 kb
Host smart-cc3ff34c-54c1-4cb5-bc4b-5a035431aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728691223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.728691223
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2197046746
Short name T547
Test name
Test status
Simulation time 6272416707 ps
CPU time 20.31 seconds
Started Feb 29 12:47:07 PM PST 24
Finished Feb 29 12:47:28 PM PST 24
Peak memory 200400 kb
Host smart-46718a98-efeb-4343-b447-e8fb9b292c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197046746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2197046746
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1169393181
Short name T383
Test name
Test status
Simulation time 309374645 ps
CPU time 2.12 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:02 PM PST 24
Peak memory 200108 kb
Host smart-d64b26b3-f796-419c-b61e-81fc6317639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169393181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1169393181
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1455569334
Short name T422
Test name
Test status
Simulation time 92206643 ps
CPU time 0.94 seconds
Started Feb 29 12:47:10 PM PST 24
Finished Feb 29 12:47:13 PM PST 24
Peak memory 200076 kb
Host smart-cde39629-a28a-4498-b9d9-2385b28600c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455569334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1455569334
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1508194361
Short name T452
Test name
Test status
Simulation time 61413452 ps
CPU time 0.71 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 199916 kb
Host smart-6c3774c4-aded-46d6-b7af-5331f710be8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508194361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1508194361
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.600127390
Short name T26
Test name
Test status
Simulation time 1226840130 ps
CPU time 5.35 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:05 PM PST 24
Peak memory 221420 kb
Host smart-35d81ebd-5753-460c-8311-696409652f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600127390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.600127390
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2538833523
Short name T448
Test name
Test status
Simulation time 244617689 ps
CPU time 1.07 seconds
Started Feb 29 12:47:10 PM PST 24
Finished Feb 29 12:47:13 PM PST 24
Peak memory 217324 kb
Host smart-3df19d93-d288-4dc7-bf58-bca395182db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538833523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2538833523
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2774147482
Short name T19
Test name
Test status
Simulation time 207030158 ps
CPU time 0.89 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 199840 kb
Host smart-344ab233-40c5-41f2-aff3-b4ec51b6ab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774147482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2774147482
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1464905034
Short name T253
Test name
Test status
Simulation time 860576405 ps
CPU time 4.37 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 200296 kb
Host smart-8f84e4c2-7b96-45c9-a3c8-f443167434d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464905034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1464905034
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.446237896
Short name T476
Test name
Test status
Simulation time 133358124 ps
CPU time 1.09 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:11 PM PST 24
Peak memory 200012 kb
Host smart-7db81cef-135f-458e-b3a2-b06cac7703ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446237896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.446237896
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3872449352
Short name T360
Test name
Test status
Simulation time 231373217 ps
CPU time 1.45 seconds
Started Feb 29 12:47:04 PM PST 24
Finished Feb 29 12:47:06 PM PST 24
Peak memory 200228 kb
Host smart-ec9dad92-d568-4fd2-aedf-642cd10c7f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872449352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3872449352
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3378044303
Short name T262
Test name
Test status
Simulation time 18747597529 ps
CPU time 64.89 seconds
Started Feb 29 12:47:21 PM PST 24
Finished Feb 29 12:48:26 PM PST 24
Peak memory 200388 kb
Host smart-5574d9de-41d8-42ca-bab0-a18d73be4190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378044303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3378044303
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.883563868
Short name T299
Test name
Test status
Simulation time 263790736 ps
CPU time 1.93 seconds
Started Feb 29 12:47:19 PM PST 24
Finished Feb 29 12:47:21 PM PST 24
Peak memory 199984 kb
Host smart-1c3f7a16-0bd2-4ea3-bd3f-b71077af684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883563868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.883563868
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1725269468
Short name T244
Test name
Test status
Simulation time 77570332 ps
CPU time 0.75 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:14 PM PST 24
Peak memory 200100 kb
Host smart-ad248fb9-ae18-415d-8ec4-67312411233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725269468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1725269468
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1929762301
Short name T140
Test name
Test status
Simulation time 65108875 ps
CPU time 0.71 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 199916 kb
Host smart-0236f81d-a048-4ad2-a32c-7e0cd43fdbf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929762301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1929762301
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3295341639
Short name T380
Test name
Test status
Simulation time 1229875790 ps
CPU time 5.73 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:20 PM PST 24
Peak memory 217352 kb
Host smart-2c7c4d9a-6d45-4bf9-9696-49fd24f0a2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295341639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3295341639
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1674135859
Short name T243
Test name
Test status
Simulation time 244612643 ps
CPU time 1.04 seconds
Started Feb 29 12:47:25 PM PST 24
Finished Feb 29 12:47:27 PM PST 24
Peak memory 217432 kb
Host smart-207e05a4-c4e9-478e-84d1-63ec1a592e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674135859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1674135859
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.4039161849
Short name T284
Test name
Test status
Simulation time 116077492 ps
CPU time 0.77 seconds
Started Feb 29 12:47:08 PM PST 24
Finished Feb 29 12:47:09 PM PST 24
Peak memory 199788 kb
Host smart-0d2c5aac-e1b1-4013-893c-1601d4562568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039161849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.4039161849
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2486734111
Short name T92
Test name
Test status
Simulation time 847629308 ps
CPU time 3.98 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 200252 kb
Host smart-9b85c5af-71cc-46c8-a4c2-10dc0881714c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486734111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2486734111
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1378255326
Short name T145
Test name
Test status
Simulation time 107364181 ps
CPU time 1.07 seconds
Started Feb 29 12:47:06 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 200016 kb
Host smart-f81af6c6-aba1-42b6-9fe8-7b7932f7e874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378255326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1378255326
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3097888130
Short name T165
Test name
Test status
Simulation time 115397558 ps
CPU time 1.14 seconds
Started Feb 29 12:47:02 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 200300 kb
Host smart-a1a082d4-5d9a-4e33-8ee4-5f7c50c5d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097888130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3097888130
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2561961265
Short name T68
Test name
Test status
Simulation time 5930421319 ps
CPU time 19.41 seconds
Started Feb 29 12:47:08 PM PST 24
Finished Feb 29 12:47:27 PM PST 24
Peak memory 200396 kb
Host smart-7c7fab7d-cf57-450a-9936-628dda8300e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561961265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2561961265
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1152345891
Short name T298
Test name
Test status
Simulation time 332084659 ps
CPU time 2.17 seconds
Started Feb 29 12:47:19 PM PST 24
Finished Feb 29 12:47:21 PM PST 24
Peak memory 200100 kb
Host smart-d09ef678-5db6-4dcc-8b40-5afdf57379af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152345891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1152345891
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4127489156
Short name T60
Test name
Test status
Simulation time 127615331 ps
CPU time 0.97 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 200000 kb
Host smart-f2731c2d-f751-4e88-8112-75e70c5bb26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127489156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4127489156
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.131961023
Short name T235
Test name
Test status
Simulation time 88741574 ps
CPU time 0.78 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 199900 kb
Host smart-87af5d12-eb3b-42f0-84d5-efe0a241aacd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131961023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.131961023
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2806863857
Short name T233
Test name
Test status
Simulation time 2342889920 ps
CPU time 8.04 seconds
Started Feb 29 12:46:40 PM PST 24
Finished Feb 29 12:46:49 PM PST 24
Peak memory 222156 kb
Host smart-573285ab-86ff-4304-8d96-b9311cc605a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806863857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2806863857
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1652583961
Short name T234
Test name
Test status
Simulation time 250485133 ps
CPU time 1.05 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 217464 kb
Host smart-1c39794f-e0f2-4110-8390-973121222a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652583961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1652583961
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.164953678
Short name T16
Test name
Test status
Simulation time 133781565 ps
CPU time 0.76 seconds
Started Feb 29 12:46:53 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 199920 kb
Host smart-84e86c45-b92d-40e1-aa65-221ab933b1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164953678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.164953678
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3448273369
Short name T343
Test name
Test status
Simulation time 1721509288 ps
CPU time 6.22 seconds
Started Feb 29 12:46:45 PM PST 24
Finished Feb 29 12:46:51 PM PST 24
Peak memory 200264 kb
Host smart-798dac4c-edb1-4444-9f08-ce6b6f88e2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448273369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3448273369
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.640161321
Short name T263
Test name
Test status
Simulation time 108609756 ps
CPU time 1.01 seconds
Started Feb 29 12:46:42 PM PST 24
Finished Feb 29 12:46:43 PM PST 24
Peak memory 200104 kb
Host smart-bd5926d3-ce8c-4bf6-89d4-2d0e16738862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640161321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.640161321
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.118856810
Short name T11
Test name
Test status
Simulation time 116158806 ps
CPU time 1.17 seconds
Started Feb 29 12:46:37 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 200184 kb
Host smart-53565ebc-a709-450e-8a56-63354147b75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118856810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.118856810
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2075924742
Short name T419
Test name
Test status
Simulation time 3477810474 ps
CPU time 12.34 seconds
Started Feb 29 12:46:51 PM PST 24
Finished Feb 29 12:47:04 PM PST 24
Peak memory 200404 kb
Host smart-95e0668e-1671-4085-86ee-faffcdab56d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075924742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2075924742
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.255300011
Short name T440
Test name
Test status
Simulation time 292036916 ps
CPU time 2.01 seconds
Started Feb 29 12:46:40 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 200072 kb
Host smart-e99eb20e-45df-43ec-a14c-b0038c48ad25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255300011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.255300011
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.4111195347
Short name T218
Test name
Test status
Simulation time 85369132 ps
CPU time 0.81 seconds
Started Feb 29 12:46:29 PM PST 24
Finished Feb 29 12:46:30 PM PST 24
Peak memory 200100 kb
Host smart-1cf41dde-06c1-4773-83e9-cef9446753ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111195347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4111195347
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1840550603
Short name T527
Test name
Test status
Simulation time 84247503 ps
CPU time 0.75 seconds
Started Feb 29 12:47:14 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 199872 kb
Host smart-dd8df98d-e588-499c-9d05-be0be466dc0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840550603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1840550603
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2003660864
Short name T220
Test name
Test status
Simulation time 1892091237 ps
CPU time 6.95 seconds
Started Feb 29 12:47:04 PM PST 24
Finished Feb 29 12:47:11 PM PST 24
Peak memory 217920 kb
Host smart-ce53b653-bc6f-481f-8bc8-a35ec11a64c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003660864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2003660864
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2389332965
Short name T133
Test name
Test status
Simulation time 244528667 ps
CPU time 1.12 seconds
Started Feb 29 12:47:07 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 217464 kb
Host smart-f8ab7180-9371-4115-aa36-557defeb8adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389332965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2389332965
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2987688826
Short name T304
Test name
Test status
Simulation time 159199064 ps
CPU time 0.82 seconds
Started Feb 29 12:47:27 PM PST 24
Finished Feb 29 12:47:29 PM PST 24
Peak memory 199912 kb
Host smart-336f59f5-6050-47b4-8a80-0a387787f252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987688826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2987688826
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2021968961
Short name T523
Test name
Test status
Simulation time 1925008884 ps
CPU time 6.92 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:20 PM PST 24
Peak memory 200264 kb
Host smart-f50ecba5-e5eb-4bd9-995b-4ca771f787ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021968961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2021968961
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3297153247
Short name T63
Test name
Test status
Simulation time 111908659 ps
CPU time 0.96 seconds
Started Feb 29 12:47:28 PM PST 24
Finished Feb 29 12:47:30 PM PST 24
Peak memory 199956 kb
Host smart-722586fc-ad71-4aa4-96cc-9ddbbde549cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297153247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3297153247
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3165877364
Short name T34
Test name
Test status
Simulation time 245070500 ps
CPU time 1.5 seconds
Started Feb 29 12:47:26 PM PST 24
Finished Feb 29 12:47:28 PM PST 24
Peak memory 200276 kb
Host smart-9c7164d3-19bb-4ec3-99fa-4b3a8b6c0fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165877364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3165877364
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2724407268
Short name T313
Test name
Test status
Simulation time 1520260470 ps
CPU time 7.22 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:37 PM PST 24
Peak memory 200304 kb
Host smart-59b4637f-03a9-4a32-b7f0-dd3daac598aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724407268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2724407268
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3173301621
Short name T467
Test name
Test status
Simulation time 150653418 ps
CPU time 1.16 seconds
Started Feb 29 12:47:26 PM PST 24
Finished Feb 29 12:47:28 PM PST 24
Peak memory 200080 kb
Host smart-38d2e633-fac4-4c52-909e-151811aa010a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173301621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3173301621
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3881062778
Short name T468
Test name
Test status
Simulation time 85743988 ps
CPU time 0.85 seconds
Started Feb 29 12:47:27 PM PST 24
Finished Feb 29 12:47:30 PM PST 24
Peak memory 199924 kb
Host smart-94adfd3f-3285-4917-8b02-4d985f8ee421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881062778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3881062778
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.637824471
Short name T27
Test name
Test status
Simulation time 1219084765 ps
CPU time 5.7 seconds
Started Feb 29 12:47:46 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 219028 kb
Host smart-b6105d79-b7f5-4bb0-9b51-abee21d33ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637824471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.637824471
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3739730956
Short name T208
Test name
Test status
Simulation time 244082930 ps
CPU time 1.08 seconds
Started Feb 29 12:47:06 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 217460 kb
Host smart-a18091f6-4139-4588-870a-a9055447b784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739730956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3739730956
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3009803706
Short name T417
Test name
Test status
Simulation time 151234300 ps
CPU time 0.77 seconds
Started Feb 29 12:47:44 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 199756 kb
Host smart-2d59120d-972c-41d0-9062-8324b45f5c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009803706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3009803706
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3167191793
Short name T90
Test name
Test status
Simulation time 1721212688 ps
CPU time 6.9 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:22 PM PST 24
Peak memory 200336 kb
Host smart-dceb8d82-03ed-4790-80f7-5a254bb8dc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167191793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3167191793
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.872049197
Short name T493
Test name
Test status
Simulation time 150689491 ps
CPU time 1.15 seconds
Started Feb 29 12:47:37 PM PST 24
Finished Feb 29 12:47:38 PM PST 24
Peak memory 200184 kb
Host smart-44963552-a65d-4355-a9fb-031c2b008153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872049197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.872049197
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.445489391
Short name T444
Test name
Test status
Simulation time 208232333 ps
CPU time 1.34 seconds
Started Feb 29 12:47:22 PM PST 24
Finished Feb 29 12:47:23 PM PST 24
Peak memory 200232 kb
Host smart-8f493d3b-3cd4-4a86-a06b-b88836dc5cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445489391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.445489391
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1739728620
Short name T300
Test name
Test status
Simulation time 13457388788 ps
CPU time 44.64 seconds
Started Feb 29 12:47:22 PM PST 24
Finished Feb 29 12:48:07 PM PST 24
Peak memory 200412 kb
Host smart-8cf2999f-7fe7-479c-a57b-bfa80fa1d9b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739728620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1739728620
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3708254191
Short name T177
Test name
Test status
Simulation time 122077464 ps
CPU time 1.47 seconds
Started Feb 29 12:47:06 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 200104 kb
Host smart-b97d7d4e-da2b-4a08-a2af-316e6a3ecda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708254191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3708254191
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.78832764
Short name T168
Test name
Test status
Simulation time 191075846 ps
CPU time 1.25 seconds
Started Feb 29 12:47:07 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 200116 kb
Host smart-266e864f-9300-49d7-8d98-a7d269b50faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78832764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.78832764
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3811857283
Short name T411
Test name
Test status
Simulation time 76662097 ps
CPU time 0.78 seconds
Started Feb 29 12:47:33 PM PST 24
Finished Feb 29 12:47:34 PM PST 24
Peak memory 199924 kb
Host smart-fc7a437b-2517-49c0-9005-31aaee4cadcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811857283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3811857283
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2928716296
Short name T28
Test name
Test status
Simulation time 1225921876 ps
CPU time 6.35 seconds
Started Feb 29 12:47:42 PM PST 24
Finished Feb 29 12:47:49 PM PST 24
Peak memory 217976 kb
Host smart-4b13a35f-6ac1-447f-9572-d870f8d8218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928716296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2928716296
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.623091865
Short name T139
Test name
Test status
Simulation time 244158447 ps
CPU time 1.05 seconds
Started Feb 29 12:47:18 PM PST 24
Finished Feb 29 12:47:20 PM PST 24
Peak memory 217452 kb
Host smart-909cab6b-f989-4187-9022-2449a878874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623091865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.623091865
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2077364734
Short name T161
Test name
Test status
Simulation time 173155931 ps
CPU time 0.85 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:15 PM PST 24
Peak memory 199636 kb
Host smart-2786b161-39d4-4236-a3c9-18944e0ac445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077364734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2077364734
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.543981642
Short name T302
Test name
Test status
Simulation time 1382825600 ps
CPU time 5.06 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:19 PM PST 24
Peak memory 199984 kb
Host smart-51a22d46-0125-4520-b58b-925bfd546b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543981642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.543981642
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3102358140
Short name T197
Test name
Test status
Simulation time 110535013 ps
CPU time 1 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:14 PM PST 24
Peak memory 200096 kb
Host smart-30d09840-098d-4f87-96c9-7ba82fee46e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102358140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3102358140
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1361740347
Short name T432
Test name
Test status
Simulation time 233359215 ps
CPU time 1.39 seconds
Started Feb 29 12:47:38 PM PST 24
Finished Feb 29 12:47:39 PM PST 24
Peak memory 200424 kb
Host smart-a95dddad-56b2-4f98-bdc0-5ea85f7e2698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361740347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1361740347
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2414079885
Short name T405
Test name
Test status
Simulation time 9551863345 ps
CPU time 35.12 seconds
Started Feb 29 12:47:10 PM PST 24
Finished Feb 29 12:47:47 PM PST 24
Peak memory 200424 kb
Host smart-d3dbca13-8882-4b0f-b3db-043c160e9c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414079885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2414079885
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1183467509
Short name T520
Test name
Test status
Simulation time 303208312 ps
CPU time 1.96 seconds
Started Feb 29 12:47:05 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 200104 kb
Host smart-366a3058-51aa-42ec-9399-8349f380572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183467509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1183467509
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2228709482
Short name T129
Test name
Test status
Simulation time 155026472 ps
CPU time 1.3 seconds
Started Feb 29 12:47:07 PM PST 24
Finished Feb 29 12:47:09 PM PST 24
Peak memory 200104 kb
Host smart-6aa54d77-71da-4214-8af2-badd20cb5a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228709482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2228709482
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2058358791
Short name T163
Test name
Test status
Simulation time 70623541 ps
CPU time 0.79 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:14 PM PST 24
Peak memory 199932 kb
Host smart-11152f32-12d7-456c-9536-44d2e294f536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058358791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2058358791
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2538524993
Short name T332
Test name
Test status
Simulation time 1899501735 ps
CPU time 7.04 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:37 PM PST 24
Peak memory 217440 kb
Host smart-c09deb2c-861f-4e1c-9017-7bf5e496975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538524993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2538524993
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4030640986
Short name T151
Test name
Test status
Simulation time 244034365 ps
CPU time 1.05 seconds
Started Feb 29 12:47:23 PM PST 24
Finished Feb 29 12:47:25 PM PST 24
Peak memory 217416 kb
Host smart-d8a25a8b-3bfb-4122-8b7d-bb97bbd81b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030640986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4030640986
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2165560578
Short name T516
Test name
Test status
Simulation time 154955789 ps
CPU time 0.85 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 199964 kb
Host smart-d75fea56-79ac-4d83-ad4e-5633b5103351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165560578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2165560578
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.512912495
Short name T491
Test name
Test status
Simulation time 1447630609 ps
CPU time 5.86 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 200308 kb
Host smart-457a00d8-0d05-4cfc-b470-5f1f22db5011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512912495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.512912495
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1956937972
Short name T228
Test name
Test status
Simulation time 113034976 ps
CPU time 1.04 seconds
Started Feb 29 12:47:17 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 200104 kb
Host smart-3db8c1be-0dab-4747-98f3-a08e7bcd87fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956937972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1956937972
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1013354825
Short name T434
Test name
Test status
Simulation time 206698666 ps
CPU time 1.37 seconds
Started Feb 29 12:47:28 PM PST 24
Finished Feb 29 12:47:30 PM PST 24
Peak memory 200364 kb
Host smart-b33850db-d0d4-4a03-a0fd-8f350135a0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013354825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1013354825
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3193465936
Short name T256
Test name
Test status
Simulation time 783783974 ps
CPU time 3.43 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 200308 kb
Host smart-9bd649ba-91c6-49c0-be78-e31aa39fb400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193465936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3193465936
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1374388285
Short name T535
Test name
Test status
Simulation time 320999438 ps
CPU time 2.11 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 200088 kb
Host smart-d56c4bd3-63df-4dfb-86f6-fd0137937305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374388285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1374388285
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3180894372
Short name T507
Test name
Test status
Simulation time 183411326 ps
CPU time 1.13 seconds
Started Feb 29 12:47:33 PM PST 24
Finished Feb 29 12:47:34 PM PST 24
Peak memory 200108 kb
Host smart-78dfdc93-f9e7-4c38-974f-789a9bfcf5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180894372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3180894372
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2541694475
Short name T429
Test name
Test status
Simulation time 86232313 ps
CPU time 0.83 seconds
Started Feb 29 12:47:27 PM PST 24
Finished Feb 29 12:47:28 PM PST 24
Peak memory 200120 kb
Host smart-7d35d02d-b82d-4249-a6ee-a1766013c2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541694475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2541694475
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.341825267
Short name T485
Test name
Test status
Simulation time 1229546861 ps
CPU time 5.47 seconds
Started Feb 29 12:47:26 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 220924 kb
Host smart-35e8a8e8-fdc9-4cdf-95a7-f12933802862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341825267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.341825267
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.670692635
Short name T340
Test name
Test status
Simulation time 245202029 ps
CPU time 1.02 seconds
Started Feb 29 12:47:14 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 217372 kb
Host smart-eaaecf74-2bcf-4d73-8a0c-171534228597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670692635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.670692635
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2601237715
Short name T480
Test name
Test status
Simulation time 195575957 ps
CPU time 0.95 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:10 PM PST 24
Peak memory 199808 kb
Host smart-1cb6b212-b056-4a78-8f92-a80c6380456d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601237715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2601237715
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2599380156
Short name T541
Test name
Test status
Simulation time 1637259109 ps
CPU time 5.87 seconds
Started Feb 29 12:47:37 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 200304 kb
Host smart-2ab69fbd-9363-496f-aa4f-38f36f59f649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599380156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2599380156
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.596773971
Short name T128
Test name
Test status
Simulation time 152273123 ps
CPU time 1.05 seconds
Started Feb 29 12:47:25 PM PST 24
Finished Feb 29 12:47:27 PM PST 24
Peak memory 200100 kb
Host smart-6dceb1c7-1e5e-4753-8239-b0f2d03caeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596773971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.596773971
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3310027174
Short name T72
Test name
Test status
Simulation time 113077196 ps
CPU time 1.14 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:15 PM PST 24
Peak memory 200300 kb
Host smart-7cc2529f-70ae-4327-ad9e-7c8ca3b52d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310027174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3310027174
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3269537725
Short name T66
Test name
Test status
Simulation time 3743553730 ps
CPU time 16.38 seconds
Started Feb 29 12:47:13 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 200412 kb
Host smart-3c5ccafa-b626-4977-a544-b9369f460539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269537725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3269537725
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4095097479
Short name T181
Test name
Test status
Simulation time 128237374 ps
CPU time 1.45 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:14 PM PST 24
Peak memory 200084 kb
Host smart-5fd95a5f-083e-4ffa-aea3-d6ae35d6a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095097479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4095097479
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.4086283667
Short name T65
Test name
Test status
Simulation time 151863171 ps
CPU time 1.14 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:15 PM PST 24
Peak memory 200084 kb
Host smart-dd1e9d3a-f897-41bd-a061-a53cf993838e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086283667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.4086283667
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.451219314
Short name T217
Test name
Test status
Simulation time 71359706 ps
CPU time 0.72 seconds
Started Feb 29 12:47:35 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 199924 kb
Host smart-fc1b0fe5-a38a-40be-b681-715d0d9eb09b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451219314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.451219314
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3107049029
Short name T513
Test name
Test status
Simulation time 1225495474 ps
CPU time 5.63 seconds
Started Feb 29 12:47:25 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 217648 kb
Host smart-ed767c3c-55ff-46a3-b3c6-2be777ba021b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107049029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3107049029
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3201382909
Short name T229
Test name
Test status
Simulation time 245078622 ps
CPU time 1.01 seconds
Started Feb 29 12:47:17 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 217360 kb
Host smart-d3dc3646-c155-4a09-94fb-6139cd2e438f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201382909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3201382909
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3262175717
Short name T428
Test name
Test status
Simulation time 185371341 ps
CPU time 0.92 seconds
Started Feb 29 12:47:35 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 200096 kb
Host smart-79ef14a2-041c-4bb7-ac93-9ae4f57be295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262175717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3262175717
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2767850651
Short name T314
Test name
Test status
Simulation time 890083530 ps
CPU time 4.52 seconds
Started Feb 29 12:47:10 PM PST 24
Finished Feb 29 12:47:17 PM PST 24
Peak memory 200308 kb
Host smart-174bc9ad-1cdd-48fb-a527-e39993b2d082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767850651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2767850651
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3796200164
Short name T349
Test name
Test status
Simulation time 155357294 ps
CPU time 1.07 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 200096 kb
Host smart-cd599606-eb46-400a-8f55-578ff1efd273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796200164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3796200164
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.899172095
Short name T415
Test name
Test status
Simulation time 115156881 ps
CPU time 1.19 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 200340 kb
Host smart-b1d541f7-87b2-4bd2-9ac2-ff46eb335032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899172095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.899172095
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2048954425
Short name T269
Test name
Test status
Simulation time 6890756279 ps
CPU time 22.13 seconds
Started Feb 29 12:47:44 PM PST 24
Finished Feb 29 12:48:07 PM PST 24
Peak memory 200376 kb
Host smart-c7337891-c7d0-46eb-af4d-e70854d2e162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048954425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2048954425
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3882587524
Short name T227
Test name
Test status
Simulation time 290658263 ps
CPU time 1.95 seconds
Started Feb 29 12:47:36 PM PST 24
Finished Feb 29 12:47:38 PM PST 24
Peak memory 200072 kb
Host smart-a3efe01e-d08f-48d8-b59b-6f18347808fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882587524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3882587524
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2327262361
Short name T508
Test name
Test status
Simulation time 117993055 ps
CPU time 0.92 seconds
Started Feb 29 12:47:49 PM PST 24
Finished Feb 29 12:47:50 PM PST 24
Peak memory 200104 kb
Host smart-6a9ee4b8-6774-4f48-b60b-0023336df0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327262361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2327262361
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.315277934
Short name T368
Test name
Test status
Simulation time 62530519 ps
CPU time 0.78 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 199856 kb
Host smart-bb2e8894-05aa-4a14-a70d-80fd533bef86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315277934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.315277934
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2563846903
Short name T306
Test name
Test status
Simulation time 2148004968 ps
CPU time 7.73 seconds
Started Feb 29 12:47:17 PM PST 24
Finished Feb 29 12:47:25 PM PST 24
Peak memory 222180 kb
Host smart-23374479-3ad2-493e-9ea8-9c672883e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563846903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2563846903
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.606238351
Short name T131
Test name
Test status
Simulation time 243788885 ps
CPU time 1.15 seconds
Started Feb 29 12:47:16 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 217436 kb
Host smart-e9ab677c-a5db-467e-ae07-4fc5e8886f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606238351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.606238351
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.128131623
Short name T503
Test name
Test status
Simulation time 83152617 ps
CPU time 0.69 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 199896 kb
Host smart-c1891d73-512c-4488-a525-234047470e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128131623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.128131623
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1393415768
Short name T308
Test name
Test status
Simulation time 1585078596 ps
CPU time 6.17 seconds
Started Feb 29 12:47:15 PM PST 24
Finished Feb 29 12:47:22 PM PST 24
Peak memory 200344 kb
Host smart-323ea6e8-01c3-49f7-91d2-2aee77e04d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393415768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1393415768
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.4213057118
Short name T431
Test name
Test status
Simulation time 168124419 ps
CPU time 1.18 seconds
Started Feb 29 12:47:14 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 200096 kb
Host smart-32437153-287d-4eed-a3b5-c6fe8771bce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213057118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.4213057118
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.727986035
Short name T58
Test name
Test status
Simulation time 205772773 ps
CPU time 1.39 seconds
Started Feb 29 12:47:15 PM PST 24
Finished Feb 29 12:47:17 PM PST 24
Peak memory 200304 kb
Host smart-d923c0ed-4527-43c5-9e17-abb3e410c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727986035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.727986035
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2500084606
Short name T325
Test name
Test status
Simulation time 372997177 ps
CPU time 2.55 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:37 PM PST 24
Peak memory 200072 kb
Host smart-14419fef-69df-42b6-8092-af91af34f31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500084606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2500084606
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.736404262
Short name T250
Test name
Test status
Simulation time 97148091 ps
CPU time 0.93 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 200056 kb
Host smart-ba019670-b721-4368-abf3-7a10529351ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736404262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.736404262
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1868161323
Short name T407
Test name
Test status
Simulation time 70949228 ps
CPU time 0.74 seconds
Started Feb 29 12:47:38 PM PST 24
Finished Feb 29 12:47:38 PM PST 24
Peak memory 199956 kb
Host smart-f0c8b686-e8da-4762-8d2d-1864479030d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868161323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1868161323
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1115410379
Short name T39
Test name
Test status
Simulation time 1229456919 ps
CPU time 5.83 seconds
Started Feb 29 12:47:13 PM PST 24
Finished Feb 29 12:47:21 PM PST 24
Peak memory 217348 kb
Host smart-d73a6820-4299-4ee4-bf81-090d4d799862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115410379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1115410379
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2196853314
Short name T510
Test name
Test status
Simulation time 244949922 ps
CPU time 1.04 seconds
Started Feb 29 12:47:31 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 217436 kb
Host smart-5a060cb8-9e06-43df-99b6-3fced4d82be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196853314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2196853314
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.769123125
Short name T226
Test name
Test status
Simulation time 206494045 ps
CPU time 0.89 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 199868 kb
Host smart-ca499de5-3b94-4e19-9c00-fdee637ee7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769123125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.769123125
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2537220025
Short name T408
Test name
Test status
Simulation time 1021112624 ps
CPU time 4.95 seconds
Started Feb 29 12:47:31 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 200320 kb
Host smart-dcead5e7-1776-4d8f-a9e5-0e20bee78021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537220025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2537220025
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2091342398
Short name T538
Test name
Test status
Simulation time 142746451 ps
CPU time 1.06 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 200012 kb
Host smart-ce9bebda-a497-46d9-9d7d-89c62b69261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091342398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2091342398
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.522200701
Short name T305
Test name
Test status
Simulation time 206571619 ps
CPU time 1.31 seconds
Started Feb 29 12:47:39 PM PST 24
Finished Feb 29 12:47:40 PM PST 24
Peak memory 200288 kb
Host smart-1e3f3cb5-404e-4311-813e-14ca54342fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522200701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.522200701
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2120452875
Short name T259
Test name
Test status
Simulation time 8007216165 ps
CPU time 28.93 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:42 PM PST 24
Peak memory 200400 kb
Host smart-c3adc18c-9b49-4f4b-9a04-9146b1869ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120452875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2120452875
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1387299902
Short name T120
Test name
Test status
Simulation time 504250779 ps
CPU time 2.49 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 200024 kb
Host smart-46872ee3-d953-4d80-879e-d55c580a71c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387299902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1387299902
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3659104276
Short name T135
Test name
Test status
Simulation time 81821761 ps
CPU time 0.83 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:47:54 PM PST 24
Peak memory 200076 kb
Host smart-e4e0ccc7-7377-4845-8a70-c26027acf07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659104276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3659104276
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3785086082
Short name T296
Test name
Test status
Simulation time 83733966 ps
CPU time 0.82 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:15 PM PST 24
Peak memory 199912 kb
Host smart-cb103b2c-b443-43ff-871f-ca3c7cd29dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785086082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3785086082
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3673468380
Short name T283
Test name
Test status
Simulation time 1892343078 ps
CPU time 6.87 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:17 PM PST 24
Peak memory 217588 kb
Host smart-81b43751-2b64-4a04-873a-cb433c91f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673468380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3673468380
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.688887404
Short name T320
Test name
Test status
Simulation time 244784637 ps
CPU time 1.07 seconds
Started Feb 29 12:47:14 PM PST 24
Finished Feb 29 12:47:20 PM PST 24
Peak memory 217428 kb
Host smart-c153fef7-0601-411b-b781-5f70922adaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688887404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.688887404
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3224972358
Short name T209
Test name
Test status
Simulation time 207859773 ps
CPU time 0.88 seconds
Started Feb 29 12:47:13 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 199896 kb
Host smart-94ab8770-dcd1-4ac5-97ce-e0c12f0fdbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224972358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3224972358
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3815944509
Short name T248
Test name
Test status
Simulation time 992922903 ps
CPU time 5.43 seconds
Started Feb 29 12:47:10 PM PST 24
Finished Feb 29 12:47:17 PM PST 24
Peak memory 200512 kb
Host smart-6de98893-29ab-4328-ad96-eb9de6621c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815944509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3815944509
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3498709822
Short name T460
Test name
Test status
Simulation time 97355769 ps
CPU time 0.94 seconds
Started Feb 29 12:47:11 PM PST 24
Finished Feb 29 12:47:15 PM PST 24
Peak memory 200288 kb
Host smart-a7fed188-854e-48d7-b8c3-ae1ad2ad20be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498709822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3498709822
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2823596449
Short name T69
Test name
Test status
Simulation time 229482171 ps
CPU time 1.48 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 200360 kb
Host smart-b9196fe7-ab1b-409d-b1f6-386f7acbd14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823596449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2823596449
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1921118936
Short name T369
Test name
Test status
Simulation time 2390557591 ps
CPU time 11.29 seconds
Started Feb 29 12:47:26 PM PST 24
Finished Feb 29 12:47:38 PM PST 24
Peak memory 200464 kb
Host smart-fce1c6eb-f7c9-4c81-82f9-672596b72ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921118936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1921118936
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.500662486
Short name T386
Test name
Test status
Simulation time 353951852 ps
CPU time 2.31 seconds
Started Feb 29 12:47:49 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 200344 kb
Host smart-26fd0489-9994-480e-aff8-463204062709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500662486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.500662486
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1423837546
Short name T351
Test name
Test status
Simulation time 116495046 ps
CPU time 0.98 seconds
Started Feb 29 12:47:15 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 200108 kb
Host smart-2adc7422-c74c-4643-8df4-17ed0b1717fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423837546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1423837546
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2486136140
Short name T396
Test name
Test status
Simulation time 65108791 ps
CPU time 0.76 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 199872 kb
Host smart-c458cd01-e893-4b57-b4d6-b74ec681fc5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486136140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2486136140
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2797372040
Short name T364
Test name
Test status
Simulation time 2163920830 ps
CPU time 7.65 seconds
Started Feb 29 12:47:46 PM PST 24
Finished Feb 29 12:47:53 PM PST 24
Peak memory 217548 kb
Host smart-6b25dad3-c5f3-4e07-8783-f294f7d552ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797372040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2797372040
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2080756918
Short name T152
Test name
Test status
Simulation time 244067466 ps
CPU time 1.01 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 217360 kb
Host smart-677c8631-9fb0-40eb-8160-3d2d738d07bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080756918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2080756918
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.414617514
Short name T21
Test name
Test status
Simulation time 172198369 ps
CPU time 0.9 seconds
Started Feb 29 12:47:48 PM PST 24
Finished Feb 29 12:47:49 PM PST 24
Peak memory 199908 kb
Host smart-e0d3804d-550f-4ad7-8b3c-481f9e5c9a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414617514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.414617514
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2450942427
Short name T295
Test name
Test status
Simulation time 679410133 ps
CPU time 3.6 seconds
Started Feb 29 12:47:14 PM PST 24
Finished Feb 29 12:47:19 PM PST 24
Peak memory 200240 kb
Host smart-ece0eb27-1634-4c9c-8556-fcb04d0192db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450942427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2450942427
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2041317832
Short name T157
Test name
Test status
Simulation time 141498240 ps
CPU time 1.09 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 200040 kb
Host smart-c5cefa97-72bd-443c-a180-3d1c22b34ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041317832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2041317832
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.961890880
Short name T328
Test name
Test status
Simulation time 115113340 ps
CPU time 1.14 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 200400 kb
Host smart-3fe35fd4-c8ce-4c0d-826c-9c5528c4cdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961890880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.961890880
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2451568645
Short name T425
Test name
Test status
Simulation time 3143934642 ps
CPU time 14.42 seconds
Started Feb 29 12:47:31 PM PST 24
Finished Feb 29 12:47:46 PM PST 24
Peak memory 200384 kb
Host smart-c5eb64bd-1392-46f3-a365-6933fe472e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451568645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2451568645
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2102857655
Short name T160
Test name
Test status
Simulation time 279792201 ps
CPU time 1.75 seconds
Started Feb 29 12:47:39 PM PST 24
Finished Feb 29 12:47:41 PM PST 24
Peak memory 200104 kb
Host smart-48f156a9-2506-4726-8d9f-d8655d52de04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102857655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2102857655
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1005674660
Short name T1
Test name
Test status
Simulation time 103160832 ps
CPU time 0.91 seconds
Started Feb 29 12:47:31 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 200092 kb
Host smart-d2edaf52-3972-4ef9-8bb7-0de3927042fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005674660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1005674660
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3676393791
Short name T22
Test name
Test status
Simulation time 71446248 ps
CPU time 0.7 seconds
Started Feb 29 12:47:06 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 199912 kb
Host smart-ef19114a-5599-47a8-a2f2-0a01e67cfa61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676393791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3676393791
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3758555097
Short name T323
Test name
Test status
Simulation time 1890930865 ps
CPU time 7.04 seconds
Started Feb 29 12:46:45 PM PST 24
Finished Feb 29 12:46:52 PM PST 24
Peak memory 217368 kb
Host smart-580f9705-d350-4c28-a8eb-58dd7f7732e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758555097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3758555097
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.492949125
Short name T141
Test name
Test status
Simulation time 244779405 ps
CPU time 1.05 seconds
Started Feb 29 12:46:29 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 217364 kb
Host smart-0a5d4e44-ebdd-46df-88d8-bbac69bf1919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492949125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.492949125
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2799943392
Short name T505
Test name
Test status
Simulation time 137613905 ps
CPU time 0.78 seconds
Started Feb 29 12:46:50 PM PST 24
Finished Feb 29 12:46:52 PM PST 24
Peak memory 199920 kb
Host smart-ddd0d322-23ba-48a1-9bec-ad0383b6103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799943392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2799943392
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.884961469
Short name T82
Test name
Test status
Simulation time 1760660652 ps
CPU time 7.05 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:46 PM PST 24
Peak memory 200312 kb
Host smart-154daae4-99b9-47dc-89c7-3a03e1a23abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884961469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.884961469
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1706845035
Short name T55
Test name
Test status
Simulation time 8468591601 ps
CPU time 12.74 seconds
Started Feb 29 12:47:05 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 217220 kb
Host smart-64c6b06c-5c3e-42a7-b38b-a12ccd54b533
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706845035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1706845035
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2103010286
Short name T255
Test name
Test status
Simulation time 97115729 ps
CPU time 1.03 seconds
Started Feb 29 12:46:39 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 200104 kb
Host smart-d93aaf33-ad5f-4703-b2b6-04d808d75d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103010286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2103010286
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.808254974
Short name T437
Test name
Test status
Simulation time 246323177 ps
CPU time 1.46 seconds
Started Feb 29 12:46:54 PM PST 24
Finished Feb 29 12:46:56 PM PST 24
Peak memory 200388 kb
Host smart-0259e7d9-d293-42b3-906d-bc391f162f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808254974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.808254974
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3267917379
Short name T470
Test name
Test status
Simulation time 5765035840 ps
CPU time 20.33 seconds
Started Feb 29 12:46:30 PM PST 24
Finished Feb 29 12:46:50 PM PST 24
Peak memory 200616 kb
Host smart-b6f12087-607b-4e4d-8246-fbe6249e1bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267917379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3267917379
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2747803703
Short name T266
Test name
Test status
Simulation time 121153167 ps
CPU time 1.55 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 200104 kb
Host smart-1547cf3c-2e28-4e3a-9095-26d31d7e3eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747803703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2747803703
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1225988515
Short name T348
Test name
Test status
Simulation time 253701630 ps
CPU time 1.45 seconds
Started Feb 29 12:46:48 PM PST 24
Finished Feb 29 12:46:49 PM PST 24
Peak memory 200036 kb
Host smart-82db245d-ba0d-404f-93e8-7353bfea5917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225988515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1225988515
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2344517129
Short name T335
Test name
Test status
Simulation time 164029554 ps
CPU time 0.97 seconds
Started Feb 29 12:47:16 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 199956 kb
Host smart-f05a4de3-cc29-4055-9176-1a507da3ef1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344517129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2344517129
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.138941611
Short name T239
Test name
Test status
Simulation time 1884287940 ps
CPU time 7.03 seconds
Started Feb 29 12:47:38 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 217420 kb
Host smart-aa33e2d5-1b54-4d4a-adfa-9ee4d8b96df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138941611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.138941611
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1391815976
Short name T189
Test name
Test status
Simulation time 243749753 ps
CPU time 1.08 seconds
Started Feb 29 12:47:35 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 217428 kb
Host smart-55f273d7-445d-49df-a9b8-8db3bfa40b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391815976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1391815976
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2847368463
Short name T20
Test name
Test status
Simulation time 87492766 ps
CPU time 0.74 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 199840 kb
Host smart-766d6848-efc9-4b3a-8f6f-5551f8677510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847368463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2847368463
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3955413859
Short name T274
Test name
Test status
Simulation time 1180707226 ps
CPU time 5.39 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 200336 kb
Host smart-070f7c97-893f-4692-9997-d9696b69f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955413859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3955413859
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3629608100
Short name T271
Test name
Test status
Simulation time 177231496 ps
CPU time 1.22 seconds
Started Feb 29 12:47:22 PM PST 24
Finished Feb 29 12:47:23 PM PST 24
Peak memory 200168 kb
Host smart-8ca65c54-02e5-4d99-bd13-b50415adb706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629608100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3629608100
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1599581499
Short name T205
Test name
Test status
Simulation time 246533978 ps
CPU time 1.46 seconds
Started Feb 29 12:47:33 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 200324 kb
Host smart-0cea5e92-65fb-40e3-9381-7cc9263a7f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599581499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1599581499
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.162219443
Short name T539
Test name
Test status
Simulation time 16658280611 ps
CPU time 59.35 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:48:32 PM PST 24
Peak memory 200380 kb
Host smart-014c4e42-2451-4ec5-9e25-a94933c9b84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162219443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.162219443
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2724712447
Short name T378
Test name
Test status
Simulation time 121901456 ps
CPU time 1.51 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:47:34 PM PST 24
Peak memory 200028 kb
Host smart-87cf0614-170a-46b9-8f83-320aca093397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724712447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2724712447
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2604545818
Short name T270
Test name
Test status
Simulation time 252454979 ps
CPU time 1.31 seconds
Started Feb 29 12:47:15 PM PST 24
Finished Feb 29 12:47:17 PM PST 24
Peak memory 200104 kb
Host smart-4649d93b-ddef-4faf-b7ef-721fea88e8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604545818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2604545818
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.697983180
Short name T212
Test name
Test status
Simulation time 68031097 ps
CPU time 0.73 seconds
Started Feb 29 12:47:33 PM PST 24
Finished Feb 29 12:47:33 PM PST 24
Peak memory 199888 kb
Host smart-e80620f1-ce46-4d47-afbc-511c065e2375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697983180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.697983180
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1079801405
Short name T273
Test name
Test status
Simulation time 1214287575 ps
CPU time 5.97 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 217948 kb
Host smart-15ec26e5-f1c9-4833-bbc8-e4a8a8e7ca6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079801405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1079801405
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.4126957553
Short name T534
Test name
Test status
Simulation time 248529966 ps
CPU time 1.1 seconds
Started Feb 29 12:47:24 PM PST 24
Finished Feb 29 12:47:25 PM PST 24
Peak memory 217356 kb
Host smart-9be4025f-96c2-4b0b-8d13-df00d82a8fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126957553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.4126957553
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.125577130
Short name T15
Test name
Test status
Simulation time 127620089 ps
CPU time 0.76 seconds
Started Feb 29 12:47:37 PM PST 24
Finished Feb 29 12:47:38 PM PST 24
Peak memory 199840 kb
Host smart-28041e8c-a19b-421f-9787-9a38edcab488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125577130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.125577130
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.127469469
Short name T86
Test name
Test status
Simulation time 1977464878 ps
CPU time 6.95 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:37 PM PST 24
Peak memory 199464 kb
Host smart-befc686f-c761-4062-9a2d-50e199ba7d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127469469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.127469469
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2537492423
Short name T331
Test name
Test status
Simulation time 145332912 ps
CPU time 1.11 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 199448 kb
Host smart-132256e1-75ce-4530-99a7-f14b440b20bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537492423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2537492423
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1158796971
Short name T544
Test name
Test status
Simulation time 247246982 ps
CPU time 1.46 seconds
Started Feb 29 12:47:15 PM PST 24
Finished Feb 29 12:47:17 PM PST 24
Peak memory 200296 kb
Host smart-da8635c9-6636-477c-92fe-fb760144b09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158796971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1158796971
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1754563054
Short name T546
Test name
Test status
Simulation time 8819103769 ps
CPU time 32.14 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 200428 kb
Host smart-2c85c264-45a5-43b1-9f86-ad34a308d6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754563054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1754563054
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.183270693
Short name T216
Test name
Test status
Simulation time 477900618 ps
CPU time 2.49 seconds
Started Feb 29 12:47:14 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 200092 kb
Host smart-cb0ce132-70a7-4522-a2ce-de4bec34391a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183270693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.183270693
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.568113064
Short name T12
Test name
Test status
Simulation time 290124366 ps
CPU time 1.45 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 200092 kb
Host smart-96c2cda0-921a-4b16-a1e6-357b12890555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568113064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.568113064
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.4049084075
Short name T146
Test name
Test status
Simulation time 77695344 ps
CPU time 0.74 seconds
Started Feb 29 12:47:27 PM PST 24
Finished Feb 29 12:47:29 PM PST 24
Peak memory 199956 kb
Host smart-fcde49a4-e3c2-4cc6-97db-91592c1b6a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049084075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.4049084075
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2740502939
Short name T311
Test name
Test status
Simulation time 1217042553 ps
CPU time 5.45 seconds
Started Feb 29 12:47:22 PM PST 24
Finished Feb 29 12:47:27 PM PST 24
Peak memory 217328 kb
Host smart-1bb40802-54fc-4564-8424-2d92551db1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740502939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2740502939
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1768549144
Short name T377
Test name
Test status
Simulation time 243828755 ps
CPU time 1.06 seconds
Started Feb 29 12:47:10 PM PST 24
Finished Feb 29 12:47:13 PM PST 24
Peak memory 217196 kb
Host smart-cc3cdeb5-a649-4458-a483-4c84f16f3c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768549144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1768549144
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.823030183
Short name T475
Test name
Test status
Simulation time 155702273 ps
CPU time 0.79 seconds
Started Feb 29 12:47:40 PM PST 24
Finished Feb 29 12:47:41 PM PST 24
Peak memory 199812 kb
Host smart-af8e08aa-2620-4254-b0c6-60ef9affe1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823030183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.823030183
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2838363337
Short name T3
Test name
Test status
Simulation time 1743792157 ps
CPU time 6.63 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:47:39 PM PST 24
Peak memory 200212 kb
Host smart-214e4f22-bdf3-4608-a8e6-5804c74b9c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838363337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2838363337
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.4043347595
Short name T172
Test name
Test status
Simulation time 173906259 ps
CPU time 1.13 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 200072 kb
Host smart-8e125d02-4526-466c-a18c-9c9644ad3fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043347595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.4043347595
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3265831871
Short name T414
Test name
Test status
Simulation time 126572611 ps
CPU time 1.16 seconds
Started Feb 29 12:47:48 PM PST 24
Finished Feb 29 12:47:49 PM PST 24
Peak memory 200260 kb
Host smart-e0d74af2-94f0-4d71-ac8c-6ad696ce64c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265831871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3265831871
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.151148361
Short name T191
Test name
Test status
Simulation time 1429255913 ps
CPU time 6.91 seconds
Started Feb 29 12:47:10 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 200196 kb
Host smart-91c6933b-9115-41eb-b09c-38815edfeb61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151148361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.151148361
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.908691517
Short name T462
Test name
Test status
Simulation time 269872260 ps
CPU time 1.85 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 200108 kb
Host smart-a4083036-feea-490f-9db5-ec63ada55028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908691517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.908691517
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2477000462
Short name T179
Test name
Test status
Simulation time 205480780 ps
CPU time 1.32 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:15 PM PST 24
Peak memory 200280 kb
Host smart-16fcaf11-a0e4-4832-84d3-2c6436d2dc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477000462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2477000462
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1665533274
Short name T53
Test name
Test status
Simulation time 65569500 ps
CPU time 0.72 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 199952 kb
Host smart-9eca1be2-448d-40ff-9981-44e4cc24392f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665533274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1665533274
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.734855976
Short name T310
Test name
Test status
Simulation time 1235415637 ps
CPU time 5.74 seconds
Started Feb 29 12:47:13 PM PST 24
Finished Feb 29 12:47:21 PM PST 24
Peak memory 216816 kb
Host smart-dbc6224a-ecb7-42ea-91ab-3a05d6ca15d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734855976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.734855976
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.598375280
Short name T317
Test name
Test status
Simulation time 246909128 ps
CPU time 1.07 seconds
Started Feb 29 12:47:27 PM PST 24
Finished Feb 29 12:47:29 PM PST 24
Peak memory 217328 kb
Host smart-abeff3d4-636d-4f72-96a5-80bf66a2677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598375280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.598375280
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1814172267
Short name T486
Test name
Test status
Simulation time 147240187 ps
CPU time 0.77 seconds
Started Feb 29 12:47:31 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 199924 kb
Host smart-96c8d50d-35b4-43b3-9fc0-bd5e16b35ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814172267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1814172267
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1654325014
Short name T509
Test name
Test status
Simulation time 1061994193 ps
CPU time 4.91 seconds
Started Feb 29 12:47:35 PM PST 24
Finished Feb 29 12:47:40 PM PST 24
Peak memory 200324 kb
Host smart-4d94cde9-aa19-4959-8f2f-417fca4840a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654325014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1654325014
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3909224606
Short name T301
Test name
Test status
Simulation time 141791904 ps
CPU time 1.07 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 200096 kb
Host smart-5a3f8023-0772-4795-952c-05f992f10790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909224606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3909224606
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1212654960
Short name T71
Test name
Test status
Simulation time 248568392 ps
CPU time 1.43 seconds
Started Feb 29 12:47:23 PM PST 24
Finished Feb 29 12:47:25 PM PST 24
Peak memory 200324 kb
Host smart-ef876e42-3490-4eaa-bb2a-295a2aa2505c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212654960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1212654960
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1855758369
Short name T457
Test name
Test status
Simulation time 9392140424 ps
CPU time 29.91 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 200380 kb
Host smart-dc28ec6f-cda7-4f72-8850-969e0d449cc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855758369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1855758369
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3611354133
Short name T504
Test name
Test status
Simulation time 342857579 ps
CPU time 2.31 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:47:35 PM PST 24
Peak memory 200136 kb
Host smart-253a4cc7-3f16-424d-9a11-b8cd2f1b7245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611354133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3611354133
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2960504932
Short name T258
Test name
Test status
Simulation time 143870404 ps
CPU time 1.14 seconds
Started Feb 29 12:47:25 PM PST 24
Finished Feb 29 12:47:27 PM PST 24
Peak memory 200120 kb
Host smart-62b75be3-50a3-40e2-b74e-a76daddda79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960504932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2960504932
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.828657871
Short name T540
Test name
Test status
Simulation time 62202375 ps
CPU time 0.72 seconds
Started Feb 29 12:47:10 PM PST 24
Finished Feb 29 12:47:13 PM PST 24
Peak memory 199980 kb
Host smart-075c9d36-4d23-4abf-a5d3-85b859c4629a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828657871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.828657871
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1242910543
Short name T447
Test name
Test status
Simulation time 1231711233 ps
CPU time 5.52 seconds
Started Feb 29 12:47:31 PM PST 24
Finished Feb 29 12:47:37 PM PST 24
Peak memory 217260 kb
Host smart-e857b074-7cc5-40e8-a660-c0b3e0482a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242910543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1242910543
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.874868905
Short name T495
Test name
Test status
Simulation time 243489612 ps
CPU time 1.1 seconds
Started Feb 29 12:47:26 PM PST 24
Finished Feb 29 12:47:28 PM PST 24
Peak memory 217500 kb
Host smart-f8deff23-a15d-4cf6-bc8c-18f1fd4da80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874868905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.874868905
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1223566070
Short name T393
Test name
Test status
Simulation time 158034707 ps
CPU time 0.88 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 199868 kb
Host smart-aae27e56-8423-49c2-bb6a-44ecf8096af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223566070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1223566070
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1815504735
Short name T483
Test name
Test status
Simulation time 855695911 ps
CPU time 4.16 seconds
Started Feb 29 12:47:14 PM PST 24
Finished Feb 29 12:47:19 PM PST 24
Peak memory 200264 kb
Host smart-e470a981-2185-4350-9d41-d08fa234945c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815504735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1815504735
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.746838329
Short name T143
Test name
Test status
Simulation time 154567341 ps
CPU time 1.13 seconds
Started Feb 29 12:47:33 PM PST 24
Finished Feb 29 12:47:34 PM PST 24
Peak memory 200028 kb
Host smart-d169b156-5f13-4e16-87e6-532048029ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746838329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.746838329
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2192536297
Short name T164
Test name
Test status
Simulation time 122456076 ps
CPU time 1.13 seconds
Started Feb 29 12:47:14 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 200176 kb
Host smart-58cbca68-1196-4617-984a-1dbe73f4a31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192536297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2192536297
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1145934913
Short name T342
Test name
Test status
Simulation time 126367439 ps
CPU time 1.64 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 200312 kb
Host smart-427b7c59-c40e-47f7-b3a0-3e4d51406140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145934913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1145934913
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.4206454217
Short name T453
Test name
Test status
Simulation time 155945085 ps
CPU time 1.04 seconds
Started Feb 29 12:47:13 PM PST 24
Finished Feb 29 12:47:16 PM PST 24
Peak memory 200048 kb
Host smart-e161c928-acce-4052-82e0-6b6b1f975efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206454217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4206454217
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3362387084
Short name T238
Test name
Test status
Simulation time 62291253 ps
CPU time 0.76 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 199960 kb
Host smart-a78b8a1f-857b-4eca-ae08-c8f49242c700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362387084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3362387084
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1139029998
Short name T471
Test name
Test status
Simulation time 1920800691 ps
CPU time 7.17 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 218076 kb
Host smart-fd0ee1a7-5fbc-4426-898c-021724aef427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139029998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1139029998
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.866268250
Short name T354
Test name
Test status
Simulation time 244619639 ps
CPU time 1.08 seconds
Started Feb 29 12:47:39 PM PST 24
Finished Feb 29 12:47:41 PM PST 24
Peak memory 217496 kb
Host smart-93008172-4dce-498b-b0a5-a54a2c159a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866268250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.866268250
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1588393803
Short name T276
Test name
Test status
Simulation time 117480072 ps
CPU time 0.78 seconds
Started Feb 29 12:47:33 PM PST 24
Finished Feb 29 12:47:34 PM PST 24
Peak memory 199872 kb
Host smart-7badd349-0777-48ba-91e1-2fae4c4b5785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588393803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1588393803
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3395562861
Short name T497
Test name
Test status
Simulation time 817042637 ps
CPU time 3.71 seconds
Started Feb 29 12:47:42 PM PST 24
Finished Feb 29 12:47:46 PM PST 24
Peak memory 200320 kb
Host smart-86694353-53bb-478c-942d-0b9c78e54307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395562861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3395562861
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2485560122
Short name T409
Test name
Test status
Simulation time 109328137 ps
CPU time 1.02 seconds
Started Feb 29 12:47:17 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 200108 kb
Host smart-392bde94-171d-47b5-b998-cbb1c9345fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485560122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2485560122
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.446611380
Short name T327
Test name
Test status
Simulation time 200149149 ps
CPU time 1.29 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 200324 kb
Host smart-10d3e7a1-a70b-4aff-9d41-e1ec3c4de1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446611380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.446611380
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3742583020
Short name T287
Test name
Test status
Simulation time 5072869336 ps
CPU time 22.65 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:48:16 PM PST 24
Peak memory 200480 kb
Host smart-5fb26bae-26bd-4721-aeba-4f7af2550a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742583020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3742583020
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3346282738
Short name T42
Test name
Test status
Simulation time 281235724 ps
CPU time 1.84 seconds
Started Feb 29 12:47:48 PM PST 24
Finished Feb 29 12:47:50 PM PST 24
Peak memory 200144 kb
Host smart-b249476f-1700-44e3-979a-129f5101375d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346282738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3346282738
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1880482660
Short name T194
Test name
Test status
Simulation time 172819261 ps
CPU time 1.16 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 200160 kb
Host smart-d6532594-6cc6-47e0-b1f3-87610785c046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880482660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1880482660
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3828016197
Short name T511
Test name
Test status
Simulation time 71072177 ps
CPU time 0.75 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:42 PM PST 24
Peak memory 199912 kb
Host smart-af6373a9-e98e-4fb2-acfa-f4f2c28f9781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828016197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3828016197
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3512458246
Short name T32
Test name
Test status
Simulation time 1884761325 ps
CPU time 7.57 seconds
Started Feb 29 12:47:15 PM PST 24
Finished Feb 29 12:47:23 PM PST 24
Peak memory 217412 kb
Host smart-05c7bef5-9c96-4325-8c20-0329aa7dd35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512458246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3512458246
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1669523688
Short name T144
Test name
Test status
Simulation time 243824036 ps
CPU time 1.06 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 217444 kb
Host smart-6b11ea7b-0f8e-4f84-9b2a-a52f4f752915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669523688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1669523688
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.647149802
Short name T158
Test name
Test status
Simulation time 215233220 ps
CPU time 0.89 seconds
Started Feb 29 12:47:52 PM PST 24
Finished Feb 29 12:47:53 PM PST 24
Peak memory 199908 kb
Host smart-a8eb46f0-af57-4097-b33c-b3bd8f97b538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647149802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.647149802
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3697958620
Short name T506
Test name
Test status
Simulation time 822532204 ps
CPU time 3.94 seconds
Started Feb 29 12:47:23 PM PST 24
Finished Feb 29 12:47:27 PM PST 24
Peak memory 200308 kb
Host smart-5d5e1a5e-8576-4d35-8ff3-c5bf1ad18b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697958620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3697958620
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3973865352
Short name T200
Test name
Test status
Simulation time 151906064 ps
CPU time 1.08 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:47:33 PM PST 24
Peak memory 200012 kb
Host smart-ee1861ef-270f-4512-b74f-52b3e4f6f9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973865352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3973865352
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3583080669
Short name T119
Test name
Test status
Simulation time 260523356 ps
CPU time 1.51 seconds
Started Feb 29 12:47:46 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 200388 kb
Host smart-983b4dbb-f7b5-47d0-9bfb-a428a61c800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583080669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3583080669
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2398067286
Short name T159
Test name
Test status
Simulation time 418070731 ps
CPU time 1.82 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:49 PM PST 24
Peak memory 200272 kb
Host smart-57e9a8e0-79e6-45d5-aaf1-a3168b8926bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398067286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2398067286
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3589280620
Short name T533
Test name
Test status
Simulation time 140952430 ps
CPU time 1.74 seconds
Started Feb 29 12:47:27 PM PST 24
Finished Feb 29 12:47:29 PM PST 24
Peak memory 200060 kb
Host smart-09acbe81-569d-472a-953f-c4006f87fec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589280620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3589280620
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2705790803
Short name T455
Test name
Test status
Simulation time 105862852 ps
CPU time 0.98 seconds
Started Feb 29 12:47:35 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 200116 kb
Host smart-85364797-48dd-4f67-b5cc-0b19e882d252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705790803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2705790803
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1051222079
Short name T375
Test name
Test status
Simulation time 56983857 ps
CPU time 0.67 seconds
Started Feb 29 12:47:27 PM PST 24
Finished Feb 29 12:47:28 PM PST 24
Peak memory 199872 kb
Host smart-5601ead3-28f5-4d42-82b5-29cc319679d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051222079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1051222079
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1980215845
Short name T363
Test name
Test status
Simulation time 2354014942 ps
CPU time 7.93 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 217784 kb
Host smart-a19c4354-1210-47b1-ab6d-8d849f2d451d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980215845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1980215845
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.300875750
Short name T155
Test name
Test status
Simulation time 243650400 ps
CPU time 1.1 seconds
Started Feb 29 12:48:07 PM PST 24
Finished Feb 29 12:48:09 PM PST 24
Peak memory 217356 kb
Host smart-8a556aad-a370-4550-94ec-68552ec8a271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300875750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.300875750
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2335795712
Short name T13
Test name
Test status
Simulation time 164820197 ps
CPU time 0.83 seconds
Started Feb 29 12:47:36 PM PST 24
Finished Feb 29 12:47:37 PM PST 24
Peak memory 199840 kb
Host smart-01401b9b-8db5-46a9-9bf7-af67c371b408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335795712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2335795712
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2605989129
Short name T347
Test name
Test status
Simulation time 721197822 ps
CPU time 3.71 seconds
Started Feb 29 12:47:20 PM PST 24
Finished Feb 29 12:47:24 PM PST 24
Peak memory 200476 kb
Host smart-6e269880-d6b6-418c-9dcb-e7d7d0bed9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605989129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2605989129
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.976943152
Short name T211
Test name
Test status
Simulation time 103947434 ps
CPU time 1.04 seconds
Started Feb 29 12:47:21 PM PST 24
Finished Feb 29 12:47:22 PM PST 24
Peak memory 200048 kb
Host smart-69a316e2-ec0c-4bbc-9f27-cdec9b36c969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976943152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.976943152
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.742913749
Short name T62
Test name
Test status
Simulation time 120370072 ps
CPU time 1.15 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:42 PM PST 24
Peak memory 200296 kb
Host smart-cb30ad69-33e6-40bd-9353-8ef78284ff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742913749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.742913749
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3635499623
Short name T385
Test name
Test status
Simulation time 9228150836 ps
CPU time 33.72 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:48:18 PM PST 24
Peak memory 200360 kb
Host smart-1200444d-4320-4f15-b925-b1412ede866e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635499623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3635499623
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.86102362
Short name T207
Test name
Test status
Simulation time 151655232 ps
CPU time 1.76 seconds
Started Feb 29 12:47:22 PM PST 24
Finished Feb 29 12:47:24 PM PST 24
Peak memory 200140 kb
Host smart-4d029f0d-6eed-45e3-a414-be0a36edbba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86102362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.86102362
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2602997864
Short name T321
Test name
Test status
Simulation time 79611747 ps
CPU time 0.88 seconds
Started Feb 29 12:47:46 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 200024 kb
Host smart-1f77f205-648c-434b-969b-0f268a3ff3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602997864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2602997864
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.912863308
Short name T472
Test name
Test status
Simulation time 62938086 ps
CPU time 0.75 seconds
Started Feb 29 12:47:46 PM PST 24
Finished Feb 29 12:47:47 PM PST 24
Peak memory 199860 kb
Host smart-226f4849-8738-44d9-9643-6f3359a53fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912863308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.912863308
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4093130592
Short name T490
Test name
Test status
Simulation time 1889382087 ps
CPU time 7.18 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:42 PM PST 24
Peak memory 217504 kb
Host smart-537e9065-868b-460c-a608-fff40a7baeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093130592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4093130592
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4189633420
Short name T442
Test name
Test status
Simulation time 244742524 ps
CPU time 1.08 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:47:44 PM PST 24
Peak memory 217244 kb
Host smart-0b432420-4fc1-4b65-9306-c53254e358db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189633420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4189633420
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2108708651
Short name T201
Test name
Test status
Simulation time 243792262 ps
CPU time 0.92 seconds
Started Feb 29 12:47:45 PM PST 24
Finished Feb 29 12:47:46 PM PST 24
Peak memory 199896 kb
Host smart-b8d2d8c6-46d9-4413-b4e5-7d2d66b338dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108708651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2108708651
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3058270804
Short name T344
Test name
Test status
Simulation time 988158154 ps
CPU time 4.49 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 200292 kb
Host smart-81902b5f-0f53-4a18-9bc6-9fedeb8b51d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058270804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3058270804
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.82402001
Short name T257
Test name
Test status
Simulation time 153158645 ps
CPU time 1.06 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 200076 kb
Host smart-ca006751-02f7-4bfe-a256-666df88d3113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82402001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.82402001
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.899978657
Short name T430
Test name
Test status
Simulation time 243621300 ps
CPU time 1.55 seconds
Started Feb 29 12:47:15 PM PST 24
Finished Feb 29 12:47:17 PM PST 24
Peak memory 200288 kb
Host smart-559e0405-8c9f-40c5-8120-b87a5e50c297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899978657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.899978657
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3951085243
Short name T247
Test name
Test status
Simulation time 2212141405 ps
CPU time 10.57 seconds
Started Feb 29 12:47:44 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 200508 kb
Host smart-8c3d3fe4-612c-44c6-a238-969cc7fede5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951085243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3951085243
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.479578809
Short name T245
Test name
Test status
Simulation time 365693480 ps
CPU time 1.98 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 200124 kb
Host smart-102059bb-b16f-432e-8b02-d316c08b6998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479578809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.479578809
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2269914349
Short name T359
Test name
Test status
Simulation time 101897615 ps
CPU time 0.89 seconds
Started Feb 29 12:47:39 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 200092 kb
Host smart-a8c3ef2c-ca92-4c10-a44c-86b706d2a150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269914349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2269914349
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1425080731
Short name T392
Test name
Test status
Simulation time 68035634 ps
CPU time 0.69 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:47:59 PM PST 24
Peak memory 199900 kb
Host smart-5e192258-a3d0-4ffc-a01d-71e7b668620a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425080731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1425080731
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1989656929
Short name T272
Test name
Test status
Simulation time 1875216208 ps
CPU time 7.03 seconds
Started Feb 29 12:47:37 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 217348 kb
Host smart-6541e717-ba37-4d67-8f06-807fad0920c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989656929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1989656929
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.4125475816
Short name T195
Test name
Test status
Simulation time 244862327 ps
CPU time 1.13 seconds
Started Feb 29 12:47:32 PM PST 24
Finished Feb 29 12:47:33 PM PST 24
Peak memory 217452 kb
Host smart-713ebe16-724b-4414-b6fd-500720162017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125475816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.4125475816
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3425406784
Short name T373
Test name
Test status
Simulation time 136574938 ps
CPU time 0.82 seconds
Started Feb 29 12:47:24 PM PST 24
Finished Feb 29 12:47:25 PM PST 24
Peak memory 199912 kb
Host smart-8e733264-b705-4c52-a4a5-d1d48c17d30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425406784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3425406784
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2817827537
Short name T116
Test name
Test status
Simulation time 1958288397 ps
CPU time 6.36 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:53 PM PST 24
Peak memory 200224 kb
Host smart-67fc9cbc-86d7-4cec-b9a7-0579c3bfc819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817827537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2817827537
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3999917021
Short name T501
Test name
Test status
Simulation time 106080381 ps
CPU time 0.98 seconds
Started Feb 29 12:47:29 PM PST 24
Finished Feb 29 12:47:31 PM PST 24
Peak memory 199692 kb
Host smart-c04f3fad-0d0a-4a33-bc48-717809bab714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999917021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3999917021
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1964049348
Short name T307
Test name
Test status
Simulation time 117737716 ps
CPU time 1.17 seconds
Started Feb 29 12:47:25 PM PST 24
Finished Feb 29 12:47:27 PM PST 24
Peak memory 200400 kb
Host smart-57b33e98-f28c-4d42-9484-efb69cf7376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964049348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1964049348
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2761026444
Short name T275
Test name
Test status
Simulation time 17577453824 ps
CPU time 58.75 seconds
Started Feb 29 12:47:35 PM PST 24
Finished Feb 29 12:48:34 PM PST 24
Peak memory 200468 kb
Host smart-66cf130d-078a-4fe4-830e-9350f55e5973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761026444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2761026444
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3795342690
Short name T387
Test name
Test status
Simulation time 328526171 ps
CPU time 2.21 seconds
Started Feb 29 12:47:36 PM PST 24
Finished Feb 29 12:47:39 PM PST 24
Peak memory 200160 kb
Host smart-639ed7d4-b390-4d5b-8931-513c20fe0197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795342690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3795342690
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.406649019
Short name T174
Test name
Test status
Simulation time 72606795 ps
CPU time 0.79 seconds
Started Feb 29 12:47:40 PM PST 24
Finished Feb 29 12:47:41 PM PST 24
Peak memory 200172 kb
Host smart-0bcf05af-d690-493c-9b9f-87a68cdc1472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406649019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.406649019
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4142191001
Short name T458
Test name
Test status
Simulation time 91114975 ps
CPU time 0.83 seconds
Started Feb 29 12:46:40 PM PST 24
Finished Feb 29 12:46:41 PM PST 24
Peak memory 199832 kb
Host smart-e427bb41-1d0d-4cee-bc47-af82d321027e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142191001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4142191001
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.793451810
Short name T530
Test name
Test status
Simulation time 2347666075 ps
CPU time 8.19 seconds
Started Feb 29 12:46:39 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 221308 kb
Host smart-79f57e39-29d5-4d60-8b52-d31d52736c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793451810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.793451810
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1653287757
Short name T153
Test name
Test status
Simulation time 243031994 ps
CPU time 1.09 seconds
Started Feb 29 12:46:53 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 217400 kb
Host smart-81fc350f-6242-4efb-9119-a4014e2a7bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653287757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1653287757
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3230828710
Short name T326
Test name
Test status
Simulation time 204620717 ps
CPU time 0.99 seconds
Started Feb 29 12:46:48 PM PST 24
Finished Feb 29 12:46:50 PM PST 24
Peak memory 200076 kb
Host smart-711ab7a2-babb-4d73-a97e-dcf1aa55e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230828710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3230828710
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2907335686
Short name T502
Test name
Test status
Simulation time 762538812 ps
CPU time 3.67 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 200364 kb
Host smart-7a564f70-845f-44c6-9445-d9f0a9cabb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907335686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2907335686
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.538821258
Short name T33
Test name
Test status
Simulation time 16575286962 ps
CPU time 26.11 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:47:13 PM PST 24
Peak memory 218116 kb
Host smart-6f89c6c5-65a2-4fb1-9588-69c29fe0579d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538821258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.538821258
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.199624347
Short name T242
Test name
Test status
Simulation time 98901169 ps
CPU time 0.92 seconds
Started Feb 29 12:47:03 PM PST 24
Finished Feb 29 12:47:04 PM PST 24
Peak memory 200060 kb
Host smart-19ac9012-f612-4066-96c8-3b2f3e7efdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199624347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.199624347
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.314658191
Short name T282
Test name
Test status
Simulation time 123997052 ps
CPU time 1.19 seconds
Started Feb 29 12:46:41 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 200336 kb
Host smart-ddb72f26-7901-4427-8468-67860de96702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314658191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.314658191
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.694208073
Short name T382
Test name
Test status
Simulation time 997903805 ps
CPU time 5 seconds
Started Feb 29 12:47:07 PM PST 24
Finished Feb 29 12:47:12 PM PST 24
Peak memory 200256 kb
Host smart-e6e272fd-29bc-4174-8f32-e510d5cb3be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694208073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.694208073
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3867952626
Short name T154
Test name
Test status
Simulation time 337695061 ps
CPU time 2.15 seconds
Started Feb 29 12:46:56 PM PST 24
Finished Feb 29 12:46:59 PM PST 24
Peak memory 200068 kb
Host smart-f6cc42bd-7518-4cdd-bcaa-fbc97390f522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867952626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3867952626
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1002473956
Short name T240
Test name
Test status
Simulation time 110026106 ps
CPU time 0.87 seconds
Started Feb 29 12:46:38 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 200172 kb
Host smart-472dfaeb-7637-42df-a5d9-ce2325940f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002473956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1002473956
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2392429797
Short name T355
Test name
Test status
Simulation time 71401943 ps
CPU time 0.74 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 199900 kb
Host smart-262258bb-dc18-4749-9288-f217f46405fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392429797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2392429797
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.117179375
Short name T337
Test name
Test status
Simulation time 1891295091 ps
CPU time 6.87 seconds
Started Feb 29 12:47:48 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 221424 kb
Host smart-7c5cad47-188a-4a82-9d54-5e6e681d4186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117179375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.117179375
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2895217427
Short name T500
Test name
Test status
Simulation time 243153764 ps
CPU time 1.18 seconds
Started Feb 29 12:47:38 PM PST 24
Finished Feb 29 12:47:40 PM PST 24
Peak memory 217332 kb
Host smart-3b8f8a2d-5914-4307-8cd2-d85f76d9ece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895217427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2895217427
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3024442627
Short name T2
Test name
Test status
Simulation time 221115059 ps
CPU time 0.9 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 199912 kb
Host smart-3fe29bfe-8c8d-48ae-bbce-38381f508e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024442627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3024442627
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.422079160
Short name T402
Test name
Test status
Simulation time 1009707514 ps
CPU time 4.69 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 200312 kb
Host smart-053e5e35-82f1-4282-8221-cfb1a238cb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422079160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.422079160
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2527997095
Short name T446
Test name
Test status
Simulation time 178989935 ps
CPU time 1.11 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:47:54 PM PST 24
Peak memory 200112 kb
Host smart-8464c52e-50b9-45c1-aa41-73876976c76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527997095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2527997095
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3058343767
Short name T59
Test name
Test status
Simulation time 124033469 ps
CPU time 1.23 seconds
Started Feb 29 12:47:42 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 200384 kb
Host smart-bba48d81-9520-4238-9dec-4287243c86dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058343767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3058343767
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.577093285
Short name T341
Test name
Test status
Simulation time 3958109737 ps
CPU time 17.78 seconds
Started Feb 29 12:48:07 PM PST 24
Finished Feb 29 12:48:25 PM PST 24
Peak memory 200388 kb
Host smart-b07c9058-31e5-427e-8aaf-d59b7fce662a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577093285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.577093285
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1526887891
Short name T357
Test name
Test status
Simulation time 120523620 ps
CPU time 1.56 seconds
Started Feb 29 12:47:30 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 200036 kb
Host smart-9076c776-39eb-4650-a070-061ad53fbba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526887891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1526887891
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2707530092
Short name T492
Test name
Test status
Simulation time 134284404 ps
CPU time 1.2 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 200080 kb
Host smart-17bba0b1-57eb-4243-ad2a-ede897c54cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707530092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2707530092
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3030848055
Short name T187
Test name
Test status
Simulation time 85324615 ps
CPU time 0.81 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:42 PM PST 24
Peak memory 199972 kb
Host smart-3bf55431-5de9-4093-a044-211046d43b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030848055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3030848055
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3553684135
Short name T36
Test name
Test status
Simulation time 1224822879 ps
CPU time 5.65 seconds
Started Feb 29 12:47:44 PM PST 24
Finished Feb 29 12:47:50 PM PST 24
Peak memory 221468 kb
Host smart-01142cc4-3ad3-4fb1-abda-96a3a38eb0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553684135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3553684135
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4245609412
Short name T175
Test name
Test status
Simulation time 247444673 ps
CPU time 0.99 seconds
Started Feb 29 12:47:42 PM PST 24
Finished Feb 29 12:47:44 PM PST 24
Peak memory 217388 kb
Host smart-100f5caa-0531-4592-bd7a-7aff2658df09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245609412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4245609412
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3197745122
Short name T17
Test name
Test status
Simulation time 133279468 ps
CPU time 0.77 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:51 PM PST 24
Peak memory 199884 kb
Host smart-745b7067-0da9-42eb-8c81-7ba36e0d1cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197745122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3197745122
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2522072389
Short name T115
Test name
Test status
Simulation time 2018962999 ps
CPU time 8.02 seconds
Started Feb 29 12:47:38 PM PST 24
Finished Feb 29 12:47:47 PM PST 24
Peak memory 200236 kb
Host smart-527415ce-9c24-4d05-95cc-d2c1bcc63667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522072389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2522072389
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3489126760
Short name T290
Test name
Test status
Simulation time 175981437 ps
CPU time 1.23 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 200108 kb
Host smart-03d31fd6-dcf2-4394-9376-b4c18b553914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489126760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3489126760
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.808597519
Short name T474
Test name
Test status
Simulation time 130948722 ps
CPU time 1.15 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:51 PM PST 24
Peak memory 200276 kb
Host smart-4477af43-6c6c-41f6-ba21-2998b470ef31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808597519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.808597519
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4292074860
Short name T406
Test name
Test status
Simulation time 1774454818 ps
CPU time 6.46 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 200276 kb
Host smart-949c4257-bf0b-4473-9c1e-49b7b4dfc81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292074860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4292074860
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1740449391
Short name T366
Test name
Test status
Simulation time 143943116 ps
CPU time 1.75 seconds
Started Feb 29 12:48:18 PM PST 24
Finished Feb 29 12:48:20 PM PST 24
Peak memory 200116 kb
Host smart-5f62ba28-d67e-401a-b749-bfb6d8086d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740449391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1740449391
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1178751660
Short name T412
Test name
Test status
Simulation time 111572370 ps
CPU time 0.93 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 200076 kb
Host smart-76049a39-10c7-4286-a096-e6e625e233a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178751660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1178751660
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2524467909
Short name T352
Test name
Test status
Simulation time 72827778 ps
CPU time 0.73 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 199956 kb
Host smart-3679e024-e1f2-418d-9265-12509c22342f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524467909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2524467909
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.441214633
Short name T29
Test name
Test status
Simulation time 1876173038 ps
CPU time 7.19 seconds
Started Feb 29 12:47:44 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 216888 kb
Host smart-35b4dfdf-20bd-4542-8b50-4b3b81937e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441214633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.441214633
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1210418513
Short name T206
Test name
Test status
Simulation time 244534029 ps
CPU time 1.01 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 217292 kb
Host smart-99365a02-239b-44bc-b6ab-741cbf0d9244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210418513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1210418513
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.411396789
Short name T435
Test name
Test status
Simulation time 190076493 ps
CPU time 0.87 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 199888 kb
Host smart-49b106c8-0b37-4a66-8d43-10c2e8e3b9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411396789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.411396789
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2845386955
Short name T294
Test name
Test status
Simulation time 1059122467 ps
CPU time 4.86 seconds
Started Feb 29 12:47:35 PM PST 24
Finished Feb 29 12:47:40 PM PST 24
Peak memory 200328 kb
Host smart-4019427f-4885-4156-b4a5-a634f3273f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845386955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2845386955
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2026861710
Short name T345
Test name
Test status
Simulation time 95188880 ps
CPU time 0.9 seconds
Started Feb 29 12:47:42 PM PST 24
Finished Feb 29 12:47:44 PM PST 24
Peak memory 200080 kb
Host smart-6c257bb3-4b5d-467a-87f6-c9f9dae832f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026861710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2026861710
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2997732499
Short name T213
Test name
Test status
Simulation time 113692435 ps
CPU time 1.11 seconds
Started Feb 29 12:47:38 PM PST 24
Finished Feb 29 12:47:39 PM PST 24
Peak memory 200288 kb
Host smart-7fde43d3-0e70-405f-8d1d-784f8c257f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997732499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2997732499
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3847804146
Short name T427
Test name
Test status
Simulation time 12505086741 ps
CPU time 45.28 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:48:29 PM PST 24
Peak memory 200424 kb
Host smart-4cb1f9bf-b363-4de8-a07a-c4f80a539b56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847804146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3847804146
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1549135328
Short name T438
Test name
Test status
Simulation time 135066050 ps
CPU time 1.57 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 200104 kb
Host smart-647521a3-bbca-477a-8287-b878a33ff736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549135328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1549135328
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2236449181
Short name T545
Test name
Test status
Simulation time 218456124 ps
CPU time 1.21 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 200148 kb
Host smart-38cfa41b-22fe-47ec-9557-9d8611cbe503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236449181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2236449181
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1136267049
Short name T167
Test name
Test status
Simulation time 84374729 ps
CPU time 0.79 seconds
Started Feb 29 12:47:59 PM PST 24
Finished Feb 29 12:48:01 PM PST 24
Peak memory 199952 kb
Host smart-3ca15f6f-75bf-4320-993b-119489698d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136267049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1136267049
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2270486709
Short name T454
Test name
Test status
Simulation time 2356341552 ps
CPU time 8.69 seconds
Started Feb 29 12:47:49 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 221328 kb
Host smart-4b7778d6-8fdf-4983-860d-e09e4ca19f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270486709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2270486709
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1388242960
Short name T403
Test name
Test status
Simulation time 244291023 ps
CPU time 1.06 seconds
Started Feb 29 12:47:31 PM PST 24
Finished Feb 29 12:47:32 PM PST 24
Peak memory 217300 kb
Host smart-08508b05-f521-4d72-86e5-e02029db8462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388242960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1388242960
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2314564535
Short name T519
Test name
Test status
Simulation time 209662895 ps
CPU time 0.92 seconds
Started Feb 29 12:47:18 PM PST 24
Finished Feb 29 12:47:19 PM PST 24
Peak memory 199888 kb
Host smart-f530d5aa-ab8f-4c4f-80a7-84d50f38fe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314564535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2314564535
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2771262395
Short name T384
Test name
Test status
Simulation time 736947148 ps
CPU time 3.93 seconds
Started Feb 29 12:47:49 PM PST 24
Finished Feb 29 12:47:53 PM PST 24
Peak memory 200496 kb
Host smart-c343b55f-eef2-4bf4-a029-1def53e31193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771262395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2771262395
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1898403087
Short name T180
Test name
Test status
Simulation time 98898804 ps
CPU time 0.95 seconds
Started Feb 29 12:47:37 PM PST 24
Finished Feb 29 12:47:38 PM PST 24
Peak memory 200136 kb
Host smart-ac032453-48a3-4264-a476-cc20a9772ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898403087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1898403087
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1970576465
Short name T346
Test name
Test status
Simulation time 245731979 ps
CPU time 1.57 seconds
Started Feb 29 12:47:42 PM PST 24
Finished Feb 29 12:47:44 PM PST 24
Peak memory 200304 kb
Host smart-11978658-805f-4bd7-84fb-5704527f22da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970576465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1970576465
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2279240670
Short name T400
Test name
Test status
Simulation time 257073791 ps
CPU time 1.87 seconds
Started Feb 29 12:47:42 PM PST 24
Finished Feb 29 12:47:45 PM PST 24
Peak memory 200292 kb
Host smart-74c0d4f5-e98e-42c2-9980-cb1a886c69f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279240670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2279240670
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3122157871
Short name T469
Test name
Test status
Simulation time 141446800 ps
CPU time 1.75 seconds
Started Feb 29 12:47:52 PM PST 24
Finished Feb 29 12:47:54 PM PST 24
Peak memory 200152 kb
Host smart-c0d83a26-8113-4e32-921a-9df182d567fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122157871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3122157871
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2738019556
Short name T210
Test name
Test status
Simulation time 94527477 ps
CPU time 0.9 seconds
Started Feb 29 12:47:42 PM PST 24
Finished Feb 29 12:47:44 PM PST 24
Peak memory 200060 kb
Host smart-43427da6-374a-4f4e-9854-ba40ec88e7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738019556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2738019556
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.311671833
Short name T214
Test name
Test status
Simulation time 63697138 ps
CPU time 0.76 seconds
Started Feb 29 12:48:04 PM PST 24
Finished Feb 29 12:48:06 PM PST 24
Peak memory 199960 kb
Host smart-9099758a-4bf6-4756-80fb-9cef1e4a3647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311671833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.311671833
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3991238662
Short name T37
Test name
Test status
Simulation time 2355918866 ps
CPU time 8.04 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 222220 kb
Host smart-7f3bcff0-c604-4f5b-aa10-51da506899f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991238662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3991238662
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3929139117
Short name T489
Test name
Test status
Simulation time 244158951 ps
CPU time 1.15 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:51 PM PST 24
Peak memory 217328 kb
Host smart-dd0af1cf-f602-4ede-91ba-851ea1fadb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929139117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3929139117
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.183955525
Short name T450
Test name
Test status
Simulation time 156158207 ps
CPU time 0.9 seconds
Started Feb 29 12:47:49 PM PST 24
Finished Feb 29 12:47:50 PM PST 24
Peak memory 199868 kb
Host smart-a6fef193-a8db-47d4-bc27-cbaa8f3d3f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183955525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.183955525
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3014117452
Short name T281
Test name
Test status
Simulation time 1438952272 ps
CPU time 5.62 seconds
Started Feb 29 12:47:36 PM PST 24
Finished Feb 29 12:47:41 PM PST 24
Peak memory 200304 kb
Host smart-799c7a5f-e3dd-478f-9e85-98f4a0cab6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014117452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3014117452
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3261835554
Short name T494
Test name
Test status
Simulation time 93955533 ps
CPU time 0.99 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 200068 kb
Host smart-71eec4e9-9430-4f2c-bd8f-8bdecfed4d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261835554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3261835554
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1569949276
Short name T439
Test name
Test status
Simulation time 120578231 ps
CPU time 1.2 seconds
Started Feb 29 12:47:41 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 200264 kb
Host smart-492b4a74-6307-4708-ba0b-a87259cf8843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569949276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1569949276
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2561742807
Short name T542
Test name
Test status
Simulation time 10314156468 ps
CPU time 38.2 seconds
Started Feb 29 12:47:49 PM PST 24
Finished Feb 29 12:48:28 PM PST 24
Peak memory 200384 kb
Host smart-1c9edb4d-cb9e-46f1-a923-f375cae1bda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561742807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2561742807
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3701916977
Short name T421
Test name
Test status
Simulation time 305941083 ps
CPU time 2.14 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:49 PM PST 24
Peak memory 200140 kb
Host smart-8cef8123-b19d-461e-afa2-892a2c03a0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701916977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3701916977
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.4018987372
Short name T130
Test name
Test status
Simulation time 117909724 ps
CPU time 1.02 seconds
Started Feb 29 12:48:01 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 200072 kb
Host smart-21c62ae4-f4ec-49d6-b83f-21bfbe25db20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018987372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.4018987372
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3161155025
Short name T426
Test name
Test status
Simulation time 64953628 ps
CPU time 0.74 seconds
Started Feb 29 12:47:37 PM PST 24
Finished Feb 29 12:47:38 PM PST 24
Peak memory 199828 kb
Host smart-f331931b-7d43-45c2-be3e-7d2ca68638aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161155025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3161155025
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.881580285
Short name T515
Test name
Test status
Simulation time 1224499102 ps
CPU time 5.29 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 222080 kb
Host smart-03d9f76f-a8f3-4f4b-8780-03c76da0f4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881580285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.881580285
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3849361022
Short name T536
Test name
Test status
Simulation time 245315067 ps
CPU time 1.09 seconds
Started Feb 29 12:47:46 PM PST 24
Finished Feb 29 12:47:47 PM PST 24
Peak memory 217348 kb
Host smart-ac07b10c-b351-4461-ada3-a5d264386987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849361022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3849361022
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.296814741
Short name T249
Test name
Test status
Simulation time 209906073 ps
CPU time 0.89 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:51 PM PST 24
Peak memory 199992 kb
Host smart-fa450fad-e1ed-4ef4-b03e-3e409c0c4998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296814741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.296814741
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.575339778
Short name T291
Test name
Test status
Simulation time 1711536034 ps
CPU time 6.73 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 200264 kb
Host smart-19e322bf-42cd-4c7a-a4fe-9f50435db5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575339778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.575339778
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1371995833
Short name T246
Test name
Test status
Simulation time 108331225 ps
CPU time 1 seconds
Started Feb 29 12:47:49 PM PST 24
Finished Feb 29 12:47:50 PM PST 24
Peak memory 200060 kb
Host smart-061029b2-8af3-481d-b3b9-586825d6c016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371995833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1371995833
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4154738214
Short name T374
Test name
Test status
Simulation time 242606881 ps
CPU time 1.47 seconds
Started Feb 29 12:48:04 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 200316 kb
Host smart-4109891a-c626-42e8-afab-dddc4d87cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154738214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4154738214
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1393213487
Short name T461
Test name
Test status
Simulation time 1666095123 ps
CPU time 8.43 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 200252 kb
Host smart-38f4f060-442f-4be7-8801-491c62747bb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393213487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1393213487
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2272798262
Short name T404
Test name
Test status
Simulation time 369956034 ps
CPU time 2.34 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 200144 kb
Host smart-10da4345-4ced-4b04-bb2e-efd82e250f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272798262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2272798262
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3708411003
Short name T330
Test name
Test status
Simulation time 252700552 ps
CPU time 1.33 seconds
Started Feb 29 12:47:44 PM PST 24
Finished Feb 29 12:47:46 PM PST 24
Peak memory 200092 kb
Host smart-8aa09b42-8ac7-48b5-9d1c-8f23fb5be298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708411003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3708411003
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2144650777
Short name T178
Test name
Test status
Simulation time 64860619 ps
CPU time 0.7 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 199880 kb
Host smart-9efd78b6-5229-4a92-8052-72e9b2948231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144650777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2144650777
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.843489642
Short name T420
Test name
Test status
Simulation time 1223823676 ps
CPU time 5.24 seconds
Started Feb 29 12:47:45 PM PST 24
Finished Feb 29 12:47:51 PM PST 24
Peak memory 217868 kb
Host smart-dff9e11f-830a-45d4-8fc9-6da3465063b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843489642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.843489642
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1010313973
Short name T132
Test name
Test status
Simulation time 244038897 ps
CPU time 1.16 seconds
Started Feb 29 12:47:39 PM PST 24
Finished Feb 29 12:47:40 PM PST 24
Peak memory 217300 kb
Host smart-675c7644-ea4c-4839-a3e0-9ab94e9d6aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010313973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1010313973
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1546364880
Short name T297
Test name
Test status
Simulation time 118741522 ps
CPU time 0.79 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 199880 kb
Host smart-82e01a5f-1c80-41e4-9494-35b78fae171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546364880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1546364880
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1533565053
Short name T316
Test name
Test status
Simulation time 1206340292 ps
CPU time 5.23 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 200168 kb
Host smart-973c12dc-a5c3-4567-a296-1d1c8077a814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533565053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1533565053
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1353892511
Short name T236
Test name
Test status
Simulation time 184831210 ps
CPU time 1.2 seconds
Started Feb 29 12:47:52 PM PST 24
Finished Feb 29 12:47:54 PM PST 24
Peak memory 200164 kb
Host smart-9c049d4e-88cf-4f5a-b487-644ef74cbb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353892511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1353892511
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2120889274
Short name T473
Test name
Test status
Simulation time 260447352 ps
CPU time 1.44 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:47:54 PM PST 24
Peak memory 200328 kb
Host smart-9825d292-c4c5-4196-8937-0fa53c9c2014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120889274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2120889274
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.691076244
Short name T441
Test name
Test status
Simulation time 752824482 ps
CPU time 3.41 seconds
Started Feb 29 12:47:33 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 200244 kb
Host smart-0dbaf5d3-c4a8-4625-bbae-66f9ed918c06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691076244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.691076244
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3421058348
Short name T150
Test name
Test status
Simulation time 367490854 ps
CPU time 2.35 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 200140 kb
Host smart-ae025481-65a6-4e48-b8b0-2b0f6e6d93b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421058348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3421058348
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4026080349
Short name T459
Test name
Test status
Simulation time 187448554 ps
CPU time 1.16 seconds
Started Feb 29 12:47:39 PM PST 24
Finished Feb 29 12:47:40 PM PST 24
Peak memory 200092 kb
Host smart-eae3de99-c71a-4e5f-b464-b57e1a105b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026080349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4026080349
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3495480001
Short name T423
Test name
Test status
Simulation time 82198553 ps
CPU time 0.79 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 199892 kb
Host smart-07016a02-6678-48b7-992c-966bafe18fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495480001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3495480001
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1324826696
Short name T394
Test name
Test status
Simulation time 1901966405 ps
CPU time 6.66 seconds
Started Feb 29 12:47:45 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 221252 kb
Host smart-eed869ec-9ba5-46d1-b0cb-1aa82106c371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324826696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1324826696
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.241432204
Short name T149
Test name
Test status
Simulation time 244326301 ps
CPU time 1.07 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 217396 kb
Host smart-c4150163-d70d-475a-8115-dd8ed98f46a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241432204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.241432204
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.206102162
Short name T322
Test name
Test status
Simulation time 207152504 ps
CPU time 0.86 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:51 PM PST 24
Peak memory 199784 kb
Host smart-489c4b79-b110-4769-9f84-c43d7d97009f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206102162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.206102162
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4098048270
Short name T324
Test name
Test status
Simulation time 1956888215 ps
CPU time 7.52 seconds
Started Feb 29 12:47:44 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 200292 kb
Host smart-6e89e51f-557e-4db5-ba48-aa672da4614c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098048270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4098048270
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1214256307
Short name T176
Test name
Test status
Simulation time 177196419 ps
CPU time 1.09 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:51 PM PST 24
Peak memory 200112 kb
Host smart-fd45a010-9e34-40d7-81d9-3c8d999c0479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214256307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1214256307
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1186636184
Short name T456
Test name
Test status
Simulation time 119747041 ps
CPU time 1.14 seconds
Started Feb 29 12:47:59 PM PST 24
Finished Feb 29 12:48:01 PM PST 24
Peak memory 200296 kb
Host smart-8b36a9fa-ecc4-4dbc-a456-949d625639b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186636184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1186636184
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1660545323
Short name T370
Test name
Test status
Simulation time 427861503 ps
CPU time 2.06 seconds
Started Feb 29 12:47:40 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 200328 kb
Host smart-8af6c453-b63a-4467-b36d-78be2782c400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660545323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1660545323
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.612240161
Short name T223
Test name
Test status
Simulation time 425869378 ps
CPU time 2.26 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 200056 kb
Host smart-c2079003-0f4a-4f42-b138-b30d5bd2a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612240161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.612240161
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3746791908
Short name T138
Test name
Test status
Simulation time 133869351 ps
CPU time 1.03 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 200064 kb
Host smart-40f0aa3b-42c8-4f33-9044-9c7c596dc8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746791908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3746791908
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2933181566
Short name T184
Test name
Test status
Simulation time 102529816 ps
CPU time 0.82 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 199880 kb
Host smart-a5182406-9014-47b5-af5c-3c5dc8db39d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933181566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2933181566
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2052873029
Short name T522
Test name
Test status
Simulation time 2375336623 ps
CPU time 7.99 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 217700 kb
Host smart-77f78364-c3cc-43bb-9c58-f52038754936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052873029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2052873029
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3879979062
Short name T64
Test name
Test status
Simulation time 244748466 ps
CPU time 1.03 seconds
Started Feb 29 12:48:00 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 217300 kb
Host smart-9dc7fdb3-b609-47e4-8737-4c17bc4e4852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879979062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3879979062
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2163081776
Short name T436
Test name
Test status
Simulation time 126192984 ps
CPU time 0.82 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:51 PM PST 24
Peak memory 199784 kb
Host smart-965cd4fb-1abb-4207-b63e-a2fe536b9036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163081776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2163081776
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2833049189
Short name T379
Test name
Test status
Simulation time 1763957939 ps
CPU time 6.84 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 200196 kb
Host smart-656e7690-b78b-4311-ac29-dafc9e182113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833049189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2833049189
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3009600472
Short name T147
Test name
Test status
Simulation time 152075628 ps
CPU time 1.08 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:53 PM PST 24
Peak memory 199984 kb
Host smart-6e3ed8f9-fe1e-4d02-9768-746e6021f190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009600472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3009600472
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2115083151
Short name T215
Test name
Test status
Simulation time 115402979 ps
CPU time 1.18 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 200292 kb
Host smart-e9e0ef68-3679-4196-8ec4-ea0efd882ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115083151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2115083151
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.578921983
Short name T85
Test name
Test status
Simulation time 3482231392 ps
CPU time 15.53 seconds
Started Feb 29 12:47:52 PM PST 24
Finished Feb 29 12:48:07 PM PST 24
Peak memory 200296 kb
Host smart-c61b752f-2229-420f-99a1-e0e4fa72e434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578921983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.578921983
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2381079238
Short name T521
Test name
Test status
Simulation time 145817507 ps
CPU time 1.95 seconds
Started Feb 29 12:48:00 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 200044 kb
Host smart-12bc0857-37e3-45e8-b548-9802282c9ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381079238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2381079238
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.527063124
Short name T267
Test name
Test status
Simulation time 107945892 ps
CPU time 0.9 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 199980 kb
Host smart-2f71a6a7-3ff9-4b5e-b635-4ce2b12ebf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527063124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.527063124
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2167420227
Short name T477
Test name
Test status
Simulation time 70536284 ps
CPU time 0.73 seconds
Started Feb 29 12:47:56 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 199916 kb
Host smart-0d229846-7039-404f-8cff-a4f695aef5e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167420227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2167420227
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.960075187
Short name T38
Test name
Test status
Simulation time 2340462177 ps
CPU time 9.58 seconds
Started Feb 29 12:47:35 PM PST 24
Finished Feb 29 12:47:44 PM PST 24
Peak memory 218080 kb
Host smart-72a0fc99-f450-4cfb-ac15-2ff87d4cabe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960075187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.960075187
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3754508380
Short name T526
Test name
Test status
Simulation time 244617626 ps
CPU time 1.07 seconds
Started Feb 29 12:47:45 PM PST 24
Finished Feb 29 12:47:47 PM PST 24
Peak memory 217332 kb
Host smart-f626e711-1052-484a-a2b8-e2e6c667d9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754508380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3754508380
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3679265433
Short name T309
Test name
Test status
Simulation time 137742349 ps
CPU time 0.78 seconds
Started Feb 29 12:48:00 PM PST 24
Finished Feb 29 12:48:01 PM PST 24
Peak memory 199884 kb
Host smart-c95409ed-89fd-4ef6-a071-3b50aa23ee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679265433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3679265433
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2869201863
Short name T117
Test name
Test status
Simulation time 1420670337 ps
CPU time 5.27 seconds
Started Feb 29 12:48:04 PM PST 24
Finished Feb 29 12:48:10 PM PST 24
Peak memory 200324 kb
Host smart-cb858ea1-713d-42f3-a6dd-d0b98eedce8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869201863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2869201863
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2013986194
Short name T293
Test name
Test status
Simulation time 168274261 ps
CPU time 1.12 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 200112 kb
Host smart-6254ea57-b871-4422-9915-ab5b993ed241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013986194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2013986194
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3736361262
Short name T433
Test name
Test status
Simulation time 199983492 ps
CPU time 1.44 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 200284 kb
Host smart-0eb09abf-b859-47ac-80e1-03ed2004dd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736361262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3736361262
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2612368000
Short name T376
Test name
Test status
Simulation time 12568126570 ps
CPU time 45.16 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:48:39 PM PST 24
Peak memory 200380 kb
Host smart-c8fb844a-0073-47e8-b358-1c17630f246e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612368000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2612368000
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3381625265
Short name T277
Test name
Test status
Simulation time 284583892 ps
CPU time 1.84 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 200048 kb
Host smart-836cc95b-10ce-4d69-837c-119cab0cef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381625265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3381625265
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3813049778
Short name T318
Test name
Test status
Simulation time 163322939 ps
CPU time 1.16 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 200200 kb
Host smart-ac5a8894-70c6-4618-8d80-4ed3503a5e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813049778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3813049778
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3601905558
Short name T188
Test name
Test status
Simulation time 89905153 ps
CPU time 0.78 seconds
Started Feb 29 12:47:02 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 199916 kb
Host smart-32e3824c-446c-4fb3-a48f-14c6662e5ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601905558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3601905558
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1411104005
Short name T401
Test name
Test status
Simulation time 1899929066 ps
CPU time 7.28 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 221496 kb
Host smart-c78d07e9-1c4f-4953-9fc8-b4c67535595c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411104005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1411104005
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2879829593
Short name T443
Test name
Test status
Simulation time 244031600 ps
CPU time 1.05 seconds
Started Feb 29 12:46:48 PM PST 24
Finished Feb 29 12:46:49 PM PST 24
Peak memory 217324 kb
Host smart-f5c2ce6d-db7d-46fd-bafc-b94cf2b588c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879829593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2879829593
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2117615680
Short name T482
Test name
Test status
Simulation time 98277045 ps
CPU time 0.77 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 199904 kb
Host smart-55b84633-8bac-4d06-ae20-5ead1c58e20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117615680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2117615680
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1168643961
Short name T260
Test name
Test status
Simulation time 1652452534 ps
CPU time 6.29 seconds
Started Feb 29 12:46:55 PM PST 24
Finished Feb 29 12:47:01 PM PST 24
Peak memory 200212 kb
Host smart-aeffddab-b0eb-4cb3-bb1e-ccc53bd1b0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168643961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1168643961
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4148933835
Short name T478
Test name
Test status
Simulation time 143825339 ps
CPU time 1.06 seconds
Started Feb 29 12:46:45 PM PST 24
Finished Feb 29 12:46:47 PM PST 24
Peak memory 200096 kb
Host smart-56b6074a-99ac-47f8-b206-ee48b68206f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148933835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4148933835
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2867827608
Short name T173
Test name
Test status
Simulation time 117244672 ps
CPU time 1.13 seconds
Started Feb 29 12:46:44 PM PST 24
Finished Feb 29 12:46:45 PM PST 24
Peak memory 200316 kb
Host smart-f82a705d-ccfe-4d42-afb2-5c69a5ca04f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867827608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2867827608
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3745928044
Short name T418
Test name
Test status
Simulation time 2620666807 ps
CPU time 8.96 seconds
Started Feb 29 12:46:44 PM PST 24
Finished Feb 29 12:46:53 PM PST 24
Peak memory 200344 kb
Host smart-f69c9f5d-b05f-4b43-9a9d-b8eafec5b051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745928044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3745928044
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1833346012
Short name T122
Test name
Test status
Simulation time 423915351 ps
CPU time 2.21 seconds
Started Feb 29 12:46:56 PM PST 24
Finished Feb 29 12:46:58 PM PST 24
Peak memory 200036 kb
Host smart-ab911f6a-efec-4c02-b284-16df083d4108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833346012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1833346012
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.850964556
Short name T518
Test name
Test status
Simulation time 228707392 ps
CPU time 1.39 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 200100 kb
Host smart-78687823-66bf-403c-8600-75088d1c52e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850964556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.850964556
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1426225326
Short name T268
Test name
Test status
Simulation time 68624067 ps
CPU time 0.76 seconds
Started Feb 29 12:46:39 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 199920 kb
Host smart-2ca43d11-ff0e-4327-a259-b61c85f6e792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426225326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1426225326
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2343855018
Short name T445
Test name
Test status
Simulation time 1225082866 ps
CPU time 5.25 seconds
Started Feb 29 12:46:40 PM PST 24
Finished Feb 29 12:46:45 PM PST 24
Peak memory 216696 kb
Host smart-d6e73b77-7f9c-4ebb-b00f-9b4dcd1af2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343855018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2343855018
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3761087800
Short name T190
Test name
Test status
Simulation time 244163859 ps
CPU time 1.05 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 217368 kb
Host smart-0ad3eb07-f3e2-49b1-821f-64d31c397d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761087800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3761087800
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2277506762
Short name T14
Test name
Test status
Simulation time 105869295 ps
CPU time 0.74 seconds
Started Feb 29 12:47:02 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 199892 kb
Host smart-1cf15d4a-a93a-4fb1-9593-fc5beccdbbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277506762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2277506762
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.94075051
Short name T81
Test name
Test status
Simulation time 779879458 ps
CPU time 3.83 seconds
Started Feb 29 12:46:58 PM PST 24
Finished Feb 29 12:47:03 PM PST 24
Peak memory 200200 kb
Host smart-b3fd7114-f79a-423c-b8cd-6bd17ad32908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94075051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.94075051
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.800278851
Short name T537
Test name
Test status
Simulation time 162617022 ps
CPU time 1.11 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 200028 kb
Host smart-5d69ebe3-1655-4ff0-8c2d-357ba72b1b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800278851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.800278851
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.230510076
Short name T137
Test name
Test status
Simulation time 205317045 ps
CPU time 1.37 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:47 PM PST 24
Peak memory 200208 kb
Host smart-c5a4b0a8-442c-4e4a-aba1-e732a06f7f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230510076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.230510076
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.424506419
Short name T121
Test name
Test status
Simulation time 615902312 ps
CPU time 2.65 seconds
Started Feb 29 12:46:29 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 200204 kb
Host smart-b0410d80-9dee-43fc-b32e-170b4d011153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424506419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.424506419
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.134844488
Short name T199
Test name
Test status
Simulation time 317027616 ps
CPU time 2.06 seconds
Started Feb 29 12:46:34 PM PST 24
Finished Feb 29 12:46:36 PM PST 24
Peak memory 200116 kb
Host smart-5c903f08-96f7-4278-bcbc-16fae3d549e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134844488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.134844488
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1709231411
Short name T528
Test name
Test status
Simulation time 83441242 ps
CPU time 0.85 seconds
Started Feb 29 12:46:41 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 199980 kb
Host smart-992c70d8-7a4e-4828-88fa-5c931fe01bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709231411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1709231411
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2815640931
Short name T395
Test name
Test status
Simulation time 61370850 ps
CPU time 0.72 seconds
Started Feb 29 12:46:53 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 199484 kb
Host smart-8abecac3-6e65-46ae-8bd0-d69ec538a127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815640931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2815640931
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3398164689
Short name T389
Test name
Test status
Simulation time 1221424371 ps
CPU time 6.03 seconds
Started Feb 29 12:46:58 PM PST 24
Finished Feb 29 12:47:04 PM PST 24
Peak memory 217572 kb
Host smart-c5cc95b3-0dc2-42fa-bd65-bb0d13a8cc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398164689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3398164689
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.444866750
Short name T286
Test name
Test status
Simulation time 244439956 ps
CPU time 1.04 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:00 PM PST 24
Peak memory 217252 kb
Host smart-d91e772c-60f9-47df-a3f2-0f3967e35dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444866750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.444866750
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2922574200
Short name T231
Test name
Test status
Simulation time 238572743 ps
CPU time 0.9 seconds
Started Feb 29 12:46:33 PM PST 24
Finished Feb 29 12:46:34 PM PST 24
Peak memory 199800 kb
Host smart-9c1ca1d5-cdea-4c96-8248-e9f9e0c8c161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922574200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2922574200
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3032385339
Short name T481
Test name
Test status
Simulation time 1867135673 ps
CPU time 7.24 seconds
Started Feb 29 12:46:43 PM PST 24
Finished Feb 29 12:46:50 PM PST 24
Peak memory 200360 kb
Host smart-2a1b3f04-b180-442d-a178-303b4580f151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032385339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3032385339
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2083003889
Short name T61
Test name
Test status
Simulation time 172988538 ps
CPU time 1.14 seconds
Started Feb 29 12:47:12 PM PST 24
Finished Feb 29 12:47:15 PM PST 24
Peak memory 200036 kb
Host smart-2ab8c13b-6605-40b6-8133-3f7a5397ee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083003889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2083003889
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4086218726
Short name T466
Test name
Test status
Simulation time 245911291 ps
CPU time 1.54 seconds
Started Feb 29 12:46:41 PM PST 24
Finished Feb 29 12:46:43 PM PST 24
Peak memory 200236 kb
Host smart-322ee76c-037a-4a6a-8f1a-8c6daa2f2b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086218726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4086218726
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1303195565
Short name T372
Test name
Test status
Simulation time 6142546865 ps
CPU time 28.5 seconds
Started Feb 29 12:46:42 PM PST 24
Finished Feb 29 12:47:11 PM PST 24
Peak memory 200400 kb
Host smart-8926fb50-1fa4-4748-b927-0e5a785e557d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303195565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1303195565
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1085183032
Short name T488
Test name
Test status
Simulation time 377034235 ps
CPU time 2.37 seconds
Started Feb 29 12:46:54 PM PST 24
Finished Feb 29 12:46:57 PM PST 24
Peak memory 200112 kb
Host smart-51599a09-6ca9-4e84-9133-842f128cd200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085183032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1085183032
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.373517505
Short name T329
Test name
Test status
Simulation time 74121524 ps
CPU time 0.81 seconds
Started Feb 29 12:46:54 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 200036 kb
Host smart-66a7b4b8-fac4-4ffe-841f-b65d791fd446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373517505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.373517505
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1779914792
Short name T169
Test name
Test status
Simulation time 61232719 ps
CPU time 0.79 seconds
Started Feb 29 12:46:47 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 199904 kb
Host smart-06178f6e-e8c7-44ee-925f-249f52791745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779914792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1779914792
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3882251885
Short name T388
Test name
Test status
Simulation time 244371742 ps
CPU time 1.05 seconds
Started Feb 29 12:47:07 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 217256 kb
Host smart-83c5b3fb-bf1e-4842-992e-bc2742020f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882251885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3882251885
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1473694949
Short name T280
Test name
Test status
Simulation time 171998753 ps
CPU time 0.81 seconds
Started Feb 29 12:46:53 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 199884 kb
Host smart-a1251343-c61c-49f6-b3c3-9a453d9f0de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473694949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1473694949
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2984895262
Short name T391
Test name
Test status
Simulation time 815164976 ps
CPU time 4.37 seconds
Started Feb 29 12:47:01 PM PST 24
Finished Feb 29 12:47:06 PM PST 24
Peak memory 200228 kb
Host smart-ade37869-a770-4c32-a730-d7c7810cd740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984895262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2984895262
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2422303394
Short name T204
Test name
Test status
Simulation time 112904819 ps
CPU time 1.04 seconds
Started Feb 29 12:46:52 PM PST 24
Finished Feb 29 12:46:54 PM PST 24
Peak memory 200064 kb
Host smart-c9a8aa15-7c22-4e0c-9960-b5889e4fd2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422303394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2422303394
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.4132951190
Short name T278
Test name
Test status
Simulation time 251746960 ps
CPU time 1.44 seconds
Started Feb 29 12:46:51 PM PST 24
Finished Feb 29 12:46:53 PM PST 24
Peak memory 200264 kb
Host smart-62efe1a5-5841-4517-aabe-73ccb9d33902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132951190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4132951190
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3138599268
Short name T193
Test name
Test status
Simulation time 1178748603 ps
CPU time 5.09 seconds
Started Feb 29 12:46:41 PM PST 24
Finished Feb 29 12:46:46 PM PST 24
Peak memory 200276 kb
Host smart-a92d222a-d512-46aa-aa08-5cd9002d64dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138599268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3138599268
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1957689407
Short name T303
Test name
Test status
Simulation time 537864478 ps
CPU time 2.65 seconds
Started Feb 29 12:46:45 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 200016 kb
Host smart-d1534e45-ac84-412b-b27d-61689c109269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957689407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1957689407
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3138837066
Short name T288
Test name
Test status
Simulation time 69914759 ps
CPU time 0.73 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:12 PM PST 24
Peak memory 200072 kb
Host smart-1664a609-118e-4c46-ad28-ae0e79265afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138837066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3138837066
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.390800275
Short name T166
Test name
Test status
Simulation time 65699016 ps
CPU time 0.75 seconds
Started Feb 29 12:46:46 PM PST 24
Finished Feb 29 12:46:47 PM PST 24
Peak memory 199904 kb
Host smart-b0339374-7a0e-445c-b879-c66093b0d102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390800275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.390800275
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.242198382
Short name T465
Test name
Test status
Simulation time 1225871880 ps
CPU time 5.62 seconds
Started Feb 29 12:47:09 PM PST 24
Finished Feb 29 12:47:17 PM PST 24
Peak memory 217952 kb
Host smart-7c7a3369-1ce6-473f-98c8-81dde0df1dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242198382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.242198382
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3747259427
Short name T185
Test name
Test status
Simulation time 244031177 ps
CPU time 1.06 seconds
Started Feb 29 12:46:53 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 217164 kb
Host smart-670db652-9a39-41c5-beae-40cbc4e81a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747259427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3747259427
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2877548133
Short name T339
Test name
Test status
Simulation time 161983762 ps
CPU time 0.86 seconds
Started Feb 29 12:46:49 PM PST 24
Finished Feb 29 12:46:50 PM PST 24
Peak memory 199784 kb
Host smart-acf4e35f-141a-40bf-b4aa-bd9aad0e7589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877548133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2877548133
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3474793388
Short name T221
Test name
Test status
Simulation time 866917377 ps
CPU time 4.64 seconds
Started Feb 29 12:46:53 PM PST 24
Finished Feb 29 12:46:57 PM PST 24
Peak memory 200252 kb
Host smart-2728051f-db00-4bd0-b5dc-1bde7fa7e028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474793388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3474793388
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.776328540
Short name T487
Test name
Test status
Simulation time 173066674 ps
CPU time 1.09 seconds
Started Feb 29 12:46:41 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 199976 kb
Host smart-baaaae2b-97fb-4c47-9725-3dd522e5492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776328540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.776328540
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1522790952
Short name T356
Test name
Test status
Simulation time 201033988 ps
CPU time 1.38 seconds
Started Feb 29 12:46:54 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 200356 kb
Host smart-67c3fff1-9f71-485b-bb39-1b6a645aad7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522790952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1522790952
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3519463643
Short name T264
Test name
Test status
Simulation time 1128459126 ps
CPU time 5.03 seconds
Started Feb 29 12:46:59 PM PST 24
Finished Feb 29 12:47:04 PM PST 24
Peak memory 200220 kb
Host smart-29e2ca69-6ec1-4dcd-b505-f06967be2df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519463643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3519463643
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.135382026
Short name T289
Test name
Test status
Simulation time 354826930 ps
CPU time 2.05 seconds
Started Feb 29 12:46:57 PM PST 24
Finished Feb 29 12:46:59 PM PST 24
Peak memory 200096 kb
Host smart-401264f5-c6df-42df-89f4-f48a7ed2dbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135382026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.135382026
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3572554679
Short name T202
Test name
Test status
Simulation time 132119207 ps
CPU time 1.03 seconds
Started Feb 29 12:46:52 PM PST 24
Finished Feb 29 12:46:54 PM PST 24
Peak memory 200076 kb
Host smart-dc4a60c8-a364-4c71-8ba7-fcdb010d4770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572554679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3572554679
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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