Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8909

1

T1

12

T3

34

T4

16

auto[1]

11791

1

T1

1

T3

28

T4

85

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6332	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6965	1			T1	1		T2	1		T3	20
reset_info_cp[2]	3251	1			T3	10		T4	19		T7	20
reset_info_cp[4]	4163	1			T3	15		T4	16		T7	13
reset_info_cp[8]	113	1			T3	1		T6	1		T7	1
reset_info_cp[16]	122	1			T6	1		T7	1		T8	2
reset_info_cp[32]	124	1			T1	1		T3	1		T6	2
reset_info_cp[64]	128	1			T3	2		T4	3		T69	5
reset_info_cp[128]	122	1			T4	1		T6	1		T7	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3343	1			T3	8		T4	16		T7	18
reset_info_cp[1]	auto[1]	3002	1			T3	11		T4	10		T7	8
reset_info_cp[2]	auto[0]	1080	1			T3	7		T9	6		T11	4
reset_info_cp[2]	auto[1]	2171	1			T3	3		T4	19		T7	20
reset_info_cp[4]	auto[0]	1549	1			T3	10		T9	10		T11	5
reset_info_cp[4]	auto[1]	2614	1			T3	5		T4	16		T7	13
reset_info_cp[8]	auto[0]	52	1			T6	1		T21	1		T69	3
reset_info_cp[8]	auto[1]	61	1			T3	1		T7	1		T69	1
reset_info_cp[16]	auto[0]	44	1			T6	1		T71	1		T92	1
reset_info_cp[16]	auto[1]	78	1			T7	1		T8	2		T10	1
reset_info_cp[32]	auto[0]	50	1			T1	1		T6	2		T21	1
reset_info_cp[32]	auto[1]	74	1			T3	1		T21	1		T94	2
reset_info_cp[64]	auto[0]	39	1			T69	3		T132	1		T133	1
reset_info_cp[64]	auto[1]	89	1			T3	2		T4	3		T69	2
reset_info_cp[128]	auto[0]	47	1			T6	1		T21	1		T33	2
reset_info_cp[128]	auto[1]	75	1			T4	1		T7	1		T8	1