Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T539 /workspace/coverage/default/10.rstmgr_stress_all.112314083 Mar 03 12:45:51 PM PST 24 Mar 03 12:46:20 PM PST 24 7235745529 ps
T540 /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1787480201 Mar 03 12:45:45 PM PST 24 Mar 03 12:45:46 PM PST 24 246281502 ps
T541 /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.278971404 Mar 03 12:47:07 PM PST 24 Mar 03 12:47:08 PM PST 24 110749874 ps
T542 /workspace/coverage/default/4.rstmgr_reset.1276883728 Mar 03 12:45:45 PM PST 24 Mar 03 12:45:52 PM PST 24 1981925443 ps
T543 /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2442053774 Mar 03 12:45:37 PM PST 24 Mar 03 12:45:43 PM PST 24 1220958141 ps
T49 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1902491208 Mar 03 12:31:42 PM PST 24 Mar 03 12:31:44 PM PST 24 272902156 ps
T50 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2028882592 Mar 03 12:31:34 PM PST 24 Mar 03 12:31:35 PM PST 24 175189898 ps
T51 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3238466000 Mar 03 12:31:46 PM PST 24 Mar 03 12:31:47 PM PST 24 75658791 ps
T54 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.653492585 Mar 03 12:31:29 PM PST 24 Mar 03 12:31:32 PM PST 24 199236776 ps
T77 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.244611435 Mar 03 12:31:37 PM PST 24 Mar 03 12:31:39 PM PST 24 204623412 ps
T116 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.271458668 Mar 03 12:32:01 PM PST 24 Mar 03 12:32:02 PM PST 24 148153385 ps
T55 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.525741445 Mar 03 12:31:30 PM PST 24 Mar 03 12:31:43 PM PST 24 383232290 ps
T117 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3528280540 Mar 03 12:31:51 PM PST 24 Mar 03 12:31:53 PM PST 24 67442375 ps
T56 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2350093517 Mar 03 12:31:47 PM PST 24 Mar 03 12:31:49 PM PST 24 181985478 ps
T118 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.766094653 Mar 03 12:32:14 PM PST 24 Mar 03 12:32:16 PM PST 24 252073874 ps
T57 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3673498628 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:36 PM PST 24 788112466 ps
T73 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1237011007 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:06 PM PST 24 163487899 ps
T119 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3882964877 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:34 PM PST 24 77618144 ps
T101 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2047586505 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:34 PM PST 24 210197389 ps
T544 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1309907860 Mar 03 12:31:46 PM PST 24 Mar 03 12:31:47 PM PST 24 73029332 ps
T129 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.341461074 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:37 PM PST 24 264915860 ps
T545 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4263044137 Mar 03 12:31:39 PM PST 24 Mar 03 12:31:41 PM PST 24 96403965 ps
T74 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2555255310 Mar 03 12:31:29 PM PST 24 Mar 03 12:31:32 PM PST 24 176984560 ps
T120 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3565378771 Mar 03 12:31:37 PM PST 24 Mar 03 12:31:39 PM PST 24 69147364 ps
T81 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3196975528 Mar 03 12:31:51 PM PST 24 Mar 03 12:31:54 PM PST 24 248489133 ps
T102 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1290368718 Mar 03 12:31:53 PM PST 24 Mar 03 12:31:55 PM PST 24 104986043 ps
T75 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1862102978 Mar 03 12:31:34 PM PST 24 Mar 03 12:31:36 PM PST 24 466612443 ps
T121 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3467744415 Mar 03 12:31:49 PM PST 24 Mar 03 12:31:51 PM PST 24 60077894 ps
T122 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1025917188 Mar 03 12:31:36 PM PST 24 Mar 03 12:31:37 PM PST 24 158244471 ps
T76 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.721637157 Mar 03 12:32:01 PM PST 24 Mar 03 12:32:05 PM PST 24 950208480 ps
T123 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2223213434 Mar 03 12:31:30 PM PST 24 Mar 03 12:31:31 PM PST 24 70320385 ps
T546 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3327469213 Mar 03 12:31:41 PM PST 24 Mar 03 12:31:42 PM PST 24 84611075 ps
T80 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.510864929 Mar 03 12:31:30 PM PST 24 Mar 03 12:31:31 PM PST 24 117744941 ps
T82 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1475297343 Mar 03 12:31:45 PM PST 24 Mar 03 12:31:48 PM PST 24 451445268 ps
T78 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3349757237 Mar 03 12:31:39 PM PST 24 Mar 03 12:31:43 PM PST 24 189364786 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2065689416 Mar 03 12:31:29 PM PST 24 Mar 03 12:31:31 PM PST 24 126648153 ps
T548 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3672909223 Mar 03 12:31:57 PM PST 24 Mar 03 12:31:59 PM PST 24 70446502 ps
T549 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.476401101 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:05 PM PST 24 57694023 ps
T550 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2061492277 Mar 03 12:31:30 PM PST 24 Mar 03 12:31:31 PM PST 24 111859085 ps
T551 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3652094261 Mar 03 12:31:35 PM PST 24 Mar 03 12:31:37 PM PST 24 86414892 ps
T79 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2627885002 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:33 PM PST 24 123825976 ps
T91 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.604077996 Mar 03 12:31:53 PM PST 24 Mar 03 12:31:56 PM PST 24 176526817 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3522829586 Mar 03 12:31:31 PM PST 24 Mar 03 12:31:33 PM PST 24 126566694 ps
T85 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.962294230 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:35 PM PST 24 786838534 ps
T553 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2362781490 Mar 03 12:31:18 PM PST 24 Mar 03 12:31:19 PM PST 24 114980971 ps
T554 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3303581735 Mar 03 12:31:34 PM PST 24 Mar 03 12:31:36 PM PST 24 492250717 ps
T555 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2474383365 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:35 PM PST 24 198654820 ps
T556 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.174960729 Mar 03 12:31:56 PM PST 24 Mar 03 12:31:57 PM PST 24 68772226 ps
T557 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3563545419 Mar 03 12:31:36 PM PST 24 Mar 03 12:31:40 PM PST 24 203400086 ps
T558 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1210393147 Mar 03 12:31:35 PM PST 24 Mar 03 12:31:37 PM PST 24 81648924 ps
T90 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3291307517 Mar 03 12:31:57 PM PST 24 Mar 03 12:31:58 PM PST 24 103856028 ps
T559 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3547471086 Mar 03 12:31:43 PM PST 24 Mar 03 12:31:45 PM PST 24 139485355 ps
T560 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3878121523 Mar 03 12:31:34 PM PST 24 Mar 03 12:31:36 PM PST 24 206080824 ps
T561 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3747230322 Mar 03 12:32:01 PM PST 24 Mar 03 12:32:03 PM PST 24 179830460 ps
T562 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1282821718 Mar 03 12:32:56 PM PST 24 Mar 03 12:32:58 PM PST 24 166287956 ps
T563 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.325337465 Mar 03 12:31:36 PM PST 24 Mar 03 12:31:40 PM PST 24 439324801 ps
T564 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3514992720 Mar 03 12:31:53 PM PST 24 Mar 03 12:31:54 PM PST 24 127193996 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1640424951 Mar 03 12:31:34 PM PST 24 Mar 03 12:31:37 PM PST 24 365912439 ps
T566 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.786737337 Mar 03 12:31:42 PM PST 24 Mar 03 12:31:44 PM PST 24 63647969 ps
T567 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2007388369 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:35 PM PST 24 188617796 ps
T568 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1475062219 Mar 03 12:31:51 PM PST 24 Mar 03 12:31:53 PM PST 24 127580486 ps
T569 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3822183513 Mar 03 12:31:46 PM PST 24 Mar 03 12:31:49 PM PST 24 287083671 ps
T570 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1336679789 Mar 03 12:31:36 PM PST 24 Mar 03 12:31:38 PM PST 24 128733455 ps
T571 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1534368261 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:35 PM PST 24 221607063 ps
T572 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2460784861 Mar 03 12:32:02 PM PST 24 Mar 03 12:32:05 PM PST 24 349108331 ps
T573 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.292389685 Mar 03 12:32:07 PM PST 24 Mar 03 12:32:08 PM PST 24 84028209 ps
T574 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2696388408 Mar 03 12:31:40 PM PST 24 Mar 03 12:31:42 PM PST 24 180957231 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.405453958 Mar 03 12:31:44 PM PST 24 Mar 03 12:31:45 PM PST 24 96110452 ps
T576 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3375403947 Mar 03 12:31:36 PM PST 24 Mar 03 12:31:37 PM PST 24 137411802 ps
T577 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3845089889 Mar 03 12:31:35 PM PST 24 Mar 03 12:31:38 PM PST 24 130152467 ps
T578 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1793807134 Mar 03 12:31:56 PM PST 24 Mar 03 12:31:57 PM PST 24 131611493 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2853330339 Mar 03 12:31:42 PM PST 24 Mar 03 12:31:44 PM PST 24 148617139 ps
T580 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1773415140 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:34 PM PST 24 62112015 ps
T581 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.426083299 Mar 03 12:31:26 PM PST 24 Mar 03 12:31:28 PM PST 24 282706267 ps
T582 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4108100283 Mar 03 12:31:37 PM PST 24 Mar 03 12:31:39 PM PST 24 78774462 ps
T86 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1109061120 Mar 03 12:31:54 PM PST 24 Mar 03 12:31:58 PM PST 24 938740693 ps
T128 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.592398067 Mar 03 12:31:45 PM PST 24 Mar 03 12:31:48 PM PST 24 403996381 ps
T583 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3134360794 Mar 03 12:31:35 PM PST 24 Mar 03 12:31:37 PM PST 24 122403733 ps
T88 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3122182531 Mar 03 12:31:28 PM PST 24 Mar 03 12:31:32 PM PST 24 806000363 ps
T584 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.44996972 Mar 03 12:31:39 PM PST 24 Mar 03 12:31:41 PM PST 24 86444667 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1356266158 Mar 03 12:31:50 PM PST 24 Mar 03 12:31:52 PM PST 24 415041290 ps
T586 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.994796077 Mar 03 12:31:41 PM PST 24 Mar 03 12:31:43 PM PST 24 77074969 ps
T587 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1858039536 Mar 03 12:31:47 PM PST 24 Mar 03 12:31:49 PM PST 24 115486269 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.95890626 Mar 03 12:31:39 PM PST 24 Mar 03 12:31:41 PM PST 24 146580527 ps
T589 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3814989854 Mar 03 12:31:39 PM PST 24 Mar 03 12:31:41 PM PST 24 117362979 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2043258744 Mar 03 12:31:51 PM PST 24 Mar 03 12:31:52 PM PST 24 102537370 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.368168803 Mar 03 12:31:39 PM PST 24 Mar 03 12:31:41 PM PST 24 69276321 ps
T592 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3579589907 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:36 PM PST 24 426331886 ps
T87 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4264151266 Mar 03 12:32:01 PM PST 24 Mar 03 12:32:03 PM PST 24 463117590 ps
T593 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1719924619 Mar 03 12:31:30 PM PST 24 Mar 03 12:31:32 PM PST 24 493614540 ps
T594 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1273886922 Mar 03 12:31:58 PM PST 24 Mar 03 12:31:59 PM PST 24 137694839 ps
T89 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3323718475 Mar 03 12:31:39 PM PST 24 Mar 03 12:31:48 PM PST 24 880410335 ps
T595 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.429490175 Mar 03 12:31:46 PM PST 24 Mar 03 12:31:47 PM PST 24 137357592 ps
T83 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3616636473 Mar 03 12:32:02 PM PST 24 Mar 03 12:32:05 PM PST 24 802328337 ps
T596 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.204894110 Mar 03 12:31:42 PM PST 24 Mar 03 12:31:43 PM PST 24 186081813 ps
T597 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2434606318 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:35 PM PST 24 65075235 ps
T598 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1714411616 Mar 03 12:31:54 PM PST 24 Mar 03 12:31:55 PM PST 24 75693187 ps
T599 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.543447616 Mar 03 12:31:43 PM PST 24 Mar 03 12:31:45 PM PST 24 190034432 ps
T600 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3390889853 Mar 03 12:31:42 PM PST 24 Mar 03 12:31:45 PM PST 24 433738856 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2396737650 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:34 PM PST 24 132316007 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.909117493 Mar 03 12:31:34 PM PST 24 Mar 03 12:31:39 PM PST 24 481943099 ps
T603 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3096358599 Mar 03 12:31:39 PM PST 24 Mar 03 12:31:42 PM PST 24 149951938 ps
T604 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2650469708 Mar 03 12:31:38 PM PST 24 Mar 03 12:31:48 PM PST 24 1989758488 ps
T605 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2205109294 Mar 03 12:31:34 PM PST 24 Mar 03 12:31:36 PM PST 24 96784354 ps
T606 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2753693339 Mar 03 12:31:30 PM PST 24 Mar 03 12:31:31 PM PST 24 65113015 ps
T84 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1049274121 Mar 03 12:32:00 PM PST 24 Mar 03 12:32:03 PM PST 24 881784951 ps
T607 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1075324976 Mar 03 12:31:36 PM PST 24 Mar 03 12:31:38 PM PST 24 67910675 ps
T608 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.4120079049 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:34 PM PST 24 112410112 ps
T609 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.531188238 Mar 03 12:31:54 PM PST 24 Mar 03 12:31:58 PM PST 24 646956005 ps
T610 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1048302680 Mar 03 12:31:43 PM PST 24 Mar 03 12:31:45 PM PST 24 80077103 ps
T611 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3766426709 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:36 PM PST 24 886665492 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3717562717 Mar 03 12:32:01 PM PST 24 Mar 03 12:32:12 PM PST 24 2288872488 ps
T613 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.736320822 Mar 03 12:32:00 PM PST 24 Mar 03 12:32:01 PM PST 24 156326816 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2375751853 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:36 PM PST 24 1032504016 ps
T615 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3067578975 Mar 03 12:31:36 PM PST 24 Mar 03 12:31:40 PM PST 24 468959430 ps
T616 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3851458978 Mar 03 12:31:47 PM PST 24 Mar 03 12:31:48 PM PST 24 422247940 ps
T617 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.801432893 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:36 PM PST 24 809292332 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3425199455 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:35 PM PST 24 123832758 ps
T619 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3933093945 Mar 03 12:33:01 PM PST 24 Mar 03 12:33:03 PM PST 24 125111518 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.462411672 Mar 03 12:31:38 PM PST 24 Mar 03 12:31:49 PM PST 24 2278003582 ps

Test location /workspace/coverage/default/42.rstmgr_reset.2160807314
Short name T3
Test name
Test status
Simulation time 1880886807 ps
CPU time 7.23 seconds
Started Mar 03 12:46:36 PM PST 24
Finished Mar 03 12:46:44 PM PST 24
Peak memory 200244 kb
Host smart-2919e5d0-7423-496c-9d56-c8842118d39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160807314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2160807314
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.983074948
Short name T5
Test name
Test status
Simulation time 496785587 ps
CPU time 2.82 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 199964 kb
Host smart-8e1eb134-4fd4-46d6-bd7b-5b6437a477cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983074948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.983074948
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.653492585
Short name T54
Test name
Test status
Simulation time 199236776 ps
CPU time 2.13 seconds
Started Mar 03 12:31:29 PM PST 24
Finished Mar 03 12:31:32 PM PST 24
Peak memory 208080 kb
Host smart-83ed7139-3bc3-41f8-a817-ba41c0910f96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653492585 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.653492585
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2334042697
Short name T58
Test name
Test status
Simulation time 16510402898 ps
CPU time 28.28 seconds
Started Mar 03 12:45:39 PM PST 24
Finished Mar 03 12:46:09 PM PST 24
Peak memory 216860 kb
Host smart-43db6c91-b11d-4c0e-b7fc-76cca5b288e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334042697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2334042697
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3234096130
Short name T7
Test name
Test status
Simulation time 1912623744 ps
CPU time 6.97 seconds
Started Mar 03 12:46:26 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 218012 kb
Host smart-cb22d9cd-681e-4c90-bfae-1462831de7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234096130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3234096130
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.721637157
Short name T76
Test name
Test status
Simulation time 950208480 ps
CPU time 3.31 seconds
Started Mar 03 12:32:01 PM PST 24
Finished Mar 03 12:32:05 PM PST 24
Peak memory 200704 kb
Host smart-495aa945-d83a-4e45-b454-7f0b357974d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721637157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.721637157
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2517634709
Short name T106
Test name
Test status
Simulation time 12303042535 ps
CPU time 42.3 seconds
Started Mar 03 12:46:18 PM PST 24
Finished Mar 03 12:47:01 PM PST 24
Peak memory 208480 kb
Host smart-2048cd58-3e9d-43d9-8c9d-8623583ae820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517634709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2517634709
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1281249695
Short name T61
Test name
Test status
Simulation time 69118874 ps
CPU time 0.78 seconds
Started Mar 03 12:46:32 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 199924 kb
Host smart-80edcb64-e572-4a89-a31c-8eed9513fdd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281249695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1281249695
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1619268497
Short name T149
Test name
Test status
Simulation time 143499659 ps
CPU time 1.11 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:45:57 PM PST 24
Peak memory 200272 kb
Host smart-ac3c55fd-b27c-49ac-9325-1c99d2cb7975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619268497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1619268497
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1907287611
Short name T22
Test name
Test status
Simulation time 2359386803 ps
CPU time 8.31 seconds
Started Mar 03 12:45:42 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 217216 kb
Host smart-bb93d245-3418-40e2-a201-70d87472da01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907287611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1907287611
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.525741445
Short name T55
Test name
Test status
Simulation time 383232290 ps
CPU time 2.81 seconds
Started Mar 03 12:31:30 PM PST 24
Finished Mar 03 12:31:43 PM PST 24
Peak memory 208504 kb
Host smart-e9ed29f5-b949-44f0-982c-972ae2dc3faf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525741445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.525741445
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.962294230
Short name T85
Test name
Test status
Simulation time 786838534 ps
CPU time 2.66 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 200480 kb
Host smart-87976d62-d84e-432a-b0fc-c8556d2f1631
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962294230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
962294230
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3673498628
Short name T57
Test name
Test status
Simulation time 788112466 ps
CPU time 2.94 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:36 PM PST 24
Peak memory 208672 kb
Host smart-627d656a-cfb8-41db-b5f9-bda853c61ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673498628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3673498628
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.4115917799
Short name T32
Test name
Test status
Simulation time 1226707419 ps
CPU time 5.4 seconds
Started Mar 03 12:46:09 PM PST 24
Finished Mar 03 12:46:15 PM PST 24
Peak memory 216120 kb
Host smart-14cb526b-5c49-4405-8d06-800226fcb708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115917799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.4115917799
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1711352478
Short name T71
Test name
Test status
Simulation time 188988531 ps
CPU time 1.31 seconds
Started Mar 03 12:45:47 PM PST 24
Finished Mar 03 12:45:50 PM PST 24
Peak memory 199908 kb
Host smart-d35630f6-3bb7-4f72-8be4-8669af46f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711352478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1711352478
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1025917188
Short name T122
Test name
Test status
Simulation time 158244471 ps
CPU time 1.22 seconds
Started Mar 03 12:31:36 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 200108 kb
Host smart-49b2490a-ade9-405f-b0ef-aef6b3d24edb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025917188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1025917188
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2534596198
Short name T15
Test name
Test status
Simulation time 88858145 ps
CPU time 0.71 seconds
Started Mar 03 12:46:06 PM PST 24
Finished Mar 03 12:46:08 PM PST 24
Peak memory 199824 kb
Host smart-2bae25d5-0fbc-4b34-b197-cb3338652e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534596198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2534596198
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3616636473
Short name T83
Test name
Test status
Simulation time 802328337 ps
CPU time 2.71 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:32:05 PM PST 24
Peak memory 200744 kb
Host smart-298f09d3-deb2-409a-9f74-df7040ce3d19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616636473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3616636473
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.523365045
Short name T267
Test name
Test status
Simulation time 4601766936 ps
CPU time 23.55 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:45 PM PST 24
Peak memory 208416 kb
Host smart-38968983-4a5b-4813-a98d-494485348e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523365045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.523365045
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.405453958
Short name T575
Test name
Test status
Simulation time 96110452 ps
CPU time 1.3 seconds
Started Mar 03 12:31:44 PM PST 24
Finished Mar 03 12:31:45 PM PST 24
Peak memory 200440 kb
Host smart-445721b0-8e55-40fd-a86f-1484a04d86cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405453958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.405453958
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.341461074
Short name T129
Test name
Test status
Simulation time 264915860 ps
CPU time 3.3 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 199812 kb
Host smart-b482c92d-5a04-4ee7-89a6-927d530b61e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341461074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.341461074
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2065689416
Short name T547
Test name
Test status
Simulation time 126648153 ps
CPU time 0.97 seconds
Started Mar 03 12:31:29 PM PST 24
Finished Mar 03 12:31:31 PM PST 24
Peak memory 199648 kb
Host smart-8cd2dea5-be0b-40e4-a2f8-3c3befaccd90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065689416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
065689416
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2350093517
Short name T56
Test name
Test status
Simulation time 181985478 ps
CPU time 1.14 seconds
Started Mar 03 12:31:47 PM PST 24
Finished Mar 03 12:31:49 PM PST 24
Peak memory 208792 kb
Host smart-161121b7-0f41-4340-9792-f79a77c71d9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350093517 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2350093517
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.476401101
Short name T549
Test name
Test status
Simulation time 57694023 ps
CPU time 0.8 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:05 PM PST 24
Peak memory 200544 kb
Host smart-44c6ba64-8448-4fc6-b60c-1d86e33d3534
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476401101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.476401101
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3425199455
Short name T618
Test name
Test status
Simulation time 123832758 ps
CPU time 1.3 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 199332 kb
Host smart-5a582759-7a39-42c2-9a1c-6dffc7a24f28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425199455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3425199455
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1534368261
Short name T571
Test name
Test status
Simulation time 221607063 ps
CPU time 1.8 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 208668 kb
Host smart-5bf86882-f8a0-43df-b8df-2600da3d1593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534368261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1534368261
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3096358599
Short name T603
Test name
Test status
Simulation time 149951938 ps
CPU time 1.93 seconds
Started Mar 03 12:31:39 PM PST 24
Finished Mar 03 12:31:42 PM PST 24
Peak memory 198908 kb
Host smart-28428430-649d-4bbb-95ed-83bc3c3c3b46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096358599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
096358599
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.462411672
Short name T620
Test name
Test status
Simulation time 2278003582 ps
CPU time 9.75 seconds
Started Mar 03 12:31:38 PM PST 24
Finished Mar 03 12:31:49 PM PST 24
Peak memory 201120 kb
Host smart-34830695-ea85-42e5-be1b-f57bbc692828
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462411672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.462411672
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2362781490
Short name T553
Test name
Test status
Simulation time 114980971 ps
CPU time 0.86 seconds
Started Mar 03 12:31:18 PM PST 24
Finished Mar 03 12:31:19 PM PST 24
Peak memory 200396 kb
Host smart-6a72ecbd-71a1-4722-ae13-b2a300b45371
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362781490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
362781490
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.95890626
Short name T588
Test name
Test status
Simulation time 146580527 ps
CPU time 1.21 seconds
Started Mar 03 12:31:39 PM PST 24
Finished Mar 03 12:31:41 PM PST 24
Peak memory 199000 kb
Host smart-8dea52a5-4a7e-479d-b0a7-619c914d50b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95890626 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.95890626
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.786737337
Short name T566
Test name
Test status
Simulation time 63647969 ps
CPU time 0.73 seconds
Started Mar 03 12:31:42 PM PST 24
Finished Mar 03 12:31:44 PM PST 24
Peak memory 200484 kb
Host smart-4c210c33-bae1-4f8c-9734-42d6bffdad05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786737337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.786737337
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.4120079049
Short name T608
Test name
Test status
Simulation time 112410112 ps
CPU time 1.23 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:34 PM PST 24
Peak memory 200504 kb
Host smart-f828e8fc-6304-461e-9fb5-46e44168a7d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120079049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.4120079049
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.426083299
Short name T581
Test name
Test status
Simulation time 282706267 ps
CPU time 2.01 seconds
Started Mar 03 12:31:26 PM PST 24
Finished Mar 03 12:31:28 PM PST 24
Peak memory 208032 kb
Host smart-2502497c-7ee5-4f96-a016-5f4daf911ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426083299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.426083299
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.204894110
Short name T596
Test name
Test status
Simulation time 186081813 ps
CPU time 1.2 seconds
Started Mar 03 12:31:42 PM PST 24
Finished Mar 03 12:31:43 PM PST 24
Peak memory 208792 kb
Host smart-6f1309fd-8959-4b3d-aed0-4cbcc4ce814d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204894110 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.204894110
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1075324976
Short name T607
Test name
Test status
Simulation time 67910675 ps
CPU time 0.84 seconds
Started Mar 03 12:31:36 PM PST 24
Finished Mar 03 12:31:38 PM PST 24
Peak memory 200280 kb
Host smart-8d4e224b-dc9c-4916-be7b-80cd3dfee50a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075324976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1075324976
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1475062219
Short name T568
Test name
Test status
Simulation time 127580486 ps
CPU time 1.09 seconds
Started Mar 03 12:31:51 PM PST 24
Finished Mar 03 12:31:53 PM PST 24
Peak memory 200368 kb
Host smart-3075c5e0-4983-4e7a-b2a5-ce35443064b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475062219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1475062219
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3196975528
Short name T81
Test name
Test status
Simulation time 248489133 ps
CPU time 2.14 seconds
Started Mar 03 12:31:51 PM PST 24
Finished Mar 03 12:31:54 PM PST 24
Peak memory 200592 kb
Host smart-20305905-aa70-4754-8db0-a8915ca45e30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196975528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3196975528
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.543447616
Short name T599
Test name
Test status
Simulation time 190034432 ps
CPU time 1.34 seconds
Started Mar 03 12:31:43 PM PST 24
Finished Mar 03 12:31:45 PM PST 24
Peak memory 209144 kb
Host smart-81157d56-7ffd-4ab9-96db-5e4455921495
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543447616 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.543447616
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1714411616
Short name T598
Test name
Test status
Simulation time 75693187 ps
CPU time 0.83 seconds
Started Mar 03 12:31:54 PM PST 24
Finished Mar 03 12:31:55 PM PST 24
Peak memory 200528 kb
Host smart-f0735976-c681-43f9-ba33-9a457fca5cf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714411616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1714411616
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3845089889
Short name T577
Test name
Test status
Simulation time 130152467 ps
CPU time 1.66 seconds
Started Mar 03 12:31:35 PM PST 24
Finished Mar 03 12:31:38 PM PST 24
Peak memory 207616 kb
Host smart-cf3fd15a-5b1b-46cb-8644-a14f89e52f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845089889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3845089889
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1109061120
Short name T86
Test name
Test status
Simulation time 938740693 ps
CPU time 3.6 seconds
Started Mar 03 12:31:54 PM PST 24
Finished Mar 03 12:31:58 PM PST 24
Peak memory 201096 kb
Host smart-95fcc81c-3dbf-4285-9e60-0184c51a3cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109061120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1109061120
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3134360794
Short name T583
Test name
Test status
Simulation time 122403733 ps
CPU time 1.36 seconds
Started Mar 03 12:31:35 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 207420 kb
Host smart-e5a18645-7cfc-45b1-a8f2-39b841709b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134360794 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3134360794
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2753693339
Short name T606
Test name
Test status
Simulation time 65113015 ps
CPU time 0.74 seconds
Started Mar 03 12:31:30 PM PST 24
Finished Mar 03 12:31:31 PM PST 24
Peak memory 200172 kb
Host smart-bc92f5cc-5a92-4e78-b0cf-8a0afb641437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753693339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2753693339
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1902491208
Short name T49
Test name
Test status
Simulation time 272902156 ps
CPU time 1.63 seconds
Started Mar 03 12:31:42 PM PST 24
Finished Mar 03 12:31:44 PM PST 24
Peak memory 199852 kb
Host smart-97599a3a-5023-498b-a7f6-a41f1aade576
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902491208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1902491208
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3122182531
Short name T88
Test name
Test status
Simulation time 806000363 ps
CPU time 2.77 seconds
Started Mar 03 12:31:28 PM PST 24
Finished Mar 03 12:31:32 PM PST 24
Peak memory 199828 kb
Host smart-1a6f83d2-d5a3-42ce-a912-e72327242bbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122182531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3122182531
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2205109294
Short name T605
Test name
Test status
Simulation time 96784354 ps
CPU time 0.87 seconds
Started Mar 03 12:31:34 PM PST 24
Finished Mar 03 12:31:36 PM PST 24
Peak memory 200228 kb
Host smart-467c3010-3834-4af8-a274-eccfc1028cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205109294 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2205109294
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3652094261
Short name T551
Test name
Test status
Simulation time 86414892 ps
CPU time 0.9 seconds
Started Mar 03 12:31:35 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 199508 kb
Host smart-e679257c-8649-4dad-99fd-ef96cf9579fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652094261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3652094261
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.429490175
Short name T595
Test name
Test status
Simulation time 137357592 ps
CPU time 1.06 seconds
Started Mar 03 12:31:46 PM PST 24
Finished Mar 03 12:31:47 PM PST 24
Peak memory 200480 kb
Host smart-6de09022-0c08-4b77-b492-9b24190a3298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429490175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.429490175
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3579589907
Short name T592
Test name
Test status
Simulation time 426331886 ps
CPU time 3.03 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:36 PM PST 24
Peak memory 208820 kb
Host smart-737c7b0b-72c8-42fa-b8dd-646498eaaa83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579589907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3579589907
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.801432893
Short name T617
Test name
Test status
Simulation time 809292332 ps
CPU time 2.72 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:36 PM PST 24
Peak memory 199788 kb
Host smart-44a273b1-3c29-4507-b7a0-12ac8b4b99c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801432893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.801432893
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2627885002
Short name T79
Test name
Test status
Simulation time 123825976 ps
CPU time 1.35 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:33 PM PST 24
Peak memory 207856 kb
Host smart-f645c243-17d4-4149-82a2-94b00205aa70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627885002 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2627885002
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3565378771
Short name T120
Test name
Test status
Simulation time 69147364 ps
CPU time 0.85 seconds
Started Mar 03 12:31:37 PM PST 24
Finished Mar 03 12:31:39 PM PST 24
Peak memory 200472 kb
Host smart-f74a2e44-9ffd-4e8b-aec9-31c83892403b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565378771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3565378771
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.292389685
Short name T573
Test name
Test status
Simulation time 84028209 ps
CPU time 0.99 seconds
Started Mar 03 12:32:07 PM PST 24
Finished Mar 03 12:32:08 PM PST 24
Peak memory 200516 kb
Host smart-5551b22d-cedc-4fa6-9173-a06935d54c68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292389685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.292389685
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3563545419
Short name T557
Test name
Test status
Simulation time 203400086 ps
CPU time 1.69 seconds
Started Mar 03 12:31:36 PM PST 24
Finished Mar 03 12:31:40 PM PST 24
Peak memory 208664 kb
Host smart-1fd22833-5437-4447-926e-89b6bd192e95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563545419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3563545419
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1475297343
Short name T82
Test name
Test status
Simulation time 451445268 ps
CPU time 1.9 seconds
Started Mar 03 12:31:45 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 200648 kb
Host smart-5a610c24-cc92-4592-94ed-4a89b35931bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475297343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1475297343
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2474383365
Short name T555
Test name
Test status
Simulation time 198654820 ps
CPU time 1.25 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 207076 kb
Host smart-7d0ae296-5dca-4c93-a48d-339a418e40f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474383365 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2474383365
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2223213434
Short name T123
Test name
Test status
Simulation time 70320385 ps
CPU time 0.84 seconds
Started Mar 03 12:31:30 PM PST 24
Finished Mar 03 12:31:31 PM PST 24
Peak memory 199672 kb
Host smart-a9228fbe-eb9d-4ae7-8c71-4ca0509f1bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223213434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2223213434
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.994796077
Short name T586
Test name
Test status
Simulation time 77074969 ps
CPU time 0.97 seconds
Started Mar 03 12:31:41 PM PST 24
Finished Mar 03 12:31:43 PM PST 24
Peak memory 200484 kb
Host smart-53eb705e-b44e-4db7-a1dc-467b0d0b2964
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994796077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.994796077
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.531188238
Short name T609
Test name
Test status
Simulation time 646956005 ps
CPU time 4.32 seconds
Started Mar 03 12:31:54 PM PST 24
Finished Mar 03 12:31:58 PM PST 24
Peak memory 216940 kb
Host smart-7124f9d9-63c5-45a5-a4af-2305e3e3e5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531188238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.531188238
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1356266158
Short name T585
Test name
Test status
Simulation time 415041290 ps
CPU time 1.9 seconds
Started Mar 03 12:31:50 PM PST 24
Finished Mar 03 12:31:52 PM PST 24
Peak memory 200688 kb
Host smart-6bb97f8f-735c-42b5-929b-6d9ef68f3371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356266158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1356266158
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.174960729
Short name T556
Test name
Test status
Simulation time 68772226 ps
CPU time 0.99 seconds
Started Mar 03 12:31:56 PM PST 24
Finished Mar 03 12:31:57 PM PST 24
Peak memory 200532 kb
Host smart-b11273a7-cc39-47e7-83d3-40084b214aa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174960729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.174960729
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3882964877
Short name T119
Test name
Test status
Simulation time 77618144 ps
CPU time 0.92 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:34 PM PST 24
Peak memory 198792 kb
Host smart-a2fc38fc-4cda-47a1-bfff-82a647f26232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882964877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3882964877
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3291307517
Short name T90
Test name
Test status
Simulation time 103856028 ps
CPU time 1.28 seconds
Started Mar 03 12:31:57 PM PST 24
Finished Mar 03 12:31:58 PM PST 24
Peak memory 200364 kb
Host smart-bef64c24-c77f-44ba-b57d-66a88030d5d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291307517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3291307517
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2375751853
Short name T614
Test name
Test status
Simulation time 1032504016 ps
CPU time 3.16 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:36 PM PST 24
Peak memory 200156 kb
Host smart-7f542fe7-1eda-43ec-be70-f6c6e6baef93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375751853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2375751853
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.736320822
Short name T613
Test name
Test status
Simulation time 156326816 ps
CPU time 1.33 seconds
Started Mar 03 12:32:00 PM PST 24
Finished Mar 03 12:32:01 PM PST 24
Peak memory 200556 kb
Host smart-fb9f8732-646e-4486-a778-7ee12d569a82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736320822 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.736320822
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3672909223
Short name T548
Test name
Test status
Simulation time 70446502 ps
CPU time 0.8 seconds
Started Mar 03 12:31:57 PM PST 24
Finished Mar 03 12:31:59 PM PST 24
Peak memory 200524 kb
Host smart-137d2a34-21cf-4129-ae62-b8db499353c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672909223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3672909223
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3375403947
Short name T576
Test name
Test status
Simulation time 137411802 ps
CPU time 1.24 seconds
Started Mar 03 12:31:36 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 200088 kb
Host smart-be9ee0ca-d7d8-4a32-b596-37f6a94b6378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375403947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3375403947
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.325337465
Short name T563
Test name
Test status
Simulation time 439324801 ps
CPU time 3.01 seconds
Started Mar 03 12:31:36 PM PST 24
Finished Mar 03 12:31:40 PM PST 24
Peak memory 208644 kb
Host smart-44350bcc-558f-4888-ba67-2ad44c0e231d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325337465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.325337465
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3851458978
Short name T616
Test name
Test status
Simulation time 422247940 ps
CPU time 1.71 seconds
Started Mar 03 12:31:47 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 200736 kb
Host smart-4a2dec8f-7375-4c53-b3a5-554ea160d662
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851458978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3851458978
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1282821718
Short name T562
Test name
Test status
Simulation time 166287956 ps
CPU time 1.44 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:32:58 PM PST 24
Peak memory 199848 kb
Host smart-6e9f4fba-818b-45e8-a0c7-32b027370606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282821718 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1282821718
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3467744415
Short name T121
Test name
Test status
Simulation time 60077894 ps
CPU time 0.85 seconds
Started Mar 03 12:31:49 PM PST 24
Finished Mar 03 12:31:51 PM PST 24
Peak memory 199672 kb
Host smart-66d5cbd9-2a5e-410b-be3f-e0c4cf4032d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467744415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3467744415
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1273886922
Short name T594
Test name
Test status
Simulation time 137694839 ps
CPU time 1.33 seconds
Started Mar 03 12:31:58 PM PST 24
Finished Mar 03 12:31:59 PM PST 24
Peak memory 200728 kb
Host smart-39d5f0c1-5238-4916-808b-5d406aab6a08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273886922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1273886922
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1237011007
Short name T73
Test name
Test status
Simulation time 163487899 ps
CPU time 1.39 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 208696 kb
Host smart-4ae53635-db3a-4d5f-8736-9a07446c6258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237011007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1237011007
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1719924619
Short name T593
Test name
Test status
Simulation time 493614540 ps
CPU time 1.88 seconds
Started Mar 03 12:31:30 PM PST 24
Finished Mar 03 12:31:32 PM PST 24
Peak memory 199880 kb
Host smart-af2a5ef9-a414-4cba-b739-50c5a8005ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719924619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1719924619
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1290368718
Short name T102
Test name
Test status
Simulation time 104986043 ps
CPU time 0.95 seconds
Started Mar 03 12:31:53 PM PST 24
Finished Mar 03 12:31:55 PM PST 24
Peak memory 200508 kb
Host smart-725d086a-b98e-405d-9ac9-f719fa5c3309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290368718 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1290368718
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1309907860
Short name T544
Test name
Test status
Simulation time 73029332 ps
CPU time 0.76 seconds
Started Mar 03 12:31:46 PM PST 24
Finished Mar 03 12:31:47 PM PST 24
Peak memory 200484 kb
Host smart-8f5b2b03-0442-426a-bf1c-a82c598cecb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309907860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1309907860
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1336679789
Short name T570
Test name
Test status
Simulation time 128733455 ps
CPU time 1.22 seconds
Started Mar 03 12:31:36 PM PST 24
Finished Mar 03 12:31:38 PM PST 24
Peak memory 200432 kb
Host smart-0d0700ea-9cf3-4b60-8a9b-ce9e4af7fd6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336679789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1336679789
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3933093945
Short name T619
Test name
Test status
Simulation time 125111518 ps
CPU time 1.89 seconds
Started Mar 03 12:33:01 PM PST 24
Finished Mar 03 12:33:03 PM PST 24
Peak memory 208924 kb
Host smart-d5f697b9-41da-4752-8806-3e73489b8943
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933093945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3933093945
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3766426709
Short name T611
Test name
Test status
Simulation time 886665492 ps
CPU time 2.95 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:36 PM PST 24
Peak memory 200632 kb
Host smart-af07ea3e-52e3-4dce-9dfc-2235795788d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766426709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3766426709
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.244611435
Short name T77
Test name
Test status
Simulation time 204623412 ps
CPU time 1.52 seconds
Started Mar 03 12:31:37 PM PST 24
Finished Mar 03 12:31:39 PM PST 24
Peak memory 201056 kb
Host smart-7934aa97-45de-4729-a1c4-b05db0283fc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244611435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.244611435
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3717562717
Short name T612
Test name
Test status
Simulation time 2288872488 ps
CPU time 10.65 seconds
Started Mar 03 12:32:01 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 200700 kb
Host smart-17b12be4-8dc4-4858-ae68-fc1d3adb21b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717562717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
717562717
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4263044137
Short name T545
Test name
Test status
Simulation time 96403965 ps
CPU time 0.86 seconds
Started Mar 03 12:31:39 PM PST 24
Finished Mar 03 12:31:41 PM PST 24
Peak memory 198776 kb
Host smart-c70db5c3-9d54-4243-920f-ad02cb166e25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263044137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4
263044137
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2396737650
Short name T601
Test name
Test status
Simulation time 132316007 ps
CPU time 1.38 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:34 PM PST 24
Peak memory 208700 kb
Host smart-8de52834-c630-41d1-a2ef-bc48f716a4dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396737650 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2396737650
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3528280540
Short name T117
Test name
Test status
Simulation time 67442375 ps
CPU time 0.9 seconds
Started Mar 03 12:31:51 PM PST 24
Finished Mar 03 12:31:53 PM PST 24
Peak memory 199580 kb
Host smart-d664d08a-130b-4c70-9849-14723dcff335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528280540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3528280540
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1858039536
Short name T587
Test name
Test status
Simulation time 115486269 ps
CPU time 1.09 seconds
Started Mar 03 12:31:47 PM PST 24
Finished Mar 03 12:31:49 PM PST 24
Peak memory 199672 kb
Host smart-c8910ffa-1351-4595-b64e-d10e7a0db0aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858039536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1858039536
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2460784861
Short name T572
Test name
Test status
Simulation time 349108331 ps
CPU time 2.47 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:32:05 PM PST 24
Peak memory 208824 kb
Host smart-a574a9bb-5d6b-4bee-8988-6c9cbc8d5dad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460784861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2460784861
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1640424951
Short name T565
Test name
Test status
Simulation time 365912439 ps
CPU time 2.43 seconds
Started Mar 03 12:31:34 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 216200 kb
Host smart-5eec0e65-c2f5-421e-bf16-44ea160def32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640424951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
640424951
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2650469708
Short name T604
Test name
Test status
Simulation time 1989758488 ps
CPU time 9.02 seconds
Started Mar 03 12:31:38 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 199840 kb
Host smart-d7f35a2d-cad0-40ec-b76b-696fc2cafce7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650469708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
650469708
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3522829586
Short name T552
Test name
Test status
Simulation time 126566694 ps
CPU time 0.94 seconds
Started Mar 03 12:31:31 PM PST 24
Finished Mar 03 12:31:33 PM PST 24
Peak memory 199656 kb
Host smart-3b1fe127-252c-418c-8427-a13e55a15879
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522829586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
522829586
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3814989854
Short name T589
Test name
Test status
Simulation time 117362979 ps
CPU time 1.01 seconds
Started Mar 03 12:31:39 PM PST 24
Finished Mar 03 12:31:41 PM PST 24
Peak memory 198736 kb
Host smart-de58c2d3-af6d-406b-8f9c-cbb522f46564
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814989854 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3814989854
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.368168803
Short name T591
Test name
Test status
Simulation time 69276321 ps
CPU time 0.86 seconds
Started Mar 03 12:31:39 PM PST 24
Finished Mar 03 12:31:41 PM PST 24
Peak memory 199124 kb
Host smart-493d0667-fa0d-4ccf-b9e4-0637f83e5089
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368168803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.368168803
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1210393147
Short name T558
Test name
Test status
Simulation time 81648924 ps
CPU time 1.01 seconds
Started Mar 03 12:31:35 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 199604 kb
Host smart-b723f4a9-64b6-4cc7-aadb-1f15a5b00fe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210393147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1210393147
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2555255310
Short name T74
Test name
Test status
Simulation time 176984560 ps
CPU time 2.57 seconds
Started Mar 03 12:31:29 PM PST 24
Finished Mar 03 12:31:32 PM PST 24
Peak memory 208012 kb
Host smart-64925ed9-8e61-4af3-b3e1-7a80cbc64fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555255310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2555255310
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3390889853
Short name T600
Test name
Test status
Simulation time 433738856 ps
CPU time 1.8 seconds
Started Mar 03 12:31:42 PM PST 24
Finished Mar 03 12:31:45 PM PST 24
Peak memory 200744 kb
Host smart-b502e9ab-5c19-426f-8576-2d1b4d1a03ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390889853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3390889853
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2853330339
Short name T579
Test name
Test status
Simulation time 148617139 ps
CPU time 1.93 seconds
Started Mar 03 12:31:42 PM PST 24
Finished Mar 03 12:31:44 PM PST 24
Peak memory 200616 kb
Host smart-52a052e1-98c5-4a77-bc93-e0cd1b3d7796
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853330339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
853330339
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.909117493
Short name T602
Test name
Test status
Simulation time 481943099 ps
CPU time 5.65 seconds
Started Mar 03 12:31:34 PM PST 24
Finished Mar 03 12:31:39 PM PST 24
Peak memory 200244 kb
Host smart-3e75c72c-a285-4bde-95d2-f872c2fd9060
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909117493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.909117493
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2043258744
Short name T590
Test name
Test status
Simulation time 102537370 ps
CPU time 0.9 seconds
Started Mar 03 12:31:51 PM PST 24
Finished Mar 03 12:31:52 PM PST 24
Peak memory 199656 kb
Host smart-a98eb96a-6c45-4b17-9ffc-2ae087c48066
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043258744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
043258744
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.510864929
Short name T80
Test name
Test status
Simulation time 117744941 ps
CPU time 1.01 seconds
Started Mar 03 12:31:30 PM PST 24
Finished Mar 03 12:31:31 PM PST 24
Peak memory 199680 kb
Host smart-d2c10e82-68cc-44bd-837e-c120567e00c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510864929 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.510864929
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3238466000
Short name T51
Test name
Test status
Simulation time 75658791 ps
CPU time 0.81 seconds
Started Mar 03 12:31:46 PM PST 24
Finished Mar 03 12:31:47 PM PST 24
Peak memory 199604 kb
Host smart-8f4927ac-170d-4fac-a916-79b668e01168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238466000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3238466000
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.766094653
Short name T118
Test name
Test status
Simulation time 252073874 ps
CPU time 1.64 seconds
Started Mar 03 12:32:14 PM PST 24
Finished Mar 03 12:32:16 PM PST 24
Peak memory 200552 kb
Host smart-fbb00b64-ebab-4152-8090-881aae75fc09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766094653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.766094653
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3067578975
Short name T615
Test name
Test status
Simulation time 468959430 ps
CPU time 3.5 seconds
Started Mar 03 12:31:36 PM PST 24
Finished Mar 03 12:31:40 PM PST 24
Peak memory 208032 kb
Host smart-c81a3b99-1534-487e-88a0-b1e48b273754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067578975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3067578975
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3323718475
Short name T89
Test name
Test status
Simulation time 880410335 ps
CPU time 3.24 seconds
Started Mar 03 12:31:39 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 200084 kb
Host smart-28ea729b-0786-4b37-8a12-d23149c51995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323718475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3323718475
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2696388408
Short name T574
Test name
Test status
Simulation time 180957231 ps
CPU time 1.35 seconds
Started Mar 03 12:31:40 PM PST 24
Finished Mar 03 12:31:42 PM PST 24
Peak memory 209592 kb
Host smart-90f722bd-dac7-4373-9817-408cd9b7cfc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696388408 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2696388408
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3327469213
Short name T546
Test name
Test status
Simulation time 84611075 ps
CPU time 0.83 seconds
Started Mar 03 12:31:41 PM PST 24
Finished Mar 03 12:31:42 PM PST 24
Peak memory 200484 kb
Host smart-5649ba67-1758-4303-965e-84e31fdf31aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327469213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3327469213
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.271458668
Short name T116
Test name
Test status
Simulation time 148153385 ps
CPU time 1.23 seconds
Started Mar 03 12:32:01 PM PST 24
Finished Mar 03 12:32:02 PM PST 24
Peak memory 200552 kb
Host smart-898055fc-70d2-46e7-81d1-3bd39730cc5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271458668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.271458668
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3878121523
Short name T560
Test name
Test status
Simulation time 206080824 ps
CPU time 1.62 seconds
Started Mar 03 12:31:34 PM PST 24
Finished Mar 03 12:31:36 PM PST 24
Peak memory 208532 kb
Host smart-5dd6d93b-15bd-477a-9e09-05daddedf742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878121523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3878121523
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3303581735
Short name T554
Test name
Test status
Simulation time 492250717 ps
CPU time 1.94 seconds
Started Mar 03 12:31:34 PM PST 24
Finished Mar 03 12:31:36 PM PST 24
Peak memory 200396 kb
Host smart-9ee2e2ad-6783-4b0b-91a1-41361ebeea25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303581735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3303581735
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3514992720
Short name T564
Test name
Test status
Simulation time 127193996 ps
CPU time 1.31 seconds
Started Mar 03 12:31:53 PM PST 24
Finished Mar 03 12:31:54 PM PST 24
Peak memory 208752 kb
Host smart-a1f1bdee-d7f7-439b-afc3-8cd1e78b9760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514992720 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3514992720
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1773415140
Short name T580
Test name
Test status
Simulation time 62112015 ps
CPU time 0.84 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:34 PM PST 24
Peak memory 199624 kb
Host smart-3105c1b3-7906-43a5-a7ef-97805a4d9d38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773415140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1773415140
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1793807134
Short name T578
Test name
Test status
Simulation time 131611493 ps
CPU time 1.13 seconds
Started Mar 03 12:31:56 PM PST 24
Finished Mar 03 12:31:57 PM PST 24
Peak memory 200484 kb
Host smart-e0536ea1-d65f-438d-8e40-a24f6195cc32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793807134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1793807134
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3349757237
Short name T78
Test name
Test status
Simulation time 189364786 ps
CPU time 2.69 seconds
Started Mar 03 12:31:39 PM PST 24
Finished Mar 03 12:31:43 PM PST 24
Peak memory 207504 kb
Host smart-c2da28a1-784e-499e-a9e9-94ea76e20621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349757237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3349757237
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1862102978
Short name T75
Test name
Test status
Simulation time 466612443 ps
CPU time 1.82 seconds
Started Mar 03 12:31:34 PM PST 24
Finished Mar 03 12:31:36 PM PST 24
Peak memory 200384 kb
Host smart-d02b94ef-f874-4fcd-9ac2-0662ab1fb420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862102978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1862102978
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3547471086
Short name T559
Test name
Test status
Simulation time 139485355 ps
CPU time 1.16 seconds
Started Mar 03 12:31:43 PM PST 24
Finished Mar 03 12:31:45 PM PST 24
Peak memory 210800 kb
Host smart-549fd570-fec1-427d-86b0-96113122eda6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547471086 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3547471086
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2434606318
Short name T597
Test name
Test status
Simulation time 65075235 ps
CPU time 0.91 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 199824 kb
Host smart-84cb1641-af74-48b3-a928-916e0764001b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434606318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2434606318
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2028882592
Short name T50
Test name
Test status
Simulation time 175189898 ps
CPU time 1.36 seconds
Started Mar 03 12:31:34 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 199860 kb
Host smart-affd8685-97b8-46f8-a987-b947446ca4cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028882592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2028882592
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.604077996
Short name T91
Test name
Test status
Simulation time 176526817 ps
CPU time 2.62 seconds
Started Mar 03 12:31:53 PM PST 24
Finished Mar 03 12:31:56 PM PST 24
Peak memory 217024 kb
Host smart-7c1b402b-ef6c-4b3e-8462-dbffc3559d68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604077996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.604077996
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1049274121
Short name T84
Test name
Test status
Simulation time 881784951 ps
CPU time 3.29 seconds
Started Mar 03 12:32:00 PM PST 24
Finished Mar 03 12:32:03 PM PST 24
Peak memory 200704 kb
Host smart-b5c2ce8c-5d42-45ad-b83b-a17d667e7cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049274121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1049274121
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2061492277
Short name T550
Test name
Test status
Simulation time 111859085 ps
CPU time 0.97 seconds
Started Mar 03 12:31:30 PM PST 24
Finished Mar 03 12:31:31 PM PST 24
Peak memory 199876 kb
Host smart-f0bc5364-4e27-43a4-9ae3-bc9109544795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061492277 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2061492277
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4108100283
Short name T582
Test name
Test status
Simulation time 78774462 ps
CPU time 0.8 seconds
Started Mar 03 12:31:37 PM PST 24
Finished Mar 03 12:31:39 PM PST 24
Peak memory 200408 kb
Host smart-0eb787d7-81d5-40fc-ac83-4b952f19cd05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108100283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4108100283
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3747230322
Short name T561
Test name
Test status
Simulation time 179830460 ps
CPU time 1.26 seconds
Started Mar 03 12:32:01 PM PST 24
Finished Mar 03 12:32:03 PM PST 24
Peak memory 199800 kb
Host smart-d34ad98e-ff28-4899-8b5b-83da6c0e1b0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747230322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3747230322
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3822183513
Short name T569
Test name
Test status
Simulation time 287083671 ps
CPU time 2.26 seconds
Started Mar 03 12:31:46 PM PST 24
Finished Mar 03 12:31:49 PM PST 24
Peak memory 208852 kb
Host smart-618c1335-c501-4164-8aa9-f53710580013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822183513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3822183513
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.592398067
Short name T128
Test name
Test status
Simulation time 403996381 ps
CPU time 1.79 seconds
Started Mar 03 12:31:45 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 199876 kb
Host smart-c32ecc1d-be86-4697-afc4-68c5dff94ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592398067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
592398067
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2047586505
Short name T101
Test name
Test status
Simulation time 210197389 ps
CPU time 1.39 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:34 PM PST 24
Peak memory 207876 kb
Host smart-6062c360-d677-422b-a913-cf3146ab5853
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047586505 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2047586505
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1048302680
Short name T610
Test name
Test status
Simulation time 80077103 ps
CPU time 0.86 seconds
Started Mar 03 12:31:43 PM PST 24
Finished Mar 03 12:31:45 PM PST 24
Peak memory 199672 kb
Host smart-184d9462-bf3d-48e0-915a-3ff36de547e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048302680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1048302680
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.44996972
Short name T584
Test name
Test status
Simulation time 86444667 ps
CPU time 1 seconds
Started Mar 03 12:31:39 PM PST 24
Finished Mar 03 12:31:41 PM PST 24
Peak memory 198740 kb
Host smart-68bae132-7994-49ed-a7ae-b22f0e37fb5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44996972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same
_csr_outstanding.44996972
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2007388369
Short name T567
Test name
Test status
Simulation time 188617796 ps
CPU time 1.63 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 210036 kb
Host smart-fd358035-07e3-4ed7-868d-524e97bf2424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007388369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2007388369
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4264151266
Short name T87
Test name
Test status
Simulation time 463117590 ps
CPU time 2.06 seconds
Started Mar 03 12:32:01 PM PST 24
Finished Mar 03 12:32:03 PM PST 24
Peak memory 199960 kb
Host smart-6b866fd1-a562-4859-950a-92574c100fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264151266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.4264151266
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.867740169
Short name T473
Test name
Test status
Simulation time 60954790 ps
CPU time 0.73 seconds
Started Mar 03 12:45:38 PM PST 24
Finished Mar 03 12:45:39 PM PST 24
Peak memory 199864 kb
Host smart-7b80b3b6-6cf6-4390-9f14-33dc8e894f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867740169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.867740169
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2442053774
Short name T543
Test name
Test status
Simulation time 1220958141 ps
CPU time 6.12 seconds
Started Mar 03 12:45:37 PM PST 24
Finished Mar 03 12:45:43 PM PST 24
Peak memory 216876 kb
Host smart-eb4b2e81-cd6f-488e-94f6-eaa178af01da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442053774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2442053774
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3632597323
Short name T480
Test name
Test status
Simulation time 244615405 ps
CPU time 1.18 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 217044 kb
Host smart-5c80d4a6-b762-49b2-a14d-8c51171c7c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632597323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3632597323
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.846892559
Short name T143
Test name
Test status
Simulation time 102745871 ps
CPU time 0.78 seconds
Started Mar 03 12:45:38 PM PST 24
Finished Mar 03 12:45:40 PM PST 24
Peak memory 199724 kb
Host smart-870ab456-e6a8-4976-98ec-bf78888c5366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846892559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.846892559
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2008363654
Short name T296
Test name
Test status
Simulation time 1411079874 ps
CPU time 5.71 seconds
Started Mar 03 12:45:39 PM PST 24
Finished Mar 03 12:45:46 PM PST 24
Peak memory 199920 kb
Host smart-6d39015a-77ca-428b-880c-d72d93edb21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008363654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2008363654
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3073238999
Short name T516
Test name
Test status
Simulation time 148650867 ps
CPU time 1.19 seconds
Started Mar 03 12:45:32 PM PST 24
Finished Mar 03 12:45:33 PM PST 24
Peak memory 199944 kb
Host smart-d1c6b5a6-7dc8-4293-bd44-7e8c3b9d07a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073238999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3073238999
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2401275798
Short name T362
Test name
Test status
Simulation time 195530938 ps
CPU time 1.42 seconds
Started Mar 03 12:45:43 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 200000 kb
Host smart-d55c5a1b-5b73-4ea2-9097-9f2a2f067e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401275798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2401275798
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1104057406
Short name T272
Test name
Test status
Simulation time 3531729305 ps
CPU time 17.3 seconds
Started Mar 03 12:45:33 PM PST 24
Finished Mar 03 12:45:50 PM PST 24
Peak memory 200216 kb
Host smart-a6508257-b16c-4e05-9c6d-9b405714484f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104057406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1104057406
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.360340635
Short name T137
Test name
Test status
Simulation time 539033483 ps
CPU time 2.83 seconds
Started Mar 03 12:45:40 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 199880 kb
Host smart-2ab80ed7-0abf-434a-8e82-775dc998785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360340635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.360340635
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3985966743
Short name T288
Test name
Test status
Simulation time 111366497 ps
CPU time 0.98 seconds
Started Mar 03 12:45:30 PM PST 24
Finished Mar 03 12:45:31 PM PST 24
Peak memory 200020 kb
Host smart-7ee2e0af-d15d-4ee5-b2df-3a08bb8dfb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985966743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3985966743
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1526206122
Short name T369
Test name
Test status
Simulation time 64774728 ps
CPU time 0.71 seconds
Started Mar 03 12:45:34 PM PST 24
Finished Mar 03 12:45:35 PM PST 24
Peak memory 199844 kb
Host smart-cf6b4f51-e667-4682-a50a-0bc343baaec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526206122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1526206122
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.251736225
Short name T375
Test name
Test status
Simulation time 1895426778 ps
CPU time 7.29 seconds
Started Mar 03 12:45:41 PM PST 24
Finished Mar 03 12:45:50 PM PST 24
Peak memory 217608 kb
Host smart-d581b70a-bf3f-4827-af27-781847250094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251736225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.251736225
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1235924511
Short name T498
Test name
Test status
Simulation time 244484924 ps
CPU time 1.1 seconds
Started Mar 03 12:45:31 PM PST 24
Finished Mar 03 12:45:33 PM PST 24
Peak memory 216948 kb
Host smart-b94272c2-034e-4b3c-8de5-99745b4758b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235924511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1235924511
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.109323398
Short name T476
Test name
Test status
Simulation time 154817942 ps
CPU time 0.89 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:53 PM PST 24
Peak memory 199732 kb
Host smart-d6ab8385-e9c6-4a03-9000-82c892ee1a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109323398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.109323398
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1347602524
Short name T390
Test name
Test status
Simulation time 1786627320 ps
CPU time 6.81 seconds
Started Mar 03 12:45:37 PM PST 24
Finished Mar 03 12:45:44 PM PST 24
Peak memory 200164 kb
Host smart-a5723add-99a5-49f5-96cf-1dcfe27048c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347602524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1347602524
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2130056772
Short name T59
Test name
Test status
Simulation time 16510672212 ps
CPU time 28.05 seconds
Started Mar 03 12:45:29 PM PST 24
Finished Mar 03 12:45:57 PM PST 24
Peak memory 216712 kb
Host smart-7c981658-2a58-4f07-8922-7732688fc7ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130056772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2130056772
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.423946173
Short name T446
Test name
Test status
Simulation time 140406087 ps
CPU time 1.1 seconds
Started Mar 03 12:45:46 PM PST 24
Finished Mar 03 12:45:48 PM PST 24
Peak memory 199912 kb
Host smart-376d07f4-5cc4-48a6-a78a-8e58c2d28939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423946173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.423946173
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1370473755
Short name T222
Test name
Test status
Simulation time 191242591 ps
CPU time 1.35 seconds
Started Mar 03 12:45:42 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 200036 kb
Host smart-21e2b967-516f-4c4a-8afa-287572ac4b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370473755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1370473755
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.75856830
Short name T98
Test name
Test status
Simulation time 157277276 ps
CPU time 1.37 seconds
Started Mar 03 12:45:31 PM PST 24
Finished Mar 03 12:45:32 PM PST 24
Peak memory 199680 kb
Host smart-fc4dd7d9-42dd-416e-a81a-a5c4c4cde4e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75856830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.75856830
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3445254216
Short name T160
Test name
Test status
Simulation time 378868342 ps
CPU time 2.15 seconds
Started Mar 03 12:45:37 PM PST 24
Finished Mar 03 12:45:39 PM PST 24
Peak memory 199836 kb
Host smart-4fff3008-826f-4afc-a27d-776f8cd88613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445254216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3445254216
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1157518905
Short name T321
Test name
Test status
Simulation time 71200532 ps
CPU time 0.84 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:46 PM PST 24
Peak memory 199916 kb
Host smart-446f3b07-2477-4ac2-8419-54c0c323c59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157518905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1157518905
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2521513073
Short name T512
Test name
Test status
Simulation time 57066060 ps
CPU time 0.73 seconds
Started Mar 03 12:45:49 PM PST 24
Finished Mar 03 12:45:50 PM PST 24
Peak memory 199844 kb
Host smart-3c9179ed-5106-4362-8e0d-c448bb03112d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521513073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2521513073
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.732667516
Short name T366
Test name
Test status
Simulation time 1221131491 ps
CPU time 5.79 seconds
Started Mar 03 12:45:42 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 217512 kb
Host smart-0bd99d30-b373-4b27-923c-7922dd495868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732667516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.732667516
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2057010698
Short name T41
Test name
Test status
Simulation time 244915697 ps
CPU time 1.08 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:58 PM PST 24
Peak memory 217088 kb
Host smart-061458bb-d8a1-4bfb-acd5-4217eb80ebad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057010698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2057010698
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1100033701
Short name T481
Test name
Test status
Simulation time 129065050 ps
CPU time 0.83 seconds
Started Mar 03 12:45:48 PM PST 24
Finished Mar 03 12:45:50 PM PST 24
Peak memory 199720 kb
Host smart-821d9141-a605-453a-827f-7e8a3e436029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100033701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1100033701
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.926077218
Short name T110
Test name
Test status
Simulation time 836322111 ps
CPU time 4.01 seconds
Started Mar 03 12:45:47 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 200068 kb
Host smart-1cf28611-1504-40e0-aa87-3afbd836dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926077218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.926077218
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.343560293
Short name T221
Test name
Test status
Simulation time 154083413 ps
CPU time 1.2 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:55 PM PST 24
Peak memory 200032 kb
Host smart-b0f95042-b64f-4401-a49c-2ea4f8593557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343560293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.343560293
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.796215951
Short name T468
Test name
Test status
Simulation time 112605642 ps
CPU time 1.27 seconds
Started Mar 03 12:45:44 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 199972 kb
Host smart-ce4586e0-888c-4f2f-85fc-0a14156f89d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796215951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.796215951
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.112314083
Short name T539
Test name
Test status
Simulation time 7235745529 ps
CPU time 27.89 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 200232 kb
Host smart-3229fd57-0c87-4e55-8528-62e9945894bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112314083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.112314083
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2772247037
Short name T176
Test name
Test status
Simulation time 353322936 ps
CPU time 1.99 seconds
Started Mar 03 12:45:48 PM PST 24
Finished Mar 03 12:45:51 PM PST 24
Peak memory 199960 kb
Host smart-09dcf7af-6f5b-4e32-8d11-0eb7288f416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772247037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2772247037
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3960884831
Short name T151
Test name
Test status
Simulation time 67695504 ps
CPU time 0.81 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:47 PM PST 24
Peak memory 199784 kb
Host smart-21b07f22-fe68-4714-9bbb-332ac8b130c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960884831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3960884831
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.304323559
Short name T36
Test name
Test status
Simulation time 1217083277 ps
CPU time 5.73 seconds
Started Mar 03 12:45:52 PM PST 24
Finished Mar 03 12:45:58 PM PST 24
Peak memory 217896 kb
Host smart-027ac495-4872-4107-9641-fd8b9ca8c02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304323559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.304323559
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3103908741
Short name T535
Test name
Test status
Simulation time 244440765 ps
CPU time 1.25 seconds
Started Mar 03 12:45:46 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 216964 kb
Host smart-06b6c9d4-01fd-4d99-ba80-e5d568e45fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103908741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3103908741
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2898203106
Short name T166
Test name
Test status
Simulation time 244575799 ps
CPU time 0.93 seconds
Started Mar 03 12:45:46 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 199688 kb
Host smart-5c30fb3b-2d72-4571-abe3-a30ead7f4a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898203106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2898203106
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3058020844
Short name T115
Test name
Test status
Simulation time 1262709118 ps
CPU time 5.27 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 200180 kb
Host smart-f22903f4-dd5c-4c62-926c-c01cf1b05d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058020844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3058020844
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.320811248
Short name T364
Test name
Test status
Simulation time 179199383 ps
CPU time 1.25 seconds
Started Mar 03 12:46:02 PM PST 24
Finished Mar 03 12:46:03 PM PST 24
Peak memory 200032 kb
Host smart-0249198c-8c3b-4919-9649-738acdfa66f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320811248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.320811248
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2475684085
Short name T402
Test name
Test status
Simulation time 201367828 ps
CPU time 1.46 seconds
Started Mar 03 12:45:46 PM PST 24
Finished Mar 03 12:45:50 PM PST 24
Peak memory 200040 kb
Host smart-6fdc2301-b085-49f9-b91d-67a1be7f0641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475684085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2475684085
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.221706845
Short name T240
Test name
Test status
Simulation time 399035884 ps
CPU time 2.37 seconds
Started Mar 03 12:45:50 PM PST 24
Finished Mar 03 12:45:53 PM PST 24
Peak memory 199876 kb
Host smart-f1acfd12-a848-41dd-9efa-16b0a0a55f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221706845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.221706845
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3323144430
Short name T48
Test name
Test status
Simulation time 148202690 ps
CPU time 1.93 seconds
Started Mar 03 12:45:50 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 199948 kb
Host smart-6798ec24-b72a-478b-a1f9-eba38a7fe18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323144430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3323144430
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2484420374
Short name T382
Test name
Test status
Simulation time 171397432 ps
CPU time 1.26 seconds
Started Mar 03 12:45:50 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 199892 kb
Host smart-2de82dee-ad67-4221-9a02-9316abd75e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484420374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2484420374
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.916942449
Short name T522
Test name
Test status
Simulation time 83204224 ps
CPU time 0.79 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 199864 kb
Host smart-4dbb523e-14f8-42a5-9da7-56f9a39e383d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916942449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.916942449
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3659012245
Short name T504
Test name
Test status
Simulation time 244333457 ps
CPU time 1.2 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 217040 kb
Host smart-ed542e88-2015-485f-b731-758d382b5e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659012245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3659012245
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2286265888
Short name T270
Test name
Test status
Simulation time 92538395 ps
CPU time 0.74 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:45:58 PM PST 24
Peak memory 199824 kb
Host smart-ac51433c-18b9-4e88-8fe5-e40978151bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286265888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2286265888
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.830735849
Short name T104
Test name
Test status
Simulation time 947865712 ps
CPU time 4.88 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:03 PM PST 24
Peak memory 200008 kb
Host smart-9b679230-619b-40a0-98c1-89d54e4fbf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830735849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.830735849
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1093560714
Short name T523
Test name
Test status
Simulation time 149238404 ps
CPU time 1.11 seconds
Started Mar 03 12:45:46 PM PST 24
Finished Mar 03 12:45:48 PM PST 24
Peak memory 199836 kb
Host smart-df631c38-39fa-4552-a419-31a8cdcf13a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093560714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1093560714
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2755900227
Short name T344
Test name
Test status
Simulation time 197861246 ps
CPU time 1.35 seconds
Started Mar 03 12:46:00 PM PST 24
Finished Mar 03 12:46:02 PM PST 24
Peak memory 200108 kb
Host smart-05b9c450-887a-4850-bb70-d22f9ce35c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755900227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2755900227
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2380616449
Short name T360
Test name
Test status
Simulation time 6666413092 ps
CPU time 32.86 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 200252 kb
Host smart-975ba1e2-d9c1-4252-abe2-0635f40d822a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380616449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2380616449
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1283559592
Short name T416
Test name
Test status
Simulation time 150204944 ps
CPU time 1.79 seconds
Started Mar 03 12:45:50 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 199836 kb
Host smart-27ecccc5-d9f2-4229-878e-b1c43262e951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283559592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1283559592
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.323068545
Short name T328
Test name
Test status
Simulation time 243818241 ps
CPU time 1.37 seconds
Started Mar 03 12:45:49 PM PST 24
Finished Mar 03 12:45:51 PM PST 24
Peak memory 200000 kb
Host smart-b66f8721-aa28-46fd-9de1-28289699817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323068545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.323068545
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3727194138
Short name T385
Test name
Test status
Simulation time 98702804 ps
CPU time 0.82 seconds
Started Mar 03 12:46:06 PM PST 24
Finished Mar 03 12:46:07 PM PST 24
Peak memory 199956 kb
Host smart-b34f561b-9b74-45e9-92a5-8bbc36f12872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727194138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3727194138
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2554033251
Short name T37
Test name
Test status
Simulation time 1234412890 ps
CPU time 5.89 seconds
Started Mar 03 12:45:59 PM PST 24
Finished Mar 03 12:46:05 PM PST 24
Peak memory 229312 kb
Host smart-7bdf0afd-a815-4c52-8c2e-5fc2221eca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554033251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2554033251
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1968187991
Short name T525
Test name
Test status
Simulation time 244445197 ps
CPU time 1.29 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 216908 kb
Host smart-46e95c7c-a483-4cb0-8e3d-26041fef01e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968187991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1968187991
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1975068380
Short name T229
Test name
Test status
Simulation time 145373667 ps
CPU time 0.86 seconds
Started Mar 03 12:45:54 PM PST 24
Finished Mar 03 12:45:55 PM PST 24
Peak memory 200080 kb
Host smart-2db62c10-79d0-4a04-88cb-60be384a2576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975068380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1975068380
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.894640424
Short name T365
Test name
Test status
Simulation time 793826081 ps
CPU time 4.34 seconds
Started Mar 03 12:45:54 PM PST 24
Finished Mar 03 12:45:59 PM PST 24
Peak memory 200108 kb
Host smart-74e4b4fb-c20a-4e5a-9f33-bde5a5e1b9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894640424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.894640424
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2684659103
Short name T529
Test name
Test status
Simulation time 180527987 ps
CPU time 1.2 seconds
Started Mar 03 12:45:52 PM PST 24
Finished Mar 03 12:45:53 PM PST 24
Peak memory 200020 kb
Host smart-3fad429b-19d0-4620-8802-69055b0620ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684659103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2684659103
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2045697892
Short name T355
Test name
Test status
Simulation time 199366682 ps
CPU time 1.46 seconds
Started Mar 03 12:45:50 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 200000 kb
Host smart-0661ee46-eaf5-4cb3-8f1b-e1c18e7e3f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045697892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2045697892
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.52680501
Short name T528
Test name
Test status
Simulation time 1998967483 ps
CPU time 7.03 seconds
Started Mar 03 12:46:04 PM PST 24
Finished Mar 03 12:46:12 PM PST 24
Peak memory 200152 kb
Host smart-249215a6-5897-4784-b86b-cce0918f4e94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52680501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.52680501
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3115138647
Short name T345
Test name
Test status
Simulation time 473732918 ps
CPU time 2.94 seconds
Started Mar 03 12:46:13 PM PST 24
Finished Mar 03 12:46:17 PM PST 24
Peak memory 208108 kb
Host smart-cda3c6e7-599b-4d0a-a7c0-b1a1f4f10d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115138647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3115138647
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.801676701
Short name T1
Test name
Test status
Simulation time 129992543 ps
CPU time 1.25 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:45:56 PM PST 24
Peak memory 199856 kb
Host smart-8b791ec0-13e7-4e21-b36e-744a15e03dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801676701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.801676701
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3441116143
Short name T479
Test name
Test status
Simulation time 81702514 ps
CPU time 0.8 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:45:56 PM PST 24
Peak memory 199844 kb
Host smart-d6f23de4-a13c-4315-8b0b-85d398ac9edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441116143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3441116143
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2799802676
Short name T40
Test name
Test status
Simulation time 1895165987 ps
CPU time 7.63 seconds
Started Mar 03 12:46:10 PM PST 24
Finished Mar 03 12:46:17 PM PST 24
Peak memory 220780 kb
Host smart-a7698e5f-4971-4253-8b8f-e29daf1d3437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799802676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2799802676
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2860666949
Short name T373
Test name
Test status
Simulation time 244946213 ps
CPU time 1.07 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 216992 kb
Host smart-baaa1fe4-ac73-4cfc-a37c-1f9f120bf0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860666949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2860666949
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2370702009
Short name T436
Test name
Test status
Simulation time 127829238 ps
CPU time 0.88 seconds
Started Mar 03 12:45:56 PM PST 24
Finished Mar 03 12:45:57 PM PST 24
Peak memory 199848 kb
Host smart-429d1c88-9842-4b86-ac39-d012798b54a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370702009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2370702009
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.245666972
Short name T232
Test name
Test status
Simulation time 1698712320 ps
CPU time 6.32 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 200192 kb
Host smart-49bc1b15-ce28-4af5-b3ec-21a45192b3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245666972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.245666972
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1300320677
Short name T220
Test name
Test status
Simulation time 102984566 ps
CPU time 1.03 seconds
Started Mar 03 12:45:54 PM PST 24
Finished Mar 03 12:45:55 PM PST 24
Peak memory 200032 kb
Host smart-36d4d49f-6560-48dd-afee-519e607f13ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300320677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1300320677
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3405669174
Short name T190
Test name
Test status
Simulation time 119442623 ps
CPU time 1.14 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:45:57 PM PST 24
Peak memory 200360 kb
Host smart-0fbedabe-08e1-4d1b-b8a7-98e60a0f6968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405669174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3405669174
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1335367237
Short name T532
Test name
Test status
Simulation time 15486823516 ps
CPU time 58.88 seconds
Started Mar 03 12:46:06 PM PST 24
Finished Mar 03 12:47:06 PM PST 24
Peak memory 200280 kb
Host smart-4ecabb81-7aac-4c0e-b7d2-5ccfd57b6811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335367237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1335367237
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.738902747
Short name T195
Test name
Test status
Simulation time 287157280 ps
CPU time 2.15 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:55 PM PST 24
Peak memory 199920 kb
Host smart-065ff628-7a7e-4a9b-8046-7dd11ae97c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738902747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.738902747
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3667557179
Short name T277
Test name
Test status
Simulation time 195111409 ps
CPU time 1.26 seconds
Started Mar 03 12:45:54 PM PST 24
Finished Mar 03 12:45:55 PM PST 24
Peak memory 200256 kb
Host smart-55f5b308-838c-4773-ad12-1fc29cfb44e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667557179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3667557179
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.132716179
Short name T226
Test name
Test status
Simulation time 86748115 ps
CPU time 0.92 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 199952 kb
Host smart-2c5cd8eb-4ada-42ad-a09d-13349a992af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132716179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.132716179
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1748738851
Short name T400
Test name
Test status
Simulation time 1225003087 ps
CPU time 5.99 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:46:01 PM PST 24
Peak memory 216464 kb
Host smart-f94c067b-e983-4bcf-9a51-77c395f78e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748738851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1748738851
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1088922723
Short name T268
Test name
Test status
Simulation time 244411526 ps
CPU time 1.08 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 217044 kb
Host smart-95b62b64-9e65-48f1-acdb-1950e930f07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088922723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1088922723
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_reset.186451578
Short name T466
Test name
Test status
Simulation time 1559992494 ps
CPU time 6.34 seconds
Started Mar 03 12:45:49 PM PST 24
Finished Mar 03 12:45:56 PM PST 24
Peak memory 200196 kb
Host smart-0456d166-56b6-4b4c-8680-0feb05387948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186451578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.186451578
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3549424375
Short name T491
Test name
Test status
Simulation time 172951232 ps
CPU time 1.21 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 199948 kb
Host smart-31a915e5-d888-4549-b7e8-658e3bd4a8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549424375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3549424375
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.527003131
Short name T185
Test name
Test status
Simulation time 115281043 ps
CPU time 1.23 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:45:56 PM PST 24
Peak memory 200160 kb
Host smart-74d99379-4b31-4f69-a90a-1075f378f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527003131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.527003131
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3192235841
Short name T241
Test name
Test status
Simulation time 383706945 ps
CPU time 2.65 seconds
Started Mar 03 12:46:08 PM PST 24
Finished Mar 03 12:46:11 PM PST 24
Peak memory 199876 kb
Host smart-66634af7-07b1-49a9-a9a7-0b5d1142cc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192235841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3192235841
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2157045292
Short name T517
Test name
Test status
Simulation time 118322896 ps
CPU time 1.08 seconds
Started Mar 03 12:46:07 PM PST 24
Finished Mar 03 12:46:08 PM PST 24
Peak memory 199928 kb
Host smart-13459e2f-514a-4b56-8693-c398b7787908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157045292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2157045292
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2938325532
Short name T500
Test name
Test status
Simulation time 83371065 ps
CPU time 0.89 seconds
Started Mar 03 12:45:54 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 199920 kb
Host smart-063afed8-cb2d-41fc-8264-124c22c952a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938325532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2938325532
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4233091891
Short name T401
Test name
Test status
Simulation time 2372088192 ps
CPU time 8.33 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:46:02 PM PST 24
Peak memory 217300 kb
Host smart-ad49291b-ec37-4615-9540-856cb8009f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233091891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4233091891
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3068536387
Short name T72
Test name
Test status
Simulation time 245733194 ps
CPU time 1.07 seconds
Started Mar 03 12:46:10 PM PST 24
Finished Mar 03 12:46:12 PM PST 24
Peak memory 217048 kb
Host smart-b100fcf8-4c26-48dc-8a02-145b30f8e471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068536387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3068536387
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3113945661
Short name T488
Test name
Test status
Simulation time 98076441 ps
CPU time 0.8 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:45:59 PM PST 24
Peak memory 200084 kb
Host smart-a4d05642-289f-4310-9307-30f450a77034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113945661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3113945661
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.728450125
Short name T92
Test name
Test status
Simulation time 1928583932 ps
CPU time 6.78 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:05 PM PST 24
Peak memory 200236 kb
Host smart-29e6f8a9-f049-4a3a-a631-4077d346c944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728450125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.728450125
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3179573654
Short name T338
Test name
Test status
Simulation time 202696634 ps
CPU time 1.38 seconds
Started Mar 03 12:46:04 PM PST 24
Finished Mar 03 12:46:06 PM PST 24
Peak memory 200404 kb
Host smart-32c5d9db-5c37-498a-beb4-0c5fa1decdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179573654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3179573654
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.319634326
Short name T494
Test name
Test status
Simulation time 915170561 ps
CPU time 4.72 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:46:01 PM PST 24
Peak memory 200468 kb
Host smart-fad33971-0803-4f72-a156-a9eb760a476f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319634326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.319634326
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1920095920
Short name T138
Test name
Test status
Simulation time 115454832 ps
CPU time 1.09 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:45:58 PM PST 24
Peak memory 199948 kb
Host smart-2b0302ea-9867-409c-9035-1dfe58c75dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920095920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1920095920
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4157671639
Short name T242
Test name
Test status
Simulation time 84356107 ps
CPU time 0.81 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:45:56 PM PST 24
Peak memory 199752 kb
Host smart-ee05467f-cf21-4bfb-bcf0-aeee125018d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157671639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4157671639
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1534162582
Short name T31
Test name
Test status
Simulation time 2364800146 ps
CPU time 9.66 seconds
Started Mar 03 12:46:15 PM PST 24
Finished Mar 03 12:46:25 PM PST 24
Peak memory 217184 kb
Host smart-55fdcda2-08fb-431d-87b8-ce2b8dc6d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534162582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1534162582
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2427386097
Short name T520
Test name
Test status
Simulation time 244319559 ps
CPU time 1.07 seconds
Started Mar 03 12:46:05 PM PST 24
Finished Mar 03 12:46:06 PM PST 24
Peak memory 216980 kb
Host smart-8aef0870-1868-41cc-9f93-e284564ee6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427386097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2427386097
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2372764305
Short name T217
Test name
Test status
Simulation time 196818757 ps
CPU time 0.88 seconds
Started Mar 03 12:46:10 PM PST 24
Finished Mar 03 12:46:11 PM PST 24
Peak memory 199824 kb
Host smart-19623a09-f218-4c35-8115-6010aecc69e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372764305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2372764305
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2875193248
Short name T484
Test name
Test status
Simulation time 960623789 ps
CPU time 5.33 seconds
Started Mar 03 12:45:56 PM PST 24
Finished Mar 03 12:46:02 PM PST 24
Peak memory 200216 kb
Host smart-70ed6565-f70b-4314-bb62-715df948f99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875193248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2875193248
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.929222794
Short name T533
Test name
Test status
Simulation time 149980938 ps
CPU time 1.14 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:45:58 PM PST 24
Peak memory 199940 kb
Host smart-05e54aa6-8461-4437-b533-2d84f09ebd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929222794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.929222794
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2636923896
Short name T319
Test name
Test status
Simulation time 123359059 ps
CPU time 1.13 seconds
Started Mar 03 12:45:54 PM PST 24
Finished Mar 03 12:45:56 PM PST 24
Peak memory 200160 kb
Host smart-5430599c-5018-4118-8ffc-37be252d2f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636923896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2636923896
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1376946136
Short name T505
Test name
Test status
Simulation time 2092583054 ps
CPU time 10.07 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:08 PM PST 24
Peak memory 200064 kb
Host smart-f9d7819a-56c7-4173-882a-721209a1e9e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376946136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1376946136
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2892047342
Short name T295
Test name
Test status
Simulation time 417288475 ps
CPU time 2.38 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 208156 kb
Host smart-8326b755-00bb-48d5-b96b-12965677e923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892047342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2892047342
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.571292050
Short name T335
Test name
Test status
Simulation time 65450983 ps
CPU time 0.83 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 200000 kb
Host smart-69218ea7-8e91-4aca-b994-1a2739d1251f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571292050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.571292050
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.4010549858
Short name T432
Test name
Test status
Simulation time 94692714 ps
CPU time 0.93 seconds
Started Mar 03 12:45:59 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 199808 kb
Host smart-81076361-9afc-4d51-bfd6-2cb139839522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010549858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4010549858
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1737282592
Short name T456
Test name
Test status
Simulation time 1901679044 ps
CPU time 6.87 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:05 PM PST 24
Peak memory 217428 kb
Host smart-5b1ead77-6d4c-4ee9-a449-ea8c00f3207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737282592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1737282592
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.87341037
Short name T448
Test name
Test status
Simulation time 244000299 ps
CPU time 1.12 seconds
Started Mar 03 12:46:02 PM PST 24
Finished Mar 03 12:46:03 PM PST 24
Peak memory 217024 kb
Host smart-54aa7d54-54ae-44db-9295-1ffc30a61b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87341037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.87341037
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1499802898
Short name T306
Test name
Test status
Simulation time 149291714 ps
CPU time 0.87 seconds
Started Mar 03 12:46:02 PM PST 24
Finished Mar 03 12:46:03 PM PST 24
Peak memory 199748 kb
Host smart-dc1ad020-f2b7-4e8e-adb1-53a3bb70c170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499802898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1499802898
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3335917916
Short name T329
Test name
Test status
Simulation time 1682125091 ps
CPU time 7.61 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:46:05 PM PST 24
Peak memory 200124 kb
Host smart-ed82e53a-3b37-41c2-b92e-979cc7ab81d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335917916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3335917916
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3149591216
Short name T130
Test name
Test status
Simulation time 107689006 ps
CPU time 1.06 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:46:03 PM PST 24
Peak memory 200020 kb
Host smart-b25a6743-26a9-44f9-b03e-daecc7ccc6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149591216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3149591216
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2524098172
Short name T42
Test name
Test status
Simulation time 243074773 ps
CPU time 1.53 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:19 PM PST 24
Peak memory 200156 kb
Host smart-7481e640-1656-48da-b226-669877f5af6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524098172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2524098172
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.739128767
Short name T114
Test name
Test status
Simulation time 5250905727 ps
CPU time 18.86 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:46:17 PM PST 24
Peak memory 208684 kb
Host smart-5c687e27-b223-4688-9594-b07f471bac65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739128767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.739128767
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.48417731
Short name T460
Test name
Test status
Simulation time 355694673 ps
CPU time 2.31 seconds
Started Mar 03 12:46:07 PM PST 24
Finished Mar 03 12:46:10 PM PST 24
Peak memory 199904 kb
Host smart-2be82d2c-320a-4b82-95aa-9879dc2507bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48417731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.48417731
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3100584523
Short name T396
Test name
Test status
Simulation time 166664622 ps
CPU time 1.16 seconds
Started Mar 03 12:46:15 PM PST 24
Finished Mar 03 12:46:17 PM PST 24
Peak memory 199944 kb
Host smart-dee889db-d388-46e6-939d-42d63243cd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100584523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3100584523
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1543216424
Short name T258
Test name
Test status
Simulation time 59992620 ps
CPU time 0.78 seconds
Started Mar 03 12:46:13 PM PST 24
Finished Mar 03 12:46:14 PM PST 24
Peak memory 199940 kb
Host smart-70508393-887c-41fd-8b4d-49d47ece55b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543216424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1543216424
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.703573901
Short name T368
Test name
Test status
Simulation time 1898621108 ps
CPU time 7.94 seconds
Started Mar 03 12:46:19 PM PST 24
Finished Mar 03 12:46:27 PM PST 24
Peak memory 217632 kb
Host smart-46fd8ade-d48e-4739-a078-828591097b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703573901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.703573901
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2765279817
Short name T177
Test name
Test status
Simulation time 245826857 ps
CPU time 1.04 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:45:59 PM PST 24
Peak memory 216960 kb
Host smart-60b75b4c-ab8a-4d14-bb58-d4438c86a091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765279817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2765279817
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.198911389
Short name T412
Test name
Test status
Simulation time 173154684 ps
CPU time 0.96 seconds
Started Mar 03 12:45:59 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 199748 kb
Host smart-98ea028f-247e-432d-8f9f-a1a62dbc5b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198911389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.198911389
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2731055503
Short name T347
Test name
Test status
Simulation time 1696669110 ps
CPU time 6.23 seconds
Started Mar 03 12:46:00 PM PST 24
Finished Mar 03 12:46:06 PM PST 24
Peak memory 200076 kb
Host smart-41085732-8726-463f-b712-12c12395667f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731055503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2731055503
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2853647456
Short name T70
Test name
Test status
Simulation time 176442056 ps
CPU time 1.17 seconds
Started Mar 03 12:46:08 PM PST 24
Finished Mar 03 12:46:09 PM PST 24
Peak memory 199988 kb
Host smart-c49202b8-b30e-4b21-a332-7347697e09e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853647456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2853647456
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.610900146
Short name T414
Test name
Test status
Simulation time 252190155 ps
CPU time 1.49 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 199968 kb
Host smart-7d97840e-0dff-41e4-9707-d8a90b52c5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610900146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.610900146
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.965960477
Short name T21
Test name
Test status
Simulation time 5261582830 ps
CPU time 23.54 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 200260 kb
Host smart-32f0dcf0-c0c2-4ead-b80f-13586eacc691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965960477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.965960477
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1521624447
Short name T237
Test name
Test status
Simulation time 458735474 ps
CPU time 2.4 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 199844 kb
Host smart-62a1b00d-c032-4c51-8dd0-57bd8f57ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521624447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1521624447
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2033162329
Short name T357
Test name
Test status
Simulation time 316952555 ps
CPU time 1.62 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 199996 kb
Host smart-9c863863-772c-49da-9fa2-6cd8b4632b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033162329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2033162329
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2230530275
Short name T398
Test name
Test status
Simulation time 76066437 ps
CPU time 0.76 seconds
Started Mar 03 12:45:32 PM PST 24
Finished Mar 03 12:45:34 PM PST 24
Peak memory 199860 kb
Host smart-eb9a4302-6347-4fea-ba3e-6efbb359f256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230530275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2230530275
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4266259946
Short name T282
Test name
Test status
Simulation time 1225083527 ps
CPU time 5.71 seconds
Started Mar 03 12:45:41 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 220380 kb
Host smart-6244caa3-b21c-4f06-adff-8abf266c6805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266259946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4266259946
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2882491138
Short name T363
Test name
Test status
Simulation time 244041880 ps
CPU time 1.16 seconds
Started Mar 03 12:45:27 PM PST 24
Finished Mar 03 12:45:29 PM PST 24
Peak memory 217112 kb
Host smart-8b666a27-3a22-4dd9-b0fc-214f33c6c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882491138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2882491138
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4057514590
Short name T409
Test name
Test status
Simulation time 99356589 ps
CPU time 0.77 seconds
Started Mar 03 12:45:38 PM PST 24
Finished Mar 03 12:45:40 PM PST 24
Peak memory 199736 kb
Host smart-4ade45e7-7803-47ea-8165-aa639816e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057514590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4057514590
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.924853100
Short name T459
Test name
Test status
Simulation time 1570826442 ps
CPU time 6.7 seconds
Started Mar 03 12:45:40 PM PST 24
Finished Mar 03 12:45:47 PM PST 24
Peak memory 199988 kb
Host smart-9175a7e4-7a14-417b-89fd-6961fa31345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924853100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.924853100
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3464738113
Short name T60
Test name
Test status
Simulation time 20664312267 ps
CPU time 35.96 seconds
Started Mar 03 12:45:37 PM PST 24
Finished Mar 03 12:46:13 PM PST 24
Peak memory 217668 kb
Host smart-6908cd41-79d0-4d47-b8d5-190a18f88309
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464738113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3464738113
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2188118743
Short name T254
Test name
Test status
Simulation time 184948812 ps
CPU time 1.15 seconds
Started Mar 03 12:45:30 PM PST 24
Finished Mar 03 12:45:32 PM PST 24
Peak memory 199868 kb
Host smart-fbbc4c94-24b3-4c67-911d-d82fb2e7b634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188118743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2188118743
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3572504575
Short name T474
Test name
Test status
Simulation time 259446576 ps
CPU time 1.65 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:48 PM PST 24
Peak memory 200028 kb
Host smart-26c67227-e0e7-4b11-94db-d5628862ddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572504575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3572504575
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.288059467
Short name T450
Test name
Test status
Simulation time 402418159 ps
CPU time 1.9 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:47 PM PST 24
Peak memory 200004 kb
Host smart-b07ca249-ef8a-480b-a88a-6865d0bc66b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288059467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.288059467
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.4176169608
Short name T518
Test name
Test status
Simulation time 127028803 ps
CPU time 1.57 seconds
Started Mar 03 12:45:46 PM PST 24
Finished Mar 03 12:45:48 PM PST 24
Peak memory 208048 kb
Host smart-73a2fdae-f247-45cd-80c3-5840fd33c6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176169608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.4176169608
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3135001183
Short name T515
Test name
Test status
Simulation time 203778054 ps
CPU time 1.22 seconds
Started Mar 03 12:45:35 PM PST 24
Finished Mar 03 12:45:37 PM PST 24
Peak memory 199948 kb
Host smart-9338b77f-b6f9-4f33-acc9-2e6238b60896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135001183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3135001183
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1732108355
Short name T314
Test name
Test status
Simulation time 84400230 ps
CPU time 0.8 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:17 PM PST 24
Peak memory 199908 kb
Host smart-b15e9f10-b970-4ed7-975a-35c0f54f22b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732108355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1732108355
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1869934661
Short name T34
Test name
Test status
Simulation time 1887919298 ps
CPU time 7.85 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:46:06 PM PST 24
Peak memory 229548 kb
Host smart-d1bf5ee2-12eb-474b-bf16-fb8e88fe1efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869934661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1869934661
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3788283442
Short name T263
Test name
Test status
Simulation time 244459192 ps
CPU time 1.07 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 216964 kb
Host smart-51bc2f7d-703f-4e8b-a2ae-d146b59fd4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788283442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3788283442
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.395210098
Short name T12
Test name
Test status
Simulation time 233068570 ps
CPU time 1.11 seconds
Started Mar 03 12:46:01 PM PST 24
Finished Mar 03 12:46:02 PM PST 24
Peak memory 199716 kb
Host smart-01274bba-6320-4852-ad70-b5cc60bbfccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395210098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.395210098
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.25025097
Short name T501
Test name
Test status
Simulation time 1203447276 ps
CPU time 5.37 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:04 PM PST 24
Peak memory 200176 kb
Host smart-596b4de8-60f6-475c-9263-a0c32cacaeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25025097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.25025097
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.827450605
Short name T307
Test name
Test status
Simulation time 103619748 ps
CPU time 1.04 seconds
Started Mar 03 12:45:59 PM PST 24
Finished Mar 03 12:46:01 PM PST 24
Peak memory 199896 kb
Host smart-b5ee82c0-8cce-485d-a18b-9b94a9c6d1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827450605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.827450605
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3987768849
Short name T323
Test name
Test status
Simulation time 266736503 ps
CPU time 1.57 seconds
Started Mar 03 12:46:00 PM PST 24
Finished Mar 03 12:46:02 PM PST 24
Peak memory 200088 kb
Host smart-5bb89adc-2da3-4945-b5a9-a51df06c019d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987768849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3987768849
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1553387583
Short name T96
Test name
Test status
Simulation time 6713291913 ps
CPU time 28.48 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:37 PM PST 24
Peak memory 208360 kb
Host smart-db42ba12-827c-4044-a050-133dc06754c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553387583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1553387583
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.756075622
Short name T184
Test name
Test status
Simulation time 149537776 ps
CPU time 1.9 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:45:59 PM PST 24
Peak memory 199788 kb
Host smart-4928664e-18b3-416a-ae4b-d23f30c30e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756075622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.756075622
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1231793530
Short name T33
Test name
Test status
Simulation time 256621400 ps
CPU time 1.66 seconds
Started Mar 03 12:45:59 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 200028 kb
Host smart-3506be8d-50b7-4b8f-a548-ebbd35a13633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231793530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1231793530
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3361399094
Short name T224
Test name
Test status
Simulation time 61067937 ps
CPU time 0.77 seconds
Started Mar 03 12:46:06 PM PST 24
Finished Mar 03 12:46:07 PM PST 24
Peak memory 199916 kb
Host smart-2ffcc43a-d80d-4b21-b4b3-5c91dc12c677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361399094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3361399094
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.102386180
Short name T421
Test name
Test status
Simulation time 2357051912 ps
CPU time 7.9 seconds
Started Mar 03 12:46:18 PM PST 24
Finished Mar 03 12:46:27 PM PST 24
Peak memory 217696 kb
Host smart-94949e88-c5fd-4e20-ab1c-5cf31a2e0dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102386180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.102386180
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.567178914
Short name T439
Test name
Test status
Simulation time 245029873 ps
CPU time 1.05 seconds
Started Mar 03 12:46:00 PM PST 24
Finished Mar 03 12:46:01 PM PST 24
Peak memory 216916 kb
Host smart-55e2eff3-9d73-4265-ac18-123eb963ef5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567178914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.567178914
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2700023926
Short name T467
Test name
Test status
Simulation time 149029482 ps
CPU time 0.91 seconds
Started Mar 03 12:46:18 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 199716 kb
Host smart-f15dddd4-2eb0-4046-9a2a-9ead89f2bae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700023926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2700023926
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.963809455
Short name T514
Test name
Test status
Simulation time 1226450462 ps
CPU time 5.16 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 200100 kb
Host smart-332953f9-07ad-4348-ba77-dd640c973191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963809455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.963809455
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2664973590
Short name T342
Test name
Test status
Simulation time 104984136 ps
CPU time 1.03 seconds
Started Mar 03 12:46:14 PM PST 24
Finished Mar 03 12:46:16 PM PST 24
Peak memory 200020 kb
Host smart-e5c244b1-5056-40b7-ba1b-f28513777f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664973590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2664973590
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1758327361
Short name T310
Test name
Test status
Simulation time 200413015 ps
CPU time 1.55 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:45:57 PM PST 24
Peak memory 200192 kb
Host smart-c70c0b29-fff6-4aeb-8fc8-b17af684fcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758327361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1758327361
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.505764431
Short name T215
Test name
Test status
Simulation time 15871823507 ps
CPU time 60.44 seconds
Started Mar 03 12:46:07 PM PST 24
Finished Mar 03 12:47:08 PM PST 24
Peak memory 200240 kb
Host smart-28744942-ea6c-4739-b5c0-16b0501ecf2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505764431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.505764431
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2484851846
Short name T465
Test name
Test status
Simulation time 292124130 ps
CPU time 2.16 seconds
Started Mar 03 12:46:01 PM PST 24
Finished Mar 03 12:46:04 PM PST 24
Peak memory 199896 kb
Host smart-ae30608e-2ef1-4f6b-baa4-e2c1620ecfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484851846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2484851846
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2376021133
Short name T309
Test name
Test status
Simulation time 195945688 ps
CPU time 1.2 seconds
Started Mar 03 12:46:01 PM PST 24
Finished Mar 03 12:46:03 PM PST 24
Peak memory 199944 kb
Host smart-114382c5-97d8-4f10-ac8f-f9f7f6dacef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376021133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2376021133
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.151440739
Short name T225
Test name
Test status
Simulation time 77737073 ps
CPU time 0.78 seconds
Started Mar 03 12:45:56 PM PST 24
Finished Mar 03 12:45:57 PM PST 24
Peak memory 199868 kb
Host smart-2a63c137-daa3-410e-8c9b-46ccdc5f0eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151440739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.151440739
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1024649630
Short name T27
Test name
Test status
Simulation time 1907345461 ps
CPU time 7.01 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:46:04 PM PST 24
Peak memory 220568 kb
Host smart-bf79c25d-ed10-4fca-a854-a659389ffeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024649630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1024649630
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3756747129
Short name T536
Test name
Test status
Simulation time 243862787 ps
CPU time 1.11 seconds
Started Mar 03 12:45:56 PM PST 24
Finished Mar 03 12:45:58 PM PST 24
Peak memory 217104 kb
Host smart-8c8cc27d-b9e3-419d-8765-6f5bde34420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756747129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3756747129
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4179595774
Short name T441
Test name
Test status
Simulation time 145290294 ps
CPU time 0.82 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:45:59 PM PST 24
Peak memory 199756 kb
Host smart-d349d22d-1350-4341-8526-514dcee17936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179595774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4179595774
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3127037125
Short name T235
Test name
Test status
Simulation time 1471009619 ps
CPU time 6.2 seconds
Started Mar 03 12:46:05 PM PST 24
Finished Mar 03 12:46:12 PM PST 24
Peak memory 200176 kb
Host smart-f67106b5-6f1e-4e10-9984-e6ae0045b6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127037125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3127037125
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3886352391
Short name T139
Test name
Test status
Simulation time 97691131 ps
CPU time 1.02 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:45:59 PM PST 24
Peak memory 199876 kb
Host smart-00d3c447-62ee-4e15-9806-6a65edb7f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886352391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3886352391
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3667651184
Short name T218
Test name
Test status
Simulation time 117317913 ps
CPU time 1.17 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 200108 kb
Host smart-6baf34cf-bad5-4e5a-b84b-140893b3ebe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667651184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3667651184
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1850153805
Short name T509
Test name
Test status
Simulation time 9451068777 ps
CPU time 32.98 seconds
Started Mar 03 12:45:58 PM PST 24
Finished Mar 03 12:46:31 PM PST 24
Peak memory 200284 kb
Host smart-eb90aa9c-ed9e-4d70-b90a-9f59af64e947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850153805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1850153805
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2030178793
Short name T147
Test name
Test status
Simulation time 373333306 ps
CPU time 2.43 seconds
Started Mar 03 12:45:59 PM PST 24
Finished Mar 03 12:46:02 PM PST 24
Peak memory 199828 kb
Host smart-345fe610-7a3a-4672-9125-fc523ad29912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030178793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2030178793
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.214223085
Short name T469
Test name
Test status
Simulation time 71747005 ps
CPU time 0.83 seconds
Started Mar 03 12:46:07 PM PST 24
Finished Mar 03 12:46:08 PM PST 24
Peak memory 200036 kb
Host smart-75fba793-898a-4285-8050-4858bd30b0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214223085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.214223085
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1056683484
Short name T208
Test name
Test status
Simulation time 68119086 ps
CPU time 0.76 seconds
Started Mar 03 12:46:17 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 199940 kb
Host smart-d011bc84-be1a-4b64-acb5-fb6131106784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056683484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1056683484
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1067695484
Short name T25
Test name
Test status
Simulation time 1227074411 ps
CPU time 5.7 seconds
Started Mar 03 12:46:15 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 217028 kb
Host smart-30c77513-3048-4c04-b69e-bd9e9f98d73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067695484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1067695484
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3291576692
Short name T165
Test name
Test status
Simulation time 244373725 ps
CPU time 1.08 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 216884 kb
Host smart-7df49c27-34b2-4bd3-8870-58e14395951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291576692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3291576692
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2282733100
Short name T359
Test name
Test status
Simulation time 227738465 ps
CPU time 0.99 seconds
Started Mar 03 12:46:01 PM PST 24
Finished Mar 03 12:46:02 PM PST 24
Peak memory 199640 kb
Host smart-a209bce0-033f-4f95-9543-a7c921b49052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282733100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2282733100
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.25864571
Short name T113
Test name
Test status
Simulation time 2033037857 ps
CPU time 8.16 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:28 PM PST 24
Peak memory 200216 kb
Host smart-ff1a7eea-14ce-4a05-abae-c8fa73303fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25864571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.25864571
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.21666665
Short name T234
Test name
Test status
Simulation time 171358175 ps
CPU time 1.24 seconds
Started Mar 03 12:46:12 PM PST 24
Finished Mar 03 12:46:15 PM PST 24
Peak memory 199992 kb
Host smart-ea5624af-97df-4f63-81f7-1d4a9df1b911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21666665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.21666665
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2175010353
Short name T249
Test name
Test status
Simulation time 188283203 ps
CPU time 1.47 seconds
Started Mar 03 12:46:14 PM PST 24
Finished Mar 03 12:46:16 PM PST 24
Peak memory 200052 kb
Host smart-45f65c53-265a-4c18-8278-daefaa0b22ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175010353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2175010353
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.710371547
Short name T259
Test name
Test status
Simulation time 15146394432 ps
CPU time 51.11 seconds
Started Mar 03 12:46:06 PM PST 24
Finished Mar 03 12:46:57 PM PST 24
Peak memory 200252 kb
Host smart-bfe879d3-bce7-4f30-a7cf-dfa3f6e72f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710371547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.710371547
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.937220764
Short name T158
Test name
Test status
Simulation time 340659544 ps
CPU time 2.34 seconds
Started Mar 03 12:46:03 PM PST 24
Finished Mar 03 12:46:05 PM PST 24
Peak memory 199976 kb
Host smart-ef35834e-cacd-4883-b86d-0c40b7078b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937220764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.937220764
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4138850627
Short name T6
Test name
Test status
Simulation time 182875509 ps
CPU time 1.28 seconds
Started Mar 03 12:46:10 PM PST 24
Finished Mar 03 12:46:13 PM PST 24
Peak memory 200008 kb
Host smart-44cfbf89-cdf3-4a90-9408-2f06b80b74f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138850627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4138850627
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2565695983
Short name T169
Test name
Test status
Simulation time 63740991 ps
CPU time 0.74 seconds
Started Mar 03 12:46:15 PM PST 24
Finished Mar 03 12:46:16 PM PST 24
Peak memory 199776 kb
Host smart-98d5362b-adab-42be-a583-c21ad4d60ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565695983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2565695983
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1829379247
Short name T489
Test name
Test status
Simulation time 2386015670 ps
CPU time 8.02 seconds
Started Mar 03 12:46:17 PM PST 24
Finished Mar 03 12:46:26 PM PST 24
Peak memory 221412 kb
Host smart-c02c0c05-a939-41ea-b370-9ed0c763362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829379247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1829379247
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.118603843
Short name T93
Test name
Test status
Simulation time 243744290 ps
CPU time 1.11 seconds
Started Mar 03 12:46:17 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 217032 kb
Host smart-93f29aa1-4ac2-4b90-befb-ee4a865081db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118603843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.118603843
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1824495586
Short name T393
Test name
Test status
Simulation time 121940039 ps
CPU time 0.81 seconds
Started Mar 03 12:46:04 PM PST 24
Finished Mar 03 12:46:05 PM PST 24
Peak memory 199756 kb
Host smart-53ef4712-bac5-4d01-8573-acd567972151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824495586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1824495586
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3267176087
Short name T227
Test name
Test status
Simulation time 1682202154 ps
CPU time 6.65 seconds
Started Mar 03 12:46:19 PM PST 24
Finished Mar 03 12:46:26 PM PST 24
Peak memory 200240 kb
Host smart-b70db5e3-19a7-462f-9648-bc77c3ee12cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267176087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3267176087
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1711130530
Short name T372
Test name
Test status
Simulation time 141119663 ps
CPU time 1.15 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 200016 kb
Host smart-e6ecc99f-95d5-449c-9f49-0811b0ee7f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711130530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1711130530
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3288794464
Short name T384
Test name
Test status
Simulation time 224608983 ps
CPU time 1.53 seconds
Started Mar 03 12:46:03 PM PST 24
Finished Mar 03 12:46:05 PM PST 24
Peak memory 200172 kb
Host smart-e2fd4087-64b4-4ac0-a6b4-3977fba7c37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288794464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3288794464
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3098892306
Short name T383
Test name
Test status
Simulation time 1268330306 ps
CPU time 6.2 seconds
Started Mar 03 12:46:14 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 200196 kb
Host smart-893fa087-33c1-4ef7-86b8-1d605cd2fc47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098892306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3098892306
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3177539055
Short name T136
Test name
Test status
Simulation time 344782382 ps
CPU time 2.31 seconds
Started Mar 03 12:46:11 PM PST 24
Finished Mar 03 12:46:14 PM PST 24
Peak memory 199928 kb
Host smart-58532d5b-8f00-441c-b116-95e6334ebab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177539055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3177539055
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3005670551
Short name T186
Test name
Test status
Simulation time 236080707 ps
CPU time 1.5 seconds
Started Mar 03 12:46:15 PM PST 24
Finished Mar 03 12:46:17 PM PST 24
Peak memory 200132 kb
Host smart-54d0af0f-67f6-4418-9bb7-6f11f6f3fe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005670551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3005670551
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.432125059
Short name T354
Test name
Test status
Simulation time 78691101 ps
CPU time 0.84 seconds
Started Mar 03 12:46:14 PM PST 24
Finished Mar 03 12:46:15 PM PST 24
Peak memory 199956 kb
Host smart-f2a55405-66d1-4f5e-828e-138160ad2b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432125059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.432125059
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.8879054
Short name T23
Test name
Test status
Simulation time 1226340841 ps
CPU time 6.51 seconds
Started Mar 03 12:46:10 PM PST 24
Finished Mar 03 12:46:17 PM PST 24
Peak memory 220924 kb
Host smart-9f4974f1-92c5-4708-8afe-9d34b2b6c61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8879054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.8879054
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4206514606
Short name T134
Test name
Test status
Simulation time 244621725 ps
CPU time 1.18 seconds
Started Mar 03 12:46:04 PM PST 24
Finished Mar 03 12:46:05 PM PST 24
Peak memory 216992 kb
Host smart-d95e1349-467c-42a7-8071-c839d2b7441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206514606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4206514606
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1511574818
Short name T16
Test name
Test status
Simulation time 191695496 ps
CPU time 0.87 seconds
Started Mar 03 12:46:17 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 199844 kb
Host smart-cb07e638-6690-4ee6-aff8-5c966fa3bbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511574818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1511574818
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.4057430295
Short name T192
Test name
Test status
Simulation time 1415923297 ps
CPU time 5.87 seconds
Started Mar 03 12:46:05 PM PST 24
Finished Mar 03 12:46:11 PM PST 24
Peak memory 200168 kb
Host smart-4e626efc-aff2-4d39-80ed-1dc621e4db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057430295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4057430295
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3116043792
Short name T247
Test name
Test status
Simulation time 100982550 ps
CPU time 1.05 seconds
Started Mar 03 12:46:24 PM PST 24
Finished Mar 03 12:46:25 PM PST 24
Peak memory 199940 kb
Host smart-d8567bc0-47a0-49f0-ba4e-f151e8f44e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116043792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3116043792
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2834133557
Short name T260
Test name
Test status
Simulation time 248277735 ps
CPU time 1.48 seconds
Started Mar 03 12:46:18 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 200140 kb
Host smart-55a47f14-842d-46d2-a46c-9881f80e22e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834133557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2834133557
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2242278374
Short name T422
Test name
Test status
Simulation time 13598690428 ps
CPU time 49.21 seconds
Started Mar 03 12:46:19 PM PST 24
Finished Mar 03 12:47:09 PM PST 24
Peak memory 200300 kb
Host smart-2cef78ba-67a2-41c0-bbd1-7fae75067df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242278374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2242278374
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.4170805567
Short name T420
Test name
Test status
Simulation time 343537314 ps
CPU time 2.16 seconds
Started Mar 03 12:46:11 PM PST 24
Finished Mar 03 12:46:15 PM PST 24
Peak memory 199716 kb
Host smart-d7fdab0a-bf7a-46c5-ad7c-32d2d26cd781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170805567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.4170805567
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1417860828
Short name T386
Test name
Test status
Simulation time 73244568 ps
CPU time 0.75 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 199928 kb
Host smart-4b743ebb-fbb1-46e9-b3e1-0dc453b6a784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417860828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1417860828
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1463806042
Short name T499
Test name
Test status
Simulation time 85788067 ps
CPU time 0.88 seconds
Started Mar 03 12:46:08 PM PST 24
Finished Mar 03 12:46:09 PM PST 24
Peak memory 199944 kb
Host smart-5502403b-399c-4968-a19f-c271e5960eff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463806042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1463806042
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1141040245
Short name T477
Test name
Test status
Simulation time 246450243 ps
CPU time 1.05 seconds
Started Mar 03 12:46:21 PM PST 24
Finished Mar 03 12:46:27 PM PST 24
Peak memory 217052 kb
Host smart-f4db7fa7-1d63-44e2-8da5-bb9fce2150d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141040245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1141040245
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.724326326
Short name T526
Test name
Test status
Simulation time 169748473 ps
CPU time 0.88 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:23 PM PST 24
Peak memory 199624 kb
Host smart-e619eaec-0b86-4fb9-aa95-98246f643670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724326326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.724326326
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.601163717
Short name T387
Test name
Test status
Simulation time 789046309 ps
CPU time 4.58 seconds
Started Mar 03 12:46:13 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 200176 kb
Host smart-21396a76-2542-4582-9993-827e6869d738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601163717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.601163717
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1386535702
Short name T202
Test name
Test status
Simulation time 181746220 ps
CPU time 1.3 seconds
Started Mar 03 12:46:18 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 200020 kb
Host smart-ba800d25-f664-491c-b679-033c03627ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386535702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1386535702
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3401253146
Short name T377
Test name
Test status
Simulation time 118872496 ps
CPU time 1.19 seconds
Started Mar 03 12:46:06 PM PST 24
Finished Mar 03 12:46:07 PM PST 24
Peak memory 200096 kb
Host smart-790b92d6-84c0-405e-bbc5-472549a67ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401253146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3401253146
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3425014502
Short name T43
Test name
Test status
Simulation time 155648879 ps
CPU time 1.09 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 199996 kb
Host smart-275c9bcd-e8fc-4c28-8edf-cf8d1805e79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425014502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3425014502
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.54762692
Short name T191
Test name
Test status
Simulation time 132914884 ps
CPU time 1.72 seconds
Started Mar 03 12:46:09 PM PST 24
Finished Mar 03 12:46:11 PM PST 24
Peak memory 208064 kb
Host smart-da0549be-5802-4f5a-b43c-8490828f239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54762692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.54762692
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.440239815
Short name T265
Test name
Test status
Simulation time 193904279 ps
CPU time 1.23 seconds
Started Mar 03 12:46:23 PM PST 24
Finished Mar 03 12:46:24 PM PST 24
Peak memory 199992 kb
Host smart-18327edb-3647-44e1-b8c9-bcf14058e084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440239815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.440239815
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2638246184
Short name T150
Test name
Test status
Simulation time 67826498 ps
CPU time 0.74 seconds
Started Mar 03 12:46:14 PM PST 24
Finished Mar 03 12:46:15 PM PST 24
Peak memory 199908 kb
Host smart-9d3efd18-860f-49e3-9abb-1d64a5f361c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638246184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2638246184
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3496351839
Short name T508
Test name
Test status
Simulation time 1902261087 ps
CPU time 8.07 seconds
Started Mar 03 12:46:14 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 216816 kb
Host smart-acaea585-e6a6-4b08-861a-e802967957f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496351839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3496351839
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3243452389
Short name T269
Test name
Test status
Simulation time 243523414 ps
CPU time 1.08 seconds
Started Mar 03 12:46:23 PM PST 24
Finished Mar 03 12:46:24 PM PST 24
Peak memory 216888 kb
Host smart-90f36206-c0a3-420c-bfe1-dee4d1dcecce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243452389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3243452389
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1337363805
Short name T318
Test name
Test status
Simulation time 118189757 ps
CPU time 0.81 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 199824 kb
Host smart-2cdc3711-7970-4365-9060-8410f08ab945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337363805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1337363805
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3988284096
Short name T492
Test name
Test status
Simulation time 865824027 ps
CPU time 4.61 seconds
Started Mar 03 12:46:14 PM PST 24
Finished Mar 03 12:46:19 PM PST 24
Peak memory 200216 kb
Host smart-2b1fe1d7-b3ce-4384-962f-b4a70c905ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988284096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3988284096
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.76988118
Short name T281
Test name
Test status
Simulation time 98615492 ps
CPU time 1.02 seconds
Started Mar 03 12:46:10 PM PST 24
Finished Mar 03 12:46:13 PM PST 24
Peak memory 200008 kb
Host smart-b9b90834-713b-4e77-bf0c-c4e87f13648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76988118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.76988118
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.477805843
Short name T189
Test name
Test status
Simulation time 196993485 ps
CPU time 1.43 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 200092 kb
Host smart-84d93bab-1397-479a-bb94-220cc0a49098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477805843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.477805843
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1353576540
Short name T256
Test name
Test status
Simulation time 5947379165 ps
CPU time 21.49 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:37 PM PST 24
Peak memory 209460 kb
Host smart-df25173d-c2fa-40ee-9eda-eb6db19ba6ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353576540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1353576540
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3445870493
Short name T346
Test name
Test status
Simulation time 141565382 ps
CPU time 1.89 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:19 PM PST 24
Peak memory 199840 kb
Host smart-3a476ddb-1903-416b-9648-ba5de5bf943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445870493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3445870493
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3565643874
Short name T458
Test name
Test status
Simulation time 167407645 ps
CPU time 1.29 seconds
Started Mar 03 12:46:09 PM PST 24
Finished Mar 03 12:46:11 PM PST 24
Peak memory 200168 kb
Host smart-32447f9c-3858-428e-b596-703ceb0333da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565643874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3565643874
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4029255665
Short name T230
Test name
Test status
Simulation time 70528061 ps
CPU time 0.79 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:23 PM PST 24
Peak memory 199756 kb
Host smart-c2f5ed68-4373-46b0-a7ea-4740c50510dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029255665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4029255665
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1910543515
Short name T140
Test name
Test status
Simulation time 243898237 ps
CPU time 1.09 seconds
Started Mar 03 12:46:24 PM PST 24
Finished Mar 03 12:46:25 PM PST 24
Peak memory 217028 kb
Host smart-9f195427-726a-4139-9cfa-3f2f1a1fa95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910543515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1910543515
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2202695532
Short name T334
Test name
Test status
Simulation time 128818193 ps
CPU time 0.81 seconds
Started Mar 03 12:46:24 PM PST 24
Finished Mar 03 12:46:25 PM PST 24
Peak memory 199828 kb
Host smart-0e9f4ef1-cf78-41c9-a661-de97a1bd4dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202695532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2202695532
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2140595199
Short name T11
Test name
Test status
Simulation time 771945958 ps
CPU time 3.61 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:23 PM PST 24
Peak memory 200176 kb
Host smart-aff432db-fe54-4058-853d-b7b9e365510a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140595199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2140595199
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1493655107
Short name T391
Test name
Test status
Simulation time 163874933 ps
CPU time 1.25 seconds
Started Mar 03 12:46:17 PM PST 24
Finished Mar 03 12:46:19 PM PST 24
Peak memory 200036 kb
Host smart-a7924738-cf54-46b4-be94-173c901ae593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493655107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1493655107
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3279432003
Short name T99
Test name
Test status
Simulation time 125870217 ps
CPU time 1.22 seconds
Started Mar 03 12:46:12 PM PST 24
Finished Mar 03 12:46:15 PM PST 24
Peak memory 200124 kb
Host smart-6736014e-8b36-4eb3-9c0b-3caaed97e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279432003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3279432003
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1623873328
Short name T483
Test name
Test status
Simulation time 6328500151 ps
CPU time 26.06 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:48 PM PST 24
Peak memory 200172 kb
Host smart-c18437c6-06c4-4cfa-8ffe-897ff0e48ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623873328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1623873328
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.4067962786
Short name T146
Test name
Test status
Simulation time 356250923 ps
CPU time 2.32 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 199928 kb
Host smart-50293752-0e61-4c61-9600-a71e5e77a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067962786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.4067962786
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.758720328
Short name T68
Test name
Test status
Simulation time 98655137 ps
CPU time 0.9 seconds
Started Mar 03 12:46:18 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 200016 kb
Host smart-264b1028-13ce-47dd-bb10-47b150226207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758720328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.758720328
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3625421857
Short name T236
Test name
Test status
Simulation time 79615741 ps
CPU time 0.79 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 199916 kb
Host smart-de0247c9-a07b-4be3-a270-4d9e40d3d5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625421857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3625421857
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2300298505
Short name T394
Test name
Test status
Simulation time 1232166148 ps
CPU time 5.65 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:23 PM PST 24
Peak memory 218652 kb
Host smart-7e7f8d57-5a47-4b49-b3b0-8c7e1f246a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300298505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2300298505
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3795897750
Short name T257
Test name
Test status
Simulation time 244275131 ps
CPU time 1.06 seconds
Started Mar 03 12:46:18 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 217044 kb
Host smart-09adf08d-4493-48b8-a44c-09d550a0a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795897750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3795897750
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1092116564
Short name T353
Test name
Test status
Simulation time 190275706 ps
CPU time 0.87 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:29 PM PST 24
Peak memory 199848 kb
Host smart-6174ff41-3c34-4391-b6d5-03918207173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092116564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1092116564
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1854351852
Short name T112
Test name
Test status
Simulation time 1766833472 ps
CPU time 6.64 seconds
Started Mar 03 12:46:17 PM PST 24
Finished Mar 03 12:46:24 PM PST 24
Peak memory 200212 kb
Host smart-61202da3-3a22-4b8f-9962-4f3cd20620a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854351852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1854351852
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2463468173
Short name T471
Test name
Test status
Simulation time 152569410 ps
CPU time 1.07 seconds
Started Mar 03 12:46:23 PM PST 24
Finished Mar 03 12:46:24 PM PST 24
Peak memory 199860 kb
Host smart-632e4fa1-00a9-4d89-9328-005c26406833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463468173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2463468173
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3857492199
Short name T245
Test name
Test status
Simulation time 232568919 ps
CPU time 1.56 seconds
Started Mar 03 12:46:19 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 200188 kb
Host smart-fc0755d5-c350-43d2-8a1a-c4c59be2b55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857492199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3857492199
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2146123753
Short name T94
Test name
Test status
Simulation time 11873544749 ps
CPU time 46.09 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:47:16 PM PST 24
Peak memory 199328 kb
Host smart-b611a147-97b1-4426-9cf0-5ec893765dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146123753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2146123753
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1108167065
Short name T497
Test name
Test status
Simulation time 115997870 ps
CPU time 1.53 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 199860 kb
Host smart-1e9df4a5-c521-474d-a3c6-413872557489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108167065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1108167065
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2342842080
Short name T449
Test name
Test status
Simulation time 152355946 ps
CPU time 1.02 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:31 PM PST 24
Peak memory 199284 kb
Host smart-e3599480-de9b-4b76-a5ba-8c067ca63483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342842080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2342842080
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2046633523
Short name T388
Test name
Test status
Simulation time 73493952 ps
CPU time 0.78 seconds
Started Mar 03 12:45:47 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 199808 kb
Host smart-054dd00b-a9c8-4581-a4f5-b188b921d2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046633523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2046633523
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.659373877
Short name T451
Test name
Test status
Simulation time 1229449741 ps
CPU time 6.51 seconds
Started Mar 03 12:45:34 PM PST 24
Finished Mar 03 12:45:40 PM PST 24
Peak memory 229240 kb
Host smart-6f8ed477-069a-4b04-94af-466bb4e3c516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659373877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.659373877
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.148698395
Short name T273
Test name
Test status
Simulation time 248033099 ps
CPU time 1.05 seconds
Started Mar 03 12:45:43 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 217044 kb
Host smart-ed093685-e68c-4f75-b83b-d33b8d4a3c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148698395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.148698395
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2756561093
Short name T405
Test name
Test status
Simulation time 140105668 ps
CPU time 0.91 seconds
Started Mar 03 12:45:41 PM PST 24
Finished Mar 03 12:45:43 PM PST 24
Peak memory 199660 kb
Host smart-ce966716-6149-493f-8007-329684c107db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756561093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2756561093
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3240238550
Short name T454
Test name
Test status
Simulation time 1808330461 ps
CPU time 7.16 seconds
Started Mar 03 12:45:40 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 200232 kb
Host smart-6f32d7dc-caf4-454a-8cb7-e2796294ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240238550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3240238550
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.548794747
Short name T66
Test name
Test status
Simulation time 16497793532 ps
CPU time 31.09 seconds
Started Mar 03 12:45:48 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 216776 kb
Host smart-4a8c2cfc-2312-4539-817d-07ac1d7be086
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548794747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.548794747
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2995290588
Short name T506
Test name
Test status
Simulation time 147332902 ps
CPU time 1.11 seconds
Started Mar 03 12:45:42 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 199916 kb
Host smart-1efdef69-fec7-41b6-a152-379e1354804b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995290588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2995290588
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1446049021
Short name T125
Test name
Test status
Simulation time 253064760 ps
CPU time 1.58 seconds
Started Mar 03 12:45:29 PM PST 24
Finished Mar 03 12:45:31 PM PST 24
Peak memory 200172 kb
Host smart-37e25202-33be-4274-93ad-741fc8b1853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446049021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1446049021
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.315385101
Short name T442
Test name
Test status
Simulation time 218083252 ps
CPU time 1.29 seconds
Started Mar 03 12:45:43 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 199752 kb
Host smart-99fbb91d-5f32-4060-a234-0df50c8d6dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315385101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.315385101
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3060856010
Short name T333
Test name
Test status
Simulation time 357065661 ps
CPU time 2.22 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:53 PM PST 24
Peak memory 200212 kb
Host smart-90cce666-dadf-4fe3-8c62-31dfc2da893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060856010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3060856010
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3338959108
Short name T135
Test name
Test status
Simulation time 175659992 ps
CPU time 1.4 seconds
Started Mar 03 12:45:36 PM PST 24
Finished Mar 03 12:45:38 PM PST 24
Peak memory 200260 kb
Host smart-71bd8026-4d51-4888-8592-248c1c3bc77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338959108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3338959108
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.15536300
Short name T62
Test name
Test status
Simulation time 53362451 ps
CPU time 0.69 seconds
Started Mar 03 12:46:19 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 199864 kb
Host smart-4828860c-d3c8-42e2-bf6a-011d3d1a34c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15536300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.15536300
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4123679921
Short name T261
Test name
Test status
Simulation time 2366891229 ps
CPU time 8.62 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:39 PM PST 24
Peak memory 221392 kb
Host smart-13bb197a-0120-4e82-8321-f13f5bf6e6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123679921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4123679921
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3177512904
Short name T65
Test name
Test status
Simulation time 244488979 ps
CPU time 1.06 seconds
Started Mar 03 12:46:11 PM PST 24
Finished Mar 03 12:46:14 PM PST 24
Peak memory 217048 kb
Host smart-62006858-e1ba-40e7-9fd9-c05f72e8274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177512904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3177512904
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3313723183
Short name T397
Test name
Test status
Simulation time 159439378 ps
CPU time 0.84 seconds
Started Mar 03 12:46:23 PM PST 24
Finished Mar 03 12:46:24 PM PST 24
Peak memory 199824 kb
Host smart-fd971f19-42e7-4bdb-83e2-09ed6a9a39f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313723183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3313723183
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.4186084297
Short name T280
Test name
Test status
Simulation time 936044930 ps
CPU time 4.61 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:35 PM PST 24
Peak memory 200136 kb
Host smart-dfdeb32e-7fc6-4542-8352-dc9259da530a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186084297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4186084297
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1308130725
Short name T278
Test name
Test status
Simulation time 176495433 ps
CPU time 1.18 seconds
Started Mar 03 12:46:32 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 200008 kb
Host smart-573faa3d-225e-414f-a9a1-ab6e1aaa03cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308130725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1308130725
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2210431975
Short name T97
Test name
Test status
Simulation time 112737039 ps
CPU time 1.22 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 200192 kb
Host smart-13d99a56-341b-44df-8686-127f4aaf8ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210431975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2210431975
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.368950846
Short name T243
Test name
Test status
Simulation time 14843851431 ps
CPU time 48.84 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:47:19 PM PST 24
Peak memory 199680 kb
Host smart-73d692b9-81ad-41af-9fa8-ede01a0cf8b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368950846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.368950846
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1894964146
Short name T370
Test name
Test status
Simulation time 115939430 ps
CPU time 1.42 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 199972 kb
Host smart-ed781a74-c8e1-409b-a4e2-e727bd1eded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894964146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1894964146
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2206092287
Short name T530
Test name
Test status
Simulation time 191374587 ps
CPU time 1.26 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:29 PM PST 24
Peak memory 200044 kb
Host smart-e26f2664-361e-465c-b76f-1f3ae247b1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206092287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2206092287
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2442354686
Short name T341
Test name
Test status
Simulation time 63914459 ps
CPU time 0.82 seconds
Started Mar 03 12:46:21 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 199952 kb
Host smart-8e9cf799-bdd0-40d1-b234-4fbc8130434d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442354686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2442354686
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3633661758
Short name T24
Test name
Test status
Simulation time 1230214888 ps
CPU time 5.58 seconds
Started Mar 03 12:46:21 PM PST 24
Finished Mar 03 12:46:26 PM PST 24
Peak memory 221072 kb
Host smart-04616458-d4e3-4a38-9b3c-7fc8a8641905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633661758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3633661758
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.489610022
Short name T408
Test name
Test status
Simulation time 244821607 ps
CPU time 1.1 seconds
Started Mar 03 12:46:32 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 217040 kb
Host smart-53359184-9c2e-4591-ab09-e0efd514c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489610022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.489610022
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1820847784
Short name T13
Test name
Test status
Simulation time 77569048 ps
CPU time 0.8 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 199760 kb
Host smart-8bd68bad-7d4e-4c17-9c27-53bf20670720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820847784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1820847784
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2262665333
Short name T103
Test name
Test status
Simulation time 1865330132 ps
CPU time 8.28 seconds
Started Mar 03 12:46:09 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 200120 kb
Host smart-99ee90f3-b2e6-471b-a4e0-1484489f2adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262665333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2262665333
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2499250617
Short name T510
Test name
Test status
Simulation time 178331451 ps
CPU time 1.2 seconds
Started Mar 03 12:46:23 PM PST 24
Finished Mar 03 12:46:25 PM PST 24
Peak memory 200020 kb
Host smart-58cb03ab-60fc-40e9-bbfd-a984d2ab5fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499250617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2499250617
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3903299034
Short name T262
Test name
Test status
Simulation time 120373584 ps
CPU time 1.3 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:17 PM PST 24
Peak memory 200136 kb
Host smart-248ff2a5-0b14-452b-9a2c-dffd4cc9c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903299034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3903299034
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3294181540
Short name T429
Test name
Test status
Simulation time 7626962138 ps
CPU time 27.49 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:49 PM PST 24
Peak memory 200180 kb
Host smart-f99dbb6c-04b1-48ce-be8a-2803b9224cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294181540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3294181540
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3788329113
Short name T255
Test name
Test status
Simulation time 141494400 ps
CPU time 1.76 seconds
Started Mar 03 12:46:15 PM PST 24
Finished Mar 03 12:46:17 PM PST 24
Peak memory 208096 kb
Host smart-262690df-cbaa-477a-b037-22302373100b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788329113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3788329113
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.4198797693
Short name T320
Test name
Test status
Simulation time 239567960 ps
CPU time 1.55 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:24 PM PST 24
Peak memory 200088 kb
Host smart-b2fdafd1-8f93-4ede-8eae-1ae7e195fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198797693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.4198797693
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2862853676
Short name T351
Test name
Test status
Simulation time 2376048210 ps
CPU time 9.4 seconds
Started Mar 03 12:46:23 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 217284 kb
Host smart-2662b36e-7a56-43ae-8151-463dd9228321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862853676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2862853676
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2836674206
Short name T407
Test name
Test status
Simulation time 244191496 ps
CPU time 1.15 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:24 PM PST 24
Peak memory 216956 kb
Host smart-6cc27a66-2f66-4cf3-855b-d128a7b06ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836674206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2836674206
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.787663221
Short name T304
Test name
Test status
Simulation time 201489723 ps
CPU time 1 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:23 PM PST 24
Peak memory 199824 kb
Host smart-1dec140e-5424-44ba-a2ec-c034582856e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787663221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.787663221
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3513797727
Short name T212
Test name
Test status
Simulation time 1993127024 ps
CPU time 7.31 seconds
Started Mar 03 12:46:24 PM PST 24
Finished Mar 03 12:46:31 PM PST 24
Peak memory 200196 kb
Host smart-212b0f3a-8a00-4a43-9141-8cb1557fde5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513797727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3513797727
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3459020264
Short name T210
Test name
Test status
Simulation time 167198240 ps
CPU time 1.21 seconds
Started Mar 03 12:46:16 PM PST 24
Finished Mar 03 12:46:18 PM PST 24
Peak memory 200032 kb
Host smart-9ca9b4af-ff70-4f30-b68e-98e092bfe009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459020264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3459020264
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3711037975
Short name T164
Test name
Test status
Simulation time 128665142 ps
CPU time 1.25 seconds
Started Mar 03 12:46:26 PM PST 24
Finished Mar 03 12:46:28 PM PST 24
Peak memory 200036 kb
Host smart-f2e9f864-4d20-46a7-904e-d64baabe7f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711037975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3711037975
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.822559900
Short name T251
Test name
Test status
Simulation time 129332718 ps
CPU time 1.6 seconds
Started Mar 03 12:46:27 PM PST 24
Finished Mar 03 12:46:29 PM PST 24
Peak memory 199824 kb
Host smart-6c462cd5-a9f7-48ff-831d-8ca2475bc378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822559900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.822559900
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1604807655
Short name T179
Test name
Test status
Simulation time 156870196 ps
CPU time 1.11 seconds
Started Mar 03 12:46:22 PM PST 24
Finished Mar 03 12:46:23 PM PST 24
Peak memory 199952 kb
Host smart-36895387-da56-4be0-9818-07d2b42dfdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604807655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1604807655
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1096762576
Short name T209
Test name
Test status
Simulation time 74452747 ps
CPU time 0.78 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:31 PM PST 24
Peak memory 199936 kb
Host smart-9f4d5b15-64e1-47a7-99d8-12101a095fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096762576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1096762576
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3525284390
Short name T293
Test name
Test status
Simulation time 1217921989 ps
CPU time 5.36 seconds
Started Mar 03 12:46:27 PM PST 24
Finished Mar 03 12:46:32 PM PST 24
Peak memory 216952 kb
Host smart-63799faa-93eb-4866-8b99-fa974fb1cebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525284390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3525284390
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2224105487
Short name T45
Test name
Test status
Simulation time 252458479 ps
CPU time 1.06 seconds
Started Mar 03 12:46:49 PM PST 24
Finished Mar 03 12:46:50 PM PST 24
Peak memory 217120 kb
Host smart-f68bd586-b4c6-438f-bd6d-460c2989ba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224105487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2224105487
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3842696610
Short name T14
Test name
Test status
Simulation time 158943868 ps
CPU time 0.87 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 199748 kb
Host smart-d92fd379-8462-409d-859e-add7493291ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842696610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3842696610
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.802570051
Short name T105
Test name
Test status
Simulation time 1632118372 ps
CPU time 5.81 seconds
Started Mar 03 12:46:19 PM PST 24
Finished Mar 03 12:46:25 PM PST 24
Peak memory 200100 kb
Host smart-512abf89-5b44-48ab-a34a-646927c05638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802570051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.802570051
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1108836610
Short name T276
Test name
Test status
Simulation time 188536561 ps
CPU time 1.19 seconds
Started Mar 03 12:46:21 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 200000 kb
Host smart-40525fa4-6125-45bc-99b0-98aaf913412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108836610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1108836610
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2001608317
Short name T521
Test name
Test status
Simulation time 117246696 ps
CPU time 1.12 seconds
Started Mar 03 12:46:19 PM PST 24
Finished Mar 03 12:46:20 PM PST 24
Peak memory 200128 kb
Host smart-21682139-07a8-49c3-bcae-97b8b4a3db3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001608317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2001608317
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3559135450
Short name T283
Test name
Test status
Simulation time 8955593609 ps
CPU time 43.02 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:47:13 PM PST 24
Peak memory 200492 kb
Host smart-951b2f5a-3da9-4fbc-8648-3c2439c7fbf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559135450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3559135450
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.416379407
Short name T248
Test name
Test status
Simulation time 136448010 ps
CPU time 1.7 seconds
Started Mar 03 12:46:32 PM PST 24
Finished Mar 03 12:46:34 PM PST 24
Peak memory 199972 kb
Host smart-0379195c-8eba-4efe-85b7-c92b6fd99517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416379407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.416379407
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1096438638
Short name T410
Test name
Test status
Simulation time 104664089 ps
CPU time 0.93 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 200036 kb
Host smart-a31147f2-5e79-4b4f-be92-ea965eeb4cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096438638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1096438638
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1512474338
Short name T64
Test name
Test status
Simulation time 76238966 ps
CPU time 0.81 seconds
Started Mar 03 12:46:29 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 199932 kb
Host smart-5e3d6039-9309-43d1-b9b2-496866a3d294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512474338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1512474338
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2270582482
Short name T428
Test name
Test status
Simulation time 2176876303 ps
CPU time 8.95 seconds
Started Mar 03 12:46:26 PM PST 24
Finished Mar 03 12:46:35 PM PST 24
Peak memory 218116 kb
Host smart-dd95b6e4-f823-45cb-89d8-8ae60834960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270582482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2270582482
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1039778748
Short name T285
Test name
Test status
Simulation time 243742501 ps
CPU time 1.11 seconds
Started Mar 03 12:46:35 PM PST 24
Finished Mar 03 12:46:36 PM PST 24
Peak memory 217072 kb
Host smart-bfd5a2ae-6e59-4280-a0b5-852efea4bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039778748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1039778748
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3803632453
Short name T419
Test name
Test status
Simulation time 202523747 ps
CPU time 0.93 seconds
Started Mar 03 12:46:34 PM PST 24
Finished Mar 03 12:46:35 PM PST 24
Peak memory 199808 kb
Host smart-8a28ad93-68a5-44f8-9f3b-97975c2fa50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803632453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3803632453
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.965949552
Short name T367
Test name
Test status
Simulation time 1213120236 ps
CPU time 4.7 seconds
Started Mar 03 12:46:36 PM PST 24
Finished Mar 03 12:46:41 PM PST 24
Peak memory 200192 kb
Host smart-7803788a-0290-4c0f-aff4-ee7ec0a98f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965949552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.965949552
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.727925382
Short name T178
Test name
Test status
Simulation time 182399532 ps
CPU time 1.16 seconds
Started Mar 03 12:46:29 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 200288 kb
Host smart-22dfcda2-ec8e-47d5-8151-0e936967a3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727925382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.727925382
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.451875100
Short name T378
Test name
Test status
Simulation time 202041238 ps
CPU time 1.43 seconds
Started Mar 03 12:46:20 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 200044 kb
Host smart-dff0e862-c038-4cfe-a63e-cce108b72ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451875100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.451875100
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2473146526
Short name T154
Test name
Test status
Simulation time 2927925607 ps
CPU time 12.91 seconds
Started Mar 03 12:46:32 PM PST 24
Finished Mar 03 12:46:45 PM PST 24
Peak memory 200276 kb
Host smart-31a286f8-375e-48ec-8727-e73e003fbb49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473146526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2473146526
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3490793669
Short name T126
Test name
Test status
Simulation time 411575155 ps
CPU time 2.29 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:31 PM PST 24
Peak memory 208052 kb
Host smart-aa1d818e-e463-48c0-90e2-e2f813c072dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490793669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3490793669
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.433554982
Short name T327
Test name
Test status
Simulation time 103320341 ps
CPU time 0.98 seconds
Started Mar 03 12:46:32 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 199972 kb
Host smart-c7223fcd-eb7b-4cc4-939e-d1a21412b87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433554982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.433554982
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2156731823
Short name T482
Test name
Test status
Simulation time 80027134 ps
CPU time 0.8 seconds
Started Mar 03 12:46:29 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 199952 kb
Host smart-dc26d0a6-779c-46d2-b97c-d3c79c862ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156731823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2156731823
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1319893385
Short name T8
Test name
Test status
Simulation time 1219577527 ps
CPU time 6.28 seconds
Started Mar 03 12:46:35 PM PST 24
Finished Mar 03 12:46:41 PM PST 24
Peak memory 216976 kb
Host smart-d7e122d4-f3d3-4bdd-a1f0-519b7868edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319893385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1319893385
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1751451894
Short name T291
Test name
Test status
Simulation time 244401113 ps
CPU time 1.05 seconds
Started Mar 03 12:46:31 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 216964 kb
Host smart-02927791-3156-46df-95f5-579a1b83dd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751451894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1751451894
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2384718405
Short name T426
Test name
Test status
Simulation time 160911398 ps
CPU time 0.89 seconds
Started Mar 03 12:46:32 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 199840 kb
Host smart-ecfcffa8-4377-416e-aaa8-d89c26c82523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384718405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2384718405
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2835155429
Short name T331
Test name
Test status
Simulation time 1258203963 ps
CPU time 5.04 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:35 PM PST 24
Peak memory 200112 kb
Host smart-fb21e47b-28bd-4b99-bd7c-4f94c149acf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835155429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2835155429
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3131173943
Short name T326
Test name
Test status
Simulation time 162915301 ps
CPU time 1.29 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:31 PM PST 24
Peak memory 199944 kb
Host smart-0c54ca51-5a88-4fd1-9953-9065dd79f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131173943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3131173943
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3433553690
Short name T336
Test name
Test status
Simulation time 243992921 ps
CPU time 1.51 seconds
Started Mar 03 12:46:19 PM PST 24
Finished Mar 03 12:46:21 PM PST 24
Peak memory 200128 kb
Host smart-96f18776-5b9d-41b8-abde-b5aea8a1aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433553690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3433553690
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3790531503
Short name T431
Test name
Test status
Simulation time 4096937185 ps
CPU time 18.72 seconds
Started Mar 03 12:46:27 PM PST 24
Finished Mar 03 12:46:46 PM PST 24
Peak memory 200204 kb
Host smart-1905052a-1ccf-452d-bd80-007571fa051e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790531503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3790531503
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2811204873
Short name T196
Test name
Test status
Simulation time 472127628 ps
CPU time 2.72 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:41 PM PST 24
Peak memory 199972 kb
Host smart-6d95a409-a5b8-44a4-9565-f274b539d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811204873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2811204873
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1738213219
Short name T490
Test name
Test status
Simulation time 170539490 ps
CPU time 1.31 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:32 PM PST 24
Peak memory 200072 kb
Host smart-10e96442-a35b-4cab-bba5-c4c3e0c329b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738213219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1738213219
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2893368580
Short name T275
Test name
Test status
Simulation time 71786806 ps
CPU time 0.75 seconds
Started Mar 03 12:46:27 PM PST 24
Finished Mar 03 12:46:28 PM PST 24
Peak memory 199936 kb
Host smart-4f59f4b8-71f2-45ff-ad3c-28aebcdc4f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893368580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2893368580
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.317553812
Short name T452
Test name
Test status
Simulation time 1227415718 ps
CPU time 5.3 seconds
Started Mar 03 12:46:35 PM PST 24
Finished Mar 03 12:46:41 PM PST 24
Peak memory 221696 kb
Host smart-9a1a30c1-db5a-4f71-9c5f-4b455d8631b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317553812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.317553812
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3956756516
Short name T152
Test name
Test status
Simulation time 244539649 ps
CPU time 1.2 seconds
Started Mar 03 12:46:24 PM PST 24
Finished Mar 03 12:46:26 PM PST 24
Peak memory 216964 kb
Host smart-7e197415-a0c8-4b1a-8d55-baec6ac0311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956756516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3956756516
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2864820747
Short name T322
Test name
Test status
Simulation time 209068140 ps
CPU time 0.88 seconds
Started Mar 03 12:46:26 PM PST 24
Finished Mar 03 12:46:27 PM PST 24
Peak memory 199760 kb
Host smart-de975e9b-bc5c-4e97-9058-5040c3f6f22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864820747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2864820747
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1281327631
Short name T44
Test name
Test status
Simulation time 1505123194 ps
CPU time 5.77 seconds
Started Mar 03 12:46:26 PM PST 24
Finished Mar 03 12:46:32 PM PST 24
Peak memory 200196 kb
Host smart-fdd3d273-d93a-4c56-9641-0fb686fe3ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281327631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1281327631
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1985725645
Short name T425
Test name
Test status
Simulation time 103448464 ps
CPU time 1 seconds
Started Mar 03 12:46:29 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 200036 kb
Host smart-a375e7fb-91f4-4851-9fa2-00be9f126a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985725645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1985725645
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.351299130
Short name T53
Test name
Test status
Simulation time 191370380 ps
CPU time 1.45 seconds
Started Mar 03 12:46:27 PM PST 24
Finished Mar 03 12:46:29 PM PST 24
Peak memory 200128 kb
Host smart-bff1c300-9b31-43c0-a84e-db2c2240ee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351299130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.351299130
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.788158286
Short name T231
Test name
Test status
Simulation time 7891968272 ps
CPU time 31.61 seconds
Started Mar 03 12:46:29 PM PST 24
Finished Mar 03 12:47:01 PM PST 24
Peak memory 209044 kb
Host smart-f82fea31-d30f-445d-8feb-82a8b39b0797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788158286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.788158286
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.4106500463
Short name T141
Test name
Test status
Simulation time 246075111 ps
CPU time 1.78 seconds
Started Mar 03 12:46:34 PM PST 24
Finished Mar 03 12:46:36 PM PST 24
Peak memory 199908 kb
Host smart-710498cb-5cfa-4444-ba38-a1e9c14d92dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106500463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4106500463
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.920730557
Short name T132
Test name
Test status
Simulation time 205653416 ps
CPU time 1.34 seconds
Started Mar 03 12:46:29 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 200020 kb
Host smart-a49079bc-4bfc-4526-99d6-fe429814afae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920730557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.920730557
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2349157925
Short name T187
Test name
Test status
Simulation time 71830132 ps
CPU time 0.77 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:31 PM PST 24
Peak memory 199936 kb
Host smart-b25b527d-442b-4e9d-9fb6-75405d1ec14b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349157925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2349157925
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1090418759
Short name T204
Test name
Test status
Simulation time 1231504275 ps
CPU time 5.65 seconds
Started Mar 03 12:46:32 PM PST 24
Finished Mar 03 12:46:38 PM PST 24
Peak memory 217028 kb
Host smart-3f9dce7e-2b5a-4484-86f0-2115113639d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090418759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1090418759
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.640459107
Short name T380
Test name
Test status
Simulation time 244366373 ps
CPU time 1.09 seconds
Started Mar 03 12:46:24 PM PST 24
Finished Mar 03 12:46:25 PM PST 24
Peak memory 217032 kb
Host smart-fb7321fb-3c0a-44e3-8d11-3076db2bed8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640459107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.640459107
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3834933745
Short name T298
Test name
Test status
Simulation time 163124722 ps
CPU time 0.86 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:29 PM PST 24
Peak memory 199844 kb
Host smart-96825816-656b-4813-bf14-3e563cac7caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834933745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3834933745
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3972387745
Short name T153
Test name
Test status
Simulation time 1248332153 ps
CPU time 5.15 seconds
Started Mar 03 12:46:31 PM PST 24
Finished Mar 03 12:46:36 PM PST 24
Peak memory 200256 kb
Host smart-7a251d85-3cf5-403b-b473-809a3978c8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972387745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3972387745
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3290021703
Short name T496
Test name
Test status
Simulation time 176743689 ps
CPU time 1.17 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:29 PM PST 24
Peak memory 199992 kb
Host smart-b33b5e8e-b3a0-4ad6-b155-6b4aaf7e6f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290021703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3290021703
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.4262966662
Short name T349
Test name
Test status
Simulation time 257690639 ps
CPU time 1.59 seconds
Started Mar 03 12:46:40 PM PST 24
Finished Mar 03 12:46:42 PM PST 24
Peak memory 200188 kb
Host smart-695df968-04d4-4686-9b82-ffb41ba41380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262966662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4262966662
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2768174806
Short name T374
Test name
Test status
Simulation time 8394921767 ps
CPU time 27.27 seconds
Started Mar 03 12:46:37 PM PST 24
Finished Mar 03 12:47:05 PM PST 24
Peak memory 200252 kb
Host smart-c4153c81-8739-4a6e-b2a8-6e495b0f3dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768174806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2768174806
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3993815597
Short name T352
Test name
Test status
Simulation time 124536568 ps
CPU time 1.45 seconds
Started Mar 03 12:46:42 PM PST 24
Finished Mar 03 12:46:43 PM PST 24
Peak memory 199832 kb
Host smart-cfc6be20-823c-4e85-a3c0-80a330a682a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993815597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3993815597
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1500390210
Short name T534
Test name
Test status
Simulation time 217745868 ps
CPU time 1.37 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:29 PM PST 24
Peak memory 200000 kb
Host smart-4c3f7c56-ee96-4916-a979-a0fe1b9b3d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500390210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1500390210
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3085736918
Short name T411
Test name
Test status
Simulation time 51706721 ps
CPU time 0.7 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:29 PM PST 24
Peak memory 199936 kb
Host smart-ccac267c-4f1e-4c35-9853-ae648b6ac1a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085736918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3085736918
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2630716896
Short name T30
Test name
Test status
Simulation time 2370141843 ps
CPU time 8.7 seconds
Started Mar 03 12:46:33 PM PST 24
Finished Mar 03 12:46:47 PM PST 24
Peak memory 217712 kb
Host smart-7a34d413-f42c-43fe-97c2-d5718b1eba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630716896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2630716896
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.793025068
Short name T332
Test name
Test status
Simulation time 244612210 ps
CPU time 1.16 seconds
Started Mar 03 12:46:36 PM PST 24
Finished Mar 03 12:46:38 PM PST 24
Peak memory 217156 kb
Host smart-bca3097d-b3b4-4c79-a60a-4161e1e33eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793025068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.793025068
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1529443478
Short name T340
Test name
Test status
Simulation time 205582226 ps
CPU time 0.92 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 199828 kb
Host smart-f378a106-c21f-4b9d-84ad-903970ec0ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529443478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1529443478
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3941082806
Short name T337
Test name
Test status
Simulation time 1579375606 ps
CPU time 5.34 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:35 PM PST 24
Peak memory 200176 kb
Host smart-13cda997-501b-4124-be7e-8e046e5daddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941082806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3941082806
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1882218622
Short name T180
Test name
Test status
Simulation time 175357630 ps
CPU time 1.21 seconds
Started Mar 03 12:46:33 PM PST 24
Finished Mar 03 12:46:34 PM PST 24
Peak memory 200040 kb
Host smart-9b0f38e3-b541-47f8-bb5d-0dc38c6d2a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882218622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1882218622
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.673188516
Short name T413
Test name
Test status
Simulation time 192858734 ps
CPU time 1.43 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 200152 kb
Host smart-d4839934-4bd0-49c0-87ad-8b24be673ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673188516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.673188516
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1796559976
Short name T173
Test name
Test status
Simulation time 5885211503 ps
CPU time 23.67 seconds
Started Mar 03 12:46:34 PM PST 24
Finished Mar 03 12:46:58 PM PST 24
Peak memory 208404 kb
Host smart-859184b3-998d-43c6-b356-e6e6ff285e34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796559976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1796559976
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3813389513
Short name T266
Test name
Test status
Simulation time 347610518 ps
CPU time 2.52 seconds
Started Mar 03 12:46:41 PM PST 24
Finished Mar 03 12:46:43 PM PST 24
Peak memory 199956 kb
Host smart-8d9fdd60-8e59-4f0f-b7e3-6b875ecdeb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813389513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3813389513
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3950148875
Short name T507
Test name
Test status
Simulation time 123403255 ps
CPU time 0.98 seconds
Started Mar 03 12:46:35 PM PST 24
Finished Mar 03 12:46:36 PM PST 24
Peak memory 199892 kb
Host smart-042805b1-db98-48a3-8e3e-f7040ddc7060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950148875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3950148875
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3198810654
Short name T271
Test name
Test status
Simulation time 62867339 ps
CPU time 0.73 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:29 PM PST 24
Peak memory 199936 kb
Host smart-dc0e6996-5e38-4557-8a58-88063eede4ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198810654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3198810654
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.707900563
Short name T290
Test name
Test status
Simulation time 2354222002 ps
CPU time 9.44 seconds
Started Mar 03 12:46:42 PM PST 24
Finished Mar 03 12:46:52 PM PST 24
Peak memory 221760 kb
Host smart-96513327-def6-4211-a006-6a4f521bde01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707900563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.707900563
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2087321037
Short name T435
Test name
Test status
Simulation time 244899269 ps
CPU time 1.14 seconds
Started Mar 03 12:46:28 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 217036 kb
Host smart-1fe3422e-89b2-483d-83bd-9e5de953bb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087321037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2087321037
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2713084188
Short name T144
Test name
Test status
Simulation time 135025476 ps
CPU time 0.81 seconds
Started Mar 03 12:46:32 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 199824 kb
Host smart-4d0fc23a-c5d0-473f-8d53-cd628749a60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713084188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2713084188
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.426664689
Short name T415
Test name
Test status
Simulation time 814194044 ps
CPU time 3.89 seconds
Started Mar 03 12:46:34 PM PST 24
Finished Mar 03 12:46:38 PM PST 24
Peak memory 199992 kb
Host smart-2a262d34-c562-4dee-a5b0-f250ecc429a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426664689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.426664689
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.286216291
Short name T203
Test name
Test status
Simulation time 186318206 ps
CPU time 1.21 seconds
Started Mar 03 12:46:33 PM PST 24
Finished Mar 03 12:46:34 PM PST 24
Peak memory 200032 kb
Host smart-cfa7f8f8-d454-41d6-aaa9-a12ec8f9d6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286216291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.286216291
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3359114579
Short name T216
Test name
Test status
Simulation time 124903000 ps
CPU time 1.34 seconds
Started Mar 03 12:46:35 PM PST 24
Finished Mar 03 12:46:37 PM PST 24
Peak memory 199976 kb
Host smart-f97dcdfb-5111-48c2-b46c-2ef1bdb84697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359114579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3359114579
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3265144367
Short name T423
Test name
Test status
Simulation time 12087254026 ps
CPU time 44.76 seconds
Started Mar 03 12:46:33 PM PST 24
Finished Mar 03 12:47:18 PM PST 24
Peak memory 210548 kb
Host smart-b7c2e496-a805-438e-bf53-c9e1a6d2c9de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265144367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3265144367
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3256761586
Short name T95
Test name
Test status
Simulation time 268000530 ps
CPU time 1.81 seconds
Started Mar 03 12:46:33 PM PST 24
Finished Mar 03 12:46:35 PM PST 24
Peak memory 199756 kb
Host smart-fd79b5a7-a449-4cd8-8f14-65b469160e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256761586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3256761586
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.881181421
Short name T183
Test name
Test status
Simulation time 136606632 ps
CPU time 1.16 seconds
Started Mar 03 12:46:33 PM PST 24
Finished Mar 03 12:46:34 PM PST 24
Peak memory 200036 kb
Host smart-82581726-cf70-426a-8f0e-fceea4f67c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881181421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.881181421
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2408717782
Short name T188
Test name
Test status
Simulation time 83318068 ps
CPU time 0.81 seconds
Started Mar 03 12:45:33 PM PST 24
Finished Mar 03 12:45:34 PM PST 24
Peak memory 199936 kb
Host smart-1ba00da4-1dfa-4888-908f-0432175c6186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408717782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2408717782
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3226800861
Short name T38
Test name
Test status
Simulation time 1228130924 ps
CPU time 5.57 seconds
Started Mar 03 12:45:43 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 221512 kb
Host smart-79753868-843f-4692-827a-f88ed9cc5fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226800861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3226800861
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1787480201
Short name T540
Test name
Test status
Simulation time 246281502 ps
CPU time 1.07 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:46 PM PST 24
Peak memory 217052 kb
Host smart-6b46d0fb-7761-46bc-bd0e-ddc42ce31b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787480201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1787480201
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3992991908
Short name T239
Test name
Test status
Simulation time 161242232 ps
CPU time 0.85 seconds
Started Mar 03 12:45:38 PM PST 24
Finished Mar 03 12:45:40 PM PST 24
Peak memory 199700 kb
Host smart-1cbcb631-5d68-4acb-9d3a-b51f68ae04fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992991908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3992991908
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1276883728
Short name T542
Test name
Test status
Simulation time 1981925443 ps
CPU time 6.8 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 200176 kb
Host smart-77163392-4eb8-4063-b6b6-866fe5c7a86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276883728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1276883728
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1991867676
Short name T67
Test name
Test status
Simulation time 16691987705 ps
CPU time 26.29 seconds
Started Mar 03 12:45:48 PM PST 24
Finished Mar 03 12:46:15 PM PST 24
Peak memory 216640 kb
Host smart-1b2e15ac-345b-4d23-8535-58e3b96d0001
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991867676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1991867676
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.153550147
Short name T223
Test name
Test status
Simulation time 168113627 ps
CPU time 1.25 seconds
Started Mar 03 12:45:42 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 199920 kb
Host smart-c2cc0cbb-d64c-4a34-a513-1a0e988d20eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153550147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.153550147
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3917584221
Short name T453
Test name
Test status
Simulation time 257201209 ps
CPU time 1.61 seconds
Started Mar 03 12:45:43 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 200132 kb
Host smart-ec5d89ba-b8cf-4e9e-b7cf-fc0df2daedfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917584221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3917584221
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2409662615
Short name T69
Test name
Test status
Simulation time 16598366797 ps
CPU time 52.36 seconds
Started Mar 03 12:45:44 PM PST 24
Finished Mar 03 12:46:37 PM PST 24
Peak memory 208936 kb
Host smart-541ee1a5-dd2f-4063-9779-b9ca2d240e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409662615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2409662615
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2620716990
Short name T301
Test name
Test status
Simulation time 129152651 ps
CPU time 1.72 seconds
Started Mar 03 12:45:44 PM PST 24
Finished Mar 03 12:45:46 PM PST 24
Peak memory 199760 kb
Host smart-712eff30-9904-4126-b849-e34554e29dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620716990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2620716990
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2497302992
Short name T199
Test name
Test status
Simulation time 81782899 ps
CPU time 0.94 seconds
Started Mar 03 12:45:44 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 200004 kb
Host smart-c110080f-fff9-437c-b319-4cdaffd03872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497302992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2497302992
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3325192797
Short name T284
Test name
Test status
Simulation time 62985329 ps
CPU time 0.77 seconds
Started Mar 03 12:46:53 PM PST 24
Finished Mar 03 12:46:54 PM PST 24
Peak memory 199792 kb
Host smart-099ef1e4-29b9-4fdb-b3ff-70b9ee37bfb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325192797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3325192797
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.760733398
Short name T524
Test name
Test status
Simulation time 2350291616 ps
CPU time 8.98 seconds
Started Mar 03 12:46:35 PM PST 24
Finished Mar 03 12:46:44 PM PST 24
Peak memory 217564 kb
Host smart-9d045776-6abf-4f69-bc29-3f263da81616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760733398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.760733398
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2673737041
Short name T493
Test name
Test status
Simulation time 243821338 ps
CPU time 1.15 seconds
Started Mar 03 12:46:39 PM PST 24
Finished Mar 03 12:46:41 PM PST 24
Peak memory 217044 kb
Host smart-25f9afb5-727c-40b8-af84-35778bcf11f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673737041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2673737041
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3639459022
Short name T250
Test name
Test status
Simulation time 86373720 ps
CPU time 0.79 seconds
Started Mar 03 12:46:35 PM PST 24
Finished Mar 03 12:46:36 PM PST 24
Peak memory 199672 kb
Host smart-2fd514b2-623e-429f-bb76-4085e5eb82bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639459022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3639459022
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.191568431
Short name T475
Test name
Test status
Simulation time 1207206763 ps
CPU time 5.64 seconds
Started Mar 03 12:46:35 PM PST 24
Finished Mar 03 12:46:40 PM PST 24
Peak memory 200192 kb
Host smart-42a716e0-f87e-4b55-838a-8616268b0850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191568431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.191568431
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2763216980
Short name T142
Test name
Test status
Simulation time 157833481 ps
CPU time 1.18 seconds
Started Mar 03 12:46:34 PM PST 24
Finished Mar 03 12:46:36 PM PST 24
Peak memory 200036 kb
Host smart-002b9f35-5f7a-4e3b-acfc-a807ed0711ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763216980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2763216980
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.4259472692
Short name T531
Test name
Test status
Simulation time 194204678 ps
CPU time 1.55 seconds
Started Mar 03 12:46:35 PM PST 24
Finished Mar 03 12:46:37 PM PST 24
Peak memory 200184 kb
Host smart-d1fe5d2f-7454-40d4-8b90-fd95af756ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259472692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.4259472692
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3883626201
Short name T201
Test name
Test status
Simulation time 1404032351 ps
CPU time 6.97 seconds
Started Mar 03 12:46:36 PM PST 24
Finished Mar 03 12:46:43 PM PST 24
Peak memory 200196 kb
Host smart-106180c1-6604-4f64-82bb-9a7dfcfaceac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883626201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3883626201
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1901136026
Short name T287
Test name
Test status
Simulation time 140067747 ps
CPU time 1.81 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:32 PM PST 24
Peak memory 199724 kb
Host smart-fcf29c74-2ac3-49f0-a9ad-2b7130607f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901136026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1901136026
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.431255890
Short name T124
Test name
Test status
Simulation time 108356933 ps
CPU time 0.87 seconds
Started Mar 03 12:46:29 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 200032 kb
Host smart-21561036-385d-4c08-b675-2e6faae6f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431255890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.431255890
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.383422360
Short name T244
Test name
Test status
Simulation time 62403321 ps
CPU time 0.77 seconds
Started Mar 03 12:46:55 PM PST 24
Finished Mar 03 12:46:56 PM PST 24
Peak memory 199936 kb
Host smart-bee3bf6c-eb6e-4c52-9919-521726416740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383422360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.383422360
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.17237847
Short name T379
Test name
Test status
Simulation time 1887872518 ps
CPU time 7.52 seconds
Started Mar 03 12:46:36 PM PST 24
Finished Mar 03 12:46:43 PM PST 24
Peak memory 216988 kb
Host smart-88576962-cd56-4f32-9778-ea25c4103e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17237847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.17237847
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3513299701
Short name T182
Test name
Test status
Simulation time 245159865 ps
CPU time 1.07 seconds
Started Mar 03 12:46:40 PM PST 24
Finished Mar 03 12:46:42 PM PST 24
Peak memory 216796 kb
Host smart-1f168c05-e096-4543-a29b-a7bf31005fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513299701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3513299701
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1354619950
Short name T461
Test name
Test status
Simulation time 239033773 ps
CPU time 0.89 seconds
Started Mar 03 12:46:39 PM PST 24
Finished Mar 03 12:46:40 PM PST 24
Peak memory 199836 kb
Host smart-1a18794a-d05e-4a0c-841d-0d3ac41cff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354619950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1354619950
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2784111622
Short name T286
Test name
Test status
Simulation time 1721545884 ps
CPU time 6.61 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:45 PM PST 24
Peak memory 200236 kb
Host smart-63ba362c-14ad-4f9c-b13e-baaab9a94d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784111622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2784111622
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1524574776
Short name T46
Test name
Test status
Simulation time 178897531 ps
CPU time 1.17 seconds
Started Mar 03 12:46:52 PM PST 24
Finished Mar 03 12:46:53 PM PST 24
Peak memory 199944 kb
Host smart-a6dadd9c-e830-418c-a969-e3748fdd97ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524574776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1524574776
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2883854324
Short name T52
Test name
Test status
Simulation time 221899991 ps
CPU time 1.33 seconds
Started Mar 03 12:46:45 PM PST 24
Finished Mar 03 12:46:47 PM PST 24
Peak memory 200140 kb
Host smart-f2446443-ba3b-4478-bf33-6477e2eda33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883854324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2883854324
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3946218878
Short name T279
Test name
Test status
Simulation time 8382977328 ps
CPU time 31.69 seconds
Started Mar 03 12:46:37 PM PST 24
Finished Mar 03 12:47:09 PM PST 24
Peak memory 208428 kb
Host smart-6c329852-1e4b-4a6e-a701-2ea530b8327b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946218878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3946218878
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2231769260
Short name T358
Test name
Test status
Simulation time 135789292 ps
CPU time 1.8 seconds
Started Mar 03 12:46:40 PM PST 24
Finished Mar 03 12:46:42 PM PST 24
Peak memory 199840 kb
Host smart-474c515d-2bbc-4015-9eff-da00f132de68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231769260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2231769260
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3030444570
Short name T207
Test name
Test status
Simulation time 154661118 ps
CPU time 1.25 seconds
Started Mar 03 12:46:43 PM PST 24
Finished Mar 03 12:46:45 PM PST 24
Peak memory 200116 kb
Host smart-2b74c4ee-8f43-4457-9703-9fc0bae38b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030444570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3030444570
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3006496822
Short name T325
Test name
Test status
Simulation time 65359822 ps
CPU time 0.78 seconds
Started Mar 03 12:46:40 PM PST 24
Finished Mar 03 12:46:41 PM PST 24
Peak memory 199920 kb
Host smart-53d23fcd-9458-4359-8c1d-101b54429556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006496822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3006496822
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.478667167
Short name T443
Test name
Test status
Simulation time 2175081583 ps
CPU time 8.26 seconds
Started Mar 03 12:46:36 PM PST 24
Finished Mar 03 12:46:45 PM PST 24
Peak memory 217480 kb
Host smart-a2d71704-af61-4656-9d6f-c5a087c3139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478667167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.478667167
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1771321548
Short name T511
Test name
Test status
Simulation time 244747809 ps
CPU time 1.16 seconds
Started Mar 03 12:46:39 PM PST 24
Finished Mar 03 12:46:41 PM PST 24
Peak memory 217164 kb
Host smart-4923c62c-2d78-4944-a0ad-0f93369f4f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771321548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1771321548
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1471753898
Short name T361
Test name
Test status
Simulation time 174908027 ps
CPU time 0.88 seconds
Started Mar 03 12:46:53 PM PST 24
Finished Mar 03 12:46:54 PM PST 24
Peak memory 199696 kb
Host smart-4c275ea9-d4ea-42f6-b8b0-c67d49c5bd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471753898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1471753898
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1917809747
Short name T161
Test name
Test status
Simulation time 104447364 ps
CPU time 0.97 seconds
Started Mar 03 12:46:39 PM PST 24
Finished Mar 03 12:46:40 PM PST 24
Peak memory 200040 kb
Host smart-9feb928d-3fe9-46df-80f3-828d1f982eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917809747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1917809747
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2117319534
Short name T219
Test name
Test status
Simulation time 127030197 ps
CPU time 1.28 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:40 PM PST 24
Peak memory 200124 kb
Host smart-e9cecf77-c634-468e-a5af-92256535eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117319534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2117319534
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1274536161
Short name T478
Test name
Test status
Simulation time 7974266814 ps
CPU time 36.01 seconds
Started Mar 03 12:46:42 PM PST 24
Finished Mar 03 12:47:18 PM PST 24
Peak memory 208364 kb
Host smart-281aff0f-8f25-4607-a53f-37c9acd45dff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274536161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1274536161
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.918296437
Short name T175
Test name
Test status
Simulation time 468903162 ps
CPU time 2.66 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:41 PM PST 24
Peak memory 199984 kb
Host smart-0814e351-7deb-4bf2-a755-688b50906984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918296437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.918296437
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3705087751
Short name T445
Test name
Test status
Simulation time 289700668 ps
CPU time 1.64 seconds
Started Mar 03 12:46:39 PM PST 24
Finished Mar 03 12:46:41 PM PST 24
Peak memory 200120 kb
Host smart-d315f595-ffd0-4a5e-aa27-f45b55703a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705087751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3705087751
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1586851638
Short name T238
Test name
Test status
Simulation time 56912987 ps
CPU time 0.74 seconds
Started Mar 03 12:46:54 PM PST 24
Finished Mar 03 12:46:55 PM PST 24
Peak memory 199932 kb
Host smart-671134d7-070a-49bc-9d56-e609fb926b22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586851638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1586851638
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2057049121
Short name T35
Test name
Test status
Simulation time 1875792599 ps
CPU time 8.07 seconds
Started Mar 03 12:46:39 PM PST 24
Finished Mar 03 12:46:48 PM PST 24
Peak memory 217008 kb
Host smart-183ef6b4-d41f-4c4d-b312-9e4eb6522d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057049121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2057049121
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.607210375
Short name T348
Test name
Test status
Simulation time 247991614 ps
CPU time 1.11 seconds
Started Mar 03 12:46:29 PM PST 24
Finished Mar 03 12:46:30 PM PST 24
Peak memory 217136 kb
Host smart-7d5aa3a4-44eb-4a2e-9784-18c01c35dee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607210375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.607210375
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2957516781
Short name T294
Test name
Test status
Simulation time 100324642 ps
CPU time 0.82 seconds
Started Mar 03 12:46:37 PM PST 24
Finished Mar 03 12:46:38 PM PST 24
Peak memory 199716 kb
Host smart-9d32c9c9-1785-4603-bfb2-96f07d4ffa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957516781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2957516781
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.917233420
Short name T316
Test name
Test status
Simulation time 1043537256 ps
CPU time 5.68 seconds
Started Mar 03 12:46:31 PM PST 24
Finished Mar 03 12:46:36 PM PST 24
Peak memory 200172 kb
Host smart-4f0086d2-5087-4f10-9728-4eeb7808fd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917233420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.917233420
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1170788126
Short name T392
Test name
Test status
Simulation time 180189037 ps
CPU time 1.17 seconds
Started Mar 03 12:46:55 PM PST 24
Finished Mar 03 12:46:57 PM PST 24
Peak memory 199944 kb
Host smart-dd3657f9-f014-4e5d-974f-e522e0cd2c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170788126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1170788126
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3159431648
Short name T206
Test name
Test status
Simulation time 115536091 ps
CPU time 1.21 seconds
Started Mar 03 12:47:01 PM PST 24
Finished Mar 03 12:47:03 PM PST 24
Peak memory 200096 kb
Host smart-83f3e9c0-dc20-4303-9a95-454ae036e913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159431648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3159431648
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3613794746
Short name T246
Test name
Test status
Simulation time 8852097719 ps
CPU time 32.58 seconds
Started Mar 03 12:46:41 PM PST 24
Finished Mar 03 12:47:14 PM PST 24
Peak memory 200324 kb
Host smart-47317505-70b1-4ef5-ae32-fcea3cd0681b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613794746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3613794746
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.716391104
Short name T100
Test name
Test status
Simulation time 137156164 ps
CPU time 1.73 seconds
Started Mar 03 12:46:52 PM PST 24
Finished Mar 03 12:46:54 PM PST 24
Peak memory 199860 kb
Host smart-503884ad-7a03-4f3d-9c25-170cd82551ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716391104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.716391104
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.4182011679
Short name T371
Test name
Test status
Simulation time 262447077 ps
CPU time 1.56 seconds
Started Mar 03 12:46:41 PM PST 24
Finished Mar 03 12:46:42 PM PST 24
Peak memory 200036 kb
Host smart-da344762-bf3d-4321-b461-c18df2e28a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182011679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4182011679
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4010636209
Short name T302
Test name
Test status
Simulation time 58281949 ps
CPU time 0.79 seconds
Started Mar 03 12:46:54 PM PST 24
Finished Mar 03 12:46:55 PM PST 24
Peak memory 199952 kb
Host smart-430a814d-6af2-42a9-8ef5-ec6b264876ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010636209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4010636209
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1540963697
Short name T26
Test name
Test status
Simulation time 2175216018 ps
CPU time 8 seconds
Started Mar 03 12:46:40 PM PST 24
Finished Mar 03 12:46:48 PM PST 24
Peak memory 217680 kb
Host smart-04c879ea-a692-4e7a-a3e0-a85adf741209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540963697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1540963697
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3612101064
Short name T311
Test name
Test status
Simulation time 244493153 ps
CPU time 1.08 seconds
Started Mar 03 12:46:31 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 217136 kb
Host smart-550f6307-17d7-49a0-aa19-c1c1428b355f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612101064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3612101064
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3694393733
Short name T18
Test name
Test status
Simulation time 166823957 ps
CPU time 0.96 seconds
Started Mar 03 12:46:39 PM PST 24
Finished Mar 03 12:46:40 PM PST 24
Peak memory 199716 kb
Host smart-73ac2369-ff34-4a40-b89f-f6efbb088804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694393733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3694393733
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2199990063
Short name T107
Test name
Test status
Simulation time 973701051 ps
CPU time 5.29 seconds
Started Mar 03 12:46:30 PM PST 24
Finished Mar 03 12:46:35 PM PST 24
Peak memory 200148 kb
Host smart-6ecec0e4-b39e-4925-865c-72611490d58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199990063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2199990063
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1467538317
Short name T159
Test name
Test status
Simulation time 150581223 ps
CPU time 1.15 seconds
Started Mar 03 12:46:31 PM PST 24
Finished Mar 03 12:46:32 PM PST 24
Peak memory 200020 kb
Host smart-643f4e2e-c1a2-4d96-96d7-8d97b126e384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467538317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1467538317
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3987012522
Short name T167
Test name
Test status
Simulation time 267525717 ps
CPU time 1.58 seconds
Started Mar 03 12:46:36 PM PST 24
Finished Mar 03 12:46:38 PM PST 24
Peak memory 200056 kb
Host smart-57f204a0-debc-45d5-b432-7f963575ce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987012522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3987012522
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1862971760
Short name T108
Test name
Test status
Simulation time 8142558006 ps
CPU time 30.72 seconds
Started Mar 03 12:46:36 PM PST 24
Finished Mar 03 12:47:07 PM PST 24
Peak memory 200216 kb
Host smart-27f63c3d-5286-43a5-814f-a53e793d01ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862971760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1862971760
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2104174778
Short name T29
Test name
Test status
Simulation time 346994805 ps
CPU time 2.24 seconds
Started Mar 03 12:46:52 PM PST 24
Finished Mar 03 12:46:54 PM PST 24
Peak memory 208092 kb
Host smart-8cbbe2f9-64c0-4a77-b29b-6facd00321fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104174778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2104174778
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3814818408
Short name T455
Test name
Test status
Simulation time 147573486 ps
CPU time 1.22 seconds
Started Mar 03 12:46:46 PM PST 24
Finished Mar 03 12:46:47 PM PST 24
Peak memory 199896 kb
Host smart-88ba0cbc-85d1-428e-833b-87ba6b6a1085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814818408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3814818408
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2414029584
Short name T472
Test name
Test status
Simulation time 52698144 ps
CPU time 0.72 seconds
Started Mar 03 12:46:42 PM PST 24
Finished Mar 03 12:46:42 PM PST 24
Peak memory 199904 kb
Host smart-9bb2a55f-2022-4102-be52-a55691136a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414029584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2414029584
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1265101616
Short name T440
Test name
Test status
Simulation time 1899911627 ps
CPU time 7.85 seconds
Started Mar 03 12:46:50 PM PST 24
Finished Mar 03 12:46:58 PM PST 24
Peak memory 221688 kb
Host smart-69458dac-f0fe-4052-be7a-f25e2f20ab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265101616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1265101616
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.902305079
Short name T145
Test name
Test status
Simulation time 244827058 ps
CPU time 1.05 seconds
Started Mar 03 12:46:41 PM PST 24
Finished Mar 03 12:46:42 PM PST 24
Peak memory 217020 kb
Host smart-c3e15cb9-0382-4055-9856-2429e5a7061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902305079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.902305079
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1083443611
Short name T17
Test name
Test status
Simulation time 167327809 ps
CPU time 0.86 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:39 PM PST 24
Peak memory 199824 kb
Host smart-feb2e1db-3185-4450-b528-6dd1b8c07b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083443611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1083443611
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3771296254
Short name T438
Test name
Test status
Simulation time 1796884476 ps
CPU time 7.09 seconds
Started Mar 03 12:46:41 PM PST 24
Finished Mar 03 12:46:48 PM PST 24
Peak memory 200164 kb
Host smart-1f8f42bb-aad7-482b-985c-323bd5aa75ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771296254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3771296254
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1366193547
Short name T447
Test name
Test status
Simulation time 153527032 ps
CPU time 1.11 seconds
Started Mar 03 12:46:31 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 200004 kb
Host smart-d0857494-6d1f-4b1f-92ab-42a2cd49158a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366193547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1366193547
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3786195994
Short name T10
Test name
Test status
Simulation time 124532180 ps
CPU time 1.2 seconds
Started Mar 03 12:46:40 PM PST 24
Finished Mar 03 12:46:42 PM PST 24
Peak memory 200108 kb
Host smart-ab21e9a0-6b93-4439-ba40-cf75fb7ddec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786195994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3786195994
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1722646193
Short name T300
Test name
Test status
Simulation time 3974561282 ps
CPU time 14.09 seconds
Started Mar 03 12:46:41 PM PST 24
Finished Mar 03 12:46:55 PM PST 24
Peak memory 200328 kb
Host smart-75469051-65f2-4491-a377-bdcb93eb5ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722646193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1722646193
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2696692626
Short name T317
Test name
Test status
Simulation time 282619237 ps
CPU time 1.9 seconds
Started Mar 03 12:46:36 PM PST 24
Finished Mar 03 12:46:38 PM PST 24
Peak memory 200184 kb
Host smart-c784c576-e452-4893-a893-476fd6071fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696692626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2696692626
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.278971404
Short name T541
Test name
Test status
Simulation time 110749874 ps
CPU time 1.05 seconds
Started Mar 03 12:47:07 PM PST 24
Finished Mar 03 12:47:08 PM PST 24
Peak memory 199944 kb
Host smart-e273c06b-0a06-4f1d-b10f-0d77d9c39270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278971404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.278971404
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3208861404
Short name T470
Test name
Test status
Simulation time 73279494 ps
CPU time 0.79 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:39 PM PST 24
Peak memory 199864 kb
Host smart-7258eda7-12af-4a18-b283-114424c0a36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208861404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3208861404
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2262374992
Short name T487
Test name
Test status
Simulation time 1899047398 ps
CPU time 7.68 seconds
Started Mar 03 12:46:45 PM PST 24
Finished Mar 03 12:46:53 PM PST 24
Peak memory 220980 kb
Host smart-874b5265-3a98-4f9e-b709-a92b04dbc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262374992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2262374992
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2382436131
Short name T324
Test name
Test status
Simulation time 246859232 ps
CPU time 1.09 seconds
Started Mar 03 12:47:00 PM PST 24
Finished Mar 03 12:47:01 PM PST 24
Peak memory 216960 kb
Host smart-29154d9f-9eae-49bb-b3bf-c78e86c929f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382436131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2382436131
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2592320268
Short name T404
Test name
Test status
Simulation time 244439934 ps
CPU time 1.04 seconds
Started Mar 03 12:47:00 PM PST 24
Finished Mar 03 12:47:01 PM PST 24
Peak memory 199832 kb
Host smart-51f36688-4bd5-4a85-a388-d8eaa4265786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592320268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2592320268
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3880112177
Short name T111
Test name
Test status
Simulation time 1598801386 ps
CPU time 5.87 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:44 PM PST 24
Peak memory 200204 kb
Host smart-e35f4bf1-33fb-4b0a-9845-4538dbdbfa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880112177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3880112177
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1491833786
Short name T406
Test name
Test status
Simulation time 152576133 ps
CPU time 1.18 seconds
Started Mar 03 12:46:40 PM PST 24
Finished Mar 03 12:46:42 PM PST 24
Peak memory 200036 kb
Host smart-17adfc1b-2e88-4931-b7ca-04ba3d894f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491833786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1491833786
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1815007004
Short name T181
Test name
Test status
Simulation time 111901533 ps
CPU time 1.12 seconds
Started Mar 03 12:46:52 PM PST 24
Finished Mar 03 12:46:53 PM PST 24
Peak memory 200012 kb
Host smart-02be18b4-9f29-4e19-b61a-d5f52bae7dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815007004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1815007004
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.4046322230
Short name T156
Test name
Test status
Simulation time 346784603 ps
CPU time 2.1 seconds
Started Mar 03 12:46:42 PM PST 24
Finished Mar 03 12:46:44 PM PST 24
Peak memory 200112 kb
Host smart-87933d7f-ceed-4074-b791-e704a99a456b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046322230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4046322230
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2071507134
Short name T527
Test name
Test status
Simulation time 261868346 ps
CPU time 1.89 seconds
Started Mar 03 12:46:47 PM PST 24
Finished Mar 03 12:46:49 PM PST 24
Peak memory 199972 kb
Host smart-2d76329d-99dd-4157-b79e-02cab9e9085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071507134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2071507134
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2431458165
Short name T162
Test name
Test status
Simulation time 104530892 ps
CPU time 1.01 seconds
Started Mar 03 12:46:43 PM PST 24
Finished Mar 03 12:46:44 PM PST 24
Peak memory 200024 kb
Host smart-0f6afffd-9f84-4b4e-b9fc-64ddaa0c8506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431458165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2431458165
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3056391498
Short name T350
Test name
Test status
Simulation time 70332668 ps
CPU time 0.75 seconds
Started Mar 03 12:46:43 PM PST 24
Finished Mar 03 12:46:44 PM PST 24
Peak memory 199900 kb
Host smart-c9f17cdd-35a8-4aa5-85f4-a03dae5d563e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056391498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3056391498
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1417803381
Short name T39
Test name
Test status
Simulation time 1890997606 ps
CPU time 6.65 seconds
Started Mar 03 12:46:51 PM PST 24
Finished Mar 03 12:46:58 PM PST 24
Peak memory 221116 kb
Host smart-f4ff6a27-e455-4751-8491-d3428856a893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417803381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1417803381
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2377749564
Short name T213
Test name
Test status
Simulation time 245444515 ps
CPU time 1.11 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:39 PM PST 24
Peak memory 217060 kb
Host smart-1a192ebe-ab83-4ad7-b3f0-52868ecadc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377749564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2377749564
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2416519476
Short name T20
Test name
Test status
Simulation time 146871471 ps
CPU time 0.87 seconds
Started Mar 03 12:46:50 PM PST 24
Finished Mar 03 12:46:51 PM PST 24
Peak memory 200084 kb
Host smart-35e82195-3dc2-4c91-9a57-1f1bb1f2a6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416519476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2416519476
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2923514579
Short name T381
Test name
Test status
Simulation time 1890921091 ps
CPU time 6.81 seconds
Started Mar 03 12:46:51 PM PST 24
Finished Mar 03 12:46:57 PM PST 24
Peak memory 200212 kb
Host smart-0cd8b140-1ed8-411a-8d0c-e369f1c09052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923514579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2923514579
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4164129771
Short name T131
Test name
Test status
Simulation time 174409041 ps
CPU time 1.31 seconds
Started Mar 03 12:46:45 PM PST 24
Finished Mar 03 12:46:47 PM PST 24
Peak memory 199992 kb
Host smart-5caca997-da6a-49e7-b985-644501306e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164129771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4164129771
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1236954068
Short name T444
Test name
Test status
Simulation time 124482902 ps
CPU time 1.22 seconds
Started Mar 03 12:47:01 PM PST 24
Finished Mar 03 12:47:03 PM PST 24
Peak memory 200128 kb
Host smart-494cde35-6ef0-455d-9289-6e9c3db353b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236954068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1236954068
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1608847227
Short name T253
Test name
Test status
Simulation time 3582844232 ps
CPU time 14 seconds
Started Mar 03 12:46:44 PM PST 24
Finished Mar 03 12:46:58 PM PST 24
Peak memory 200228 kb
Host smart-e8ede3dc-6723-4263-9629-30d4db893f5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608847227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1608847227
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.468779644
Short name T174
Test name
Test status
Simulation time 121823169 ps
CPU time 1.54 seconds
Started Mar 03 12:46:52 PM PST 24
Finished Mar 03 12:46:53 PM PST 24
Peak memory 199980 kb
Host smart-abd9e440-e406-42cd-bb28-e65bc27bb1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468779644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.468779644
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.116351498
Short name T133
Test name
Test status
Simulation time 175489846 ps
CPU time 1.16 seconds
Started Mar 03 12:46:52 PM PST 24
Finished Mar 03 12:46:54 PM PST 24
Peak memory 200016 kb
Host smart-cb8ec63a-f902-4988-bd74-987c720f28f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116351498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.116351498
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.875117844
Short name T519
Test name
Test status
Simulation time 73529612 ps
CPU time 0.81 seconds
Started Mar 03 12:46:42 PM PST 24
Finished Mar 03 12:46:43 PM PST 24
Peak memory 199956 kb
Host smart-8bd75bf8-0a5e-4403-acc1-e9662a294612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875117844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.875117844
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3859817119
Short name T205
Test name
Test status
Simulation time 1899096017 ps
CPU time 7.23 seconds
Started Mar 03 12:47:06 PM PST 24
Finished Mar 03 12:47:13 PM PST 24
Peak memory 216988 kb
Host smart-a964fc4a-2ad1-41ad-a503-86ee32989128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859817119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3859817119
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.716271519
Short name T343
Test name
Test status
Simulation time 244025184 ps
CPU time 1.14 seconds
Started Mar 03 12:46:41 PM PST 24
Finished Mar 03 12:46:42 PM PST 24
Peak memory 217144 kb
Host smart-1fcc8755-738a-4beb-9093-5a836e7efcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716271519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.716271519
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1824117686
Short name T19
Test name
Test status
Simulation time 168649364 ps
CPU time 0.91 seconds
Started Mar 03 12:46:59 PM PST 24
Finished Mar 03 12:47:00 PM PST 24
Peak memory 199728 kb
Host smart-a79f6900-2199-4159-8645-2870f980874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824117686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1824117686
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1216762501
Short name T157
Test name
Test status
Simulation time 1879469830 ps
CPU time 6.84 seconds
Started Mar 03 12:46:42 PM PST 24
Finished Mar 03 12:46:49 PM PST 24
Peak memory 200188 kb
Host smart-9e9be147-e414-4f2e-969a-fdb408f65a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216762501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1216762501
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1232340680
Short name T228
Test name
Test status
Simulation time 162497126 ps
CPU time 1.24 seconds
Started Mar 03 12:46:55 PM PST 24
Finished Mar 03 12:46:57 PM PST 24
Peak memory 200000 kb
Host smart-c7c8f4d2-6e5f-408e-bd0f-276e71ce8f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232340680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1232340680
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.906686883
Short name T403
Test name
Test status
Simulation time 218825098 ps
CPU time 1.48 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:40 PM PST 24
Peak memory 200092 kb
Host smart-e8347768-75dd-44c3-a2f5-b35afd45e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906686883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.906686883
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1272329854
Short name T315
Test name
Test status
Simulation time 7279547227 ps
CPU time 25.39 seconds
Started Mar 03 12:46:47 PM PST 24
Finished Mar 03 12:47:12 PM PST 24
Peak memory 216864 kb
Host smart-cbfdcb35-081a-432a-8ad9-e90cc3470ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272329854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1272329854
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1414849389
Short name T376
Test name
Test status
Simulation time 454370679 ps
CPU time 2.37 seconds
Started Mar 03 12:46:43 PM PST 24
Finished Mar 03 12:46:45 PM PST 24
Peak memory 199884 kb
Host smart-90160008-713a-4553-b98a-7e9d7b9830cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414849389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1414849389
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3917658668
Short name T485
Test name
Test status
Simulation time 106570512 ps
CPU time 1.03 seconds
Started Mar 03 12:46:42 PM PST 24
Finished Mar 03 12:46:44 PM PST 24
Peak memory 200020 kb
Host smart-53e01806-cd1f-4ade-ad06-90c3d31ea9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917658668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3917658668
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2188695444
Short name T252
Test name
Test status
Simulation time 72744192 ps
CPU time 0.79 seconds
Started Mar 03 12:46:50 PM PST 24
Finished Mar 03 12:46:51 PM PST 24
Peak memory 199952 kb
Host smart-fd91650a-8824-4c7e-926a-feae7da6cb1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188695444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2188695444
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1783050567
Short name T4
Test name
Test status
Simulation time 1220709605 ps
CPU time 5.32 seconds
Started Mar 03 12:46:39 PM PST 24
Finished Mar 03 12:46:45 PM PST 24
Peak memory 216972 kb
Host smart-2f510917-3df2-4125-9b29-4e86c2dc4043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783050567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1783050567
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3184262187
Short name T538
Test name
Test status
Simulation time 243626070 ps
CPU time 1.17 seconds
Started Mar 03 12:46:43 PM PST 24
Finished Mar 03 12:46:45 PM PST 24
Peak memory 216964 kb
Host smart-fdc96965-abd6-4864-867d-bb83d1ec71a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184262187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3184262187
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.232969800
Short name T433
Test name
Test status
Simulation time 176319818 ps
CPU time 0.93 seconds
Started Mar 03 12:46:45 PM PST 24
Finished Mar 03 12:46:46 PM PST 24
Peak memory 199820 kb
Host smart-f99c34d8-5fb1-4b05-8948-4cf2d93128f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232969800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.232969800
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2191467429
Short name T356
Test name
Test status
Simulation time 1665879359 ps
CPU time 7.11 seconds
Started Mar 03 12:46:48 PM PST 24
Finished Mar 03 12:46:55 PM PST 24
Peak memory 200236 kb
Host smart-7c7995a4-b948-4cb1-b66a-2d8ceab99bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191467429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2191467429
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2194924191
Short name T503
Test name
Test status
Simulation time 106036972 ps
CPU time 0.98 seconds
Started Mar 03 12:46:42 PM PST 24
Finished Mar 03 12:46:44 PM PST 24
Peak memory 199976 kb
Host smart-9a7cc73f-108e-4c00-a7d6-104748f3f20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194924191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2194924191
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2665986404
Short name T274
Test name
Test status
Simulation time 248283549 ps
CPU time 1.51 seconds
Started Mar 03 12:46:59 PM PST 24
Finished Mar 03 12:47:01 PM PST 24
Peak memory 200032 kb
Host smart-d428371c-0e20-43ed-b3bb-8d9ae99324fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665986404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2665986404
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3986684523
Short name T312
Test name
Test status
Simulation time 3834185665 ps
CPU time 19.08 seconds
Started Mar 03 12:46:51 PM PST 24
Finished Mar 03 12:47:10 PM PST 24
Peak memory 200180 kb
Host smart-dd749cb1-a76d-4637-b1d9-e3c71055c933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986684523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3986684523
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.568957791
Short name T537
Test name
Test status
Simulation time 126190194 ps
CPU time 1.49 seconds
Started Mar 03 12:46:38 PM PST 24
Finished Mar 03 12:46:40 PM PST 24
Peak memory 199756 kb
Host smart-518f0e83-4817-4586-b363-be341862373c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568957791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.568957791
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1457909151
Short name T211
Test name
Test status
Simulation time 137826294 ps
CPU time 1.16 seconds
Started Mar 03 12:46:51 PM PST 24
Finished Mar 03 12:46:52 PM PST 24
Peak memory 199928 kb
Host smart-b6e769de-43e1-4595-ba47-fe8f9296dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457909151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1457909151
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3835671304
Short name T464
Test name
Test status
Simulation time 60622633 ps
CPU time 0.74 seconds
Started Mar 03 12:45:43 PM PST 24
Finished Mar 03 12:45:44 PM PST 24
Peak memory 199880 kb
Host smart-5c2fb7d5-0864-45d3-bc8c-16fc1b10d516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835671304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3835671304
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1672282885
Short name T28
Test name
Test status
Simulation time 1890965158 ps
CPU time 7.51 seconds
Started Mar 03 12:45:42 PM PST 24
Finished Mar 03 12:45:51 PM PST 24
Peak memory 221604 kb
Host smart-695f7413-d530-4529-85d7-89ab94dd6520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672282885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1672282885
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1427875498
Short name T163
Test name
Test status
Simulation time 243816404 ps
CPU time 1.13 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:48 PM PST 24
Peak memory 216964 kb
Host smart-5948d0b9-ac7f-4d26-aa77-99a712b3e1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427875498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1427875498
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1538958306
Short name T434
Test name
Test status
Simulation time 146828989 ps
CPU time 0.86 seconds
Started Mar 03 12:45:47 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 199836 kb
Host smart-203cae16-3096-4aca-acc8-9c5c5180e903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538958306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1538958306
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2140383650
Short name T168
Test name
Test status
Simulation time 1668459520 ps
CPU time 7.32 seconds
Started Mar 03 12:45:36 PM PST 24
Finished Mar 03 12:45:44 PM PST 24
Peak memory 200120 kb
Host smart-2a8e4d52-ed93-461f-ba7c-b363730ac764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140383650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2140383650
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.860502869
Short name T127
Test name
Test status
Simulation time 182746286 ps
CPU time 1.24 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:46 PM PST 24
Peak memory 199936 kb
Host smart-d8d8fc1f-1f2d-41a6-ac9c-44c6fae9dcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860502869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.860502869
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2292801633
Short name T424
Test name
Test status
Simulation time 223317964 ps
CPU time 1.46 seconds
Started Mar 03 12:45:53 PM PST 24
Finished Mar 03 12:45:55 PM PST 24
Peak memory 200156 kb
Host smart-ca37efff-9516-490f-8d2b-c00160776dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292801633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2292801633
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1992745538
Short name T389
Test name
Test status
Simulation time 6873841302 ps
CPU time 23.6 seconds
Started Mar 03 12:45:36 PM PST 24
Finished Mar 03 12:46:00 PM PST 24
Peak memory 208360 kb
Host smart-be617ef9-fb9d-40cd-90fb-b264eb87b633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992745538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1992745538
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.107128067
Short name T233
Test name
Test status
Simulation time 124039358 ps
CPU time 1.62 seconds
Started Mar 03 12:45:36 PM PST 24
Finished Mar 03 12:45:38 PM PST 24
Peak memory 208064 kb
Host smart-545d3dec-0567-4239-bc50-12cd12acb982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107128067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.107128067
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.882714954
Short name T155
Test name
Test status
Simulation time 106410035 ps
CPU time 0.92 seconds
Started Mar 03 12:45:40 PM PST 24
Finished Mar 03 12:45:42 PM PST 24
Peak memory 199944 kb
Host smart-ea33158d-d25b-4cee-8d01-1210cd74efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882714954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.882714954
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.967769242
Short name T214
Test name
Test status
Simulation time 76290483 ps
CPU time 0.81 seconds
Started Mar 03 12:45:44 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 199844 kb
Host smart-737420f9-3bc1-48a3-8ebd-b646ecde83c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967769242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.967769242
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1872786648
Short name T399
Test name
Test status
Simulation time 1894423053 ps
CPU time 7.76 seconds
Started Mar 03 12:45:34 PM PST 24
Finished Mar 03 12:45:42 PM PST 24
Peak memory 217456 kb
Host smart-47dc4480-8e42-4c1c-9628-121e1816668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872786648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1872786648
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2485415136
Short name T502
Test name
Test status
Simulation time 244317441 ps
CPU time 1.03 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 216972 kb
Host smart-6eed7d15-f817-4267-9c08-b5d91da19e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485415136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2485415136
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3839529646
Short name T194
Test name
Test status
Simulation time 166406102 ps
CPU time 0.92 seconds
Started Mar 03 12:45:35 PM PST 24
Finished Mar 03 12:45:36 PM PST 24
Peak memory 199748 kb
Host smart-76096f82-e204-4140-87fb-f3fa75418d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839529646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3839529646
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2504307905
Short name T486
Test name
Test status
Simulation time 879039344 ps
CPU time 5.04 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:56 PM PST 24
Peak memory 200164 kb
Host smart-3775ce54-c587-459f-a109-d50a440514e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504307905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2504307905
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3335352286
Short name T172
Test name
Test status
Simulation time 102191693 ps
CPU time 1.04 seconds
Started Mar 03 12:45:42 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 199940 kb
Host smart-3caf3fef-0d55-4cc9-8ef0-6e063a1f5fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335352286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3335352286
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3848564340
Short name T198
Test name
Test status
Simulation time 202070694 ps
CPU time 1.35 seconds
Started Mar 03 12:45:41 PM PST 24
Finished Mar 03 12:45:44 PM PST 24
Peak memory 200124 kb
Host smart-c4f0dcc5-0318-46fa-8453-f006e75f5c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848564340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3848564340
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2480654174
Short name T297
Test name
Test status
Simulation time 9829735441 ps
CPU time 45.09 seconds
Started Mar 03 12:45:36 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 209828 kb
Host smart-f7c279e1-cde3-4e87-85cb-04bede2e3062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480654174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2480654174
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1524466460
Short name T171
Test name
Test status
Simulation time 145984510 ps
CPU time 1.84 seconds
Started Mar 03 12:45:38 PM PST 24
Finished Mar 03 12:45:41 PM PST 24
Peak memory 199916 kb
Host smart-2810e7d9-f211-49b5-a928-32bbf8e13d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524466460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1524466460
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.30400605
Short name T457
Test name
Test status
Simulation time 80820729 ps
CPU time 0.87 seconds
Started Mar 03 12:45:33 PM PST 24
Finished Mar 03 12:45:35 PM PST 24
Peak memory 199804 kb
Host smart-0335bf45-69c4-4dc5-9af8-2bddf438d905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30400605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.30400605
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.440227854
Short name T264
Test name
Test status
Simulation time 66272180 ps
CPU time 0.8 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:46 PM PST 24
Peak memory 199860 kb
Host smart-59d1e5f7-3d78-4053-8c1d-d5b7cb8fe75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440227854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.440227854
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.4284511504
Short name T495
Test name
Test status
Simulation time 1228409873 ps
CPU time 5.66 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:57 PM PST 24
Peak memory 217556 kb
Host smart-0373d4db-f067-4f8d-b4f3-358e811c59ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284511504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.4284511504
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3559423599
Short name T330
Test name
Test status
Simulation time 244459337 ps
CPU time 1.12 seconds
Started Mar 03 12:46:06 PM PST 24
Finished Mar 03 12:46:07 PM PST 24
Peak memory 217120 kb
Host smart-d99ba9d6-7dba-4fdb-81cf-2c42b5925735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559423599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3559423599
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1811178843
Short name T2
Test name
Test status
Simulation time 171288520 ps
CPU time 0.88 seconds
Started Mar 03 12:45:44 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 199756 kb
Host smart-04e2c447-638d-48b2-8cae-87f07d3ad7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811178843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1811178843
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3139205104
Short name T200
Test name
Test status
Simulation time 1256616847 ps
CPU time 5.06 seconds
Started Mar 03 12:45:43 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 200128 kb
Host smart-368032b0-1cfe-4aa7-a436-2e7f6ec49a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139205104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3139205104
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.942994972
Short name T47
Test name
Test status
Simulation time 141829606 ps
CPU time 1.13 seconds
Started Mar 03 12:45:52 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 200012 kb
Host smart-f54c0a1f-b1ec-4d87-a704-c3b1fc9656c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942994972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.942994972
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2239682007
Short name T427
Test name
Test status
Simulation time 195107678 ps
CPU time 1.43 seconds
Started Mar 03 12:45:43 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 200052 kb
Host smart-c8cbfd64-139e-4c3f-9414-c5562259eda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239682007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2239682007
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2128601277
Short name T395
Test name
Test status
Simulation time 170740237 ps
CPU time 1.36 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:45:59 PM PST 24
Peak memory 200024 kb
Host smart-937d2b64-aef9-40ed-a6da-a3bf98ef898e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128601277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2128601277
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.464968373
Short name T193
Test name
Test status
Simulation time 304205063 ps
CPU time 2.05 seconds
Started Mar 03 12:45:55 PM PST 24
Finished Mar 03 12:45:58 PM PST 24
Peak memory 208152 kb
Host smart-7dde5795-4ab4-461b-ada3-0b836dbf7132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464968373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.464968373
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2211111996
Short name T170
Test name
Test status
Simulation time 105035147 ps
CPU time 1.02 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 199924 kb
Host smart-fbc91b7c-80d2-4c74-925b-c9a231308ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211111996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2211111996
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3415407288
Short name T63
Test name
Test status
Simulation time 67829200 ps
CPU time 0.84 seconds
Started Mar 03 12:45:50 PM PST 24
Finished Mar 03 12:45:51 PM PST 24
Peak memory 199944 kb
Host smart-c30c162f-0111-4c60-bf0e-727c4c81a3ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415407288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3415407288
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3383942375
Short name T308
Test name
Test status
Simulation time 1890718091 ps
CPU time 7.25 seconds
Started Mar 03 12:45:54 PM PST 24
Finished Mar 03 12:46:01 PM PST 24
Peak memory 216832 kb
Host smart-d77c4a4d-071f-4b10-9b0a-b74ff864a106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383942375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3383942375
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1182954364
Short name T430
Test name
Test status
Simulation time 244500938 ps
CPU time 1.09 seconds
Started Mar 03 12:45:48 PM PST 24
Finished Mar 03 12:45:50 PM PST 24
Peak memory 216908 kb
Host smart-b2b7c8fb-7451-4b76-b9b4-8f5cf75bf1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182954364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1182954364
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.765174185
Short name T303
Test name
Test status
Simulation time 109244483 ps
CPU time 0.77 seconds
Started Mar 03 12:45:50 PM PST 24
Finished Mar 03 12:45:51 PM PST 24
Peak memory 199696 kb
Host smart-94c376c7-3b95-424d-bf6d-8e1445c372f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765174185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.765174185
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2934907583
Short name T197
Test name
Test status
Simulation time 1815595497 ps
CPU time 7.67 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:59 PM PST 24
Peak memory 200192 kb
Host smart-9e77f8a5-95c5-456b-8df9-5693e46cf99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934907583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2934907583
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2459532673
Short name T313
Test name
Test status
Simulation time 103205842 ps
CPU time 1.06 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:52 PM PST 24
Peak memory 200004 kb
Host smart-90ccec9e-341f-488b-a437-bbb9f925410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459532673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2459532673
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3835857093
Short name T462
Test name
Test status
Simulation time 117984366 ps
CPU time 1.12 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:48 PM PST 24
Peak memory 199980 kb
Host smart-7eb2eca5-98da-4769-b3ab-a9c7d3274581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835857093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3835857093
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2733048322
Short name T109
Test name
Test status
Simulation time 6128414532 ps
CPU time 24.25 seconds
Started Mar 03 12:45:47 PM PST 24
Finished Mar 03 12:46:13 PM PST 24
Peak memory 208424 kb
Host smart-da5b7693-4fa7-4bdb-ba8a-11a920af3125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733048322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2733048322
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2418344548
Short name T299
Test name
Test status
Simulation time 140021941 ps
CPU time 2.01 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:53 PM PST 24
Peak memory 199848 kb
Host smart-b2174821-101e-49d1-8682-e0f4f9d491fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418344548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2418344548
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.35996645
Short name T437
Test name
Test status
Simulation time 79745864 ps
CPU time 0.85 seconds
Started Mar 03 12:45:47 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 199936 kb
Host smart-68a76046-16f5-46f5-b5cc-b2b9774dcf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35996645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.35996645
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1720576895
Short name T289
Test name
Test status
Simulation time 76991950 ps
CPU time 0.84 seconds
Started Mar 03 12:45:46 PM PST 24
Finished Mar 03 12:45:48 PM PST 24
Peak memory 199808 kb
Host smart-ffc982cb-9863-4ddf-8ece-17601c1e8fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720576895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1720576895
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2147020180
Short name T292
Test name
Test status
Simulation time 1908591066 ps
CPU time 7.38 seconds
Started Mar 03 12:45:49 PM PST 24
Finished Mar 03 12:45:57 PM PST 24
Peak memory 221536 kb
Host smart-1833e1ac-1dce-4813-9049-679df0cf58a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147020180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2147020180
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2545709227
Short name T339
Test name
Test status
Simulation time 245453512 ps
CPU time 1.04 seconds
Started Mar 03 12:45:57 PM PST 24
Finished Mar 03 12:45:58 PM PST 24
Peak memory 216980 kb
Host smart-3b06ce55-cf5a-403a-83d2-0829fa701440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545709227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2545709227
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2695213189
Short name T463
Test name
Test status
Simulation time 176189981 ps
CPU time 0.9 seconds
Started Mar 03 12:45:48 PM PST 24
Finished Mar 03 12:45:50 PM PST 24
Peak memory 199748 kb
Host smart-57377748-8527-4562-bce4-0ff0367b5675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695213189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2695213189
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1184007998
Short name T9
Test name
Test status
Simulation time 1552913293 ps
CPU time 5.94 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:45:58 PM PST 24
Peak memory 200052 kb
Host smart-59bbb6cc-bdc1-4a86-851c-e085adcf30ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184007998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1184007998
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.671557399
Short name T417
Test name
Test status
Simulation time 181784786 ps
CPU time 1.2 seconds
Started Mar 03 12:45:45 PM PST 24
Finished Mar 03 12:45:46 PM PST 24
Peak memory 199996 kb
Host smart-6c2cad02-9e9b-4834-9a4b-402698e4615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671557399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.671557399
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3277111267
Short name T305
Test name
Test status
Simulation time 200899399 ps
CPU time 1.41 seconds
Started Mar 03 12:45:43 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 200024 kb
Host smart-8fa2896b-b713-49c4-b38e-21b5b23c2996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277111267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3277111267
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2300155196
Short name T418
Test name
Test status
Simulation time 15935240754 ps
CPU time 58.76 seconds
Started Mar 03 12:45:51 PM PST 24
Finished Mar 03 12:46:50 PM PST 24
Peak memory 208328 kb
Host smart-c5a4b8ac-8242-4de1-a19e-457440c775bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300155196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2300155196
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3479016176
Short name T513
Test name
Test status
Simulation time 144327779 ps
CPU time 1.84 seconds
Started Mar 03 12:46:01 PM PST 24
Finished Mar 03 12:46:03 PM PST 24
Peak memory 199832 kb
Host smart-da5f647e-a420-4f88-bc30-18e98d93ef56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479016176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3479016176
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1441730763
Short name T148
Test name
Test status
Simulation time 104358809 ps
CPU time 0.95 seconds
Started Mar 03 12:45:47 PM PST 24
Finished Mar 03 12:45:49 PM PST 24
Peak memory 200012 kb
Host smart-1e9696cc-6e7d-4847-80ab-9d763fd8dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441730763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1441730763
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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