Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8235

1

T4

26

T5

21

T7

14

auto[1]

11027

1

T1

4

T2

4

T4

22

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5979	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6424	1			T1	2		T2	2		T3	1
reset_info_cp[2]	2974	1			T1	1		T2	1		T4	4
reset_info_cp[4]	3935	1			T1	1		T2	1		T4	7
reset_info_cp[8]	114	1			T5	1		T62	2		T84	3
reset_info_cp[16]	108	1			T13	1		T62	1		T83	1
reset_info_cp[32]	119	1			T2	1		T62	1		T83	1
reset_info_cp[64]	123	1			T62	3		T99	1		T85	1
reset_info_cp[128]	105	1			T84	1		T114	1		T89	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3114	1			T4	14		T5	4		T7	14
reset_info_cp[1]	auto[1]	2691	1			T1	1		T2	1		T4	10
reset_info_cp[2]	auto[0]	926	1			T4	2		T5	4		T13	3
reset_info_cp[2]	auto[1]	2048	1			T1	1		T2	1		T4	2
reset_info_cp[4]	auto[0]	1437	1			T4	3		T5	6		T13	4
reset_info_cp[4]	auto[1]	2498	1			T1	1		T2	1		T4	4
reset_info_cp[8]	auto[0]	44	1			T62	1		T84	1		T85	2
reset_info_cp[8]	auto[1]	70	1			T5	1		T62	1		T84	2
reset_info_cp[16]	auto[0]	46	1			T13	1		T99	2		T89	1
reset_info_cp[16]	auto[1]	62	1			T62	1		T83	1		T89	1
reset_info_cp[32]	auto[0]	49	1			T62	1		T83	1		T84	2
reset_info_cp[32]	auto[1]	70	1			T2	1		T84	1		T89	1
reset_info_cp[64]	auto[0]	46	1			T62	1		T99	1		T114	1
reset_info_cp[64]	auto[1]	77	1			T62	2		T85	1		T43	1
reset_info_cp[128]	auto[0]	42	1			T84	1		T89	1		T90	1
reset_info_cp[128]	auto[1]	63	1			T114	1		T90	1		T35	2