Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 619
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T533 /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2033753148 Mar 05 12:42:19 PM PST 24 Mar 05 12:42:21 PM PST 24 244111815 ps
T534 /workspace/coverage/default/18.rstmgr_por_stretcher.2828390218 Mar 05 12:41:43 PM PST 24 Mar 05 12:41:44 PM PST 24 214817361 ps
T535 /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2683839065 Mar 05 12:41:45 PM PST 24 Mar 05 12:41:53 PM PST 24 1908675156 ps
T536 /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3612106010 Mar 05 12:41:45 PM PST 24 Mar 05 12:41:52 PM PST 24 1217949306 ps
T57 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.936649307 Mar 05 12:38:40 PM PST 24 Mar 05 12:38:42 PM PST 24 127661196 ps
T63 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1616127319 Mar 05 12:38:49 PM PST 24 Mar 05 12:38:53 PM PST 24 513956039 ps
T58 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3848027687 Mar 05 12:38:43 PM PST 24 Mar 05 12:38:46 PM PST 24 206277731 ps
T64 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2318100298 Mar 05 12:38:34 PM PST 24 Mar 05 12:38:36 PM PST 24 235618245 ps
T59 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1088108217 Mar 05 12:38:30 PM PST 24 Mar 05 12:38:33 PM PST 24 776779589 ps
T60 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2189892130 Mar 05 12:38:53 PM PST 24 Mar 05 12:38:54 PM PST 24 199156744 ps
T97 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1804268446 Mar 05 12:38:37 PM PST 24 Mar 05 12:38:40 PM PST 24 432829636 ps
T65 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.845233709 Mar 05 12:38:37 PM PST 24 Mar 05 12:38:39 PM PST 24 104531774 ps
T91 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3828719880 Mar 05 12:39:52 PM PST 24 Mar 05 12:39:55 PM PST 24 294899976 ps
T131 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3868541141 Mar 05 12:38:24 PM PST 24 Mar 05 12:38:27 PM PST 24 276275620 ps
T70 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.699126734 Mar 05 12:38:28 PM PST 24 Mar 05 12:38:30 PM PST 24 185153223 ps
T92 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.376285378 Mar 05 12:39:02 PM PST 24 Mar 05 12:39:05 PM PST 24 165242315 ps
T105 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1989637214 Mar 05 12:39:49 PM PST 24 Mar 05 12:39:51 PM PST 24 112734674 ps
T93 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3225784859 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:45 PM PST 24 133914720 ps
T95 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1975033686 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:45 PM PST 24 867278147 ps
T106 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2949208121 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:12 PM PST 24 140939418 ps
T107 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.288654121 Mar 05 12:38:47 PM PST 24 Mar 05 12:38:49 PM PST 24 214198965 ps
T115 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1576617776 Mar 05 12:38:45 PM PST 24 Mar 05 12:38:48 PM PST 24 503407609 ps
T108 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2266698611 Mar 05 12:39:03 PM PST 24 Mar 05 12:39:04 PM PST 24 66999547 ps
T121 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.204628074 Mar 05 12:38:40 PM PST 24 Mar 05 12:38:43 PM PST 24 495775349 ps
T109 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3647205010 Mar 05 12:38:47 PM PST 24 Mar 05 12:38:48 PM PST 24 58363468 ps
T94 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3366748362 Mar 05 12:39:01 PM PST 24 Mar 05 12:39:05 PM PST 24 485359058 ps
T110 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.292458738 Mar 05 12:38:29 PM PST 24 Mar 05 12:38:30 PM PST 24 81787042 ps
T537 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1435342285 Mar 05 12:38:43 PM PST 24 Mar 05 12:38:45 PM PST 24 182455833 ps
T538 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.378801941 Mar 05 12:38:52 PM PST 24 Mar 05 12:39:02 PM PST 24 2278879652 ps
T539 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3498837379 Mar 05 12:38:56 PM PST 24 Mar 05 12:38:58 PM PST 24 187192543 ps
T116 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1390629783 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:39 PM PST 24 867829044 ps
T540 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2060377920 Mar 05 12:38:52 PM PST 24 Mar 05 12:38:54 PM PST 24 211695945 ps
T541 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3172066153 Mar 05 12:38:56 PM PST 24 Mar 05 12:38:57 PM PST 24 445041744 ps
T542 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4185221481 Mar 05 12:38:32 PM PST 24 Mar 05 12:38:36 PM PST 24 490574656 ps
T543 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2585258913 Mar 05 12:38:21 PM PST 24 Mar 05 12:38:23 PM PST 24 149657698 ps
T544 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.393515003 Mar 05 12:39:35 PM PST 24 Mar 05 12:39:36 PM PST 24 131824228 ps
T111 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4105527163 Mar 05 12:39:02 PM PST 24 Mar 05 12:39:03 PM PST 24 55531166 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3921096730 Mar 05 12:38:30 PM PST 24 Mar 05 12:38:32 PM PST 24 78772665 ps
T112 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3144300440 Mar 05 12:38:43 PM PST 24 Mar 05 12:38:45 PM PST 24 110080836 ps
T113 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3139059716 Mar 05 12:38:45 PM PST 24 Mar 05 12:38:47 PM PST 24 61858401 ps
T546 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1433163519 Mar 05 12:38:28 PM PST 24 Mar 05 12:38:29 PM PST 24 62442967 ps
T547 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3334788856 Mar 05 12:38:33 PM PST 24 Mar 05 12:38:36 PM PST 24 946865081 ps
T548 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4052839319 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:43 PM PST 24 178814569 ps
T549 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1330550996 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:45 PM PST 24 135614018 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.740236429 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:59 PM PST 24 956695578 ps
T551 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3225088591 Mar 05 12:38:48 PM PST 24 Mar 05 12:38:50 PM PST 24 67203535 ps
T552 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2424676754 Mar 05 12:38:31 PM PST 24 Mar 05 12:38:32 PM PST 24 96328496 ps
T553 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2451697159 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:52 PM PST 24 110566905 ps
T554 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.208864023 Mar 05 12:38:35 PM PST 24 Mar 05 12:38:36 PM PST 24 94074325 ps
T555 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3838939610 Mar 05 12:38:49 PM PST 24 Mar 05 12:38:51 PM PST 24 126781378 ps
T117 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1214883995 Mar 05 12:40:01 PM PST 24 Mar 05 12:40:04 PM PST 24 492531297 ps
T556 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2885846246 Mar 05 12:38:34 PM PST 24 Mar 05 12:38:34 PM PST 24 63741855 ps
T557 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2621905257 Mar 05 12:38:37 PM PST 24 Mar 05 12:38:41 PM PST 24 502358747 ps
T558 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2102988162 Mar 05 12:38:58 PM PST 24 Mar 05 12:38:59 PM PST 24 152064112 ps
T559 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.794977067 Mar 05 12:40:03 PM PST 24 Mar 05 12:40:05 PM PST 24 132456443 ps
T560 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2606493261 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:45 PM PST 24 298499957 ps
T561 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2768800633 Mar 05 12:38:37 PM PST 24 Mar 05 12:38:38 PM PST 24 135072921 ps
T562 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2763873347 Mar 05 12:39:56 PM PST 24 Mar 05 12:39:58 PM PST 24 171204857 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.302546212 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:45 PM PST 24 389571593 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.226044293 Mar 05 12:38:39 PM PST 24 Mar 05 12:38:53 PM PST 24 492863840 ps
T565 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2462169670 Mar 05 12:40:05 PM PST 24 Mar 05 12:40:07 PM PST 24 161912568 ps
T566 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2844053868 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:50 PM PST 24 478787870 ps
T130 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.511541787 Mar 05 12:38:44 PM PST 24 Mar 05 12:38:46 PM PST 24 416918574 ps
T567 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3459074277 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:45 PM PST 24 1036631837 ps
T568 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.850334331 Mar 05 12:38:57 PM PST 24 Mar 05 12:38:58 PM PST 24 66077467 ps
T569 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.560542285 Mar 05 12:38:40 PM PST 24 Mar 05 12:38:41 PM PST 24 75415537 ps
T570 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1539386982 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:44 PM PST 24 76401953 ps
T571 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.728705874 Mar 05 12:38:49 PM PST 24 Mar 05 12:38:51 PM PST 24 457528980 ps
T572 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3052923753 Mar 05 12:38:29 PM PST 24 Mar 05 12:38:30 PM PST 24 108743118 ps
T573 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3889380748 Mar 05 12:38:56 PM PST 24 Mar 05 12:38:58 PM PST 24 449446608 ps
T574 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3967827709 Mar 05 12:38:37 PM PST 24 Mar 05 12:38:39 PM PST 24 80037043 ps
T575 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2958324611 Mar 05 12:38:50 PM PST 24 Mar 05 12:38:52 PM PST 24 80490901 ps
T576 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3011063976 Mar 05 12:38:54 PM PST 24 Mar 05 12:38:58 PM PST 24 413788770 ps
T577 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2094715477 Mar 05 12:38:56 PM PST 24 Mar 05 12:38:59 PM PST 24 388820756 ps
T578 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4293577028 Mar 05 12:38:46 PM PST 24 Mar 05 12:38:48 PM PST 24 137363056 ps
T579 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1736821172 Mar 05 12:38:33 PM PST 24 Mar 05 12:38:34 PM PST 24 429820166 ps
T580 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3515455812 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:53 PM PST 24 193241853 ps
T581 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3364943094 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:44 PM PST 24 100828909 ps
T582 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2004616893 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:39 PM PST 24 446289793 ps
T583 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4162554226 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:43 PM PST 24 86113156 ps
T584 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4140257286 Mar 05 12:38:58 PM PST 24 Mar 05 12:39:00 PM PST 24 83986226 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4073080774 Mar 05 12:38:23 PM PST 24 Mar 05 12:38:25 PM PST 24 133859687 ps
T586 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2564291987 Mar 05 12:38:45 PM PST 24 Mar 05 12:38:47 PM PST 24 72455644 ps
T587 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2889466691 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:45 PM PST 24 70856788 ps
T588 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1236560670 Mar 05 12:39:40 PM PST 24 Mar 05 12:39:44 PM PST 24 372241826 ps
T589 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.765712836 Mar 05 12:38:43 PM PST 24 Mar 05 12:38:54 PM PST 24 2289175271 ps
T590 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3112230423 Mar 05 12:40:01 PM PST 24 Mar 05 12:40:02 PM PST 24 135656746 ps
T591 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4188641913 Mar 05 12:38:54 PM PST 24 Mar 05 12:38:57 PM PST 24 805211067 ps
T592 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2419989490 Mar 05 12:39:50 PM PST 24 Mar 05 12:39:51 PM PST 24 104331682 ps
T593 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3520864139 Mar 05 12:38:40 PM PST 24 Mar 05 12:38:42 PM PST 24 175579787 ps
T594 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.969636537 Mar 05 12:38:48 PM PST 24 Mar 05 12:38:51 PM PST 24 171082491 ps
T119 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4222427522 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:47 PM PST 24 790654944 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3945470484 Mar 05 12:38:24 PM PST 24 Mar 05 12:38:29 PM PST 24 793736451 ps
T596 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.815907000 Mar 05 12:38:35 PM PST 24 Mar 05 12:38:36 PM PST 24 79987604 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1155700133 Mar 05 12:40:05 PM PST 24 Mar 05 12:40:07 PM PST 24 87574615 ps
T598 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3304476784 Mar 05 12:38:26 PM PST 24 Mar 05 12:38:28 PM PST 24 200648574 ps
T599 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2312504504 Mar 05 12:38:42 PM PST 24 Mar 05 12:38:44 PM PST 24 73521824 ps
T600 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3931871653 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:52 PM PST 24 208750303 ps
T601 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.50415994 Mar 05 12:40:01 PM PST 24 Mar 05 12:40:03 PM PST 24 176237004 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1512212685 Mar 05 12:38:22 PM PST 24 Mar 05 12:38:25 PM PST 24 225749056 ps
T603 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.527834076 Mar 05 12:38:54 PM PST 24 Mar 05 12:38:55 PM PST 24 62493303 ps
T604 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3156885810 Mar 05 12:38:29 PM PST 24 Mar 05 12:38:31 PM PST 24 238941599 ps
T605 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4219601275 Mar 05 12:38:46 PM PST 24 Mar 05 12:38:48 PM PST 24 134366612 ps
T606 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3440481894 Mar 05 12:38:39 PM PST 24 Mar 05 12:38:41 PM PST 24 68773875 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2653588181 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:43 PM PST 24 100367324 ps
T608 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2556166993 Mar 05 12:38:39 PM PST 24 Mar 05 12:38:42 PM PST 24 183664311 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3119860769 Mar 05 12:40:03 PM PST 24 Mar 05 12:40:05 PM PST 24 202280496 ps
T610 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.270562020 Mar 05 12:38:14 PM PST 24 Mar 05 12:38:16 PM PST 24 72947620 ps
T118 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1776177493 Mar 05 12:38:57 PM PST 24 Mar 05 12:39:00 PM PST 24 944570552 ps
T611 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1564450417 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:43 PM PST 24 62749421 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1796384427 Mar 05 12:38:59 PM PST 24 Mar 05 12:39:01 PM PST 24 285577489 ps
T613 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1531110929 Mar 05 12:38:24 PM PST 24 Mar 05 12:38:26 PM PST 24 131816514 ps
T614 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1610295434 Mar 05 12:38:50 PM PST 24 Mar 05 12:38:51 PM PST 24 136412165 ps
T120 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3104218858 Mar 05 12:38:38 PM PST 24 Mar 05 12:38:40 PM PST 24 480078145 ps
T615 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3711226717 Mar 05 12:38:37 PM PST 24 Mar 05 12:38:39 PM PST 24 433985995 ps
T616 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2407665007 Mar 05 12:38:51 PM PST 24 Mar 05 12:38:53 PM PST 24 480583289 ps
T617 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2798949291 Mar 05 12:38:57 PM PST 24 Mar 05 12:38:58 PM PST 24 168030782 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.435530779 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:38 PM PST 24 159414082 ps
T619 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2458345074 Mar 05 12:40:03 PM PST 24 Mar 05 12:40:06 PM PST 24 377874164 ps

Test location /workspace/coverage/default/25.rstmgr_reset.3022671950
Short name T5
Test name
Test status
Simulation time 1334994623 ps
CPU time 5.33 seconds
Started Mar 05 12:42:14 PM PST 24
Finished Mar 05 12:42:20 PM PST 24
Peak memory 200364 kb
Host smart-1d6018b1-05f2-4c5a-95e0-5bcab26558d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022671950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3022671950
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.809415698
Short name T21
Test name
Test status
Simulation time 127155967 ps
CPU time 1.7 seconds
Started Mar 05 12:41:44 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 200220 kb
Host smart-102a8b5c-e156-40c2-b534-d5d1fa46192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809415698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.809415698
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1088108217
Short name T59
Test name
Test status
Simulation time 776779589 ps
CPU time 3.06 seconds
Started Mar 05 12:38:30 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200356 kb
Host smart-19d0c717-1d3e-4593-a62e-fba4b4a56d35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088108217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1088108217
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.856040674
Short name T66
Test name
Test status
Simulation time 16570160901 ps
CPU time 27.36 seconds
Started Mar 05 12:41:31 PM PST 24
Finished Mar 05 12:41:58 PM PST 24
Peak memory 217756 kb
Host smart-46a18d17-9ab8-4daa-ba4d-ff6580d11a27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856040674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.856040674
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2226073476
Short name T7
Test name
Test status
Simulation time 1889049810 ps
CPU time 7.36 seconds
Started Mar 05 12:41:52 PM PST 24
Finished Mar 05 12:42:00 PM PST 24
Peak memory 217680 kb
Host smart-e3bebb78-941f-4d8c-88a1-03ba19e5ab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226073476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2226073476
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.672094022
Short name T43
Test name
Test status
Simulation time 13519723634 ps
CPU time 44.73 seconds
Started Mar 05 12:42:16 PM PST 24
Finished Mar 05 12:43:01 PM PST 24
Peak memory 209200 kb
Host smart-ee4d56d8-61b3-41ef-9d4d-51e3f0c60321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672094022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.672094022
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1616127319
Short name T63
Test name
Test status
Simulation time 513956039 ps
CPU time 3.31 seconds
Started Mar 05 12:38:49 PM PST 24
Finished Mar 05 12:38:53 PM PST 24
Peak memory 208496 kb
Host smart-efe5e13a-f89b-4b26-930b-dadcd394e19d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616127319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1616127319
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2201999887
Short name T10
Test name
Test status
Simulation time 180917113 ps
CPU time 1.25 seconds
Started Mar 05 12:41:16 PM PST 24
Finished Mar 05 12:41:18 PM PST 24
Peak memory 200348 kb
Host smart-d6ea69db-bc7b-48fd-90db-c2ac26ccf2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201999887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2201999887
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.586587607
Short name T35
Test name
Test status
Simulation time 1907247834 ps
CPU time 7.03 seconds
Started Mar 05 12:42:07 PM PST 24
Finished Mar 05 12:42:15 PM PST 24
Peak memory 217660 kb
Host smart-5dbbe233-af21-48aa-9c83-13b425ee041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586587607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.586587607
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.253055372
Short name T140
Test name
Test status
Simulation time 63816188 ps
CPU time 0.71 seconds
Started Mar 05 12:41:35 PM PST 24
Finished Mar 05 12:41:36 PM PST 24
Peak memory 200032 kb
Host smart-94fc679b-4c02-486a-a79d-8a5b84499bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253055372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.253055372
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1214883995
Short name T117
Test name
Test status
Simulation time 492531297 ps
CPU time 1.94 seconds
Started Mar 05 12:40:01 PM PST 24
Finished Mar 05 12:40:04 PM PST 24
Peak memory 200324 kb
Host smart-569e9b6f-ac5b-48fd-bd99-25db43b5a29d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214883995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1214883995
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2049288373
Short name T9
Test name
Test status
Simulation time 158606990 ps
CPU time 0.83 seconds
Started Mar 05 12:41:58 PM PST 24
Finished Mar 05 12:42:04 PM PST 24
Peak memory 200160 kb
Host smart-049951e2-a6e7-41f8-ba4a-80b174cc4efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049288373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2049288373
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2961968662
Short name T99
Test name
Test status
Simulation time 191655810 ps
CPU time 1.16 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:35 PM PST 24
Peak memory 200220 kb
Host smart-eed8da22-6ae7-4071-b63b-be0509434791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961968662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2961968662
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3986748157
Short name T51
Test name
Test status
Simulation time 2355128368 ps
CPU time 8.75 seconds
Started Mar 05 12:41:43 PM PST 24
Finished Mar 05 12:41:52 PM PST 24
Peak memory 216920 kb
Host smart-bccca93c-bc13-490b-afdc-b0c9b8913976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986748157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3986748157
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2318100298
Short name T64
Test name
Test status
Simulation time 235618245 ps
CPU time 1.88 seconds
Started Mar 05 12:38:34 PM PST 24
Finished Mar 05 12:38:36 PM PST 24
Peak memory 208472 kb
Host smart-2267680f-6353-4501-b100-bad830c6db9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318100298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2318100298
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.292458738
Short name T110
Test name
Test status
Simulation time 81787042 ps
CPU time 0.9 seconds
Started Mar 05 12:38:29 PM PST 24
Finished Mar 05 12:38:30 PM PST 24
Peak memory 200136 kb
Host smart-be4119f9-4c2e-4391-b5e4-7fff01a09fd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292458738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.292458738
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4222427522
Short name T119
Test name
Test status
Simulation time 790654944 ps
CPU time 2.78 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:47 PM PST 24
Peak memory 200396 kb
Host smart-c940a67c-3ec8-4d31-bd3c-f813b13d0b12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222427522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4222427522
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1776177493
Short name T118
Test name
Test status
Simulation time 944570552 ps
CPU time 3.06 seconds
Started Mar 05 12:38:57 PM PST 24
Finished Mar 05 12:39:00 PM PST 24
Peak memory 200348 kb
Host smart-7662605a-42b9-481b-94e3-8db2d649e14e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776177493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1776177493
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.204628074
Short name T121
Test name
Test status
Simulation time 495775349 ps
CPU time 2.03 seconds
Started Mar 05 12:38:40 PM PST 24
Finished Mar 05 12:38:43 PM PST 24
Peak memory 200340 kb
Host smart-7e4a6a2a-9fb6-49d9-a9af-b66b62e131cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204628074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.204628074
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2060377920
Short name T540
Test name
Test status
Simulation time 211695945 ps
CPU time 1.53 seconds
Started Mar 05 12:38:52 PM PST 24
Finished Mar 05 12:38:54 PM PST 24
Peak memory 200292 kb
Host smart-bbee1d7e-6237-44aa-bfda-d3bc2a6e1cd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060377920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
060377920
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3945470484
Short name T595
Test name
Test status
Simulation time 793736451 ps
CPU time 4.69 seconds
Started Mar 05 12:38:24 PM PST 24
Finished Mar 05 12:38:29 PM PST 24
Peak memory 200316 kb
Host smart-ef939bb9-79ee-40ef-bdd0-37c4c7370a93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945470484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
945470484
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1330550996
Short name T549
Test name
Test status
Simulation time 135614018 ps
CPU time 0.93 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:45 PM PST 24
Peak memory 200160 kb
Host smart-d3e8e151-2e5d-4c39-a130-eac57caeadf1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330550996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
330550996
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.699126734
Short name T70
Test name
Test status
Simulation time 185153223 ps
CPU time 1.68 seconds
Started Mar 05 12:38:28 PM PST 24
Finished Mar 05 12:38:30 PM PST 24
Peak memory 212612 kb
Host smart-17c51d5f-cdc3-46bd-9c9a-45be2902ae6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699126734 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.699126734
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.270562020
Short name T610
Test name
Test status
Simulation time 72947620 ps
CPU time 0.75 seconds
Started Mar 05 12:38:14 PM PST 24
Finished Mar 05 12:38:16 PM PST 24
Peak memory 200128 kb
Host smart-a853e6c1-3a45-4512-a37d-c4483de66633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270562020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.270562020
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1531110929
Short name T613
Test name
Test status
Simulation time 131816514 ps
CPU time 1.3 seconds
Started Mar 05 12:38:24 PM PST 24
Finished Mar 05 12:38:26 PM PST 24
Peak memory 200212 kb
Host smart-00fb1215-1829-4fed-a68a-ede3081bdf2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531110929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1531110929
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1975033686
Short name T95
Test name
Test status
Simulation time 867278147 ps
CPU time 3.48 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:45 PM PST 24
Peak memory 200344 kb
Host smart-a2e86c3e-efa2-4ac5-b4c3-c7546f828503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975033686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1975033686
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1804268446
Short name T97
Test name
Test status
Simulation time 432829636 ps
CPU time 2.44 seconds
Started Mar 05 12:38:37 PM PST 24
Finished Mar 05 12:38:40 PM PST 24
Peak memory 200352 kb
Host smart-74845e31-a39b-4b6c-8ea5-67131b79798b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804268446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
804268446
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2844053868
Short name T566
Test name
Test status
Simulation time 478787870 ps
CPU time 5.77 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:50 PM PST 24
Peak memory 200380 kb
Host smart-1e4e9245-03b7-402f-bce0-10680ce4de1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844053868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
844053868
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2424676754
Short name T552
Test name
Test status
Simulation time 96328496 ps
CPU time 0.87 seconds
Started Mar 05 12:38:31 PM PST 24
Finished Mar 05 12:38:32 PM PST 24
Peak memory 200152 kb
Host smart-6234f30e-075b-4c5d-a307-ca8c7ae4316c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424676754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
424676754
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4073080774
Short name T585
Test name
Test status
Simulation time 133859687 ps
CPU time 1.55 seconds
Started Mar 05 12:38:23 PM PST 24
Finished Mar 05 12:38:25 PM PST 24
Peak memory 212684 kb
Host smart-fb4feff9-63ed-4cd4-9db4-e17f49f10334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073080774 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.4073080774
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3156885810
Short name T604
Test name
Test status
Simulation time 238941599 ps
CPU time 1.56 seconds
Started Mar 05 12:38:29 PM PST 24
Finished Mar 05 12:38:31 PM PST 24
Peak memory 200360 kb
Host smart-cce401a4-2c8d-4fd2-88fb-9ed88088bbff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156885810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3156885810
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2556166993
Short name T608
Test name
Test status
Simulation time 183664311 ps
CPU time 2.65 seconds
Started Mar 05 12:38:39 PM PST 24
Finished Mar 05 12:38:42 PM PST 24
Peak memory 212008 kb
Host smart-f955cfb2-d3e2-470a-9a4a-d1b42386e82f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556166993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2556166993
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3334788856
Short name T547
Test name
Test status
Simulation time 946865081 ps
CPU time 3.08 seconds
Started Mar 05 12:38:33 PM PST 24
Finished Mar 05 12:38:36 PM PST 24
Peak memory 200288 kb
Host smart-0c109bba-3111-4a0b-835d-c947c167b5d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334788856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3334788856
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2763873347
Short name T562
Test name
Test status
Simulation time 171204857 ps
CPU time 1.79 seconds
Started Mar 05 12:39:56 PM PST 24
Finished Mar 05 12:39:58 PM PST 24
Peak memory 208580 kb
Host smart-747e5d2b-d59a-4c93-ada8-0a970412468a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763873347 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2763873347
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3139059716
Short name T113
Test name
Test status
Simulation time 61858401 ps
CPU time 0.83 seconds
Started Mar 05 12:38:45 PM PST 24
Finished Mar 05 12:38:47 PM PST 24
Peak memory 200088 kb
Host smart-6e51a9a7-d547-4ffe-8c7f-005fe64fef9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139059716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3139059716
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3931871653
Short name T600
Test name
Test status
Simulation time 208750303 ps
CPU time 1.56 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:52 PM PST 24
Peak memory 200352 kb
Host smart-73baa912-6910-42bf-8cfe-ab3af4f01fd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931871653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3931871653
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.302546212
Short name T563
Test name
Test status
Simulation time 389571593 ps
CPU time 2.79 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:45 PM PST 24
Peak memory 200328 kb
Host smart-fdf04d3f-f65e-4e1b-bd63-41a58f33d8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302546212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.302546212
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.511541787
Short name T130
Test name
Test status
Simulation time 416918574 ps
CPU time 1.97 seconds
Started Mar 05 12:38:44 PM PST 24
Finished Mar 05 12:38:46 PM PST 24
Peak memory 200336 kb
Host smart-c82ecb36-3086-4533-b0ac-b2d93f407b6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511541787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.511541787
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3119860769
Short name T609
Test name
Test status
Simulation time 202280496 ps
CPU time 1.36 seconds
Started Mar 05 12:40:03 PM PST 24
Finished Mar 05 12:40:05 PM PST 24
Peak memory 208284 kb
Host smart-9cc26b44-74cc-4617-8539-d755d21f0ee1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119860769 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3119860769
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3225088591
Short name T551
Test name
Test status
Simulation time 67203535 ps
CPU time 0.77 seconds
Started Mar 05 12:38:48 PM PST 24
Finished Mar 05 12:38:50 PM PST 24
Peak memory 200168 kb
Host smart-ea2634a4-0baa-4aec-b7ae-084adb63df61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225088591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3225088591
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.794977067
Short name T559
Test name
Test status
Simulation time 132456443 ps
CPU time 1.15 seconds
Started Mar 05 12:40:03 PM PST 24
Finished Mar 05 12:40:05 PM PST 24
Peak memory 200032 kb
Host smart-5cac7d52-0923-4629-b2f2-c890e586358d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794977067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.794977067
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1236560670
Short name T588
Test name
Test status
Simulation time 372241826 ps
CPU time 2.77 seconds
Started Mar 05 12:39:40 PM PST 24
Finished Mar 05 12:39:44 PM PST 24
Peak memory 211212 kb
Host smart-15e4f4d6-d6a1-4201-8e84-039826a4b0c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236560670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1236560670
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4052839319
Short name T548
Test name
Test status
Simulation time 178814569 ps
CPU time 1.37 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:43 PM PST 24
Peak memory 208488 kb
Host smart-423ee2ad-b43e-4460-a1a7-1803ac5950c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052839319 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.4052839319
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1564450417
Short name T611
Test name
Test status
Simulation time 62749421 ps
CPU time 0.92 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:43 PM PST 24
Peak memory 198104 kb
Host smart-6a40f1ec-3e3c-4539-ab09-0e61281ac124
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564450417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1564450417
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1610295434
Short name T614
Test name
Test status
Simulation time 136412165 ps
CPU time 1.28 seconds
Started Mar 05 12:38:50 PM PST 24
Finished Mar 05 12:38:51 PM PST 24
Peak memory 200260 kb
Host smart-894872d3-2826-4ab7-bc67-befebd5d24f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610295434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1610295434
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2458345074
Short name T619
Test name
Test status
Simulation time 377874164 ps
CPU time 2.6 seconds
Started Mar 05 12:40:03 PM PST 24
Finished Mar 05 12:40:06 PM PST 24
Peak memory 216584 kb
Host smart-6540a632-3b0c-4461-8072-dc35fd2ecc5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458345074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2458345074
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1576617776
Short name T115
Test name
Test status
Simulation time 503407609 ps
CPU time 2.07 seconds
Started Mar 05 12:38:45 PM PST 24
Finished Mar 05 12:38:48 PM PST 24
Peak memory 200388 kb
Host smart-044349bc-343b-4733-b1a8-906648e95a86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576617776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1576617776
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3364943094
Short name T581
Test name
Test status
Simulation time 100828909 ps
CPU time 1.05 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:44 PM PST 24
Peak memory 208424 kb
Host smart-30dcd538-cafa-4553-93c5-d3741d3ab325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364943094 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3364943094
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3440481894
Short name T606
Test name
Test status
Simulation time 68773875 ps
CPU time 0.88 seconds
Started Mar 05 12:38:39 PM PST 24
Finished Mar 05 12:38:41 PM PST 24
Peak memory 200140 kb
Host smart-24501b6b-0400-4afa-869c-abb3dbef5866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440481894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3440481894
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2653588181
Short name T607
Test name
Test status
Simulation time 100367324 ps
CPU time 1.26 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:43 PM PST 24
Peak memory 200304 kb
Host smart-8b687cdf-927d-4dbb-a79d-4c94a9dc67a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653588181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2653588181
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2606493261
Short name T560
Test name
Test status
Simulation time 298499957 ps
CPU time 2.26 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:45 PM PST 24
Peak memory 208532 kb
Host smart-e51edb13-ea65-4bf0-8155-b3b0685b98b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606493261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2606493261
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3459074277
Short name T567
Test name
Test status
Simulation time 1036631837 ps
CPU time 3.26 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:45 PM PST 24
Peak memory 198348 kb
Host smart-1457d6a6-31e0-4bd8-bad4-60d28bb2d2bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459074277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3459074277
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2189892130
Short name T60
Test name
Test status
Simulation time 199156744 ps
CPU time 1.29 seconds
Started Mar 05 12:38:53 PM PST 24
Finished Mar 05 12:38:54 PM PST 24
Peak memory 208384 kb
Host smart-2794ed7d-b622-4c77-9b47-40f19382c142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189892130 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2189892130
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.527834076
Short name T603
Test name
Test status
Simulation time 62493303 ps
CPU time 0.77 seconds
Started Mar 05 12:38:54 PM PST 24
Finished Mar 05 12:38:55 PM PST 24
Peak memory 200168 kb
Host smart-9bd677b8-72fb-4e2c-a6ee-109c9ff1a117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527834076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.527834076
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4140257286
Short name T584
Test name
Test status
Simulation time 83986226 ps
CPU time 1.04 seconds
Started Mar 05 12:38:58 PM PST 24
Finished Mar 05 12:39:00 PM PST 24
Peak memory 200112 kb
Host smart-b47f3bcf-9c26-4ba7-bfc2-dd4456618a05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140257286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.4140257286
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2462169670
Short name T565
Test name
Test status
Simulation time 161912568 ps
CPU time 2.26 seconds
Started Mar 05 12:40:05 PM PST 24
Finished Mar 05 12:40:07 PM PST 24
Peak memory 208440 kb
Host smart-8263c787-8064-4f24-8f29-05842b5ae835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462169670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2462169670
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.969636537
Short name T594
Test name
Test status
Simulation time 171082491 ps
CPU time 1.64 seconds
Started Mar 05 12:38:48 PM PST 24
Finished Mar 05 12:38:51 PM PST 24
Peak memory 208632 kb
Host smart-14390272-3083-4a2b-a045-c79268d066a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969636537 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.969636537
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.560542285
Short name T569
Test name
Test status
Simulation time 75415537 ps
CPU time 0.8 seconds
Started Mar 05 12:38:40 PM PST 24
Finished Mar 05 12:38:41 PM PST 24
Peak memory 200072 kb
Host smart-5e7771d6-74ca-4c6c-b258-136fa2d61ca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560542285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.560542285
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2958324611
Short name T575
Test name
Test status
Simulation time 80490901 ps
CPU time 1.05 seconds
Started Mar 05 12:38:50 PM PST 24
Finished Mar 05 12:38:52 PM PST 24
Peak memory 200128 kb
Host smart-6f0ad097-41fd-4dd7-a98d-3fb2733604c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958324611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2958324611
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3366748362
Short name T94
Test name
Test status
Simulation time 485359058 ps
CPU time 3.61 seconds
Started Mar 05 12:39:01 PM PST 24
Finished Mar 05 12:39:05 PM PST 24
Peak memory 208516 kb
Host smart-25258a5e-ca3b-4bf3-a940-65da2c9cd103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366748362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3366748362
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2407665007
Short name T616
Test name
Test status
Simulation time 480583289 ps
CPU time 1.9 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:53 PM PST 24
Peak memory 200388 kb
Host smart-3a8001b4-ceb4-40ef-a409-68b7439e68be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407665007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2407665007
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3498837379
Short name T539
Test name
Test status
Simulation time 187192543 ps
CPU time 1.81 seconds
Started Mar 05 12:38:56 PM PST 24
Finished Mar 05 12:38:58 PM PST 24
Peak memory 208632 kb
Host smart-9764c758-424f-4933-926e-c2c15f2f0916
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498837379 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3498837379
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.850334331
Short name T568
Test name
Test status
Simulation time 66077467 ps
CPU time 0.82 seconds
Started Mar 05 12:38:57 PM PST 24
Finished Mar 05 12:38:58 PM PST 24
Peak memory 200144 kb
Host smart-c6e5cb92-fa52-4587-bc26-4cd919fbecb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850334331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.850334331
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2451697159
Short name T553
Test name
Test status
Simulation time 110566905 ps
CPU time 0.96 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:52 PM PST 24
Peak memory 200040 kb
Host smart-0bfaf71d-6a5d-40d1-977f-1fc1921c9de1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451697159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2451697159
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3011063976
Short name T576
Test name
Test status
Simulation time 413788770 ps
CPU time 3.26 seconds
Started Mar 05 12:38:54 PM PST 24
Finished Mar 05 12:38:58 PM PST 24
Peak memory 208720 kb
Host smart-1f14f71d-74f2-4de9-8648-ce1ff44c994c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011063976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3011063976
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4293577028
Short name T578
Test name
Test status
Simulation time 137363056 ps
CPU time 1.42 seconds
Started Mar 05 12:38:46 PM PST 24
Finished Mar 05 12:38:48 PM PST 24
Peak memory 208564 kb
Host smart-7dc79171-44bf-45d4-b884-12fed911cd25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293577028 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.4293577028
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4105527163
Short name T111
Test name
Test status
Simulation time 55531166 ps
CPU time 0.81 seconds
Started Mar 05 12:39:02 PM PST 24
Finished Mar 05 12:39:03 PM PST 24
Peak memory 200160 kb
Host smart-b5f1bf96-ffd7-4ff5-b6ef-3731cd98c140
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105527163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.4105527163
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2102988162
Short name T558
Test name
Test status
Simulation time 152064112 ps
CPU time 1.12 seconds
Started Mar 05 12:38:58 PM PST 24
Finished Mar 05 12:38:59 PM PST 24
Peak memory 200180 kb
Host smart-15926791-211b-4d9f-aecb-a1399cbb7224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102988162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2102988162
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3520864139
Short name T593
Test name
Test status
Simulation time 175579787 ps
CPU time 1.46 seconds
Started Mar 05 12:38:40 PM PST 24
Finished Mar 05 12:38:42 PM PST 24
Peak memory 200092 kb
Host smart-2b9ecb19-3cdb-45ac-9209-50c917950ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520864139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3520864139
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4219601275
Short name T605
Test name
Test status
Simulation time 134366612 ps
CPU time 1.38 seconds
Started Mar 05 12:38:46 PM PST 24
Finished Mar 05 12:38:48 PM PST 24
Peak memory 208824 kb
Host smart-5bd4c218-f666-4cee-87ae-800bea644c72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219601275 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.4219601275
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2266698611
Short name T108
Test name
Test status
Simulation time 66999547 ps
CPU time 0.79 seconds
Started Mar 05 12:39:03 PM PST 24
Finished Mar 05 12:39:04 PM PST 24
Peak memory 200168 kb
Host smart-d7a20c9a-9659-4743-814c-faaa881c13e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266698611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2266698611
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2949208121
Short name T106
Test name
Test status
Simulation time 140939418 ps
CPU time 1.28 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:12 PM PST 24
Peak memory 200256 kb
Host smart-dc5a939e-e432-49a0-8ccc-5510bd9116b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949208121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2949208121
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.376285378
Short name T92
Test name
Test status
Simulation time 165242315 ps
CPU time 2.42 seconds
Started Mar 05 12:39:02 PM PST 24
Finished Mar 05 12:39:05 PM PST 24
Peak memory 208472 kb
Host smart-201b3549-2562-45b0-ba0a-622f13f17217
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376285378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.376285378
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3889380748
Short name T573
Test name
Test status
Simulation time 449446608 ps
CPU time 1.98 seconds
Started Mar 05 12:38:56 PM PST 24
Finished Mar 05 12:38:58 PM PST 24
Peak memory 200396 kb
Host smart-8f25fe37-853a-4a14-aeea-9f5a3f30c111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889380748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3889380748
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2798949291
Short name T617
Test name
Test status
Simulation time 168030782 ps
CPU time 1.45 seconds
Started Mar 05 12:38:57 PM PST 24
Finished Mar 05 12:38:58 PM PST 24
Peak memory 208596 kb
Host smart-cdc4d62b-f2ad-4593-a407-86104b56a8c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798949291 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2798949291
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1539386982
Short name T570
Test name
Test status
Simulation time 76401953 ps
CPU time 0.84 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:44 PM PST 24
Peak memory 200164 kb
Host smart-28f5c7f0-971f-44bb-9daa-fb2f2967bc8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539386982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1539386982
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1796384427
Short name T612
Test name
Test status
Simulation time 285577489 ps
CPU time 1.77 seconds
Started Mar 05 12:38:59 PM PST 24
Finished Mar 05 12:39:01 PM PST 24
Peak memory 200360 kb
Host smart-fa7043ef-d929-4614-9915-664a27f04a30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796384427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1796384427
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3515455812
Short name T580
Test name
Test status
Simulation time 193241853 ps
CPU time 1.64 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:53 PM PST 24
Peak memory 216604 kb
Host smart-869a2f7c-9604-49f8-abbd-818d2c9fd55c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515455812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3515455812
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4188641913
Short name T591
Test name
Test status
Simulation time 805211067 ps
CPU time 2.88 seconds
Started Mar 05 12:38:54 PM PST 24
Finished Mar 05 12:38:57 PM PST 24
Peak memory 200396 kb
Host smart-4a34f703-53f5-444b-8245-2bc3f411e41b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188641913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.4188641913
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3848027687
Short name T58
Test name
Test status
Simulation time 206277731 ps
CPU time 1.64 seconds
Started Mar 05 12:38:43 PM PST 24
Finished Mar 05 12:38:46 PM PST 24
Peak memory 200312 kb
Host smart-10495619-aef8-4c34-b9c1-d0c2768a575d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848027687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
848027687
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3868541141
Short name T131
Test name
Test status
Simulation time 276275620 ps
CPU time 3.35 seconds
Started Mar 05 12:38:24 PM PST 24
Finished Mar 05 12:38:27 PM PST 24
Peak memory 200340 kb
Host smart-6d147704-69e9-4506-b517-634f2e0fdf76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868541141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
868541141
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2585258913
Short name T543
Test name
Test status
Simulation time 149657698 ps
CPU time 0.94 seconds
Started Mar 05 12:38:21 PM PST 24
Finished Mar 05 12:38:23 PM PST 24
Peak memory 200128 kb
Host smart-a446cc10-92fc-4272-b562-b5d31c4a9c6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585258913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
585258913
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2768800633
Short name T561
Test name
Test status
Simulation time 135072921 ps
CPU time 1.1 seconds
Started Mar 05 12:38:37 PM PST 24
Finished Mar 05 12:38:38 PM PST 24
Peak memory 208344 kb
Host smart-12880645-9865-4318-874f-9e4c9fea92b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768800633 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2768800633
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2885846246
Short name T556
Test name
Test status
Simulation time 63741855 ps
CPU time 0.79 seconds
Started Mar 05 12:38:34 PM PST 24
Finished Mar 05 12:38:34 PM PST 24
Peak memory 200156 kb
Host smart-2069407f-f2e9-465b-b0c6-69bd89332ac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885846246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2885846246
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.936649307
Short name T57
Test name
Test status
Simulation time 127661196 ps
CPU time 1.12 seconds
Started Mar 05 12:38:40 PM PST 24
Finished Mar 05 12:38:42 PM PST 24
Peak memory 200168 kb
Host smart-2e69562c-e979-4f18-b7c9-608a2b13da23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936649307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.936649307
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.226044293
Short name T564
Test name
Test status
Simulation time 492863840 ps
CPU time 3.48 seconds
Started Mar 05 12:38:39 PM PST 24
Finished Mar 05 12:38:53 PM PST 24
Peak memory 216636 kb
Host smart-85de181a-e986-4a63-8700-7352a50edb63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226044293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.226044293
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.740236429
Short name T550
Test name
Test status
Simulation time 956695578 ps
CPU time 3.28 seconds
Started Mar 05 12:38:51 PM PST 24
Finished Mar 05 12:38:59 PM PST 24
Peak memory 200388 kb
Host smart-51e45ed3-3617-4969-a1df-449f5a8a1aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740236429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
740236429
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3304476784
Short name T598
Test name
Test status
Simulation time 200648574 ps
CPU time 1.6 seconds
Started Mar 05 12:38:26 PM PST 24
Finished Mar 05 12:38:28 PM PST 24
Peak memory 200256 kb
Host smart-6ae2e8a2-287f-4994-acc7-693780c2fe37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304476784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
304476784
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.765712836
Short name T589
Test name
Test status
Simulation time 2289175271 ps
CPU time 9.54 seconds
Started Mar 05 12:38:43 PM PST 24
Finished Mar 05 12:38:54 PM PST 24
Peak memory 200392 kb
Host smart-3159c3b5-6ca5-4980-aad8-a77a52426af9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765712836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.765712836
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3052923753
Short name T572
Test name
Test status
Simulation time 108743118 ps
CPU time 0.85 seconds
Started Mar 05 12:38:29 PM PST 24
Finished Mar 05 12:38:30 PM PST 24
Peak memory 200064 kb
Host smart-ceb1679a-6564-4e98-8089-3f071db4366c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052923753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
052923753
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3225784859
Short name T93
Test name
Test status
Simulation time 133914720 ps
CPU time 1.5 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:45 PM PST 24
Peak memory 208584 kb
Host smart-bc69d471-aed1-4a8b-9f86-849abc51ede3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225784859 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3225784859
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2312504504
Short name T599
Test name
Test status
Simulation time 73521824 ps
CPU time 0.86 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:44 PM PST 24
Peak memory 200144 kb
Host smart-8a6d33d2-9255-4dd5-a8ad-aea284871739
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312504504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2312504504
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4162554226
Short name T583
Test name
Test status
Simulation time 86113156 ps
CPU time 0.96 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:43 PM PST 24
Peak memory 200144 kb
Host smart-a4707b8a-6e9f-422b-8f20-f5727aba3ec2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162554226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4162554226
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.845233709
Short name T65
Test name
Test status
Simulation time 104531774 ps
CPU time 1.52 seconds
Started Mar 05 12:38:37 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 200320 kb
Host smart-c1b6a045-7249-4d96-9b38-b82190514829
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845233709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.845233709
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2004616893
Short name T582
Test name
Test status
Simulation time 446289793 ps
CPU time 2.87 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 200488 kb
Host smart-173e6be2-c81d-4469-97a8-4783def423c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004616893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
004616893
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.378801941
Short name T538
Test name
Test status
Simulation time 2278879652 ps
CPU time 9.93 seconds
Started Mar 05 12:38:52 PM PST 24
Finished Mar 05 12:39:02 PM PST 24
Peak memory 200408 kb
Host smart-0f5e8150-3bce-44ef-8b62-6cac8334413e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378801941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.378801941
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.208864023
Short name T554
Test name
Test status
Simulation time 94074325 ps
CPU time 0.88 seconds
Started Mar 05 12:38:35 PM PST 24
Finished Mar 05 12:38:36 PM PST 24
Peak memory 200164 kb
Host smart-5a12ac93-5d6c-4f97-ade4-ecf223e44245
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208864023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.208864023
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.435530779
Short name T618
Test name
Test status
Simulation time 159414082 ps
CPU time 1.32 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:38 PM PST 24
Peak memory 200208 kb
Host smart-56cf81f2-a572-44b2-a883-c45453657bd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435530779 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.435530779
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3921096730
Short name T545
Test name
Test status
Simulation time 78772665 ps
CPU time 0.82 seconds
Started Mar 05 12:38:30 PM PST 24
Finished Mar 05 12:38:32 PM PST 24
Peak memory 200160 kb
Host smart-c0cbd4a7-336a-4e55-a863-fac93143db61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921096730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3921096730
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1155700133
Short name T597
Test name
Test status
Simulation time 87574615 ps
CPU time 0.95 seconds
Started Mar 05 12:40:05 PM PST 24
Finished Mar 05 12:40:07 PM PST 24
Peak memory 200104 kb
Host smart-cc87abd2-a4cf-48d7-8ad9-f5900ce7644e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155700133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1155700133
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1512212685
Short name T602
Test name
Test status
Simulation time 225749056 ps
CPU time 1.71 seconds
Started Mar 05 12:38:22 PM PST 24
Finished Mar 05 12:38:25 PM PST 24
Peak memory 207264 kb
Host smart-2a2a8cf9-876d-4eda-a713-0b6d5babe7be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512212685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1512212685
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3104218858
Short name T120
Test name
Test status
Simulation time 480078145 ps
CPU time 1.91 seconds
Started Mar 05 12:38:38 PM PST 24
Finished Mar 05 12:38:40 PM PST 24
Peak memory 200264 kb
Host smart-dc6b1464-ba6f-40c1-9a3b-0cbadd272d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104218858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3104218858
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3838939610
Short name T555
Test name
Test status
Simulation time 126781378 ps
CPU time 1.39 seconds
Started Mar 05 12:38:49 PM PST 24
Finished Mar 05 12:38:51 PM PST 24
Peak memory 208384 kb
Host smart-651661ef-1123-4f8a-8860-a12c0a01345f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838939610 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3838939610
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3647205010
Short name T109
Test name
Test status
Simulation time 58363468 ps
CPU time 0.85 seconds
Started Mar 05 12:38:47 PM PST 24
Finished Mar 05 12:38:48 PM PST 24
Peak memory 200236 kb
Host smart-264ef376-968d-4ae1-bf7b-8d8a85095577
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647205010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3647205010
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.288654121
Short name T107
Test name
Test status
Simulation time 214198965 ps
CPU time 1.64 seconds
Started Mar 05 12:38:47 PM PST 24
Finished Mar 05 12:38:49 PM PST 24
Peak memory 200308 kb
Host smart-43841036-446f-4e65-925d-e1a8d171f84c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288654121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.288654121
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3828719880
Short name T91
Test name
Test status
Simulation time 294899976 ps
CPU time 2.41 seconds
Started Mar 05 12:39:52 PM PST 24
Finished Mar 05 12:39:55 PM PST 24
Peak memory 208536 kb
Host smart-69d1c201-68b2-4fab-ae2d-58a644fe7b65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828719880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3828719880
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3172066153
Short name T541
Test name
Test status
Simulation time 445041744 ps
CPU time 1.76 seconds
Started Mar 05 12:38:56 PM PST 24
Finished Mar 05 12:38:57 PM PST 24
Peak memory 200336 kb
Host smart-942abc01-67d1-4327-b232-bae1357dce41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172066153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3172066153
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3112230423
Short name T590
Test name
Test status
Simulation time 135656746 ps
CPU time 1.26 seconds
Started Mar 05 12:40:01 PM PST 24
Finished Mar 05 12:40:02 PM PST 24
Peak memory 208364 kb
Host smart-701635e8-0cc4-463a-80ab-a2bbd3deda1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112230423 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3112230423
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2564291987
Short name T586
Test name
Test status
Simulation time 72455644 ps
CPU time 0.86 seconds
Started Mar 05 12:38:45 PM PST 24
Finished Mar 05 12:38:47 PM PST 24
Peak memory 200096 kb
Host smart-85f9141b-4d9f-4827-a939-fa38fe97267a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564291987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2564291987
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.815907000
Short name T596
Test name
Test status
Simulation time 79987604 ps
CPU time 1 seconds
Started Mar 05 12:38:35 PM PST 24
Finished Mar 05 12:38:36 PM PST 24
Peak memory 200216 kb
Host smart-e1c0252d-3f0f-4b8c-8aea-71e889214580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815907000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.815907000
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1736821172
Short name T579
Test name
Test status
Simulation time 429820166 ps
CPU time 1.68 seconds
Started Mar 05 12:38:33 PM PST 24
Finished Mar 05 12:38:34 PM PST 24
Peak memory 200220 kb
Host smart-b2fffc5a-3bd9-4b1f-9e0d-404ab77d14db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736821172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1736821172
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.393515003
Short name T544
Test name
Test status
Simulation time 131824228 ps
CPU time 0.92 seconds
Started Mar 05 12:39:35 PM PST 24
Finished Mar 05 12:39:36 PM PST 24
Peak memory 200144 kb
Host smart-94475724-6fa7-49ec-9f51-990cd774b445
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393515003 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.393515003
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3967827709
Short name T574
Test name
Test status
Simulation time 80037043 ps
CPU time 0.82 seconds
Started Mar 05 12:38:37 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 200096 kb
Host smart-2d01af9f-33c4-4b2b-8ed4-c711ff5af8dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967827709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3967827709
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3144300440
Short name T112
Test name
Test status
Simulation time 110080836 ps
CPU time 1.25 seconds
Started Mar 05 12:38:43 PM PST 24
Finished Mar 05 12:38:45 PM PST 24
Peak memory 200392 kb
Host smart-3acd8481-118c-4a2c-baa8-dcb8e0261cf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144300440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3144300440
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2621905257
Short name T557
Test name
Test status
Simulation time 502358747 ps
CPU time 3.06 seconds
Started Mar 05 12:38:37 PM PST 24
Finished Mar 05 12:38:41 PM PST 24
Peak memory 208548 kb
Host smart-8ae55c9b-2acd-4179-8c7b-c9fb18388880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621905257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2621905257
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3711226717
Short name T615
Test name
Test status
Simulation time 433985995 ps
CPU time 2.02 seconds
Started Mar 05 12:38:37 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 200356 kb
Host smart-ce5a9134-9909-4866-813d-fabe12a60f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711226717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3711226717
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1435342285
Short name T537
Test name
Test status
Simulation time 182455833 ps
CPU time 1.32 seconds
Started Mar 05 12:38:43 PM PST 24
Finished Mar 05 12:38:45 PM PST 24
Peak memory 208480 kb
Host smart-f8f0edaf-4c55-4b6d-b4e7-265ee58b2340
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435342285 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1435342285
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1433163519
Short name T546
Test name
Test status
Simulation time 62442967 ps
CPU time 0.79 seconds
Started Mar 05 12:38:28 PM PST 24
Finished Mar 05 12:38:29 PM PST 24
Peak memory 200140 kb
Host smart-be30d2b8-add5-4a75-a2bd-bc2657816e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433163519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1433163519
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.50415994
Short name T601
Test name
Test status
Simulation time 176237004 ps
CPU time 1.36 seconds
Started Mar 05 12:40:01 PM PST 24
Finished Mar 05 12:40:03 PM PST 24
Peak memory 200324 kb
Host smart-a6734a2f-a8bf-4079-8e67-a25de625e612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50415994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same
_csr_outstanding.50415994
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2094715477
Short name T577
Test name
Test status
Simulation time 388820756 ps
CPU time 2.9 seconds
Started Mar 05 12:38:56 PM PST 24
Finished Mar 05 12:38:59 PM PST 24
Peak memory 208552 kb
Host smart-6bce245c-8863-435f-8acf-5d14cbeef46b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094715477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2094715477
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1390629783
Short name T116
Test name
Test status
Simulation time 867829044 ps
CPU time 2.93 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 200444 kb
Host smart-f4665c10-7dbd-4633-8182-1fe86ffcc864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390629783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1390629783
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2419989490
Short name T592
Test name
Test status
Simulation time 104331682 ps
CPU time 0.9 seconds
Started Mar 05 12:39:50 PM PST 24
Finished Mar 05 12:39:51 PM PST 24
Peak memory 200216 kb
Host smart-3d2b8691-6257-4683-aac0-8b0f2f2408a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419989490 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2419989490
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2889466691
Short name T587
Test name
Test status
Simulation time 70856788 ps
CPU time 0.82 seconds
Started Mar 05 12:38:42 PM PST 24
Finished Mar 05 12:38:45 PM PST 24
Peak memory 200100 kb
Host smart-b8a7c863-a09b-475d-85b0-38da45ee4ffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889466691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2889466691
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1989637214
Short name T105
Test name
Test status
Simulation time 112734674 ps
CPU time 0.98 seconds
Started Mar 05 12:39:49 PM PST 24
Finished Mar 05 12:39:51 PM PST 24
Peak memory 200172 kb
Host smart-41bf3199-7924-448c-a98f-9dfcd483d5ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989637214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1989637214
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4185221481
Short name T542
Test name
Test status
Simulation time 490574656 ps
CPU time 3.41 seconds
Started Mar 05 12:38:32 PM PST 24
Finished Mar 05 12:38:36 PM PST 24
Peak memory 208472 kb
Host smart-913580ba-d314-4b77-8a1b-3eeb0a76f25b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185221481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4185221481
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.728705874
Short name T571
Test name
Test status
Simulation time 457528980 ps
CPU time 1.89 seconds
Started Mar 05 12:38:49 PM PST 24
Finished Mar 05 12:38:51 PM PST 24
Peak memory 200392 kb
Host smart-d73d87d8-2aaa-4e93-877c-e206a647fb0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728705874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
728705874
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4215160005
Short name T517
Test name
Test status
Simulation time 244450643 ps
CPU time 1.1 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 217216 kb
Host smart-54f9a2ab-bb57-40a8-916f-16c910a37119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215160005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4215160005
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1862684774
Short name T491
Test name
Test status
Simulation time 128155218 ps
CPU time 0.83 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:41:39 PM PST 24
Peak memory 200052 kb
Host smart-a341e85f-43eb-49a1-bdea-cdd528d70e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862684774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1862684774
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2094289100
Short name T13
Test name
Test status
Simulation time 1388549602 ps
CPU time 5.88 seconds
Started Mar 05 12:41:32 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200568 kb
Host smart-a5f300a1-f72d-42e4-8b0b-7ce9e54a5558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094289100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2094289100
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1085837528
Short name T71
Test name
Test status
Simulation time 8289388037 ps
CPU time 15.23 seconds
Started Mar 05 12:41:30 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 217416 kb
Host smart-39fab53b-5699-4ede-a6cd-27c89c7bf4d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085837528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1085837528
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2002075200
Short name T309
Test name
Test status
Simulation time 115443148 ps
CPU time 1.12 seconds
Started Mar 05 12:41:19 PM PST 24
Finished Mar 05 12:41:20 PM PST 24
Peak memory 200404 kb
Host smart-a105b5b4-3f64-4a57-9e8c-fa34fced587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002075200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2002075200
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1015230957
Short name T103
Test name
Test status
Simulation time 9130605517 ps
CPU time 39.54 seconds
Started Mar 05 12:41:17 PM PST 24
Finished Mar 05 12:41:57 PM PST 24
Peak memory 208616 kb
Host smart-85114eaf-09bb-4868-91b7-a24aeb4b9bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015230957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1015230957
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1891483741
Short name T185
Test name
Test status
Simulation time 148788104 ps
CPU time 1.92 seconds
Started Mar 05 12:41:20 PM PST 24
Finished Mar 05 12:41:23 PM PST 24
Peak memory 200252 kb
Host smart-f4b7a081-b2ff-4ed7-8faf-9a499af56524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891483741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1891483741
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3244294529
Short name T222
Test name
Test status
Simulation time 83196778 ps
CPU time 0.8 seconds
Started Mar 05 12:41:24 PM PST 24
Finished Mar 05 12:41:25 PM PST 24
Peak memory 200124 kb
Host smart-288eca3b-ed7d-4280-8330-0480eb96b7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244294529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3244294529
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1017986095
Short name T27
Test name
Test status
Simulation time 1230591515 ps
CPU time 5.93 seconds
Started Mar 05 12:41:24 PM PST 24
Finished Mar 05 12:41:30 PM PST 24
Peak memory 217016 kb
Host smart-13af2237-a16f-4c71-b583-acf6541abd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017986095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1017986095
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.109284857
Short name T529
Test name
Test status
Simulation time 243867292 ps
CPU time 1.15 seconds
Started Mar 05 12:41:29 PM PST 24
Finished Mar 05 12:41:31 PM PST 24
Peak memory 217084 kb
Host smart-91f23e82-bc51-45d0-9e96-5e66eac2b966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109284857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.109284857
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.722521129
Short name T398
Test name
Test status
Simulation time 182114885 ps
CPU time 0.84 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 200016 kb
Host smart-6116f4fe-c100-46db-89aa-4954924bda56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722521129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.722521129
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.107875152
Short name T448
Test name
Test status
Simulation time 1656286927 ps
CPU time 5.84 seconds
Started Mar 05 12:41:18 PM PST 24
Finished Mar 05 12:41:23 PM PST 24
Peak memory 200484 kb
Host smart-94b953a1-1920-40c0-a1f3-6e8d265ef95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107875152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.107875152
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1287679123
Short name T216
Test name
Test status
Simulation time 171077432 ps
CPU time 1.17 seconds
Started Mar 05 12:41:30 PM PST 24
Finished Mar 05 12:41:31 PM PST 24
Peak memory 200500 kb
Host smart-3094037c-7739-4a25-8064-2a0be2650b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287679123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1287679123
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3827392930
Short name T365
Test name
Test status
Simulation time 257619121 ps
CPU time 1.45 seconds
Started Mar 05 12:41:15 PM PST 24
Finished Mar 05 12:41:17 PM PST 24
Peak memory 200360 kb
Host smart-e3248982-a8b7-42ac-a7ba-c24a09448f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827392930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3827392930
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3762722230
Short name T352
Test name
Test status
Simulation time 2681561723 ps
CPU time 12.88 seconds
Started Mar 05 12:41:34 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 200468 kb
Host smart-3335e621-4330-4314-81cd-cf4500f71ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762722230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3762722230
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3832461448
Short name T266
Test name
Test status
Simulation time 130732024 ps
CPU time 1.64 seconds
Started Mar 05 12:41:31 PM PST 24
Finished Mar 05 12:41:33 PM PST 24
Peak memory 200244 kb
Host smart-569986a2-ee11-45d2-8ad4-fd2fbf0c4a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832461448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3832461448
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.583921225
Short name T431
Test name
Test status
Simulation time 137689882 ps
CPU time 1.03 seconds
Started Mar 05 12:41:26 PM PST 24
Finished Mar 05 12:41:27 PM PST 24
Peak memory 200136 kb
Host smart-3b916689-ad07-4f63-915e-5c7a72051d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583921225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.583921225
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1548239926
Short name T249
Test name
Test status
Simulation time 74277209 ps
CPU time 0.75 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 200052 kb
Host smart-c15c7a11-e0b8-45b8-8350-a6675f0891cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548239926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1548239926
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3835590205
Short name T424
Test name
Test status
Simulation time 2339793503 ps
CPU time 8.42 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:42 PM PST 24
Peak memory 217016 kb
Host smart-92d92f46-50b5-4805-b0a9-9b5afcad6d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835590205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3835590205
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2377114537
Short name T270
Test name
Test status
Simulation time 244663064 ps
CPU time 1.08 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 217128 kb
Host smart-a83075df-72e1-45cb-ae23-f7bdb10a3a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377114537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2377114537
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3643143653
Short name T454
Test name
Test status
Simulation time 117321158 ps
CPU time 0.82 seconds
Started Mar 05 12:41:32 PM PST 24
Finished Mar 05 12:41:33 PM PST 24
Peak memory 200052 kb
Host smart-61cb87a0-91de-4757-a943-e3773243d999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643143653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3643143653
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2041360420
Short name T142
Test name
Test status
Simulation time 995029744 ps
CPU time 5.64 seconds
Started Mar 05 12:41:26 PM PST 24
Finished Mar 05 12:41:32 PM PST 24
Peak memory 200396 kb
Host smart-a084ef42-8be4-4f9f-bdd5-1bde3839870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041360420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2041360420
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2618875231
Short name T349
Test name
Test status
Simulation time 107494987 ps
CPU time 1.04 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:41:40 PM PST 24
Peak memory 200336 kb
Host smart-305ba6df-62bb-479b-9536-affb215c4650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618875231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2618875231
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2170531610
Short name T486
Test name
Test status
Simulation time 195285352 ps
CPU time 1.34 seconds
Started Mar 05 12:41:27 PM PST 24
Finished Mar 05 12:41:29 PM PST 24
Peak memory 200364 kb
Host smart-8cb18e00-c8f5-430f-b290-95932d44224c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170531610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2170531610
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2433307816
Short name T345
Test name
Test status
Simulation time 203825354 ps
CPU time 1.43 seconds
Started Mar 05 12:41:39 PM PST 24
Finished Mar 05 12:41:40 PM PST 24
Peak memory 200356 kb
Host smart-eb594eb5-3016-475e-80bf-b47656bb1834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433307816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2433307816
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2919676923
Short name T145
Test name
Test status
Simulation time 360283162 ps
CPU time 2.32 seconds
Started Mar 05 12:41:25 PM PST 24
Finished Mar 05 12:41:27 PM PST 24
Peak memory 200192 kb
Host smart-d2704de7-e449-4b22-82b1-73b31e76995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919676923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2919676923
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1233253345
Short name T532
Test name
Test status
Simulation time 256744510 ps
CPU time 1.5 seconds
Started Mar 05 12:41:32 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 200380 kb
Host smart-0c499a94-beda-41e3-bcf8-6bfd54331e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233253345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1233253345
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.4233243588
Short name T322
Test name
Test status
Simulation time 69206450 ps
CPU time 0.76 seconds
Started Mar 05 12:41:28 PM PST 24
Finished Mar 05 12:41:29 PM PST 24
Peak memory 200156 kb
Host smart-ca56f667-e940-4acb-9e72-2a7c26c285f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233243588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.4233243588
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4057066281
Short name T480
Test name
Test status
Simulation time 1899249545 ps
CPU time 6.95 seconds
Started Mar 05 12:42:00 PM PST 24
Finished Mar 05 12:42:08 PM PST 24
Peak memory 220936 kb
Host smart-d4277c39-9ae6-4563-8078-5309ae440818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057066281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4057066281
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.341565949
Short name T245
Test name
Test status
Simulation time 244903703 ps
CPU time 1.02 seconds
Started Mar 05 12:41:50 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 217080 kb
Host smart-95d0c7e8-ece8-49fd-a470-d146613284b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341565949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.341565949
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.909633100
Short name T306
Test name
Test status
Simulation time 124163251 ps
CPU time 0.79 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 200160 kb
Host smart-fe9c5f1d-9ff1-48f0-abde-1fe98e4f384f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909633100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.909633100
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1962783299
Short name T191
Test name
Test status
Simulation time 1667125089 ps
CPU time 6.48 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:41:45 PM PST 24
Peak memory 200496 kb
Host smart-318a45e1-1909-4dc2-b404-1967f8149c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962783299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1962783299
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2237013493
Short name T23
Test name
Test status
Simulation time 94652579 ps
CPU time 0.97 seconds
Started Mar 05 12:41:50 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 200220 kb
Host smart-56034a30-2edc-4e37-a90b-da0805a2b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237013493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2237013493
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2212626577
Short name T25
Test name
Test status
Simulation time 259706670 ps
CPU time 1.59 seconds
Started Mar 05 12:41:52 PM PST 24
Finished Mar 05 12:41:54 PM PST 24
Peak memory 200360 kb
Host smart-106583b5-34d4-4140-93b3-09ac30d76e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212626577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2212626577
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1723250729
Short name T208
Test name
Test status
Simulation time 5647028778 ps
CPU time 25.78 seconds
Started Mar 05 12:41:53 PM PST 24
Finished Mar 05 12:42:19 PM PST 24
Peak memory 200524 kb
Host smart-02e6c685-50c9-4e9d-8823-9c6c62f21035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723250729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1723250729
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.127868136
Short name T134
Test name
Test status
Simulation time 131873436 ps
CPU time 1.6 seconds
Started Mar 05 12:41:36 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 208480 kb
Host smart-0991b8b6-57d0-41c5-bc7c-c761ed06de4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127868136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.127868136
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.4246276437
Short name T160
Test name
Test status
Simulation time 114732799 ps
CPU time 1.04 seconds
Started Mar 05 12:41:58 PM PST 24
Finished Mar 05 12:41:59 PM PST 24
Peak memory 200368 kb
Host smart-be24dc7f-013c-4ec7-8869-5c48045d724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246276437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.4246276437
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.760745626
Short name T252
Test name
Test status
Simulation time 79199028 ps
CPU time 0.78 seconds
Started Mar 05 12:41:46 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 200160 kb
Host smart-db192be9-e291-4f57-8fe2-2c066edf059e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760745626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.760745626
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3856848437
Short name T466
Test name
Test status
Simulation time 1228379824 ps
CPU time 5.33 seconds
Started Mar 05 12:41:35 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 218148 kb
Host smart-cdb16639-d34e-4e99-ade9-69e22c83fc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856848437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3856848437
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4188581579
Short name T363
Test name
Test status
Simulation time 244997518 ps
CPU time 1.04 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:41:50 PM PST 24
Peak memory 217248 kb
Host smart-0ef4ed51-2511-4844-9ea8-61c8ada79b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188581579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.4188581579
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.4158548043
Short name T148
Test name
Test status
Simulation time 114788701 ps
CPU time 0.8 seconds
Started Mar 05 12:41:55 PM PST 24
Finished Mar 05 12:41:56 PM PST 24
Peak memory 200168 kb
Host smart-e4f43bce-aff5-475a-b6a7-f7813b2fff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158548043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.4158548043
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2577155338
Short name T172
Test name
Test status
Simulation time 1264789834 ps
CPU time 5.14 seconds
Started Mar 05 12:41:52 PM PST 24
Finished Mar 05 12:41:57 PM PST 24
Peak memory 200428 kb
Host smart-ba6e4435-9737-46b8-9b48-a24d47275a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577155338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2577155338
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.176557975
Short name T468
Test name
Test status
Simulation time 115734902 ps
CPU time 1.08 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 200312 kb
Host smart-927c5c6d-4be0-4af5-bb7b-456f6acce70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176557975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.176557975
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1925377961
Short name T125
Test name
Test status
Simulation time 234154411 ps
CPU time 1.49 seconds
Started Mar 05 12:41:47 PM PST 24
Finished Mar 05 12:41:48 PM PST 24
Peak memory 200368 kb
Host smart-4704a936-8ca6-4d30-b6c2-d510c2a54295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925377961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1925377961
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3340165335
Short name T368
Test name
Test status
Simulation time 2653348908 ps
CPU time 9.24 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 200576 kb
Host smart-abc4b71f-44d3-46e2-9811-1dc0438b6af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340165335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3340165335
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1315376668
Short name T404
Test name
Test status
Simulation time 132366185 ps
CPU time 1.67 seconds
Started Mar 05 12:41:50 PM PST 24
Finished Mar 05 12:41:52 PM PST 24
Peak memory 200188 kb
Host smart-d2cc2151-82c9-49ce-aeba-55b82d14a413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315376668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1315376668
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.4008280439
Short name T326
Test name
Test status
Simulation time 126777366 ps
CPU time 0.99 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:41:50 PM PST 24
Peak memory 200252 kb
Host smart-fea64c10-3462-4c88-bc04-dbee1a49650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008280439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.4008280439
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2358435642
Short name T285
Test name
Test status
Simulation time 64612607 ps
CPU time 0.77 seconds
Started Mar 05 12:41:55 PM PST 24
Finished Mar 05 12:41:56 PM PST 24
Peak memory 200252 kb
Host smart-87667516-c58f-41cf-899b-a34e1937b33b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358435642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2358435642
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2683839065
Short name T535
Test name
Test status
Simulation time 1908675156 ps
CPU time 7.76 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:53 PM PST 24
Peak memory 216524 kb
Host smart-2de7020c-7864-4fe4-9230-31c479036064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683839065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2683839065
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3517683422
Short name T425
Test name
Test status
Simulation time 245484210 ps
CPU time 1.05 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:41:40 PM PST 24
Peak memory 217164 kb
Host smart-7a7e8487-1208-4de3-b666-d715badec042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517683422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3517683422
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.662151860
Short name T504
Test name
Test status
Simulation time 177197011 ps
CPU time 0.84 seconds
Started Mar 05 12:41:37 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200056 kb
Host smart-e8daf7bd-f267-4317-9432-ec4e96dc7a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662151860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.662151860
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.676164823
Short name T413
Test name
Test status
Simulation time 1441243776 ps
CPU time 5.99 seconds
Started Mar 05 12:41:46 PM PST 24
Finished Mar 05 12:41:53 PM PST 24
Peak memory 200412 kb
Host smart-b71f6fce-a9dc-4270-8f79-3c91f0d84c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676164823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.676164823
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2880443406
Short name T135
Test name
Test status
Simulation time 98491057 ps
CPU time 0.95 seconds
Started Mar 05 12:41:47 PM PST 24
Finished Mar 05 12:41:48 PM PST 24
Peak memory 200260 kb
Host smart-dbac270c-c311-4916-8cc6-2c48ed42e161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880443406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2880443406
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3127868295
Short name T496
Test name
Test status
Simulation time 196324145 ps
CPU time 1.33 seconds
Started Mar 05 12:42:02 PM PST 24
Finished Mar 05 12:42:03 PM PST 24
Peak memory 200344 kb
Host smart-6197dcb8-85bd-41eb-a9ac-66a7b24d5260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127868295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3127868295
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3228520020
Short name T90
Test name
Test status
Simulation time 7000121824 ps
CPU time 31.55 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:42:10 PM PST 24
Peak memory 209396 kb
Host smart-603ff6db-f6a2-4ad8-b599-99980001d29f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228520020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3228520020
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3075441057
Short name T401
Test name
Test status
Simulation time 130867230 ps
CPU time 1.59 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 208724 kb
Host smart-c9ad7ade-9300-4286-8927-05dabd1534a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075441057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3075441057
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4000036803
Short name T314
Test name
Test status
Simulation time 226356110 ps
CPU time 1.34 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:42 PM PST 24
Peak memory 200252 kb
Host smart-3791575a-f1d4-4ed9-b521-de00e717f438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000036803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4000036803
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3898883863
Short name T163
Test name
Test status
Simulation time 72190604 ps
CPU time 0.8 seconds
Started Mar 05 12:41:47 PM PST 24
Finished Mar 05 12:41:48 PM PST 24
Peak memory 200268 kb
Host smart-051aca03-8b45-4964-af01-3f4e5f293b1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898883863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3898883863
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3185519016
Short name T34
Test name
Test status
Simulation time 1886594508 ps
CPU time 7.07 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:52 PM PST 24
Peak memory 218248 kb
Host smart-1cc03c9d-bcb5-4512-bd0f-1709dc3146de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185519016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3185519016
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3957411642
Short name T329
Test name
Test status
Simulation time 244158287 ps
CPU time 1.06 seconds
Started Mar 05 12:42:00 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 217084 kb
Host smart-70978132-47f4-47d4-8e67-1bfaacedb098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957411642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3957411642
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3624358896
Short name T152
Test name
Test status
Simulation time 161147522 ps
CPU time 0.86 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 200048 kb
Host smart-8eb74dc0-9c4f-4e87-9a72-becf3fbcb75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624358896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3624358896
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1869335899
Short name T122
Test name
Test status
Simulation time 1740001855 ps
CPU time 6.45 seconds
Started Mar 05 12:41:41 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 200400 kb
Host smart-cef2e54d-0cc6-4474-bf06-ef04aac06355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869335899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1869335899
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.554247489
Short name T383
Test name
Test status
Simulation time 159119072 ps
CPU time 1.1 seconds
Started Mar 05 12:41:41 PM PST 24
Finished Mar 05 12:41:43 PM PST 24
Peak memory 200256 kb
Host smart-f949f9df-988b-46f1-a2b2-72012f04fcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554247489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.554247489
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1737770344
Short name T173
Test name
Test status
Simulation time 198321049 ps
CPU time 1.43 seconds
Started Mar 05 12:41:41 PM PST 24
Finished Mar 05 12:41:43 PM PST 24
Peak memory 200504 kb
Host smart-df1c2295-4540-4612-b924-f26825f31cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737770344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1737770344
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2114982462
Short name T441
Test name
Test status
Simulation time 206201004 ps
CPU time 1.19 seconds
Started Mar 05 12:41:44 PM PST 24
Finished Mar 05 12:41:45 PM PST 24
Peak memory 200264 kb
Host smart-4d587ea9-b16c-44da-ab29-6f18f055df3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114982462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2114982462
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2594235719
Short name T520
Test name
Test status
Simulation time 273784441 ps
CPU time 1.97 seconds
Started Mar 05 12:41:41 PM PST 24
Finished Mar 05 12:41:43 PM PST 24
Peak memory 200192 kb
Host smart-84a34b78-59af-4f9d-9409-cbc68e656c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594235719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2594235719
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1273399422
Short name T75
Test name
Test status
Simulation time 270735468 ps
CPU time 1.6 seconds
Started Mar 05 12:41:37 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200128 kb
Host smart-9e101707-2133-4792-ac19-05375eaee3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273399422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1273399422
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2710328807
Short name T492
Test name
Test status
Simulation time 63163915 ps
CPU time 0.8 seconds
Started Mar 05 12:42:05 PM PST 24
Finished Mar 05 12:42:06 PM PST 24
Peak memory 200156 kb
Host smart-bdb4062a-06cb-4ac6-814c-e4835c760bfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710328807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2710328807
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3612106010
Short name T536
Test name
Test status
Simulation time 1217949306 ps
CPU time 6.24 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:52 PM PST 24
Peak memory 221748 kb
Host smart-9bc13dc2-1bdd-4513-b039-cde4cce603cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612106010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3612106010
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3593262748
Short name T269
Test name
Test status
Simulation time 243996655 ps
CPU time 1.18 seconds
Started Mar 05 12:41:50 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 217168 kb
Host smart-663df006-80da-488b-ac6d-e6855a4edfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593262748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3593262748
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3630337550
Short name T291
Test name
Test status
Simulation time 202359327 ps
CPU time 0.9 seconds
Started Mar 05 12:41:37 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200056 kb
Host smart-70daa39a-addf-495c-82bd-b979603599f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630337550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3630337550
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.598289187
Short name T460
Test name
Test status
Simulation time 1650256358 ps
CPU time 6.08 seconds
Started Mar 05 12:41:43 PM PST 24
Finished Mar 05 12:41:54 PM PST 24
Peak memory 200552 kb
Host smart-f55174cd-75a1-47f9-8ad6-9501549610ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598289187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.598289187
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.589810442
Short name T231
Test name
Test status
Simulation time 112743080 ps
CPU time 1.04 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 200176 kb
Host smart-b38d020c-6170-46b3-b90d-5e4c3ea8cca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589810442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.589810442
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2041644417
Short name T527
Test name
Test status
Simulation time 124397132 ps
CPU time 1.2 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:42 PM PST 24
Peak memory 200460 kb
Host smart-dbe4b9b7-7af2-48d1-acad-6bd52b78ff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041644417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2041644417
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.85036244
Short name T493
Test name
Test status
Simulation time 4188348503 ps
CPU time 14.53 seconds
Started Mar 05 12:41:36 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 200388 kb
Host smart-a0301f7f-b493-4e38-b00d-8ad2df63afc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85036244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.85036244
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1067915772
Short name T530
Test name
Test status
Simulation time 488449389 ps
CPU time 2.59 seconds
Started Mar 05 12:41:36 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200264 kb
Host smart-70786a42-288f-4f47-af26-4db3abec7f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067915772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1067915772
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3858582381
Short name T503
Test name
Test status
Simulation time 95540626 ps
CPU time 0.91 seconds
Started Mar 05 12:41:41 PM PST 24
Finished Mar 05 12:41:42 PM PST 24
Peak memory 200356 kb
Host smart-797d8d5f-214c-47a2-a254-32441d04b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858582381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3858582381
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3622765525
Short name T478
Test name
Test status
Simulation time 69282535 ps
CPU time 0.78 seconds
Started Mar 05 12:42:00 PM PST 24
Finished Mar 05 12:42:01 PM PST 24
Peak memory 200264 kb
Host smart-c4706452-331c-4838-8fbd-363c5f3bce39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622765525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3622765525
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2747574293
Short name T355
Test name
Test status
Simulation time 2361850931 ps
CPU time 8.34 seconds
Started Mar 05 12:41:53 PM PST 24
Finished Mar 05 12:42:01 PM PST 24
Peak memory 216860 kb
Host smart-b3c9a023-6ed8-4d11-a6bb-9c9663cddb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747574293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2747574293
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.144781239
Short name T211
Test name
Test status
Simulation time 244909542 ps
CPU time 1.04 seconds
Started Mar 05 12:41:37 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 217048 kb
Host smart-5e604290-429b-44fb-b3b1-283e6aef11b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144781239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.144781239
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.493179326
Short name T18
Test name
Test status
Simulation time 163281289 ps
CPU time 0.83 seconds
Started Mar 05 12:41:52 PM PST 24
Finished Mar 05 12:41:53 PM PST 24
Peak memory 200152 kb
Host smart-a43a9bb1-b5cf-40f6-a464-67047c073d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493179326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.493179326
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2752091688
Short name T158
Test name
Test status
Simulation time 1565921613 ps
CPU time 6.59 seconds
Started Mar 05 12:41:39 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 200348 kb
Host smart-1d96347f-04c6-4697-8d45-bbe4d5b7564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752091688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2752091688
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.646627237
Short name T206
Test name
Test status
Simulation time 113861966 ps
CPU time 1.05 seconds
Started Mar 05 12:41:37 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200252 kb
Host smart-d33d537d-381d-4bc1-9c39-d9c0ea55c8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646627237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.646627237
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.167918678
Short name T366
Test name
Test status
Simulation time 224613903 ps
CPU time 1.41 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 200412 kb
Host smart-f12b7653-f65c-4b80-923a-31a32c66b59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167918678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.167918678
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3441772109
Short name T406
Test name
Test status
Simulation time 3290552881 ps
CPU time 13.03 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 200628 kb
Host smart-b171a04f-5ce7-437d-a56c-55d5d84453eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441772109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3441772109
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2402568137
Short name T506
Test name
Test status
Simulation time 85624172 ps
CPU time 0.79 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 200176 kb
Host smart-db41199c-3643-432f-9842-56d44179c24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402568137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2402568137
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1838508252
Short name T471
Test name
Test status
Simulation time 74535856 ps
CPU time 0.75 seconds
Started Mar 05 12:41:43 PM PST 24
Finished Mar 05 12:41:44 PM PST 24
Peak memory 200116 kb
Host smart-e8f7dcb2-b80d-4eed-bfd2-86d07dbf96d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838508252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1838508252
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.244173697
Short name T30
Test name
Test status
Simulation time 2346374704 ps
CPU time 8.75 seconds
Started Mar 05 12:41:43 PM PST 24
Finished Mar 05 12:41:52 PM PST 24
Peak memory 217756 kb
Host smart-137588b1-09ff-44dc-bd73-8e403128cb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244173697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.244173697
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2002044257
Short name T423
Test name
Test status
Simulation time 243870232 ps
CPU time 1.13 seconds
Started Mar 05 12:41:44 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 217028 kb
Host smart-d21aed88-5eca-41a3-b692-1af04704bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002044257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2002044257
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.316962200
Short name T207
Test name
Test status
Simulation time 225737481 ps
CPU time 0.9 seconds
Started Mar 05 12:42:05 PM PST 24
Finished Mar 05 12:42:06 PM PST 24
Peak memory 200052 kb
Host smart-c427c323-d75f-4356-ab1f-efc96080d15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316962200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.316962200
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3594842517
Short name T262
Test name
Test status
Simulation time 1339076122 ps
CPU time 5.21 seconds
Started Mar 05 12:41:46 PM PST 24
Finished Mar 05 12:41:52 PM PST 24
Peak memory 200476 kb
Host smart-228de3a5-eff4-4cc7-a42e-f6585919dfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594842517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3594842517
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3049394157
Short name T237
Test name
Test status
Simulation time 107208130 ps
CPU time 1.08 seconds
Started Mar 05 12:42:11 PM PST 24
Finished Mar 05 12:42:12 PM PST 24
Peak memory 200324 kb
Host smart-fce8aa8e-26bc-45fc-88b5-6552bfa904b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049394157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3049394157
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1563094015
Short name T149
Test name
Test status
Simulation time 227777765 ps
CPU time 1.49 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:41:50 PM PST 24
Peak memory 200288 kb
Host smart-6b40ede1-50f1-43e3-b34b-fb3f7dc2786a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563094015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1563094015
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1092624203
Short name T194
Test name
Test status
Simulation time 1226282862 ps
CPU time 6.28 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 200288 kb
Host smart-c35a162e-b28b-42bd-88c4-f560e5a0cd4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092624203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1092624203
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2963714655
Short name T253
Test name
Test status
Simulation time 354995902 ps
CPU time 2.11 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 200248 kb
Host smart-70ab9adb-8b0d-4cb5-9e3c-c167dfda2570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963714655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2963714655
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1673457925
Short name T254
Test name
Test status
Simulation time 196036934 ps
CPU time 1.25 seconds
Started Mar 05 12:41:44 PM PST 24
Finished Mar 05 12:41:45 PM PST 24
Peak memory 200500 kb
Host smart-4eb78b00-771f-4391-a061-924f89a5732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673457925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1673457925
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.164078085
Short name T271
Test name
Test status
Simulation time 82248881 ps
CPU time 0.83 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 200256 kb
Host smart-3a86c97e-58a3-467c-afd3-556a22e5e2fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164078085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.164078085
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.552649349
Short name T28
Test name
Test status
Simulation time 2336678829 ps
CPU time 8.12 seconds
Started Mar 05 12:41:54 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 217128 kb
Host smart-61e36ad5-645b-46e4-a821-294fcada9c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552649349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.552649349
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2545457465
Short name T360
Test name
Test status
Simulation time 243451486 ps
CPU time 1.09 seconds
Started Mar 05 12:41:54 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 217076 kb
Host smart-3f76901f-c90d-4d0b-a0ca-302465406295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545457465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2545457465
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2828390218
Short name T534
Test name
Test status
Simulation time 214817361 ps
CPU time 0.89 seconds
Started Mar 05 12:41:43 PM PST 24
Finished Mar 05 12:41:44 PM PST 24
Peak memory 200012 kb
Host smart-7ee09aa7-f3d8-479d-b37d-95b3dff14793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828390218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2828390218
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1357358300
Short name T124
Test name
Test status
Simulation time 1764300710 ps
CPU time 6.04 seconds
Started Mar 05 12:41:51 PM PST 24
Finished Mar 05 12:41:57 PM PST 24
Peak memory 200476 kb
Host smart-1ba0ff3a-160b-4a5c-9f26-e0afeda6d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357358300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1357358300
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2175572755
Short name T408
Test name
Test status
Simulation time 154360166 ps
CPU time 1.07 seconds
Started Mar 05 12:41:55 PM PST 24
Finished Mar 05 12:41:56 PM PST 24
Peak memory 200360 kb
Host smart-7e53311c-b820-4fd5-99bc-8d6b0992ecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175572755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2175572755
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2425876759
Short name T250
Test name
Test status
Simulation time 108663048 ps
CPU time 1.13 seconds
Started Mar 05 12:41:43 PM PST 24
Finished Mar 05 12:41:44 PM PST 24
Peak memory 200408 kb
Host smart-b3478f24-f35f-405d-b4a6-57c516210441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425876759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2425876759
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.973403276
Short name T200
Test name
Test status
Simulation time 342375034 ps
CPU time 1.91 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:41:44 PM PST 24
Peak memory 200344 kb
Host smart-ec7298a5-115c-4a47-b8f8-ed4860da8a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973403276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.973403276
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.71559571
Short name T287
Test name
Test status
Simulation time 368828828 ps
CPU time 2.13 seconds
Started Mar 05 12:41:44 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 200336 kb
Host smart-592df6ab-1be8-4378-94f6-11ac02c5c536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71559571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.71559571
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2234153160
Short name T343
Test name
Test status
Simulation time 150564060 ps
CPU time 1.27 seconds
Started Mar 05 12:41:43 PM PST 24
Finished Mar 05 12:41:45 PM PST 24
Peak memory 200308 kb
Host smart-080c8345-2dc6-43b4-8530-0a2aae3d7d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234153160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2234153160
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.920347059
Short name T456
Test name
Test status
Simulation time 71404807 ps
CPU time 0.83 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:41:50 PM PST 24
Peak memory 200288 kb
Host smart-24597317-77bc-424e-9287-35e955c0a959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920347059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.920347059
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1146131818
Short name T31
Test name
Test status
Simulation time 2363337243 ps
CPU time 8.04 seconds
Started Mar 05 12:41:47 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 217344 kb
Host smart-f570a3b7-fca6-4e01-b323-21d11a039bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146131818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1146131818
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2897439969
Short name T430
Test name
Test status
Simulation time 244816643 ps
CPU time 1.06 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 217216 kb
Host smart-795caee4-e55c-4136-9be1-0b2f9cadbde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897439969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2897439969
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3378986522
Short name T512
Test name
Test status
Simulation time 117107929 ps
CPU time 0.78 seconds
Started Mar 05 12:42:04 PM PST 24
Finished Mar 05 12:42:04 PM PST 24
Peak memory 200156 kb
Host smart-c931a252-c4ea-4f7c-8117-0b0f877069b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378986522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3378986522
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2408342676
Short name T147
Test name
Test status
Simulation time 1006582329 ps
CPU time 4.74 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 200332 kb
Host smart-ff1ad149-79fa-4d8d-b1fe-7cfb02dae799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408342676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2408342676
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2760353694
Short name T409
Test name
Test status
Simulation time 102449759 ps
CPU time 0.96 seconds
Started Mar 05 12:41:41 PM PST 24
Finished Mar 05 12:41:42 PM PST 24
Peak memory 200256 kb
Host smart-f3902b10-e430-4ad2-8079-a8bf64314f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760353694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2760353694
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.240430508
Short name T354
Test name
Test status
Simulation time 120408757 ps
CPU time 1.21 seconds
Started Mar 05 12:41:53 PM PST 24
Finished Mar 05 12:41:54 PM PST 24
Peak memory 200488 kb
Host smart-89b0d5f4-c335-45c8-a63e-205262d6d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240430508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.240430508
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.263487269
Short name T174
Test name
Test status
Simulation time 1924872927 ps
CPU time 7.17 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:48 PM PST 24
Peak memory 208708 kb
Host smart-689d71a3-0ed5-44b9-9d59-3fefc108b73e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263487269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.263487269
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3032464600
Short name T170
Test name
Test status
Simulation time 293250799 ps
CPU time 1.95 seconds
Started Mar 05 12:41:43 PM PST 24
Finished Mar 05 12:41:45 PM PST 24
Peak memory 200264 kb
Host smart-ac90b07b-0f9c-4616-b17a-30f1d357a5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032464600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3032464600
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.84993010
Short name T516
Test name
Test status
Simulation time 91732268 ps
CPU time 0.89 seconds
Started Mar 05 12:41:51 PM PST 24
Finished Mar 05 12:41:52 PM PST 24
Peak memory 200208 kb
Host smart-f881d96d-5b76-48e2-b1d4-df49bf03491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84993010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.84993010
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4227844399
Short name T215
Test name
Test status
Simulation time 77867888 ps
CPU time 0.81 seconds
Started Mar 05 12:41:28 PM PST 24
Finished Mar 05 12:41:29 PM PST 24
Peak memory 200160 kb
Host smart-f6a9e555-b3da-452b-839b-5e2d974d040d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227844399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4227844399
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1752638148
Short name T469
Test name
Test status
Simulation time 2361250127 ps
CPU time 8.59 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 217504 kb
Host smart-8f2f24a9-68eb-4cd3-8390-c6d4d39ededb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752638148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1752638148
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.510125956
Short name T298
Test name
Test status
Simulation time 244651744 ps
CPU time 1.07 seconds
Started Mar 05 12:41:18 PM PST 24
Finished Mar 05 12:41:19 PM PST 24
Peak memory 217152 kb
Host smart-9d55e49c-feb1-4b8d-bcef-14c1ee36e96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510125956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.510125956
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.720646813
Short name T19
Test name
Test status
Simulation time 216373335 ps
CPU time 0.98 seconds
Started Mar 05 12:41:18 PM PST 24
Finished Mar 05 12:41:19 PM PST 24
Peak memory 200132 kb
Host smart-ff0cb7d2-4cb5-4de0-abe6-b00ad4c3cc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720646813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.720646813
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.998648232
Short name T257
Test name
Test status
Simulation time 1388749527 ps
CPU time 5.38 seconds
Started Mar 05 12:41:25 PM PST 24
Finished Mar 05 12:41:30 PM PST 24
Peak memory 200308 kb
Host smart-6fa191ba-4317-47e0-9fd9-87e89279df23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998648232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.998648232
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2154716114
Short name T72
Test name
Test status
Simulation time 8658890366 ps
CPU time 13.65 seconds
Started Mar 05 12:41:16 PM PST 24
Finished Mar 05 12:41:30 PM PST 24
Peak memory 216892 kb
Host smart-e2f9339c-3e68-4f28-9e4a-cba579a3786c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154716114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2154716114
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1208614208
Short name T415
Test name
Test status
Simulation time 162569126 ps
CPU time 1.25 seconds
Started Mar 05 12:41:27 PM PST 24
Finished Mar 05 12:41:28 PM PST 24
Peak memory 200216 kb
Host smart-dcb243c0-a3d7-4f78-a163-3d1d908cf9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208614208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1208614208
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1087770502
Short name T61
Test name
Test status
Simulation time 252821000 ps
CPU time 1.59 seconds
Started Mar 05 12:41:26 PM PST 24
Finished Mar 05 12:41:28 PM PST 24
Peak memory 200320 kb
Host smart-6163631e-4f3a-4282-b206-bebc23b30980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087770502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1087770502
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.4267195047
Short name T268
Test name
Test status
Simulation time 8645764064 ps
CPU time 31.45 seconds
Started Mar 05 12:41:23 PM PST 24
Finished Mar 05 12:41:54 PM PST 24
Peak memory 200440 kb
Host smart-95b2e89f-5848-41e4-99b2-dd479333faa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267195047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4267195047
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.158145664
Short name T150
Test name
Test status
Simulation time 439662695 ps
CPU time 2.37 seconds
Started Mar 05 12:41:36 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200172 kb
Host smart-098e2d63-e0e3-4cb6-b1d7-e260dacf99f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158145664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.158145664
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1481159646
Short name T473
Test name
Test status
Simulation time 182069643 ps
CPU time 1.25 seconds
Started Mar 05 12:41:27 PM PST 24
Finished Mar 05 12:41:28 PM PST 24
Peak memory 200252 kb
Host smart-646a3db7-cf40-4a1f-bd64-7c60eda38183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481159646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1481159646
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2506728450
Short name T499
Test name
Test status
Simulation time 59121115 ps
CPU time 0.76 seconds
Started Mar 05 12:42:02 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 200268 kb
Host smart-f188ade2-93f4-4879-8454-55b2ab98cb6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506728450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2506728450
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1987800033
Short name T55
Test name
Test status
Simulation time 2171873511 ps
CPU time 7.5 seconds
Started Mar 05 12:42:06 PM PST 24
Finished Mar 05 12:42:13 PM PST 24
Peak memory 217256 kb
Host smart-5a2cd588-113e-4ba9-96ef-528d4f2ad166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987800033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1987800033
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2745203184
Short name T82
Test name
Test status
Simulation time 250205298 ps
CPU time 1.04 seconds
Started Mar 05 12:42:05 PM PST 24
Finished Mar 05 12:42:06 PM PST 24
Peak memory 217228 kb
Host smart-9d2cba1a-eb52-4007-9d17-3fbe7dd48328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745203184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2745203184
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.4180341376
Short name T233
Test name
Test status
Simulation time 160125397 ps
CPU time 0.83 seconds
Started Mar 05 12:41:43 PM PST 24
Finished Mar 05 12:41:44 PM PST 24
Peak memory 200168 kb
Host smart-f63a89fb-c8da-4cfd-a980-d91301d0fc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180341376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4180341376
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3589639081
Short name T386
Test name
Test status
Simulation time 1639875770 ps
CPU time 6.41 seconds
Started Mar 05 12:41:41 PM PST 24
Finished Mar 05 12:41:48 PM PST 24
Peak memory 200432 kb
Host smart-ffd0988d-f4bd-4575-93d7-e5aaef3a340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589639081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3589639081
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.148226149
Short name T78
Test name
Test status
Simulation time 155318685 ps
CPU time 1.09 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:41:39 PM PST 24
Peak memory 200320 kb
Host smart-b52252e8-9536-45cc-b7e7-313e2fd67abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148226149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.148226149
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2035755945
Short name T146
Test name
Test status
Simulation time 117521923 ps
CPU time 1.23 seconds
Started Mar 05 12:42:02 PM PST 24
Finished Mar 05 12:42:03 PM PST 24
Peak memory 200428 kb
Host smart-39d0519f-21e5-4e4e-98fb-45df2de7d5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035755945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2035755945
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3089093743
Short name T256
Test name
Test status
Simulation time 13815689766 ps
CPU time 48.42 seconds
Started Mar 05 12:42:16 PM PST 24
Finished Mar 05 12:43:05 PM PST 24
Peak memory 208740 kb
Host smart-af0c7ba8-7819-4759-a202-f7db101b1aae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089093743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3089093743
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.154366845
Short name T362
Test name
Test status
Simulation time 354112543 ps
CPU time 1.91 seconds
Started Mar 05 12:41:53 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 200204 kb
Host smart-e4f452b8-b190-49f6-bd14-2ff5da9a4bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154366845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.154366845
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1431644919
Short name T341
Test name
Test status
Simulation time 83566413 ps
CPU time 0.84 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:40 PM PST 24
Peak memory 200180 kb
Host smart-a25d97d1-8f91-4294-a456-fe1400fbae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431644919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1431644919
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3695791166
Short name T221
Test name
Test status
Simulation time 77166018 ps
CPU time 0.82 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 200156 kb
Host smart-a16e9864-d3a4-4e58-b0c2-e964837bcca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695791166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3695791166
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.985514693
Short name T428
Test name
Test status
Simulation time 253774416 ps
CPU time 1.06 seconds
Started Mar 05 12:41:59 PM PST 24
Finished Mar 05 12:42:00 PM PST 24
Peak memory 208780 kb
Host smart-4de04080-a4c3-4f4b-94c2-b0700a80a239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985514693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.985514693
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.978904457
Short name T16
Test name
Test status
Simulation time 105783598 ps
CPU time 0.78 seconds
Started Mar 05 12:41:41 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 200052 kb
Host smart-7a9eb778-9b12-4af7-b4c1-a077f65d9d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978904457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.978904457
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.951480753
Short name T96
Test name
Test status
Simulation time 1272745719 ps
CPU time 4.94 seconds
Started Mar 05 12:41:53 PM PST 24
Finished Mar 05 12:41:59 PM PST 24
Peak memory 200352 kb
Host smart-24f6dbaa-fff5-472b-9cb7-92528140fdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951480753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.951480753
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3617915935
Short name T510
Test name
Test status
Simulation time 187782592 ps
CPU time 1.19 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 200220 kb
Host smart-4c561b12-82dd-4d95-aa8a-f3a7578bc819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617915935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3617915935
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3464193325
Short name T228
Test name
Test status
Simulation time 115821351 ps
CPU time 1.2 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:41:50 PM PST 24
Peak memory 200480 kb
Host smart-e32b3547-552b-4afc-a289-c05570ca99d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464193325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3464193325
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1835371322
Short name T290
Test name
Test status
Simulation time 4250403181 ps
CPU time 19.67 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:42:06 PM PST 24
Peak memory 200616 kb
Host smart-4e5f441c-b4f1-43e2-97c5-c03239337d44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835371322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1835371322
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4293912502
Short name T242
Test name
Test status
Simulation time 379082710 ps
CPU time 2.37 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:43 PM PST 24
Peak memory 200196 kb
Host smart-894b3167-8414-46ec-9f44-4ee354043b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293912502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4293912502
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1369714819
Short name T387
Test name
Test status
Simulation time 99953696 ps
CPU time 0.89 seconds
Started Mar 05 12:41:59 PM PST 24
Finished Mar 05 12:42:05 PM PST 24
Peak memory 200360 kb
Host smart-df83e69d-108e-4910-904f-7ac8317375c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369714819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1369714819
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3927659213
Short name T247
Test name
Test status
Simulation time 73314433 ps
CPU time 0.82 seconds
Started Mar 05 12:41:56 PM PST 24
Finished Mar 05 12:41:57 PM PST 24
Peak memory 200284 kb
Host smart-6ad3b2c5-ed97-436c-826d-ae512ac9b6b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927659213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3927659213
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1742589501
Short name T420
Test name
Test status
Simulation time 244164064 ps
CPU time 1.14 seconds
Started Mar 05 12:41:58 PM PST 24
Finished Mar 05 12:42:00 PM PST 24
Peak memory 217080 kb
Host smart-677e7b1b-0c87-43dd-ae8b-4e8341854b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742589501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1742589501
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1483335176
Short name T318
Test name
Test status
Simulation time 1362841599 ps
CPU time 5.57 seconds
Started Mar 05 12:42:17 PM PST 24
Finished Mar 05 12:42:22 PM PST 24
Peak memory 200624 kb
Host smart-841b178f-6746-4d4a-ac8d-1d98543c2713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483335176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1483335176
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.557916686
Short name T410
Test name
Test status
Simulation time 115160357 ps
CPU time 0.98 seconds
Started Mar 05 12:42:00 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 200372 kb
Host smart-e0da01bf-3196-4eb2-a2f1-ce40457cb1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557916686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.557916686
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1447653831
Short name T139
Test name
Test status
Simulation time 116329892 ps
CPU time 1.21 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:41:43 PM PST 24
Peak memory 200556 kb
Host smart-d9db4615-6048-4b11-b262-bc18c130b91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447653831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1447653831
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3103096644
Short name T164
Test name
Test status
Simulation time 3558472993 ps
CPU time 13.07 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:59 PM PST 24
Peak memory 200620 kb
Host smart-d9e865fb-c7c0-4303-b67a-93ca7ecad736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103096644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3103096644
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3467907765
Short name T417
Test name
Test status
Simulation time 141413918 ps
CPU time 1.77 seconds
Started Mar 05 12:41:55 PM PST 24
Finished Mar 05 12:41:57 PM PST 24
Peak memory 200380 kb
Host smart-e7017ae2-c5cd-4147-8d76-38e0c7599fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467907765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3467907765
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.4125437739
Short name T361
Test name
Test status
Simulation time 86080337 ps
CPU time 0.86 seconds
Started Mar 05 12:41:53 PM PST 24
Finished Mar 05 12:41:54 PM PST 24
Peak memory 200216 kb
Host smart-76cb8d64-f2f7-44a3-98d6-139c612200f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125437739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.4125437739
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3809895377
Short name T384
Test name
Test status
Simulation time 63407616 ps
CPU time 0.77 seconds
Started Mar 05 12:42:03 PM PST 24
Finished Mar 05 12:42:03 PM PST 24
Peak memory 200264 kb
Host smart-d7e22ac5-9bfa-453f-bb0c-7530107083bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809895377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3809895377
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.366150166
Short name T38
Test name
Test status
Simulation time 1873045923 ps
CPU time 7.38 seconds
Started Mar 05 12:42:05 PM PST 24
Finished Mar 05 12:42:18 PM PST 24
Peak memory 217732 kb
Host smart-b14d1cbf-0715-4932-9719-5387681a13bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366150166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.366150166
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.296179962
Short name T501
Test name
Test status
Simulation time 244115282 ps
CPU time 1.04 seconds
Started Mar 05 12:42:04 PM PST 24
Finished Mar 05 12:42:05 PM PST 24
Peak memory 217140 kb
Host smart-d6a08cd4-ad0a-4d02-b23c-1c9be13f2297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296179962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.296179962
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2059952984
Short name T220
Test name
Test status
Simulation time 74361010 ps
CPU time 0.72 seconds
Started Mar 05 12:42:03 PM PST 24
Finished Mar 05 12:42:04 PM PST 24
Peak memory 200168 kb
Host smart-fab4f24d-325e-44f0-a5a6-20dead2abe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059952984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2059952984
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3693847634
Short name T272
Test name
Test status
Simulation time 1505577917 ps
CPU time 6.66 seconds
Started Mar 05 12:41:51 PM PST 24
Finished Mar 05 12:41:58 PM PST 24
Peak memory 200580 kb
Host smart-b2f862e9-e2db-4d70-b69b-58872b7f93ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693847634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3693847634
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2275545820
Short name T438
Test name
Test status
Simulation time 152248566 ps
CPU time 1.21 seconds
Started Mar 05 12:41:57 PM PST 24
Finished Mar 05 12:41:59 PM PST 24
Peak memory 200260 kb
Host smart-523a7aee-1c6e-4e8a-a505-e84d3b3aeab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275545820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2275545820
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1684508454
Short name T171
Test name
Test status
Simulation time 185083614 ps
CPU time 1.35 seconds
Started Mar 05 12:41:59 PM PST 24
Finished Mar 05 12:42:01 PM PST 24
Peak memory 200328 kb
Host smart-fbbc4fe2-3c6e-490f-83ac-2b097f241452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684508454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1684508454
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2878143751
Short name T89
Test name
Test status
Simulation time 7116055766 ps
CPU time 31.18 seconds
Started Mar 05 12:41:50 PM PST 24
Finished Mar 05 12:42:22 PM PST 24
Peak memory 200476 kb
Host smart-7b646541-f6e6-4c93-b330-31dc756a2c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878143751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2878143751
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.4083115126
Short name T217
Test name
Test status
Simulation time 431124328 ps
CPU time 2.32 seconds
Started Mar 05 12:41:54 PM PST 24
Finished Mar 05 12:41:56 PM PST 24
Peak memory 208488 kb
Host smart-12fa7bbe-1618-4d6d-a012-bc34505d6b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083115126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.4083115126
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3137726447
Short name T305
Test name
Test status
Simulation time 200791859 ps
CPU time 1.23 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:11 PM PST 24
Peak memory 200372 kb
Host smart-8781e9cf-f836-46f3-8936-a0ab9a02c8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137726447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3137726447
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2752386400
Short name T193
Test name
Test status
Simulation time 74450851 ps
CPU time 0.77 seconds
Started Mar 05 12:42:00 PM PST 24
Finished Mar 05 12:42:01 PM PST 24
Peak memory 200112 kb
Host smart-59f97ae6-935b-4f02-adf5-aff350a602c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752386400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2752386400
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2804863511
Short name T52
Test name
Test status
Simulation time 1208665112 ps
CPU time 5.61 seconds
Started Mar 05 12:41:59 PM PST 24
Finished Mar 05 12:42:05 PM PST 24
Peak memory 216816 kb
Host smart-90642c33-b22a-480a-a769-3e20a3b03817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804863511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2804863511
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1809775188
Short name T453
Test name
Test status
Simulation time 244498095 ps
CPU time 1.17 seconds
Started Mar 05 12:42:14 PM PST 24
Finished Mar 05 12:42:16 PM PST 24
Peak memory 216740 kb
Host smart-df8dff31-82e3-4bbf-9d35-86acffedf9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809775188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1809775188
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3738736247
Short name T482
Test name
Test status
Simulation time 234331042 ps
CPU time 1 seconds
Started Mar 05 12:41:46 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 200164 kb
Host smart-8646b615-e148-4d4e-8cae-cb3dbed98b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738736247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3738736247
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.653502441
Short name T505
Test name
Test status
Simulation time 924114577 ps
CPU time 4.49 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:14 PM PST 24
Peak memory 200516 kb
Host smart-a0762571-7dd5-405a-84dd-961a64944251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653502441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.653502441
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3859508010
Short name T379
Test name
Test status
Simulation time 104449617 ps
CPU time 1.06 seconds
Started Mar 05 12:41:59 PM PST 24
Finished Mar 05 12:42:00 PM PST 24
Peak memory 200356 kb
Host smart-7e6e9c75-6566-4415-b965-9a63c6335479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859508010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3859508010
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.502131244
Short name T419
Test name
Test status
Simulation time 226234741 ps
CPU time 1.37 seconds
Started Mar 05 12:41:58 PM PST 24
Finished Mar 05 12:42:00 PM PST 24
Peak memory 200460 kb
Host smart-5597e95e-21d0-4b02-ace4-de5d7dde0d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502131244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.502131244
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2999338398
Short name T348
Test name
Test status
Simulation time 1038863114 ps
CPU time 5.21 seconds
Started Mar 05 12:41:56 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 208660 kb
Host smart-e2c22d3b-d90b-4da9-a478-59656e9c7554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999338398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2999338398
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3477564505
Short name T210
Test name
Test status
Simulation time 373526023 ps
CPU time 2.4 seconds
Started Mar 05 12:42:05 PM PST 24
Finished Mar 05 12:42:07 PM PST 24
Peak memory 200128 kb
Host smart-c89e1fa0-9968-4847-8c1b-80aee3f0bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477564505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3477564505
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.970130469
Short name T338
Test name
Test status
Simulation time 229042463 ps
CPU time 1.34 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:12 PM PST 24
Peak memory 200276 kb
Host smart-1508bd56-58a8-4eda-8321-20e5f39dc8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970130469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.970130469
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1338154400
Short name T445
Test name
Test status
Simulation time 59606255 ps
CPU time 0.71 seconds
Started Mar 05 12:41:57 PM PST 24
Finished Mar 05 12:41:58 PM PST 24
Peak memory 200208 kb
Host smart-e24c2c63-afb9-4b0a-b416-ce10d896a5f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338154400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1338154400
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2445096701
Short name T6
Test name
Test status
Simulation time 244400844 ps
CPU time 1.1 seconds
Started Mar 05 12:42:14 PM PST 24
Finished Mar 05 12:42:15 PM PST 24
Peak memory 217104 kb
Host smart-18d6f9d2-75a6-4c80-934f-d078dbf49d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445096701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2445096701
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1739306092
Short name T184
Test name
Test status
Simulation time 228119510 ps
CPU time 0.92 seconds
Started Mar 05 12:41:54 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 200124 kb
Host smart-e1fa6eb3-9a4a-4409-86af-9b1f3f596438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739306092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1739306092
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1310112901
Short name T320
Test name
Test status
Simulation time 98574824 ps
CPU time 1.02 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:41:50 PM PST 24
Peak memory 200260 kb
Host smart-77cdb125-5a43-43df-a211-ae9dbaebe644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310112901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1310112901
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3443798692
Short name T2
Test name
Test status
Simulation time 191363234 ps
CPU time 1.33 seconds
Started Mar 05 12:41:58 PM PST 24
Finished Mar 05 12:42:00 PM PST 24
Peak memory 200464 kb
Host smart-a946cba6-aee9-46a6-8873-8163c13a9619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443798692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3443798692
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3869487087
Short name T461
Test name
Test status
Simulation time 2180378184 ps
CPU time 10.52 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:18 PM PST 24
Peak memory 208792 kb
Host smart-d6f31b41-6070-4749-85e9-a04c29546391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869487087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3869487087
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.4103644384
Short name T308
Test name
Test status
Simulation time 315662161 ps
CPU time 2.24 seconds
Started Mar 05 12:42:16 PM PST 24
Finished Mar 05 12:42:19 PM PST 24
Peak memory 200236 kb
Host smart-cb45fe9a-86c1-455c-bdd9-d4e7fa5bdf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103644384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.4103644384
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.810126293
Short name T377
Test name
Test status
Simulation time 79396501 ps
CPU time 0.83 seconds
Started Mar 05 12:41:55 PM PST 24
Finished Mar 05 12:41:56 PM PST 24
Peak memory 200156 kb
Host smart-db1c122c-b4ff-4ef4-8ea8-e7cf478e65f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810126293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.810126293
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1350257412
Short name T523
Test name
Test status
Simulation time 68370137 ps
CPU time 0.74 seconds
Started Mar 05 12:41:50 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 200116 kb
Host smart-e6f4433c-d6e5-4fcb-b5cb-0796e5738b13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350257412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1350257412
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2671360532
Short name T39
Test name
Test status
Simulation time 1888836171 ps
CPU time 6.79 seconds
Started Mar 05 12:41:58 PM PST 24
Finished Mar 05 12:42:04 PM PST 24
Peak memory 217204 kb
Host smart-b6dce608-c18f-4056-a402-295046874942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671360532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2671360532
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3358272130
Short name T295
Test name
Test status
Simulation time 244481979 ps
CPU time 1.14 seconds
Started Mar 05 12:41:53 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 216952 kb
Host smart-8020ed02-69ef-42a8-b6a6-460efcf95a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358272130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3358272130
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.339064643
Short name T14
Test name
Test status
Simulation time 86692957 ps
CPU time 0.75 seconds
Started Mar 05 12:42:09 PM PST 24
Finished Mar 05 12:42:10 PM PST 24
Peak memory 200116 kb
Host smart-58669582-ce0e-4d11-8eba-a5d4accfd4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339064643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.339064643
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2916324591
Short name T273
Test name
Test status
Simulation time 1159091383 ps
CPU time 5.25 seconds
Started Mar 05 12:41:54 PM PST 24
Finished Mar 05 12:42:00 PM PST 24
Peak memory 200416 kb
Host smart-994db65e-14c7-41eb-b069-42cda3a0f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916324591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2916324591
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3255848618
Short name T418
Test name
Test status
Simulation time 102121442 ps
CPU time 1.02 seconds
Started Mar 05 12:41:58 PM PST 24
Finished Mar 05 12:42:00 PM PST 24
Peak memory 200160 kb
Host smart-e2db2016-0698-4a8a-898b-67f86d67d8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255848618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3255848618
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1797298846
Short name T358
Test name
Test status
Simulation time 205995946 ps
CPU time 1.37 seconds
Started Mar 05 12:42:06 PM PST 24
Finished Mar 05 12:42:08 PM PST 24
Peak memory 200428 kb
Host smart-dd3609cf-b688-4888-8b46-1b9c2e996652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797298846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1797298846
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.443617424
Short name T218
Test name
Test status
Simulation time 3027812903 ps
CPU time 10.81 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 208780 kb
Host smart-519bc151-e26e-4698-b429-15ed090d1dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443617424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.443617424
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2404048480
Short name T385
Test name
Test status
Simulation time 145693169 ps
CPU time 1.95 seconds
Started Mar 05 12:42:11 PM PST 24
Finished Mar 05 12:42:13 PM PST 24
Peak memory 200112 kb
Host smart-792bb84c-5b8b-432a-bd19-eb1d73a2781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404048480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2404048480
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.155506617
Short name T477
Test name
Test status
Simulation time 153193231 ps
CPU time 1.27 seconds
Started Mar 05 12:41:58 PM PST 24
Finished Mar 05 12:42:00 PM PST 24
Peak memory 200636 kb
Host smart-e540b2e8-c473-4cd2-9c5a-e25b2843e8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155506617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.155506617
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1479749582
Short name T69
Test name
Test status
Simulation time 72456362 ps
CPU time 0.77 seconds
Started Mar 05 12:41:54 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 200252 kb
Host smart-05c79bbb-b3e0-4a5b-98ba-0a0bad25cc63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479749582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1479749582
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2583050838
Short name T128
Test name
Test status
Simulation time 1224049983 ps
CPU time 5.64 seconds
Started Mar 05 12:42:06 PM PST 24
Finished Mar 05 12:42:12 PM PST 24
Peak memory 221024 kb
Host smart-783f5a91-0f20-4c5b-8465-18af5f5fc3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583050838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2583050838
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3376860024
Short name T22
Test name
Test status
Simulation time 244415719 ps
CPU time 1.04 seconds
Started Mar 05 12:41:55 PM PST 24
Finished Mar 05 12:41:56 PM PST 24
Peak memory 217136 kb
Host smart-0dfa9c5a-0d16-442c-910f-43d3858cd123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376860024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3376860024
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2246619817
Short name T282
Test name
Test status
Simulation time 172481575 ps
CPU time 0.81 seconds
Started Mar 05 12:42:04 PM PST 24
Finished Mar 05 12:42:05 PM PST 24
Peak memory 200304 kb
Host smart-04f42065-4ab2-48e4-8f1b-07b465cfc379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246619817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2246619817
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3635230510
Short name T524
Test name
Test status
Simulation time 866205945 ps
CPU time 4.12 seconds
Started Mar 05 12:41:57 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 200476 kb
Host smart-40f35878-4ca0-4340-83c4-924381b85b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635230510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3635230510
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3606735856
Short name T156
Test name
Test status
Simulation time 138314023 ps
CPU time 1.16 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:10 PM PST 24
Peak memory 200368 kb
Host smart-b98de54e-ae21-4a34-8625-1ffaaaf56be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606735856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3606735856
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.957190229
Short name T481
Test name
Test status
Simulation time 110438754 ps
CPU time 1.19 seconds
Started Mar 05 12:42:07 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 200452 kb
Host smart-0fb61ee6-2782-4b4a-ab46-baf36ae70690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957190229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.957190229
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1570292611
Short name T325
Test name
Test status
Simulation time 115581182 ps
CPU time 0.83 seconds
Started Mar 05 12:42:13 PM PST 24
Finished Mar 05 12:42:14 PM PST 24
Peak memory 200024 kb
Host smart-f5f97baa-e119-4c40-90de-6eb22ed6e104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570292611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1570292611
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3011258361
Short name T284
Test name
Test status
Simulation time 529539548 ps
CPU time 2.76 seconds
Started Mar 05 12:42:00 PM PST 24
Finished Mar 05 12:42:03 PM PST 24
Peak memory 200148 kb
Host smart-d2e804a2-f247-40ac-859c-65b28777dabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011258361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3011258361
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1965634103
Short name T518
Test name
Test status
Simulation time 70813541 ps
CPU time 0.84 seconds
Started Mar 05 12:42:04 PM PST 24
Finished Mar 05 12:42:05 PM PST 24
Peak memory 200212 kb
Host smart-3a4dc51c-f450-49eb-916f-9c8a3d18d655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965634103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1965634103
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1435210690
Short name T255
Test name
Test status
Simulation time 76831438 ps
CPU time 0.78 seconds
Started Mar 05 12:42:01 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 200148 kb
Host smart-15302c95-3dad-4df6-a7f1-cffdb06148fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435210690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1435210690
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3160988177
Short name T500
Test name
Test status
Simulation time 1901581121 ps
CPU time 6.87 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:15 PM PST 24
Peak memory 218228 kb
Host smart-36a399ae-7224-4a18-9539-f070dbd1aaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160988177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3160988177
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.276687633
Short name T169
Test name
Test status
Simulation time 243623136 ps
CPU time 1.11 seconds
Started Mar 05 12:41:57 PM PST 24
Finished Mar 05 12:41:58 PM PST 24
Peak memory 217128 kb
Host smart-e1036aba-2deb-4fb7-a46c-88f3218f83ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276687633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.276687633
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.93318820
Short name T8
Test name
Test status
Simulation time 193540189 ps
CPU time 0.86 seconds
Started Mar 05 12:42:01 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 200128 kb
Host smart-63f44dda-858b-4f8e-b765-ed6cd382f68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93318820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.93318820
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.878528437
Short name T380
Test name
Test status
Simulation time 1255910309 ps
CPU time 5.05 seconds
Started Mar 05 12:42:04 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 200496 kb
Host smart-1feaeea6-b80c-4d57-8b10-1f2a4fafeefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878528437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.878528437
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.253386430
Short name T226
Test name
Test status
Simulation time 177705209 ps
CPU time 1.17 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 200312 kb
Host smart-ca1a530b-4dc5-4e39-a5b9-be9ed4f91c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253386430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.253386430
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.351620626
Short name T310
Test name
Test status
Simulation time 109230160 ps
CPU time 1.23 seconds
Started Mar 05 12:42:11 PM PST 24
Finished Mar 05 12:42:12 PM PST 24
Peak memory 200428 kb
Host smart-871b7551-e825-48e9-975e-3c5aa8ab81ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351620626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.351620626
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.25986485
Short name T84
Test name
Test status
Simulation time 6707924181 ps
CPU time 32.73 seconds
Started Mar 05 12:41:58 PM PST 24
Finished Mar 05 12:42:31 PM PST 24
Peak memory 200612 kb
Host smart-fe26ac32-9676-40fc-ba34-252d42cd24d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25986485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.25986485
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2684022730
Short name T88
Test name
Test status
Simulation time 265194593 ps
CPU time 1.82 seconds
Started Mar 05 12:42:07 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 200240 kb
Host smart-5928fcd9-6969-4faa-b9cd-23c68ed74ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684022730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2684022730
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.442193573
Short name T292
Test name
Test status
Simulation time 110949543 ps
CPU time 0.95 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 200432 kb
Host smart-8aeeeda9-e9ee-4671-9d79-3b8dddf0ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442193573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.442193573
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.4014758582
Short name T276
Test name
Test status
Simulation time 74996162 ps
CPU time 0.82 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 200252 kb
Host smart-0a4024c9-89f5-4ded-900e-2a5587bcb32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014758582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.4014758582
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1750210116
Short name T407
Test name
Test status
Simulation time 1897970743 ps
CPU time 7.11 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:17 PM PST 24
Peak memory 217176 kb
Host smart-a25b7265-9386-4b96-b140-660a5a073ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750210116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1750210116
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2572006940
Short name T451
Test name
Test status
Simulation time 243530128 ps
CPU time 1.13 seconds
Started Mar 05 12:41:48 PM PST 24
Finished Mar 05 12:41:50 PM PST 24
Peak memory 217100 kb
Host smart-182eac22-9b9f-43ee-9961-82a27fc3de2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572006940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2572006940
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3407313409
Short name T483
Test name
Test status
Simulation time 123077691 ps
CPU time 0.79 seconds
Started Mar 05 12:42:07 PM PST 24
Finished Mar 05 12:42:08 PM PST 24
Peak memory 200148 kb
Host smart-f2c8874d-2351-41be-86d0-ff3f35e1978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407313409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3407313409
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.477637562
Short name T123
Test name
Test status
Simulation time 2096050053 ps
CPU time 7.15 seconds
Started Mar 05 12:42:12 PM PST 24
Finished Mar 05 12:42:19 PM PST 24
Peak memory 200548 kb
Host smart-07c0487f-52a7-4b82-94d1-9abd518e4eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477637562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.477637562
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3600822423
Short name T519
Test name
Test status
Simulation time 141317141 ps
CPU time 1.09 seconds
Started Mar 05 12:41:57 PM PST 24
Finished Mar 05 12:41:59 PM PST 24
Peak memory 200316 kb
Host smart-5a3dec71-a693-4223-8ee4-0c75e357388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600822423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3600822423
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3984239702
Short name T370
Test name
Test status
Simulation time 258990659 ps
CPU time 1.57 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:12 PM PST 24
Peak memory 200452 kb
Host smart-5f207a46-ea62-4a30-bb8d-7fab2430159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984239702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3984239702
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.834581233
Short name T278
Test name
Test status
Simulation time 1881129442 ps
CPU time 6.56 seconds
Started Mar 05 12:42:06 PM PST 24
Finished Mar 05 12:42:13 PM PST 24
Peak memory 200328 kb
Host smart-ae87b5db-ad48-44b9-ac20-1968fdffefb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834581233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.834581233
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2017035210
Short name T79
Test name
Test status
Simulation time 254152769 ps
CPU time 1.68 seconds
Started Mar 05 12:41:57 PM PST 24
Finished Mar 05 12:41:59 PM PST 24
Peak memory 200108 kb
Host smart-63c747aa-f884-4105-91db-6b67f79d495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017035210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2017035210
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2821687405
Short name T465
Test name
Test status
Simulation time 192815991 ps
CPU time 1.23 seconds
Started Mar 05 12:41:57 PM PST 24
Finished Mar 05 12:41:59 PM PST 24
Peak memory 200172 kb
Host smart-8a8856e4-9807-44bd-99b5-f8f1ab8d9041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821687405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2821687405
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1073762203
Short name T212
Test name
Test status
Simulation time 58190161 ps
CPU time 0.73 seconds
Started Mar 05 12:41:31 PM PST 24
Finished Mar 05 12:41:32 PM PST 24
Peak memory 200204 kb
Host smart-d039f1eb-2fcc-445b-9aac-e45822d8ae79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073762203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1073762203
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3496945111
Short name T450
Test name
Test status
Simulation time 1896508977 ps
CPU time 7.05 seconds
Started Mar 05 12:41:22 PM PST 24
Finished Mar 05 12:41:29 PM PST 24
Peak memory 221524 kb
Host smart-3833bbe5-488c-4e9b-b877-18f5a01cb4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496945111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3496945111
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2257963778
Short name T190
Test name
Test status
Simulation time 245948900 ps
CPU time 1.08 seconds
Started Mar 05 12:41:30 PM PST 24
Finished Mar 05 12:41:32 PM PST 24
Peak memory 217084 kb
Host smart-e9cf24fe-a2f9-4420-8877-52e6036acbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257963778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2257963778
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.103959554
Short name T264
Test name
Test status
Simulation time 100066677 ps
CPU time 0.82 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 200012 kb
Host smart-387a9de0-f773-46a6-bcbe-9d7d812d99ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103959554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.103959554
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3187545117
Short name T376
Test name
Test status
Simulation time 785028276 ps
CPU time 4.27 seconds
Started Mar 05 12:41:19 PM PST 24
Finished Mar 05 12:41:24 PM PST 24
Peak memory 200332 kb
Host smart-3be3c8a1-0c14-4b29-8110-9b4777ecc74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187545117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3187545117
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1952355491
Short name T68
Test name
Test status
Simulation time 16585869339 ps
CPU time 26.91 seconds
Started Mar 05 12:41:35 PM PST 24
Finished Mar 05 12:42:02 PM PST 24
Peak memory 216860 kb
Host smart-8435464d-72d5-46f7-9c19-e150a6715c03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952355491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1952355491
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1689486245
Short name T462
Test name
Test status
Simulation time 107612971 ps
CPU time 0.99 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 200356 kb
Host smart-e69af203-7c27-49e0-9624-4a183c482a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689486245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1689486245
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4271623321
Short name T381
Test name
Test status
Simulation time 121996794 ps
CPU time 1.19 seconds
Started Mar 05 12:41:31 PM PST 24
Finished Mar 05 12:41:32 PM PST 24
Peak memory 200360 kb
Host smart-c79e3fc5-9969-4e1c-b8b1-05183df3745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271623321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4271623321
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.603390198
Short name T303
Test name
Test status
Simulation time 6989746174 ps
CPU time 30.72 seconds
Started Mar 05 12:41:17 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 208632 kb
Host smart-ba377f8a-0b16-4d48-9112-89144d51f002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603390198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.603390198
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.4009376780
Short name T47
Test name
Test status
Simulation time 471706466 ps
CPU time 2.73 seconds
Started Mar 05 12:41:27 PM PST 24
Finished Mar 05 12:41:30 PM PST 24
Peak memory 208244 kb
Host smart-cb991904-ab3c-4ca1-b9eb-0d1f2dcac13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009376780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4009376780
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2977106962
Short name T199
Test name
Test status
Simulation time 201362383 ps
CPU time 1.2 seconds
Started Mar 05 12:41:27 PM PST 24
Finished Mar 05 12:41:28 PM PST 24
Peak memory 200192 kb
Host smart-ec97fc93-04aa-4223-8f68-51f55824c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977106962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2977106962
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3221033604
Short name T439
Test name
Test status
Simulation time 92444568 ps
CPU time 0.82 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:11 PM PST 24
Peak memory 200112 kb
Host smart-acad7290-6d74-4162-b68b-d441652669a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221033604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3221033604
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1229354074
Short name T497
Test name
Test status
Simulation time 1220924533 ps
CPU time 5.23 seconds
Started Mar 05 12:42:18 PM PST 24
Finished Mar 05 12:42:23 PM PST 24
Peak memory 220576 kb
Host smart-dbadeff5-1c22-4b8a-94dc-9dc405f01e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229354074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1229354074
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2013970564
Short name T490
Test name
Test status
Simulation time 244329848 ps
CPU time 1.03 seconds
Started Mar 05 12:42:07 PM PST 24
Finished Mar 05 12:42:08 PM PST 24
Peak memory 217064 kb
Host smart-a6e62b62-801e-404a-8c58-640d927f1195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013970564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2013970564
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3805111993
Short name T442
Test name
Test status
Simulation time 123905857 ps
CPU time 0.84 seconds
Started Mar 05 12:42:07 PM PST 24
Finished Mar 05 12:42:08 PM PST 24
Peak memory 199968 kb
Host smart-3060b19b-9c80-4409-a86c-4b5960d8d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805111993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3805111993
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2210932669
Short name T344
Test name
Test status
Simulation time 859286428 ps
CPU time 4.24 seconds
Started Mar 05 12:42:13 PM PST 24
Finished Mar 05 12:42:17 PM PST 24
Peak memory 200528 kb
Host smart-17ce03f0-d804-4387-b27b-5f66e9361c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210932669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2210932669
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3876959231
Short name T42
Test name
Test status
Simulation time 105607430 ps
CPU time 1.04 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:11 PM PST 24
Peak memory 200356 kb
Host smart-4af51697-4fa8-482f-a4b8-a9d6179beba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876959231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3876959231
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.10519008
Short name T412
Test name
Test status
Simulation time 123272046 ps
CPU time 1.19 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 200428 kb
Host smart-8e2f6236-9b67-4d77-9bbc-f1c7e18d1edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10519008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.10519008
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2506806009
Short name T317
Test name
Test status
Simulation time 525609180 ps
CPU time 2.87 seconds
Started Mar 05 12:42:01 PM PST 24
Finished Mar 05 12:42:04 PM PST 24
Peak memory 200268 kb
Host smart-cb5abafb-21fa-441b-a7ae-92fc543f63a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506806009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2506806009
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3540810367
Short name T86
Test name
Test status
Simulation time 124074207 ps
CPU time 1.56 seconds
Started Mar 05 12:41:54 PM PST 24
Finished Mar 05 12:41:56 PM PST 24
Peak memory 208308 kb
Host smart-f3e8e7ae-9a7f-4c69-a8b2-379aff533945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540810367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3540810367
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3044610086
Short name T214
Test name
Test status
Simulation time 187917012 ps
CPU time 1.19 seconds
Started Mar 05 12:42:12 PM PST 24
Finished Mar 05 12:42:13 PM PST 24
Peak memory 200364 kb
Host smart-4276b4f5-f27d-432b-b97c-8633a8dba379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044610086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3044610086
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3974705471
Short name T302
Test name
Test status
Simulation time 82499246 ps
CPU time 0.79 seconds
Started Mar 05 12:42:29 PM PST 24
Finished Mar 05 12:42:30 PM PST 24
Peak memory 200196 kb
Host smart-93a2eee4-5884-443c-9127-3bff7c17ddcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974705471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3974705471
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1641431031
Short name T526
Test name
Test status
Simulation time 1220456832 ps
CPU time 5.52 seconds
Started Mar 05 12:42:14 PM PST 24
Finished Mar 05 12:42:19 PM PST 24
Peak memory 220676 kb
Host smart-68698d58-c348-4197-8839-e13881692fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641431031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1641431031
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.158951830
Short name T301
Test name
Test status
Simulation time 245148621 ps
CPU time 1.02 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:25 PM PST 24
Peak memory 217136 kb
Host smart-ef0aacb8-1d87-4e46-a639-c0c67a2981a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158951830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.158951830
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.769640367
Short name T11
Test name
Test status
Simulation time 209322918 ps
CPU time 0.91 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:11 PM PST 24
Peak memory 200056 kb
Host smart-1ad6821c-f7ae-444d-b4b6-7d35f63f41c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769640367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.769640367
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.731534013
Short name T286
Test name
Test status
Simulation time 1502584755 ps
CPU time 6.78 seconds
Started Mar 05 12:42:15 PM PST 24
Finished Mar 05 12:42:22 PM PST 24
Peak memory 200516 kb
Host smart-080733f3-e9ee-49bd-8a2c-c998b3a901e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731534013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.731534013
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2163836181
Short name T307
Test name
Test status
Simulation time 179570483 ps
CPU time 1.14 seconds
Started Mar 05 12:42:06 PM PST 24
Finished Mar 05 12:42:07 PM PST 24
Peak memory 200316 kb
Host smart-01be7a57-58f8-4e0e-a3d5-a6938de2f9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163836181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2163836181
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3231780930
Short name T1
Test name
Test status
Simulation time 110775364 ps
CPU time 1.09 seconds
Started Mar 05 12:42:07 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 200396 kb
Host smart-b604f302-5c0c-47bc-84dc-bf7af74212b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231780930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3231780930
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2582076672
Short name T213
Test name
Test status
Simulation time 462793938 ps
CPU time 2.33 seconds
Started Mar 05 12:42:19 PM PST 24
Finished Mar 05 12:42:22 PM PST 24
Peak memory 208508 kb
Host smart-f52f7357-220c-4a4f-a66b-8204591fce9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582076672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2582076672
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.4130250278
Short name T367
Test name
Test status
Simulation time 164272690 ps
CPU time 1.05 seconds
Started Mar 05 12:42:13 PM PST 24
Finished Mar 05 12:42:14 PM PST 24
Peak memory 200368 kb
Host smart-020de3a3-39a7-4e9a-b9f6-c33b0fb81a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130250278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.4130250278
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1035283462
Short name T447
Test name
Test status
Simulation time 67402308 ps
CPU time 0.83 seconds
Started Mar 05 12:42:13 PM PST 24
Finished Mar 05 12:42:14 PM PST 24
Peak memory 200116 kb
Host smart-a694a15c-4f15-4b69-8102-65b275ce0a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035283462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1035283462
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1736934989
Short name T53
Test name
Test status
Simulation time 1895591245 ps
CPU time 8.12 seconds
Started Mar 05 12:42:30 PM PST 24
Finished Mar 05 12:42:38 PM PST 24
Peak memory 217632 kb
Host smart-1fa939db-7c45-49b0-9fe6-508438dd1ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736934989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1736934989
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2541324188
Short name T202
Test name
Test status
Simulation time 244238740 ps
CPU time 1.09 seconds
Started Mar 05 12:42:11 PM PST 24
Finished Mar 05 12:42:12 PM PST 24
Peak memory 217140 kb
Host smart-938140d4-ab3a-4f4b-9326-79a6492620f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541324188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2541324188
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2398254178
Short name T288
Test name
Test status
Simulation time 157532549 ps
CPU time 0.84 seconds
Started Mar 05 12:42:28 PM PST 24
Finished Mar 05 12:42:29 PM PST 24
Peak memory 200136 kb
Host smart-5dd23389-3a2a-4729-bbca-acef8bd9949c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398254178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2398254178
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2452606083
Short name T168
Test name
Test status
Simulation time 1515257502 ps
CPU time 6.4 seconds
Started Mar 05 12:42:09 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 200500 kb
Host smart-456512c1-94ed-4047-9df8-535f81bd2641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452606083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2452606083
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.776596402
Short name T403
Test name
Test status
Simulation time 100166148 ps
CPU time 1 seconds
Started Mar 05 12:42:19 PM PST 24
Finished Mar 05 12:42:20 PM PST 24
Peak memory 200360 kb
Host smart-c0860d21-8005-46b9-b9fc-d61e8d417c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776596402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.776596402
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1139316963
Short name T274
Test name
Test status
Simulation time 109778095 ps
CPU time 1.14 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:30 PM PST 24
Peak memory 200512 kb
Host smart-a5c9b4d8-a425-4f58-bb3b-bcb0b9847c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139316963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1139316963
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3859291016
Short name T455
Test name
Test status
Simulation time 468237833 ps
CPU time 1.99 seconds
Started Mar 05 12:42:12 PM PST 24
Finished Mar 05 12:42:14 PM PST 24
Peak memory 200504 kb
Host smart-cfd5a206-d1c7-4d19-9633-8e50989027f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859291016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3859291016
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3880963466
Short name T259
Test name
Test status
Simulation time 131912063 ps
CPU time 1.75 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:10 PM PST 24
Peak memory 200196 kb
Host smart-1df83ac5-ecf5-41f5-96e0-c1492da4b3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880963466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3880963466
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2279522559
Short name T498
Test name
Test status
Simulation time 60787109 ps
CPU time 0.71 seconds
Started Mar 05 12:42:06 PM PST 24
Finished Mar 05 12:42:07 PM PST 24
Peak memory 200372 kb
Host smart-c937457a-4cca-4bcc-a825-2b6b28511718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279522559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2279522559
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2772601773
Short name T3
Test name
Test status
Simulation time 63236552 ps
CPU time 0.76 seconds
Started Mar 05 12:42:22 PM PST 24
Finished Mar 05 12:42:23 PM PST 24
Peak memory 200272 kb
Host smart-a156d951-5cf7-49e2-93f4-3e299f865580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772601773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2772601773
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2332714444
Short name T509
Test name
Test status
Simulation time 1222869688 ps
CPU time 5.51 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:14 PM PST 24
Peak memory 217128 kb
Host smart-b0afb567-594a-4145-979b-b4ea1f9a814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332714444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2332714444
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.280733129
Short name T235
Test name
Test status
Simulation time 248237110 ps
CPU time 1.06 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:33 PM PST 24
Peak memory 217148 kb
Host smart-c28c87d1-69c0-46db-b676-c6943f10cefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280733129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.280733129
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2463641547
Short name T175
Test name
Test status
Simulation time 194112017 ps
CPU time 1.01 seconds
Started Mar 05 12:42:19 PM PST 24
Finished Mar 05 12:42:20 PM PST 24
Peak memory 200012 kb
Host smart-065f5939-536c-4e77-8813-79b734647983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463641547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2463641547
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1352462655
Short name T507
Test name
Test status
Simulation time 1410992734 ps
CPU time 5.34 seconds
Started Mar 05 12:42:05 PM PST 24
Finished Mar 05 12:42:10 PM PST 24
Peak memory 200572 kb
Host smart-3b08a8fe-ce0c-4357-8313-9e7a2b72d2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352462655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1352462655
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.521939969
Short name T241
Test name
Test status
Simulation time 94041074 ps
CPU time 0.99 seconds
Started Mar 05 12:42:15 PM PST 24
Finished Mar 05 12:42:16 PM PST 24
Peak memory 200360 kb
Host smart-bb1d9885-4e5c-4143-b88a-2c3d442e3ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521939969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.521939969
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3466356747
Short name T204
Test name
Test status
Simulation time 189119021 ps
CPU time 1.36 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 200368 kb
Host smart-2d792fd7-d7a8-47a4-aaf3-48b6d206cd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466356747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3466356747
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1556944486
Short name T487
Test name
Test status
Simulation time 3416859079 ps
CPU time 16.41 seconds
Started Mar 05 12:42:17 PM PST 24
Finished Mar 05 12:42:33 PM PST 24
Peak memory 209904 kb
Host smart-e275889e-95b6-47eb-a64b-69c5e9635885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556944486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1556944486
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.90280738
Short name T353
Test name
Test status
Simulation time 120063447 ps
CPU time 1.51 seconds
Started Mar 05 12:42:11 PM PST 24
Finished Mar 05 12:42:13 PM PST 24
Peak memory 200272 kb
Host smart-eb8e419b-bd0b-450d-a8df-01fba59c3864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90280738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.90280738
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.231673286
Short name T432
Test name
Test status
Simulation time 130614786 ps
CPU time 1.07 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:11 PM PST 24
Peak memory 200232 kb
Host smart-b1dc7e4c-34eb-499f-a67b-2fff080e4755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231673286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.231673286
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.597093129
Short name T81
Test name
Test status
Simulation time 65451812 ps
CPU time 0.73 seconds
Started Mar 05 12:42:18 PM PST 24
Finished Mar 05 12:42:19 PM PST 24
Peak memory 200272 kb
Host smart-b5073984-dcd3-439d-a35d-515eb67f5986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597093129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.597093129
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.918934754
Short name T508
Test name
Test status
Simulation time 2166722975 ps
CPU time 8.15 seconds
Started Mar 05 12:42:21 PM PST 24
Finished Mar 05 12:42:30 PM PST 24
Peak memory 217140 kb
Host smart-00df545a-7309-47ae-b547-84215f006970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918934754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.918934754
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.21533700
Short name T463
Test name
Test status
Simulation time 243945039 ps
CPU time 1.12 seconds
Started Mar 05 12:42:15 PM PST 24
Finished Mar 05 12:42:16 PM PST 24
Peak memory 217340 kb
Host smart-0dae841b-3cae-44d8-884b-f17cb44b9338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21533700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.21533700
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3049926367
Short name T449
Test name
Test status
Simulation time 145024631 ps
CPU time 0.83 seconds
Started Mar 05 12:42:29 PM PST 24
Finished Mar 05 12:42:30 PM PST 24
Peak memory 200280 kb
Host smart-47d7804c-d739-42e4-8d63-59c84bf5f014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049926367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3049926367
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.734685050
Short name T426
Test name
Test status
Simulation time 886910749 ps
CPU time 4.29 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:14 PM PST 24
Peak memory 200372 kb
Host smart-240100d2-7f0f-4688-ae2b-87150f1348ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734685050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.734685050
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3688956011
Short name T74
Test name
Test status
Simulation time 104907081 ps
CPU time 1.06 seconds
Started Mar 05 12:42:04 PM PST 24
Finished Mar 05 12:42:05 PM PST 24
Peak memory 200336 kb
Host smart-b0977c77-ab58-48e1-850b-972bf14ac43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688956011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3688956011
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3215465410
Short name T239
Test name
Test status
Simulation time 249249146 ps
CPU time 1.44 seconds
Started Mar 05 12:42:09 PM PST 24
Finished Mar 05 12:42:11 PM PST 24
Peak memory 200332 kb
Host smart-b70c9125-42d9-4a45-a1a2-468d403e5621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215465410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3215465410
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3521741123
Short name T356
Test name
Test status
Simulation time 4740019595 ps
CPU time 20.3 seconds
Started Mar 05 12:42:17 PM PST 24
Finished Mar 05 12:42:38 PM PST 24
Peak memory 209540 kb
Host smart-70cf7d53-c126-4f82-a938-a4c9a2e0de82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521741123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3521741123
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2203502680
Short name T246
Test name
Test status
Simulation time 470040354 ps
CPU time 2.41 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:22 PM PST 24
Peak memory 208344 kb
Host smart-a29dde6f-e4d9-4911-a7ed-056f4923262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203502680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2203502680
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2674728230
Short name T400
Test name
Test status
Simulation time 119400100 ps
CPU time 1.05 seconds
Started Mar 05 12:42:35 PM PST 24
Finished Mar 05 12:42:37 PM PST 24
Peak memory 200364 kb
Host smart-c0ff0f93-27b9-4747-b380-f88fd054eaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674728230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2674728230
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1986366470
Short name T195
Test name
Test status
Simulation time 70689322 ps
CPU time 0.75 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:24 PM PST 24
Peak memory 200284 kb
Host smart-76cde9b6-05ac-43db-84ea-0dcc32bcfbf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986366470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1986366470
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.4236050731
Short name T399
Test name
Test status
Simulation time 1229282422 ps
CPU time 5.63 seconds
Started Mar 05 12:42:33 PM PST 24
Finished Mar 05 12:42:39 PM PST 24
Peak memory 217780 kb
Host smart-b2d44a37-b2c7-495d-806b-7f766b067762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236050731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.4236050731
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2419712978
Short name T280
Test name
Test status
Simulation time 244993771 ps
CPU time 1.07 seconds
Started Mar 05 12:42:15 PM PST 24
Finished Mar 05 12:42:16 PM PST 24
Peak memory 217084 kb
Host smart-8bc3dd21-8502-4cc6-8578-8646a52a2c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419712978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2419712978
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2696121833
Short name T165
Test name
Test status
Simulation time 210498584 ps
CPU time 0.96 seconds
Started Mar 05 12:42:18 PM PST 24
Finished Mar 05 12:42:19 PM PST 24
Peak memory 200016 kb
Host smart-19b2a4a3-a9f8-451d-b55a-aa2b44b295ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696121833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2696121833
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3689987490
Short name T230
Test name
Test status
Simulation time 1227047583 ps
CPU time 4.85 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:15 PM PST 24
Peak memory 200432 kb
Host smart-8d2aa287-1aa9-4ef9-b422-4dd6fc51d4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689987490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3689987490
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.807148821
Short name T328
Test name
Test status
Simulation time 147071763 ps
CPU time 1.1 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:24 PM PST 24
Peak memory 200312 kb
Host smart-52e1fe43-2420-47a8-9602-b32cb412740d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807148821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.807148821
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.4267340745
Short name T311
Test name
Test status
Simulation time 245447156 ps
CPU time 1.48 seconds
Started Mar 05 12:42:33 PM PST 24
Finished Mar 05 12:42:34 PM PST 24
Peak memory 200516 kb
Host smart-c7c15167-447c-43d7-a7e3-4e7875cac022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267340745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4267340745
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.953951969
Short name T102
Test name
Test status
Simulation time 9693606595 ps
CPU time 34.38 seconds
Started Mar 05 12:42:16 PM PST 24
Finished Mar 05 12:42:51 PM PST 24
Peak memory 200576 kb
Host smart-70dd6b0e-063f-4d9a-8cb3-679b306cf7d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953951969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.953951969
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1131015640
Short name T357
Test name
Test status
Simulation time 131576748 ps
CPU time 1.62 seconds
Started Mar 05 12:42:22 PM PST 24
Finished Mar 05 12:42:24 PM PST 24
Peak memory 208092 kb
Host smart-5efff83a-b55f-4588-a83e-211a492f15cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131015640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1131015640
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3518017953
Short name T166
Test name
Test status
Simulation time 120249537 ps
CPU time 1.05 seconds
Started Mar 05 12:42:19 PM PST 24
Finished Mar 05 12:42:20 PM PST 24
Peak memory 200372 kb
Host smart-eb46487d-2c48-4ad0-ad8f-e86d70336c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518017953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3518017953
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1475120356
Short name T351
Test name
Test status
Simulation time 79356078 ps
CPU time 0.76 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:24 PM PST 24
Peak memory 200208 kb
Host smart-c52bb8ba-9d81-4c38-ab60-6be534b4e75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475120356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1475120356
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.340666838
Short name T41
Test name
Test status
Simulation time 1215615806 ps
CPU time 5.71 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:16 PM PST 24
Peak memory 221700 kb
Host smart-475fe60f-3856-476e-bdd3-e571858e74c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340666838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.340666838
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1390804007
Short name T281
Test name
Test status
Simulation time 244031419 ps
CPU time 1.06 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 217076 kb
Host smart-1837e6e5-f214-4a53-820e-d23d5461683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390804007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1390804007
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3872263795
Short name T15
Test name
Test status
Simulation time 203290609 ps
CPU time 0.95 seconds
Started Mar 05 12:42:09 PM PST 24
Finished Mar 05 12:42:10 PM PST 24
Peak memory 200160 kb
Host smart-bbcd008e-416d-44fa-a9ed-9cfcb97b946a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872263795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3872263795
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1899025731
Short name T443
Test name
Test status
Simulation time 888493008 ps
CPU time 4.55 seconds
Started Mar 05 12:42:39 PM PST 24
Finished Mar 05 12:42:44 PM PST 24
Peak memory 200396 kb
Host smart-d808405d-e4f4-4960-8af4-9217c2613d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899025731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1899025731
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3429071069
Short name T188
Test name
Test status
Simulation time 179910880 ps
CPU time 1.18 seconds
Started Mar 05 12:42:11 PM PST 24
Finished Mar 05 12:42:13 PM PST 24
Peak memory 200276 kb
Host smart-cef283f3-ed97-45ff-aef8-24c24b00274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429071069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3429071069
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.278252677
Short name T182
Test name
Test status
Simulation time 126282791 ps
CPU time 1.25 seconds
Started Mar 05 12:42:02 PM PST 24
Finished Mar 05 12:42:03 PM PST 24
Peak memory 200504 kb
Host smart-89fd6c37-a63e-491c-b65d-1864b0088099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278252677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.278252677
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2379687398
Short name T436
Test name
Test status
Simulation time 380862071 ps
CPU time 1.75 seconds
Started Mar 05 12:42:08 PM PST 24
Finished Mar 05 12:42:09 PM PST 24
Peak memory 200364 kb
Host smart-b1b2cee4-3447-45df-bb89-d7ea86f03c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379687398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2379687398
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.862995302
Short name T157
Test name
Test status
Simulation time 127403192 ps
CPU time 1.62 seconds
Started Mar 05 12:42:14 PM PST 24
Finished Mar 05 12:42:15 PM PST 24
Peak memory 208336 kb
Host smart-6b441643-ad4d-4c23-a60e-ca59c713d0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862995302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.862995302
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2189424758
Short name T511
Test name
Test status
Simulation time 224913814 ps
CPU time 1.41 seconds
Started Mar 05 12:42:14 PM PST 24
Finished Mar 05 12:42:16 PM PST 24
Peak memory 200016 kb
Host smart-677da592-0774-47b6-b94a-8f1ac82650c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189424758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2189424758
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1325236398
Short name T232
Test name
Test status
Simulation time 63903297 ps
CPU time 0.77 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:20 PM PST 24
Peak memory 200248 kb
Host smart-b516fde1-c9ec-49f7-8dfa-8c1c30f0b666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325236398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1325236398
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2240475819
Short name T488
Test name
Test status
Simulation time 1234675179 ps
CPU time 5.62 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:16 PM PST 24
Peak memory 218224 kb
Host smart-45ae0f20-6fbc-4865-9751-b7f556fbf9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240475819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2240475819
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2742428253
Short name T141
Test name
Test status
Simulation time 244115260 ps
CPU time 1.09 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:24 PM PST 24
Peak memory 217168 kb
Host smart-3af45e74-5e6e-4b2f-88d7-e9888b839334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742428253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2742428253
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2971861886
Short name T323
Test name
Test status
Simulation time 212528172 ps
CPU time 0.92 seconds
Started Mar 05 12:42:10 PM PST 24
Finished Mar 05 12:42:11 PM PST 24
Peak memory 200008 kb
Host smart-ef7fe555-e946-4537-9686-be0d4f279092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971861886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2971861886
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1665604969
Short name T446
Test name
Test status
Simulation time 1837546782 ps
CPU time 6.25 seconds
Started Mar 05 12:42:26 PM PST 24
Finished Mar 05 12:42:32 PM PST 24
Peak memory 200544 kb
Host smart-07b87e7c-bc50-4a8b-aac0-5791def0e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665604969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1665604969
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3806862734
Short name T46
Test name
Test status
Simulation time 111533623 ps
CPU time 0.99 seconds
Started Mar 05 12:42:15 PM PST 24
Finished Mar 05 12:42:16 PM PST 24
Peak memory 200364 kb
Host smart-de171b80-9bdb-49bc-8c35-6727d9c40c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806862734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3806862734
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1535151506
Short name T159
Test name
Test status
Simulation time 190619081 ps
CPU time 1.42 seconds
Started Mar 05 12:42:15 PM PST 24
Finished Mar 05 12:42:17 PM PST 24
Peak memory 200592 kb
Host smart-f3763850-fbd2-480b-b137-dbdd0ff56536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535151506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1535151506
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3698473052
Short name T62
Test name
Test status
Simulation time 5074813865 ps
CPU time 23.32 seconds
Started Mar 05 12:42:11 PM PST 24
Finished Mar 05 12:42:34 PM PST 24
Peak memory 200432 kb
Host smart-1ec4b84d-7d41-439c-86da-5bc3f0a6f918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698473052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3698473052
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.4012181608
Short name T390
Test name
Test status
Simulation time 473779509 ps
CPU time 2.43 seconds
Started Mar 05 12:42:27 PM PST 24
Finished Mar 05 12:42:29 PM PST 24
Peak memory 200292 kb
Host smart-bea7f5d8-4333-4447-8db4-e38b420e7fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012181608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.4012181608
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3910768001
Short name T143
Test name
Test status
Simulation time 63663674 ps
CPU time 0.75 seconds
Started Mar 05 12:42:33 PM PST 24
Finished Mar 05 12:42:34 PM PST 24
Peak memory 200308 kb
Host smart-d51c3396-51ba-4eee-83bd-6fdc66292136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910768001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3910768001
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2715142041
Short name T373
Test name
Test status
Simulation time 77444042 ps
CPU time 0.81 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 200268 kb
Host smart-0e61d147-324a-4714-89dd-7aa6d297153e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715142041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2715142041
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1789758244
Short name T29
Test name
Test status
Simulation time 1901873978 ps
CPU time 7.47 seconds
Started Mar 05 12:42:13 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 221724 kb
Host smart-73e256bf-bc1e-4e8d-a77c-5e0a4c8cd5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789758244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1789758244
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3440156068
Short name T331
Test name
Test status
Simulation time 244658836 ps
CPU time 1.08 seconds
Started Mar 05 12:42:17 PM PST 24
Finished Mar 05 12:42:18 PM PST 24
Peak memory 217132 kb
Host smart-8268d84b-60c9-4b21-adaa-ea558c7a15fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440156068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3440156068
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2237994687
Short name T502
Test name
Test status
Simulation time 150110830 ps
CPU time 0.85 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 200148 kb
Host smart-d47ad3ed-337d-4b42-9e23-3b2cdfc1efcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237994687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2237994687
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3493411533
Short name T101
Test name
Test status
Simulation time 2110182414 ps
CPU time 8 seconds
Started Mar 05 12:42:15 PM PST 24
Finished Mar 05 12:42:23 PM PST 24
Peak memory 200536 kb
Host smart-87c5a447-1dc3-4495-9588-07d73cfd6e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493411533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3493411533
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2052515017
Short name T464
Test name
Test status
Simulation time 114206797 ps
CPU time 0.99 seconds
Started Mar 05 12:42:13 PM PST 24
Finished Mar 05 12:42:14 PM PST 24
Peak memory 200356 kb
Host smart-d5697a21-785e-47be-9191-47fca279e0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052515017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2052515017
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3476984983
Short name T396
Test name
Test status
Simulation time 113743563 ps
CPU time 1.15 seconds
Started Mar 05 12:42:11 PM PST 24
Finished Mar 05 12:42:12 PM PST 24
Peak memory 200564 kb
Host smart-3776452f-f92a-4ba0-8d47-8d8ce9e74f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476984983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3476984983
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1264488847
Short name T392
Test name
Test status
Simulation time 9104266299 ps
CPU time 34.23 seconds
Started Mar 05 12:42:40 PM PST 24
Finished Mar 05 12:43:14 PM PST 24
Peak memory 210300 kb
Host smart-2871e0a8-4fa5-400f-9eae-e6ddede946e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264488847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1264488847
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1504311552
Short name T327
Test name
Test status
Simulation time 139946163 ps
CPU time 1.69 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:22 PM PST 24
Peak memory 200212 kb
Host smart-38b5eb55-5de2-462a-b0e5-ca4c8f657381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504311552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1504311552
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3891905480
Short name T161
Test name
Test status
Simulation time 241028497 ps
CPU time 1.4 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:26 PM PST 24
Peak memory 200400 kb
Host smart-34b82f34-61a1-423c-8096-659de52926ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891905480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3891905480
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1429958232
Short name T263
Test name
Test status
Simulation time 67123183 ps
CPU time 0.75 seconds
Started Mar 05 12:42:22 PM PST 24
Finished Mar 05 12:42:22 PM PST 24
Peak memory 200268 kb
Host smart-9387a107-d9f4-4ad9-be28-824ff68c7d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429958232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1429958232
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1218914487
Short name T36
Test name
Test status
Simulation time 1901386562 ps
CPU time 7.64 seconds
Started Mar 05 12:42:19 PM PST 24
Finished Mar 05 12:42:27 PM PST 24
Peak memory 217176 kb
Host smart-c7a06fc9-3530-4e3e-ac87-95bd572cee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218914487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1218914487
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.520426999
Short name T312
Test name
Test status
Simulation time 246906765 ps
CPU time 1.09 seconds
Started Mar 05 12:42:19 PM PST 24
Finished Mar 05 12:42:20 PM PST 24
Peak memory 217160 kb
Host smart-438cb2e8-f198-448a-bda9-d8e99e8016c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520426999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.520426999
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2965326048
Short name T515
Test name
Test status
Simulation time 132318744 ps
CPU time 0.82 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 200156 kb
Host smart-82f44791-13c8-4d95-8adc-3489df684b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965326048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2965326048
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3763928371
Short name T236
Test name
Test status
Simulation time 717114486 ps
CPU time 3.96 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:24 PM PST 24
Peak memory 200580 kb
Host smart-f8053320-1082-433d-9409-664fdeab56f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763928371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3763928371
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3727802911
Short name T374
Test name
Test status
Simulation time 171530337 ps
CPU time 1.24 seconds
Started Mar 05 12:42:34 PM PST 24
Finished Mar 05 12:42:35 PM PST 24
Peak memory 200256 kb
Host smart-368de2ed-1e19-4807-bbc7-4aed9ac6556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727802911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3727802911
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.878617517
Short name T80
Test name
Test status
Simulation time 112781231 ps
CPU time 1.16 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:32 PM PST 24
Peak memory 200556 kb
Host smart-22919dc1-3b23-47a3-a432-67dbbac54673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878617517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.878617517
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1437779961
Short name T476
Test name
Test status
Simulation time 306818916 ps
CPU time 1.72 seconds
Started Mar 05 12:42:28 PM PST 24
Finished Mar 05 12:42:30 PM PST 24
Peak memory 200232 kb
Host smart-7ce4b957-58ef-40b3-a88a-5a0a623d22c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437779961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1437779961
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1414767449
Short name T12
Test name
Test status
Simulation time 314945698 ps
CPU time 2.07 seconds
Started Mar 05 12:42:35 PM PST 24
Finished Mar 05 12:42:37 PM PST 24
Peak memory 200248 kb
Host smart-e9bd65e9-e8b8-4a36-8e64-00b8bce5f537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414767449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1414767449
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1506305025
Short name T248
Test name
Test status
Simulation time 70940470 ps
CPU time 0.82 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:31 PM PST 24
Peak memory 200360 kb
Host smart-1c961ac8-2915-4c25-92cc-3ae3fa4e75b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506305025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1506305025
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.533970966
Short name T444
Test name
Test status
Simulation time 58078128 ps
CPU time 0.72 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:41:42 PM PST 24
Peak memory 200288 kb
Host smart-2ea0c4ab-5c21-4aba-82e8-c2f01039a5a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533970966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.533970966
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2355445162
Short name T422
Test name
Test status
Simulation time 1226244694 ps
CPU time 5.28 seconds
Started Mar 05 12:41:21 PM PST 24
Finished Mar 05 12:41:26 PM PST 24
Peak memory 217164 kb
Host smart-cea9625d-4848-4501-92e4-cf927b8e8d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355445162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2355445162
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.390793032
Short name T514
Test name
Test status
Simulation time 245290475 ps
CPU time 1.03 seconds
Started Mar 05 12:41:34 PM PST 24
Finished Mar 05 12:41:35 PM PST 24
Peak memory 217136 kb
Host smart-260ea239-97a2-4b4a-909f-af91d18246f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390793032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.390793032
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2604947157
Short name T225
Test name
Test status
Simulation time 85039651 ps
CPU time 0.75 seconds
Started Mar 05 12:41:34 PM PST 24
Finished Mar 05 12:41:35 PM PST 24
Peak memory 200016 kb
Host smart-66547909-d42a-4b81-b624-92deaecab58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604947157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2604947157
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3694309420
Short name T144
Test name
Test status
Simulation time 1229912033 ps
CPU time 4.87 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200392 kb
Host smart-5bacc81a-e8f9-4641-a2ea-99af192b99f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694309420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3694309420
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.285707074
Short name T67
Test name
Test status
Simulation time 8617142736 ps
CPU time 12.96 seconds
Started Mar 05 12:41:34 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 216512 kb
Host smart-2c57ae46-ba3c-4788-82ec-7f94d8b14513
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285707074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.285707074
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1055483423
Short name T414
Test name
Test status
Simulation time 146913869 ps
CPU time 1.16 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 200176 kb
Host smart-f890a371-c56a-4d9f-956b-3bb0d617d4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055483423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1055483423
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1449792689
Short name T87
Test name
Test status
Simulation time 251209024 ps
CPU time 1.51 seconds
Started Mar 05 12:41:36 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200468 kb
Host smart-912a03d2-0592-49f8-9884-931e130bbb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449792689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1449792689
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.286736492
Short name T45
Test name
Test status
Simulation time 5666287893 ps
CPU time 26.99 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:42:05 PM PST 24
Peak memory 200576 kb
Host smart-637326ff-4f63-4071-b24e-002bb740fbc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286736492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.286736492
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2066479569
Short name T186
Test name
Test status
Simulation time 408125842 ps
CPU time 2.44 seconds
Started Mar 05 12:41:22 PM PST 24
Finished Mar 05 12:41:25 PM PST 24
Peak memory 208424 kb
Host smart-f4aa6b8b-9762-4174-9b19-09da8f248ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066479569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2066479569
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1962477359
Short name T334
Test name
Test status
Simulation time 112153550 ps
CPU time 0.94 seconds
Started Mar 05 12:41:35 PM PST 24
Finished Mar 05 12:41:36 PM PST 24
Peak memory 200360 kb
Host smart-8dd08e62-0e0a-4327-8674-0a095713ca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962477359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1962477359
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3145366143
Short name T283
Test name
Test status
Simulation time 73524780 ps
CPU time 0.83 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:25 PM PST 24
Peak memory 200248 kb
Host smart-0539ebae-b58f-4fa0-bbad-814f4ce39e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145366143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3145366143
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1292270792
Short name T40
Test name
Test status
Simulation time 2177455261 ps
CPU time 7.42 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:31 PM PST 24
Peak memory 229596 kb
Host smart-445ec838-27b0-46d2-a483-3a2cf4e3114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292270792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1292270792
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3448366436
Short name T154
Test name
Test status
Simulation time 244202252 ps
CPU time 1.1 seconds
Started Mar 05 12:42:29 PM PST 24
Finished Mar 05 12:42:30 PM PST 24
Peak memory 217248 kb
Host smart-967a8947-9c5e-4fd7-be74-631b718252c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448366436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3448366436
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3340971081
Short name T17
Test name
Test status
Simulation time 110494682 ps
CPU time 0.77 seconds
Started Mar 05 12:42:52 PM PST 24
Finished Mar 05 12:42:53 PM PST 24
Peak memory 200152 kb
Host smart-6f9d3513-518f-46b0-a33f-db9b65e5d5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340971081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3340971081
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1591537395
Short name T388
Test name
Test status
Simulation time 1778132941 ps
CPU time 6.53 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:31 PM PST 24
Peak memory 200524 kb
Host smart-9be7bdc4-006a-41d4-b524-d8ee4af856aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591537395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1591537395
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4233379675
Short name T296
Test name
Test status
Simulation time 110605013 ps
CPU time 1.05 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:32 PM PST 24
Peak memory 200364 kb
Host smart-2387f903-175c-48dd-bc12-ed9d7943432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233379675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4233379675
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2568669450
Short name T333
Test name
Test status
Simulation time 118039282 ps
CPU time 1.14 seconds
Started Mar 05 12:42:16 PM PST 24
Finished Mar 05 12:42:17 PM PST 24
Peak memory 200492 kb
Host smart-8c3943ff-9d27-41d2-b672-0c02dde64676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568669450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2568669450
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2060839742
Short name T83
Test name
Test status
Simulation time 6521875296 ps
CPU time 25.01 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:48 PM PST 24
Peak memory 200576 kb
Host smart-ba797c85-73fe-45ad-8675-628a91fd3fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060839742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2060839742
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3375941781
Short name T421
Test name
Test status
Simulation time 116274312 ps
CPU time 1.43 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:25 PM PST 24
Peak memory 200184 kb
Host smart-d67c5f3f-cec6-44f6-836c-9dfa8c43447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375941781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3375941781
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.351221316
Short name T474
Test name
Test status
Simulation time 304984096 ps
CPU time 1.58 seconds
Started Mar 05 12:42:45 PM PST 24
Finished Mar 05 12:42:47 PM PST 24
Peak memory 200444 kb
Host smart-66e3cdc7-eeaa-4b1d-a65c-d721cd668a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351221316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.351221316
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.4152265461
Short name T378
Test name
Test status
Simulation time 71364728 ps
CPU time 0.77 seconds
Started Mar 05 12:42:25 PM PST 24
Finished Mar 05 12:42:25 PM PST 24
Peak memory 200252 kb
Host smart-87d32421-03e6-4bcc-90d9-6590c3203371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152265461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.4152265461
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3478774014
Short name T347
Test name
Test status
Simulation time 1226952235 ps
CPU time 5.21 seconds
Started Mar 05 12:42:32 PM PST 24
Finished Mar 05 12:42:37 PM PST 24
Peak memory 216676 kb
Host smart-c0b32a7d-67a4-4d44-a843-bafaa5935a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478774014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3478774014
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2033753148
Short name T533
Test name
Test status
Simulation time 244111815 ps
CPU time 1.08 seconds
Started Mar 05 12:42:19 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 217216 kb
Host smart-363d2a85-e81a-4151-901d-7ce3ee282093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033753148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2033753148
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.767514532
Short name T342
Test name
Test status
Simulation time 190445835 ps
CPU time 0.87 seconds
Started Mar 05 12:42:36 PM PST 24
Finished Mar 05 12:42:37 PM PST 24
Peak memory 200160 kb
Host smart-fbef0255-929a-476e-ad05-dfa1e19d14a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767514532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.767514532
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.712451053
Short name T177
Test name
Test status
Simulation time 712953223 ps
CPU time 4.14 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:35 PM PST 24
Peak memory 200456 kb
Host smart-84caadd8-ffd1-49f6-8ba9-6b443fa8bf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712451053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.712451053
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3705899964
Short name T332
Test name
Test status
Simulation time 153908272 ps
CPU time 1.12 seconds
Started Mar 05 12:42:27 PM PST 24
Finished Mar 05 12:42:28 PM PST 24
Peak memory 200376 kb
Host smart-6a2e3af8-c4b6-419a-951e-cc0fe1a63edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705899964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3705899964
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2353249903
Short name T289
Test name
Test status
Simulation time 197898737 ps
CPU time 1.32 seconds
Started Mar 05 12:42:30 PM PST 24
Finished Mar 05 12:42:32 PM PST 24
Peak memory 200516 kb
Host smart-8319531f-1276-45ed-8d8a-c85b08d92fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353249903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2353249903
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.689165618
Short name T227
Test name
Test status
Simulation time 3207898359 ps
CPU time 13.89 seconds
Started Mar 05 12:42:36 PM PST 24
Finished Mar 05 12:42:50 PM PST 24
Peak memory 200572 kb
Host smart-f4bfd35e-bbfb-4ac7-b004-1c160c4625c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689165618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.689165618
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1333427197
Short name T405
Test name
Test status
Simulation time 336651091 ps
CPU time 2.12 seconds
Started Mar 05 12:42:25 PM PST 24
Finished Mar 05 12:42:27 PM PST 24
Peak memory 200292 kb
Host smart-d0d1314f-10f8-4c35-aec7-d398916b8518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333427197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1333427197
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.207568288
Short name T49
Test name
Test status
Simulation time 272233034 ps
CPU time 1.55 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:33 PM PST 24
Peak memory 200480 kb
Host smart-76051e75-18d6-4ed1-bf8b-e11c6ecc75a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207568288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.207568288
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3456108487
Short name T339
Test name
Test status
Simulation time 84190960 ps
CPU time 0.79 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:24 PM PST 24
Peak memory 200216 kb
Host smart-82411d5b-42fb-4c52-9094-e543d4188131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456108487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3456108487
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1702223960
Short name T416
Test name
Test status
Simulation time 1895888860 ps
CPU time 6.98 seconds
Started Mar 05 12:42:35 PM PST 24
Finished Mar 05 12:42:42 PM PST 24
Peak memory 217764 kb
Host smart-6f422115-6765-4216-9522-621bcbd1537f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702223960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1702223960
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1390769762
Short name T132
Test name
Test status
Simulation time 244083633 ps
CPU time 1.04 seconds
Started Mar 05 12:42:34 PM PST 24
Finished Mar 05 12:42:36 PM PST 24
Peak memory 217128 kb
Host smart-c20b328b-12dd-4abe-bc4b-6c536b81d5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390769762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1390769762
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.251737472
Short name T20
Test name
Test status
Simulation time 177115536 ps
CPU time 0.86 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:31 PM PST 24
Peak memory 200148 kb
Host smart-c5bfe67d-0e9d-4e07-b701-32a367408396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251737472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.251737472
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3505978
Short name T316
Test name
Test status
Simulation time 1602924845 ps
CPU time 6.83 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:31 PM PST 24
Peak memory 200512 kb
Host smart-ac914c91-74ba-4025-ad01-328ca1ec0396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3505978
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3192258102
Short name T201
Test name
Test status
Simulation time 94942687 ps
CPU time 0.97 seconds
Started Mar 05 12:42:32 PM PST 24
Finished Mar 05 12:42:33 PM PST 24
Peak memory 200224 kb
Host smart-a421ea61-f2ed-4846-b016-b57f741856d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192258102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3192258102
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1362251253
Short name T277
Test name
Test status
Simulation time 113826151 ps
CPU time 1.16 seconds
Started Mar 05 12:42:28 PM PST 24
Finished Mar 05 12:42:29 PM PST 24
Peak memory 200428 kb
Host smart-d26b4d10-50b7-4e3b-a4dd-3cb7124dbf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362251253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1362251253
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3454862430
Short name T485
Test name
Test status
Simulation time 9150402821 ps
CPU time 34.15 seconds
Started Mar 05 12:42:30 PM PST 24
Finished Mar 05 12:43:05 PM PST 24
Peak memory 209836 kb
Host smart-37817bdf-fa87-4290-9147-4374062cfa93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454862430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3454862430
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.559481358
Short name T313
Test name
Test status
Simulation time 555537027 ps
CPU time 2.84 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:23 PM PST 24
Peak memory 200292 kb
Host smart-3d10d299-1f29-43ab-ac9a-e679a7ba2a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559481358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.559481358
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2288574330
Short name T76
Test name
Test status
Simulation time 147036689 ps
CPU time 1.23 seconds
Started Mar 05 12:42:29 PM PST 24
Finished Mar 05 12:42:30 PM PST 24
Peak memory 200444 kb
Host smart-712f3755-0bb1-4c4e-88e0-7946475a38a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288574330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2288574330
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2086306809
Short name T521
Test name
Test status
Simulation time 78530935 ps
CPU time 0.79 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 200364 kb
Host smart-8c707a5a-41b3-4eef-a828-eef8c6ccafc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086306809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2086306809
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3919725255
Short name T54
Test name
Test status
Simulation time 2170970826 ps
CPU time 7.65 seconds
Started Mar 05 12:42:35 PM PST 24
Finished Mar 05 12:42:42 PM PST 24
Peak memory 221280 kb
Host smart-dd7fec5d-06aa-42ea-ad6f-7da16ccca8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919725255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3919725255
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1694454864
Short name T196
Test name
Test status
Simulation time 244625762 ps
CPU time 1.08 seconds
Started Mar 05 12:42:43 PM PST 24
Finished Mar 05 12:42:44 PM PST 24
Peak memory 217160 kb
Host smart-961d2f0c-a93e-4e2f-bb7e-effc38e97efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694454864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1694454864
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3803420741
Short name T178
Test name
Test status
Simulation time 205701129 ps
CPU time 0.91 seconds
Started Mar 05 12:42:40 PM PST 24
Finished Mar 05 12:42:41 PM PST 24
Peak memory 200164 kb
Host smart-cf32bb08-8109-4142-91f3-2020d9fda226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803420741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3803420741
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3877219027
Short name T4
Test name
Test status
Simulation time 945748690 ps
CPU time 4.81 seconds
Started Mar 05 12:42:25 PM PST 24
Finished Mar 05 12:42:30 PM PST 24
Peak memory 200548 kb
Host smart-c7c92279-1519-43cd-b6e6-182603ac643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877219027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3877219027
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3296643148
Short name T176
Test name
Test status
Simulation time 172733834 ps
CPU time 1.26 seconds
Started Mar 05 12:42:15 PM PST 24
Finished Mar 05 12:42:17 PM PST 24
Peak memory 200420 kb
Host smart-dd14f67c-f4a8-4794-a8dd-58b694eb5b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296643148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3296643148
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1279054916
Short name T484
Test name
Test status
Simulation time 250658033 ps
CPU time 1.54 seconds
Started Mar 05 12:42:35 PM PST 24
Finished Mar 05 12:42:37 PM PST 24
Peak memory 200480 kb
Host smart-ea01de5f-5ddc-482a-84f0-987df51adcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279054916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1279054916
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3889540666
Short name T192
Test name
Test status
Simulation time 1976635505 ps
CPU time 7.87 seconds
Started Mar 05 12:42:32 PM PST 24
Finished Mar 05 12:42:40 PM PST 24
Peak memory 209800 kb
Host smart-3d017ed0-b6b0-496f-ba4a-e4ce37ba9394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889540666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3889540666
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.341467390
Short name T127
Test name
Test status
Simulation time 348241943 ps
CPU time 1.95 seconds
Started Mar 05 12:42:26 PM PST 24
Finished Mar 05 12:42:28 PM PST 24
Peak memory 200232 kb
Host smart-07c82de1-6707-4291-b05a-1cc39354679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341467390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.341467390
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3717876132
Short name T391
Test name
Test status
Simulation time 76995532 ps
CPU time 0.8 seconds
Started Mar 05 12:42:25 PM PST 24
Finished Mar 05 12:42:26 PM PST 24
Peak memory 200360 kb
Host smart-4df7a0d7-acad-4c43-a456-ea05dc1091d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717876132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3717876132
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3849044516
Short name T251
Test name
Test status
Simulation time 84790024 ps
CPU time 0.76 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:24 PM PST 24
Peak memory 200156 kb
Host smart-3582d539-cce6-4e21-acb3-acaef672ef71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849044516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3849044516
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3332069668
Short name T32
Test name
Test status
Simulation time 1918248077 ps
CPU time 6.83 seconds
Started Mar 05 12:42:29 PM PST 24
Finished Mar 05 12:42:36 PM PST 24
Peak memory 221308 kb
Host smart-02793401-98b9-46fd-92ea-49ca5bcba798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332069668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3332069668
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1558934789
Short name T350
Test name
Test status
Simulation time 244081245 ps
CPU time 1.12 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:25 PM PST 24
Peak memory 217136 kb
Host smart-e8b15e4a-ceb9-4fac-96dc-faa4f34fbeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558934789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1558934789
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1807157305
Short name T189
Test name
Test status
Simulation time 109872496 ps
CPU time 0.83 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:21 PM PST 24
Peak memory 200160 kb
Host smart-c8bd7001-e171-4ea2-a051-700f790d6bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807157305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1807157305
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3514431890
Short name T180
Test name
Test status
Simulation time 917838993 ps
CPU time 4.68 seconds
Started Mar 05 12:42:34 PM PST 24
Finished Mar 05 12:42:43 PM PST 24
Peak memory 200576 kb
Host smart-e5b051d1-dd7f-408b-bda9-67f989d38c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514431890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3514431890
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.100484263
Short name T433
Test name
Test status
Simulation time 113444550 ps
CPU time 1.03 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:25 PM PST 24
Peak memory 200356 kb
Host smart-01e940da-0344-4410-9045-2abd1720f801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100484263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.100484263
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3199220060
Short name T337
Test name
Test status
Simulation time 113705871 ps
CPU time 1.15 seconds
Started Mar 05 12:42:35 PM PST 24
Finished Mar 05 12:42:36 PM PST 24
Peak memory 200508 kb
Host smart-996583a6-3a95-44c5-9e97-b84692605fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199220060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3199220060
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1742868222
Short name T394
Test name
Test status
Simulation time 7017458078 ps
CPU time 25.19 seconds
Started Mar 05 12:42:32 PM PST 24
Finished Mar 05 12:42:57 PM PST 24
Peak memory 208696 kb
Host smart-0d1ee5d0-155c-4a27-a747-c1f317c8d85f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742868222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1742868222
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.988874670
Short name T56
Test name
Test status
Simulation time 331415398 ps
CPU time 2.18 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:26 PM PST 24
Peak memory 200296 kb
Host smart-d0e8124f-6b16-4d71-9b8b-074e25142b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988874670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.988874670
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3218334446
Short name T136
Test name
Test status
Simulation time 91403145 ps
CPU time 0.91 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:32 PM PST 24
Peak memory 200352 kb
Host smart-23771c64-3c03-4f66-95ff-41a93786fddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218334446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3218334446
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4138451033
Short name T244
Test name
Test status
Simulation time 68688119 ps
CPU time 0.77 seconds
Started Mar 05 12:42:36 PM PST 24
Finished Mar 05 12:42:47 PM PST 24
Peak memory 200036 kb
Host smart-ff562780-0522-43b1-ac73-b7a3aaf3edd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138451033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4138451033
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.649009660
Short name T494
Test name
Test status
Simulation time 1215504275 ps
CPU time 5.64 seconds
Started Mar 05 12:42:17 PM PST 24
Finished Mar 05 12:42:22 PM PST 24
Peak memory 217756 kb
Host smart-9dc1c028-8c03-42bb-9c24-31976bc79a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649009660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.649009660
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1010599395
Short name T489
Test name
Test status
Simulation time 245123673 ps
CPU time 1.04 seconds
Started Mar 05 12:42:28 PM PST 24
Finished Mar 05 12:42:29 PM PST 24
Peak memory 217120 kb
Host smart-a68ee110-15df-4977-8db2-7b0dfc302834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010599395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1010599395
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.140237719
Short name T319
Test name
Test status
Simulation time 167952913 ps
CPU time 0.85 seconds
Started Mar 05 12:42:45 PM PST 24
Finished Mar 05 12:42:46 PM PST 24
Peak memory 200164 kb
Host smart-dd4ad2ab-1f4b-48a2-adc8-08fe4331f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140237719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.140237719
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1430823470
Short name T513
Test name
Test status
Simulation time 955702961 ps
CPU time 4.81 seconds
Started Mar 05 12:42:23 PM PST 24
Finished Mar 05 12:42:28 PM PST 24
Peak memory 200468 kb
Host smart-a49ccc55-a09d-4bf7-910a-e29a807f524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430823470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1430823470
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1237702312
Short name T234
Test name
Test status
Simulation time 103482600 ps
CPU time 1.02 seconds
Started Mar 05 12:42:27 PM PST 24
Finished Mar 05 12:42:33 PM PST 24
Peak memory 200512 kb
Host smart-7badffb1-00d5-4460-a145-f35a733e3c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237702312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1237702312
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3134648456
Short name T315
Test name
Test status
Simulation time 224408572 ps
CPU time 1.4 seconds
Started Mar 05 12:42:29 PM PST 24
Finished Mar 05 12:42:31 PM PST 24
Peak memory 200484 kb
Host smart-3ad3177c-6e4f-4e6c-94be-7f43788476db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134648456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3134648456
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.618319708
Short name T395
Test name
Test status
Simulation time 8180088566 ps
CPU time 29.71 seconds
Started Mar 05 12:42:36 PM PST 24
Finished Mar 05 12:43:05 PM PST 24
Peak memory 208820 kb
Host smart-629b0181-bdfb-47a6-a564-e9a64736852e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618319708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.618319708
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.660440174
Short name T304
Test name
Test status
Simulation time 115396865 ps
CPU time 1.56 seconds
Started Mar 05 12:42:30 PM PST 24
Finished Mar 05 12:42:36 PM PST 24
Peak memory 200272 kb
Host smart-20a186d0-851b-4394-a301-f53e2f883f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660440174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.660440174
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2563521422
Short name T209
Test name
Test status
Simulation time 90777842 ps
CPU time 0.96 seconds
Started Mar 05 12:42:29 PM PST 24
Finished Mar 05 12:42:31 PM PST 24
Peak memory 200360 kb
Host smart-54bc0999-f11f-4c51-a2a7-2b084b211a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563521422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2563521422
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1543291404
Short name T153
Test name
Test status
Simulation time 71747346 ps
CPU time 0.8 seconds
Started Mar 05 12:42:37 PM PST 24
Finished Mar 05 12:42:38 PM PST 24
Peak memory 200200 kb
Host smart-909d045f-7c81-48b2-968d-cda40e9ee85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543291404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1543291404
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.4276944888
Short name T475
Test name
Test status
Simulation time 1230002495 ps
CPU time 5.34 seconds
Started Mar 05 12:42:40 PM PST 24
Finished Mar 05 12:42:46 PM PST 24
Peak memory 217512 kb
Host smart-ceada37f-22d7-4acb-a896-b423f6a6bd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276944888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4276944888
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2067896038
Short name T321
Test name
Test status
Simulation time 243611720 ps
CPU time 1.05 seconds
Started Mar 05 12:42:21 PM PST 24
Finished Mar 05 12:42:22 PM PST 24
Peak memory 217168 kb
Host smart-3189ce9e-466e-4dae-81a0-48b49c95ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067896038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2067896038
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2957990966
Short name T293
Test name
Test status
Simulation time 166909176 ps
CPU time 0.93 seconds
Started Mar 05 12:42:35 PM PST 24
Finished Mar 05 12:42:36 PM PST 24
Peak memory 199832 kb
Host smart-5de1693f-c255-4aad-9b0b-656e339868ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957990966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2957990966
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.654732931
Short name T382
Test name
Test status
Simulation time 1338540223 ps
CPU time 5.53 seconds
Started Mar 05 12:42:20 PM PST 24
Finished Mar 05 12:42:25 PM PST 24
Peak memory 200448 kb
Host smart-8c4dd4be-1f08-4e2d-a73b-5b793758cd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654732931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.654732931
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.547283216
Short name T522
Test name
Test status
Simulation time 104032291 ps
CPU time 0.99 seconds
Started Mar 05 12:42:32 PM PST 24
Finished Mar 05 12:42:33 PM PST 24
Peak memory 200292 kb
Host smart-c93f2eb2-a758-4d57-925b-e5abbf30db2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547283216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.547283216
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1649686867
Short name T258
Test name
Test status
Simulation time 257858753 ps
CPU time 1.49 seconds
Started Mar 05 12:42:28 PM PST 24
Finished Mar 05 12:42:29 PM PST 24
Peak memory 200444 kb
Host smart-52ce6030-b53c-47b6-9061-7665cb5bb52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649686867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1649686867
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3718902265
Short name T375
Test name
Test status
Simulation time 8415923367 ps
CPU time 27.35 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:52 PM PST 24
Peak memory 209264 kb
Host smart-01ad0109-435b-49d5-a3a4-84a18a55564d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718902265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3718902265
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2468503835
Short name T197
Test name
Test status
Simulation time 451579409 ps
CPU time 2.53 seconds
Started Mar 05 12:42:35 PM PST 24
Finished Mar 05 12:42:38 PM PST 24
Peak memory 200076 kb
Host smart-2d0b33b1-19a2-4a92-9939-18ae68bbc5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468503835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2468503835
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.88083716
Short name T48
Test name
Test status
Simulation time 103034163 ps
CPU time 0.94 seconds
Started Mar 05 12:42:24 PM PST 24
Finished Mar 05 12:42:25 PM PST 24
Peak memory 200368 kb
Host smart-81e8a674-f9cb-4614-848f-6ff1de0bda95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88083716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.88083716
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2788192195
Short name T219
Test name
Test status
Simulation time 67784135 ps
CPU time 0.77 seconds
Started Mar 05 12:42:37 PM PST 24
Finished Mar 05 12:42:38 PM PST 24
Peak memory 200156 kb
Host smart-19d38b5a-dbda-4eae-ab5c-30e7660c69a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788192195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2788192195
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3203932702
Short name T33
Test name
Test status
Simulation time 1224530648 ps
CPU time 5.81 seconds
Started Mar 05 12:42:34 PM PST 24
Finished Mar 05 12:42:40 PM PST 24
Peak memory 221788 kb
Host smart-9f0a9594-fd7e-40ee-bc2a-4ddab6cf81cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203932702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3203932702
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2536918431
Short name T470
Test name
Test status
Simulation time 243486011 ps
CPU time 1.1 seconds
Started Mar 05 12:42:34 PM PST 24
Finished Mar 05 12:42:35 PM PST 24
Peak memory 217084 kb
Host smart-99649d58-c52c-48df-8737-e40923f58549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536918431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2536918431
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1039249242
Short name T238
Test name
Test status
Simulation time 198570190 ps
CPU time 0.93 seconds
Started Mar 05 12:42:39 PM PST 24
Finished Mar 05 12:42:40 PM PST 24
Peak memory 200168 kb
Host smart-445d5ec6-c14c-4668-ac74-8271bc05b1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039249242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1039249242
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1019250187
Short name T114
Test name
Test status
Simulation time 1276467501 ps
CPU time 5.13 seconds
Started Mar 05 12:42:32 PM PST 24
Finished Mar 05 12:42:37 PM PST 24
Peak memory 200488 kb
Host smart-b342e6db-109f-4965-b9a7-31042dc44e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019250187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1019250187
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3373294417
Short name T393
Test name
Test status
Simulation time 140155128 ps
CPU time 1.1 seconds
Started Mar 05 12:42:34 PM PST 24
Finished Mar 05 12:42:35 PM PST 24
Peak memory 200296 kb
Host smart-70f79d7c-fc75-49ec-b57f-a99fd9bc6332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373294417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3373294417
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3621580907
Short name T346
Test name
Test status
Simulation time 113284784 ps
CPU time 1.19 seconds
Started Mar 05 12:42:22 PM PST 24
Finished Mar 05 12:42:23 PM PST 24
Peak memory 199960 kb
Host smart-a533ea3c-d594-4894-9332-5d544d198704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621580907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3621580907
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3998750202
Short name T429
Test name
Test status
Simulation time 10776446226 ps
CPU time 39.2 seconds
Started Mar 05 12:42:21 PM PST 24
Finished Mar 05 12:43:00 PM PST 24
Peak memory 208772 kb
Host smart-657186ef-23db-49c6-a231-7f691652fa3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998750202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3998750202
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.174822482
Short name T335
Test name
Test status
Simulation time 127108594 ps
CPU time 1.54 seconds
Started Mar 05 12:42:35 PM PST 24
Finished Mar 05 12:42:37 PM PST 24
Peak memory 200000 kb
Host smart-c669418d-7481-4c6c-835d-4801b3739b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174822482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.174822482
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3102486495
Short name T336
Test name
Test status
Simulation time 176357023 ps
CPU time 1.3 seconds
Started Mar 05 12:42:43 PM PST 24
Finished Mar 05 12:42:45 PM PST 24
Peak memory 200424 kb
Host smart-c8697d2c-1ee1-4ba1-8bbc-9635966c5386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102486495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3102486495
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3407017291
Short name T44
Test name
Test status
Simulation time 89581069 ps
CPU time 0.85 seconds
Started Mar 05 12:42:46 PM PST 24
Finished Mar 05 12:42:47 PM PST 24
Peak memory 200272 kb
Host smart-d8081620-2d2f-4aa3-84ca-6f033039c269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407017291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3407017291
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3246030386
Short name T369
Test name
Test status
Simulation time 1227420324 ps
CPU time 6.15 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:37 PM PST 24
Peak memory 217736 kb
Host smart-6a2c47fd-acdc-4ed7-a1ee-9131e25d9ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246030386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3246030386
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.407020915
Short name T179
Test name
Test status
Simulation time 245035177 ps
CPU time 1.03 seconds
Started Mar 05 12:42:33 PM PST 24
Finished Mar 05 12:42:34 PM PST 24
Peak memory 217148 kb
Host smart-9a7cc653-9599-4d9e-a561-fecd01b8baa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407020915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.407020915
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3174520643
Short name T260
Test name
Test status
Simulation time 157704034 ps
CPU time 0.82 seconds
Started Mar 05 12:42:26 PM PST 24
Finished Mar 05 12:42:27 PM PST 24
Peak memory 200160 kb
Host smart-93a01805-7953-4b32-aa3b-59ca7127bc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174520643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3174520643
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1314499437
Short name T137
Test name
Test status
Simulation time 1185255266 ps
CPU time 4.96 seconds
Started Mar 05 12:42:27 PM PST 24
Finished Mar 05 12:42:32 PM PST 24
Peak memory 200500 kb
Host smart-1cc1c07b-eb41-47f3-a7ff-1b47cd6d1560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314499437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1314499437
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.561076813
Short name T133
Test name
Test status
Simulation time 177870719 ps
CPU time 1.13 seconds
Started Mar 05 12:42:46 PM PST 24
Finished Mar 05 12:42:47 PM PST 24
Peak memory 200320 kb
Host smart-174481de-169e-4ded-a485-f12e7afd93b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561076813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.561076813
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.282906194
Short name T261
Test name
Test status
Simulation time 113867762 ps
CPU time 1.2 seconds
Started Mar 05 12:42:26 PM PST 24
Finished Mar 05 12:42:28 PM PST 24
Peak memory 200276 kb
Host smart-02fd9a01-e180-4a2f-a825-9483cd285a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282906194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.282906194
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2925211585
Short name T198
Test name
Test status
Simulation time 2909171898 ps
CPU time 12.86 seconds
Started Mar 05 12:42:33 PM PST 24
Finished Mar 05 12:42:46 PM PST 24
Peak memory 200588 kb
Host smart-49435c0b-62c9-4140-acd0-53645801214b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925211585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2925211585
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1898685370
Short name T372
Test name
Test status
Simulation time 142566354 ps
CPU time 1.81 seconds
Started Mar 05 12:42:32 PM PST 24
Finished Mar 05 12:42:39 PM PST 24
Peak memory 200196 kb
Host smart-d19ec078-d481-4111-92bb-79dd47320841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898685370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1898685370
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2852334471
Short name T452
Test name
Test status
Simulation time 79582861 ps
CPU time 0.88 seconds
Started Mar 05 12:42:28 PM PST 24
Finished Mar 05 12:42:29 PM PST 24
Peak memory 200304 kb
Host smart-d67344de-d1ea-49e3-9b2b-7fad5f93622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852334471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2852334471
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3922604975
Short name T151
Test name
Test status
Simulation time 73898915 ps
CPU time 0.77 seconds
Started Mar 05 12:42:27 PM PST 24
Finished Mar 05 12:42:28 PM PST 24
Peak memory 200044 kb
Host smart-e4440c52-1548-4c9f-af2a-6d632b967dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922604975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3922604975
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3694215236
Short name T437
Test name
Test status
Simulation time 2363833607 ps
CPU time 7.67 seconds
Started Mar 05 12:42:27 PM PST 24
Finished Mar 05 12:42:35 PM PST 24
Peak memory 221744 kb
Host smart-deda0188-cd76-4e62-9513-c9f116abf620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694215236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3694215236
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.213822007
Short name T525
Test name
Test status
Simulation time 243860393 ps
CPU time 1.09 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:32 PM PST 24
Peak memory 217056 kb
Host smart-8990c363-dc3b-42a6-b2ff-51c12844a1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213822007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.213822007
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1779967207
Short name T73
Test name
Test status
Simulation time 110285853 ps
CPU time 0.79 seconds
Started Mar 05 12:42:38 PM PST 24
Finished Mar 05 12:42:39 PM PST 24
Peak memory 200152 kb
Host smart-02cc8b51-c24f-4a6e-9cd8-d22043c5e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779967207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1779967207
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2357095897
Short name T294
Test name
Test status
Simulation time 1330217463 ps
CPU time 4.92 seconds
Started Mar 05 12:42:30 PM PST 24
Finished Mar 05 12:42:35 PM PST 24
Peak memory 200580 kb
Host smart-2f352bae-d5fb-406a-9241-0ede81228994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357095897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2357095897
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1036423037
Short name T24
Test name
Test status
Simulation time 151945552 ps
CPU time 1.08 seconds
Started Mar 05 12:42:25 PM PST 24
Finished Mar 05 12:42:26 PM PST 24
Peak memory 200364 kb
Host smart-9ac20e71-ae18-4f08-b4ef-b35994d98df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036423037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1036423037
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2636919002
Short name T435
Test name
Test status
Simulation time 125952653 ps
CPU time 1.23 seconds
Started Mar 05 12:42:31 PM PST 24
Finished Mar 05 12:42:33 PM PST 24
Peak memory 200364 kb
Host smart-2d44f2f1-72ff-45fa-960f-6c0e245b6024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636919002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2636919002
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2469788093
Short name T100
Test name
Test status
Simulation time 18476146264 ps
CPU time 63.54 seconds
Started Mar 05 12:42:41 PM PST 24
Finished Mar 05 12:43:44 PM PST 24
Peak memory 208768 kb
Host smart-f835e646-2eec-46a0-9910-607e5dbd5984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469788093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2469788093
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2580970874
Short name T187
Test name
Test status
Simulation time 451199706 ps
CPU time 2.47 seconds
Started Mar 05 12:42:37 PM PST 24
Finished Mar 05 12:42:40 PM PST 24
Peak memory 200308 kb
Host smart-31d72734-ee0e-42fe-a851-0fa96209de4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580970874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2580970874
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1490092067
Short name T50
Test name
Test status
Simulation time 166404470 ps
CPU time 1.27 seconds
Started Mar 05 12:42:29 PM PST 24
Finished Mar 05 12:42:30 PM PST 24
Peak memory 200436 kb
Host smart-cd3bd005-1809-4609-bbb6-01b5c7425c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490092067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1490092067
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2824254340
Short name T411
Test name
Test status
Simulation time 71188139 ps
CPU time 0.8 seconds
Started Mar 05 12:41:46 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 200152 kb
Host smart-fa81901b-f4f0-45b1-a482-247acae0b5e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824254340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2824254340
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3681359612
Short name T434
Test name
Test status
Simulation time 1221866011 ps
CPU time 5.87 seconds
Started Mar 05 12:41:23 PM PST 24
Finished Mar 05 12:41:29 PM PST 24
Peak memory 217688 kb
Host smart-35ea3e89-db96-49a0-a255-c1795d588bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681359612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3681359612
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2338312981
Short name T528
Test name
Test status
Simulation time 244821517 ps
CPU time 1.13 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:41:43 PM PST 24
Peak memory 217076 kb
Host smart-a9a7caf3-46b3-4ab1-9718-a3aa7e85d719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338312981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2338312981
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1577303334
Short name T495
Test name
Test status
Simulation time 79150979 ps
CPU time 0.76 seconds
Started Mar 05 12:42:04 PM PST 24
Finished Mar 05 12:42:05 PM PST 24
Peak memory 200148 kb
Host smart-f964b86f-d035-452c-bcdf-da132fcc8b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577303334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1577303334
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.537855855
Short name T359
Test name
Test status
Simulation time 1920665186 ps
CPU time 7.44 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 200572 kb
Host smart-d5e9016b-6a0e-43fa-b12d-3cbe3ecb3089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537855855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.537855855
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4150026068
Short name T203
Test name
Test status
Simulation time 140362791 ps
CPU time 1.16 seconds
Started Mar 05 12:41:30 PM PST 24
Finished Mar 05 12:41:31 PM PST 24
Peak memory 200252 kb
Host smart-1d91be39-9934-4ab7-a4e5-9171958cd49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150026068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4150026068
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3247827607
Short name T77
Test name
Test status
Simulation time 198579099 ps
CPU time 1.44 seconds
Started Mar 05 12:41:39 PM PST 24
Finished Mar 05 12:41:40 PM PST 24
Peak memory 200460 kb
Host smart-3feb3a25-0e56-420a-9f6f-24568132190d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247827607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3247827607
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2554287503
Short name T265
Test name
Test status
Simulation time 4579155757 ps
CPU time 18.94 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:41:57 PM PST 24
Peak memory 200468 kb
Host smart-7a14df1d-7189-4aea-96aa-963ff7e744e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554287503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2554287503
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.558285124
Short name T364
Test name
Test status
Simulation time 407834968 ps
CPU time 2.17 seconds
Started Mar 05 12:41:24 PM PST 24
Finished Mar 05 12:41:26 PM PST 24
Peak memory 200072 kb
Host smart-cd8f5523-fce7-4bdc-b044-8f9dc73551ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558285124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.558285124
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.619222170
Short name T467
Test name
Test status
Simulation time 149083294 ps
CPU time 1.05 seconds
Started Mar 05 12:41:21 PM PST 24
Finished Mar 05 12:41:22 PM PST 24
Peak memory 200256 kb
Host smart-d5f5ce19-04fa-4741-90a7-c36b078ce805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619222170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.619222170
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1688203634
Short name T267
Test name
Test status
Simulation time 81697239 ps
CPU time 0.84 seconds
Started Mar 05 12:41:44 PM PST 24
Finished Mar 05 12:41:55 PM PST 24
Peak memory 200252 kb
Host smart-3bdf2015-d006-4d4b-8cdf-ab09516078bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688203634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1688203634
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3588847275
Short name T37
Test name
Test status
Simulation time 1899422828 ps
CPU time 7.6 seconds
Started Mar 05 12:41:36 PM PST 24
Finished Mar 05 12:41:43 PM PST 24
Peak memory 216772 kb
Host smart-e86fad75-34a4-456e-a7aa-c527acaa5cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588847275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3588847275
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.725387107
Short name T229
Test name
Test status
Simulation time 243916565 ps
CPU time 1.06 seconds
Started Mar 05 12:41:35 PM PST 24
Finished Mar 05 12:41:36 PM PST 24
Peak memory 217172 kb
Host smart-81cea2f2-53ae-4091-864c-2fae1703fa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725387107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.725387107
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2781161256
Short name T300
Test name
Test status
Simulation time 116397121 ps
CPU time 0.88 seconds
Started Mar 05 12:41:31 PM PST 24
Finished Mar 05 12:41:33 PM PST 24
Peak memory 200052 kb
Host smart-148a9baa-b74f-4a9b-9f77-03f8ed17f72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781161256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2781161256
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2972063497
Short name T402
Test name
Test status
Simulation time 2125088544 ps
CPU time 7.89 seconds
Started Mar 05 12:41:51 PM PST 24
Finished Mar 05 12:41:59 PM PST 24
Peak memory 200468 kb
Host smart-f5cb60a3-f546-4acd-b8d3-ce538e69e9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972063497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2972063497
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3726699257
Short name T371
Test name
Test status
Simulation time 150661241 ps
CPU time 1.03 seconds
Started Mar 05 12:41:17 PM PST 24
Finished Mar 05 12:41:18 PM PST 24
Peak memory 200252 kb
Host smart-7ac91bed-cfb0-4cac-ad89-82b041ab842e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726699257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3726699257
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.821485928
Short name T126
Test name
Test status
Simulation time 251532278 ps
CPU time 1.68 seconds
Started Mar 05 12:41:25 PM PST 24
Finished Mar 05 12:41:27 PM PST 24
Peak memory 200384 kb
Host smart-07159cbd-49e1-41cf-ac92-97c5bdedd3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821485928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.821485928
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.4220996081
Short name T279
Test name
Test status
Simulation time 9529651717 ps
CPU time 36 seconds
Started Mar 05 12:41:21 PM PST 24
Finished Mar 05 12:41:57 PM PST 24
Peak memory 208636 kb
Host smart-49fe5e31-e8dc-4f34-a3e4-298b6ecda0bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220996081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.4220996081
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1959591684
Short name T389
Test name
Test status
Simulation time 452457817 ps
CPU time 2.75 seconds
Started Mar 05 12:41:39 PM PST 24
Finished Mar 05 12:41:42 PM PST 24
Peak memory 200296 kb
Host smart-5078c63d-980c-49d2-9c19-554d67490a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959591684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1959591684
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2547962811
Short name T297
Test name
Test status
Simulation time 103318002 ps
CPU time 0.85 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:41:39 PM PST 24
Peak memory 200292 kb
Host smart-dce1530f-d629-47a2-a86a-5fba5617977a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547962811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2547962811
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3557004668
Short name T531
Test name
Test status
Simulation time 59772070 ps
CPU time 0.74 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 200252 kb
Host smart-15ae6456-285b-4878-9ffe-3006cf91ac15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557004668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3557004668
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.826203744
Short name T459
Test name
Test status
Simulation time 1901885195 ps
CPU time 7.39 seconds
Started Mar 05 12:41:22 PM PST 24
Finished Mar 05 12:41:29 PM PST 24
Peak memory 217004 kb
Host smart-4a1c51cc-452c-4c72-8120-7c578263417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826203744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.826203744
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.112011032
Short name T98
Test name
Test status
Simulation time 244828958 ps
CPU time 1.03 seconds
Started Mar 05 12:41:50 PM PST 24
Finished Mar 05 12:41:57 PM PST 24
Peak memory 217132 kb
Host smart-baa29c5d-591d-4d3d-a100-3d62cca97d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112011032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.112011032
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.458941856
Short name T427
Test name
Test status
Simulation time 228083337 ps
CPU time 0.88 seconds
Started Mar 05 12:41:47 PM PST 24
Finished Mar 05 12:41:48 PM PST 24
Peak memory 200152 kb
Host smart-dc14c1fb-337e-4530-8bd8-d5faa0c7bb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458941856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.458941856
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.211625564
Short name T104
Test name
Test status
Simulation time 2060461469 ps
CPU time 7.47 seconds
Started Mar 05 12:41:30 PM PST 24
Finished Mar 05 12:41:37 PM PST 24
Peak memory 200368 kb
Host smart-d2338b78-b55f-47bd-ad5a-51febfae73cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211625564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.211625564
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4158351620
Short name T243
Test name
Test status
Simulation time 173900965 ps
CPU time 1.17 seconds
Started Mar 05 12:41:47 PM PST 24
Finished Mar 05 12:41:48 PM PST 24
Peak memory 200356 kb
Host smart-ecec5b84-e0db-427c-a023-0ce9eb6948d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158351620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4158351620
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.852576813
Short name T275
Test name
Test status
Simulation time 198290088 ps
CPU time 1.46 seconds
Started Mar 05 12:41:41 PM PST 24
Finished Mar 05 12:41:42 PM PST 24
Peak memory 200376 kb
Host smart-9c4c0355-cfd7-4dd1-bf2b-ae8ffaf7f0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852576813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.852576813
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.781240109
Short name T240
Test name
Test status
Simulation time 3490888606 ps
CPU time 16.73 seconds
Started Mar 05 12:41:30 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 200476 kb
Host smart-96caa7af-091a-448e-8f78-aad464e695ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781240109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.781240109
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2473271302
Short name T330
Test name
Test status
Simulation time 141123723 ps
CPU time 1.78 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:41:41 PM PST 24
Peak memory 200208 kb
Host smart-22398cd5-9cdb-4d4c-8674-fe6aab065fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473271302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2473271302
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2876530045
Short name T223
Test name
Test status
Simulation time 228654224 ps
CPU time 1.35 seconds
Started Mar 05 12:41:25 PM PST 24
Finished Mar 05 12:41:27 PM PST 24
Peak memory 200256 kb
Host smart-6e92a47c-97b8-414b-9d3c-3eba24b3cd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876530045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2876530045
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1016058612
Short name T138
Test name
Test status
Simulation time 70028289 ps
CPU time 0.73 seconds
Started Mar 05 12:41:38 PM PST 24
Finished Mar 05 12:41:38 PM PST 24
Peak memory 200152 kb
Host smart-7921f2c3-9b69-4cb6-8322-1342894d8343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016058612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1016058612
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3770921590
Short name T129
Test name
Test status
Simulation time 2345003562 ps
CPU time 8.77 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 217424 kb
Host smart-42ecf080-d673-49d4-9745-97d6c67c1f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770921590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3770921590
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2041246070
Short name T472
Test name
Test status
Simulation time 244120464 ps
CPU time 1.12 seconds
Started Mar 05 12:41:32 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 217064 kb
Host smart-7e060d3e-b4e8-4777-854b-cb44bd4c0d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041246070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2041246070
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.144463417
Short name T479
Test name
Test status
Simulation time 213694800 ps
CPU time 0.9 seconds
Started Mar 05 12:41:31 PM PST 24
Finished Mar 05 12:41:33 PM PST 24
Peak memory 200088 kb
Host smart-74fdc724-f451-4b89-a75c-b4739df01efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144463417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.144463417
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1637211273
Short name T457
Test name
Test status
Simulation time 951286293 ps
CPU time 4.91 seconds
Started Mar 05 12:41:48 PM PST 24
Finished Mar 05 12:41:53 PM PST 24
Peak memory 200576 kb
Host smart-44e6aa28-a1dd-4290-a681-8626ad5f985d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637211273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1637211273
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1181215243
Short name T440
Test name
Test status
Simulation time 99535985 ps
CPU time 0.97 seconds
Started Mar 05 12:41:22 PM PST 24
Finished Mar 05 12:41:24 PM PST 24
Peak memory 200256 kb
Host smart-c9345869-71cd-4fbe-99db-e6f3b49c455c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181215243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1181215243
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1218475244
Short name T167
Test name
Test status
Simulation time 225527405 ps
CPU time 1.39 seconds
Started Mar 05 12:41:25 PM PST 24
Finished Mar 05 12:41:26 PM PST 24
Peak memory 200464 kb
Host smart-7bc9e84f-b56c-4007-a044-b0d8e9e67578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218475244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1218475244
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4043332692
Short name T85
Test name
Test status
Simulation time 5557697353 ps
CPU time 20.2 seconds
Started Mar 05 12:41:40 PM PST 24
Finished Mar 05 12:42:01 PM PST 24
Peak memory 200508 kb
Host smart-fce7b464-dd76-42fd-bf3e-6089fae47401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043332692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4043332692
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.789017259
Short name T397
Test name
Test status
Simulation time 375870738 ps
CPU time 2.18 seconds
Started Mar 05 12:41:49 PM PST 24
Finished Mar 05 12:41:51 PM PST 24
Peak memory 208472 kb
Host smart-c72b6036-cff1-418a-a3d8-98a8c0227a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789017259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.789017259
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2824129816
Short name T324
Test name
Test status
Simulation time 161114708 ps
CPU time 1.3 seconds
Started Mar 05 12:41:27 PM PST 24
Finished Mar 05 12:41:28 PM PST 24
Peak memory 200384 kb
Host smart-11587c7a-cbb6-47a3-b8a6-4d297706ea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824129816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2824129816
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2926399425
Short name T340
Test name
Test status
Simulation time 74189672 ps
CPU time 0.74 seconds
Started Mar 05 12:41:37 PM PST 24
Finished Mar 05 12:41:37 PM PST 24
Peak memory 200156 kb
Host smart-af94651f-c2b1-4755-b7de-a8ba5fbabcfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926399425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2926399425
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1496212836
Short name T26
Test name
Test status
Simulation time 2349931058 ps
CPU time 8.02 seconds
Started Mar 05 12:41:29 PM PST 24
Finished Mar 05 12:41:37 PM PST 24
Peak memory 221732 kb
Host smart-58ac2f16-0318-4eef-b1be-b1491f448b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496212836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1496212836
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.917203475
Short name T205
Test name
Test status
Simulation time 244691765 ps
CPU time 1.14 seconds
Started Mar 05 12:41:28 PM PST 24
Finished Mar 05 12:41:29 PM PST 24
Peak memory 217072 kb
Host smart-5cab09de-ccdc-42f7-b1b4-8b3b7a792f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917203475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.917203475
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2090962898
Short name T155
Test name
Test status
Simulation time 109447366 ps
CPU time 0.75 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:41:43 PM PST 24
Peak memory 200148 kb
Host smart-015a6116-b380-4bbc-b246-679c96cd0b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090962898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2090962898
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3210887970
Short name T299
Test name
Test status
Simulation time 1549329601 ps
CPU time 6.1 seconds
Started Mar 05 12:41:42 PM PST 24
Finished Mar 05 12:41:48 PM PST 24
Peak memory 200472 kb
Host smart-06bef96f-c673-4a55-b920-ef0cb432900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210887970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3210887970
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4030512271
Short name T458
Test name
Test status
Simulation time 153701309 ps
CPU time 1.11 seconds
Started Mar 05 12:41:45 PM PST 24
Finished Mar 05 12:41:46 PM PST 24
Peak memory 200256 kb
Host smart-b9830d88-fd06-45bb-8c06-937e9e3ec095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030512271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.4030512271
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4000475985
Short name T181
Test name
Test status
Simulation time 186023033 ps
CPU time 1.33 seconds
Started Mar 05 12:41:33 PM PST 24
Finished Mar 05 12:41:34 PM PST 24
Peak memory 200460 kb
Host smart-c97177aa-d67e-4c82-aea7-b19afa4b681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000475985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4000475985
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1536823297
Short name T183
Test name
Test status
Simulation time 7773000104 ps
CPU time 31.52 seconds
Started Mar 05 12:41:39 PM PST 24
Finished Mar 05 12:42:11 PM PST 24
Peak memory 208664 kb
Host smart-e919685c-32fc-48d3-a835-73442af89ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536823297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1536823297
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2177396287
Short name T224
Test name
Test status
Simulation time 349957935 ps
CPU time 2.22 seconds
Started Mar 05 12:41:22 PM PST 24
Finished Mar 05 12:41:24 PM PST 24
Peak memory 200148 kb
Host smart-0697391f-136f-4a42-80ac-38283fc10cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177396287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2177396287
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3285864071
Short name T162
Test name
Test status
Simulation time 125442791 ps
CPU time 1.03 seconds
Started Mar 05 12:41:39 PM PST 24
Finished Mar 05 12:41:40 PM PST 24
Peak memory 200324 kb
Host smart-252fb1de-b866-4d00-8fea-63fc5efe1aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285864071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3285864071
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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