Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8381

1

T1

76

T3

24

T5

12

auto[1]

11261

1

T1

65

T3

20

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6185	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6566	1			T1	44		T2	1		T3	19
reset_info_cp[2]	2922	1			T1	25		T3	3		T4	1
reset_info_cp[4]	4032	1			T1	29		T3	8		T4	1
reset_info_cp[8]	110	1			T1	1		T3	1		T56	1
reset_info_cp[16]	118	1			T1	1		T12	1		T56	1
reset_info_cp[32]	107	1			T12	1		T56	1		T107	1
reset_info_cp[64]	98	1			T11	1		T12	2		T56	5
reset_info_cp[128]	124	1			T5	1		T11	1		T56	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3158	1			T1	19		T3	8		T5	12
reset_info_cp[1]	auto[1]	2788	1			T1	24		T3	10		T4	1
reset_info_cp[2]	auto[0]	902	1			T1	11		T3	1		T56	22
reset_info_cp[2]	auto[1]	2020	1			T1	14		T3	2		T4	1
reset_info_cp[4]	auto[0]	1416	1			T1	16		T3	4		T56	34
reset_info_cp[4]	auto[1]	2616	1			T1	13		T3	4		T4	1
reset_info_cp[8]	auto[0]	38	1			T3	1		T52	1		T147	1
reset_info_cp[8]	auto[1]	72	1			T1	1		T56	1		T57	1
reset_info_cp[16]	auto[0]	46	1			T12	1		T107	1		T50	1
reset_info_cp[16]	auto[1]	72	1			T1	1		T56	1		T107	1
reset_info_cp[32]	auto[0]	38	1			T12	1		T56	1		T107	1
reset_info_cp[32]	auto[1]	69	1			T57	2		T55	1		T44	1
reset_info_cp[64]	auto[0]	36	1			T11	1		T12	2		T56	2
reset_info_cp[64]	auto[1]	62	1			T56	3		T57	1		T44	1
reset_info_cp[128]	auto[0]	52	1			T11	1		T56	1		T107	1
reset_info_cp[128]	auto[1]	72	1			T5	1		T56	1		T44	1