Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8399

1

T1

76

T3

28

T5

12

auto[1]

11243

1

T1

65

T3

16

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6185	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6566	1			T1	44		T2	1		T3	19
reset_info_cp[2]	2922	1			T1	25		T3	3		T4	1
reset_info_cp[4]	4032	1			T1	29		T3	8		T4	1
reset_info_cp[8]	110	1			T1	1		T3	1		T56	1
reset_info_cp[16]	118	1			T1	1		T12	1		T56	1
reset_info_cp[32]	107	1			T12	1		T56	1		T107	1
reset_info_cp[64]	98	1			T11	1		T12	2		T56	5
reset_info_cp[128]	124	1			T5	1		T11	1		T56	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3142	1			T1	27		T3	12		T5	12
reset_info_cp[1]	auto[1]	2804	1			T1	16		T3	6		T4	1
reset_info_cp[2]	auto[0]	912	1			T1	9		T3	1		T56	23
reset_info_cp[2]	auto[1]	2010	1			T1	16		T3	2		T4	1
reset_info_cp[4]	auto[0]	1459	1			T1	12		T3	5		T56	25
reset_info_cp[4]	auto[1]	2573	1			T1	17		T3	3		T4	1
reset_info_cp[8]	auto[0]	44	1			T3	1		T52	1		T114	2
reset_info_cp[8]	auto[1]	66	1			T1	1		T56	1		T57	1
reset_info_cp[16]	auto[0]	54	1			T1	1		T12	1		T56	1
reset_info_cp[16]	auto[1]	64	1			T107	1		T57	1		T43	2
reset_info_cp[32]	auto[0]	36	1			T12	1		T56	1		T107	1
reset_info_cp[32]	auto[1]	71	1			T57	2		T44	1		T111	1
reset_info_cp[64]	auto[0]	40	1			T11	1		T12	2		T56	1
reset_info_cp[64]	auto[1]	58	1			T56	4		T57	1		T44	1
reset_info_cp[128]	auto[0]	49	1			T11	1		T56	1		T107	1
reset_info_cp[128]	auto[1]	75	1			T5	1		T56	1		T44	1