Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/24.rstmgr_smoke.3368608097 Mar 07 12:32:31 PM PST 24 Mar 07 12:32:32 PM PST 24 114230437 ps
T539 /workspace/coverage/default/23.rstmgr_reset.3075953025 Mar 07 12:32:43 PM PST 24 Mar 07 12:32:49 PM PST 24 1442375201 ps
T540 /workspace/coverage/default/37.rstmgr_alert_test.1556970239 Mar 07 12:33:07 PM PST 24 Mar 07 12:33:08 PM PST 24 82333039 ps
T541 /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3589851486 Mar 07 12:32:16 PM PST 24 Mar 07 12:32:18 PM PST 24 190699035 ps
T542 /workspace/coverage/default/14.rstmgr_reset.300234923 Mar 07 12:32:09 PM PST 24 Mar 07 12:32:16 PM PST 24 1481995981 ps
T64 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.621482623 Mar 07 12:26:54 PM PST 24 Mar 07 12:26:58 PM PST 24 157447068 ps
T67 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3891990541 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:14 PM PST 24 162699973 ps
T65 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2542445172 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:15 PM PST 24 791713286 ps
T66 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4116930836 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:14 PM PST 24 181664917 ps
T87 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3387563967 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:13 PM PST 24 135656396 ps
T68 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.384354779 Mar 07 12:27:13 PM PST 24 Mar 07 12:27:14 PM PST 24 115193792 ps
T125 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2511414673 Mar 07 12:27:07 PM PST 24 Mar 07 12:27:08 PM PST 24 61707356 ps
T85 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3180157003 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:14 PM PST 24 549861802 ps
T91 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3156880911 Mar 07 12:27:04 PM PST 24 Mar 07 12:27:07 PM PST 24 180317996 ps
T83 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1951896859 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:10 PM PST 24 243409341 ps
T84 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.334329327 Mar 07 12:27:07 PM PST 24 Mar 07 12:27:09 PM PST 24 219026768 ps
T86 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1908809532 Mar 07 12:26:54 PM PST 24 Mar 07 12:26:57 PM PST 24 459524836 ps
T126 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3030055623 Mar 07 12:27:05 PM PST 24 Mar 07 12:27:07 PM PST 24 224857784 ps
T543 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3586906476 Mar 07 12:27:06 PM PST 24 Mar 07 12:27:14 PM PST 24 1553909303 ps
T127 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.115028837 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:09 PM PST 24 62153391 ps
T88 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.555315685 Mar 07 12:27:07 PM PST 24 Mar 07 12:27:09 PM PST 24 508909639 ps
T128 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3322759070 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:43 PM PST 24 76999676 ps
T102 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.419546335 Mar 07 12:26:58 PM PST 24 Mar 07 12:27:00 PM PST 24 114108578 ps
T129 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.683142872 Mar 07 12:26:55 PM PST 24 Mar 07 12:26:57 PM PST 24 143207129 ps
T130 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2431971300 Mar 07 12:26:49 PM PST 24 Mar 07 12:26:51 PM PST 24 217790149 ps
T131 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1953256243 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:11 PM PST 24 192820813 ps
T132 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1742421264 Mar 07 12:27:02 PM PST 24 Mar 07 12:27:04 PM PST 24 140236874 ps
T95 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2977743144 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:14 PM PST 24 465084844 ps
T89 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.669283712 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:15 PM PST 24 898737460 ps
T544 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3104986181 Mar 07 12:26:53 PM PST 24 Mar 07 12:27:04 PM PST 24 2304301035 ps
T133 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.546483334 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:13 PM PST 24 57952752 ps
T103 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1979474623 Mar 07 12:26:47 PM PST 24 Mar 07 12:26:49 PM PST 24 118621440 ps
T545 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3296383704 Mar 07 12:27:01 PM PST 24 Mar 07 12:27:02 PM PST 24 87415812 ps
T546 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2270040509 Mar 07 12:27:43 PM PST 24 Mar 07 12:27:45 PM PST 24 251952996 ps
T547 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1764807353 Mar 07 12:27:31 PM PST 24 Mar 07 12:27:33 PM PST 24 507987790 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1733591148 Mar 07 12:26:47 PM PST 24 Mar 07 12:26:49 PM PST 24 132440011 ps
T549 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.678420550 Mar 07 12:26:48 PM PST 24 Mar 07 12:26:50 PM PST 24 71528453 ps
T550 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1440455229 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:14 PM PST 24 203699388 ps
T100 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1077526971 Mar 07 12:27:13 PM PST 24 Mar 07 12:27:14 PM PST 24 118330225 ps
T551 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.909498399 Mar 07 12:26:50 PM PST 24 Mar 07 12:26:53 PM PST 24 279581835 ps
T90 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2945526993 Mar 07 12:26:56 PM PST 24 Mar 07 12:26:58 PM PST 24 125955952 ps
T92 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1435241667 Mar 07 12:27:06 PM PST 24 Mar 07 12:27:08 PM PST 24 184449918 ps
T552 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2762435853 Mar 07 12:27:02 PM PST 24 Mar 07 12:27:03 PM PST 24 163530510 ps
T553 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3776112382 Mar 07 12:26:57 PM PST 24 Mar 07 12:27:00 PM PST 24 878533635 ps
T554 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3561910884 Mar 07 12:27:19 PM PST 24 Mar 07 12:27:20 PM PST 24 149365821 ps
T555 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1450160433 Mar 07 12:27:31 PM PST 24 Mar 07 12:27:32 PM PST 24 74456048 ps
T104 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.764057016 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:44 PM PST 24 111821248 ps
T97 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3532105892 Mar 07 12:27:27 PM PST 24 Mar 07 12:27:29 PM PST 24 194662285 ps
T99 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1468003627 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:11 PM PST 24 165245887 ps
T98 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1078010378 Mar 07 12:26:54 PM PST 24 Mar 07 12:26:57 PM PST 24 136731215 ps
T556 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.345232437 Mar 07 12:26:48 PM PST 24 Mar 07 12:26:52 PM PST 24 495160585 ps
T93 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3060446524 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:44 PM PST 24 485456775 ps
T557 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2786279639 Mar 07 12:27:03 PM PST 24 Mar 07 12:27:04 PM PST 24 104241461 ps
T101 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.4195663192 Mar 07 12:27:00 PM PST 24 Mar 07 12:27:02 PM PST 24 206164338 ps
T558 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3074768131 Mar 07 12:26:48 PM PST 24 Mar 07 12:26:52 PM PST 24 351748276 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3931024565 Mar 07 12:27:06 PM PST 24 Mar 07 12:27:08 PM PST 24 122321341 ps
T96 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.788623552 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:10 PM PST 24 439401397 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1843662440 Mar 07 12:26:53 PM PST 24 Mar 07 12:26:54 PM PST 24 73038032 ps
T146 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.328458099 Mar 07 12:27:17 PM PST 24 Mar 07 12:27:21 PM PST 24 1043213254 ps
T561 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4246075661 Mar 07 12:27:04 PM PST 24 Mar 07 12:27:06 PM PST 24 419066855 ps
T94 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4177549403 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:12 PM PST 24 529203101 ps
T562 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.528943237 Mar 07 12:26:50 PM PST 24 Mar 07 12:26:54 PM PST 24 251908466 ps
T563 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4218197346 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:10 PM PST 24 128445685 ps
T564 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3662521818 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:14 PM PST 24 232778073 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1310021793 Mar 07 12:27:39 PM PST 24 Mar 07 12:27:40 PM PST 24 145574295 ps
T566 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1378946691 Mar 07 12:26:43 PM PST 24 Mar 07 12:26:46 PM PST 24 425290088 ps
T567 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2983933840 Mar 07 12:27:04 PM PST 24 Mar 07 12:27:06 PM PST 24 231203251 ps
T568 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2320201659 Mar 07 12:26:55 PM PST 24 Mar 07 12:27:02 PM PST 24 1166038502 ps
T569 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1939502934 Mar 07 12:27:02 PM PST 24 Mar 07 12:27:03 PM PST 24 197820338 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2913805700 Mar 07 12:26:08 PM PST 24 Mar 07 12:26:09 PM PST 24 67621033 ps
T571 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1603571508 Mar 07 12:26:48 PM PST 24 Mar 07 12:26:52 PM PST 24 362774522 ps
T572 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.511291047 Mar 07 12:27:05 PM PST 24 Mar 07 12:27:07 PM PST 24 451870918 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1819512434 Mar 07 12:26:02 PM PST 24 Mar 07 12:26:03 PM PST 24 133739014 ps
T574 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.456757805 Mar 07 12:28:08 PM PST 24 Mar 07 12:28:10 PM PST 24 98108000 ps
T575 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.750111913 Mar 07 12:27:02 PM PST 24 Mar 07 12:27:05 PM PST 24 369112212 ps
T576 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1009326525 Mar 07 12:27:41 PM PST 24 Mar 07 12:27:42 PM PST 24 74914381 ps
T577 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3515899718 Mar 07 12:27:27 PM PST 24 Mar 07 12:27:28 PM PST 24 63652990 ps
T578 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.534172572 Mar 07 12:27:19 PM PST 24 Mar 07 12:27:20 PM PST 24 156039968 ps
T579 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.596593437 Mar 07 12:27:15 PM PST 24 Mar 07 12:27:17 PM PST 24 474235462 ps
T580 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.428043762 Mar 07 12:26:08 PM PST 24 Mar 07 12:26:11 PM PST 24 428943141 ps
T581 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3202743404 Mar 07 12:27:10 PM PST 24 Mar 07 12:27:11 PM PST 24 66403003 ps
T582 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1605585110 Mar 07 12:27:38 PM PST 24 Mar 07 12:27:42 PM PST 24 466822450 ps
T583 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.603807493 Mar 07 12:27:13 PM PST 24 Mar 07 12:27:17 PM PST 24 559120529 ps
T584 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.562900956 Mar 07 12:27:00 PM PST 24 Mar 07 12:27:04 PM PST 24 878630688 ps
T585 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1156038815 Mar 07 12:27:13 PM PST 24 Mar 07 12:27:15 PM PST 24 108564471 ps
T586 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1412935897 Mar 07 12:26:58 PM PST 24 Mar 07 12:27:01 PM PST 24 195034664 ps
T587 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1575042636 Mar 07 12:26:54 PM PST 24 Mar 07 12:26:55 PM PST 24 104871753 ps
T588 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3674634698 Mar 07 12:26:56 PM PST 24 Mar 07 12:26:57 PM PST 24 58492911 ps
T589 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2432976710 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:10 PM PST 24 151158107 ps
T590 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.388855240 Mar 07 12:27:11 PM PST 24 Mar 07 12:27:12 PM PST 24 56445396 ps
T591 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3973622710 Mar 07 12:27:03 PM PST 24 Mar 07 12:27:05 PM PST 24 465027150 ps
T592 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3035143915 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:10 PM PST 24 67813526 ps
T593 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1760154853 Mar 07 12:28:55 PM PST 24 Mar 07 12:28:56 PM PST 24 113787477 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2964225101 Mar 07 12:26:50 PM PST 24 Mar 07 12:26:53 PM PST 24 127446860 ps
T595 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2928052669 Mar 07 12:27:08 PM PST 24 Mar 07 12:27:09 PM PST 24 103818663 ps
T596 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3636125553 Mar 07 12:27:41 PM PST 24 Mar 07 12:27:42 PM PST 24 495322974 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4207398434 Mar 07 12:27:17 PM PST 24 Mar 07 12:27:19 PM PST 24 130188756 ps
T598 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.10261365 Mar 07 12:26:46 PM PST 24 Mar 07 12:26:48 PM PST 24 118032477 ps
T599 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1833871281 Mar 07 12:26:48 PM PST 24 Mar 07 12:26:49 PM PST 24 133076969 ps
T600 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3914504583 Mar 07 12:27:09 PM PST 24 Mar 07 12:27:10 PM PST 24 149363122 ps
T601 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3504924270 Mar 07 12:27:18 PM PST 24 Mar 07 12:27:19 PM PST 24 77994850 ps
T602 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1015389346 Mar 07 12:27:28 PM PST 24 Mar 07 12:27:30 PM PST 24 122231658 ps
T603 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2426519101 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:46 PM PST 24 878496380 ps
T604 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.871354208 Mar 07 12:27:04 PM PST 24 Mar 07 12:27:05 PM PST 24 85154784 ps
T605 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1673775372 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:13 PM PST 24 140193895 ps
T606 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.370813120 Mar 07 12:27:43 PM PST 24 Mar 07 12:27:44 PM PST 24 189872939 ps
T607 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.428666686 Mar 07 12:27:29 PM PST 24 Mar 07 12:27:31 PM PST 24 261194061 ps
T608 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3704519483 Mar 07 12:27:12 PM PST 24 Mar 07 12:27:15 PM PST 24 1236671662 ps
T609 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2423180532 Mar 07 12:27:17 PM PST 24 Mar 07 12:27:19 PM PST 24 208833463 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2570108017 Mar 07 12:26:51 PM PST 24 Mar 07 12:26:58 PM PST 24 479536349 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2260212580 Mar 07 12:27:29 PM PST 24 Mar 07 12:27:31 PM PST 24 487789881 ps
T612 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3941301198 Mar 07 12:27:13 PM PST 24 Mar 07 12:27:14 PM PST 24 87198144 ps
T613 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2854799996 Mar 07 12:27:13 PM PST 24 Mar 07 12:27:15 PM PST 24 260875435 ps
T614 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2811619888 Mar 07 12:26:57 PM PST 24 Mar 07 12:26:58 PM PST 24 53611987 ps
T615 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.605506961 Mar 07 12:26:47 PM PST 24 Mar 07 12:26:50 PM PST 24 133397493 ps
T616 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3081858218 Mar 07 12:26:53 PM PST 24 Mar 07 12:27:04 PM PST 24 2331594307 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1826185418 Mar 07 12:26:50 PM PST 24 Mar 07 12:26:52 PM PST 24 84783675 ps
T618 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1794681063 Mar 07 12:27:40 PM PST 24 Mar 07 12:27:41 PM PST 24 121488529 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2553708063 Mar 07 12:27:42 PM PST 24 Mar 07 12:27:44 PM PST 24 139858596 ps
T620 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3547767779 Mar 07 12:26:59 PM PST 24 Mar 07 12:27:00 PM PST 24 143191537 ps

Test location /workspace/coverage/default/33.rstmgr_stress_all.3204605766
Short name T1
Test name
Test status
Simulation time 2537766751 ps
CPU time 11.57 seconds
Started Mar 07 12:32:57 PM PST 24
Finished Mar 07 12:33:10 PM PST 24
Peak memory 209120 kb
Host smart-0d2e15a0-3800-43a6-81e9-9af357bbce07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204605766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3204605766
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.115454392
Short name T9
Test name
Test status
Simulation time 121791534 ps
CPU time 1.47 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200116 kb
Host smart-a8e7e531-f718-4d4f-a9fe-d119a8c19b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115454392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.115454392
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4116930836
Short name T66
Test name
Test status
Simulation time 181664917 ps
CPU time 1.79 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 208648 kb
Host smart-630b12d6-c4ce-45b0-ba15-069b4d261c6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116930836 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4116930836
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4291172371
Short name T69
Test name
Test status
Simulation time 8283681411 ps
CPU time 13.33 seconds
Started Mar 07 12:32:05 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 220808 kb
Host smart-2b77397b-b45d-4f4b-9aaa-87ce52669d9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291172371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4291172371
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1345979366
Short name T44
Test name
Test status
Simulation time 1881383526 ps
CPU time 7.52 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 216696 kb
Host smart-47880f2f-ff46-4dbc-9745-a6317f824c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345979366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1345979366
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1624439166
Short name T117
Test name
Test status
Simulation time 6491993884 ps
CPU time 20.97 seconds
Started Mar 07 12:33:06 PM PST 24
Finished Mar 07 12:33:28 PM PST 24
Peak memory 208772 kb
Host smart-226fc0bf-23df-4454-bd83-a361b923195a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624439166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1624439166
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.555315685
Short name T88
Test name
Test status
Simulation time 508909639 ps
CPU time 1.98 seconds
Started Mar 07 12:27:07 PM PST 24
Finished Mar 07 12:27:09 PM PST 24
Peak memory 200408 kb
Host smart-b79737e5-a171-4a1c-b833-68e7bae197d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555315685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.555315685
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1613067963
Short name T24
Test name
Test status
Simulation time 56661267 ps
CPU time 0.73 seconds
Started Mar 07 12:32:25 PM PST 24
Finished Mar 07 12:32:27 PM PST 24
Peak memory 200236 kb
Host smart-27977800-018e-412b-9623-945246f3536d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613067963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1613067963
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3534099069
Short name T56
Test name
Test status
Simulation time 5423832048 ps
CPU time 23.29 seconds
Started Mar 07 12:32:18 PM PST 24
Finished Mar 07 12:32:42 PM PST 24
Peak memory 200476 kb
Host smart-d7d955b1-76a9-4064-ba32-58c6e8d1a6ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534099069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3534099069
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3891990541
Short name T67
Test name
Test status
Simulation time 162699973 ps
CPU time 2.33 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 208488 kb
Host smart-944ff006-f987-4551-9484-3d9e9649a0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891990541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3891990541
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.933111815
Short name T154
Test name
Test status
Simulation time 154776881 ps
CPU time 1.13 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 200288 kb
Host smart-35fa52f7-17d0-4b32-a129-2b7d3608c446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933111815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.933111815
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2441612670
Short name T52
Test name
Test status
Simulation time 163958645 ps
CPU time 1.29 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:14 PM PST 24
Peak memory 200412 kb
Host smart-35cc09db-1aea-4eff-89da-c18981029165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441612670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2441612670
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4124166647
Short name T26
Test name
Test status
Simulation time 1876251999 ps
CPU time 7.14 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:33:23 PM PST 24
Peak memory 229424 kb
Host smart-fd5db90d-66a0-4f90-928c-43e3762dac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124166647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4124166647
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1908809532
Short name T86
Test name
Test status
Simulation time 459524836 ps
CPU time 1.9 seconds
Started Mar 07 12:26:54 PM PST 24
Finished Mar 07 12:26:57 PM PST 24
Peak memory 200280 kb
Host smart-92cb672d-704e-426d-acc9-51525c38f689
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908809532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1908809532
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3532105892
Short name T97
Test name
Test status
Simulation time 194662285 ps
CPU time 2 seconds
Started Mar 07 12:27:27 PM PST 24
Finished Mar 07 12:27:29 PM PST 24
Peak memory 208688 kb
Host smart-6dc9ecd8-42ab-4469-973d-9c73d7c9b0c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532105892 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3532105892
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1744122813
Short name T45
Test name
Test status
Simulation time 2354708103 ps
CPU time 10.07 seconds
Started Mar 07 12:32:47 PM PST 24
Finished Mar 07 12:32:57 PM PST 24
Peak memory 221188 kb
Host smart-5390e517-92ad-4a2d-87f1-4729033d499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744122813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1744122813
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.115028837
Short name T127
Test name
Test status
Simulation time 62153391 ps
CPU time 0.83 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:09 PM PST 24
Peak memory 200288 kb
Host smart-10a8ec9a-461c-4d8e-a168-dd625214a501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115028837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.115028837
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2537562418
Short name T21
Test name
Test status
Simulation time 160064461 ps
CPU time 0.84 seconds
Started Mar 07 12:32:29 PM PST 24
Finished Mar 07 12:32:31 PM PST 24
Peak memory 200020 kb
Host smart-2665d0a0-d58f-49b4-975e-e934998816d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537562418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2537562418
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2977743144
Short name T95
Test name
Test status
Simulation time 465084844 ps
CPU time 2.09 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 200296 kb
Host smart-0ebb5cb0-1ca7-4b03-94f5-0b1b6d772ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977743144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2977743144
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.669283712
Short name T89
Test name
Test status
Simulation time 898737460 ps
CPU time 3.13 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:15 PM PST 24
Peak memory 200312 kb
Host smart-55c0ef9a-1942-42ec-8e52-762f81ffb2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669283712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.669283712
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.428666686
Short name T607
Test name
Test status
Simulation time 261194061 ps
CPU time 1.66 seconds
Started Mar 07 12:27:29 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 200112 kb
Host smart-abdeb094-78da-48c0-b1c3-f2330c36970c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428666686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.428666686
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3586906476
Short name T543
Test name
Test status
Simulation time 1553909303 ps
CPU time 8.37 seconds
Started Mar 07 12:27:06 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 200412 kb
Host smart-24b9312c-955b-4908-aadd-7d58a75589f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586906476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
586906476
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1819512434
Short name T573
Test name
Test status
Simulation time 133739014 ps
CPU time 0.97 seconds
Started Mar 07 12:26:02 PM PST 24
Finished Mar 07 12:26:03 PM PST 24
Peak memory 200256 kb
Host smart-8801af1b-f994-4f43-b092-dc3034c73f95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819512434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
819512434
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1979474623
Short name T103
Test name
Test status
Simulation time 118621440 ps
CPU time 0.96 seconds
Started Mar 07 12:26:47 PM PST 24
Finished Mar 07 12:26:49 PM PST 24
Peak memory 200200 kb
Host smart-4de3046d-82d6-4a89-898d-51be47033e68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979474623 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1979474623
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2913805700
Short name T570
Test name
Test status
Simulation time 67621033 ps
CPU time 0.74 seconds
Started Mar 07 12:26:08 PM PST 24
Finished Mar 07 12:26:09 PM PST 24
Peak memory 200060 kb
Host smart-2ba2e90f-f9ea-4852-8402-0d550df5da77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913805700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2913805700
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.909498399
Short name T551
Test name
Test status
Simulation time 279581835 ps
CPU time 1.7 seconds
Started Mar 07 12:26:50 PM PST 24
Finished Mar 07 12:26:53 PM PST 24
Peak memory 200256 kb
Host smart-c6934dcf-2b10-480b-baf0-4a47c72f329a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909498399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.909498399
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.428043762
Short name T580
Test name
Test status
Simulation time 428943141 ps
CPU time 3.3 seconds
Started Mar 07 12:26:08 PM PST 24
Finished Mar 07 12:26:11 PM PST 24
Peak memory 208408 kb
Host smart-4ee61ff9-c5b6-4ab7-918f-500de791063a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428043762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.428043762
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3074768131
Short name T558
Test name
Test status
Simulation time 351748276 ps
CPU time 2.57 seconds
Started Mar 07 12:26:48 PM PST 24
Finished Mar 07 12:26:52 PM PST 24
Peak memory 200468 kb
Host smart-09015ab7-6967-4652-b822-223e40ea9fe2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074768131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
074768131
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2320201659
Short name T568
Test name
Test status
Simulation time 1166038502 ps
CPU time 5.41 seconds
Started Mar 07 12:26:55 PM PST 24
Finished Mar 07 12:27:02 PM PST 24
Peak memory 200516 kb
Host smart-335d7cd6-7acd-4e26-a0ad-218a5f9ff30c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320201659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
320201659
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.10261365
Short name T598
Test name
Test status
Simulation time 118032477 ps
CPU time 0.88 seconds
Started Mar 07 12:26:46 PM PST 24
Finished Mar 07 12:26:48 PM PST 24
Peak memory 200088 kb
Host smart-df6e5d4e-01a1-4f87-9f07-27f1542294cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10261365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.10261365
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.419546335
Short name T102
Test name
Test status
Simulation time 114108578 ps
CPU time 0.94 seconds
Started Mar 07 12:26:58 PM PST 24
Finished Mar 07 12:27:00 PM PST 24
Peak memory 199420 kb
Host smart-aecbb428-ea3f-4f3c-8ab5-d21d653ba19d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419546335 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.419546335
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.678420550
Short name T549
Test name
Test status
Simulation time 71528453 ps
CPU time 0.8 seconds
Started Mar 07 12:26:48 PM PST 24
Finished Mar 07 12:26:50 PM PST 24
Peak memory 200120 kb
Host smart-0a3a40b7-ca96-431c-b939-12f464665b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678420550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.678420550
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1733591148
Short name T548
Test name
Test status
Simulation time 132440011 ps
CPU time 1.2 seconds
Started Mar 07 12:26:47 PM PST 24
Finished Mar 07 12:26:49 PM PST 24
Peak memory 200272 kb
Host smart-31639d24-a7a0-4f78-b876-e31c84931645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733591148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1733591148
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1378946691
Short name T566
Test name
Test status
Simulation time 425290088 ps
CPU time 2.98 seconds
Started Mar 07 12:26:43 PM PST 24
Finished Mar 07 12:26:46 PM PST 24
Peak memory 210672 kb
Host smart-956077a0-cc69-474b-ab9a-ec0a1c09cd7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378946691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1378946691
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3156880911
Short name T91
Test name
Test status
Simulation time 180317996 ps
CPU time 1.6 seconds
Started Mar 07 12:27:04 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 208700 kb
Host smart-4ef9b94e-871e-45a9-82a3-e476e61653ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156880911 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3156880911
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2270040509
Short name T546
Test name
Test status
Simulation time 251952996 ps
CPU time 1.6 seconds
Started Mar 07 12:27:43 PM PST 24
Finished Mar 07 12:27:45 PM PST 24
Peak memory 200292 kb
Host smart-cc1cf61d-26ed-4e2f-8c00-d5b4245b35c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270040509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2270040509
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1412935897
Short name T586
Test name
Test status
Simulation time 195034664 ps
CPU time 3.03 seconds
Started Mar 07 12:26:58 PM PST 24
Finished Mar 07 12:27:01 PM PST 24
Peak memory 208580 kb
Host smart-8e3a9324-8823-4015-a7e5-2fb58c4409ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412935897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1412935897
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3704519483
Short name T608
Test name
Test status
Simulation time 1236671662 ps
CPU time 3.79 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:15 PM PST 24
Peak memory 200348 kb
Host smart-001f0b0e-926b-4f00-b392-af326dbbfb21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704519483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3704519483
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1939502934
Short name T569
Test name
Test status
Simulation time 197820338 ps
CPU time 1.33 seconds
Started Mar 07 12:27:02 PM PST 24
Finished Mar 07 12:27:03 PM PST 24
Peak memory 208488 kb
Host smart-caeb9be3-82b5-4557-bebc-54a275c20d63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939502934 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1939502934
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.871354208
Short name T604
Test name
Test status
Simulation time 85154784 ps
CPU time 0.87 seconds
Started Mar 07 12:27:04 PM PST 24
Finished Mar 07 12:27:05 PM PST 24
Peak memory 200184 kb
Host smart-2bb14fab-af68-4b18-aa44-f99bee0fe106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871354208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.871354208
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3914504583
Short name T600
Test name
Test status
Simulation time 149363122 ps
CPU time 1.12 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 200220 kb
Host smart-1bed2a99-a220-4646-a73d-bd6181b41450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914504583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3914504583
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1015389346
Short name T602
Test name
Test status
Simulation time 122231658 ps
CPU time 1.74 seconds
Started Mar 07 12:27:28 PM PST 24
Finished Mar 07 12:27:30 PM PST 24
Peak memory 215956 kb
Host smart-c5824a4b-7103-42c1-aa32-5705bda0a8ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015389346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1015389346
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4246075661
Short name T561
Test name
Test status
Simulation time 419066855 ps
CPU time 1.86 seconds
Started Mar 07 12:27:04 PM PST 24
Finished Mar 07 12:27:06 PM PST 24
Peak memory 200456 kb
Host smart-7ba228b9-3660-4fab-9aa5-fd1942c3f9be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246075661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4246075661
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1673775372
Short name T605
Test name
Test status
Simulation time 140193895 ps
CPU time 1.1 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:13 PM PST 24
Peak memory 200172 kb
Host smart-48d2ad63-f1e7-4697-a941-ab7a9211d9ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673775372 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1673775372
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.388855240
Short name T590
Test name
Test status
Simulation time 56445396 ps
CPU time 0.81 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 200040 kb
Host smart-bf9213db-631d-416e-876f-228f902d23d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388855240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.388855240
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2786279639
Short name T557
Test name
Test status
Simulation time 104241461 ps
CPU time 1.23 seconds
Started Mar 07 12:27:03 PM PST 24
Finished Mar 07 12:27:04 PM PST 24
Peak memory 200316 kb
Host smart-04249180-1987-4103-840c-9f87e2f198b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786279639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2786279639
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4177549403
Short name T94
Test name
Test status
Simulation time 529203101 ps
CPU time 3.66 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:12 PM PST 24
Peak memory 208628 kb
Host smart-9e44e890-d48b-40c9-9e65-8d2725c9116c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177549403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4177549403
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.511291047
Short name T572
Test name
Test status
Simulation time 451870918 ps
CPU time 1.74 seconds
Started Mar 07 12:27:05 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 200388 kb
Host smart-fad84431-13d7-46a8-9248-38eb1c542498
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511291047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.511291047
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2511414673
Short name T125
Test name
Test status
Simulation time 61707356 ps
CPU time 0.74 seconds
Started Mar 07 12:27:07 PM PST 24
Finished Mar 07 12:27:08 PM PST 24
Peak memory 200108 kb
Host smart-fc15b21b-081c-4705-a0fb-e29bb5233cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511414673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2511414673
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2983933840
Short name T567
Test name
Test status
Simulation time 231203251 ps
CPU time 1.56 seconds
Started Mar 07 12:27:04 PM PST 24
Finished Mar 07 12:27:06 PM PST 24
Peak memory 200456 kb
Host smart-4ff57f2b-4ddb-41e3-8f9e-262f3a502ae9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983933840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2983933840
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1951896859
Short name T83
Test name
Test status
Simulation time 243409341 ps
CPU time 1.88 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 208640 kb
Host smart-8a0dfc84-9d1b-4059-8314-45cb415265af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951896859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1951896859
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.384354779
Short name T68
Test name
Test status
Simulation time 115193792 ps
CPU time 0.97 seconds
Started Mar 07 12:27:13 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 200200 kb
Host smart-4112d4a9-216f-4bbe-80b1-0fc38ee3edde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384354779 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.384354779
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3515899718
Short name T577
Test name
Test status
Simulation time 63652990 ps
CPU time 0.88 seconds
Started Mar 07 12:27:27 PM PST 24
Finished Mar 07 12:27:28 PM PST 24
Peak memory 200224 kb
Host smart-81f9c633-be99-4016-a110-050c07c97ec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515899718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3515899718
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3931024565
Short name T559
Test name
Test status
Simulation time 122321341 ps
CPU time 1.07 seconds
Started Mar 07 12:27:06 PM PST 24
Finished Mar 07 12:27:08 PM PST 24
Peak memory 200096 kb
Host smart-0af9d57b-a4be-428f-975c-8b025c463961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931024565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3931024565
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.334329327
Short name T84
Test name
Test status
Simulation time 219026768 ps
CPU time 1.88 seconds
Started Mar 07 12:27:07 PM PST 24
Finished Mar 07 12:27:09 PM PST 24
Peak memory 208528 kb
Host smart-b885bfd1-ef90-4f0f-a0ce-cc1ee005306b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334329327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.334329327
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1764807353
Short name T547
Test name
Test status
Simulation time 507987790 ps
CPU time 1.9 seconds
Started Mar 07 12:27:31 PM PST 24
Finished Mar 07 12:27:33 PM PST 24
Peak memory 200356 kb
Host smart-c403a47c-5d1d-4e43-a096-11fe45ab302e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764807353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1764807353
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3322759070
Short name T128
Test name
Test status
Simulation time 76999676 ps
CPU time 0.85 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:43 PM PST 24
Peak memory 198300 kb
Host smart-52bfb10e-c3f9-4222-8c60-5e722cb7486e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322759070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3322759070
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1760154853
Short name T593
Test name
Test status
Simulation time 113787477 ps
CPU time 1.06 seconds
Started Mar 07 12:28:55 PM PST 24
Finished Mar 07 12:28:56 PM PST 24
Peak memory 200352 kb
Host smart-11450cce-9db0-4ee1-a0ea-61bce1249954
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760154853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1760154853
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1156038815
Short name T585
Test name
Test status
Simulation time 108564471 ps
CPU time 1.37 seconds
Started Mar 07 12:27:13 PM PST 24
Finished Mar 07 12:27:15 PM PST 24
Peak memory 208556 kb
Host smart-0a18afc1-8986-44f9-9e3d-1989c1e19462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156038815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1156038815
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3547767779
Short name T620
Test name
Test status
Simulation time 143191537 ps
CPU time 1.12 seconds
Started Mar 07 12:26:59 PM PST 24
Finished Mar 07 12:27:00 PM PST 24
Peak memory 208484 kb
Host smart-3b7040d1-6cd5-4834-bc4a-8e430b9c6b8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547767779 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3547767779
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3202743404
Short name T581
Test name
Test status
Simulation time 66403003 ps
CPU time 0.82 seconds
Started Mar 07 12:27:10 PM PST 24
Finished Mar 07 12:27:11 PM PST 24
Peak memory 200200 kb
Host smart-e049b6f9-9691-411f-98cd-dc428f2d2717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202743404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3202743404
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3662521818
Short name T564
Test name
Test status
Simulation time 232778073 ps
CPU time 1.64 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 200292 kb
Host smart-6620f09a-5dc3-4507-981a-948dbc02deb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662521818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3662521818
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1605585110
Short name T582
Test name
Test status
Simulation time 466822450 ps
CPU time 3.74 seconds
Started Mar 07 12:27:38 PM PST 24
Finished Mar 07 12:27:42 PM PST 24
Peak memory 208480 kb
Host smart-d060e3f7-50d8-487d-b675-a60495c4e5f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605585110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1605585110
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3060446524
Short name T93
Test name
Test status
Simulation time 485456775 ps
CPU time 1.96 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:44 PM PST 24
Peak memory 198804 kb
Host smart-8f625e70-7ff8-4a7e-a407-bd7a43039424
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060446524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3060446524
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1794681063
Short name T618
Test name
Test status
Simulation time 121488529 ps
CPU time 1 seconds
Started Mar 07 12:27:40 PM PST 24
Finished Mar 07 12:27:41 PM PST 24
Peak memory 200288 kb
Host smart-0daa6e9b-16a3-43a2-9177-dd3d8c8924fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794681063 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1794681063
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3035143915
Short name T592
Test name
Test status
Simulation time 67813526 ps
CPU time 0.79 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 200132 kb
Host smart-db8a91ac-6bb3-4c43-be31-ef64742c76e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035143915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3035143915
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2928052669
Short name T595
Test name
Test status
Simulation time 103818663 ps
CPU time 1.2 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:09 PM PST 24
Peak memory 200284 kb
Host smart-a49ae80a-7df6-4ffd-af17-c6b7678eeb69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928052669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2928052669
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2432976710
Short name T589
Test name
Test status
Simulation time 151158107 ps
CPU time 1.99 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 208540 kb
Host smart-3eaa74a6-7479-48cc-ae77-38fe8742033d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432976710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2432976710
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.562900956
Short name T584
Test name
Test status
Simulation time 878630688 ps
CPU time 3.19 seconds
Started Mar 07 12:27:00 PM PST 24
Finished Mar 07 12:27:04 PM PST 24
Peak memory 200448 kb
Host smart-cd90a861-c088-4c19-a8ba-bcf8a993abf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562900956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.562900956
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4218197346
Short name T563
Test name
Test status
Simulation time 128445685 ps
CPU time 1.28 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 208416 kb
Host smart-62076882-b70d-4640-904e-6fcc6c6a4fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218197346 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.4218197346
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1009326525
Short name T576
Test name
Test status
Simulation time 74914381 ps
CPU time 0.83 seconds
Started Mar 07 12:27:41 PM PST 24
Finished Mar 07 12:27:42 PM PST 24
Peak memory 200284 kb
Host smart-7ee8c014-cdf7-4306-a90f-d91ff3bdedc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009326525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1009326525
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1953256243
Short name T131
Test name
Test status
Simulation time 192820813 ps
CPU time 1.41 seconds
Started Mar 07 12:27:09 PM PST 24
Finished Mar 07 12:27:11 PM PST 24
Peak memory 200316 kb
Host smart-5083ae68-f366-47e8-acff-fdc60a968bd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953256243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1953256243
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1468003627
Short name T99
Test name
Test status
Simulation time 165245887 ps
CPU time 2.35 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:11 PM PST 24
Peak memory 208560 kb
Host smart-0f0c679b-febd-4a52-907f-0c64ebb9ce83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468003627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1468003627
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3973622710
Short name T591
Test name
Test status
Simulation time 465027150 ps
CPU time 1.87 seconds
Started Mar 07 12:27:03 PM PST 24
Finished Mar 07 12:27:05 PM PST 24
Peak memory 200288 kb
Host smart-13ff1fe2-c2e2-410d-a0ae-e7c8be9079a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973622710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3973622710
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3561910884
Short name T554
Test name
Test status
Simulation time 149365821 ps
CPU time 1.03 seconds
Started Mar 07 12:27:19 PM PST 24
Finished Mar 07 12:27:20 PM PST 24
Peak memory 208340 kb
Host smart-f9874699-5cb6-474f-9a98-35662ec5b004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561910884 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3561910884
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3504924270
Short name T601
Test name
Test status
Simulation time 77994850 ps
CPU time 0.78 seconds
Started Mar 07 12:27:18 PM PST 24
Finished Mar 07 12:27:19 PM PST 24
Peak memory 200088 kb
Host smart-c47ed4d3-cb8f-48ef-a3c7-0ef6c58a4dc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504924270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3504924270
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.534172572
Short name T578
Test name
Test status
Simulation time 156039968 ps
CPU time 1.12 seconds
Started Mar 07 12:27:19 PM PST 24
Finished Mar 07 12:27:20 PM PST 24
Peak memory 200136 kb
Host smart-3c2dbd16-f42b-46ef-94d2-fdf08272f06b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534172572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.534172572
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.456757805
Short name T574
Test name
Test status
Simulation time 98108000 ps
CPU time 1.4 seconds
Started Mar 07 12:28:08 PM PST 24
Finished Mar 07 12:28:10 PM PST 24
Peak memory 208292 kb
Host smart-304e7564-8260-4691-bf9a-44124f5d7d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456757805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.456757805
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2426519101
Short name T603
Test name
Test status
Simulation time 878496380 ps
CPU time 3.24 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:46 PM PST 24
Peak memory 199040 kb
Host smart-319ac7d9-edcb-484d-8089-bbcf0879802c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426519101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2426519101
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.621482623
Short name T64
Test name
Test status
Simulation time 157447068 ps
CPU time 1.99 seconds
Started Mar 07 12:26:54 PM PST 24
Finished Mar 07 12:26:58 PM PST 24
Peak memory 200336 kb
Host smart-fc0a7935-dc4c-4471-b1cc-38c32fc3343b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621482623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.621482623
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3081858218
Short name T616
Test name
Test status
Simulation time 2331594307 ps
CPU time 10.2 seconds
Started Mar 07 12:26:53 PM PST 24
Finished Mar 07 12:27:04 PM PST 24
Peak memory 200228 kb
Host smart-d83060d5-4b93-4e42-9da4-0a0a1e8cb0de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081858218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
081858218
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1575042636
Short name T587
Test name
Test status
Simulation time 104871753 ps
CPU time 0.87 seconds
Started Mar 07 12:26:54 PM PST 24
Finished Mar 07 12:26:55 PM PST 24
Peak memory 200108 kb
Host smart-2dfa664b-1315-48cc-8901-2f40c50b1e4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575042636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
575042636
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2964225101
Short name T594
Test name
Test status
Simulation time 127446860 ps
CPU time 1.26 seconds
Started Mar 07 12:26:50 PM PST 24
Finished Mar 07 12:26:53 PM PST 24
Peak memory 216484 kb
Host smart-4633892f-46d0-46cd-9ff1-d154b8894254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964225101 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2964225101
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1843662440
Short name T560
Test name
Test status
Simulation time 73038032 ps
CPU time 0.76 seconds
Started Mar 07 12:26:53 PM PST 24
Finished Mar 07 12:26:54 PM PST 24
Peak memory 199920 kb
Host smart-6ed866fb-0b3f-4000-b402-5b114bca2937
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843662440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1843662440
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2431971300
Short name T130
Test name
Test status
Simulation time 217790149 ps
CPU time 1.8 seconds
Started Mar 07 12:26:49 PM PST 24
Finished Mar 07 12:26:51 PM PST 24
Peak memory 200412 kb
Host smart-64414d51-4188-45d0-b3ab-2889841de3b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431971300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2431971300
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1078010378
Short name T98
Test name
Test status
Simulation time 136731215 ps
CPU time 1.91 seconds
Started Mar 07 12:26:54 PM PST 24
Finished Mar 07 12:26:57 PM PST 24
Peak memory 208536 kb
Host smart-c60f359c-aa8b-499d-a9f8-c4986f29775f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078010378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1078010378
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3180157003
Short name T85
Test name
Test status
Simulation time 549861802 ps
CPU time 2.04 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 200404 kb
Host smart-56e38df1-0607-46ac-9b0e-1730ec64eac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180157003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3180157003
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1440455229
Short name T550
Test name
Test status
Simulation time 203699388 ps
CPU time 1.63 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 200220 kb
Host smart-8fad69a1-3af4-40c1-98f0-88ff195bbca6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440455229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
440455229
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2570108017
Short name T610
Test name
Test status
Simulation time 479536349 ps
CPU time 5.94 seconds
Started Mar 07 12:26:51 PM PST 24
Finished Mar 07 12:26:58 PM PST 24
Peak memory 200384 kb
Host smart-33fde324-329f-4818-8036-5a462d70b891
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570108017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
570108017
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1833871281
Short name T599
Test name
Test status
Simulation time 133076969 ps
CPU time 0.94 seconds
Started Mar 07 12:26:48 PM PST 24
Finished Mar 07 12:26:49 PM PST 24
Peak memory 200124 kb
Host smart-8567266a-1a93-495a-ad50-84e630d9c3cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833871281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
833871281
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2945526993
Short name T90
Test name
Test status
Simulation time 125955952 ps
CPU time 1.48 seconds
Started Mar 07 12:26:56 PM PST 24
Finished Mar 07 12:26:58 PM PST 24
Peak memory 207780 kb
Host smart-07ac3b89-d90d-4cc7-8079-b1f1a703c2f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945526993 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2945526993
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1826185418
Short name T617
Test name
Test status
Simulation time 84783675 ps
CPU time 0.86 seconds
Started Mar 07 12:26:50 PM PST 24
Finished Mar 07 12:26:52 PM PST 24
Peak memory 200124 kb
Host smart-84e7ca27-5fe0-43d5-9432-f440ee334209
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826185418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1826185418
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.605506961
Short name T615
Test name
Test status
Simulation time 133397493 ps
CPU time 1.4 seconds
Started Mar 07 12:26:47 PM PST 24
Finished Mar 07 12:26:50 PM PST 24
Peak memory 200368 kb
Host smart-093fbec2-22a7-4b8d-aecc-22db4dc29b9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605506961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.605506961
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1603571508
Short name T571
Test name
Test status
Simulation time 362774522 ps
CPU time 2.68 seconds
Started Mar 07 12:26:48 PM PST 24
Finished Mar 07 12:26:52 PM PST 24
Peak memory 208540 kb
Host smart-6622e5ce-4644-4572-bb71-4e2012cd3a97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603571508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1603571508
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.596593437
Short name T579
Test name
Test status
Simulation time 474235462 ps
CPU time 1.87 seconds
Started Mar 07 12:27:15 PM PST 24
Finished Mar 07 12:27:17 PM PST 24
Peak memory 200296 kb
Host smart-e55f3b17-02ec-4539-bd5d-24cbe5155119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596593437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
596593437
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.528943237
Short name T562
Test name
Test status
Simulation time 251908466 ps
CPU time 1.94 seconds
Started Mar 07 12:26:50 PM PST 24
Finished Mar 07 12:26:54 PM PST 24
Peak memory 208528 kb
Host smart-835ef870-133a-4359-bb85-a0d06f043319
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528943237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.528943237
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3104986181
Short name T544
Test name
Test status
Simulation time 2304301035 ps
CPU time 10.56 seconds
Started Mar 07 12:26:53 PM PST 24
Finished Mar 07 12:27:04 PM PST 24
Peak memory 200460 kb
Host smart-b992d55f-3040-4539-83c8-117b22b8b070
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104986181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
104986181
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4207398434
Short name T597
Test name
Test status
Simulation time 130188756 ps
CPU time 0.95 seconds
Started Mar 07 12:27:17 PM PST 24
Finished Mar 07 12:27:19 PM PST 24
Peak memory 200160 kb
Host smart-a608f504-0498-475d-9f2a-38b19b7a2deb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207398434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4
207398434
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2553708063
Short name T619
Test name
Test status
Simulation time 139858596 ps
CPU time 1.17 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:44 PM PST 24
Peak memory 208028 kb
Host smart-cc5f1c0b-84a8-41d4-b649-96fea6074a60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553708063 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2553708063
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3674634698
Short name T588
Test name
Test status
Simulation time 58492911 ps
CPU time 0.85 seconds
Started Mar 07 12:26:56 PM PST 24
Finished Mar 07 12:26:57 PM PST 24
Peak memory 200352 kb
Host smart-3849644f-1617-4668-ba99-a6c6d03f40de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674634698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3674634698
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.683142872
Short name T129
Test name
Test status
Simulation time 143207129 ps
CPU time 1.06 seconds
Started Mar 07 12:26:55 PM PST 24
Finished Mar 07 12:26:57 PM PST 24
Peak memory 200116 kb
Host smart-82b5f983-0a0a-4051-906c-18cf6875ba79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683142872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.683142872
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.345232437
Short name T556
Test name
Test status
Simulation time 495160585 ps
CPU time 3.66 seconds
Started Mar 07 12:26:48 PM PST 24
Finished Mar 07 12:26:52 PM PST 24
Peak memory 208528 kb
Host smart-d59b37d9-6388-45b5-b41b-2911daede3a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345232437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.345232437
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.328458099
Short name T146
Test name
Test status
Simulation time 1043213254 ps
CPU time 3.23 seconds
Started Mar 07 12:27:17 PM PST 24
Finished Mar 07 12:27:21 PM PST 24
Peak memory 200336 kb
Host smart-159608f2-a936-4596-be90-990f0d8fdb5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328458099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
328458099
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.370813120
Short name T606
Test name
Test status
Simulation time 189872939 ps
CPU time 1.21 seconds
Started Mar 07 12:27:43 PM PST 24
Finished Mar 07 12:27:44 PM PST 24
Peak memory 200116 kb
Host smart-c06b2ac6-8c0e-460f-a67b-709cf1002bed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370813120 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.370813120
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3941301198
Short name T612
Test name
Test status
Simulation time 87198144 ps
CPU time 1.01 seconds
Started Mar 07 12:27:13 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 198344 kb
Host smart-660f1f35-9523-4071-9aa4-4abe1df16f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941301198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3941301198
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2854799996
Short name T613
Test name
Test status
Simulation time 260875435 ps
CPU time 2.08 seconds
Started Mar 07 12:27:13 PM PST 24
Finished Mar 07 12:27:15 PM PST 24
Peak memory 198656 kb
Host smart-43be4119-655a-439c-a4b7-798c9e9c1e01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854799996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2854799996
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.4195663192
Short name T101
Test name
Test status
Simulation time 206164338 ps
CPU time 1.7 seconds
Started Mar 07 12:27:00 PM PST 24
Finished Mar 07 12:27:02 PM PST 24
Peak memory 208444 kb
Host smart-62e30742-1df3-4d6f-98f7-68c9153348d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195663192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.4195663192
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.788623552
Short name T96
Test name
Test status
Simulation time 439401397 ps
CPU time 1.86 seconds
Started Mar 07 12:27:08 PM PST 24
Finished Mar 07 12:27:10 PM PST 24
Peak memory 200480 kb
Host smart-09e100c6-3933-4411-912c-17637177a651
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788623552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
788623552
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1077526971
Short name T100
Test name
Test status
Simulation time 118330225 ps
CPU time 1.44 seconds
Started Mar 07 12:27:13 PM PST 24
Finished Mar 07 12:27:14 PM PST 24
Peak memory 206400 kb
Host smart-3938d0f4-3220-4259-b915-509a866ef02f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077526971 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1077526971
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.546483334
Short name T133
Test name
Test status
Simulation time 57952752 ps
CPU time 0.79 seconds
Started Mar 07 12:27:12 PM PST 24
Finished Mar 07 12:27:13 PM PST 24
Peak memory 200128 kb
Host smart-2464d566-dce5-44e8-8d86-6075e56df649
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546483334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.546483334
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3387563967
Short name T87
Test name
Test status
Simulation time 135656396 ps
CPU time 1.36 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:13 PM PST 24
Peak memory 200348 kb
Host smart-3ba8b45c-3db3-4716-873c-52db2cdd2def
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387563967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3387563967
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.764057016
Short name T104
Test name
Test status
Simulation time 111821248 ps
CPU time 1.57 seconds
Started Mar 07 12:27:42 PM PST 24
Finished Mar 07 12:27:44 PM PST 24
Peak memory 208236 kb
Host smart-410eec09-ee93-4595-9c26-a836b20909c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764057016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.764057016
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3776112382
Short name T553
Test name
Test status
Simulation time 878533635 ps
CPU time 3.01 seconds
Started Mar 07 12:26:57 PM PST 24
Finished Mar 07 12:27:00 PM PST 24
Peak memory 200460 kb
Host smart-9e38d3d7-ad84-4612-9009-89ce2879ce56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776112382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3776112382
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1435241667
Short name T92
Test name
Test status
Simulation time 184449918 ps
CPU time 1.74 seconds
Started Mar 07 12:27:06 PM PST 24
Finished Mar 07 12:27:08 PM PST 24
Peak memory 212536 kb
Host smart-4b769e9b-d494-4c41-8b42-c46a2e52d326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435241667 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1435241667
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1450160433
Short name T555
Test name
Test status
Simulation time 74456048 ps
CPU time 0.79 seconds
Started Mar 07 12:27:31 PM PST 24
Finished Mar 07 12:27:32 PM PST 24
Peak memory 200116 kb
Host smart-99286e3d-a86c-4b83-a0bd-a4aec8453f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450160433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1450160433
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3030055623
Short name T126
Test name
Test status
Simulation time 224857784 ps
CPU time 1.55 seconds
Started Mar 07 12:27:05 PM PST 24
Finished Mar 07 12:27:07 PM PST 24
Peak memory 200428 kb
Host smart-bd9c9758-5801-4b43-8829-4f8f13f73462
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030055623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3030055623
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.750111913
Short name T575
Test name
Test status
Simulation time 369112212 ps
CPU time 2.69 seconds
Started Mar 07 12:27:02 PM PST 24
Finished Mar 07 12:27:05 PM PST 24
Peak memory 199512 kb
Host smart-59523d35-f49b-43b3-99e6-4f72a4b292d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750111913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.750111913
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3636125553
Short name T596
Test name
Test status
Simulation time 495322974 ps
CPU time 1.79 seconds
Started Mar 07 12:27:41 PM PST 24
Finished Mar 07 12:27:42 PM PST 24
Peak memory 200332 kb
Host smart-e04cee07-4e6e-4294-902f-1e408334de86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636125553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3636125553
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1310021793
Short name T565
Test name
Test status
Simulation time 145574295 ps
CPU time 1.06 seconds
Started Mar 07 12:27:39 PM PST 24
Finished Mar 07 12:27:40 PM PST 24
Peak memory 208324 kb
Host smart-6de64afd-7764-4f17-b008-9ef02814210a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310021793 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1310021793
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2811619888
Short name T614
Test name
Test status
Simulation time 53611987 ps
CPU time 0.76 seconds
Started Mar 07 12:26:57 PM PST 24
Finished Mar 07 12:26:58 PM PST 24
Peak memory 200232 kb
Host smart-51fa6f09-3218-4cf4-89e3-3281b6086afd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811619888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2811619888
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1742421264
Short name T132
Test name
Test status
Simulation time 140236874 ps
CPU time 1.43 seconds
Started Mar 07 12:27:02 PM PST 24
Finished Mar 07 12:27:04 PM PST 24
Peak memory 200412 kb
Host smart-913cd479-9cd5-4c62-ba5c-235c298c3f38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742421264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1742421264
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.603807493
Short name T583
Test name
Test status
Simulation time 559120529 ps
CPU time 4.07 seconds
Started Mar 07 12:27:13 PM PST 24
Finished Mar 07 12:27:17 PM PST 24
Peak memory 210288 kb
Host smart-3a128838-dd7b-4ee1-b1e2-678c38133d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603807493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.603807493
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2260212580
Short name T611
Test name
Test status
Simulation time 487789881 ps
CPU time 1.88 seconds
Started Mar 07 12:27:29 PM PST 24
Finished Mar 07 12:27:31 PM PST 24
Peak memory 200060 kb
Host smart-9572893b-f77c-4045-ac9f-3d6d1bfb8041
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260212580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2260212580
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2423180532
Short name T609
Test name
Test status
Simulation time 208833463 ps
CPU time 1.25 seconds
Started Mar 07 12:27:17 PM PST 24
Finished Mar 07 12:27:19 PM PST 24
Peak memory 200232 kb
Host smart-2269aa00-59cb-4529-abbe-96246468ecaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423180532 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2423180532
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3296383704
Short name T545
Test name
Test status
Simulation time 87415812 ps
CPU time 0.89 seconds
Started Mar 07 12:27:01 PM PST 24
Finished Mar 07 12:27:02 PM PST 24
Peak memory 200092 kb
Host smart-ee989faa-4e54-48a3-8485-56ffb2b97f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296383704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3296383704
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2762435853
Short name T552
Test name
Test status
Simulation time 163530510 ps
CPU time 1.19 seconds
Started Mar 07 12:27:02 PM PST 24
Finished Mar 07 12:27:03 PM PST 24
Peak memory 200124 kb
Host smart-2daf6c93-3268-4767-8eaa-7e6554986e69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762435853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2762435853
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2542445172
Short name T65
Test name
Test status
Simulation time 791713286 ps
CPU time 2.94 seconds
Started Mar 07 12:27:11 PM PST 24
Finished Mar 07 12:27:15 PM PST 24
Peak memory 200352 kb
Host smart-ad522c05-3b31-438e-9668-20b5f872c5df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542445172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2542445172
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2003650143
Short name T273
Test name
Test status
Simulation time 75903642 ps
CPU time 0.78 seconds
Started Mar 07 12:31:38 PM PST 24
Finished Mar 07 12:31:39 PM PST 24
Peak memory 200228 kb
Host smart-de40087a-aa26-459d-b07d-70e2c3cfd800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003650143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2003650143
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1208161899
Short name T33
Test name
Test status
Simulation time 1899039640 ps
CPU time 7.3 seconds
Started Mar 07 12:31:42 PM PST 24
Finished Mar 07 12:31:50 PM PST 24
Peak memory 220964 kb
Host smart-06be4302-7ea1-4b5b-929c-bfc672611141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208161899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1208161899
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.270527432
Short name T235
Test name
Test status
Simulation time 244454466 ps
CPU time 1.13 seconds
Started Mar 07 12:31:37 PM PST 24
Finished Mar 07 12:31:38 PM PST 24
Peak memory 217072 kb
Host smart-4e06bfc5-4170-45ce-96d6-b059d586c25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270527432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.270527432
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.329740967
Short name T384
Test name
Test status
Simulation time 217107880 ps
CPU time 0.89 seconds
Started Mar 07 12:31:38 PM PST 24
Finished Mar 07 12:31:39 PM PST 24
Peak memory 199976 kb
Host smart-c04a474f-5a44-49f9-91a1-de8fcc66377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329740967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.329740967
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.4177115795
Short name T447
Test name
Test status
Simulation time 751738333 ps
CPU time 4.08 seconds
Started Mar 07 12:31:39 PM PST 24
Finished Mar 07 12:31:43 PM PST 24
Peak memory 200408 kb
Host smart-ae81fe16-3afb-4bb9-be35-3936cf7ca373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177115795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.4177115795
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1292649397
Short name T73
Test name
Test status
Simulation time 8382649140 ps
CPU time 13 seconds
Started Mar 07 12:31:39 PM PST 24
Finished Mar 07 12:31:52 PM PST 24
Peak memory 216616 kb
Host smart-15cb866c-4dc8-4b31-86b6-470d124833bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292649397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1292649397
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2715059760
Short name T516
Test name
Test status
Simulation time 149029210 ps
CPU time 1.07 seconds
Started Mar 07 12:31:40 PM PST 24
Finished Mar 07 12:31:41 PM PST 24
Peak memory 200276 kb
Host smart-23ca9443-5748-4dd1-891a-7216d8673a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715059760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2715059760
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3409962045
Short name T157
Test name
Test status
Simulation time 187939808 ps
CPU time 1.35 seconds
Started Mar 07 12:31:43 PM PST 24
Finished Mar 07 12:31:44 PM PST 24
Peak memory 200340 kb
Host smart-0f272a0b-3476-4953-aed5-a315f5d23642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409962045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3409962045
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.682913310
Short name T494
Test name
Test status
Simulation time 5340866714 ps
CPU time 19.96 seconds
Started Mar 07 12:31:38 PM PST 24
Finished Mar 07 12:31:59 PM PST 24
Peak memory 200468 kb
Host smart-027f28c1-0d51-4f66-b851-2d8ce73c749a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682913310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.682913310
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2128881135
Short name T376
Test name
Test status
Simulation time 153582960 ps
CPU time 1.86 seconds
Started Mar 07 12:31:42 PM PST 24
Finished Mar 07 12:31:44 PM PST 24
Peak memory 200124 kb
Host smart-c1514aa9-824c-47cf-92f0-661a9540a564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128881135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2128881135
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3967173791
Short name T521
Test name
Test status
Simulation time 131404547 ps
CPU time 0.97 seconds
Started Mar 07 12:31:37 PM PST 24
Finished Mar 07 12:31:38 PM PST 24
Peak memory 200240 kb
Host smart-047b4de1-a6b7-46b9-b474-7e0d7a2f159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967173791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3967173791
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1505209853
Short name T236
Test name
Test status
Simulation time 80615350 ps
CPU time 0.86 seconds
Started Mar 07 12:32:05 PM PST 24
Finished Mar 07 12:32:06 PM PST 24
Peak memory 200044 kb
Host smart-fcda3f5c-1e3a-4916-a6b0-c670d8ad79e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505209853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1505209853
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.676590173
Short name T405
Test name
Test status
Simulation time 1905006458 ps
CPU time 7.74 seconds
Started Mar 07 12:32:05 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 218180 kb
Host smart-d094e17c-b685-4c9e-96f7-d13f0c154841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676590173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.676590173
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3126999451
Short name T240
Test name
Test status
Simulation time 244362494 ps
CPU time 1.32 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 217072 kb
Host smart-fdf1e8e9-9ab6-4e46-9e53-2a1d190dc39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126999451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3126999451
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3911169875
Short name T448
Test name
Test status
Simulation time 185822293 ps
CPU time 0.84 seconds
Started Mar 07 12:31:43 PM PST 24
Finished Mar 07 12:31:44 PM PST 24
Peak memory 200044 kb
Host smart-be325063-63b8-414c-8ccf-db0db5991e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911169875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3911169875
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1477873781
Short name T116
Test name
Test status
Simulation time 825163405 ps
CPU time 4.12 seconds
Started Mar 07 12:31:37 PM PST 24
Finished Mar 07 12:31:41 PM PST 24
Peak memory 200448 kb
Host smart-e41f3ebc-5b11-4351-aea1-1819f7c26131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477873781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1477873781
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1904794960
Short name T173
Test name
Test status
Simulation time 109457953 ps
CPU time 1.01 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:10 PM PST 24
Peak memory 200332 kb
Host smart-cc72d84e-a511-4cbd-a5dd-d6d38ab8f1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904794960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1904794960
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1051543131
Short name T53
Test name
Test status
Simulation time 259820562 ps
CPU time 1.41 seconds
Started Mar 07 12:31:42 PM PST 24
Finished Mar 07 12:31:44 PM PST 24
Peak memory 200336 kb
Host smart-201e23bd-6d62-433c-b81a-58c91fa8620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051543131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1051543131
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2817930782
Short name T136
Test name
Test status
Simulation time 1903246028 ps
CPU time 7.63 seconds
Started Mar 07 12:32:11 PM PST 24
Finished Mar 07 12:32:19 PM PST 24
Peak memory 200428 kb
Host smart-28b25923-a4d8-4b33-be55-aef8573d0e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817930782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2817930782
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1160654085
Short name T425
Test name
Test status
Simulation time 130737706 ps
CPU time 1.71 seconds
Started Mar 07 12:31:39 PM PST 24
Finished Mar 07 12:31:40 PM PST 24
Peak memory 200076 kb
Host smart-0077dbd0-9e35-4c91-87f3-c3e2722798e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160654085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1160654085
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.880286930
Short name T395
Test name
Test status
Simulation time 175230992 ps
CPU time 1.11 seconds
Started Mar 07 12:31:38 PM PST 24
Finished Mar 07 12:31:39 PM PST 24
Peak memory 200324 kb
Host smart-215e17bf-a36e-42b8-b155-c1d407b1ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880286930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.880286930
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.464714944
Short name T242
Test name
Test status
Simulation time 80109513 ps
CPU time 0.92 seconds
Started Mar 07 12:32:11 PM PST 24
Finished Mar 07 12:32:12 PM PST 24
Peak memory 200072 kb
Host smart-f8b6c835-b516-47e3-aeff-0fdbd160263a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464714944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.464714944
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3428039568
Short name T77
Test name
Test status
Simulation time 244208749 ps
CPU time 1.26 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 217168 kb
Host smart-c40fb984-f205-4d32-a76a-6e5d1bd5710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428039568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3428039568
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2425543175
Short name T444
Test name
Test status
Simulation time 139274171 ps
CPU time 0.84 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 200100 kb
Host smart-508e797f-6145-4027-a933-674e5c40771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425543175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2425543175
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.22386013
Short name T291
Test name
Test status
Simulation time 1232414623 ps
CPU time 5.44 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:21 PM PST 24
Peak memory 200444 kb
Host smart-48bb0c63-50d8-476e-a30b-a22498d49cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22386013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.22386013
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1423163803
Short name T440
Test name
Test status
Simulation time 119234389 ps
CPU time 1.18 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:10 PM PST 24
Peak memory 200348 kb
Host smart-1c3c237b-d436-4c34-bbd4-609b0ad26c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423163803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1423163803
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.4112371267
Short name T311
Test name
Test status
Simulation time 9059935297 ps
CPU time 34.66 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:49 PM PST 24
Peak memory 200488 kb
Host smart-4e7e78d3-3511-4ef7-8526-3f550992c2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112371267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.4112371267
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1460491486
Short name T489
Test name
Test status
Simulation time 354658234 ps
CPU time 2.3 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200192 kb
Host smart-aa308f64-118e-41a1-b70f-22f6f0bdaad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460491486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1460491486
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2619987437
Short name T519
Test name
Test status
Simulation time 101369632 ps
CPU time 0.85 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 200176 kb
Host smart-d3760702-91a2-4636-b106-a7c9ec38d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619987437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2619987437
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1077068117
Short name T272
Test name
Test status
Simulation time 67400819 ps
CPU time 0.76 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:14 PM PST 24
Peak memory 200228 kb
Host smart-3af8760c-fc8c-403e-b28c-750a84a714cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077068117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1077068117
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4119843457
Short name T31
Test name
Test status
Simulation time 1896505024 ps
CPU time 7.55 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 217532 kb
Host smart-cbadd122-bdd0-4ed3-ae41-528375460a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119843457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4119843457
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.568736906
Short name T204
Test name
Test status
Simulation time 251125274 ps
CPU time 1.1 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 217128 kb
Host smart-c3e3fa55-47cc-49ac-9542-943a60119fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568736906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.568736906
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3852909521
Short name T345
Test name
Test status
Simulation time 220829109 ps
CPU time 0.93 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 200052 kb
Host smart-3039822f-1e29-48cf-9df2-23722b7c9f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852909521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3852909521
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4111834036
Short name T232
Test name
Test status
Simulation time 898459250 ps
CPU time 4.41 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:14 PM PST 24
Peak memory 200432 kb
Host smart-2c7fed80-f7d5-4069-b76d-26a9cc5cf0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111834036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4111834036
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3545912506
Short name T460
Test name
Test status
Simulation time 180784028 ps
CPU time 1.42 seconds
Started Mar 07 12:32:11 PM PST 24
Finished Mar 07 12:32:12 PM PST 24
Peak memory 200180 kb
Host smart-20acba51-ce5d-4c88-a1bc-8955c84bd229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545912506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3545912506
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2549430013
Short name T511
Test name
Test status
Simulation time 120039622 ps
CPU time 1.27 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200364 kb
Host smart-94299001-468a-4eb3-b8b3-c59916fbd9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549430013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2549430013
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2910350816
Short name T446
Test name
Test status
Simulation time 10967491152 ps
CPU time 35.67 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:45 PM PST 24
Peak memory 200504 kb
Host smart-5f6da329-4905-4e32-b828-77e2fa7e82bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910350816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2910350816
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2993337977
Short name T266
Test name
Test status
Simulation time 159207441 ps
CPU time 1.93 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:12 PM PST 24
Peak memory 200132 kb
Host smart-6cf048f8-dbb3-4eb3-b728-16eb3a7e3be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993337977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2993337977
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3420426202
Short name T360
Test name
Test status
Simulation time 247037418 ps
CPU time 1.6 seconds
Started Mar 07 12:32:11 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 200264 kb
Host smart-6fd02a68-6afd-444b-91e7-5a5bd24589ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420426202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3420426202
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.757502798
Short name T392
Test name
Test status
Simulation time 92116589 ps
CPU time 0.85 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 200216 kb
Host smart-5cdad840-6f7f-42c6-b0f8-cc568c840cc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757502798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.757502798
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3394734942
Short name T500
Test name
Test status
Simulation time 1227790582 ps
CPU time 5.82 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:19 PM PST 24
Peak memory 216592 kb
Host smart-ee4a3d8d-18a8-4a0b-886f-cc5d1ecd6299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394734942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3394734942
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3692590899
Short name T162
Test name
Test status
Simulation time 244448240 ps
CPU time 1.05 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:14 PM PST 24
Peak memory 217064 kb
Host smart-f44f2b69-531f-41f9-9773-61a21b58b387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692590899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3692590899
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3035359911
Short name T163
Test name
Test status
Simulation time 168408671 ps
CPU time 0.91 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:14 PM PST 24
Peak memory 200076 kb
Host smart-8f6d69a6-5302-427a-bed0-f84fff1971a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035359911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3035359911
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1443717330
Short name T138
Test name
Test status
Simulation time 1414132606 ps
CPU time 5.06 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:21 PM PST 24
Peak memory 200372 kb
Host smart-b327d88b-1a26-4ef1-914e-4d1e5b79b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443717330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1443717330
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2914368481
Short name T312
Test name
Test status
Simulation time 112780643 ps
CPU time 1.03 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 200216 kb
Host smart-6578927d-5f7d-4424-b2cf-74627b933214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914368481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2914368481
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1926896403
Short name T385
Test name
Test status
Simulation time 109444450 ps
CPU time 1.14 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 200292 kb
Host smart-cbde0483-ac11-4387-b4d2-cfbfbf2ac472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926896403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1926896403
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2932845542
Short name T261
Test name
Test status
Simulation time 67734641 ps
CPU time 0.76 seconds
Started Mar 07 12:32:17 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200056 kb
Host smart-172346ff-bf10-42b6-807b-cadd0af2b6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932845542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2932845542
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1054699262
Short name T348
Test name
Test status
Simulation time 2344923788 ps
CPU time 7.85 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:25 PM PST 24
Peak memory 217616 kb
Host smart-d3d4cddb-9c98-4498-80c2-be09098cf932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054699262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1054699262
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1819357486
Short name T148
Test name
Test status
Simulation time 243625915 ps
CPU time 1.2 seconds
Started Mar 07 12:32:17 PM PST 24
Finished Mar 07 12:32:19 PM PST 24
Peak memory 217084 kb
Host smart-5415959a-0932-4395-82f1-71183601b03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819357486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1819357486
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1107275882
Short name T340
Test name
Test status
Simulation time 147998563 ps
CPU time 0.83 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 199912 kb
Host smart-c45e12d1-3643-400c-a77f-1e3e71ea2d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107275882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1107275882
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3268603690
Short name T368
Test name
Test status
Simulation time 1690293013 ps
CPU time 6.22 seconds
Started Mar 07 12:32:17 PM PST 24
Finished Mar 07 12:32:24 PM PST 24
Peak memory 200364 kb
Host smart-80b30b38-8b46-4f3f-a51e-23331cece6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268603690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3268603690
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3796341317
Short name T183
Test name
Test status
Simulation time 109569363 ps
CPU time 1 seconds
Started Mar 07 12:32:17 PM PST 24
Finished Mar 07 12:32:19 PM PST 24
Peak memory 200208 kb
Host smart-2d78c3dc-f99d-48c2-bb3d-44e24b763c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796341317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3796341317
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2069641779
Short name T356
Test name
Test status
Simulation time 257201706 ps
CPU time 1.45 seconds
Started Mar 07 12:32:18 PM PST 24
Finished Mar 07 12:32:20 PM PST 24
Peak memory 200308 kb
Host smart-69cf5f5d-abba-4c0e-a6f3-596965b4e289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069641779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2069641779
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1589731132
Short name T246
Test name
Test status
Simulation time 4568111859 ps
CPU time 20.05 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 209464 kb
Host smart-44ef814d-174b-4cc2-ab76-1dbecc22cdd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589731132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1589731132
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2211362712
Short name T363
Test name
Test status
Simulation time 139483440 ps
CPU time 1.75 seconds
Started Mar 07 12:32:17 PM PST 24
Finished Mar 07 12:32:19 PM PST 24
Peak memory 200104 kb
Host smart-72d1da20-66a1-4449-a732-d3e112e72a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211362712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2211362712
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3039894093
Short name T12
Test name
Test status
Simulation time 123606229 ps
CPU time 1.18 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 200112 kb
Host smart-d5eb0524-fcc4-463d-a721-07268cfe0b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039894093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3039894093
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1253670322
Short name T417
Test name
Test status
Simulation time 63200614 ps
CPU time 0.76 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 200188 kb
Host smart-ce990bfc-6e47-44dd-bdbd-1658c6e4fe12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253670322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1253670322
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1121899385
Short name T61
Test name
Test status
Simulation time 1893668083 ps
CPU time 7.08 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:23 PM PST 24
Peak memory 217508 kb
Host smart-e2ba5371-7e01-4e87-bc64-6d7dde2bc658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121899385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1121899385
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3637511916
Short name T496
Test name
Test status
Simulation time 244622017 ps
CPU time 1.11 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 217204 kb
Host smart-016241f4-61af-4e27-bf03-5dcff0ae5a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637511916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3637511916
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1049075083
Short name T479
Test name
Test status
Simulation time 175772631 ps
CPU time 0.85 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 199976 kb
Host smart-62579ba7-8f13-4336-8043-2b068ceb1bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049075083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1049075083
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.300234923
Short name T542
Test name
Test status
Simulation time 1481995981 ps
CPU time 6.25 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 200376 kb
Host smart-eddf7a7c-bc37-4a9f-8d95-67b0d3a2d884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300234923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.300234923
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1360927517
Short name T259
Test name
Test status
Simulation time 183319618 ps
CPU time 1.19 seconds
Started Mar 07 12:33:04 PM PST 24
Finished Mar 07 12:33:06 PM PST 24
Peak memory 199420 kb
Host smart-6c8fd480-cb9e-4a7c-b3ef-b762d87ca527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360927517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1360927517
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2173793319
Short name T453
Test name
Test status
Simulation time 253789234 ps
CPU time 1.68 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200348 kb
Host smart-75349766-98ea-4029-8943-98e552f615dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173793319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2173793319
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3320539950
Short name T457
Test name
Test status
Simulation time 2211598514 ps
CPU time 9.05 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:25 PM PST 24
Peak memory 208800 kb
Host smart-534b952c-ba2d-44ec-8828-bf931936c9ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320539950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3320539950
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2836459914
Short name T341
Test name
Test status
Simulation time 117565399 ps
CPU time 1.49 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 208404 kb
Host smart-c583208f-99f2-4d47-9cf7-19ccf9f7bf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836459914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2836459914
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3787899246
Short name T315
Test name
Test status
Simulation time 143121548 ps
CPU time 1.23 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 200088 kb
Host smart-eb2aa70f-bb66-479c-92cc-1ba6dd5b28a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787899246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3787899246
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.384620810
Short name T329
Test name
Test status
Simulation time 58202023 ps
CPU time 0.75 seconds
Started Mar 07 12:32:24 PM PST 24
Finished Mar 07 12:32:25 PM PST 24
Peak memory 200324 kb
Host smart-0ddf2397-a397-43d9-bc05-868868fc68c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384620810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.384620810
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.835126201
Short name T62
Test name
Test status
Simulation time 2192884695 ps
CPU time 7.62 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 217720 kb
Host smart-c089834f-123d-43f6-ab95-4e524fa36c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835126201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.835126201
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.93286353
Short name T140
Test name
Test status
Simulation time 243582853 ps
CPU time 1.12 seconds
Started Mar 07 12:32:26 PM PST 24
Finished Mar 07 12:32:27 PM PST 24
Peak memory 217096 kb
Host smart-0cf9336a-5fc4-4bbf-afb6-039a11280c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93286353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.93286353
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2587528688
Short name T256
Test name
Test status
Simulation time 104981099 ps
CPU time 0.92 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 200024 kb
Host smart-aa42fa6a-9a1a-434d-87cb-01bfc1188b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587528688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2587528688
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2853693074
Short name T137
Test name
Test status
Simulation time 1948428068 ps
CPU time 7.24 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:23 PM PST 24
Peak memory 200528 kb
Host smart-02f2d082-7935-431e-a426-6d645a7520bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853693074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2853693074
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2675946059
Short name T25
Test name
Test status
Simulation time 155869178 ps
CPU time 1.26 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 200152 kb
Host smart-50e516e7-3f8e-4f47-a12d-2aa982e5035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675946059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2675946059
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1911994019
Short name T307
Test name
Test status
Simulation time 198024102 ps
CPU time 1.46 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 200404 kb
Host smart-77812d9d-2e0f-420f-9a34-e5458c4614b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911994019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1911994019
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2844681764
Short name T310
Test name
Test status
Simulation time 153323215 ps
CPU time 1.12 seconds
Started Mar 07 12:32:26 PM PST 24
Finished Mar 07 12:32:29 PM PST 24
Peak memory 200140 kb
Host smart-6ee6ce73-8092-4797-9aa2-0ba05f87ddea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844681764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2844681764
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2093547033
Short name T156
Test name
Test status
Simulation time 351701069 ps
CPU time 2.57 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200124 kb
Host smart-513c1ba5-fc22-4ce6-b79f-a11f29982d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093547033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2093547033
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.367994254
Short name T383
Test name
Test status
Simulation time 141611822 ps
CPU time 1.07 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200408 kb
Host smart-fa02c2b1-c222-45b1-b00b-8972f6b232ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367994254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.367994254
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3781514419
Short name T324
Test name
Test status
Simulation time 2196266390 ps
CPU time 7.75 seconds
Started Mar 07 12:32:20 PM PST 24
Finished Mar 07 12:32:28 PM PST 24
Peak memory 221716 kb
Host smart-59391c81-d472-42c7-9918-2c814d5b6ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781514419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3781514419
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2485627425
Short name T301
Test name
Test status
Simulation time 243745769 ps
CPU time 1.11 seconds
Started Mar 07 12:32:22 PM PST 24
Finished Mar 07 12:32:23 PM PST 24
Peak memory 217084 kb
Host smart-849e6d33-b2d4-4435-85cc-e2dd5ce04ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485627425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2485627425
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.616875833
Short name T377
Test name
Test status
Simulation time 202204886 ps
CPU time 0.95 seconds
Started Mar 07 12:32:19 PM PST 24
Finished Mar 07 12:32:20 PM PST 24
Peak memory 200244 kb
Host smart-e3a940e4-5e00-4881-9017-c2e36274e83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616875833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.616875833
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3870234758
Short name T179
Test name
Test status
Simulation time 1330165192 ps
CPU time 5.16 seconds
Started Mar 07 12:32:29 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 200368 kb
Host smart-b9b7da13-5ff0-40d2-9ea0-84c2a67df9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870234758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3870234758
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.955779557
Short name T149
Test name
Test status
Simulation time 105862799 ps
CPU time 1.02 seconds
Started Mar 07 12:32:21 PM PST 24
Finished Mar 07 12:32:23 PM PST 24
Peak memory 200344 kb
Host smart-44e7f7fd-0ac7-4049-9e5b-7fdf69fd7bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955779557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.955779557
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1906999241
Short name T258
Test name
Test status
Simulation time 197204468 ps
CPU time 1.33 seconds
Started Mar 07 12:32:22 PM PST 24
Finished Mar 07 12:32:24 PM PST 24
Peak memory 200452 kb
Host smart-c81cbb5e-bc36-401a-99fb-a0dd280ca1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906999241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1906999241
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3101883198
Short name T249
Test name
Test status
Simulation time 3296813936 ps
CPU time 12.21 seconds
Started Mar 07 12:32:26 PM PST 24
Finished Mar 07 12:32:38 PM PST 24
Peak memory 200624 kb
Host smart-dda0440e-99ae-4f24-a7f6-9cf7772cc528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101883198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3101883198
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2244644969
Short name T432
Test name
Test status
Simulation time 436125833 ps
CPU time 2.25 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:36 PM PST 24
Peak memory 208456 kb
Host smart-4436d09a-3f3e-4fe2-9cbe-30657f647db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244644969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2244644969
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.210815803
Short name T267
Test name
Test status
Simulation time 142621988 ps
CPU time 1.11 seconds
Started Mar 07 12:32:23 PM PST 24
Finished Mar 07 12:32:24 PM PST 24
Peak memory 200312 kb
Host smart-4f11d426-e9ba-46a4-9677-9e0135de3676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210815803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.210815803
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.507992317
Short name T186
Test name
Test status
Simulation time 77871585 ps
CPU time 0.8 seconds
Started Mar 07 12:32:24 PM PST 24
Finished Mar 07 12:32:25 PM PST 24
Peak memory 200300 kb
Host smart-ba5813f2-c28b-4028-bb80-d3ed62d7d5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507992317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.507992317
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3468180016
Short name T439
Test name
Test status
Simulation time 1219073767 ps
CPU time 5.75 seconds
Started Mar 07 12:32:20 PM PST 24
Finished Mar 07 12:32:26 PM PST 24
Peak memory 217060 kb
Host smart-8e1f41ed-4610-4fd9-8ba7-205853baebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468180016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3468180016
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.951488714
Short name T305
Test name
Test status
Simulation time 243908189 ps
CPU time 1.15 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 217196 kb
Host smart-cd2a586e-428a-4a32-b7e9-5bd7f07955d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951488714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.951488714
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2469863585
Short name T118
Test name
Test status
Simulation time 740624258 ps
CPU time 3.88 seconds
Started Mar 07 12:32:28 PM PST 24
Finished Mar 07 12:32:33 PM PST 24
Peak memory 200448 kb
Host smart-77d56365-7c4c-4c46-8c44-25440bb03ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469863585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2469863585
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.62079278
Short name T227
Test name
Test status
Simulation time 190605759 ps
CPU time 1.23 seconds
Started Mar 07 12:32:26 PM PST 24
Finished Mar 07 12:32:29 PM PST 24
Peak memory 200336 kb
Host smart-e1c53673-d1b0-4da7-b3f0-54543fc0ded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62079278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.62079278
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3317253736
Short name T480
Test name
Test status
Simulation time 227331527 ps
CPU time 1.58 seconds
Started Mar 07 12:32:23 PM PST 24
Finished Mar 07 12:32:25 PM PST 24
Peak memory 200284 kb
Host smart-1af64261-e6ec-4005-b60e-6106f8649a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317253736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3317253736
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1893669163
Short name T172
Test name
Test status
Simulation time 9940073052 ps
CPU time 40.34 seconds
Started Mar 07 12:32:27 PM PST 24
Finished Mar 07 12:33:09 PM PST 24
Peak memory 200576 kb
Host smart-7ea61e28-158f-449b-bb13-53b2fad469e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893669163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1893669163
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2229253325
Short name T396
Test name
Test status
Simulation time 376569466 ps
CPU time 2.45 seconds
Started Mar 07 12:33:13 PM PST 24
Finished Mar 07 12:33:15 PM PST 24
Peak memory 200304 kb
Host smart-cab51f15-e253-4dba-98c0-2234ba371b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229253325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2229253325
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1627245330
Short name T234
Test name
Test status
Simulation time 110447523 ps
CPU time 0.88 seconds
Started Mar 07 12:32:25 PM PST 24
Finished Mar 07 12:32:26 PM PST 24
Peak memory 200240 kb
Host smart-a7e04c7f-432a-47a2-8fb6-da47577282e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627245330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1627245330
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3296398798
Short name T166
Test name
Test status
Simulation time 77481412 ps
CPU time 0.77 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200192 kb
Host smart-5690f371-0ce5-4b40-abac-494b4dbf754e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296398798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3296398798
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.4004517029
Short name T379
Test name
Test status
Simulation time 1898176829 ps
CPU time 6.97 seconds
Started Mar 07 12:32:21 PM PST 24
Finished Mar 07 12:32:28 PM PST 24
Peak memory 221640 kb
Host smart-34ad9816-cc18-486a-b060-c6e4f1d9adcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004517029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.4004517029
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2151816734
Short name T106
Test name
Test status
Simulation time 243695255 ps
CPU time 1.02 seconds
Started Mar 07 12:32:26 PM PST 24
Finished Mar 07 12:32:28 PM PST 24
Peak memory 217052 kb
Host smart-a5866cc4-d323-4761-a89d-47108f36e1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151816734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2151816734
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3260789657
Short name T435
Test name
Test status
Simulation time 215458255 ps
CPU time 0.93 seconds
Started Mar 07 12:32:25 PM PST 24
Finished Mar 07 12:32:27 PM PST 24
Peak memory 200108 kb
Host smart-55bca226-1b25-4563-bf98-b48070bc08a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260789657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3260789657
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2838392164
Short name T528
Test name
Test status
Simulation time 1555541655 ps
CPU time 5.93 seconds
Started Mar 07 12:32:24 PM PST 24
Finished Mar 07 12:32:30 PM PST 24
Peak memory 200664 kb
Host smart-ed878e48-dfab-4e83-9ab8-199188a36ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838392164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2838392164
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2455338050
Short name T250
Test name
Test status
Simulation time 116777033 ps
CPU time 1.01 seconds
Started Mar 07 12:32:26 PM PST 24
Finished Mar 07 12:32:28 PM PST 24
Peak memory 200268 kb
Host smart-5747d196-c1d4-4936-8f6d-1f76d17f5eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455338050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2455338050
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.4215276498
Short name T289
Test name
Test status
Simulation time 110522698 ps
CPU time 1.26 seconds
Started Mar 07 12:32:22 PM PST 24
Finished Mar 07 12:32:24 PM PST 24
Peak memory 200556 kb
Host smart-6009802c-10ed-4777-ab0c-6ddf858e94f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215276498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.4215276498
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1754977529
Short name T298
Test name
Test status
Simulation time 2590635681 ps
CPU time 11.14 seconds
Started Mar 07 12:32:24 PM PST 24
Finished Mar 07 12:32:36 PM PST 24
Peak memory 209132 kb
Host smart-24b90c80-7d1c-4429-9101-b891bf1123ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754977529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1754977529
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3985709518
Short name T352
Test name
Test status
Simulation time 408992587 ps
CPU time 2.15 seconds
Started Mar 07 12:32:23 PM PST 24
Finished Mar 07 12:32:25 PM PST 24
Peak memory 200196 kb
Host smart-0ee65ef5-a8ad-45a7-bf26-b5c09f977caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985709518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3985709518
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2915770714
Short name T50
Test name
Test status
Simulation time 149624960 ps
CPU time 1.17 seconds
Started Mar 07 12:32:26 PM PST 24
Finished Mar 07 12:32:29 PM PST 24
Peak memory 200444 kb
Host smart-a712ca0b-c545-42ec-9cac-5a72d3040121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915770714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2915770714
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.488217059
Short name T51
Test name
Test status
Simulation time 71653363 ps
CPU time 0.9 seconds
Started Mar 07 12:32:21 PM PST 24
Finished Mar 07 12:32:23 PM PST 24
Peak memory 200220 kb
Host smart-bc6408db-d4da-41dc-b471-acc31b8e0874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488217059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.488217059
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1809402650
Short name T351
Test name
Test status
Simulation time 2370799133 ps
CPU time 8.29 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:41 PM PST 24
Peak memory 221764 kb
Host smart-e6d19046-fc03-4469-99e7-4e818f645349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809402650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1809402650
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2719303072
Short name T7
Test name
Test status
Simulation time 245537286 ps
CPU time 1.09 seconds
Started Mar 07 12:32:28 PM PST 24
Finished Mar 07 12:32:30 PM PST 24
Peak memory 217020 kb
Host smart-d1959030-6d47-40a4-bca6-251f6c7bfb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719303072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2719303072
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2281305042
Short name T344
Test name
Test status
Simulation time 237114218 ps
CPU time 0.93 seconds
Started Mar 07 12:32:27 PM PST 24
Finished Mar 07 12:32:28 PM PST 24
Peak memory 200116 kb
Host smart-5f880069-72dc-4148-b38a-3b3ef4a82026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281305042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2281305042
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2023241369
Short name T498
Test name
Test status
Simulation time 1484158193 ps
CPU time 5.85 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:39 PM PST 24
Peak memory 200480 kb
Host smart-2791e2d2-aa34-40b3-bb82-f1571419b85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023241369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2023241369
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3136706442
Short name T409
Test name
Test status
Simulation time 97786474 ps
CPU time 0.93 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200328 kb
Host smart-807fd524-cb44-4c63-9bcc-d863c051f255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136706442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3136706442
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1492194079
Short name T303
Test name
Test status
Simulation time 248441705 ps
CPU time 1.64 seconds
Started Mar 07 12:32:24 PM PST 24
Finished Mar 07 12:32:26 PM PST 24
Peak memory 200452 kb
Host smart-61e269c3-2905-4977-b27a-657bfdbb8304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492194079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1492194079
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2395302867
Short name T230
Test name
Test status
Simulation time 18973396032 ps
CPU time 59.08 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:33:33 PM PST 24
Peak memory 209596 kb
Host smart-5abc681f-1db7-4a19-8c8e-4972c6e7e839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395302867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2395302867
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3442006379
Short name T42
Test name
Test status
Simulation time 306285178 ps
CPU time 2.06 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:07 PM PST 24
Peak memory 208436 kb
Host smart-3c3c79bc-e6de-48ac-a7de-9041d3e13686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442006379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3442006379
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3665493276
Short name T486
Test name
Test status
Simulation time 69330171 ps
CPU time 0.76 seconds
Started Mar 07 12:32:29 PM PST 24
Finished Mar 07 12:32:30 PM PST 24
Peak memory 200176 kb
Host smart-46db98a5-6f23-4381-8e7c-f0ee4d3c6984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665493276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3665493276
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1489146840
Short name T79
Test name
Test status
Simulation time 68278993 ps
CPU time 0.79 seconds
Started Mar 07 12:32:07 PM PST 24
Finished Mar 07 12:32:08 PM PST 24
Peak memory 200176 kb
Host smart-6f90cca6-38e1-4d7f-9e71-6e6f15208dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489146840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1489146840
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3912673807
Short name T239
Test name
Test status
Simulation time 1911370785 ps
CPU time 7.25 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 217764 kb
Host smart-429da9c3-f892-4c14-badb-dde78469144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912673807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3912673807
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2744317926
Short name T194
Test name
Test status
Simulation time 245037545 ps
CPU time 1.18 seconds
Started Mar 07 12:32:07 PM PST 24
Finished Mar 07 12:32:08 PM PST 24
Peak memory 217128 kb
Host smart-7da8dce3-4dd2-4bdc-9bad-da027a5c8189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744317926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2744317926
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4108306860
Short name T277
Test name
Test status
Simulation time 88024856 ps
CPU time 0.77 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:10 PM PST 24
Peak memory 200116 kb
Host smart-dd660bac-328f-4daa-82d3-24db015ffc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108306860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4108306860
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.794758512
Short name T369
Test name
Test status
Simulation time 959584602 ps
CPU time 4.69 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 200372 kb
Host smart-a9ab907f-fe04-496e-85a1-2a07aabc0c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794758512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.794758512
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2046846271
Short name T70
Test name
Test status
Simulation time 17065706056 ps
CPU time 23.87 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:36 PM PST 24
Peak memory 216760 kb
Host smart-df6c300c-15d9-4cdd-a05c-53ed78f276cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046846271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2046846271
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3808802657
Short name T206
Test name
Test status
Simulation time 143113225 ps
CPU time 1.2 seconds
Started Mar 07 12:32:06 PM PST 24
Finished Mar 07 12:32:07 PM PST 24
Peak memory 200192 kb
Host smart-52db8b36-d516-44b1-9434-1e1d93a79129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808802657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3808802657
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2103104015
Short name T475
Test name
Test status
Simulation time 234029160 ps
CPU time 1.73 seconds
Started Mar 07 12:32:11 PM PST 24
Finished Mar 07 12:32:12 PM PST 24
Peak memory 200276 kb
Host smart-ece4d3e6-b964-477c-bf1e-8f1775264c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103104015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2103104015
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2252091395
Short name T219
Test name
Test status
Simulation time 17708136346 ps
CPU time 59.24 seconds
Started Mar 07 12:32:06 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 208644 kb
Host smart-1149dd0a-71e0-48bd-90e7-b1d0acb66eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252091395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2252091395
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3087183757
Short name T320
Test name
Test status
Simulation time 456538284 ps
CPU time 2.51 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200360 kb
Host smart-5c66a56d-7cd0-4775-8c18-d0f080a727ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087183757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3087183757
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3027273411
Short name T217
Test name
Test status
Simulation time 120989807 ps
CPU time 1.11 seconds
Started Mar 07 12:32:06 PM PST 24
Finished Mar 07 12:32:07 PM PST 24
Peak memory 200324 kb
Host smart-7bcf84c9-98db-4321-a20f-856925a0a37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027273411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3027273411
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.337069403
Short name T523
Test name
Test status
Simulation time 81531630 ps
CPU time 0.82 seconds
Started Mar 07 12:32:29 PM PST 24
Finished Mar 07 12:32:30 PM PST 24
Peak memory 200136 kb
Host smart-f06c3f51-0c23-47b5-844a-eaf6bd75a484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337069403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.337069403
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.386237261
Short name T285
Test name
Test status
Simulation time 1880459113 ps
CPU time 7.1 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:40 PM PST 24
Peak memory 216680 kb
Host smart-e519af18-5b0f-4e9c-91f2-a76794a5d279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386237261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.386237261
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3092718077
Short name T306
Test name
Test status
Simulation time 244161253 ps
CPU time 1.05 seconds
Started Mar 07 12:32:24 PM PST 24
Finished Mar 07 12:32:25 PM PST 24
Peak memory 217172 kb
Host smart-2c42ef4e-47c0-4982-81ea-819fbfd061d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092718077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3092718077
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3173433235
Short name T393
Test name
Test status
Simulation time 133743410 ps
CPU time 0.85 seconds
Started Mar 07 12:32:28 PM PST 24
Finished Mar 07 12:32:30 PM PST 24
Peak memory 200016 kb
Host smart-896682ce-0fc8-430a-8346-0fc621cc8d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173433235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3173433235
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1485927511
Short name T122
Test name
Test status
Simulation time 802528920 ps
CPU time 4.3 seconds
Started Mar 07 12:32:24 PM PST 24
Finished Mar 07 12:32:30 PM PST 24
Peak memory 200564 kb
Host smart-1aece040-9681-4fbd-8467-bb3af125924b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485927511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1485927511
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3962263021
Short name T467
Test name
Test status
Simulation time 151036172 ps
CPU time 1.12 seconds
Started Mar 07 12:32:23 PM PST 24
Finished Mar 07 12:32:24 PM PST 24
Peak memory 200372 kb
Host smart-7e3115e0-20ee-4b80-9ee3-2ce7d16fe9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962263021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3962263021
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2635286981
Short name T502
Test name
Test status
Simulation time 245316723 ps
CPU time 1.42 seconds
Started Mar 07 12:32:32 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200272 kb
Host smart-f17b9541-f391-4367-9238-e7582c7be2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635286981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2635286981
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2455622814
Short name T400
Test name
Test status
Simulation time 4288402038 ps
CPU time 18.08 seconds
Started Mar 07 12:32:28 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 200460 kb
Host smart-44bed2bd-ecb8-4cec-8cec-044116647bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455622814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2455622814
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1867700154
Short name T211
Test name
Test status
Simulation time 356457697 ps
CPU time 2.04 seconds
Started Mar 07 12:32:29 PM PST 24
Finished Mar 07 12:32:32 PM PST 24
Peak memory 208308 kb
Host smart-7dc36665-1000-41f2-8aef-dbd0aa7d36d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867700154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1867700154
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.4116626434
Short name T321
Test name
Test status
Simulation time 61075165 ps
CPU time 0.76 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200332 kb
Host smart-fda65a4d-b3e5-4223-bac3-d0c15d9a6e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116626434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.4116626434
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1220786130
Short name T391
Test name
Test status
Simulation time 64374205 ps
CPU time 0.76 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:42 PM PST 24
Peak memory 200084 kb
Host smart-9560917a-f738-4aa1-ab00-8cafe7116196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220786130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1220786130
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1353466473
Short name T484
Test name
Test status
Simulation time 1901222134 ps
CPU time 8.06 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:42 PM PST 24
Peak memory 216616 kb
Host smart-799ed8c7-470f-48c5-b0cd-abe9b6e48939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353466473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1353466473
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3170318412
Short name T327
Test name
Test status
Simulation time 244363236 ps
CPU time 1.07 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:43 PM PST 24
Peak memory 217144 kb
Host smart-e3da33f9-0c79-4f1e-ab3a-d766d53121f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170318412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3170318412
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1937782305
Short name T342
Test name
Test status
Simulation time 198580594 ps
CPU time 1.02 seconds
Started Mar 07 12:32:24 PM PST 24
Finished Mar 07 12:32:27 PM PST 24
Peak memory 200112 kb
Host smart-9331b0ae-0a24-43b7-8be5-9580dcf34a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937782305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1937782305
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3506946340
Short name T110
Test name
Test status
Simulation time 635823075 ps
CPU time 3.81 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:45 PM PST 24
Peak memory 200340 kb
Host smart-8ce2647b-eb8b-4f4f-af1b-7b46cc0acfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506946340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3506946340
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3582963376
Short name T531
Test name
Test status
Simulation time 176940888 ps
CPU time 1.26 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 200356 kb
Host smart-57202c46-0877-4362-b286-7d2933136f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582963376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3582963376
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3449978186
Short name T74
Test name
Test status
Simulation time 245031161 ps
CPU time 1.51 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:43 PM PST 24
Peak memory 200308 kb
Host smart-084019c8-7248-483f-8da9-d620c0404b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449978186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3449978186
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.71578027
Short name T283
Test name
Test status
Simulation time 5725581927 ps
CPU time 23.4 seconds
Started Mar 07 12:32:26 PM PST 24
Finished Mar 07 12:32:51 PM PST 24
Peak memory 200636 kb
Host smart-7ad17351-c77b-4894-b9ad-13a8f23c5259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71578027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.71578027
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1381218271
Short name T151
Test name
Test status
Simulation time 306741331 ps
CPU time 1.98 seconds
Started Mar 07 12:32:29 PM PST 24
Finished Mar 07 12:32:31 PM PST 24
Peak memory 208380 kb
Host smart-3e782adc-fda4-41ed-b57a-9650a15ff7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381218271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1381218271
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.210641759
Short name T468
Test name
Test status
Simulation time 275358359 ps
CPU time 1.61 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 200484 kb
Host smart-7263e27e-a930-4344-b2f0-e91e7878c402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210641759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.210641759
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1603364603
Short name T58
Test name
Test status
Simulation time 61195681 ps
CPU time 0.69 seconds
Started Mar 07 12:32:38 PM PST 24
Finished Mar 07 12:32:39 PM PST 24
Peak memory 199952 kb
Host smart-31d1ccc9-f0fc-4726-8433-bc9bd2c12ff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603364603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1603364603
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1967067567
Short name T34
Test name
Test status
Simulation time 1227412577 ps
CPU time 5.58 seconds
Started Mar 07 12:32:29 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 217044 kb
Host smart-42f1ed1a-2dd4-4c1d-8191-f31b087f61d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967067567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1967067567
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3205833791
Short name T367
Test name
Test status
Simulation time 243571958 ps
CPU time 1.08 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:42 PM PST 24
Peak memory 217096 kb
Host smart-cd39c327-ecd7-4f82-8eb1-8fc3014e2c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205833791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3205833791
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3120958462
Short name T275
Test name
Test status
Simulation time 135238323 ps
CPU time 0.78 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:42 PM PST 24
Peak memory 200028 kb
Host smart-28eca1c8-beaa-41f6-bb7d-57ddf0d1d66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120958462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3120958462
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1595258713
Short name T428
Test name
Test status
Simulation time 785944002 ps
CPU time 3.65 seconds
Started Mar 07 12:32:27 PM PST 24
Finished Mar 07 12:32:32 PM PST 24
Peak memory 200476 kb
Host smart-6bf1caf9-c388-437f-a25a-0392c68c4934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595258713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1595258713
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.842371715
Short name T141
Test name
Test status
Simulation time 179208001 ps
CPU time 1.18 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:42 PM PST 24
Peak memory 200236 kb
Host smart-7208ecf0-e708-40cd-bc0f-3a95a4ff6921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842371715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.842371715
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.774705384
Short name T304
Test name
Test status
Simulation time 202232690 ps
CPU time 1.39 seconds
Started Mar 07 12:32:30 PM PST 24
Finished Mar 07 12:32:31 PM PST 24
Peak memory 200444 kb
Host smart-491a88d8-679e-4b79-bf8f-a00c0be2f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774705384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.774705384
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2359119772
Short name T135
Test name
Test status
Simulation time 8271727333 ps
CPU time 28.83 seconds
Started Mar 07 12:32:43 PM PST 24
Finished Mar 07 12:33:12 PM PST 24
Peak memory 208764 kb
Host smart-b92b450e-a756-4cc8-8e76-2ca1c624d90b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359119772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2359119772
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3371226759
Short name T142
Test name
Test status
Simulation time 125448247 ps
CPU time 1.47 seconds
Started Mar 07 12:32:29 PM PST 24
Finished Mar 07 12:32:30 PM PST 24
Peak memory 200092 kb
Host smart-c9ca9338-0ed4-48a4-af43-3301d9f9c9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371226759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3371226759
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2398268735
Short name T518
Test name
Test status
Simulation time 63357114 ps
CPU time 0.76 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:42 PM PST 24
Peak memory 200228 kb
Host smart-406253c6-ac93-4605-802c-a8a4288c7dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398268735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2398268735
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2929229580
Short name T509
Test name
Test status
Simulation time 62580672 ps
CPU time 0.73 seconds
Started Mar 07 12:32:30 PM PST 24
Finished Mar 07 12:32:30 PM PST 24
Peak memory 200100 kb
Host smart-1b82358b-74f9-4d94-bc1b-baf8fc3583c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929229580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2929229580
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.733711913
Short name T325
Test name
Test status
Simulation time 2363719893 ps
CPU time 7.93 seconds
Started Mar 07 12:32:38 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 221620 kb
Host smart-69196b60-e296-4f55-a0bd-a179d8079f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733711913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.733711913
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.848724405
Short name T160
Test name
Test status
Simulation time 243160670 ps
CPU time 1.03 seconds
Started Mar 07 12:32:32 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 217048 kb
Host smart-7b5349ee-9fd3-41a8-bf77-dbdfbd14411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848724405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.848724405
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1899934255
Short name T255
Test name
Test status
Simulation time 175664944 ps
CPU time 0.83 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200124 kb
Host smart-83481dbd-1de4-4ced-a098-f3e76fd873f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899934255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1899934255
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3075953025
Short name T539
Test name
Test status
Simulation time 1442375201 ps
CPU time 5.34 seconds
Started Mar 07 12:32:43 PM PST 24
Finished Mar 07 12:32:49 PM PST 24
Peak memory 200540 kb
Host smart-081ca935-3ee2-4048-9d4b-4bccfcd35b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075953025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3075953025
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1484333447
Short name T49
Test name
Test status
Simulation time 185283470 ps
CPU time 1.27 seconds
Started Mar 07 12:32:35 PM PST 24
Finished Mar 07 12:32:36 PM PST 24
Peak memory 200360 kb
Host smart-f0e5cadb-923b-4e17-8938-c600f0ec650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484333447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1484333447
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3684572776
Short name T375
Test name
Test status
Simulation time 196743677 ps
CPU time 1.46 seconds
Started Mar 07 12:32:30 PM PST 24
Finished Mar 07 12:32:32 PM PST 24
Peak memory 200280 kb
Host smart-4887ddbf-6d12-469f-b504-7bdb69e31113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684572776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3684572776
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3616336761
Short name T191
Test name
Test status
Simulation time 492491828 ps
CPU time 2.51 seconds
Started Mar 07 12:32:30 PM PST 24
Finished Mar 07 12:32:33 PM PST 24
Peak memory 200460 kb
Host smart-92fbf4bd-9f5b-4a31-920a-9c34200c6508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616336761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3616336761
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3036720251
Short name T322
Test name
Test status
Simulation time 122991358 ps
CPU time 1.55 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:43 PM PST 24
Peak memory 208404 kb
Host smart-84ca8dd1-af48-4a8a-89b2-92b53e1f062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036720251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3036720251
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.452099415
Short name T415
Test name
Test status
Simulation time 110203017 ps
CPU time 1.03 seconds
Started Mar 07 12:32:34 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 200360 kb
Host smart-29e4ca24-29bb-4633-bb78-edc9f62b08b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452099415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.452099415
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.975407016
Short name T408
Test name
Test status
Simulation time 82943124 ps
CPU time 0.82 seconds
Started Mar 07 12:32:51 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 200104 kb
Host smart-7805c53f-26c7-4f36-8965-d6bb95e664ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975407016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.975407016
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1604229796
Short name T28
Test name
Test status
Simulation time 2177963604 ps
CPU time 7.69 seconds
Started Mar 07 12:32:36 PM PST 24
Finished Mar 07 12:32:44 PM PST 24
Peak memory 217076 kb
Host smart-56f4fe13-2f48-4e2c-88d2-15bbe92424f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604229796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1604229796
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.395874931
Short name T150
Test name
Test status
Simulation time 245325451 ps
CPU time 1.12 seconds
Started Mar 07 12:32:32 PM PST 24
Finished Mar 07 12:32:33 PM PST 24
Peak memory 217216 kb
Host smart-601ec8fe-af65-4a9f-8adc-5beca7335e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395874931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.395874931
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1211946794
Short name T8
Test name
Test status
Simulation time 178445851 ps
CPU time 0.92 seconds
Started Mar 07 12:32:36 PM PST 24
Finished Mar 07 12:32:37 PM PST 24
Peak memory 200048 kb
Host smart-c3d1ced4-e34b-4c08-a85a-8a5a44dad299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211946794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1211946794
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.4216160377
Short name T380
Test name
Test status
Simulation time 1410874504 ps
CPU time 5.36 seconds
Started Mar 07 12:32:36 PM PST 24
Finished Mar 07 12:32:41 PM PST 24
Peak memory 200400 kb
Host smart-4bcbc5eb-039f-4f33-8547-e9c456283ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216160377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.4216160377
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1928420108
Short name T105
Test name
Test status
Simulation time 181831371 ps
CPU time 1.1 seconds
Started Mar 07 12:32:32 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200232 kb
Host smart-1a1482f9-850d-4cd5-beb0-43f401fb3934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928420108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1928420108
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3368608097
Short name T538
Test name
Test status
Simulation time 114230437 ps
CPU time 1.11 seconds
Started Mar 07 12:32:31 PM PST 24
Finished Mar 07 12:32:32 PM PST 24
Peak memory 200348 kb
Host smart-ce429c93-2d50-42d8-9ddc-496e823d4143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368608097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3368608097
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1126756171
Short name T182
Test name
Test status
Simulation time 2347379401 ps
CPU time 11.27 seconds
Started Mar 07 12:33:00 PM PST 24
Finished Mar 07 12:33:12 PM PST 24
Peak memory 200576 kb
Host smart-b160c4f4-593c-4070-9351-072154064b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126756171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1126756171
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.10238960
Short name T347
Test name
Test status
Simulation time 132867718 ps
CPU time 1.71 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 208436 kb
Host smart-ab450a2c-3f2c-41b2-ae00-9805616d5027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10238960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.10238960
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.871452237
Short name T268
Test name
Test status
Simulation time 163242356 ps
CPU time 1.4 seconds
Started Mar 07 12:32:22 PM PST 24
Finished Mar 07 12:32:23 PM PST 24
Peak memory 200404 kb
Host smart-b4ede3e1-7ad2-43cb-957d-324ecb8fa4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871452237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.871452237
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1785792877
Short name T231
Test name
Test status
Simulation time 64912517 ps
CPU time 0.77 seconds
Started Mar 07 12:32:34 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 200272 kb
Host smart-e55eaca6-46e1-4481-a303-5426a8fdba9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785792877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1785792877
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1238073160
Short name T57
Test name
Test status
Simulation time 1888209420 ps
CPU time 6.94 seconds
Started Mar 07 12:32:45 PM PST 24
Finished Mar 07 12:32:53 PM PST 24
Peak memory 219964 kb
Host smart-4b7c9038-0e53-4307-b135-52e3ed456d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238073160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1238073160
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.360023764
Short name T168
Test name
Test status
Simulation time 244242934 ps
CPU time 1.15 seconds
Started Mar 07 12:32:51 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 217044 kb
Host smart-28b25507-b5a1-44e8-9f51-db69a65cb290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360023764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.360023764
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.377537914
Short name T401
Test name
Test status
Simulation time 172147952 ps
CPU time 0.82 seconds
Started Mar 07 12:32:50 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 200160 kb
Host smart-0cc512ea-90d0-4447-b507-7f4f90287c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377537914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.377537914
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1523465010
Short name T153
Test name
Test status
Simulation time 1361743002 ps
CPU time 5.33 seconds
Started Mar 07 12:32:38 PM PST 24
Finished Mar 07 12:32:44 PM PST 24
Peak memory 200504 kb
Host smart-75b9782d-9dec-4c6f-be02-a4a29ae05424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523465010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1523465010
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1290887857
Short name T421
Test name
Test status
Simulation time 143409012 ps
CPU time 1.09 seconds
Started Mar 07 12:32:31 PM PST 24
Finished Mar 07 12:32:33 PM PST 24
Peak memory 200332 kb
Host smart-377d3913-4f8f-458a-9cee-ac8a59e6621f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290887857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1290887857
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2750487993
Short name T177
Test name
Test status
Simulation time 230035613 ps
CPU time 1.53 seconds
Started Mar 07 12:32:32 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200492 kb
Host smart-b6ccd779-b453-4d05-a28d-b946614f53a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750487993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2750487993
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.4109334959
Short name T465
Test name
Test status
Simulation time 3605808747 ps
CPU time 12.24 seconds
Started Mar 07 12:32:54 PM PST 24
Finished Mar 07 12:33:07 PM PST 24
Peak memory 200576 kb
Host smart-3f3a4018-c53b-46db-a854-b35ee5c8f464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109334959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.4109334959
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1085515547
Short name T454
Test name
Test status
Simulation time 147947710 ps
CPU time 1.99 seconds
Started Mar 07 12:32:34 PM PST 24
Finished Mar 07 12:32:37 PM PST 24
Peak memory 200268 kb
Host smart-7b6cff9f-03ee-43cb-b7c7-1597eaf7febe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085515547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1085515547
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1472957996
Short name T510
Test name
Test status
Simulation time 116273208 ps
CPU time 1.16 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 200328 kb
Host smart-48264255-1fb4-40fd-93ce-cce980922428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472957996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1472957996
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2845072699
Short name T237
Test name
Test status
Simulation time 74406645 ps
CPU time 0.78 seconds
Started Mar 07 12:32:37 PM PST 24
Finished Mar 07 12:32:39 PM PST 24
Peak memory 200188 kb
Host smart-9a82cc27-4304-4a9a-9ed3-6f5165ac6d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845072699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2845072699
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2013460151
Short name T32
Test name
Test status
Simulation time 1909670359 ps
CPU time 7.72 seconds
Started Mar 07 12:32:35 PM PST 24
Finished Mar 07 12:32:43 PM PST 24
Peak memory 220664 kb
Host smart-7b4c8958-57a8-442b-974c-e641c809e1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013460151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2013460151
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2993683275
Short name T386
Test name
Test status
Simulation time 243955237 ps
CPU time 1.03 seconds
Started Mar 07 12:32:47 PM PST 24
Finished Mar 07 12:32:48 PM PST 24
Peak memory 216984 kb
Host smart-20f16263-fe68-4eac-856f-6cbea4901441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993683275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2993683275
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1670725266
Short name T495
Test name
Test status
Simulation time 167945162 ps
CPU time 0.9 seconds
Started Mar 07 12:32:50 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 199976 kb
Host smart-088714a4-9541-4a7d-9f67-9a2ee9a1ff48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670725266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1670725266
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1832928604
Short name T247
Test name
Test status
Simulation time 963629643 ps
CPU time 4.46 seconds
Started Mar 07 12:32:31 PM PST 24
Finished Mar 07 12:32:36 PM PST 24
Peak memory 200528 kb
Host smart-aa63abef-9f2f-41d1-a939-0f8e0e611834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832928604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1832928604
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2526309093
Short name T223
Test name
Test status
Simulation time 147033047 ps
CPU time 1.09 seconds
Started Mar 07 12:32:48 PM PST 24
Finished Mar 07 12:32:49 PM PST 24
Peak memory 200360 kb
Host smart-2c349dc1-172e-4247-a68f-21e7193514bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526309093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2526309093
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.388997276
Short name T188
Test name
Test status
Simulation time 108453093 ps
CPU time 1.26 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200336 kb
Host smart-b98df406-4c1e-420d-b5af-88da56d76c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388997276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.388997276
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3971887641
Short name T525
Test name
Test status
Simulation time 2380432761 ps
CPU time 8.82 seconds
Started Mar 07 12:32:53 PM PST 24
Finished Mar 07 12:33:02 PM PST 24
Peak memory 200156 kb
Host smart-2f5eb8f8-ade8-4773-b083-97fbff576886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971887641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3971887641
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.4226249484
Short name T143
Test name
Test status
Simulation time 432077108 ps
CPU time 2.48 seconds
Started Mar 07 12:32:51 PM PST 24
Finished Mar 07 12:32:53 PM PST 24
Peak memory 208372 kb
Host smart-33894ed0-6fa5-411b-a19c-2ed6c7fc5f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226249484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4226249484
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1874921804
Short name T437
Test name
Test status
Simulation time 73574759 ps
CPU time 0.79 seconds
Started Mar 07 12:32:50 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 200212 kb
Host smart-656382dd-f053-4c48-8ca3-ada153dd4b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874921804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1874921804
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1093826963
Short name T76
Test name
Test status
Simulation time 72450023 ps
CPU time 0.78 seconds
Started Mar 07 12:33:51 PM PST 24
Finished Mar 07 12:33:52 PM PST 24
Peak memory 200096 kb
Host smart-ca4bb182-58b4-44b5-8fb5-42d73a2bf6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093826963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1093826963
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1685632938
Short name T43
Test name
Test status
Simulation time 1222162265 ps
CPU time 6.21 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:40 PM PST 24
Peak memory 221708 kb
Host smart-50a4142a-476e-4fe4-bf72-0e849be25269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685632938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1685632938
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3231939644
Short name T407
Test name
Test status
Simulation time 243822058 ps
CPU time 1.04 seconds
Started Mar 07 12:32:50 PM PST 24
Finished Mar 07 12:32:51 PM PST 24
Peak memory 217188 kb
Host smart-33261125-6132-4e58-a825-c22ad1e2ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231939644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3231939644
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2709644775
Short name T365
Test name
Test status
Simulation time 155198848 ps
CPU time 0.86 seconds
Started Mar 07 12:32:40 PM PST 24
Finished Mar 07 12:32:42 PM PST 24
Peak memory 200116 kb
Host smart-ae56d483-e2ff-4b42-97b0-6aec93f9a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709644775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2709644775
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.604304171
Short name T424
Test name
Test status
Simulation time 1379500006 ps
CPU time 5.3 seconds
Started Mar 07 12:32:51 PM PST 24
Finished Mar 07 12:32:56 PM PST 24
Peak memory 200408 kb
Host smart-58619ac0-52f8-4203-8405-14c248ecfd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604304171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.604304171
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3973318109
Short name T430
Test name
Test status
Simulation time 147913144 ps
CPU time 1.22 seconds
Started Mar 07 12:32:31 PM PST 24
Finished Mar 07 12:32:33 PM PST 24
Peak memory 200332 kb
Host smart-3b0464de-bf72-4735-83e3-133bf6b91aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973318109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3973318109
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2741350958
Short name T174
Test name
Test status
Simulation time 258657854 ps
CPU time 1.58 seconds
Started Mar 07 12:32:32 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200544 kb
Host smart-f1b087da-40b0-4362-9f44-7469c77ab625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741350958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2741350958
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.4213389488
Short name T55
Test name
Test status
Simulation time 2146672591 ps
CPU time 9.08 seconds
Started Mar 07 12:32:51 PM PST 24
Finished Mar 07 12:33:00 PM PST 24
Peak memory 200364 kb
Host smart-d5381d9b-5a5f-421e-b224-6ba115207ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213389488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.4213389488
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3224330259
Short name T286
Test name
Test status
Simulation time 324774455 ps
CPU time 2.06 seconds
Started Mar 07 12:32:45 PM PST 24
Finished Mar 07 12:32:48 PM PST 24
Peak memory 198268 kb
Host smart-b71ac08f-42f6-4584-9dbc-3cc6dbee1ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224330259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3224330259
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3836661268
Short name T38
Test name
Test status
Simulation time 69398138 ps
CPU time 0.88 seconds
Started Mar 07 12:32:31 PM PST 24
Finished Mar 07 12:32:33 PM PST 24
Peak memory 200344 kb
Host smart-2e9001d4-4fd8-4434-ab74-ad47b2b1b40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836661268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3836661268
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2532180012
Short name T387
Test name
Test status
Simulation time 67485186 ps
CPU time 0.75 seconds
Started Mar 07 12:32:45 PM PST 24
Finished Mar 07 12:32:46 PM PST 24
Peak memory 198668 kb
Host smart-991e03cf-989c-4182-bbf4-c7990c3630f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532180012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2532180012
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4278996887
Short name T451
Test name
Test status
Simulation time 1888330120 ps
CPU time 7.74 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 216964 kb
Host smart-b2b04264-d046-4b09-bd68-7277ec1ba76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278996887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4278996887
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2837776996
Short name T193
Test name
Test status
Simulation time 244084097 ps
CPU time 1.07 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 217020 kb
Host smart-8e90b4ac-6488-48d0-8691-63a43b59d8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837776996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2837776996
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2150513776
Short name T492
Test name
Test status
Simulation time 158622616 ps
CPU time 0.85 seconds
Started Mar 07 12:32:53 PM PST 24
Finished Mar 07 12:32:54 PM PST 24
Peak memory 199764 kb
Host smart-5cd55ab9-d655-4683-b9a0-0f5eb5be2d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150513776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2150513776
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.815896341
Short name T292
Test name
Test status
Simulation time 2103673800 ps
CPU time 7.19 seconds
Started Mar 07 12:32:31 PM PST 24
Finished Mar 07 12:32:39 PM PST 24
Peak memory 200540 kb
Host smart-cd527c35-b7ff-457d-bf0e-eb6774f34eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815896341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.815896341
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.4294151635
Short name T195
Test name
Test status
Simulation time 106065490 ps
CPU time 0.98 seconds
Started Mar 07 12:33:50 PM PST 24
Finished Mar 07 12:33:52 PM PST 24
Peak memory 200092 kb
Host smart-068d95f8-b9c7-4f71-b176-d7cff3005f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294151635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.4294151635
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1182968327
Short name T253
Test name
Test status
Simulation time 125660316 ps
CPU time 1.18 seconds
Started Mar 07 12:32:51 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 200344 kb
Host smart-372636c1-d5a0-46ea-a153-158c54396859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182968327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1182968327
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.151205140
Short name T112
Test name
Test status
Simulation time 972253138 ps
CPU time 4.8 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:51 PM PST 24
Peak memory 200356 kb
Host smart-caaf260a-ca3a-4686-8dd7-db3324dc8773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151205140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.151205140
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1355461881
Short name T145
Test name
Test status
Simulation time 409941732 ps
CPU time 2.37 seconds
Started Mar 07 12:32:32 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 200176 kb
Host smart-2f8c2800-55bd-4d2b-98c5-bf0a40556bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355461881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1355461881
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.871193144
Short name T13
Test name
Test status
Simulation time 125150759 ps
CPU time 1.03 seconds
Started Mar 07 12:32:51 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 200212 kb
Host smart-a289c8fb-ca95-4056-8f06-03fa4285aba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871193144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.871193144
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3398322970
Short name T214
Test name
Test status
Simulation time 60357820 ps
CPU time 0.72 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 200188 kb
Host smart-bfb4d3bd-c6f0-4d1c-8fa8-fef7048a8d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398322970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3398322970
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.317859684
Short name T241
Test name
Test status
Simulation time 2333514265 ps
CPU time 7.89 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 217148 kb
Host smart-b288df2f-8773-4603-b449-19661b26ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317859684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.317859684
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3228279926
Short name T165
Test name
Test status
Simulation time 245452056 ps
CPU time 1.05 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 216916 kb
Host smart-d0961b5e-6b72-4cdc-bc2d-86d2c1855edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228279926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3228279926
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1730666413
Short name T512
Test name
Test status
Simulation time 156572187 ps
CPU time 0.85 seconds
Started Mar 07 12:33:00 PM PST 24
Finished Mar 07 12:33:01 PM PST 24
Peak memory 200120 kb
Host smart-abf03378-c061-477a-8bdb-39d5f9df26ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730666413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1730666413
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2743891300
Short name T215
Test name
Test status
Simulation time 877458008 ps
CPU time 4.07 seconds
Started Mar 07 12:32:58 PM PST 24
Finished Mar 07 12:33:03 PM PST 24
Peak memory 200468 kb
Host smart-9328d095-32db-45b7-890b-5b8485fda111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743891300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2743891300
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3685738466
Short name T358
Test name
Test status
Simulation time 142411227 ps
CPU time 1.08 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 200356 kb
Host smart-78c5865a-63a4-4dd1-a8ab-80cc6ca38f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685738466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3685738466
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2897675837
Short name T420
Test name
Test status
Simulation time 120662766 ps
CPU time 1.22 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 200400 kb
Host smart-f04a018f-54a4-4abc-a629-23ef2bb0bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897675837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2897675837
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2193872840
Short name T471
Test name
Test status
Simulation time 5708571965 ps
CPU time 22.62 seconds
Started Mar 07 12:32:37 PM PST 24
Finished Mar 07 12:33:00 PM PST 24
Peak memory 200540 kb
Host smart-c91d4b87-3f2c-47f5-9c3c-ca858b6d13bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193872840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2193872840
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.4242324624
Short name T390
Test name
Test status
Simulation time 125024426 ps
CPU time 1.61 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 200252 kb
Host smart-7dec7db4-b13c-4e81-afba-de921cd32d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242324624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.4242324624
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2920466378
Short name T158
Test name
Test status
Simulation time 139611141 ps
CPU time 1.19 seconds
Started Mar 07 12:32:45 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 199068 kb
Host smart-92610cc9-35d3-47bb-90f4-4db959fdbaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920466378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2920466378
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3888756195
Short name T314
Test name
Test status
Simulation time 62826050 ps
CPU time 0.78 seconds
Started Mar 07 12:32:11 PM PST 24
Finished Mar 07 12:32:12 PM PST 24
Peak memory 200204 kb
Host smart-32156cae-9ce4-48c8-b0f4-6a0ec4da6fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888756195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3888756195
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1851303965
Short name T245
Test name
Test status
Simulation time 1223129649 ps
CPU time 5.62 seconds
Started Mar 07 12:32:07 PM PST 24
Finished Mar 07 12:32:12 PM PST 24
Peak memory 217136 kb
Host smart-f1eb96ec-0fdf-4985-bf0f-98ca50d69449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851303965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1851303965
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2127409057
Short name T487
Test name
Test status
Simulation time 244702284 ps
CPU time 1.05 seconds
Started Mar 07 12:32:07 PM PST 24
Finished Mar 07 12:32:08 PM PST 24
Peak memory 217116 kb
Host smart-c08b7c37-877d-4229-9f5b-5a73617ec43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127409057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2127409057
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.795572695
Short name T279
Test name
Test status
Simulation time 175489674 ps
CPU time 0.92 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200120 kb
Host smart-6554d26b-73b5-4c62-aecd-6499217b369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795572695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.795572695
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1390767315
Short name T459
Test name
Test status
Simulation time 2037220617 ps
CPU time 8.02 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 200572 kb
Host smart-9a08f2da-bf53-401a-9848-76d3af66122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390767315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1390767315
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3768722866
Short name T71
Test name
Test status
Simulation time 8298631095 ps
CPU time 15.58 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:24 PM PST 24
Peak memory 216508 kb
Host smart-fd80c5cb-9274-4b95-a54e-1fff7a8cd5a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768722866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3768722866
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2067049232
Short name T4
Test name
Test status
Simulation time 103571783 ps
CPU time 1.05 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:09 PM PST 24
Peak memory 200448 kb
Host smart-b3d12b15-a8ab-44dc-bc65-7f3530e8969c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067049232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2067049232
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.575188805
Short name T503
Test name
Test status
Simulation time 254904493 ps
CPU time 1.57 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:10 PM PST 24
Peak memory 200312 kb
Host smart-7cdfb523-35c0-4f1f-b779-09daaaeac6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575188805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.575188805
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3880406283
Short name T121
Test name
Test status
Simulation time 2714008404 ps
CPU time 13.17 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:21 PM PST 24
Peak memory 200468 kb
Host smart-3332c461-1709-4b62-95f9-498882becf1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880406283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3880406283
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3163309416
Short name T337
Test name
Test status
Simulation time 299776876 ps
CPU time 2.03 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:10 PM PST 24
Peak memory 208440 kb
Host smart-49ba1514-ce00-4840-9137-3daddad780c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163309416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3163309416
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3526317663
Short name T355
Test name
Test status
Simulation time 143281209 ps
CPU time 1.05 seconds
Started Mar 07 12:32:11 PM PST 24
Finished Mar 07 12:32:12 PM PST 24
Peak memory 200336 kb
Host smart-9eff476e-3c1e-40f8-97c6-d899870f5b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526317663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3526317663
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2250405788
Short name T205
Test name
Test status
Simulation time 116570376 ps
CPU time 0.82 seconds
Started Mar 07 12:32:37 PM PST 24
Finished Mar 07 12:32:38 PM PST 24
Peak memory 200176 kb
Host smart-20ef44a7-6b5b-4a4d-8acb-97fbfe862044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250405788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2250405788
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2476578624
Short name T5
Test name
Test status
Simulation time 1895054385 ps
CPU time 6.59 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:40 PM PST 24
Peak memory 217076 kb
Host smart-ca54cf85-ac53-4fe9-aa1b-002c0dcd32e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476578624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2476578624
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.375567739
Short name T463
Test name
Test status
Simulation time 245205529 ps
CPU time 1.14 seconds
Started Mar 07 12:32:45 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 216528 kb
Host smart-b604d78d-be60-4efe-b2e0-8ce2f0cf01bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375567739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.375567739
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.4136360021
Short name T16
Test name
Test status
Simulation time 143609182 ps
CPU time 0.87 seconds
Started Mar 07 12:32:33 PM PST 24
Finished Mar 07 12:32:35 PM PST 24
Peak memory 200116 kb
Host smart-58b329a8-0710-491e-9e28-ffe07a04ff02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136360021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.4136360021
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2407487422
Short name T316
Test name
Test status
Simulation time 701741265 ps
CPU time 4.06 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:07 PM PST 24
Peak memory 200468 kb
Host smart-4c81d08d-5dd5-4207-9f22-39cf5edcba7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407487422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2407487422
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1956008186
Short name T478
Test name
Test status
Simulation time 161857761 ps
CPU time 1.2 seconds
Started Mar 07 12:33:05 PM PST 24
Finished Mar 07 12:33:06 PM PST 24
Peak memory 200328 kb
Host smart-ff88c906-21df-4a03-bfc7-3e2dd7a794c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956008186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1956008186
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1878517950
Short name T221
Test name
Test status
Simulation time 248817467 ps
CPU time 1.49 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 200032 kb
Host smart-97065409-71a0-4586-8304-76a0374d89ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878517950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1878517950
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1605228590
Short name T389
Test name
Test status
Simulation time 5816292288 ps
CPU time 25.28 seconds
Started Mar 07 12:32:32 PM PST 24
Finished Mar 07 12:32:58 PM PST 24
Peak memory 208740 kb
Host smart-5862bc1a-5657-4035-aef3-695fed834729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605228590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1605228590
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.826131775
Short name T155
Test name
Test status
Simulation time 382110420 ps
CPU time 2.42 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 200220 kb
Host smart-61d7aad8-c380-4c89-895c-45dd237f92a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826131775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.826131775
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3018926599
Short name T361
Test name
Test status
Simulation time 140939057 ps
CPU time 1.15 seconds
Started Mar 07 12:32:37 PM PST 24
Finished Mar 07 12:32:39 PM PST 24
Peak memory 200280 kb
Host smart-7a2b4847-f7f5-4205-be82-02d97e1c44bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018926599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3018926599
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2601633623
Short name T388
Test name
Test status
Simulation time 75743964 ps
CPU time 0.74 seconds
Started Mar 07 12:32:32 PM PST 24
Finished Mar 07 12:32:33 PM PST 24
Peak memory 200076 kb
Host smart-9d60b2c0-39ca-4f36-bb4a-048a7b8714e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601633623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2601633623
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.4041861243
Short name T482
Test name
Test status
Simulation time 2344924235 ps
CPU time 7.99 seconds
Started Mar 07 12:32:41 PM PST 24
Finished Mar 07 12:32:49 PM PST 24
Peak memory 217788 kb
Host smart-ea9a2475-8348-4991-adf3-729a25db6796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041861243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.4041861243
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2016832514
Short name T39
Test name
Test status
Simulation time 244538663 ps
CPU time 1.02 seconds
Started Mar 07 12:32:37 PM PST 24
Finished Mar 07 12:32:39 PM PST 24
Peak memory 217020 kb
Host smart-519e5284-682e-41ba-aeab-a1f8a7e3cc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016832514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2016832514
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1126312847
Short name T449
Test name
Test status
Simulation time 75740371 ps
CPU time 0.76 seconds
Started Mar 07 12:32:38 PM PST 24
Finished Mar 07 12:32:39 PM PST 24
Peak memory 200156 kb
Host smart-dbf4467f-1b74-4e14-9f47-f1c783a65a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126312847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1126312847
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2915281105
Short name T403
Test name
Test status
Simulation time 881754519 ps
CPU time 4.48 seconds
Started Mar 07 12:32:45 PM PST 24
Finished Mar 07 12:32:50 PM PST 24
Peak memory 199036 kb
Host smart-f252bcfa-67fd-4289-984a-3f54ff32a194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915281105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2915281105
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1471763304
Short name T412
Test name
Test status
Simulation time 177447217 ps
CPU time 1.17 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 199652 kb
Host smart-502f966a-0689-4eeb-b9f6-cff4a8572c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471763304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1471763304
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3095994824
Short name T499
Test name
Test status
Simulation time 255900786 ps
CPU time 1.65 seconds
Started Mar 07 12:32:36 PM PST 24
Finished Mar 07 12:32:38 PM PST 24
Peak memory 200496 kb
Host smart-1c8e15d2-c724-4822-aa27-127248d515a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095994824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3095994824
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3368276929
Short name T119
Test name
Test status
Simulation time 5691358717 ps
CPU time 23.69 seconds
Started Mar 07 12:32:34 PM PST 24
Finished Mar 07 12:32:58 PM PST 24
Peak memory 200660 kb
Host smart-3773538e-f737-4c1b-837c-b658e5b8be45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368276929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3368276929
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2631098643
Short name T262
Test name
Test status
Simulation time 141329557 ps
CPU time 1.84 seconds
Started Mar 07 12:32:38 PM PST 24
Finished Mar 07 12:32:41 PM PST 24
Peak memory 200152 kb
Host smart-7f33ec24-decc-49a6-b782-6ae138c9767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631098643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2631098643
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2774091338
Short name T513
Test name
Test status
Simulation time 84650496 ps
CPU time 0.87 seconds
Started Mar 07 12:32:38 PM PST 24
Finished Mar 07 12:32:40 PM PST 24
Peak memory 200260 kb
Host smart-4f686354-2d19-41f6-9ff5-7469b3e50edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774091338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2774091338
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.363652752
Short name T507
Test name
Test status
Simulation time 64536988 ps
CPU time 0.82 seconds
Started Mar 07 12:32:47 PM PST 24
Finished Mar 07 12:32:48 PM PST 24
Peak memory 200236 kb
Host smart-5ce73539-dc38-4eda-85ab-2eb8f0a0b563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363652752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.363652752
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3974308233
Short name T35
Test name
Test status
Simulation time 1896790913 ps
CPU time 7.8 seconds
Started Mar 07 12:32:49 PM PST 24
Finished Mar 07 12:32:57 PM PST 24
Peak memory 217204 kb
Host smart-8888f2a5-c315-4c41-90db-5918a3d2158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974308233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3974308233
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3996704630
Short name T413
Test name
Test status
Simulation time 244356998 ps
CPU time 1.07 seconds
Started Mar 07 12:32:54 PM PST 24
Finished Mar 07 12:32:55 PM PST 24
Peak memory 217164 kb
Host smart-8aef2230-3d5c-44d4-92d2-ddc541d1f35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996704630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3996704630
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.325821209
Short name T287
Test name
Test status
Simulation time 168582441 ps
CPU time 0.8 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 200036 kb
Host smart-a3d4f949-9528-408e-867c-9cccf6f63b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325821209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.325821209
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2347089900
Short name T124
Test name
Test status
Simulation time 1536094210 ps
CPU time 6.4 seconds
Started Mar 07 12:32:45 PM PST 24
Finished Mar 07 12:32:51 PM PST 24
Peak memory 200524 kb
Host smart-890211b8-e242-4893-9413-f5d6c559313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347089900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2347089900
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1263169284
Short name T175
Test name
Test status
Simulation time 104023972 ps
CPU time 0.97 seconds
Started Mar 07 12:32:55 PM PST 24
Finished Mar 07 12:32:57 PM PST 24
Peak memory 199080 kb
Host smart-29ffe237-0255-490d-93de-003fec3abeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263169284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1263169284
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1632407705
Short name T381
Test name
Test status
Simulation time 190275001 ps
CPU time 1.35 seconds
Started Mar 07 12:32:36 PM PST 24
Finished Mar 07 12:32:37 PM PST 24
Peak memory 200476 kb
Host smart-4d4230de-48bb-4c8b-9d12-d7fce6cba596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632407705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1632407705
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.8842588
Short name T535
Test name
Test status
Simulation time 3669389912 ps
CPU time 18.22 seconds
Started Mar 07 12:32:47 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 200552 kb
Host smart-2b575904-9aad-4944-8b5d-cd69c616c05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8842588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.8842588
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2888694160
Short name T189
Test name
Test status
Simulation time 116457561 ps
CPU time 1.47 seconds
Started Mar 07 12:32:51 PM PST 24
Finished Mar 07 12:32:53 PM PST 24
Peak memory 200196 kb
Host smart-11470485-85dc-448f-950c-bbf682a19e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888694160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2888694160
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1047684182
Short name T107
Test name
Test status
Simulation time 154190912 ps
CPU time 1.37 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:48 PM PST 24
Peak memory 200540 kb
Host smart-3c41be15-a268-4817-a642-3ff37af88f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047684182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1047684182
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3369600049
Short name T208
Test name
Test status
Simulation time 80114719 ps
CPU time 0.81 seconds
Started Mar 07 12:32:55 PM PST 24
Finished Mar 07 12:32:57 PM PST 24
Peak memory 198844 kb
Host smart-88cb12c3-2090-43ed-9baa-2ebdbeffe574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369600049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3369600049
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1407331964
Short name T406
Test name
Test status
Simulation time 1229420090 ps
CPU time 5.36 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:51 PM PST 24
Peak memory 217028 kb
Host smart-2badb60c-b5b7-4eaa-b760-1f30a7e01ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407331964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1407331964
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1541055457
Short name T357
Test name
Test status
Simulation time 245869639 ps
CPU time 1.07 seconds
Started Mar 07 12:32:55 PM PST 24
Finished Mar 07 12:32:57 PM PST 24
Peak memory 207064 kb
Host smart-74d3365e-f159-4744-a296-d921744764c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541055457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1541055457
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.402233216
Short name T178
Test name
Test status
Simulation time 133416488 ps
CPU time 0.84 seconds
Started Mar 07 12:32:50 PM PST 24
Finished Mar 07 12:32:51 PM PST 24
Peak memory 200164 kb
Host smart-4629bb01-2ef3-4b98-b604-5d1543df86c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402233216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.402233216
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.515450172
Short name T169
Test name
Test status
Simulation time 1280958462 ps
CPU time 6.13 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 200428 kb
Host smart-76fd17f7-e8b2-4ea9-876c-5649e1404d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515450172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.515450172
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3897099567
Short name T302
Test name
Test status
Simulation time 101271884 ps
CPU time 0.96 seconds
Started Mar 07 12:32:55 PM PST 24
Finished Mar 07 12:32:57 PM PST 24
Peak memory 198276 kb
Host smart-0924baf4-d08c-4ae5-8fbf-b74c0a4bbfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897099567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3897099567
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2154824633
Short name T469
Test name
Test status
Simulation time 201749994 ps
CPU time 1.35 seconds
Started Mar 07 12:32:57 PM PST 24
Finished Mar 07 12:32:59 PM PST 24
Peak memory 200328 kb
Host smart-2785198e-fbbd-4377-a892-31405b5679a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154824633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2154824633
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.943055875
Short name T216
Test name
Test status
Simulation time 148651405 ps
CPU time 1.91 seconds
Started Mar 07 12:32:58 PM PST 24
Finished Mar 07 12:33:01 PM PST 24
Peak memory 200220 kb
Host smart-1ef41fbd-9920-40ab-9a6b-3267ec2c69cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943055875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.943055875
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2907509982
Short name T506
Test name
Test status
Simulation time 189117054 ps
CPU time 1.2 seconds
Started Mar 07 12:32:48 PM PST 24
Finished Mar 07 12:32:50 PM PST 24
Peak memory 200372 kb
Host smart-65821421-b957-4d76-8fd2-6e392494d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907509982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2907509982
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.279552712
Short name T220
Test name
Test status
Simulation time 73028269 ps
CPU time 0.81 seconds
Started Mar 07 12:32:48 PM PST 24
Finished Mar 07 12:32:49 PM PST 24
Peak memory 200284 kb
Host smart-0bba1b40-743c-48e6-97c5-5974900d6677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279552712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.279552712
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2011791029
Short name T339
Test name
Test status
Simulation time 244331183 ps
CPU time 1.01 seconds
Started Mar 07 12:32:57 PM PST 24
Finished Mar 07 12:32:59 PM PST 24
Peak memory 217144 kb
Host smart-c748442d-de34-442f-b75c-40bca9c6274d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011791029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2011791029
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1790173739
Short name T228
Test name
Test status
Simulation time 170415497 ps
CPU time 0.91 seconds
Started Mar 07 12:32:53 PM PST 24
Finished Mar 07 12:32:54 PM PST 24
Peak memory 200208 kb
Host smart-f40c0219-de2d-4b9c-b209-d5a9ade6a7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790173739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1790173739
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3363612448
Short name T123
Test name
Test status
Simulation time 1332993492 ps
CPU time 5.59 seconds
Started Mar 07 12:32:49 PM PST 24
Finished Mar 07 12:32:55 PM PST 24
Peak memory 200460 kb
Host smart-a061f16a-cbfd-448a-b666-036e7ee2fa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363612448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3363612448
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1290417055
Short name T505
Test name
Test status
Simulation time 174408371 ps
CPU time 1.16 seconds
Started Mar 07 12:32:55 PM PST 24
Finished Mar 07 12:32:58 PM PST 24
Peak memory 200040 kb
Host smart-8fee49c7-9b54-448e-84ce-b1d54df3054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290417055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1290417055
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.39806740
Short name T504
Test name
Test status
Simulation time 258403450 ps
CPU time 1.57 seconds
Started Mar 07 12:33:09 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 200448 kb
Host smart-26652924-1eca-4ce7-beeb-f8c20b35d189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39806740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.39806740
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1614346189
Short name T438
Test name
Test status
Simulation time 4268475762 ps
CPU time 19.56 seconds
Started Mar 07 12:32:49 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 200632 kb
Host smart-b80bbbc1-2815-4d93-86a4-ea4e7ccc522e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614346189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1614346189
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3429885672
Short name T263
Test name
Test status
Simulation time 141190406 ps
CPU time 1.82 seconds
Started Mar 07 12:32:45 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 200356 kb
Host smart-8415aa3b-64db-4417-86e6-b35b58e6b200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429885672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3429885672
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1760274004
Short name T270
Test name
Test status
Simulation time 144650205 ps
CPU time 1.11 seconds
Started Mar 07 12:32:45 PM PST 24
Finished Mar 07 12:32:46 PM PST 24
Peak memory 200288 kb
Host smart-48e8669f-69d0-4da3-9dcc-9f1e97b07011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760274004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1760274004
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3820940598
Short name T336
Test name
Test status
Simulation time 61491002 ps
CPU time 0.75 seconds
Started Mar 07 12:32:52 PM PST 24
Finished Mar 07 12:32:53 PM PST 24
Peak memory 200172 kb
Host smart-7be264d2-d7e8-4f94-878f-6d69c16a9551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820940598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3820940598
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3097330302
Short name T46
Test name
Test status
Simulation time 2354757294 ps
CPU time 8.27 seconds
Started Mar 07 12:32:55 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 216328 kb
Host smart-7f768937-04a3-4c35-b563-1a656ef4b7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097330302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3097330302
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3153028088
Short name T433
Test name
Test status
Simulation time 244916671 ps
CPU time 1.11 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 217220 kb
Host smart-0023f7be-73ab-4b23-a749-fe235e4478bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153028088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3153028088
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3408870359
Short name T350
Test name
Test status
Simulation time 133357245 ps
CPU time 0.84 seconds
Started Mar 07 12:32:59 PM PST 24
Finished Mar 07 12:33:00 PM PST 24
Peak memory 200156 kb
Host smart-9eecd3ab-c980-40da-a201-1526f69fed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408870359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3408870359
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.682191563
Short name T416
Test name
Test status
Simulation time 1572838480 ps
CPU time 6.17 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 200496 kb
Host smart-53283e3a-39f6-4e37-8666-838a63cff4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682191563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.682191563
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2496615128
Short name T472
Test name
Test status
Simulation time 97869371 ps
CPU time 0.95 seconds
Started Mar 07 12:32:57 PM PST 24
Finished Mar 07 12:32:59 PM PST 24
Peak memory 200264 kb
Host smart-d44ef2ee-653b-4017-8071-a1e2db954c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496615128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2496615128
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2128026593
Short name T445
Test name
Test status
Simulation time 202694733 ps
CPU time 1.55 seconds
Started Mar 07 12:32:49 PM PST 24
Finished Mar 07 12:32:51 PM PST 24
Peak memory 200456 kb
Host smart-5cbd00d0-f753-4e99-9275-71753ad3b05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128026593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2128026593
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1412395501
Short name T476
Test name
Test status
Simulation time 3641230664 ps
CPU time 16.25 seconds
Started Mar 07 12:32:49 PM PST 24
Finished Mar 07 12:33:06 PM PST 24
Peak memory 200548 kb
Host smart-27fd0b7e-a4dc-4299-b667-64b4acf1b3c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412395501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1412395501
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2753705084
Short name T501
Test name
Test status
Simulation time 346861993 ps
CPU time 2.41 seconds
Started Mar 07 12:32:59 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 200244 kb
Host smart-177451aa-9e01-40aa-bcab-a6e2332d7ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753705084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2753705084
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2595055531
Short name T280
Test name
Test status
Simulation time 186082968 ps
CPU time 1.21 seconds
Started Mar 07 12:32:59 PM PST 24
Finished Mar 07 12:33:02 PM PST 24
Peak memory 200308 kb
Host smart-35a4cb7d-96f8-48e9-8141-84e1ffc4f84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595055531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2595055531
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3670241434
Short name T198
Test name
Test status
Simulation time 68116851 ps
CPU time 0.87 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:47 PM PST 24
Peak memory 200228 kb
Host smart-8e384904-62a7-4e93-a11c-c6b8c30c109a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670241434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3670241434
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3310241520
Short name T330
Test name
Test status
Simulation time 1909418318 ps
CPU time 7.06 seconds
Started Mar 07 12:32:51 PM PST 24
Finished Mar 07 12:32:58 PM PST 24
Peak memory 220836 kb
Host smart-14fdd918-8fe4-44c3-9be5-ee47e8cbad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310241520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3310241520
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1161884768
Short name T338
Test name
Test status
Simulation time 243530963 ps
CPU time 1.06 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 217180 kb
Host smart-c9c7cb32-becf-411d-9f67-dd159312024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161884768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1161884768
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3338372848
Short name T164
Test name
Test status
Simulation time 142612487 ps
CPU time 0.87 seconds
Started Mar 07 12:32:47 PM PST 24
Finished Mar 07 12:32:48 PM PST 24
Peak memory 199808 kb
Host smart-d7872a93-e6ed-4dd9-8da7-8b0a8a1c2083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338372848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3338372848
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3121072003
Short name T281
Test name
Test status
Simulation time 969447067 ps
CPU time 4.76 seconds
Started Mar 07 12:32:53 PM PST 24
Finished Mar 07 12:32:57 PM PST 24
Peak memory 200476 kb
Host smart-10ebd3c8-e0f5-4e28-8cc1-2603e666fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121072003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3121072003
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3535783086
Short name T431
Test name
Test status
Simulation time 154916098 ps
CPU time 1.18 seconds
Started Mar 07 12:32:47 PM PST 24
Finished Mar 07 12:32:48 PM PST 24
Peak memory 200348 kb
Host smart-a3b392c2-c861-4fbf-a202-120701b29058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535783086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3535783086
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4292909550
Short name T108
Test name
Test status
Simulation time 194900102 ps
CPU time 1.34 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 200484 kb
Host smart-155abbfb-953d-411f-ac4a-99a32b747e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292909550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4292909550
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1266241986
Short name T111
Test name
Test status
Simulation time 6110529356 ps
CPU time 20.1 seconds
Started Mar 07 12:32:49 PM PST 24
Finished Mar 07 12:33:10 PM PST 24
Peak memory 200564 kb
Host smart-fa54085e-c99f-491e-bf12-7a28f0469e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266241986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1266241986
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1557703446
Short name T427
Test name
Test status
Simulation time 140657240 ps
CPU time 1.89 seconds
Started Mar 07 12:32:46 PM PST 24
Finished Mar 07 12:32:48 PM PST 24
Peak memory 200272 kb
Host smart-cdea3a91-8f76-4abe-bfa3-aa99e4a85140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557703446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1557703446
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3390731043
Short name T466
Test name
Test status
Simulation time 186116545 ps
CPU time 1.14 seconds
Started Mar 07 12:32:50 PM PST 24
Finished Mar 07 12:32:52 PM PST 24
Peak memory 200328 kb
Host smart-ec044e5e-1166-4531-942c-14ed841c949c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390731043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3390731043
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1556970239
Short name T540
Test name
Test status
Simulation time 82333039 ps
CPU time 0.78 seconds
Started Mar 07 12:33:07 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 200144 kb
Host smart-23af70b2-2b36-4e5c-9288-4b43695de9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556970239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1556970239
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2899278877
Short name T264
Test name
Test status
Simulation time 1896536603 ps
CPU time 7.16 seconds
Started Mar 07 12:33:14 PM PST 24
Finished Mar 07 12:33:21 PM PST 24
Peak memory 216948 kb
Host smart-9d74839a-4542-4714-bd05-ad8049bb4064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899278877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2899278877
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3061138564
Short name T434
Test name
Test status
Simulation time 244160201 ps
CPU time 1.12 seconds
Started Mar 07 12:33:21 PM PST 24
Finished Mar 07 12:33:22 PM PST 24
Peak memory 217060 kb
Host smart-cddfa1d2-ba56-4309-847e-d2ca63eb0539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061138564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3061138564
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.4005786637
Short name T297
Test name
Test status
Simulation time 179649192 ps
CPU time 0.95 seconds
Started Mar 07 12:33:00 PM PST 24
Finished Mar 07 12:33:01 PM PST 24
Peak memory 200084 kb
Host smart-c838dc6b-5eba-4769-9410-2927f9a08fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005786637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.4005786637
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.480994384
Short name T257
Test name
Test status
Simulation time 694458442 ps
CPU time 3.47 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:06 PM PST 24
Peak memory 200532 kb
Host smart-6622dd2a-331b-48c9-a630-76bad7edf354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480994384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.480994384
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3057688470
Short name T335
Test name
Test status
Simulation time 179522675 ps
CPU time 1.22 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:33:21 PM PST 24
Peak memory 200368 kb
Host smart-f521d272-a405-44c2-9f63-8898f92f881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057688470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3057688470
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.998075506
Short name T470
Test name
Test status
Simulation time 186859221 ps
CPU time 1.35 seconds
Started Mar 07 12:32:55 PM PST 24
Finished Mar 07 12:32:58 PM PST 24
Peak memory 200456 kb
Host smart-6fd12059-c87d-415b-9853-6c9a4d611987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998075506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.998075506
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2988522606
Short name T382
Test name
Test status
Simulation time 3786731643 ps
CPU time 16.34 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:20 PM PST 24
Peak memory 208740 kb
Host smart-1ef9692c-9894-490c-9d41-7fd171c77903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988522606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2988522606
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.675729841
Short name T48
Test name
Test status
Simulation time 410080115 ps
CPU time 2.37 seconds
Started Mar 07 12:33:07 PM PST 24
Finished Mar 07 12:33:10 PM PST 24
Peak memory 200252 kb
Host smart-433db8b9-7fd2-4760-b463-b86afc752a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675729841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.675729841
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1439647631
Short name T252
Test name
Test status
Simulation time 166988074 ps
CPU time 1.22 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 200352 kb
Host smart-293ac0bc-3a6f-4168-9137-e1ae3842cb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439647631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1439647631
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1391254342
Short name T210
Test name
Test status
Simulation time 69448137 ps
CPU time 0.79 seconds
Started Mar 07 12:33:08 PM PST 24
Finished Mar 07 12:33:09 PM PST 24
Peak memory 200176 kb
Host smart-b45ba2b5-4607-4a08-aa2d-b1202c7d628b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391254342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1391254342
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.862267749
Short name T349
Test name
Test status
Simulation time 2340086192 ps
CPU time 9.26 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:12 PM PST 24
Peak memory 217868 kb
Host smart-84384739-ea76-4f8e-acee-2d23feb10120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862267749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.862267749
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4052969284
Short name T491
Test name
Test status
Simulation time 244573725 ps
CPU time 1.14 seconds
Started Mar 07 12:33:01 PM PST 24
Finished Mar 07 12:33:02 PM PST 24
Peak memory 217296 kb
Host smart-175027c8-7f82-45e1-82b8-20743b30b27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052969284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4052969284
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4153937390
Short name T464
Test name
Test status
Simulation time 218285345 ps
CPU time 0.91 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:33:16 PM PST 24
Peak memory 200136 kb
Host smart-e69fe41f-eeea-4642-899f-51e9b312b652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153937390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4153937390
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.4056969311
Short name T209
Test name
Test status
Simulation time 835254759 ps
CPU time 3.89 seconds
Started Mar 07 12:33:13 PM PST 24
Finished Mar 07 12:33:17 PM PST 24
Peak memory 200476 kb
Host smart-10afc062-c873-4dce-a8f4-d25c75b5c52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056969311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.4056969311
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3617219298
Short name T224
Test name
Test status
Simulation time 150583542 ps
CPU time 1.11 seconds
Started Mar 07 12:32:59 PM PST 24
Finished Mar 07 12:33:01 PM PST 24
Peak memory 200448 kb
Host smart-679dee52-509a-4267-9a20-c1335d29bcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617219298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3617219298
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2777187926
Short name T184
Test name
Test status
Simulation time 236368365 ps
CPU time 1.39 seconds
Started Mar 07 12:33:05 PM PST 24
Finished Mar 07 12:33:06 PM PST 24
Peak memory 200472 kb
Host smart-6145b144-7be3-48ee-b2d0-a86d54b4ae18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777187926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2777187926
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1201349173
Short name T244
Test name
Test status
Simulation time 5236409229 ps
CPU time 21.31 seconds
Started Mar 07 12:33:30 PM PST 24
Finished Mar 07 12:33:52 PM PST 24
Peak memory 200528 kb
Host smart-cefbbd9f-b991-42a6-ba40-2bdb0d301cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201349173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1201349173
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4095517989
Short name T109
Test name
Test status
Simulation time 342200587 ps
CPU time 2.13 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:06 PM PST 24
Peak memory 200264 kb
Host smart-5c6122e4-cacc-456d-ab86-bb883fe888a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095517989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4095517989
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2490454464
Short name T200
Test name
Test status
Simulation time 79984976 ps
CPU time 0.89 seconds
Started Mar 07 12:32:59 PM PST 24
Finished Mar 07 12:33:01 PM PST 24
Peak memory 200360 kb
Host smart-8411964a-a1cd-40dc-b2a2-9dca7bdf7a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490454464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2490454464
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2480742661
Short name T185
Test name
Test status
Simulation time 78621976 ps
CPU time 0.86 seconds
Started Mar 07 12:32:59 PM PST 24
Finished Mar 07 12:33:01 PM PST 24
Peak memory 200228 kb
Host smart-cbb6af62-c9b8-4e69-8723-1effcee83349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480742661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2480742661
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.28477430
Short name T332
Test name
Test status
Simulation time 1888380834 ps
CPU time 6.99 seconds
Started Mar 07 12:33:01 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 221840 kb
Host smart-d77446f6-5552-421e-b28c-04cffceda0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28477430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.28477430
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2734037503
Short name T328
Test name
Test status
Simulation time 245405836 ps
CPU time 1.08 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:33:25 PM PST 24
Peak memory 217152 kb
Host smart-d0b56fcd-7870-4603-b43a-8ca0106d9262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734037503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2734037503
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.765813920
Short name T288
Test name
Test status
Simulation time 87399307 ps
CPU time 0.74 seconds
Started Mar 07 12:33:10 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 200136 kb
Host smart-f20b4dc8-f010-48d7-9147-82f95304a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765813920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.765813920
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1292673821
Short name T423
Test name
Test status
Simulation time 1064914048 ps
CPU time 4.89 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:33:25 PM PST 24
Peak memory 200532 kb
Host smart-bc11aee9-6683-4653-88b2-4d8de44eb06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292673821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1292673821
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.692280915
Short name T300
Test name
Test status
Simulation time 167451475 ps
CPU time 1.26 seconds
Started Mar 07 12:33:09 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 200352 kb
Host smart-f4ede3f7-8071-4f31-a863-6e6eb870dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692280915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.692280915
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3490344750
Short name T212
Test name
Test status
Simulation time 202238793 ps
CPU time 1.39 seconds
Started Mar 07 12:32:57 PM PST 24
Finished Mar 07 12:32:59 PM PST 24
Peak memory 200436 kb
Host smart-b0c843f6-639d-4c01-82da-88d643f97afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490344750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3490344750
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2109744065
Short name T233
Test name
Test status
Simulation time 14710362013 ps
CPU time 54.25 seconds
Started Mar 07 12:33:10 PM PST 24
Finished Mar 07 12:34:06 PM PST 24
Peak memory 200460 kb
Host smart-196f2d99-377b-4188-aac6-9681ece5a424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109744065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2109744065
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1754746156
Short name T313
Test name
Test status
Simulation time 114494708 ps
CPU time 1.62 seconds
Started Mar 07 12:32:58 PM PST 24
Finished Mar 07 12:33:02 PM PST 24
Peak memory 200308 kb
Host smart-2144db2d-8930-4659-b22f-95f4fd8a10d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754746156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1754746156
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3313987608
Short name T144
Test name
Test status
Simulation time 129985391 ps
CPU time 1.04 seconds
Started Mar 07 12:33:11 PM PST 24
Finished Mar 07 12:33:12 PM PST 24
Peak memory 200328 kb
Host smart-23c95808-2dbb-4e25-ad7e-eb0bceed458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313987608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3313987608
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4173264982
Short name T508
Test name
Test status
Simulation time 132068546 ps
CPU time 0.95 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200240 kb
Host smart-f296f894-eaff-4849-a4ca-55222dd3575f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173264982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4173264982
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4098441321
Short name T373
Test name
Test status
Simulation time 1227592158 ps
CPU time 5.87 seconds
Started Mar 07 12:32:07 PM PST 24
Finished Mar 07 12:32:14 PM PST 24
Peak memory 216548 kb
Host smart-d0e7379d-df18-4db1-909a-57741bfb809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098441321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4098441321
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.630983711
Short name T243
Test name
Test status
Simulation time 244209313 ps
CPU time 1.14 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:10 PM PST 24
Peak memory 217148 kb
Host smart-5ba1a958-4db1-448a-8f7f-fa0319e16806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630983711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.630983711
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.5079057
Short name T17
Test name
Test status
Simulation time 131158817 ps
CPU time 0.84 seconds
Started Mar 07 12:32:05 PM PST 24
Finished Mar 07 12:32:06 PM PST 24
Peak memory 200008 kb
Host smart-3201a896-c240-4e84-a620-cd394cf44a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5079057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.5079057
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.178855087
Short name T113
Test name
Test status
Simulation time 1952137011 ps
CPU time 7.83 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 200472 kb
Host smart-8aad0e49-4eba-4174-997d-37e240b1f068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178855087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.178855087
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2429571303
Short name T72
Test name
Test status
Simulation time 8432143040 ps
CPU time 12.79 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:21 PM PST 24
Peak memory 220828 kb
Host smart-786efcf6-cded-4059-a013-4adf993d8eb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429571303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2429571303
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3579172906
Short name T532
Test name
Test status
Simulation time 141940103 ps
CPU time 1.08 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:09 PM PST 24
Peak memory 200176 kb
Host smart-f95962c1-5363-4423-ac94-e640f31c57c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579172906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3579172906
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2409281206
Short name T493
Test name
Test status
Simulation time 263038770 ps
CPU time 1.5 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:10 PM PST 24
Peak memory 200408 kb
Host smart-fa8facb5-a8f8-442f-86f8-c02b06243089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409281206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2409281206
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3507954069
Short name T114
Test name
Test status
Simulation time 8608524402 ps
CPU time 38.29 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:46 PM PST 24
Peak memory 200500 kb
Host smart-fa5d3382-75c5-4e3f-9b8f-3460c9406f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507954069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3507954069
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2136076833
Short name T82
Test name
Test status
Simulation time 135108330 ps
CPU time 1.72 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:10 PM PST 24
Peak memory 200232 kb
Host smart-9c38703e-7a0c-4a77-8357-2108af3f58f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136076833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2136076833
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.649665383
Short name T526
Test name
Test status
Simulation time 176625267 ps
CPU time 1.21 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 200280 kb
Host smart-c4b724b5-9ce9-4c6b-8ae0-2d8ab7874be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649665383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.649665383
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2479268011
Short name T167
Test name
Test status
Simulation time 74408487 ps
CPU time 0.82 seconds
Started Mar 07 12:33:01 PM PST 24
Finished Mar 07 12:33:02 PM PST 24
Peak memory 200324 kb
Host smart-c35629ff-3774-41b2-9472-319b6b93adeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479268011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2479268011
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2033382842
Short name T251
Test name
Test status
Simulation time 243776516 ps
CPU time 1.2 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 217172 kb
Host smart-e1f6fed8-b707-49d6-ab2f-c4e156aa9fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033382842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2033382842
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.621900149
Short name T180
Test name
Test status
Simulation time 102738055 ps
CPU time 0.8 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:03 PM PST 24
Peak memory 200144 kb
Host smart-88bf2169-c621-4d9e-afc7-a3984cea1944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621900149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.621900149
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2031426972
Short name T333
Test name
Test status
Simulation time 1288824291 ps
CPU time 5.95 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:09 PM PST 24
Peak memory 200532 kb
Host smart-69d22172-470e-4cef-9e42-916785ae86c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031426972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2031426972
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3496581936
Short name T414
Test name
Test status
Simulation time 147191361 ps
CPU time 1.17 seconds
Started Mar 07 12:33:17 PM PST 24
Finished Mar 07 12:33:18 PM PST 24
Peak memory 200336 kb
Host smart-71fa43e4-9e2e-4944-931e-b508ff0e4e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496581936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3496581936
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3763688250
Short name T181
Test name
Test status
Simulation time 199447738 ps
CPU time 1.41 seconds
Started Mar 07 12:33:06 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 200452 kb
Host smart-99b1b8da-6586-4185-a729-785585a892c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763688250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3763688250
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1826014019
Short name T522
Test name
Test status
Simulation time 4240697411 ps
CPU time 20.43 seconds
Started Mar 07 12:33:05 PM PST 24
Finished Mar 07 12:33:26 PM PST 24
Peak memory 208776 kb
Host smart-4e47a2d0-cc5b-4f79-b0f5-bcc78b158dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826014019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1826014019
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1163833487
Short name T171
Test name
Test status
Simulation time 123073519 ps
CPU time 1.52 seconds
Started Mar 07 12:33:08 PM PST 24
Finished Mar 07 12:33:09 PM PST 24
Peak memory 208424 kb
Host smart-9b882374-62b5-432c-976f-9a61880a9b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163833487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1163833487
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2873526844
Short name T260
Test name
Test status
Simulation time 69368136 ps
CPU time 0.77 seconds
Started Mar 07 12:33:06 PM PST 24
Finished Mar 07 12:33:07 PM PST 24
Peak memory 200356 kb
Host smart-1f2ac303-1fd7-4ea6-9966-a3982bbd6336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873526844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2873526844
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2839862683
Short name T533
Test name
Test status
Simulation time 62830546 ps
CPU time 0.75 seconds
Started Mar 07 12:33:17 PM PST 24
Finished Mar 07 12:33:18 PM PST 24
Peak memory 200200 kb
Host smart-75c5217c-f26f-453a-bb33-ac0741c061ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839862683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2839862683
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.517695510
Short name T59
Test name
Test status
Simulation time 1216756221 ps
CPU time 5.52 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:33:24 PM PST 24
Peak memory 216620 kb
Host smart-004693bf-86da-48ab-8ccb-ef02110ee2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517695510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.517695510
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1391269632
Short name T276
Test name
Test status
Simulation time 244362887 ps
CPU time 1.22 seconds
Started Mar 07 12:33:00 PM PST 24
Finished Mar 07 12:33:02 PM PST 24
Peak memory 217104 kb
Host smart-92465db8-a9d6-4d35-bfb0-052a95d83768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391269632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1391269632
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3658347613
Short name T481
Test name
Test status
Simulation time 205814128 ps
CPU time 0.91 seconds
Started Mar 07 12:32:58 PM PST 24
Finished Mar 07 12:33:01 PM PST 24
Peak memory 200244 kb
Host smart-3718354a-b4ac-4dfb-968f-417f42b5e852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658347613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3658347613
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3369530377
Short name T411
Test name
Test status
Simulation time 785028516 ps
CPU time 4.01 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:06 PM PST 24
Peak memory 200528 kb
Host smart-c55cf821-8597-4db1-a6f2-84f8c722435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369530377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3369530377
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2426322371
Short name T197
Test name
Test status
Simulation time 148819323 ps
CPU time 1.17 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:33:16 PM PST 24
Peak memory 200360 kb
Host smart-eeb579f6-c6af-4702-94e7-b270b86ea3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426322371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2426322371
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3300785144
Short name T207
Test name
Test status
Simulation time 248815405 ps
CPU time 1.59 seconds
Started Mar 07 12:33:06 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 200448 kb
Host smart-be80b59b-a262-4885-852f-a3b68fa27c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300785144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3300785144
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.763548563
Short name T192
Test name
Test status
Simulation time 2812677203 ps
CPU time 14.1 seconds
Started Mar 07 12:32:59 PM PST 24
Finished Mar 07 12:33:14 PM PST 24
Peak memory 200536 kb
Host smart-3eeedf64-f381-48ba-bac2-980cd9b6eb05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763548563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.763548563
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2490107331
Short name T170
Test name
Test status
Simulation time 342028074 ps
CPU time 2.22 seconds
Started Mar 07 12:33:08 PM PST 24
Finished Mar 07 12:33:10 PM PST 24
Peak memory 200236 kb
Host smart-17fd3e19-6af5-4cdd-a96d-748de902a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490107331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2490107331
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1821590494
Short name T274
Test name
Test status
Simulation time 144031108 ps
CPU time 1.05 seconds
Started Mar 07 12:32:58 PM PST 24
Finished Mar 07 12:32:59 PM PST 24
Peak memory 200456 kb
Host smart-0177d5e4-7882-403d-b903-85724d7dfbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821590494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1821590494
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.675996677
Short name T323
Test name
Test status
Simulation time 73445696 ps
CPU time 0.8 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 200256 kb
Host smart-298a6bd6-3e5b-4214-92ae-e9a6aecacfbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675996677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.675996677
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.790813220
Short name T29
Test name
Test status
Simulation time 1898506872 ps
CPU time 7.02 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 217748 kb
Host smart-287dfe34-b9a7-4772-ab24-31002201a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790813220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.790813220
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2223432991
Short name T254
Test name
Test status
Simulation time 244109254 ps
CPU time 1.21 seconds
Started Mar 07 12:33:01 PM PST 24
Finished Mar 07 12:33:03 PM PST 24
Peak memory 217292 kb
Host smart-3299d452-215b-4c1f-8aa1-29e1be081e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223432991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2223432991
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2888386203
Short name T20
Test name
Test status
Simulation time 201035786 ps
CPU time 0.91 seconds
Started Mar 07 12:33:27 PM PST 24
Finished Mar 07 12:33:28 PM PST 24
Peak memory 200168 kb
Host smart-939e552f-f671-40c8-8fce-616286159237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888386203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2888386203
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1870523949
Short name T419
Test name
Test status
Simulation time 1235090442 ps
CPU time 4.73 seconds
Started Mar 07 12:33:14 PM PST 24
Finished Mar 07 12:33:18 PM PST 24
Peak memory 200516 kb
Host smart-ab95a4ef-87ac-4536-b214-47ea7be5be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870523949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1870523949
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1085382482
Short name T6
Test name
Test status
Simulation time 143155871 ps
CPU time 1.04 seconds
Started Mar 07 12:33:07 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 200244 kb
Host smart-0937af52-ede8-4e2d-a189-98c90517b07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085382482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1085382482
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.665848504
Short name T402
Test name
Test status
Simulation time 194656407 ps
CPU time 1.32 seconds
Started Mar 07 12:33:09 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 200396 kb
Host smart-67bac358-27d0-4699-8486-279e8226964a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665848504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.665848504
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3831936307
Short name T477
Test name
Test status
Simulation time 144777953 ps
CPU time 1.75 seconds
Started Mar 07 12:33:06 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 208500 kb
Host smart-fd4286de-4699-458f-9058-c4234d3ae6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831936307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3831936307
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2740685595
Short name T456
Test name
Test status
Simulation time 177119226 ps
CPU time 1.39 seconds
Started Mar 07 12:33:01 PM PST 24
Finished Mar 07 12:33:03 PM PST 24
Peak memory 200540 kb
Host smart-466c8400-b185-4dc0-b03a-704693a9a8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740685595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2740685595
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3327086354
Short name T269
Test name
Test status
Simulation time 71454548 ps
CPU time 0.77 seconds
Started Mar 07 12:33:05 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 200184 kb
Host smart-45bfdf1d-4aac-45bd-9511-c409b1c92714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327086354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3327086354
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.4260843083
Short name T346
Test name
Test status
Simulation time 1224077700 ps
CPU time 5.54 seconds
Started Mar 07 12:33:11 PM PST 24
Finished Mar 07 12:33:17 PM PST 24
Peak memory 221596 kb
Host smart-15178983-8fc6-4b6e-bfca-3a4b582a9544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260843083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4260843083
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1572179590
Short name T229
Test name
Test status
Simulation time 244152529 ps
CPU time 1.06 seconds
Started Mar 07 12:33:04 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 217140 kb
Host smart-3ecd7e7c-e56e-40b4-8d49-bd1de2b2da60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572179590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1572179590
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.4074205869
Short name T278
Test name
Test status
Simulation time 141655848 ps
CPU time 0.95 seconds
Started Mar 07 12:33:01 PM PST 24
Finished Mar 07 12:33:02 PM PST 24
Peak memory 200148 kb
Host smart-2020c1e6-5bf9-4326-a276-961b306164a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074205869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.4074205869
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3811374318
Short name T3
Test name
Test status
Simulation time 1265711613 ps
CPU time 5.12 seconds
Started Mar 07 12:33:04 PM PST 24
Finished Mar 07 12:33:09 PM PST 24
Peak memory 200540 kb
Host smart-7d70a770-1852-4be1-b049-888ff79d025f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811374318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3811374318
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1717754431
Short name T282
Test name
Test status
Simulation time 180027616 ps
CPU time 1.29 seconds
Started Mar 07 12:33:07 PM PST 24
Finished Mar 07 12:33:09 PM PST 24
Peak memory 200300 kb
Host smart-6100916d-61cb-4e78-8916-248f769ea032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717754431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1717754431
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1008622920
Short name T462
Test name
Test status
Simulation time 124401176 ps
CPU time 1.24 seconds
Started Mar 07 12:32:59 PM PST 24
Finished Mar 07 12:33:02 PM PST 24
Peak memory 200456 kb
Host smart-81e755ab-2377-46ea-929f-80c51aecd0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008622920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1008622920
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2784641616
Short name T134
Test name
Test status
Simulation time 9226989562 ps
CPU time 34.58 seconds
Started Mar 07 12:33:07 PM PST 24
Finished Mar 07 12:33:42 PM PST 24
Peak memory 200512 kb
Host smart-b4653b1e-64e9-4566-b8ea-e2cb3536bf93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784641616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2784641616
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3734449219
Short name T2
Test name
Test status
Simulation time 297065461 ps
CPU time 1.99 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:33:28 PM PST 24
Peak memory 208440 kb
Host smart-d5f3b635-12cc-4a99-89cb-4f4697ba1d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734449219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3734449219
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.4053892648
Short name T11
Test name
Test status
Simulation time 159659203 ps
CPU time 1.11 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:33:18 PM PST 24
Peak memory 200344 kb
Host smart-2bfc2cc1-546a-4b8a-89b8-c24cbf69f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053892648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4053892648
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3805972091
Short name T40
Test name
Test status
Simulation time 94951380 ps
CPU time 0.86 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 200176 kb
Host smart-86821f82-c220-4bd0-8efd-7c5a82bb6a93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805972091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3805972091
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1740687361
Short name T343
Test name
Test status
Simulation time 2347219053 ps
CPU time 8.41 seconds
Started Mar 07 12:33:07 PM PST 24
Finished Mar 07 12:33:16 PM PST 24
Peak memory 220972 kb
Host smart-25060751-61bd-4787-8a39-ecb91b53b62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740687361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1740687361
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1287562520
Short name T190
Test name
Test status
Simulation time 244483123 ps
CPU time 1.12 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:03 PM PST 24
Peak memory 217004 kb
Host smart-5611e93c-4385-4c78-ac08-53af1bc77068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287562520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1287562520
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3544094161
Short name T10
Test name
Test status
Simulation time 93858804 ps
CPU time 0.79 seconds
Started Mar 07 12:33:11 PM PST 24
Finished Mar 07 12:33:12 PM PST 24
Peak memory 200144 kb
Host smart-ad612479-bcce-4b20-94fb-5d1f3251403e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544094161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3544094161
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.4078203330
Short name T485
Test name
Test status
Simulation time 2156792322 ps
CPU time 8.2 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 200604 kb
Host smart-b381873d-9d59-4306-8843-29e2ae290879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078203330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4078203330
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2471230015
Short name T534
Test name
Test status
Simulation time 104039614 ps
CPU time 1.09 seconds
Started Mar 07 12:33:04 PM PST 24
Finished Mar 07 12:33:06 PM PST 24
Peak memory 200340 kb
Host smart-6f42c481-e7dc-4c85-93b6-2d3170b07426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471230015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2471230015
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1428993153
Short name T226
Test name
Test status
Simulation time 114279797 ps
CPU time 1.29 seconds
Started Mar 07 12:33:07 PM PST 24
Finished Mar 07 12:33:09 PM PST 24
Peak memory 200444 kb
Host smart-a24195cf-49a7-47ba-8e46-d65857d3d647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428993153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1428993153
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3854927151
Short name T23
Test name
Test status
Simulation time 519458485 ps
CPU time 2.81 seconds
Started Mar 07 12:32:59 PM PST 24
Finished Mar 07 12:33:03 PM PST 24
Peak memory 200500 kb
Host smart-9f501ffa-9c8f-4696-8833-766f222987f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854927151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3854927151
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4055659551
Short name T238
Test name
Test status
Simulation time 371573006 ps
CPU time 2.28 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:33:28 PM PST 24
Peak memory 200196 kb
Host smart-0630a042-8d2e-4564-8f60-c673f910aaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055659551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4055659551
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2167450819
Short name T418
Test name
Test status
Simulation time 190908030 ps
CPU time 1.27 seconds
Started Mar 07 12:33:17 PM PST 24
Finished Mar 07 12:33:18 PM PST 24
Peak memory 200300 kb
Host smart-bb21f2fc-4a6e-4a39-b74b-08c66ad1bd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167450819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2167450819
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.602081924
Short name T366
Test name
Test status
Simulation time 67646920 ps
CPU time 0.76 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:33:19 PM PST 24
Peak memory 200136 kb
Host smart-a4e7021c-4799-42c7-aae5-98b9f17f836e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602081924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.602081924
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1796299161
Short name T60
Test name
Test status
Simulation time 1219671618 ps
CPU time 5.38 seconds
Started Mar 07 12:33:10 PM PST 24
Finished Mar 07 12:33:16 PM PST 24
Peak memory 217756 kb
Host smart-b5e2ca78-2030-4729-8893-95d01dcc34ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796299161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1796299161
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3224109262
Short name T497
Test name
Test status
Simulation time 243872936 ps
CPU time 1.09 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 217072 kb
Host smart-e46b2b16-d341-43b0-b6f8-74144631a64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224109262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3224109262
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2564874861
Short name T15
Test name
Test status
Simulation time 122615710 ps
CPU time 0.78 seconds
Started Mar 07 12:33:26 PM PST 24
Finished Mar 07 12:33:27 PM PST 24
Peak memory 200132 kb
Host smart-b511cae3-3386-45d0-9da0-4113181974c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564874861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2564874861
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1847196959
Short name T394
Test name
Test status
Simulation time 1573585877 ps
CPU time 5.54 seconds
Started Mar 07 12:33:11 PM PST 24
Finished Mar 07 12:33:17 PM PST 24
Peak memory 200444 kb
Host smart-a8ddde31-7760-4fce-8005-7d6b96720c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847196959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1847196959
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2495644364
Short name T161
Test name
Test status
Simulation time 180113970 ps
CPU time 1.22 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 200276 kb
Host smart-3a98edc5-8f22-47b8-a9b6-7e16a853aa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495644364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2495644364
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1168088402
Short name T426
Test name
Test status
Simulation time 121123957 ps
CPU time 1.26 seconds
Started Mar 07 12:33:03 PM PST 24
Finished Mar 07 12:33:04 PM PST 24
Peak memory 200408 kb
Host smart-9efac48f-53c2-4bd8-a1ba-a2b191b6bddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168088402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1168088402
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3154334934
Short name T443
Test name
Test status
Simulation time 2559099338 ps
CPU time 11.36 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:14 PM PST 24
Peak memory 200680 kb
Host smart-bff094c8-8783-44d9-b858-edfd495d7896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154334934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3154334934
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.350404902
Short name T474
Test name
Test status
Simulation time 440362499 ps
CPU time 2.55 seconds
Started Mar 07 12:33:21 PM PST 24
Finished Mar 07 12:33:24 PM PST 24
Peak memory 200272 kb
Host smart-9a63e585-bb6b-46cb-ae92-042117908ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350404902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.350404902
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3048284271
Short name T524
Test name
Test status
Simulation time 104156097 ps
CPU time 0.91 seconds
Started Mar 07 12:33:07 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 200328 kb
Host smart-96c84a22-bd90-4429-8dcc-ddd820774e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048284271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3048284271
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1264423903
Short name T398
Test name
Test status
Simulation time 66400460 ps
CPU time 0.74 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:33:19 PM PST 24
Peak memory 200184 kb
Host smart-7f5b3fd9-0784-4f4d-a6f3-6d3d89bec518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264423903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1264423903
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1344889083
Short name T515
Test name
Test status
Simulation time 2367168506 ps
CPU time 7.99 seconds
Started Mar 07 12:33:13 PM PST 24
Finished Mar 07 12:33:21 PM PST 24
Peak memory 217780 kb
Host smart-ec83a97e-f6b3-4db7-856d-8d5b8e8dd070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344889083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1344889083
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1096946334
Short name T54
Test name
Test status
Simulation time 244998397 ps
CPU time 1.12 seconds
Started Mar 07 12:33:08 PM PST 24
Finished Mar 07 12:33:09 PM PST 24
Peak memory 217128 kb
Host smart-186edce9-21b7-4332-b04b-7ca31652f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096946334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1096946334
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.33764963
Short name T458
Test name
Test status
Simulation time 112066057 ps
CPU time 0.81 seconds
Started Mar 07 12:33:10 PM PST 24
Finished Mar 07 12:33:11 PM PST 24
Peak memory 200132 kb
Host smart-eb5cc3c5-1f87-4081-baea-0a39fbb3f2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33764963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.33764963
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.788846825
Short name T404
Test name
Test status
Simulation time 799536323 ps
CPU time 3.95 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:33:20 PM PST 24
Peak memory 200428 kb
Host smart-267fe7c7-8b6d-4cde-b893-a8a40014bf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788846825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.788846825
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3869900201
Short name T47
Test name
Test status
Simulation time 139992099 ps
CPU time 1.11 seconds
Started Mar 07 12:33:19 PM PST 24
Finished Mar 07 12:33:20 PM PST 24
Peak memory 200336 kb
Host smart-d451065a-4c10-496d-be26-2f5f68391df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869900201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3869900201
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.831829232
Short name T225
Test name
Test status
Simulation time 206370634 ps
CPU time 1.4 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:33:21 PM PST 24
Peak memory 200400 kb
Host smart-57f50e76-4162-46ad-8ded-d381a257af99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831829232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.831829232
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1197742743
Short name T271
Test name
Test status
Simulation time 5176034986 ps
CPU time 21.76 seconds
Started Mar 07 12:33:13 PM PST 24
Finished Mar 07 12:33:35 PM PST 24
Peak memory 200552 kb
Host smart-c5576a4b-b584-442d-b6c0-594e781b9537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197742743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1197742743
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1150423716
Short name T530
Test name
Test status
Simulation time 146410576 ps
CPU time 1.76 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:33:20 PM PST 24
Peak memory 200208 kb
Host smart-55ce6974-5fd9-456e-877e-f1d672d0dd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150423716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1150423716
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.827901198
Short name T308
Test name
Test status
Simulation time 156154632 ps
CPU time 1.19 seconds
Started Mar 07 12:33:05 PM PST 24
Finished Mar 07 12:33:07 PM PST 24
Peak memory 200268 kb
Host smart-af12cdf9-3302-411e-8cf1-5dced68430bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827901198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.827901198
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1250510414
Short name T359
Test name
Test status
Simulation time 59366172 ps
CPU time 0.71 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:33:19 PM PST 24
Peak memory 200248 kb
Host smart-e6f0e3ed-a77e-4361-9848-95c2d8b10ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250510414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1250510414
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.660315867
Short name T27
Test name
Test status
Simulation time 1889292049 ps
CPU time 7.28 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:33:23 PM PST 24
Peak memory 216984 kb
Host smart-d61702f6-6aa1-434d-a1f5-d622d5c33709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660315867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.660315867
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2982981192
Short name T488
Test name
Test status
Simulation time 244237336 ps
CPU time 1.05 seconds
Started Mar 07 12:33:12 PM PST 24
Finished Mar 07 12:33:13 PM PST 24
Peak memory 217120 kb
Host smart-e78e677f-73d3-4e09-9692-3e98fe6218bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982981192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2982981192
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2939169990
Short name T19
Test name
Test status
Simulation time 212248440 ps
CPU time 0.97 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:33:16 PM PST 24
Peak memory 200120 kb
Host smart-5d85848a-3f38-416e-9fae-beb9a2ded261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939169990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2939169990
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1537438507
Short name T517
Test name
Test status
Simulation time 860450225 ps
CPU time 4.69 seconds
Started Mar 07 12:33:02 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 200620 kb
Host smart-42d9b35d-6087-43b3-8288-cf6ff91ca304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537438507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1537438507
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2685141945
Short name T441
Test name
Test status
Simulation time 154873125 ps
CPU time 1.16 seconds
Started Mar 07 12:33:04 PM PST 24
Finished Mar 07 12:33:05 PM PST 24
Peak memory 200332 kb
Host smart-0ef35ee2-fc86-404d-83d7-f85eecdef9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685141945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2685141945
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2153892688
Short name T284
Test name
Test status
Simulation time 198495635 ps
CPU time 1.5 seconds
Started Mar 07 12:33:01 PM PST 24
Finished Mar 07 12:33:03 PM PST 24
Peak memory 200460 kb
Host smart-94353a05-e879-4738-ac40-63531b174475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153892688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2153892688
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2974576155
Short name T370
Test name
Test status
Simulation time 10637533008 ps
CPU time 34.9 seconds
Started Mar 07 12:33:05 PM PST 24
Finished Mar 07 12:33:40 PM PST 24
Peak memory 200520 kb
Host smart-4f87f51f-19fe-4954-94d5-d25e74ff35f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974576155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2974576155
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2910809898
Short name T293
Test name
Test status
Simulation time 123026967 ps
CPU time 1.59 seconds
Started Mar 07 12:33:06 PM PST 24
Finished Mar 07 12:33:08 PM PST 24
Peak memory 200172 kb
Host smart-62e0b464-300c-49ef-a183-cc86af222121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910809898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2910809898
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1866988950
Short name T290
Test name
Test status
Simulation time 189623152 ps
CPU time 1.2 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:33:21 PM PST 24
Peak memory 200356 kb
Host smart-c50ac7db-a435-4161-baaf-87a260623779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866988950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1866988950
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1010135166
Short name T371
Test name
Test status
Simulation time 85986638 ps
CPU time 0.84 seconds
Started Mar 07 12:33:14 PM PST 24
Finished Mar 07 12:33:15 PM PST 24
Peak memory 200236 kb
Host smart-d4e163fe-128b-41be-a8cb-e1157a66e608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010135166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1010135166
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.714451423
Short name T410
Test name
Test status
Simulation time 1224211490 ps
CPU time 5.65 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:33:24 PM PST 24
Peak memory 216512 kb
Host smart-5f21cdad-2dbd-415a-a269-ffe82f51d8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714451423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.714451423
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3468194165
Short name T520
Test name
Test status
Simulation time 244946759 ps
CPU time 1.15 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:33:16 PM PST 24
Peak memory 217116 kb
Host smart-32e8be25-b631-4f2e-8dc8-ab82ab41383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468194165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3468194165
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3386317492
Short name T331
Test name
Test status
Simulation time 141815613 ps
CPU time 0.8 seconds
Started Mar 07 12:33:13 PM PST 24
Finished Mar 07 12:33:14 PM PST 24
Peak memory 200140 kb
Host smart-b7c35ee8-4e46-4e94-9c0b-f0d2ce5ac47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386317492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3386317492
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1636141674
Short name T299
Test name
Test status
Simulation time 1558537384 ps
CPU time 6.37 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:33:32 PM PST 24
Peak memory 200476 kb
Host smart-582cc663-78be-4cfe-80df-d92484d51526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636141674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1636141674
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4237724530
Short name T364
Test name
Test status
Simulation time 179705204 ps
CPU time 1.22 seconds
Started Mar 07 12:33:11 PM PST 24
Finished Mar 07 12:33:13 PM PST 24
Peak memory 200368 kb
Host smart-27de6f7f-f96a-48e8-a771-96f60a86bc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237724530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4237724530
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.223677513
Short name T442
Test name
Test status
Simulation time 120774031 ps
CPU time 1.23 seconds
Started Mar 07 12:33:17 PM PST 24
Finished Mar 07 12:33:18 PM PST 24
Peak memory 200572 kb
Host smart-a6665563-7e28-4c10-a6ca-8a483d2f6696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223677513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.223677513
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3168298010
Short name T115
Test name
Test status
Simulation time 2920711139 ps
CPU time 11.35 seconds
Started Mar 07 12:33:30 PM PST 24
Finished Mar 07 12:33:42 PM PST 24
Peak memory 210092 kb
Host smart-6b9a4e90-bffa-40ac-b684-ccff75e71e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168298010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3168298010
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.917913597
Short name T75
Test name
Test status
Simulation time 355491710 ps
CPU time 2.18 seconds
Started Mar 07 12:33:12 PM PST 24
Finished Mar 07 12:33:14 PM PST 24
Peak memory 200404 kb
Host smart-fb720443-db6c-4d8a-9b7b-7d769b6ed75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917913597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.917913597
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3715426580
Short name T353
Test name
Test status
Simulation time 299498617 ps
CPU time 1.62 seconds
Started Mar 07 12:33:15 PM PST 24
Finished Mar 07 12:33:17 PM PST 24
Peak memory 200420 kb
Host smart-a296dc41-3251-446d-b5b8-ab05523945b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715426580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3715426580
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1292944545
Short name T202
Test name
Test status
Simulation time 70237184 ps
CPU time 0.82 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:33:17 PM PST 24
Peak memory 200276 kb
Host smart-698a83b7-4370-47b6-b374-2c8c254c8bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292944545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1292944545
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.590726444
Short name T63
Test name
Test status
Simulation time 1226838781 ps
CPU time 5.31 seconds
Started Mar 07 12:33:24 PM PST 24
Finished Mar 07 12:33:29 PM PST 24
Peak memory 217612 kb
Host smart-2e73d59a-b733-4155-a596-3931c7d60ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590726444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.590726444
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1812162875
Short name T295
Test name
Test status
Simulation time 244818671 ps
CPU time 1.07 seconds
Started Mar 07 12:33:14 PM PST 24
Finished Mar 07 12:33:15 PM PST 24
Peak memory 217220 kb
Host smart-66cca1fd-f896-476d-92b6-ea5a8e9ae8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812162875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1812162875
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.460638151
Short name T265
Test name
Test status
Simulation time 189316173 ps
CPU time 0.83 seconds
Started Mar 07 12:33:16 PM PST 24
Finished Mar 07 12:33:17 PM PST 24
Peak memory 200072 kb
Host smart-5f98b224-b1e1-4080-afdd-397f14881a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460638151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.460638151
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3793873204
Short name T199
Test name
Test status
Simulation time 932369029 ps
CPU time 4.51 seconds
Started Mar 07 12:33:23 PM PST 24
Finished Mar 07 12:33:28 PM PST 24
Peak memory 200460 kb
Host smart-28fe8217-7db8-474d-a678-59c387f0aad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793873204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3793873204
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.972169457
Short name T452
Test name
Test status
Simulation time 185160571 ps
CPU time 1.25 seconds
Started Mar 07 12:33:12 PM PST 24
Finished Mar 07 12:33:14 PM PST 24
Peak memory 200332 kb
Host smart-26bb1d45-129b-4905-a1f9-752cffa866b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972169457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.972169457
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1773067966
Short name T203
Test name
Test status
Simulation time 256868242 ps
CPU time 1.5 seconds
Started Mar 07 12:33:22 PM PST 24
Finished Mar 07 12:33:24 PM PST 24
Peak memory 200408 kb
Host smart-d32fb4b9-b170-45c6-8a6b-c1efeb3e6611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773067966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1773067966
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3413005171
Short name T296
Test name
Test status
Simulation time 3634890785 ps
CPU time 13.58 seconds
Started Mar 07 12:33:25 PM PST 24
Finished Mar 07 12:33:39 PM PST 24
Peak memory 200572 kb
Host smart-a2cd0f9c-a660-4b05-be4e-9ca811d59c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413005171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3413005171
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.645396126
Short name T159
Test name
Test status
Simulation time 106695848 ps
CPU time 1.42 seconds
Started Mar 07 12:33:18 PM PST 24
Finished Mar 07 12:33:20 PM PST 24
Peak memory 200288 kb
Host smart-670692d1-7629-4818-b7cb-b81971f44f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645396126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.645396126
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2558333945
Short name T80
Test name
Test status
Simulation time 131739627 ps
CPU time 1.03 seconds
Started Mar 07 12:33:20 PM PST 24
Finished Mar 07 12:33:21 PM PST 24
Peak memory 200300 kb
Host smart-cbe24474-ace5-4611-a56f-6bf47b645103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558333945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2558333945
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3895247247
Short name T527
Test name
Test status
Simulation time 79118448 ps
CPU time 0.87 seconds
Started Mar 07 12:32:07 PM PST 24
Finished Mar 07 12:32:08 PM PST 24
Peak memory 200152 kb
Host smart-5dc8ba05-d42d-4fd1-b18d-9f849b484b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895247247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3895247247
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2494844644
Short name T294
Test name
Test status
Simulation time 2336848748 ps
CPU time 7.96 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 218152 kb
Host smart-39d130aa-d4d8-433e-b898-bd1dd1de2c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494844644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2494844644
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1104583438
Short name T490
Test name
Test status
Simulation time 243500010 ps
CPU time 1.05 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 216976 kb
Host smart-b7afc135-7a3f-4591-8450-751c50c01b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104583438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1104583438
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2765504844
Short name T514
Test name
Test status
Simulation time 203034585 ps
CPU time 0.95 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:09 PM PST 24
Peak memory 200020 kb
Host smart-f3d50eca-5a83-40cf-b3ac-25c76f91a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765504844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2765504844
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2781664522
Short name T326
Test name
Test status
Simulation time 1896796344 ps
CPU time 6.95 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 200572 kb
Host smart-651dfcde-d8ed-4293-8e49-36dcf7844e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781664522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2781664522
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1668898011
Short name T222
Test name
Test status
Simulation time 142201292 ps
CPU time 1.1 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200324 kb
Host smart-f1716122-33bb-4b89-9359-f9b91ce67685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668898011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1668898011
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3967741989
Short name T536
Test name
Test status
Simulation time 117121480 ps
CPU time 1.16 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200348 kb
Host smart-f2458015-95c2-4bfa-bcd9-6b99df55038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967741989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3967741989
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1587152708
Short name T461
Test name
Test status
Simulation time 2201960111 ps
CPU time 8.34 seconds
Started Mar 07 12:32:11 PM PST 24
Finished Mar 07 12:32:19 PM PST 24
Peak memory 200548 kb
Host smart-b64807db-9304-49f2-ba2d-9ab40e0ea8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587152708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1587152708
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1006465932
Short name T334
Test name
Test status
Simulation time 138738766 ps
CPU time 1.68 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:12 PM PST 24
Peak memory 208448 kb
Host smart-ea651ba3-96f4-450e-9b1d-d28dd4337540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006465932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1006465932
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1259618583
Short name T139
Test name
Test status
Simulation time 186329757 ps
CPU time 1.2 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200224 kb
Host smart-1c227769-ba7a-4fc3-8a56-8d1e2fa4f665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259618583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1259618583
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2938173660
Short name T450
Test name
Test status
Simulation time 76866972 ps
CPU time 0.8 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 200152 kb
Host smart-fcee8423-45c0-4906-9d7a-cc880bd6349e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938173660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2938173660
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.4282168315
Short name T399
Test name
Test status
Simulation time 1898000783 ps
CPU time 6.86 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 220768 kb
Host smart-415484ef-0e68-4ce1-8670-84e2fcbc969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282168315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.4282168315
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3407296878
Short name T196
Test name
Test status
Simulation time 243823965 ps
CPU time 1.13 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 216972 kb
Host smart-19e1fa2a-38b9-466d-8789-6c9bbb93468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407296878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3407296878
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2708598626
Short name T187
Test name
Test status
Simulation time 210499903 ps
CPU time 0.87 seconds
Started Mar 07 12:32:09 PM PST 24
Finished Mar 07 12:32:10 PM PST 24
Peak memory 200036 kb
Host smart-7b58a26c-a182-462a-99d3-1473fe2ee63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708598626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2708598626
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1585617136
Short name T372
Test name
Test status
Simulation time 1699093164 ps
CPU time 6.11 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200388 kb
Host smart-fb2f1da1-4d31-469d-9cfd-65d6df98682f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585617136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1585617136
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.981694834
Short name T429
Test name
Test status
Simulation time 173122665 ps
CPU time 1.22 seconds
Started Mar 07 12:32:08 PM PST 24
Finished Mar 07 12:32:09 PM PST 24
Peak memory 200252 kb
Host smart-4950950c-b179-410b-9424-ec527494d8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981694834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.981694834
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1291986782
Short name T201
Test name
Test status
Simulation time 199110639 ps
CPU time 1.4 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200324 kb
Host smart-c9644a3a-09a3-428a-aa8d-fb22687e3ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291986782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1291986782
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1723048932
Short name T120
Test name
Test status
Simulation time 11972587799 ps
CPU time 40.44 seconds
Started Mar 07 12:32:07 PM PST 24
Finished Mar 07 12:32:48 PM PST 24
Peak memory 200556 kb
Host smart-6fcdcc03-c572-4989-b1e7-8128d3fe6398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723048932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1723048932
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1016411638
Short name T248
Test name
Test status
Simulation time 117401021 ps
CPU time 1.45 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 200156 kb
Host smart-4e5d80f5-ca89-4576-94c5-574a05d63121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016411638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1016411638
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1320908781
Short name T422
Test name
Test status
Simulation time 103236356 ps
CPU time 1 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 200316 kb
Host smart-d848663c-6855-4ba3-9476-1c5889bdf47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320908781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1320908781
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.483709773
Short name T152
Test name
Test status
Simulation time 62736642 ps
CPU time 0.76 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 200092 kb
Host smart-b3657201-3da6-4a38-8cb3-fbfae5944dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483709773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.483709773
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3066132148
Short name T537
Test name
Test status
Simulation time 2364464112 ps
CPU time 8.44 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:20 PM PST 24
Peak memory 221808 kb
Host smart-8ee266e2-65ac-4680-b4ac-bdc6b77c2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066132148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3066132148
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.4083002099
Short name T455
Test name
Test status
Simulation time 244159982 ps
CPU time 1.09 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:14 PM PST 24
Peak memory 217064 kb
Host smart-3f0004d1-df8f-4a93-ac45-eff20cbd1ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083002099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.4083002099
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1474399099
Short name T309
Test name
Test status
Simulation time 158077481 ps
CPU time 0.83 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:14 PM PST 24
Peak memory 199928 kb
Host smart-cfce899a-8ada-4956-a3d0-b3e276078181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474399099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1474399099
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.699012627
Short name T378
Test name
Test status
Simulation time 1771846602 ps
CPU time 6.76 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:19 PM PST 24
Peak memory 200404 kb
Host smart-bfc014db-3d90-4af8-89cc-ddda6bfac32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699012627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.699012627
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3441393492
Short name T362
Test name
Test status
Simulation time 138903425 ps
CPU time 1.12 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 200160 kb
Host smart-8cf4eb69-ca1e-4927-bdcd-632433aa45ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441393492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3441393492
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3582470702
Short name T176
Test name
Test status
Simulation time 120415537 ps
CPU time 1.24 seconds
Started Mar 07 12:32:13 PM PST 24
Finished Mar 07 12:32:14 PM PST 24
Peak memory 200436 kb
Host smart-cbb2bf60-44cd-4249-b0ec-0631d2d18000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582470702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3582470702
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.659224002
Short name T374
Test name
Test status
Simulation time 3655016796 ps
CPU time 16.29 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:32 PM PST 24
Peak memory 208636 kb
Host smart-69864396-f5de-428f-8296-2a6a4e0e7b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659224002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.659224002
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.111573350
Short name T397
Test name
Test status
Simulation time 343948775 ps
CPU time 2.32 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 200196 kb
Host smart-ba3f5189-d803-4df3-b9e7-81ed88be0a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111573350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.111573350
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.968807286
Short name T354
Test name
Test status
Simulation time 107606713 ps
CPU time 0.93 seconds
Started Mar 07 12:32:12 PM PST 24
Finished Mar 07 12:32:13 PM PST 24
Peak memory 200212 kb
Host smart-6b41ffde-492d-46fc-a1e7-1a9e99a0cd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968807286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.968807286
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.617022509
Short name T436
Test name
Test status
Simulation time 87867353 ps
CPU time 0.86 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200116 kb
Host smart-8b2c7b14-aae8-40a9-82f9-01ad0b4d70aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617022509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.617022509
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2111919897
Short name T30
Test name
Test status
Simulation time 1232202330 ps
CPU time 6.12 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:23 PM PST 24
Peak memory 216920 kb
Host smart-acf1a7a4-3c73-4714-b3da-e767c3dff2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111919897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2111919897
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.4044036785
Short name T213
Test name
Test status
Simulation time 243856684 ps
CPU time 1.08 seconds
Started Mar 07 12:32:18 PM PST 24
Finished Mar 07 12:32:19 PM PST 24
Peak memory 217084 kb
Host smart-d8c34188-01f2-4112-9ddd-35e8ff34662c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044036785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.4044036785
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.4127265408
Short name T18
Test name
Test status
Simulation time 83774918 ps
CPU time 0.82 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 200024 kb
Host smart-16f86207-c033-445f-b64a-a8262e0f44c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127265408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.4127265408
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.546782231
Short name T473
Test name
Test status
Simulation time 1458635032 ps
CPU time 5.61 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:20 PM PST 24
Peak memory 200368 kb
Host smart-2b12c8bb-9efb-4a15-9e67-b9df32a82fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546782231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.546782231
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3589851486
Short name T541
Test name
Test status
Simulation time 190699035 ps
CPU time 1.22 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200120 kb
Host smart-8ebce63b-c782-43de-873e-0da052653b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589851486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3589851486
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.524310738
Short name T81
Test name
Test status
Simulation time 195900471 ps
CPU time 1.38 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200196 kb
Host smart-78268aec-475c-44c5-a28c-9bef31eb6669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524310738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.524310738
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4062014436
Short name T483
Test name
Test status
Simulation time 9214443807 ps
CPU time 34.86 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:50 PM PST 24
Peak memory 208760 kb
Host smart-61c6292c-837a-494b-b3f3-d279e73bf205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062014436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4062014436
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.869923546
Short name T78
Test name
Test status
Simulation time 114856855 ps
CPU time 1.61 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:17 PM PST 24
Peak memory 200108 kb
Host smart-231bad37-4812-40f0-8bc8-22f62c46d255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869923546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.869923546
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2287388855
Short name T36
Test name
Test status
Simulation time 136980581 ps
CPU time 1.17 seconds
Started Mar 07 12:32:18 PM PST 24
Finished Mar 07 12:32:20 PM PST 24
Peak memory 200216 kb
Host smart-236bfb40-344b-47ad-8dc6-514431373b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287388855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2287388855
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3601472992
Short name T218
Test name
Test status
Simulation time 63288330 ps
CPU time 0.73 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 200072 kb
Host smart-c2bc5ce2-e68c-41dc-ae9e-5e874bee4920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601472992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3601472992
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4119040101
Short name T529
Test name
Test status
Simulation time 2168761604 ps
CPU time 7.66 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:23 PM PST 24
Peak memory 217772 kb
Host smart-63c0baa3-dc86-42aa-9533-10e1aacf3f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119040101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4119040101
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.675875802
Short name T22
Test name
Test status
Simulation time 246207925 ps
CPU time 1.04 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:15 PM PST 24
Peak memory 217008 kb
Host smart-510897fd-eaa8-462a-98e8-a2b36a87f948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675875802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.675875802
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1464231874
Short name T14
Test name
Test status
Simulation time 204912080 ps
CPU time 0.97 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:18 PM PST 24
Peak memory 200012 kb
Host smart-e4453228-fca5-44de-818f-0e961d0352a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464231874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1464231874
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3330605032
Short name T41
Test name
Test status
Simulation time 1397793993 ps
CPU time 5.53 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:22 PM PST 24
Peak memory 200416 kb
Host smart-2b7bfca7-0b1f-4ccf-a118-ef7bb2ebf12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330605032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3330605032
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2289493114
Short name T317
Test name
Test status
Simulation time 99530903 ps
CPU time 1 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 200356 kb
Host smart-c21afba1-d4ee-458c-a0ca-8fb48714b51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289493114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2289493114
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4121690872
Short name T318
Test name
Test status
Simulation time 111986894 ps
CPU time 1.27 seconds
Started Mar 07 12:32:10 PM PST 24
Finished Mar 07 12:32:11 PM PST 24
Peak memory 200276 kb
Host smart-a53d08ee-1ce7-457b-8d17-0c6a69314839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121690872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4121690872
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.810362341
Short name T319
Test name
Test status
Simulation time 6021073611 ps
CPU time 19.4 seconds
Started Mar 07 12:32:14 PM PST 24
Finished Mar 07 12:32:34 PM PST 24
Peak memory 200500 kb
Host smart-1cf94f7a-3cb1-4b5d-9219-72d1c94c33ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810362341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.810362341
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.141666220
Short name T37
Test name
Test status
Simulation time 356441202 ps
CPU time 2.35 seconds
Started Mar 07 12:32:16 PM PST 24
Finished Mar 07 12:32:19 PM PST 24
Peak memory 200160 kb
Host smart-3c5c4592-b553-475f-b448-a1a4478faeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141666220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.141666220
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1689376020
Short name T147
Test name
Test status
Simulation time 153860541 ps
CPU time 1.19 seconds
Started Mar 07 12:32:15 PM PST 24
Finished Mar 07 12:32:16 PM PST 24
Peak memory 200348 kb
Host smart-e2c553a2-a4f5-4949-b3dd-6d95364ca847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689376020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1689376020
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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