Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7697

1

T3

60

T5

14

T7

240

auto[1]

10759

1

T3

60

T5

87

T6

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5729	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6209	1			T1	1		T2	1		T3	40
reset_info_cp[2]	2851	1			T3	21		T5	19		T6	1
reset_info_cp[4]	3780	1			T3	30		T5	18		T6	1
reset_info_cp[8]	117	1			T3	1		T5	1		T7	1
reset_info_cp[16]	90	1			T3	1		T5	1		T7	2
reset_info_cp[32]	98	1			T7	3		T8	2		T38	2
reset_info_cp[64]	111	1			T8	1		T12	1		T28	1
reset_info_cp[128]	91	1			T5	2		T7	2		T40	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2946	1			T3	20		T5	14		T7	74
reset_info_cp[1]	auto[1]	2643	1			T3	19		T5	12		T6	1
reset_info_cp[2]	auto[0]	832	1			T3	10		T7	36		T25	2
reset_info_cp[2]	auto[1]	2019	1			T3	11		T5	19		T6	1
reset_info_cp[4]	auto[0]	1334	1			T3	12		T7	58		T25	2
reset_info_cp[4]	auto[1]	2446	1			T3	18		T5	18		T6	1
reset_info_cp[8]	auto[0]	43	1			T14	1		T148	1		T118	1
reset_info_cp[8]	auto[1]	74	1			T3	1		T5	1		T7	1
reset_info_cp[16]	auto[0]	35	1			T7	2		T14	1		T110	1
reset_info_cp[16]	auto[1]	55	1			T3	1		T5	1		T110	1
reset_info_cp[32]	auto[0]	36	1			T8	2		T38	1		T65	1
reset_info_cp[32]	auto[1]	62	1			T7	3		T38	1		T106	1
reset_info_cp[64]	auto[0]	43	1			T8	1		T12	1		T82	3
reset_info_cp[64]	auto[1]	68	1			T28	1		T38	3		T47	1
reset_info_cp[128]	auto[0]	36	1			T115	1		T149	2		T82	1
reset_info_cp[128]	auto[1]	55	1			T5	2		T7	2		T40	1