Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T541 /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2031608223 Mar 10 01:25:08 PM PDT 24 Mar 10 01:25:09 PM PDT 24 125151435 ps
T542 /workspace/coverage/default/7.rstmgr_sw_rst.1453699940 Mar 10 01:24:48 PM PDT 24 Mar 10 01:24:51 PM PDT 24 472319139 ps
T543 /workspace/coverage/default/30.rstmgr_smoke.3229974811 Mar 10 01:25:25 PM PDT 24 Mar 10 01:25:26 PM PDT 24 261209522 ps
T544 /workspace/coverage/default/23.rstmgr_smoke.3034752494 Mar 10 01:25:13 PM PDT 24 Mar 10 01:25:14 PM PDT 24 123993464 ps
T545 /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1650608478 Mar 10 01:25:18 PM PDT 24 Mar 10 01:25:19 PM PDT 24 108569183 ps
T67 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3562550761 Mar 10 01:11:46 PM PDT 24 Mar 10 01:11:47 PM PDT 24 119533461 ps
T72 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1865929377 Mar 10 01:11:55 PM PDT 24 Mar 10 01:11:56 PM PDT 24 104824329 ps
T73 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1853004476 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:46 PM PDT 24 215080050 ps
T68 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1345654026 Mar 10 01:11:55 PM PDT 24 Mar 10 01:11:56 PM PDT 24 59320093 ps
T69 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3049170506 Mar 10 01:11:42 PM PDT 24 Mar 10 01:11:42 PM PDT 24 78330436 ps
T70 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.284259534 Mar 10 01:11:55 PM PDT 24 Mar 10 01:11:58 PM PDT 24 963124582 ps
T71 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2112554745 Mar 10 01:11:52 PM PDT 24 Mar 10 01:11:53 PM PDT 24 196363662 ps
T90 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3275929105 Mar 10 01:11:56 PM PDT 24 Mar 10 01:11:57 PM PDT 24 105444504 ps
T87 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1877111183 Mar 10 01:11:49 PM PDT 24 Mar 10 01:11:53 PM PDT 24 498991999 ps
T91 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.173914263 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:46 PM PDT 24 130815671 ps
T114 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1000878597 Mar 10 01:11:56 PM PDT 24 Mar 10 01:11:58 PM PDT 24 157988691 ps
T95 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1135695632 Mar 10 01:12:01 PM PDT 24 Mar 10 01:12:04 PM PDT 24 425113788 ps
T93 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3767731625 Mar 10 01:11:43 PM PDT 24 Mar 10 01:11:46 PM PDT 24 239955969 ps
T92 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.840080682 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:51 PM PDT 24 490664786 ps
T128 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1590306874 Mar 10 01:11:47 PM PDT 24 Mar 10 01:11:48 PM PDT 24 57608460 ps
T129 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3985276733 Mar 10 01:11:57 PM PDT 24 Mar 10 01:11:58 PM PDT 24 143866552 ps
T546 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.342088476 Mar 10 01:11:54 PM PDT 24 Mar 10 01:11:56 PM PDT 24 144789195 ps
T94 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1338532198 Mar 10 01:11:55 PM PDT 24 Mar 10 01:12:00 PM PDT 24 649669778 ps
T547 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3006596719 Mar 10 01:11:57 PM PDT 24 Mar 10 01:11:58 PM PDT 24 213323082 ps
T130 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4074460990 Mar 10 01:11:50 PM PDT 24 Mar 10 01:11:51 PM PDT 24 161071064 ps
T99 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2046018289 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:50 PM PDT 24 686419372 ps
T548 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3996610980 Mar 10 01:11:48 PM PDT 24 Mar 10 01:11:50 PM PDT 24 131985938 ps
T131 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1655477408 Mar 10 01:11:58 PM PDT 24 Mar 10 01:12:00 PM PDT 24 129610333 ps
T103 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1990513289 Mar 10 01:11:51 PM PDT 24 Mar 10 01:11:53 PM PDT 24 128571811 ps
T549 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.611894827 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:50 PM PDT 24 1184744752 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3340596044 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:49 PM PDT 24 272489020 ps
T551 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1921496316 Mar 10 01:11:48 PM PDT 24 Mar 10 01:11:51 PM PDT 24 207982090 ps
T132 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.801167782 Mar 10 01:11:43 PM PDT 24 Mar 10 01:11:44 PM PDT 24 87576344 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2753089064 Mar 10 01:11:47 PM PDT 24 Mar 10 01:11:49 PM PDT 24 121955769 ps
T104 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3481632143 Mar 10 01:11:55 PM PDT 24 Mar 10 01:11:56 PM PDT 24 100732142 ps
T88 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.971473745 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:46 PM PDT 24 516775491 ps
T89 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2560707133 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:49 PM PDT 24 1087742791 ps
T553 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3157762893 Mar 10 01:11:57 PM PDT 24 Mar 10 01:11:59 PM PDT 24 417869005 ps
T144 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3177974920 Mar 10 01:11:48 PM PDT 24 Mar 10 01:11:50 PM PDT 24 501540102 ps
T133 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1238635480 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:46 PM PDT 24 133359892 ps
T134 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.314699033 Mar 10 01:11:43 PM PDT 24 Mar 10 01:11:45 PM PDT 24 133900517 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2592568121 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:47 PM PDT 24 254652388 ps
T135 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2818834999 Mar 10 01:11:50 PM PDT 24 Mar 10 01:11:51 PM PDT 24 93066323 ps
T555 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1848447293 Mar 10 01:11:49 PM PDT 24 Mar 10 01:11:52 PM PDT 24 203327507 ps
T136 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3110290963 Mar 10 01:11:48 PM PDT 24 Mar 10 01:11:49 PM PDT 24 67608512 ps
T556 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1448014776 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:46 PM PDT 24 176647819 ps
T557 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3201213063 Mar 10 01:11:43 PM PDT 24 Mar 10 01:11:44 PM PDT 24 73694430 ps
T558 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1413962976 Mar 10 01:11:54 PM PDT 24 Mar 10 01:11:56 PM PDT 24 182958330 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4258659889 Mar 10 01:11:55 PM PDT 24 Mar 10 01:11:57 PM PDT 24 173151723 ps
T560 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2148089506 Mar 10 01:11:53 PM PDT 24 Mar 10 01:11:54 PM PDT 24 105326124 ps
T561 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1820327019 Mar 10 01:11:54 PM PDT 24 Mar 10 01:11:58 PM PDT 24 572452500 ps
T562 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2888577097 Mar 10 01:12:00 PM PDT 24 Mar 10 01:12:01 PM PDT 24 160497110 ps
T563 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4253833576 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:47 PM PDT 24 157620031 ps
T564 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2990614746 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:47 PM PDT 24 72454035 ps
T565 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2855674549 Mar 10 01:11:50 PM PDT 24 Mar 10 01:11:51 PM PDT 24 118861076 ps
T566 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3103486900 Mar 10 01:11:51 PM PDT 24 Mar 10 01:11:53 PM PDT 24 135448096 ps
T567 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1638540689 Mar 10 01:11:50 PM PDT 24 Mar 10 01:11:51 PM PDT 24 88452514 ps
T568 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.344361061 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:47 PM PDT 24 172822055 ps
T145 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1893061710 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:47 PM PDT 24 469657163 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3541086957 Mar 10 01:11:46 PM PDT 24 Mar 10 01:11:48 PM PDT 24 90076402 ps
T100 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1812739634 Mar 10 01:11:59 PM PDT 24 Mar 10 01:12:01 PM PDT 24 417040794 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.19184542 Mar 10 01:11:41 PM PDT 24 Mar 10 01:11:43 PM PDT 24 212704057 ps
T120 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.773709643 Mar 10 01:11:45 PM PDT 24 Mar 10 01:11:46 PM PDT 24 85567301 ps
T571 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2852929124 Mar 10 01:11:49 PM PDT 24 Mar 10 01:11:51 PM PDT 24 498710177 ps
T572 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3059590550 Mar 10 01:11:59 PM PDT 24 Mar 10 01:12:00 PM PDT 24 99274764 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4193475133 Mar 10 01:11:46 PM PDT 24 Mar 10 01:11:47 PM PDT 24 223912054 ps
T574 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2099013227 Mar 10 01:12:01 PM PDT 24 Mar 10 01:12:03 PM PDT 24 266998212 ps
T147 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1136355327 Mar 10 01:11:47 PM PDT 24 Mar 10 01:11:50 PM PDT 24 867695896 ps
T575 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.515618231 Mar 10 01:11:49 PM PDT 24 Mar 10 01:11:51 PM PDT 24 490621029 ps
T576 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1234579907 Mar 10 01:12:01 PM PDT 24 Mar 10 01:12:02 PM PDT 24 80570789 ps
T101 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4128078696 Mar 10 01:11:57 PM PDT 24 Mar 10 01:11:59 PM PDT 24 462540493 ps
T577 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1954491374 Mar 10 01:12:04 PM PDT 24 Mar 10 01:12:05 PM PDT 24 137950362 ps
T578 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2103112293 Mar 10 01:12:00 PM PDT 24 Mar 10 01:12:01 PM PDT 24 81997204 ps
T579 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.722259955 Mar 10 01:11:49 PM PDT 24 Mar 10 01:11:52 PM PDT 24 795578629 ps
T580 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3130353933 Mar 10 01:11:56 PM PDT 24 Mar 10 01:11:58 PM PDT 24 230318705 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2506370912 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:45 PM PDT 24 120113559 ps
T96 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1166043664 Mar 10 01:11:56 PM PDT 24 Mar 10 01:11:58 PM PDT 24 478448304 ps
T582 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4040650597 Mar 10 01:11:54 PM PDT 24 Mar 10 01:11:55 PM PDT 24 74775387 ps
T583 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3744873162 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:45 PM PDT 24 85403069 ps
T146 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1745727426 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:47 PM PDT 24 782703151 ps
T584 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.274798943 Mar 10 01:11:49 PM PDT 24 Mar 10 01:11:50 PM PDT 24 177487515 ps
T585 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2005449099 Mar 10 01:11:43 PM PDT 24 Mar 10 01:11:46 PM PDT 24 299700395 ps
T97 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3904711211 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:46 PM PDT 24 478914731 ps
T586 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.268562448 Mar 10 01:12:02 PM PDT 24 Mar 10 01:12:04 PM PDT 24 209782383 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1002839536 Mar 10 01:11:43 PM PDT 24 Mar 10 01:11:45 PM PDT 24 355735591 ps
T588 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.794853744 Mar 10 01:11:51 PM PDT 24 Mar 10 01:11:52 PM PDT 24 66358568 ps
T589 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2204987753 Mar 10 01:11:56 PM PDT 24 Mar 10 01:11:57 PM PDT 24 70238237 ps
T590 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1090403583 Mar 10 01:11:59 PM PDT 24 Mar 10 01:12:01 PM PDT 24 206272706 ps
T591 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.947983960 Mar 10 01:11:58 PM PDT 24 Mar 10 01:12:00 PM PDT 24 477200311 ps
T592 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3491106419 Mar 10 01:12:01 PM PDT 24 Mar 10 01:12:02 PM PDT 24 63731452 ps
T593 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2396169947 Mar 10 01:11:40 PM PDT 24 Mar 10 01:11:41 PM PDT 24 59107994 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1732846777 Mar 10 01:11:43 PM PDT 24 Mar 10 01:11:45 PM PDT 24 194486199 ps
T595 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2527197503 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:48 PM PDT 24 268208998 ps
T596 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1555559356 Mar 10 01:12:00 PM PDT 24 Mar 10 01:12:02 PM PDT 24 89193729 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4090748974 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:45 PM PDT 24 121623765 ps
T598 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2904138101 Mar 10 01:11:54 PM PDT 24 Mar 10 01:11:57 PM PDT 24 775749811 ps
T599 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2277751656 Mar 10 01:11:51 PM PDT 24 Mar 10 01:11:52 PM PDT 24 140529004 ps
T600 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1667711402 Mar 10 01:12:00 PM PDT 24 Mar 10 01:12:01 PM PDT 24 66857019 ps
T601 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3136792492 Mar 10 01:12:02 PM PDT 24 Mar 10 01:12:03 PM PDT 24 163164602 ps
T602 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2489696352 Mar 10 01:11:59 PM PDT 24 Mar 10 01:12:00 PM PDT 24 64528308 ps
T603 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3138070993 Mar 10 01:12:01 PM PDT 24 Mar 10 01:12:02 PM PDT 24 134198945 ps
T604 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3925105618 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:46 PM PDT 24 230950885 ps
T605 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2619886700 Mar 10 01:11:42 PM PDT 24 Mar 10 01:11:44 PM PDT 24 138856562 ps
T102 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1146725373 Mar 10 01:11:57 PM PDT 24 Mar 10 01:11:58 PM PDT 24 424152601 ps
T98 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1094149041 Mar 10 01:11:55 PM PDT 24 Mar 10 01:11:58 PM PDT 24 918165769 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1336166653 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:47 PM PDT 24 437737899 ps
T607 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3847502463 Mar 10 01:11:47 PM PDT 24 Mar 10 01:11:49 PM PDT 24 205523285 ps
T608 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.478549041 Mar 10 01:12:00 PM PDT 24 Mar 10 01:12:01 PM PDT 24 55700348 ps
T609 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.516425376 Mar 10 01:11:49 PM PDT 24 Mar 10 01:11:51 PM PDT 24 193615753 ps
T610 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2563929863 Mar 10 01:12:00 PM PDT 24 Mar 10 01:12:01 PM PDT 24 86773488 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3215966437 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:48 PM PDT 24 937880462 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2708198963 Mar 10 01:11:43 PM PDT 24 Mar 10 01:11:53 PM PDT 24 1993829293 ps
T613 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.776091222 Mar 10 01:11:55 PM PDT 24 Mar 10 01:11:57 PM PDT 24 158402352 ps
T614 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.579695265 Mar 10 01:11:55 PM PDT 24 Mar 10 01:11:56 PM PDT 24 189534775 ps
T615 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.821069636 Mar 10 01:11:56 PM PDT 24 Mar 10 01:11:57 PM PDT 24 68356484 ps
T616 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1351008127 Mar 10 01:11:49 PM PDT 24 Mar 10 01:11:50 PM PDT 24 118451482 ps
T617 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2455128276 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:46 PM PDT 24 245066289 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1816389768 Mar 10 01:11:48 PM PDT 24 Mar 10 01:11:49 PM PDT 24 115855610 ps
T619 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2264406947 Mar 10 01:12:00 PM PDT 24 Mar 10 01:12:04 PM PDT 24 518330041 ps
T620 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.91952445 Mar 10 01:11:44 PM PDT 24 Mar 10 01:11:46 PM PDT 24 151902619 ps

Test location /workspace/coverage/default/20.rstmgr_stress_all.1532556699
Short name T3
Test name
Test status
Simulation time 1998955735 ps
CPU time 10.5 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:24 PM PDT 24
Peak memory 209704 kb
Host smart-a5ead95e-cb5b-4895-9453-8d0239c4416c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532556699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1532556699
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3160623522
Short name T4
Test name
Test status
Simulation time 430119569 ps
CPU time 2.63 seconds
Started Mar 10 01:25:16 PM PDT 24
Finished Mar 10 01:25:19 PM PDT 24
Peak memory 200380 kb
Host smart-03c40382-0d6b-4f99-8ea2-1e1265d4fdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160623522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3160623522
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.284259534
Short name T70
Test name
Test status
Simulation time 963124582 ps
CPU time 3.14 seconds
Started Mar 10 01:11:55 PM PDT 24
Finished Mar 10 01:11:58 PM PDT 24
Peak memory 200492 kb
Host smart-842428cf-62f2-4f3f-9ef8-a17e2ccddfd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284259534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.284259534
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1158119027
Short name T77
Test name
Test status
Simulation time 17320879041 ps
CPU time 25.44 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:56 PM PDT 24
Peak memory 216856 kb
Host smart-ebc92700-a87e-4979-b0a6-a1f3f9d4f5c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158119027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1158119027
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3495635952
Short name T5
Test name
Test status
Simulation time 1222410071 ps
CPU time 5.44 seconds
Started Mar 10 01:25:17 PM PDT 24
Finished Mar 10 01:25:23 PM PDT 24
Peak memory 217764 kb
Host smart-f01bb1e0-86bd-494a-80a5-c8ff5e6ec421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495635952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3495635952
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1877111183
Short name T87
Test name
Test status
Simulation time 498991999 ps
CPU time 3.51 seconds
Started Mar 10 01:11:49 PM PDT 24
Finished Mar 10 01:11:53 PM PDT 24
Peak memory 216784 kb
Host smart-ca8dc6ff-ab8a-4541-a906-f8d8f1afd80b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877111183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1877111183
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.590432586
Short name T82
Test name
Test status
Simulation time 279361205 ps
CPU time 1.52 seconds
Started Mar 10 01:25:27 PM PDT 24
Finished Mar 10 01:25:28 PM PDT 24
Peak memory 200520 kb
Host smart-4293ccf6-07ca-4c26-aba2-a09ca0730018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590432586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.590432586
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3740709438
Short name T152
Test name
Test status
Simulation time 70860258 ps
CPU time 0.75 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:20 PM PDT 24
Peak memory 200236 kb
Host smart-4c59ffd3-26e5-4b70-b2ed-cb2c679d3113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740709438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3740709438
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3607764893
Short name T38
Test name
Test status
Simulation time 7080513248 ps
CPU time 22.75 seconds
Started Mar 10 01:25:08 PM PDT 24
Finished Mar 10 01:25:31 PM PDT 24
Peak memory 200572 kb
Host smart-59ee8408-7399-4eda-8aa7-7fccbb57330e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607764893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3607764893
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.721697723
Short name T49
Test name
Test status
Simulation time 147122836 ps
CPU time 1.15 seconds
Started Mar 10 01:24:53 PM PDT 24
Finished Mar 10 01:24:54 PM PDT 24
Peak memory 200420 kb
Host smart-67420f00-d8df-4b92-a124-e9361cb50407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721697723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.721697723
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3095147706
Short name T30
Test name
Test status
Simulation time 1218668038 ps
CPU time 6.19 seconds
Started Mar 10 01:25:34 PM PDT 24
Finished Mar 10 01:25:41 PM PDT 24
Peak memory 221784 kb
Host smart-896357e7-e1b9-4c14-b1de-436206007e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095147706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3095147706
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1745727426
Short name T146
Test name
Test status
Simulation time 782703151 ps
CPU time 2.82 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:47 PM PDT 24
Peak memory 200480 kb
Host smart-f06d3615-e1dc-4300-b683-58b5b99a30f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745727426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1745727426
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3411716725
Short name T39
Test name
Test status
Simulation time 2362138349 ps
CPU time 8.38 seconds
Started Mar 10 01:24:53 PM PDT 24
Finished Mar 10 01:25:01 PM PDT 24
Peak memory 221112 kb
Host smart-eb0d3106-52d7-4268-8125-7eb2b3452803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411716725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3411716725
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.404202377
Short name T115
Test name
Test status
Simulation time 2776845575 ps
CPU time 14.27 seconds
Started Mar 10 01:25:32 PM PDT 24
Finished Mar 10 01:25:47 PM PDT 24
Peak memory 200616 kb
Host smart-cc3155f1-ac2d-4483-a54d-9c5169846854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404202377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.404202377
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1921496316
Short name T551
Test name
Test status
Simulation time 207982090 ps
CPU time 3.15 seconds
Started Mar 10 01:11:48 PM PDT 24
Finished Mar 10 01:11:51 PM PDT 24
Peak memory 208560 kb
Host smart-2391f03b-3f79-485a-905d-4510917ae96f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921496316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1921496316
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.314699033
Short name T134
Test name
Test status
Simulation time 133900517 ps
CPU time 1.14 seconds
Started Mar 10 01:11:43 PM PDT 24
Finished Mar 10 01:11:45 PM PDT 24
Peak memory 200168 kb
Host smart-ffc0604b-49e5-4b21-91f3-340141a15be2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314699033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.314699033
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2217453929
Short name T21
Test name
Test status
Simulation time 226994179 ps
CPU time 1.02 seconds
Started Mar 10 01:24:30 PM PDT 24
Finished Mar 10 01:24:32 PM PDT 24
Peak memory 200200 kb
Host smart-4a60a49e-b3f8-48b8-85f8-02373ac4c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217453929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2217453929
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1094149041
Short name T98
Test name
Test status
Simulation time 918165769 ps
CPU time 3.21 seconds
Started Mar 10 01:11:55 PM PDT 24
Finished Mar 10 01:11:58 PM PDT 24
Peak memory 200448 kb
Host smart-21106874-e2e9-4315-b2a3-d9cabbd43865
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094149041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1094149041
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2592568121
Short name T554
Test name
Test status
Simulation time 254652388 ps
CPU time 1.85 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:47 PM PDT 24
Peak memory 200420 kb
Host smart-c34881c2-c900-454b-ae1d-77f92f40bd06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592568121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
592568121
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.611894827
Short name T549
Test name
Test status
Simulation time 1184744752 ps
CPU time 6.1 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:50 PM PDT 24
Peak memory 200524 kb
Host smart-b7272ef9-8362-4c70-8b2c-9ac49eefaad6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611894827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.611894827
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3744873162
Short name T583
Test name
Test status
Simulation time 85403069 ps
CPU time 0.84 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:45 PM PDT 24
Peak memory 200284 kb
Host smart-281c8a67-066a-4d0d-ade8-9c4dca29beae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744873162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
744873162
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.173914263
Short name T91
Test name
Test status
Simulation time 130815671 ps
CPU time 1.01 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 200184 kb
Host smart-9f164151-7177-4d13-97ed-267e0c607c16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173914263 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.173914263
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2396169947
Short name T593
Test name
Test status
Simulation time 59107994 ps
CPU time 0.75 seconds
Started Mar 10 01:11:40 PM PDT 24
Finished Mar 10 01:11:41 PM PDT 24
Peak memory 200272 kb
Host smart-717ac43f-b1a8-421a-9e45-361b076b60dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396169947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2396169947
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.19184542
Short name T570
Test name
Test status
Simulation time 212704057 ps
CPU time 1.51 seconds
Started Mar 10 01:11:41 PM PDT 24
Finished Mar 10 01:11:43 PM PDT 24
Peak memory 200468 kb
Host smart-a8ebdb7f-cde2-4697-8eaa-743c88e8bdf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19184542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same
_csr_outstanding.19184542
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2619886700
Short name T605
Test name
Test status
Simulation time 138856562 ps
CPU time 2.1 seconds
Started Mar 10 01:11:42 PM PDT 24
Finished Mar 10 01:11:44 PM PDT 24
Peak memory 216844 kb
Host smart-6372ea67-8349-4cc5-a72c-93cc3c45f1e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619886700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2619886700
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3215966437
Short name T611
Test name
Test status
Simulation time 937880462 ps
CPU time 3.48 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:48 PM PDT 24
Peak memory 200472 kb
Host smart-0def58f3-709a-4ea3-8049-57bdd220fe8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215966437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3215966437
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4193475133
Short name T573
Test name
Test status
Simulation time 223912054 ps
CPU time 1.61 seconds
Started Mar 10 01:11:46 PM PDT 24
Finished Mar 10 01:11:47 PM PDT 24
Peak memory 208744 kb
Host smart-69ac510e-3e0f-42a9-9a06-45307e1bda32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193475133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.4
193475133
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2708198963
Short name T612
Test name
Test status
Simulation time 1993829293 ps
CPU time 10 seconds
Started Mar 10 01:11:43 PM PDT 24
Finished Mar 10 01:11:53 PM PDT 24
Peak memory 200392 kb
Host smart-1c61303b-9e03-47df-af51-258cc1f75e6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708198963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
708198963
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1816389768
Short name T618
Test name
Test status
Simulation time 115855610 ps
CPU time 0.93 seconds
Started Mar 10 01:11:48 PM PDT 24
Finished Mar 10 01:11:49 PM PDT 24
Peak memory 200252 kb
Host smart-91005626-fd72-4509-84a7-616d5b753c26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816389768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
816389768
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3562550761
Short name T67
Test name
Test status
Simulation time 119533461 ps
CPU time 0.97 seconds
Started Mar 10 01:11:46 PM PDT 24
Finished Mar 10 01:11:47 PM PDT 24
Peak memory 200380 kb
Host smart-812a5762-77d0-49e4-92ee-9528eb3157c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562550761 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3562550761
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3049170506
Short name T69
Test name
Test status
Simulation time 78330436 ps
CPU time 0.79 seconds
Started Mar 10 01:11:42 PM PDT 24
Finished Mar 10 01:11:42 PM PDT 24
Peak memory 200292 kb
Host smart-f84c1ceb-0d17-4348-bf85-e3f442b865f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049170506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3049170506
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1853004476
Short name T73
Test name
Test status
Simulation time 215080050 ps
CPU time 1.67 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 210720 kb
Host smart-74b8b41e-cbc7-4453-9cc3-d4805f85ce39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853004476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1853004476
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1136355327
Short name T147
Test name
Test status
Simulation time 867695896 ps
CPU time 3.08 seconds
Started Mar 10 01:11:47 PM PDT 24
Finished Mar 10 01:11:50 PM PDT 24
Peak memory 200536 kb
Host smart-d99e0456-f9d1-4234-986a-8da2278dc110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136355327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1136355327
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1413962976
Short name T558
Test name
Test status
Simulation time 182958330 ps
CPU time 1.7 seconds
Started Mar 10 01:11:54 PM PDT 24
Finished Mar 10 01:11:56 PM PDT 24
Peak memory 208712 kb
Host smart-16377776-d437-4f2f-bba8-121d0693c3de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413962976 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1413962976
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1667711402
Short name T600
Test name
Test status
Simulation time 66857019 ps
CPU time 0.85 seconds
Started Mar 10 01:12:00 PM PDT 24
Finished Mar 10 01:12:01 PM PDT 24
Peak memory 200316 kb
Host smart-c10c841d-14cd-4797-9ba5-069d46c622af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667711402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1667711402
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.776091222
Short name T613
Test name
Test status
Simulation time 158402352 ps
CPU time 1.31 seconds
Started Mar 10 01:11:55 PM PDT 24
Finished Mar 10 01:11:57 PM PDT 24
Peak memory 200248 kb
Host smart-75141f25-558e-419b-a9e1-6a53531d4982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776091222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.776091222
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2852929124
Short name T571
Test name
Test status
Simulation time 498710177 ps
CPU time 1.96 seconds
Started Mar 10 01:11:49 PM PDT 24
Finished Mar 10 01:11:51 PM PDT 24
Peak memory 200460 kb
Host smart-b96e23d8-13fe-40d0-870f-cb6bc579f5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852929124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2852929124
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.579695265
Short name T614
Test name
Test status
Simulation time 189534775 ps
CPU time 1.2 seconds
Started Mar 10 01:11:55 PM PDT 24
Finished Mar 10 01:11:56 PM PDT 24
Peak memory 209784 kb
Host smart-9a71bee3-3fd5-4846-8f41-f6e2aac30fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579695265 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.579695265
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.478549041
Short name T608
Test name
Test status
Simulation time 55700348 ps
CPU time 0.74 seconds
Started Mar 10 01:12:00 PM PDT 24
Finished Mar 10 01:12:01 PM PDT 24
Peak memory 200316 kb
Host smart-ed8e3162-e29e-44e1-bcc4-6f4fb4aa8d2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478549041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.478549041
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2148089506
Short name T560
Test name
Test status
Simulation time 105326124 ps
CPU time 1.21 seconds
Started Mar 10 01:11:53 PM PDT 24
Finished Mar 10 01:11:54 PM PDT 24
Peak memory 200552 kb
Host smart-9c32eebc-eafc-45d2-a28a-00663894e130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148089506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2148089506
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3130353933
Short name T580
Test name
Test status
Simulation time 230318705 ps
CPU time 1.75 seconds
Started Mar 10 01:11:56 PM PDT 24
Finished Mar 10 01:11:58 PM PDT 24
Peak memory 210768 kb
Host smart-52f85487-7cc4-4545-9bc6-e9f34d9da667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130353933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3130353933
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2904138101
Short name T598
Test name
Test status
Simulation time 775749811 ps
CPU time 2.91 seconds
Started Mar 10 01:11:54 PM PDT 24
Finished Mar 10 01:11:57 PM PDT 24
Peak memory 200456 kb
Host smart-db1cfc35-0bc3-4b7f-a858-3805cec16861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904138101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2904138101
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.342088476
Short name T546
Test name
Test status
Simulation time 144789195 ps
CPU time 1.1 seconds
Started Mar 10 01:11:54 PM PDT 24
Finished Mar 10 01:11:56 PM PDT 24
Peak memory 208460 kb
Host smart-5f56e368-0fcc-4f1e-be03-7febea05234c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342088476 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.342088476
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2103112293
Short name T578
Test name
Test status
Simulation time 81997204 ps
CPU time 0.83 seconds
Started Mar 10 01:12:00 PM PDT 24
Finished Mar 10 01:12:01 PM PDT 24
Peak memory 200316 kb
Host smart-630141e9-784c-4aac-832f-2cd528053c47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103112293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2103112293
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.268562448
Short name T586
Test name
Test status
Simulation time 209782383 ps
CPU time 1.53 seconds
Started Mar 10 01:12:02 PM PDT 24
Finished Mar 10 01:12:04 PM PDT 24
Peak memory 200664 kb
Host smart-7401b7fc-70db-4047-9585-55bcbe57256b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268562448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.268562448
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3481632143
Short name T104
Test name
Test status
Simulation time 100732142 ps
CPU time 1.38 seconds
Started Mar 10 01:11:55 PM PDT 24
Finished Mar 10 01:11:56 PM PDT 24
Peak memory 210600 kb
Host smart-28d385f6-ed43-496c-a6b6-950216ea0e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481632143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3481632143
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3275929105
Short name T90
Test name
Test status
Simulation time 105444504 ps
CPU time 1.02 seconds
Started Mar 10 01:11:56 PM PDT 24
Finished Mar 10 01:11:57 PM PDT 24
Peak memory 200576 kb
Host smart-7c0bb9c6-1ed7-488c-9b7d-f18309aa088b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275929105 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3275929105
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3491106419
Short name T592
Test name
Test status
Simulation time 63731452 ps
CPU time 0.81 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:02 PM PDT 24
Peak memory 200304 kb
Host smart-efc88ae2-e260-499b-a503-612c0489c75b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491106419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3491106419
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3138070993
Short name T603
Test name
Test status
Simulation time 134198945 ps
CPU time 1.17 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:02 PM PDT 24
Peak memory 200312 kb
Host smart-7146fb01-1c7c-40cd-82e4-a47ebc45aeda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138070993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3138070993
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1820327019
Short name T561
Test name
Test status
Simulation time 572452500 ps
CPU time 4.3 seconds
Started Mar 10 01:11:54 PM PDT 24
Finished Mar 10 01:11:58 PM PDT 24
Peak memory 208652 kb
Host smart-127183c1-d35d-4c5f-aaab-49b64a67b2c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820327019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1820327019
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4258659889
Short name T559
Test name
Test status
Simulation time 173151723 ps
CPU time 1.09 seconds
Started Mar 10 01:11:55 PM PDT 24
Finished Mar 10 01:11:57 PM PDT 24
Peak memory 200576 kb
Host smart-6ecc7ed9-4957-4cb5-bb2c-5ea06b471d53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258659889 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4258659889
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2204987753
Short name T589
Test name
Test status
Simulation time 70238237 ps
CPU time 0.79 seconds
Started Mar 10 01:11:56 PM PDT 24
Finished Mar 10 01:11:57 PM PDT 24
Peak memory 200200 kb
Host smart-4e653517-3388-44dd-a2ed-61dfd7666fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204987753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2204987753
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3985276733
Short name T129
Test name
Test status
Simulation time 143866552 ps
CPU time 1.13 seconds
Started Mar 10 01:11:57 PM PDT 24
Finished Mar 10 01:11:58 PM PDT 24
Peak memory 200084 kb
Host smart-b2e58dc4-eb2f-4dee-8e0f-228ceb8651c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985276733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3985276733
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1865929377
Short name T72
Test name
Test status
Simulation time 104824329 ps
CPU time 1.46 seconds
Started Mar 10 01:11:55 PM PDT 24
Finished Mar 10 01:11:56 PM PDT 24
Peak memory 208684 kb
Host smart-9468eaea-df0b-4f73-a1fe-5aca90c730b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865929377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1865929377
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3157762893
Short name T553
Test name
Test status
Simulation time 417869005 ps
CPU time 2.04 seconds
Started Mar 10 01:11:57 PM PDT 24
Finished Mar 10 01:11:59 PM PDT 24
Peak memory 200284 kb
Host smart-d9465cef-f8b4-4941-b571-93fc65d9b32a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157762893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3157762893
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3006596719
Short name T547
Test name
Test status
Simulation time 213323082 ps
CPU time 1.37 seconds
Started Mar 10 01:11:57 PM PDT 24
Finished Mar 10 01:11:58 PM PDT 24
Peak memory 208580 kb
Host smart-9fab6f8a-1a10-4578-9ef1-2bf7045479ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006596719 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3006596719
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4040650597
Short name T582
Test name
Test status
Simulation time 74775387 ps
CPU time 0.88 seconds
Started Mar 10 01:11:54 PM PDT 24
Finished Mar 10 01:11:55 PM PDT 24
Peak memory 200300 kb
Host smart-b89a67f4-31ed-4024-80ed-dad1973b0afb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040650597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.4040650597
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3103486900
Short name T566
Test name
Test status
Simulation time 135448096 ps
CPU time 1.23 seconds
Started Mar 10 01:11:51 PM PDT 24
Finished Mar 10 01:11:53 PM PDT 24
Peak memory 200424 kb
Host smart-49fce647-0608-4a3a-803a-5b0294084bd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103486900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3103486900
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3059590550
Short name T572
Test name
Test status
Simulation time 99274764 ps
CPU time 1.28 seconds
Started Mar 10 01:11:59 PM PDT 24
Finished Mar 10 01:12:00 PM PDT 24
Peak memory 200272 kb
Host smart-4f25c992-b626-44c6-a105-08e3cabea0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059590550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3059590550
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1166043664
Short name T96
Test name
Test status
Simulation time 478448304 ps
CPU time 2 seconds
Started Mar 10 01:11:56 PM PDT 24
Finished Mar 10 01:11:58 PM PDT 24
Peak memory 200552 kb
Host smart-a5adeb3b-e450-4111-9035-1a54c6685486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166043664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1166043664
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1000878597
Short name T114
Test name
Test status
Simulation time 157988691 ps
CPU time 1.49 seconds
Started Mar 10 01:11:56 PM PDT 24
Finished Mar 10 01:11:58 PM PDT 24
Peak memory 200560 kb
Host smart-eb49ca15-b701-4548-bad6-1b4f30f1668a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000878597 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1000878597
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.821069636
Short name T615
Test name
Test status
Simulation time 68356484 ps
CPU time 0.81 seconds
Started Mar 10 01:11:56 PM PDT 24
Finished Mar 10 01:11:57 PM PDT 24
Peak memory 200488 kb
Host smart-663005aa-c3ab-4ee2-b578-641adc935812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821069636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.821069636
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1555559356
Short name T596
Test name
Test status
Simulation time 89193729 ps
CPU time 1.01 seconds
Started Mar 10 01:12:00 PM PDT 24
Finished Mar 10 01:12:02 PM PDT 24
Peak memory 200312 kb
Host smart-7daf791d-675d-4075-8d7b-a011a31af64c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555559356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1555559356
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1338532198
Short name T94
Test name
Test status
Simulation time 649669778 ps
CPU time 4.59 seconds
Started Mar 10 01:11:55 PM PDT 24
Finished Mar 10 01:12:00 PM PDT 24
Peak memory 216680 kb
Host smart-362d1919-a13c-4613-885d-540d85b02142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338532198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1338532198
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4128078696
Short name T101
Test name
Test status
Simulation time 462540493 ps
CPU time 1.82 seconds
Started Mar 10 01:11:57 PM PDT 24
Finished Mar 10 01:11:59 PM PDT 24
Peak memory 200556 kb
Host smart-2284234b-3e0d-4c14-8510-6e630635d086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128078696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.4128078696
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1090403583
Short name T590
Test name
Test status
Simulation time 206272706 ps
CPU time 1.37 seconds
Started Mar 10 01:11:59 PM PDT 24
Finished Mar 10 01:12:01 PM PDT 24
Peak memory 208584 kb
Host smart-4e16e139-d3f3-47b0-b83f-c1cecd278950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090403583 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1090403583
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1345654026
Short name T68
Test name
Test status
Simulation time 59320093 ps
CPU time 0.75 seconds
Started Mar 10 01:11:55 PM PDT 24
Finished Mar 10 01:11:56 PM PDT 24
Peak memory 200220 kb
Host smart-f1511ff2-1b28-43a0-8107-fb9262210a13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345654026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1345654026
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1655477408
Short name T131
Test name
Test status
Simulation time 129610333 ps
CPU time 1.34 seconds
Started Mar 10 01:11:58 PM PDT 24
Finished Mar 10 01:12:00 PM PDT 24
Peak memory 200424 kb
Host smart-39409ae6-cdc9-493b-9177-fead0703a5b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655477408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1655477408
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2264406947
Short name T619
Test name
Test status
Simulation time 518330041 ps
CPU time 3.65 seconds
Started Mar 10 01:12:00 PM PDT 24
Finished Mar 10 01:12:04 PM PDT 24
Peak memory 216752 kb
Host smart-e45ccf2e-e6cc-4f76-a056-5d7ed769ab3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264406947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2264406947
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1146725373
Short name T102
Test name
Test status
Simulation time 424152601 ps
CPU time 1.82 seconds
Started Mar 10 01:11:57 PM PDT 24
Finished Mar 10 01:11:58 PM PDT 24
Peak memory 200500 kb
Host smart-b952929b-2150-4fc2-ac46-a5f9def29372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146725373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1146725373
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1954491374
Short name T577
Test name
Test status
Simulation time 137950362 ps
CPU time 1.12 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:05 PM PDT 24
Peak memory 209584 kb
Host smart-8c1f0d90-93dc-41f7-8238-d46e144c01e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954491374 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1954491374
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2489696352
Short name T602
Test name
Test status
Simulation time 64528308 ps
CPU time 0.8 seconds
Started Mar 10 01:11:59 PM PDT 24
Finished Mar 10 01:12:00 PM PDT 24
Peak memory 200256 kb
Host smart-81438330-b53f-4c8a-979b-0968ec7a52d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489696352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2489696352
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1234579907
Short name T576
Test name
Test status
Simulation time 80570789 ps
CPU time 0.98 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:02 PM PDT 24
Peak memory 200176 kb
Host smart-a8bdb74f-837f-4da5-9a22-5d10034d35aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234579907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1234579907
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1135695632
Short name T95
Test name
Test status
Simulation time 425113788 ps
CPU time 3.42 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:04 PM PDT 24
Peak memory 216732 kb
Host smart-3e6036a3-1ea7-432d-b336-5dbdfcf29a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135695632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1135695632
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.947983960
Short name T591
Test name
Test status
Simulation time 477200311 ps
CPU time 1.94 seconds
Started Mar 10 01:11:58 PM PDT 24
Finished Mar 10 01:12:00 PM PDT 24
Peak memory 200428 kb
Host smart-09349230-b6e5-4ec4-9a24-9c6c9c93adb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947983960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.947983960
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2888577097
Short name T562
Test name
Test status
Simulation time 160497110 ps
CPU time 1.42 seconds
Started Mar 10 01:12:00 PM PDT 24
Finished Mar 10 01:12:01 PM PDT 24
Peak memory 208700 kb
Host smart-88ed42fb-e45e-4b57-960e-9cf4acdb1abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888577097 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2888577097
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2563929863
Short name T610
Test name
Test status
Simulation time 86773488 ps
CPU time 0.86 seconds
Started Mar 10 01:12:00 PM PDT 24
Finished Mar 10 01:12:01 PM PDT 24
Peak memory 200240 kb
Host smart-db5ad01d-b848-4ac8-98c0-fd806ff6e17b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563929863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2563929863
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3136792492
Short name T601
Test name
Test status
Simulation time 163164602 ps
CPU time 1.16 seconds
Started Mar 10 01:12:02 PM PDT 24
Finished Mar 10 01:12:03 PM PDT 24
Peak memory 200304 kb
Host smart-67070fd0-acda-46dd-ad94-57b2724368df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136792492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3136792492
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2099013227
Short name T574
Test name
Test status
Simulation time 266998212 ps
CPU time 1.78 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:03 PM PDT 24
Peak memory 208652 kb
Host smart-a31d1b78-c6ce-44e6-b7ce-157ee190679d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099013227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2099013227
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1812739634
Short name T100
Test name
Test status
Simulation time 417040794 ps
CPU time 1.86 seconds
Started Mar 10 01:11:59 PM PDT 24
Finished Mar 10 01:12:01 PM PDT 24
Peak memory 200560 kb
Host smart-60199179-2276-4318-b40e-85b34aec0722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812739634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1812739634
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1336166653
Short name T606
Test name
Test status
Simulation time 437737899 ps
CPU time 2.59 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:47 PM PDT 24
Peak memory 200484 kb
Host smart-63bcc854-11fc-4512-831d-0d53bad2c581
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336166653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
336166653
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3340596044
Short name T550
Test name
Test status
Simulation time 272489020 ps
CPU time 3.25 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:49 PM PDT 24
Peak memory 200356 kb
Host smart-f23fe69a-3d0f-48f8-a619-2aeadbc5ab84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340596044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
340596044
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2506370912
Short name T581
Test name
Test status
Simulation time 120113559 ps
CPU time 0.88 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:45 PM PDT 24
Peak memory 200264 kb
Host smart-3eb26e39-dfbe-43fb-a89b-b6ebac07455e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506370912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
506370912
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1732846777
Short name T594
Test name
Test status
Simulation time 194486199 ps
CPU time 2.2 seconds
Started Mar 10 01:11:43 PM PDT 24
Finished Mar 10 01:11:45 PM PDT 24
Peak memory 213688 kb
Host smart-62461cb9-ed83-4acb-a2cf-529974d15d1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732846777 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1732846777
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.801167782
Short name T132
Test name
Test status
Simulation time 87576344 ps
CPU time 0.89 seconds
Started Mar 10 01:11:43 PM PDT 24
Finished Mar 10 01:11:44 PM PDT 24
Peak memory 200300 kb
Host smart-0010e897-8590-4365-9dec-96a50f00e22e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801167782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.801167782
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2455128276
Short name T617
Test name
Test status
Simulation time 245066289 ps
CPU time 1.68 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 200488 kb
Host smart-0abbd304-89ac-4ce5-9faa-0fc41a55e966
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455128276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2455128276
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2046018289
Short name T99
Test name
Test status
Simulation time 686419372 ps
CPU time 4.39 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:50 PM PDT 24
Peak memory 208648 kb
Host smart-26b74b70-abcd-4d73-9da1-6e05c877f9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046018289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2046018289
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1893061710
Short name T145
Test name
Test status
Simulation time 469657163 ps
CPU time 1.81 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:47 PM PDT 24
Peak memory 200428 kb
Host smart-d96e066b-0589-45ea-9fdc-50f76454c032
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893061710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1893061710
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4253833576
Short name T563
Test name
Test status
Simulation time 157620031 ps
CPU time 2 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:47 PM PDT 24
Peak memory 200424 kb
Host smart-4e5b2108-8d19-453f-9576-eced01970952
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253833576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
253833576
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.840080682
Short name T92
Test name
Test status
Simulation time 490664786 ps
CPU time 6.03 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:51 PM PDT 24
Peak memory 200332 kb
Host smart-826f90aa-b85b-43c4-9364-12a7db6f6998
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840080682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.840080682
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.773709643
Short name T120
Test name
Test status
Simulation time 85567301 ps
CPU time 0.85 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 200148 kb
Host smart-3ca3919e-cdfa-4e05-8e21-3d7909ec2c01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773709643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.773709643
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2753089064
Short name T552
Test name
Test status
Simulation time 121955769 ps
CPU time 1.29 seconds
Started Mar 10 01:11:47 PM PDT 24
Finished Mar 10 01:11:49 PM PDT 24
Peak memory 208456 kb
Host smart-893ccc25-f4f0-44cb-a67d-6ec9e88fc62e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753089064 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2753089064
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2990614746
Short name T564
Test name
Test status
Simulation time 72454035 ps
CPU time 0.87 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:47 PM PDT 24
Peak memory 200220 kb
Host smart-23363ae8-ade7-435f-8aba-98e828f1dcab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990614746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2990614746
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3925105618
Short name T604
Test name
Test status
Simulation time 230950885 ps
CPU time 1.73 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 200484 kb
Host smart-1d76b5ae-65d5-4b4d-9701-a14dc755e47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925105618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3925105618
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2005449099
Short name T585
Test name
Test status
Simulation time 299700395 ps
CPU time 2.07 seconds
Started Mar 10 01:11:43 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 208616 kb
Host smart-049c6028-f380-4815-afb1-dd9c6ff9f2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005449099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2005449099
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.971473745
Short name T88
Test name
Test status
Simulation time 516775491 ps
CPU time 2.02 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 200492 kb
Host smart-e2ee3447-31b8-4026-9e87-fd428dc57c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971473745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
971473745
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1002839536
Short name T587
Test name
Test status
Simulation time 355735591 ps
CPU time 2.32 seconds
Started Mar 10 01:11:43 PM PDT 24
Finished Mar 10 01:11:45 PM PDT 24
Peak memory 200428 kb
Host smart-73ad1dee-63c4-4934-899e-24c71bc06d3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002839536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
002839536
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2527197503
Short name T595
Test name
Test status
Simulation time 268208998 ps
CPU time 3.21 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:48 PM PDT 24
Peak memory 200440 kb
Host smart-acc64905-38a3-4bda-bf5b-45cfff4aabc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527197503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
527197503
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3996610980
Short name T548
Test name
Test status
Simulation time 131985938 ps
CPU time 0.96 seconds
Started Mar 10 01:11:48 PM PDT 24
Finished Mar 10 01:11:50 PM PDT 24
Peak memory 200252 kb
Host smart-0faad83f-0f01-4fc7-a9cb-ec36dc218bd7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996610980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
996610980
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1448014776
Short name T556
Test name
Test status
Simulation time 176647819 ps
CPU time 1.63 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 208708 kb
Host smart-65ce4f17-a03d-498e-adf3-3baab0c13493
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448014776 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1448014776
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3541086957
Short name T569
Test name
Test status
Simulation time 90076402 ps
CPU time 0.91 seconds
Started Mar 10 01:11:46 PM PDT 24
Finished Mar 10 01:11:48 PM PDT 24
Peak memory 200256 kb
Host smart-41a0aa50-5b1d-48fa-9c4e-14fa5239fe9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541086957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3541086957
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4090748974
Short name T597
Test name
Test status
Simulation time 121623765 ps
CPU time 1.06 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:45 PM PDT 24
Peak memory 200200 kb
Host smart-cc383e0f-28c3-4d29-9a07-b3d2671d0c8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090748974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4090748974
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3767731625
Short name T93
Test name
Test status
Simulation time 239955969 ps
CPU time 1.73 seconds
Started Mar 10 01:11:43 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 211736 kb
Host smart-2b655310-2fc2-4781-a56f-a247f47e606b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767731625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3767731625
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2560707133
Short name T89
Test name
Test status
Simulation time 1087742791 ps
CPU time 3.26 seconds
Started Mar 10 01:11:45 PM PDT 24
Finished Mar 10 01:11:49 PM PDT 24
Peak memory 200424 kb
Host smart-6e2f3860-bae1-4ce9-8a69-98060efd14f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560707133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2560707133
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.91952445
Short name T620
Test name
Test status
Simulation time 151902619 ps
CPU time 1.28 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 208592 kb
Host smart-13c69574-da86-4bd4-bae0-9ddb2c49a8ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91952445 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.91952445
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3201213063
Short name T557
Test name
Test status
Simulation time 73694430 ps
CPU time 0.82 seconds
Started Mar 10 01:11:43 PM PDT 24
Finished Mar 10 01:11:44 PM PDT 24
Peak memory 200248 kb
Host smart-9341d37b-74a4-4eb9-bee3-9034412ece43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201213063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3201213063
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1238635480
Short name T133
Test name
Test status
Simulation time 133359892 ps
CPU time 1.27 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 200548 kb
Host smart-6c58f6ec-b785-4192-a714-e7d75c86bf40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238635480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1238635480
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.344361061
Short name T568
Test name
Test status
Simulation time 172822055 ps
CPU time 2.42 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:47 PM PDT 24
Peak memory 200468 kb
Host smart-c449f89c-88b1-4498-afc3-3c1043dab50c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344361061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.344361061
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1351008127
Short name T616
Test name
Test status
Simulation time 118451482 ps
CPU time 0.98 seconds
Started Mar 10 01:11:49 PM PDT 24
Finished Mar 10 01:11:50 PM PDT 24
Peak memory 200316 kb
Host smart-5930da86-2028-46ac-a6e5-93a6d3c9e82c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351008127 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1351008127
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1590306874
Short name T128
Test name
Test status
Simulation time 57608460 ps
CPU time 0.74 seconds
Started Mar 10 01:11:47 PM PDT 24
Finished Mar 10 01:11:48 PM PDT 24
Peak memory 200240 kb
Host smart-d5e7a224-a5dd-405e-8bb2-3227e723cd7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590306874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1590306874
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.274798943
Short name T584
Test name
Test status
Simulation time 177487515 ps
CPU time 1.52 seconds
Started Mar 10 01:11:49 PM PDT 24
Finished Mar 10 01:11:50 PM PDT 24
Peak memory 200436 kb
Host smart-696927d9-d6ae-4901-86e8-e81b3dfe7139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274798943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.274798943
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3847502463
Short name T607
Test name
Test status
Simulation time 205523285 ps
CPU time 1.71 seconds
Started Mar 10 01:11:47 PM PDT 24
Finished Mar 10 01:11:49 PM PDT 24
Peak memory 211328 kb
Host smart-c72b82bb-1660-43df-b624-4eef2a7333d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847502463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3847502463
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3904711211
Short name T97
Test name
Test status
Simulation time 478914731 ps
CPU time 1.84 seconds
Started Mar 10 01:11:44 PM PDT 24
Finished Mar 10 01:11:46 PM PDT 24
Peak memory 200476 kb
Host smart-7b384c47-ccf1-4c8c-97fb-584c7642b089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904711211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3904711211
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2855674549
Short name T565
Test name
Test status
Simulation time 118861076 ps
CPU time 1.01 seconds
Started Mar 10 01:11:50 PM PDT 24
Finished Mar 10 01:11:51 PM PDT 24
Peak memory 200356 kb
Host smart-37c52eb8-984a-43e1-b293-ca2a4cdeb0a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855674549 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2855674549
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2818834999
Short name T135
Test name
Test status
Simulation time 93066323 ps
CPU time 0.89 seconds
Started Mar 10 01:11:50 PM PDT 24
Finished Mar 10 01:11:51 PM PDT 24
Peak memory 200332 kb
Host smart-728613dd-8d90-4f89-a444-91df53ffb812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818834999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2818834999
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1638540689
Short name T567
Test name
Test status
Simulation time 88452514 ps
CPU time 1.06 seconds
Started Mar 10 01:11:50 PM PDT 24
Finished Mar 10 01:11:51 PM PDT 24
Peak memory 200288 kb
Host smart-0c7f3f48-a997-4ecd-8155-bf1038131d28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638540689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1638540689
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1990513289
Short name T103
Test name
Test status
Simulation time 128571811 ps
CPU time 1.79 seconds
Started Mar 10 01:11:51 PM PDT 24
Finished Mar 10 01:11:53 PM PDT 24
Peak memory 208636 kb
Host smart-88f319ea-4367-4097-bb92-9ed6dd7ebcbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990513289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1990513289
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.722259955
Short name T579
Test name
Test status
Simulation time 795578629 ps
CPU time 3.04 seconds
Started Mar 10 01:11:49 PM PDT 24
Finished Mar 10 01:11:52 PM PDT 24
Peak memory 200472 kb
Host smart-5d040c2f-d555-490a-b264-c03dcc952067
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722259955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
722259955
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.516425376
Short name T609
Test name
Test status
Simulation time 193615753 ps
CPU time 1.29 seconds
Started Mar 10 01:11:49 PM PDT 24
Finished Mar 10 01:11:51 PM PDT 24
Peak memory 208676 kb
Host smart-495c15b5-69ad-4080-9e91-c2457f0ae872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516425376 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.516425376
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.794853744
Short name T588
Test name
Test status
Simulation time 66358568 ps
CPU time 0.76 seconds
Started Mar 10 01:11:51 PM PDT 24
Finished Mar 10 01:11:52 PM PDT 24
Peak memory 200304 kb
Host smart-d30339cf-f67c-4d00-94b1-baea509f7e87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794853744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.794853744
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2277751656
Short name T599
Test name
Test status
Simulation time 140529004 ps
CPU time 1.38 seconds
Started Mar 10 01:11:51 PM PDT 24
Finished Mar 10 01:11:52 PM PDT 24
Peak memory 200496 kb
Host smart-2e49b05a-3497-4f5c-a8c2-2d479f27a88c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277751656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2277751656
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3177974920
Short name T144
Test name
Test status
Simulation time 501540102 ps
CPU time 1.87 seconds
Started Mar 10 01:11:48 PM PDT 24
Finished Mar 10 01:11:50 PM PDT 24
Peak memory 200476 kb
Host smart-2b07fc07-b355-4f11-b8d1-dd34be9d6835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177974920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3177974920
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2112554745
Short name T71
Test name
Test status
Simulation time 196363662 ps
CPU time 1.42 seconds
Started Mar 10 01:11:52 PM PDT 24
Finished Mar 10 01:11:53 PM PDT 24
Peak memory 208556 kb
Host smart-5f26951c-b155-41de-aba8-89efeac5219e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112554745 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2112554745
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3110290963
Short name T136
Test name
Test status
Simulation time 67608512 ps
CPU time 0.79 seconds
Started Mar 10 01:11:48 PM PDT 24
Finished Mar 10 01:11:49 PM PDT 24
Peak memory 200248 kb
Host smart-01816584-47a9-49a9-8978-1dcda550a809
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110290963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3110290963
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4074460990
Short name T130
Test name
Test status
Simulation time 161071064 ps
CPU time 1.17 seconds
Started Mar 10 01:11:50 PM PDT 24
Finished Mar 10 01:11:51 PM PDT 24
Peak memory 200232 kb
Host smart-974d571e-d241-4f58-90b2-839056d784b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074460990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4074460990
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1848447293
Short name T555
Test name
Test status
Simulation time 203327507 ps
CPU time 3 seconds
Started Mar 10 01:11:49 PM PDT 24
Finished Mar 10 01:11:52 PM PDT 24
Peak memory 216684 kb
Host smart-52d11f35-e0fe-4504-8cf3-b5c7547406d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848447293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1848447293
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.515618231
Short name T575
Test name
Test status
Simulation time 490621029 ps
CPU time 2.05 seconds
Started Mar 10 01:11:49 PM PDT 24
Finished Mar 10 01:11:51 PM PDT 24
Peak memory 200472 kb
Host smart-9ffb9f3b-6628-4455-85a1-2137e44fe040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515618231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
515618231
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.94836924
Short name T330
Test name
Test status
Simulation time 87523410 ps
CPU time 0.83 seconds
Started Mar 10 01:24:30 PM PDT 24
Finished Mar 10 01:24:31 PM PDT 24
Peak memory 200280 kb
Host smart-7a71b4ae-730b-42dd-b4ba-a7470bc6a5a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94836924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.94836924
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1092689525
Short name T328
Test name
Test status
Simulation time 1221238920 ps
CPU time 5.89 seconds
Started Mar 10 01:24:32 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 217080 kb
Host smart-8fde67bd-5f39-4f6a-9a55-1cba55e54fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092689525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1092689525
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2448107319
Short name T314
Test name
Test status
Simulation time 244610941 ps
CPU time 1.04 seconds
Started Mar 10 01:24:34 PM PDT 24
Finished Mar 10 01:24:36 PM PDT 24
Peak memory 217132 kb
Host smart-2e1d80cb-6bab-4fd6-b0ff-606870a9a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448107319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2448107319
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1687790810
Short name T298
Test name
Test status
Simulation time 206190237 ps
CPU time 0.98 seconds
Started Mar 10 01:24:34 PM PDT 24
Finished Mar 10 01:24:36 PM PDT 24
Peak memory 200220 kb
Host smart-608a5cc1-140f-4c9d-b8d5-f38a35f7e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687790810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1687790810
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3798453487
Short name T121
Test name
Test status
Simulation time 914619863 ps
CPU time 4.33 seconds
Started Mar 10 01:24:30 PM PDT 24
Finished Mar 10 01:24:34 PM PDT 24
Peak memory 200568 kb
Host smart-a056d0e0-c6ee-4853-8354-9cc0481429c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798453487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3798453487
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3752450793
Short name T285
Test name
Test status
Simulation time 135280098 ps
CPU time 1.03 seconds
Started Mar 10 01:24:28 PM PDT 24
Finished Mar 10 01:24:30 PM PDT 24
Peak memory 200444 kb
Host smart-d153bd17-c17c-42a4-86db-16a4e3fa9dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752450793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3752450793
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.372028722
Short name T112
Test name
Test status
Simulation time 119072160 ps
CPU time 1.2 seconds
Started Mar 10 01:24:30 PM PDT 24
Finished Mar 10 01:24:31 PM PDT 24
Peak memory 200504 kb
Host smart-483c6812-b2ef-41b0-b51c-d0210ed96bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372028722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.372028722
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.4134994473
Short name T450
Test name
Test status
Simulation time 499417285 ps
CPU time 2.9 seconds
Started Mar 10 01:24:34 PM PDT 24
Finished Mar 10 01:24:37 PM PDT 24
Peak memory 200520 kb
Host smart-ef5c4ac5-2d9d-413d-aafa-e827167e8685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134994473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4134994473
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.715907043
Short name T249
Test name
Test status
Simulation time 280775106 ps
CPU time 1.96 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:33 PM PDT 24
Peak memory 200312 kb
Host smart-9149bb62-ef92-4cc5-9062-59ad428ea9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715907043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.715907043
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3540299086
Short name T279
Test name
Test status
Simulation time 235816324 ps
CPU time 1.31 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:33 PM PDT 24
Peak memory 200424 kb
Host smart-fd89c507-52b0-4668-9074-2523a1dd52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540299086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3540299086
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3651098718
Short name T48
Test name
Test status
Simulation time 82114407 ps
CPU time 0.78 seconds
Started Mar 10 01:24:34 PM PDT 24
Finished Mar 10 01:24:36 PM PDT 24
Peak memory 200256 kb
Host smart-f484ef23-d792-43e3-ab52-24bc35ee5322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651098718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3651098718
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2991039657
Short name T495
Test name
Test status
Simulation time 1227493070 ps
CPU time 5.41 seconds
Started Mar 10 01:24:35 PM PDT 24
Finished Mar 10 01:24:41 PM PDT 24
Peak memory 220828 kb
Host smart-af51ebf9-a7ac-4592-a03e-a4c9294261c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991039657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2991039657
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3239604394
Short name T80
Test name
Test status
Simulation time 244610232 ps
CPU time 1.11 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 217224 kb
Host smart-cda306b0-8727-4e0d-98ae-01786c6cd1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239604394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3239604394
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2768854955
Short name T324
Test name
Test status
Simulation time 1143376684 ps
CPU time 6.09 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:37 PM PDT 24
Peak memory 200592 kb
Host smart-cb8c534b-61d8-43c8-8678-a96dc99afcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768854955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2768854955
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3803171280
Short name T78
Test name
Test status
Simulation time 8429648658 ps
CPU time 13.85 seconds
Started Mar 10 01:24:38 PM PDT 24
Finished Mar 10 01:24:53 PM PDT 24
Peak memory 216900 kb
Host smart-ac926b02-f520-4bcc-9be6-adabbddcdba5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803171280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3803171280
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3679614066
Short name T503
Test name
Test status
Simulation time 165777645 ps
CPU time 1.16 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:33 PM PDT 24
Peak memory 200376 kb
Host smart-ec56de22-7da5-494c-bda7-30d514553d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679614066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3679614066
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.67282082
Short name T166
Test name
Test status
Simulation time 127276048 ps
CPU time 1.19 seconds
Started Mar 10 01:24:31 PM PDT 24
Finished Mar 10 01:24:32 PM PDT 24
Peak memory 200532 kb
Host smart-d0b7e70b-b60a-471c-b470-b77905e1f474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67282082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.67282082
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.594359098
Short name T432
Test name
Test status
Simulation time 7161555252 ps
CPU time 23.22 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:25:01 PM PDT 24
Peak memory 200668 kb
Host smart-eeaef326-caae-4d10-be3e-205e03b280c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594359098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.594359098
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.239019360
Short name T291
Test name
Test status
Simulation time 123151766 ps
CPU time 1.55 seconds
Started Mar 10 01:24:33 PM PDT 24
Finished Mar 10 01:24:35 PM PDT 24
Peak memory 200316 kb
Host smart-ff17b54a-2a89-4a16-9832-6fc3bed54021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239019360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.239019360
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2330133683
Short name T326
Test name
Test status
Simulation time 114622710 ps
CPU time 0.99 seconds
Started Mar 10 01:24:32 PM PDT 24
Finished Mar 10 01:24:33 PM PDT 24
Peak memory 200424 kb
Host smart-8c90dde4-4490-403d-ab0d-8203c7ccbeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330133683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2330133683
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3353559326
Short name T191
Test name
Test status
Simulation time 66953298 ps
CPU time 0.8 seconds
Started Mar 10 01:24:58 PM PDT 24
Finished Mar 10 01:24:59 PM PDT 24
Peak memory 200252 kb
Host smart-3a6d690e-c54f-496a-8883-498c869ea418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353559326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3353559326
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2652011171
Short name T468
Test name
Test status
Simulation time 1220332641 ps
CPU time 6.44 seconds
Started Mar 10 01:24:50 PM PDT 24
Finished Mar 10 01:24:57 PM PDT 24
Peak memory 218272 kb
Host smart-0f78063b-21d9-4910-8f17-cb0b3acc2bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652011171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2652011171
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1705684083
Short name T506
Test name
Test status
Simulation time 244609061 ps
CPU time 1.13 seconds
Started Mar 10 01:24:59 PM PDT 24
Finished Mar 10 01:25:01 PM PDT 24
Peak memory 217188 kb
Host smart-e25b674a-9042-4388-ae5b-116211c01fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705684083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1705684083
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2191120116
Short name T22
Test name
Test status
Simulation time 86451393 ps
CPU time 0.78 seconds
Started Mar 10 01:24:55 PM PDT 24
Finished Mar 10 01:24:56 PM PDT 24
Peak memory 200212 kb
Host smart-65f2b3cb-12ff-488f-a248-f72d8a60520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191120116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2191120116
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2816631752
Short name T312
Test name
Test status
Simulation time 1131374256 ps
CPU time 5.37 seconds
Started Mar 10 01:24:51 PM PDT 24
Finished Mar 10 01:24:57 PM PDT 24
Peak memory 200516 kb
Host smart-790be5bb-c018-489b-a1a2-c9a06e436c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816631752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2816631752
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2852506541
Short name T221
Test name
Test status
Simulation time 229788599 ps
CPU time 1.47 seconds
Started Mar 10 01:24:51 PM PDT 24
Finished Mar 10 01:24:53 PM PDT 24
Peak memory 200484 kb
Host smart-4a802fff-86db-4ab4-ad38-971a222c5858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852506541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2852506541
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3929551706
Short name T126
Test name
Test status
Simulation time 2296209832 ps
CPU time 11.06 seconds
Started Mar 10 01:24:54 PM PDT 24
Finished Mar 10 01:25:06 PM PDT 24
Peak memory 210852 kb
Host smart-103ff312-f3ff-4aaa-acee-afd0b9ff975e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929551706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3929551706
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3770517021
Short name T386
Test name
Test status
Simulation time 526824259 ps
CPU time 2.88 seconds
Started Mar 10 01:24:54 PM PDT 24
Finished Mar 10 01:24:57 PM PDT 24
Peak memory 200288 kb
Host smart-2ccd7695-0264-43d5-bcc6-b9e69801f1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770517021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3770517021
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2414412426
Short name T385
Test name
Test status
Simulation time 80371819 ps
CPU time 0.85 seconds
Started Mar 10 01:24:52 PM PDT 24
Finished Mar 10 01:24:53 PM PDT 24
Peak memory 200440 kb
Host smart-f14bec6c-5264-47e3-9d37-2a4fa80b5ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414412426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2414412426
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.922655308
Short name T79
Test name
Test status
Simulation time 67647849 ps
CPU time 0.8 seconds
Started Mar 10 01:25:02 PM PDT 24
Finished Mar 10 01:25:03 PM PDT 24
Peak memory 200208 kb
Host smart-027a8d14-8275-48c1-a13c-18c0a7d7a892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922655308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.922655308
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1482692077
Short name T164
Test name
Test status
Simulation time 243528395 ps
CPU time 1.17 seconds
Started Mar 10 01:24:50 PM PDT 24
Finished Mar 10 01:24:51 PM PDT 24
Peak memory 217204 kb
Host smart-56f995db-320c-48d5-8fe2-28af0b8524cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482692077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1482692077
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1504584207
Short name T18
Test name
Test status
Simulation time 145653147 ps
CPU time 0.81 seconds
Started Mar 10 01:24:52 PM PDT 24
Finished Mar 10 01:24:53 PM PDT 24
Peak memory 200216 kb
Host smart-159e9ca7-88ae-4fa6-8695-cde4c2f8632e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504584207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1504584207
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.999870247
Short name T476
Test name
Test status
Simulation time 735958488 ps
CPU time 3.92 seconds
Started Mar 10 01:24:53 PM PDT 24
Finished Mar 10 01:24:57 PM PDT 24
Peak memory 200636 kb
Host smart-7900a43a-2eee-4af3-b9fb-e3eb8112ce46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999870247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.999870247
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2168263932
Short name T511
Test name
Test status
Simulation time 151449480 ps
CPU time 1.2 seconds
Started Mar 10 01:24:54 PM PDT 24
Finished Mar 10 01:24:56 PM PDT 24
Peak memory 200408 kb
Host smart-cfc4d2bc-2bd3-4ce4-a14a-26fa61ae5149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168263932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2168263932
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1571149109
Short name T253
Test name
Test status
Simulation time 193994101 ps
CPU time 1.42 seconds
Started Mar 10 01:24:55 PM PDT 24
Finished Mar 10 01:24:56 PM PDT 24
Peak memory 200524 kb
Host smart-d25f3bad-1bed-467d-b643-ac0d24014dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571149109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1571149109
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2206814068
Short name T521
Test name
Test status
Simulation time 5420908855 ps
CPU time 18.65 seconds
Started Mar 10 01:24:58 PM PDT 24
Finished Mar 10 01:25:16 PM PDT 24
Peak memory 209480 kb
Host smart-16ce35b1-23ac-4adc-b60a-b43f645da451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206814068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2206814068
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3507813611
Short name T202
Test name
Test status
Simulation time 118193088 ps
CPU time 1.58 seconds
Started Mar 10 01:24:49 PM PDT 24
Finished Mar 10 01:24:51 PM PDT 24
Peak memory 208484 kb
Host smart-76d9ef85-4e5b-4f2f-a593-0d7af4df79ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507813611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3507813611
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1589487521
Short name T376
Test name
Test status
Simulation time 140286804 ps
CPU time 1.17 seconds
Started Mar 10 01:24:52 PM PDT 24
Finished Mar 10 01:24:53 PM PDT 24
Peak memory 200412 kb
Host smart-abdca72b-d9f5-4f4a-964c-761756a4f236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589487521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1589487521
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.135526897
Short name T154
Test name
Test status
Simulation time 90567309 ps
CPU time 0.91 seconds
Started Mar 10 01:24:58 PM PDT 24
Finished Mar 10 01:24:59 PM PDT 24
Peak memory 200256 kb
Host smart-dcaa86bf-2e96-429d-babf-ba904e3d08c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135526897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.135526897
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2228232913
Short name T397
Test name
Test status
Simulation time 1218207021 ps
CPU time 5.54 seconds
Started Mar 10 01:24:58 PM PDT 24
Finished Mar 10 01:25:03 PM PDT 24
Peak memory 217080 kb
Host smart-b9800586-4456-4642-b203-7e72696dd65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228232913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2228232913
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2177277294
Short name T488
Test name
Test status
Simulation time 245249488 ps
CPU time 1.04 seconds
Started Mar 10 01:24:58 PM PDT 24
Finished Mar 10 01:24:59 PM PDT 24
Peak memory 217248 kb
Host smart-6fdf7f3f-1d2f-4285-82be-f5d595a7a914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177277294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2177277294
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.454582228
Short name T348
Test name
Test status
Simulation time 222155629 ps
CPU time 1.01 seconds
Started Mar 10 01:24:57 PM PDT 24
Finished Mar 10 01:24:58 PM PDT 24
Peak memory 200156 kb
Host smart-79534ab9-5b70-423e-a0d0-299ffb87b63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454582228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.454582228
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.4147377978
Short name T229
Test name
Test status
Simulation time 1179753274 ps
CPU time 4.73 seconds
Started Mar 10 01:24:57 PM PDT 24
Finished Mar 10 01:25:02 PM PDT 24
Peak memory 200548 kb
Host smart-609e9c25-64ae-428e-8dd9-71530f95504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147377978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.4147377978
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1608931575
Short name T469
Test name
Test status
Simulation time 177901256 ps
CPU time 1.2 seconds
Started Mar 10 01:24:58 PM PDT 24
Finished Mar 10 01:25:00 PM PDT 24
Peak memory 200360 kb
Host smart-225b1de0-a9d5-4de9-85d9-f137c1650d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608931575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1608931575
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1345212647
Short name T105
Test name
Test status
Simulation time 262205517 ps
CPU time 1.46 seconds
Started Mar 10 01:24:58 PM PDT 24
Finished Mar 10 01:25:00 PM PDT 24
Peak memory 200548 kb
Host smart-13123e86-36ec-4eb4-a8fa-e4328f7cd6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345212647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1345212647
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2691031705
Short name T429
Test name
Test status
Simulation time 1515459847 ps
CPU time 5.71 seconds
Started Mar 10 01:24:54 PM PDT 24
Finished Mar 10 01:25:00 PM PDT 24
Peak memory 200564 kb
Host smart-3b604e2d-1c25-488d-8b3a-cab0b7ec3164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691031705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2691031705
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2983775809
Short name T331
Test name
Test status
Simulation time 271784965 ps
CPU time 1.88 seconds
Started Mar 10 01:24:56 PM PDT 24
Finished Mar 10 01:24:58 PM PDT 24
Peak memory 200308 kb
Host smart-ff658188-0f8c-49ae-bbc8-c0be8befa4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983775809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2983775809
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3905141769
Short name T486
Test name
Test status
Simulation time 252826451 ps
CPU time 1.49 seconds
Started Mar 10 01:24:56 PM PDT 24
Finished Mar 10 01:24:57 PM PDT 24
Peak memory 200392 kb
Host smart-7ec2877f-321c-4804-aeae-deb98a2127df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905141769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3905141769
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1239728678
Short name T172
Test name
Test status
Simulation time 73400353 ps
CPU time 0.8 seconds
Started Mar 10 01:24:56 PM PDT 24
Finished Mar 10 01:24:57 PM PDT 24
Peak memory 200308 kb
Host smart-69f725f3-afea-44a9-8073-76e1325f5eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239728678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1239728678
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.4194249287
Short name T410
Test name
Test status
Simulation time 1235173946 ps
CPU time 5.84 seconds
Started Mar 10 01:24:56 PM PDT 24
Finished Mar 10 01:25:02 PM PDT 24
Peak memory 221828 kb
Host smart-30475202-3dae-4448-b6c5-836daacb2e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194249287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.4194249287
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.246950001
Short name T85
Test name
Test status
Simulation time 243528552 ps
CPU time 1.21 seconds
Started Mar 10 01:24:55 PM PDT 24
Finished Mar 10 01:24:56 PM PDT 24
Peak memory 217304 kb
Host smart-1ebc4d95-e990-460a-8e4b-27e7196732ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246950001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.246950001
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1937968730
Short name T377
Test name
Test status
Simulation time 101455712 ps
CPU time 0.78 seconds
Started Mar 10 01:24:57 PM PDT 24
Finished Mar 10 01:24:58 PM PDT 24
Peak memory 200212 kb
Host smart-767bd188-a7c4-4902-bbc4-7ad9385fb70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937968730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1937968730
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3131429049
Short name T212
Test name
Test status
Simulation time 1594747513 ps
CPU time 6.32 seconds
Started Mar 10 01:24:55 PM PDT 24
Finished Mar 10 01:25:01 PM PDT 24
Peak memory 200564 kb
Host smart-cea09b1b-d52e-49a8-af53-eb6bdcb78b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131429049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3131429049
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1111809610
Short name T174
Test name
Test status
Simulation time 102870600 ps
CPU time 1.01 seconds
Started Mar 10 01:24:57 PM PDT 24
Finished Mar 10 01:24:58 PM PDT 24
Peak memory 200440 kb
Host smart-c0604e3c-5d2e-46d2-9928-9dbf4bac8d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111809610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1111809610
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3776659641
Short name T390
Test name
Test status
Simulation time 231570302 ps
CPU time 1.48 seconds
Started Mar 10 01:24:59 PM PDT 24
Finished Mar 10 01:25:01 PM PDT 24
Peak memory 200572 kb
Host smart-b6fdc805-6160-4a89-9710-bb60c93c5320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776659641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3776659641
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2674515901
Short name T210
Test name
Test status
Simulation time 13159133911 ps
CPU time 48.51 seconds
Started Mar 10 01:24:58 PM PDT 24
Finished Mar 10 01:25:47 PM PDT 24
Peak memory 200652 kb
Host smart-19b26529-0884-4e1d-8201-839f57ebe470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674515901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2674515901
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1324961703
Short name T234
Test name
Test status
Simulation time 521043079 ps
CPU time 2.81 seconds
Started Mar 10 01:24:55 PM PDT 24
Finished Mar 10 01:24:58 PM PDT 24
Peak memory 200376 kb
Host smart-6fb560b9-c5fd-4151-8f40-8ddc6274035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324961703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1324961703
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2593736090
Short name T157
Test name
Test status
Simulation time 78071237 ps
CPU time 0.78 seconds
Started Mar 10 01:24:54 PM PDT 24
Finished Mar 10 01:24:55 PM PDT 24
Peak memory 200380 kb
Host smart-6fc95485-e755-43d6-ba99-e3a921e5383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593736090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2593736090
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.967054274
Short name T512
Test name
Test status
Simulation time 75856365 ps
CPU time 0.77 seconds
Started Mar 10 01:24:59 PM PDT 24
Finished Mar 10 01:25:00 PM PDT 24
Peak memory 200340 kb
Host smart-0f09720b-4b4f-46f5-8502-c13d205da666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967054274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.967054274
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3721442163
Short name T35
Test name
Test status
Simulation time 1232780724 ps
CPU time 5.63 seconds
Started Mar 10 01:25:02 PM PDT 24
Finished Mar 10 01:25:07 PM PDT 24
Peak memory 217824 kb
Host smart-96810fbd-0338-4597-8ed8-ddbb3f413195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721442163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3721442163
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3718042759
Short name T182
Test name
Test status
Simulation time 243991556 ps
CPU time 1.2 seconds
Started Mar 10 01:25:01 PM PDT 24
Finished Mar 10 01:25:02 PM PDT 24
Peak memory 217248 kb
Host smart-95fb6fbc-4ff3-4694-be12-8d517309debb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718042759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3718042759
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.848292209
Short name T230
Test name
Test status
Simulation time 138990256 ps
CPU time 0.82 seconds
Started Mar 10 01:24:55 PM PDT 24
Finished Mar 10 01:24:56 PM PDT 24
Peak memory 200124 kb
Host smart-864211a4-4f84-4604-a6f3-ed13e135a20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848292209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.848292209
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2216407971
Short name T342
Test name
Test status
Simulation time 1580382090 ps
CPU time 6.09 seconds
Started Mar 10 01:24:56 PM PDT 24
Finished Mar 10 01:25:02 PM PDT 24
Peak memory 200604 kb
Host smart-385db51e-a0dc-4a63-a338-0145c35556e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216407971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2216407971
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1389473318
Short name T496
Test name
Test status
Simulation time 109402219 ps
CPU time 1.07 seconds
Started Mar 10 01:24:58 PM PDT 24
Finished Mar 10 01:24:59 PM PDT 24
Peak memory 200380 kb
Host smart-99c5deb9-64de-4dc8-b7c8-43defa06a7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389473318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1389473318
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.470212205
Short name T226
Test name
Test status
Simulation time 124457722 ps
CPU time 1.17 seconds
Started Mar 10 01:24:57 PM PDT 24
Finished Mar 10 01:24:59 PM PDT 24
Peak memory 200564 kb
Host smart-a3e1f9d1-7f89-4e81-aec9-51f692410ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470212205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.470212205
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3218895906
Short name T343
Test name
Test status
Simulation time 410582677 ps
CPU time 1.86 seconds
Started Mar 10 01:25:03 PM PDT 24
Finished Mar 10 01:25:05 PM PDT 24
Peak memory 200504 kb
Host smart-7dccaed7-8d43-4f5b-ae67-807af10c8b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218895906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3218895906
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1604716241
Short name T295
Test name
Test status
Simulation time 369489738 ps
CPU time 2.32 seconds
Started Mar 10 01:25:01 PM PDT 24
Finished Mar 10 01:25:03 PM PDT 24
Peak memory 200288 kb
Host smart-168e611c-c258-4776-a8a5-6708b3ee989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604716241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1604716241
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2558011063
Short name T289
Test name
Test status
Simulation time 96199059 ps
CPU time 0.93 seconds
Started Mar 10 01:24:56 PM PDT 24
Finished Mar 10 01:24:57 PM PDT 24
Peak memory 200380 kb
Host smart-a25a3c18-1f42-4171-a927-74f5b7493585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558011063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2558011063
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.4280344452
Short name T475
Test name
Test status
Simulation time 93614749 ps
CPU time 0.8 seconds
Started Mar 10 01:25:03 PM PDT 24
Finished Mar 10 01:25:04 PM PDT 24
Peak memory 200236 kb
Host smart-2060d88f-27a8-4392-8e25-79345a5ebc93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280344452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.4280344452
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3817023421
Short name T499
Test name
Test status
Simulation time 1880875290 ps
CPU time 7.49 seconds
Started Mar 10 01:25:03 PM PDT 24
Finished Mar 10 01:25:11 PM PDT 24
Peak memory 217152 kb
Host smart-23bc1394-cb4c-4b2f-889b-b94d8d998786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817023421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3817023421
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1643899956
Short name T378
Test name
Test status
Simulation time 243621695 ps
CPU time 1.13 seconds
Started Mar 10 01:25:02 PM PDT 24
Finished Mar 10 01:25:04 PM PDT 24
Peak memory 217304 kb
Host smart-ef9d3620-9c4c-46a4-ad8f-95bbd0ee2f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643899956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1643899956
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1394444205
Short name T247
Test name
Test status
Simulation time 148206201 ps
CPU time 0.88 seconds
Started Mar 10 01:25:09 PM PDT 24
Finished Mar 10 01:25:10 PM PDT 24
Peak memory 200232 kb
Host smart-4c32ff5a-f5c3-4650-9df1-d5b1c0f02156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394444205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1394444205
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.111044488
Short name T281
Test name
Test status
Simulation time 1529630755 ps
CPU time 6.9 seconds
Started Mar 10 01:25:03 PM PDT 24
Finished Mar 10 01:25:10 PM PDT 24
Peak memory 200604 kb
Host smart-b57c7dbf-16ce-4081-a13f-abde8010323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111044488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.111044488
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1690457620
Short name T211
Test name
Test status
Simulation time 110082350 ps
CPU time 1.1 seconds
Started Mar 10 01:25:01 PM PDT 24
Finished Mar 10 01:25:02 PM PDT 24
Peak memory 200440 kb
Host smart-88f973a5-22c3-4301-99c1-4b742927d626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690457620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1690457620
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1074678093
Short name T236
Test name
Test status
Simulation time 248778050 ps
CPU time 1.47 seconds
Started Mar 10 01:25:02 PM PDT 24
Finished Mar 10 01:25:04 PM PDT 24
Peak memory 200484 kb
Host smart-35b5330e-3e1e-4ce1-93c9-232f5b6cc0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074678093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1074678093
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.665756844
Short name T302
Test name
Test status
Simulation time 492027573 ps
CPU time 2.59 seconds
Started Mar 10 01:25:08 PM PDT 24
Finished Mar 10 01:25:11 PM PDT 24
Peak memory 200568 kb
Host smart-c31d447b-eb7e-488f-aadc-d643f52e71b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665756844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.665756844
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2684079182
Short name T375
Test name
Test status
Simulation time 272865132 ps
CPU time 1.91 seconds
Started Mar 10 01:25:09 PM PDT 24
Finished Mar 10 01:25:11 PM PDT 24
Peak memory 200368 kb
Host smart-3c00cccb-f64c-4e28-992e-0755836408eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684079182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2684079182
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1522271931
Short name T259
Test name
Test status
Simulation time 86442516 ps
CPU time 0.9 seconds
Started Mar 10 01:25:07 PM PDT 24
Finished Mar 10 01:25:08 PM PDT 24
Peak memory 200348 kb
Host smart-35d89e16-94c5-4cb1-8e21-969217d00880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522271931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1522271931
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1734093948
Short name T365
Test name
Test status
Simulation time 63066629 ps
CPU time 0.77 seconds
Started Mar 10 01:25:11 PM PDT 24
Finished Mar 10 01:25:11 PM PDT 24
Peak memory 200340 kb
Host smart-b5618d32-01f6-41f1-afed-12ebe2f8a726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734093948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1734093948
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2594221993
Short name T33
Test name
Test status
Simulation time 2170467336 ps
CPU time 8.06 seconds
Started Mar 10 01:25:08 PM PDT 24
Finished Mar 10 01:25:17 PM PDT 24
Peak memory 217796 kb
Host smart-b1df4c0d-620b-4207-b54b-fa72c0ae351a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594221993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2594221993
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3750368641
Short name T515
Test name
Test status
Simulation time 243747026 ps
CPU time 1.12 seconds
Started Mar 10 01:25:07 PM PDT 24
Finished Mar 10 01:25:08 PM PDT 24
Peak memory 217212 kb
Host smart-aa818a74-1006-4f8a-827b-2b0d5b37a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750368641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3750368641
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2797284267
Short name T217
Test name
Test status
Simulation time 101356658 ps
CPU time 0.79 seconds
Started Mar 10 01:25:01 PM PDT 24
Finished Mar 10 01:25:02 PM PDT 24
Peak memory 200232 kb
Host smart-164de643-dd03-47ee-9693-70e98865dc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797284267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2797284267
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1253786518
Short name T274
Test name
Test status
Simulation time 951740760 ps
CPU time 4.88 seconds
Started Mar 10 01:25:04 PM PDT 24
Finished Mar 10 01:25:09 PM PDT 24
Peak memory 200572 kb
Host smart-af50990f-8fd5-4bbb-b8d2-cfed317ecbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253786518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1253786518
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1259509635
Short name T470
Test name
Test status
Simulation time 160204997 ps
CPU time 1.22 seconds
Started Mar 10 01:25:03 PM PDT 24
Finished Mar 10 01:25:04 PM PDT 24
Peak memory 200340 kb
Host smart-5149c9dc-93a9-422e-acd1-a905e1171f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259509635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1259509635
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3502598327
Short name T535
Test name
Test status
Simulation time 125067480 ps
CPU time 1.19 seconds
Started Mar 10 01:25:03 PM PDT 24
Finished Mar 10 01:25:05 PM PDT 24
Peak memory 200540 kb
Host smart-b12634fa-554a-4fd7-a4b4-bc8f8644f12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502598327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3502598327
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.953016547
Short name T7
Test name
Test status
Simulation time 16412325200 ps
CPU time 59.34 seconds
Started Mar 10 01:25:08 PM PDT 24
Finished Mar 10 01:26:08 PM PDT 24
Peak memory 200664 kb
Host smart-6c35c874-4d82-44c6-a5ef-0a46f64e61bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953016547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.953016547
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3742579495
Short name T352
Test name
Test status
Simulation time 139663428 ps
CPU time 1.84 seconds
Started Mar 10 01:25:03 PM PDT 24
Finished Mar 10 01:25:05 PM PDT 24
Peak memory 200396 kb
Host smart-8a825064-6051-410d-97ba-37c7815afdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742579495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3742579495
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.109008442
Short name T484
Test name
Test status
Simulation time 66868189 ps
CPU time 0.89 seconds
Started Mar 10 01:25:09 PM PDT 24
Finished Mar 10 01:25:10 PM PDT 24
Peak memory 200436 kb
Host smart-347f841c-9ee3-4467-b63d-2621baef3d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109008442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.109008442
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1425017685
Short name T167
Test name
Test status
Simulation time 76242635 ps
CPU time 0.85 seconds
Started Mar 10 01:25:11 PM PDT 24
Finished Mar 10 01:25:12 PM PDT 24
Peak memory 200316 kb
Host smart-5c547192-c1e2-48ff-8855-c119efda606f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425017685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1425017685
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.918561786
Short name T264
Test name
Test status
Simulation time 1883635325 ps
CPU time 7.52 seconds
Started Mar 10 01:25:10 PM PDT 24
Finished Mar 10 01:25:17 PM PDT 24
Peak memory 220868 kb
Host smart-bef7de98-d1f1-4f46-ab69-053646201c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918561786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.918561786
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3584928974
Short name T428
Test name
Test status
Simulation time 243692682 ps
CPU time 1.16 seconds
Started Mar 10 01:25:08 PM PDT 24
Finished Mar 10 01:25:09 PM PDT 24
Peak memory 217252 kb
Host smart-e462701f-975a-4f29-ad07-49521a05c1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584928974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3584928974
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1854305839
Short name T406
Test name
Test status
Simulation time 167491020 ps
CPU time 0.86 seconds
Started Mar 10 01:25:07 PM PDT 24
Finished Mar 10 01:25:08 PM PDT 24
Peak memory 200192 kb
Host smart-ceca0d97-77b8-4f3b-8cd8-f82bb9769839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854305839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1854305839
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3959677720
Short name T309
Test name
Test status
Simulation time 1565161459 ps
CPU time 6.23 seconds
Started Mar 10 01:25:07 PM PDT 24
Finished Mar 10 01:25:13 PM PDT 24
Peak memory 200660 kb
Host smart-d6271ff4-321f-490e-ad18-4e3f4614a000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959677720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3959677720
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1355747479
Short name T241
Test name
Test status
Simulation time 105744801 ps
CPU time 1.06 seconds
Started Mar 10 01:25:06 PM PDT 24
Finished Mar 10 01:25:07 PM PDT 24
Peak memory 200436 kb
Host smart-2768acff-c1e8-482b-a614-fe89f1cafe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355747479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1355747479
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3301649948
Short name T66
Test name
Test status
Simulation time 262441055 ps
CPU time 1.53 seconds
Started Mar 10 01:25:13 PM PDT 24
Finished Mar 10 01:25:14 PM PDT 24
Peak memory 200588 kb
Host smart-d5f59e9b-5d4e-4fe9-8697-373becede124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301649948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3301649948
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2345546042
Short name T413
Test name
Test status
Simulation time 2244591400 ps
CPU time 8.73 seconds
Started Mar 10 01:25:08 PM PDT 24
Finished Mar 10 01:25:17 PM PDT 24
Peak memory 200568 kb
Host smart-fdcdd0a0-034a-402a-8451-08154b8403bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345546042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2345546042
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1417486325
Short name T64
Test name
Test status
Simulation time 145705145 ps
CPU time 1.92 seconds
Started Mar 10 01:25:10 PM PDT 24
Finished Mar 10 01:25:12 PM PDT 24
Peak memory 200332 kb
Host smart-6a4044c5-83de-4e78-9b21-c68a72beebfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417486325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1417486325
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2031608223
Short name T541
Test name
Test status
Simulation time 125151435 ps
CPU time 1.05 seconds
Started Mar 10 01:25:08 PM PDT 24
Finished Mar 10 01:25:09 PM PDT 24
Peak memory 200384 kb
Host smart-3a935e95-ef1d-46bb-8474-06af36b69e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031608223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2031608223
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1465198783
Short name T332
Test name
Test status
Simulation time 75038931 ps
CPU time 0.79 seconds
Started Mar 10 01:25:05 PM PDT 24
Finished Mar 10 01:25:06 PM PDT 24
Peak memory 200232 kb
Host smart-40d4a452-e2bb-430a-8765-ef711ea00bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465198783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1465198783
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1620561089
Short name T472
Test name
Test status
Simulation time 1228160498 ps
CPU time 5.59 seconds
Started Mar 10 01:25:07 PM PDT 24
Finished Mar 10 01:25:13 PM PDT 24
Peak memory 220840 kb
Host smart-5ec076de-1aaf-4c9b-8519-07cba6466440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620561089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1620561089
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1866153893
Short name T61
Test name
Test status
Simulation time 244402585 ps
CPU time 1.13 seconds
Started Mar 10 01:25:07 PM PDT 24
Finished Mar 10 01:25:08 PM PDT 24
Peak memory 217164 kb
Host smart-dde68391-1d0a-4ca4-95b4-0a233810bd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866153893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1866153893
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2564535876
Short name T231
Test name
Test status
Simulation time 127735293 ps
CPU time 0.8 seconds
Started Mar 10 01:25:06 PM PDT 24
Finished Mar 10 01:25:07 PM PDT 24
Peak memory 200232 kb
Host smart-31dd1bab-70b8-4aff-84e6-21390b1ba612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564535876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2564535876
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.196347848
Short name T117
Test name
Test status
Simulation time 1972886327 ps
CPU time 6.64 seconds
Started Mar 10 01:25:09 PM PDT 24
Finished Mar 10 01:25:15 PM PDT 24
Peak memory 200604 kb
Host smart-3c90707f-4d6e-4621-ac7b-a4e6789eab3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196347848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.196347848
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3667320090
Short name T520
Test name
Test status
Simulation time 112491422 ps
CPU time 1 seconds
Started Mar 10 01:25:09 PM PDT 24
Finished Mar 10 01:25:10 PM PDT 24
Peak memory 200304 kb
Host smart-d9ef6903-a250-4f5a-91f9-cc3c64e5f63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667320090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3667320090
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1073227080
Short name T107
Test name
Test status
Simulation time 251284620 ps
CPU time 1.46 seconds
Started Mar 10 01:25:08 PM PDT 24
Finished Mar 10 01:25:10 PM PDT 24
Peak memory 200548 kb
Host smart-1e3bc0ce-3cfd-472b-983b-7c6065372597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073227080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1073227080
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.576972389
Short name T206
Test name
Test status
Simulation time 426903693 ps
CPU time 2.24 seconds
Started Mar 10 01:25:07 PM PDT 24
Finished Mar 10 01:25:09 PM PDT 24
Peak memory 208524 kb
Host smart-d404e124-38e4-4bac-af5b-d0272def6f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576972389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.576972389
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.962169040
Short name T149
Test name
Test status
Simulation time 263233481 ps
CPU time 1.55 seconds
Started Mar 10 01:25:06 PM PDT 24
Finished Mar 10 01:25:07 PM PDT 24
Peak memory 200408 kb
Host smart-33a5b544-59c3-4ff8-bb52-5bcd0da38a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962169040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.962169040
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1957876840
Short name T159
Test name
Test status
Simulation time 73069194 ps
CPU time 0.79 seconds
Started Mar 10 01:25:16 PM PDT 24
Finished Mar 10 01:25:17 PM PDT 24
Peak memory 200324 kb
Host smart-5d46cf00-cce0-45fe-8116-5eb4cb6f4b8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957876840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1957876840
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2585518611
Short name T52
Test name
Test status
Simulation time 1893509259 ps
CPU time 7.34 seconds
Started Mar 10 01:25:06 PM PDT 24
Finished Mar 10 01:25:13 PM PDT 24
Peak memory 217788 kb
Host smart-3f5bf6d3-a3cf-43aa-a844-df8f87950132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585518611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2585518611
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3625555692
Short name T232
Test name
Test status
Simulation time 244774287 ps
CPU time 1.21 seconds
Started Mar 10 01:25:11 PM PDT 24
Finished Mar 10 01:25:12 PM PDT 24
Peak memory 217284 kb
Host smart-2c89293c-ab54-4804-8722-d2e3218c24b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625555692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3625555692
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3987511846
Short name T382
Test name
Test status
Simulation time 174121385 ps
CPU time 0.87 seconds
Started Mar 10 01:25:07 PM PDT 24
Finished Mar 10 01:25:08 PM PDT 24
Peak memory 200180 kb
Host smart-dae18f20-e0ad-4a1f-a2b8-c278bc05ce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987511846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3987511846
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2011282987
Short name T138
Test name
Test status
Simulation time 2253057506 ps
CPU time 8.21 seconds
Started Mar 10 01:25:13 PM PDT 24
Finished Mar 10 01:25:21 PM PDT 24
Peak memory 200676 kb
Host smart-2b916933-6562-4dab-b2f0-90a0bf96c1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011282987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2011282987
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1495427211
Short name T353
Test name
Test status
Simulation time 97438573 ps
CPU time 1.02 seconds
Started Mar 10 01:25:09 PM PDT 24
Finished Mar 10 01:25:10 PM PDT 24
Peak memory 200324 kb
Host smart-886246fa-19b7-4ae1-9dd0-d20d74f32435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495427211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1495427211
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.122131128
Short name T46
Test name
Test status
Simulation time 198949508 ps
CPU time 1.37 seconds
Started Mar 10 01:25:06 PM PDT 24
Finished Mar 10 01:25:07 PM PDT 24
Peak memory 200420 kb
Host smart-90cd211e-2482-449a-a3d6-f39a2fa1e9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122131128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.122131128
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.4063536203
Short name T122
Test name
Test status
Simulation time 8728396549 ps
CPU time 29.98 seconds
Started Mar 10 01:25:05 PM PDT 24
Finished Mar 10 01:25:36 PM PDT 24
Peak memory 210380 kb
Host smart-52b12640-900e-4e0a-bf08-6d7248dffbd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063536203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4063536203
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3062050045
Short name T444
Test name
Test status
Simulation time 134860028 ps
CPU time 1.59 seconds
Started Mar 10 01:25:08 PM PDT 24
Finished Mar 10 01:25:09 PM PDT 24
Peak memory 208388 kb
Host smart-d63b8553-ca37-4e15-a6b4-8e786213ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062050045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3062050045
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4095335541
Short name T440
Test name
Test status
Simulation time 90231353 ps
CPU time 0.84 seconds
Started Mar 10 01:25:06 PM PDT 24
Finished Mar 10 01:25:07 PM PDT 24
Peak memory 200436 kb
Host smart-f357bbc1-48b7-4f24-a8ad-f836168cfa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095335541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4095335541
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2447430012
Short name T208
Test name
Test status
Simulation time 68278419 ps
CPU time 0.79 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 200216 kb
Host smart-8f71ba44-c7da-4066-af66-46011248d9f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447430012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2447430012
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3513651695
Short name T56
Test name
Test status
Simulation time 1227289032 ps
CPU time 5.84 seconds
Started Mar 10 01:24:35 PM PDT 24
Finished Mar 10 01:24:43 PM PDT 24
Peak memory 221284 kb
Host smart-226a718a-e9fc-4f07-b4ce-6f595bdee27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513651695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3513651695
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2708360848
Short name T235
Test name
Test status
Simulation time 243790948 ps
CPU time 1.08 seconds
Started Mar 10 01:24:33 PM PDT 24
Finished Mar 10 01:24:35 PM PDT 24
Peak memory 217144 kb
Host smart-25567598-151d-4d33-8a7e-30b8d75fae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708360848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2708360848
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1148215556
Short name T325
Test name
Test status
Simulation time 136647877 ps
CPU time 0.81 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 200228 kb
Host smart-7c7efcdb-5f34-45d6-863b-2706ac7b24d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148215556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1148215556
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.432251541
Short name T452
Test name
Test status
Simulation time 1377465309 ps
CPU time 6.06 seconds
Started Mar 10 01:24:34 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 200588 kb
Host smart-4b0ea385-5882-4841-aa0d-de5f8289b8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432251541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.432251541
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2238426280
Short name T74
Test name
Test status
Simulation time 16511159303 ps
CPU time 27.77 seconds
Started Mar 10 01:24:36 PM PDT 24
Finished Mar 10 01:25:05 PM PDT 24
Peak memory 217848 kb
Host smart-23a34210-5ca9-4178-8e50-9f5981fcbf1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238426280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2238426280
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2291575591
Short name T81
Test name
Test status
Simulation time 110372089 ps
CPU time 1.13 seconds
Started Mar 10 01:24:35 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 200444 kb
Host smart-3599600a-e294-41e1-a6e5-97b85d99fb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291575591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2291575591
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1381542070
Short name T391
Test name
Test status
Simulation time 107156220 ps
CPU time 1.18 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:39 PM PDT 24
Peak memory 200536 kb
Host smart-0337d617-dedc-4cae-a30b-be71c7bfd0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381542070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1381542070
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3063973639
Short name T265
Test name
Test status
Simulation time 899631044 ps
CPU time 4.28 seconds
Started Mar 10 01:24:40 PM PDT 24
Finished Mar 10 01:24:45 PM PDT 24
Peak memory 200604 kb
Host smart-493a6d82-6a7c-4347-95ea-403d8e240673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063973639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3063973639
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1110153785
Short name T169
Test name
Test status
Simulation time 141791642 ps
CPU time 1.77 seconds
Started Mar 10 01:24:34 PM PDT 24
Finished Mar 10 01:24:37 PM PDT 24
Peak memory 200376 kb
Host smart-15fdefc2-6dff-474d-b0f3-e281d87c1874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110153785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1110153785
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3589389599
Short name T407
Test name
Test status
Simulation time 103441444 ps
CPU time 0.93 seconds
Started Mar 10 01:24:40 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 200344 kb
Host smart-866b7d0c-a12f-4d31-822d-5dbf6a580d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589389599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3589389599
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.4232731516
Short name T409
Test name
Test status
Simulation time 74040398 ps
CPU time 0.8 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:15 PM PDT 24
Peak memory 200292 kb
Host smart-7dabff56-78f3-411a-a162-3b881472f0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232731516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.4232731516
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.581423811
Short name T36
Test name
Test status
Simulation time 1240327054 ps
CPU time 5.61 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 217092 kb
Host smart-4268ea20-f0ae-426d-b889-28e1bc3249a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581423811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.581423811
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2766932409
Short name T216
Test name
Test status
Simulation time 243356303 ps
CPU time 1.13 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:16 PM PDT 24
Peak memory 217292 kb
Host smart-f032c5ef-7b33-413a-98a5-b30209c06c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766932409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2766932409
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.993430587
Short name T463
Test name
Test status
Simulation time 161031023 ps
CPU time 0.84 seconds
Started Mar 10 01:25:15 PM PDT 24
Finished Mar 10 01:25:16 PM PDT 24
Peak memory 199956 kb
Host smart-2a7b7461-7209-4bdb-8ed6-c7b2f0cbf33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993430587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.993430587
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1814595763
Short name T137
Test name
Test status
Simulation time 1397283804 ps
CPU time 5.15 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:19 PM PDT 24
Peak memory 200536 kb
Host smart-26990151-9754-46d7-bdd1-2c29b23cf0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814595763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1814595763
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3922955449
Short name T237
Test name
Test status
Simulation time 107246440 ps
CPU time 1.05 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:20 PM PDT 24
Peak memory 200440 kb
Host smart-f4c9a845-66df-46f2-9de8-afb69e484464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922955449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3922955449
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1502096911
Short name T189
Test name
Test status
Simulation time 217610728 ps
CPU time 1.45 seconds
Started Mar 10 01:25:16 PM PDT 24
Finished Mar 10 01:25:17 PM PDT 24
Peak memory 200516 kb
Host smart-63968d5d-c89d-4923-8d09-e18df37a1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502096911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1502096911
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3831213494
Short name T50
Test name
Test status
Simulation time 62956380 ps
CPU time 0.8 seconds
Started Mar 10 01:25:11 PM PDT 24
Finished Mar 10 01:25:12 PM PDT 24
Peak memory 200436 kb
Host smart-28c66760-2989-490e-9817-1b41faf1efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831213494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3831213494
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1205212204
Short name T273
Test name
Test status
Simulation time 65156071 ps
CPU time 0.76 seconds
Started Mar 10 01:25:13 PM PDT 24
Finished Mar 10 01:25:14 PM PDT 24
Peak memory 200312 kb
Host smart-167991ae-fce9-417b-b7dd-ec37f1052f75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205212204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1205212204
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.818675675
Short name T11
Test name
Test status
Simulation time 2362007779 ps
CPU time 8.55 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:23 PM PDT 24
Peak memory 217876 kb
Host smart-46e470fc-fe71-4117-a604-71c587b5ee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818675675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.818675675
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.623179667
Short name T268
Test name
Test status
Simulation time 248784091 ps
CPU time 1.11 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:15 PM PDT 24
Peak memory 217208 kb
Host smart-7b230a45-1c95-462a-811f-50e35a13ca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623179667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.623179667
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.562841036
Short name T441
Test name
Test status
Simulation time 102029419 ps
CPU time 0.79 seconds
Started Mar 10 01:25:13 PM PDT 24
Finished Mar 10 01:25:14 PM PDT 24
Peak memory 200192 kb
Host smart-738984e0-a87d-4ac5-b4a0-2eb6eea7fd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562841036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.562841036
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.4177560149
Short name T140
Test name
Test status
Simulation time 1642250139 ps
CPU time 5.84 seconds
Started Mar 10 01:25:15 PM PDT 24
Finished Mar 10 01:25:21 PM PDT 24
Peak memory 200612 kb
Host smart-1985204c-ddfb-49cf-a24a-8ebfd5031b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177560149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4177560149
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1574733652
Short name T431
Test name
Test status
Simulation time 94607386 ps
CPU time 0.98 seconds
Started Mar 10 01:25:15 PM PDT 24
Finished Mar 10 01:25:17 PM PDT 24
Peak memory 200444 kb
Host smart-655fe1eb-b1fc-4ce5-9bd8-b708a560430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574733652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1574733652
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.267040117
Short name T156
Test name
Test status
Simulation time 248235625 ps
CPU time 1.6 seconds
Started Mar 10 01:25:17 PM PDT 24
Finished Mar 10 01:25:18 PM PDT 24
Peak memory 200544 kb
Host smart-595e79a9-b514-4e6e-b397-9f26337794b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267040117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.267040117
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1562864960
Short name T209
Test name
Test status
Simulation time 884086648 ps
CPU time 4.56 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:18 PM PDT 24
Peak memory 208880 kb
Host smart-d937ade9-e0f2-4e6a-86dc-172a7b5a74a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562864960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1562864960
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.349164248
Short name T458
Test name
Test status
Simulation time 130157448 ps
CPU time 1.75 seconds
Started Mar 10 01:25:15 PM PDT 24
Finished Mar 10 01:25:17 PM PDT 24
Peak memory 200344 kb
Host smart-15c53b77-9e49-4c54-83e3-24ae37ae3f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349164248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.349164248
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2057751502
Short name T316
Test name
Test status
Simulation time 124905451 ps
CPU time 1.13 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:20 PM PDT 24
Peak memory 200068 kb
Host smart-af2b8d55-bc9d-494c-9164-df70e9ec8d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057751502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2057751502
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2751802202
Short name T62
Test name
Test status
Simulation time 64899503 ps
CPU time 0.78 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:15 PM PDT 24
Peak memory 200296 kb
Host smart-56005ee3-2349-49f9-8a7d-1048bc8573e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751802202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2751802202
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2638430415
Short name T287
Test name
Test status
Simulation time 1905007508 ps
CPU time 7.56 seconds
Started Mar 10 01:25:15 PM PDT 24
Finished Mar 10 01:25:23 PM PDT 24
Peak memory 221700 kb
Host smart-5038d7a2-7343-405a-a3a6-5eaf41618b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638430415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2638430415
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3409015685
Short name T445
Test name
Test status
Simulation time 245024157 ps
CPU time 1.11 seconds
Started Mar 10 01:25:12 PM PDT 24
Finished Mar 10 01:25:13 PM PDT 24
Peak memory 217148 kb
Host smart-a1cc5ee2-28f0-4bcc-923a-1ba72dbf8cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409015685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3409015685
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2854999924
Short name T398
Test name
Test status
Simulation time 151984815 ps
CPU time 0.88 seconds
Started Mar 10 01:25:15 PM PDT 24
Finished Mar 10 01:25:16 PM PDT 24
Peak memory 200252 kb
Host smart-5fa9379e-3d68-4582-b3e5-c609e84f2519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854999924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2854999924
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1574860385
Short name T527
Test name
Test status
Simulation time 1551369003 ps
CPU time 6.19 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 199980 kb
Host smart-ce70be9d-0566-404d-8afd-e3ee58aaa9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574860385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1574860385
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.279204308
Short name T254
Test name
Test status
Simulation time 184539895 ps
CPU time 1.23 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:16 PM PDT 24
Peak memory 200412 kb
Host smart-24b82080-92c6-44cc-ace1-c430f67f2d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279204308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.279204308
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1580542823
Short name T538
Test name
Test status
Simulation time 252995382 ps
CPU time 1.56 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:15 PM PDT 24
Peak memory 200528 kb
Host smart-77938b75-20e1-4d5e-8c82-546859e13240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580542823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1580542823
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2096878686
Short name T251
Test name
Test status
Simulation time 3343723402 ps
CPU time 13.64 seconds
Started Mar 10 01:25:16 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 208848 kb
Host smart-f909374a-efbb-404a-a46c-60e475091e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096878686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2096878686
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3005305183
Short name T190
Test name
Test status
Simulation time 141579140 ps
CPU time 1.74 seconds
Started Mar 10 01:25:15 PM PDT 24
Finished Mar 10 01:25:17 PM PDT 24
Peak memory 208528 kb
Host smart-73b6efff-7775-44f0-a46e-0adec1dd966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005305183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3005305183
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.4240141341
Short name T294
Test name
Test status
Simulation time 146531455 ps
CPU time 1.28 seconds
Started Mar 10 01:25:16 PM PDT 24
Finished Mar 10 01:25:17 PM PDT 24
Peak memory 200436 kb
Host smart-944ae758-e042-484e-b83a-3188dd4345a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240141341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.4240141341
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3061767965
Short name T420
Test name
Test status
Simulation time 63864928 ps
CPU time 0.76 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:19 PM PDT 24
Peak memory 200280 kb
Host smart-33450277-d10e-4c34-bb77-6c77b75ab5c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061767965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3061767965
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1295974011
Short name T318
Test name
Test status
Simulation time 1226752082 ps
CPU time 5.97 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 217044 kb
Host smart-8f95a578-ac55-45ee-b569-20c1faeeddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295974011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1295974011
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.933521782
Short name T446
Test name
Test status
Simulation time 244621057 ps
CPU time 1.09 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 217224 kb
Host smart-4b1d1c05-eb99-491e-aa45-394025b01684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933521782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.933521782
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.589828370
Short name T510
Test name
Test status
Simulation time 102610776 ps
CPU time 0.89 seconds
Started Mar 10 01:25:12 PM PDT 24
Finished Mar 10 01:25:13 PM PDT 24
Peak memory 200176 kb
Host smart-f5af9ac3-4e19-49f2-821a-ebbcff9735cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589828370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.589828370
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2910075193
Short name T292
Test name
Test status
Simulation time 741872057 ps
CPU time 3.98 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:18 PM PDT 24
Peak memory 200608 kb
Host smart-49b827ff-c7d2-46c0-88e1-ce8bf556f8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910075193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2910075193
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3276841241
Short name T161
Test name
Test status
Simulation time 154995903 ps
CPU time 1.22 seconds
Started Mar 10 01:25:14 PM PDT 24
Finished Mar 10 01:25:15 PM PDT 24
Peak memory 200424 kb
Host smart-7f6d2a8c-db54-407c-bcc8-cbc593eddd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276841241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3276841241
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3034752494
Short name T544
Test name
Test status
Simulation time 123993464 ps
CPU time 1.13 seconds
Started Mar 10 01:25:13 PM PDT 24
Finished Mar 10 01:25:14 PM PDT 24
Peak memory 200532 kb
Host smart-cba2bf78-2fd0-494c-80b6-1fcc918f6196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034752494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3034752494
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2984657040
Short name T337
Test name
Test status
Simulation time 7150043185 ps
CPU time 26.05 seconds
Started Mar 10 01:25:17 PM PDT 24
Finished Mar 10 01:25:44 PM PDT 24
Peak memory 209412 kb
Host smart-0674fd18-44f8-40ad-9751-f12b3d41b3cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984657040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2984657040
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.4221132344
Short name T466
Test name
Test status
Simulation time 401107746 ps
CPU time 2.25 seconds
Started Mar 10 01:25:13 PM PDT 24
Finished Mar 10 01:25:15 PM PDT 24
Peak memory 200304 kb
Host smart-05465512-dd16-4489-b363-51b8101006d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221132344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.4221132344
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3863065305
Short name T179
Test name
Test status
Simulation time 124814641 ps
CPU time 1.08 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:20 PM PDT 24
Peak memory 199668 kb
Host smart-b509ee70-fe98-46b8-b260-7156cda84971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863065305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3863065305
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2687227048
Short name T456
Test name
Test status
Simulation time 1879373611 ps
CPU time 8.2 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:27 PM PDT 24
Peak memory 217092 kb
Host smart-501c8a25-ca0a-4c85-955a-00ec6ebd0be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687227048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2687227048
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3471133965
Short name T465
Test name
Test status
Simulation time 244288859 ps
CPU time 1.12 seconds
Started Mar 10 01:25:23 PM PDT 24
Finished Mar 10 01:25:24 PM PDT 24
Peak memory 217140 kb
Host smart-330c3acd-098c-4546-a064-8fc8c901ac1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471133965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3471133965
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1269404331
Short name T439
Test name
Test status
Simulation time 225740118 ps
CPU time 0.91 seconds
Started Mar 10 01:25:26 PM PDT 24
Finished Mar 10 01:25:27 PM PDT 24
Peak memory 200212 kb
Host smart-1f3eb876-9d17-442f-ab25-f97afdda5384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269404331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1269404331
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2794422223
Short name T399
Test name
Test status
Simulation time 1174504724 ps
CPU time 5.26 seconds
Started Mar 10 01:25:25 PM PDT 24
Finished Mar 10 01:25:30 PM PDT 24
Peak memory 200124 kb
Host smart-2d03e7c4-f180-458f-8281-d0ff1fe17882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794422223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2794422223
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.69527595
Short name T13
Test name
Test status
Simulation time 164284947 ps
CPU time 1.14 seconds
Started Mar 10 01:25:27 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 200432 kb
Host smart-32d8b51c-e6fb-44bd-bbe0-75f61991d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69527595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.69527595
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3443623021
Short name T106
Test name
Test status
Simulation time 194582265 ps
CPU time 1.44 seconds
Started Mar 10 01:25:21 PM PDT 24
Finished Mar 10 01:25:23 PM PDT 24
Peak memory 200536 kb
Host smart-a3fe773f-b291-445b-8484-7b6994cbcbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443623021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3443623021
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1018392740
Short name T532
Test name
Test status
Simulation time 4538568053 ps
CPU time 18.56 seconds
Started Mar 10 01:25:18 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200648 kb
Host smart-b3888051-1fce-4f95-9f20-21d93c5cfee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018392740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1018392740
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.168014787
Short name T155
Test name
Test status
Simulation time 123319069 ps
CPU time 1.59 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:26 PM PDT 24
Peak memory 208508 kb
Host smart-92ba7cb5-b96b-45be-a6a6-08fc10e70ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168014787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.168014787
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1740889422
Short name T435
Test name
Test status
Simulation time 111160746 ps
CPU time 1 seconds
Started Mar 10 01:25:25 PM PDT 24
Finished Mar 10 01:25:26 PM PDT 24
Peak memory 200440 kb
Host smart-58c4fdd8-c603-47c7-8ea8-2c37b6998b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740889422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1740889422
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.33371560
Short name T344
Test name
Test status
Simulation time 68273514 ps
CPU time 0.76 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 200304 kb
Host smart-14a698d7-20fa-420b-862b-a73c4c588927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33371560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.33371560
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.875821955
Short name T59
Test name
Test status
Simulation time 2192093909 ps
CPU time 8.05 seconds
Started Mar 10 01:25:21 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 217880 kb
Host smart-ec94a923-feed-4b13-893d-85d1341a429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875821955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.875821955
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.301227542
Short name T341
Test name
Test status
Simulation time 244648822 ps
CPU time 1.06 seconds
Started Mar 10 01:25:18 PM PDT 24
Finished Mar 10 01:25:19 PM PDT 24
Peak memory 217296 kb
Host smart-57ea4f23-f731-4018-ae7d-d2850a4af000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301227542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.301227542
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2107162176
Short name T297
Test name
Test status
Simulation time 99148664 ps
CPU time 0.78 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:20 PM PDT 24
Peak memory 200232 kb
Host smart-811109b1-7314-4a65-88b4-764a576aef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107162176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2107162176
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.4199443628
Short name T537
Test name
Test status
Simulation time 804246987 ps
CPU time 4.05 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:28 PM PDT 24
Peak memory 200564 kb
Host smart-3e16672e-0747-4b4c-b6a6-1f05736efcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199443628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4199443628
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3694095613
Short name T416
Test name
Test status
Simulation time 156992786 ps
CPU time 1.14 seconds
Started Mar 10 01:25:20 PM PDT 24
Finished Mar 10 01:25:21 PM PDT 24
Peak memory 200428 kb
Host smart-7d4719d3-937c-4976-a472-d639e153e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694095613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3694095613
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4036962618
Short name T220
Test name
Test status
Simulation time 197160094 ps
CPU time 1.46 seconds
Started Mar 10 01:25:21 PM PDT 24
Finished Mar 10 01:25:22 PM PDT 24
Peak memory 200564 kb
Host smart-ef560a36-2380-4cae-b569-b550f11f3d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036962618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4036962618
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.744872979
Short name T118
Test name
Test status
Simulation time 1530794101 ps
CPU time 7.49 seconds
Started Mar 10 01:25:23 PM PDT 24
Finished Mar 10 01:25:31 PM PDT 24
Peak memory 200560 kb
Host smart-f7abfb70-8871-49d4-8f5f-a945b894fafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744872979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.744872979
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3140466874
Short name T423
Test name
Test status
Simulation time 130397440 ps
CPU time 1.72 seconds
Started Mar 10 01:25:20 PM PDT 24
Finished Mar 10 01:25:22 PM PDT 24
Peak memory 208528 kb
Host smart-a5a07504-ee00-4141-9deb-3563fbedbd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140466874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3140466874
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3357491004
Short name T257
Test name
Test status
Simulation time 92998552 ps
CPU time 0.95 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:20 PM PDT 24
Peak memory 200436 kb
Host smart-2b34256e-8f66-4120-a97d-98a81d376bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357491004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3357491004
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1125063190
Short name T395
Test name
Test status
Simulation time 83290226 ps
CPU time 0.79 seconds
Started Mar 10 01:25:21 PM PDT 24
Finished Mar 10 01:25:22 PM PDT 24
Peak memory 200312 kb
Host smart-2d6096be-35a5-49e8-8de2-82049ac4d84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125063190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1125063190
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3366788509
Short name T321
Test name
Test status
Simulation time 243869224 ps
CPU time 1.16 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 217164 kb
Host smart-94818f03-6a00-4b0e-8ca6-da1a93c09ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366788509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3366788509
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.251109017
Short name T194
Test name
Test status
Simulation time 140165319 ps
CPU time 0.92 seconds
Started Mar 10 01:25:20 PM PDT 24
Finished Mar 10 01:25:21 PM PDT 24
Peak memory 200264 kb
Host smart-090a7791-15b6-4fef-abef-b5c47364a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251109017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.251109017
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2236128380
Short name T201
Test name
Test status
Simulation time 1216532388 ps
CPU time 5.17 seconds
Started Mar 10 01:25:18 PM PDT 24
Finished Mar 10 01:25:23 PM PDT 24
Peak memory 200648 kb
Host smart-5e56d2d6-d37a-4198-8c14-b74fb5b757c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236128380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2236128380
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1650608478
Short name T545
Test name
Test status
Simulation time 108569183 ps
CPU time 1.08 seconds
Started Mar 10 01:25:18 PM PDT 24
Finished Mar 10 01:25:19 PM PDT 24
Peak memory 200412 kb
Host smart-3df8c845-e767-4518-83da-71da382a4e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650608478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1650608478
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1088946194
Short name T362
Test name
Test status
Simulation time 188498252 ps
CPU time 1.38 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:20 PM PDT 24
Peak memory 200532 kb
Host smart-47183545-7d9d-4af4-b2f2-68f4389eab07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088946194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1088946194
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.614621217
Short name T430
Test name
Test status
Simulation time 7670464261 ps
CPU time 35.95 seconds
Started Mar 10 01:25:18 PM PDT 24
Finished Mar 10 01:25:54 PM PDT 24
Peak memory 208900 kb
Host smart-6de78a43-de98-49c2-bb2d-04dd35ec1981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614621217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.614621217
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2571951469
Short name T474
Test name
Test status
Simulation time 481363534 ps
CPU time 2.93 seconds
Started Mar 10 01:25:22 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 200372 kb
Host smart-e3352e24-c152-417b-b78f-169a14750afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571951469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2571951469
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2916935312
Short name T200
Test name
Test status
Simulation time 140161158 ps
CPU time 1.07 seconds
Started Mar 10 01:25:20 PM PDT 24
Finished Mar 10 01:25:22 PM PDT 24
Peak memory 200432 kb
Host smart-e4917fe8-d379-4c87-b425-f5b0de364a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916935312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2916935312
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1439837623
Short name T248
Test name
Test status
Simulation time 70313140 ps
CPU time 0.76 seconds
Started Mar 10 01:25:21 PM PDT 24
Finished Mar 10 01:25:22 PM PDT 24
Peak memory 200328 kb
Host smart-91ff1cbe-45d1-463b-9e1d-8b1a4b10f813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439837623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1439837623
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3604974866
Short name T462
Test name
Test status
Simulation time 1225628823 ps
CPU time 5.52 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 221348 kb
Host smart-28780493-6c94-4373-952c-4646108d8aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604974866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3604974866
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1419358568
Short name T358
Test name
Test status
Simulation time 244917392 ps
CPU time 1.19 seconds
Started Mar 10 01:25:23 PM PDT 24
Finished Mar 10 01:25:24 PM PDT 24
Peak memory 217224 kb
Host smart-51cdfaa5-4dad-4aa0-be8f-c6fa613a50ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419358568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1419358568
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2421504066
Short name T307
Test name
Test status
Simulation time 78949598 ps
CPU time 0.74 seconds
Started Mar 10 01:25:21 PM PDT 24
Finished Mar 10 01:25:22 PM PDT 24
Peak memory 200208 kb
Host smart-31c7976b-f29a-40cc-8d47-412bd4e6607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421504066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2421504066
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2878433162
Short name T523
Test name
Test status
Simulation time 1997211402 ps
CPU time 8.51 seconds
Started Mar 10 01:25:20 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 200660 kb
Host smart-a90a1aef-f083-46ce-826c-948f9b8e0338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878433162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2878433162
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3286240699
Short name T280
Test name
Test status
Simulation time 98740045 ps
CPU time 0.99 seconds
Started Mar 10 01:25:18 PM PDT 24
Finished Mar 10 01:25:19 PM PDT 24
Peak memory 200336 kb
Host smart-33ce6553-a6cf-4e3e-bf54-172d65ad4df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286240699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3286240699
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1895056900
Short name T310
Test name
Test status
Simulation time 198947608 ps
CPU time 1.41 seconds
Started Mar 10 01:25:25 PM PDT 24
Finished Mar 10 01:25:26 PM PDT 24
Peak memory 199972 kb
Host smart-e49050b6-07bc-4e7d-9f00-0f5e3ec6559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895056900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1895056900
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1364698135
Short name T110
Test name
Test status
Simulation time 1685590955 ps
CPU time 8.09 seconds
Started Mar 10 01:25:26 PM PDT 24
Finished Mar 10 01:25:34 PM PDT 24
Peak memory 200644 kb
Host smart-d39bfcad-c47f-4024-89ff-6f30726cd850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364698135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1364698135
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1770749044
Short name T457
Test name
Test status
Simulation time 430207589 ps
CPU time 2.31 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:26 PM PDT 24
Peak memory 208584 kb
Host smart-3cdbd70d-2ff9-4d47-9860-b7051fa2c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770749044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1770749044
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.15937397
Short name T84
Test name
Test status
Simulation time 222366350 ps
CPU time 1.37 seconds
Started Mar 10 01:25:22 PM PDT 24
Finished Mar 10 01:25:24 PM PDT 24
Peak memory 200452 kb
Host smart-91e69156-f1ea-4957-8561-386b291adf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15937397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.15937397
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1760166654
Short name T494
Test name
Test status
Simulation time 75573834 ps
CPU time 0.77 seconds
Started Mar 10 01:25:22 PM PDT 24
Finished Mar 10 01:25:23 PM PDT 24
Peak memory 200264 kb
Host smart-8a7df8db-24fd-4286-947c-7e89e47d519e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760166654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1760166654
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2397829479
Short name T51
Test name
Test status
Simulation time 1897180289 ps
CPU time 7.22 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:31 PM PDT 24
Peak memory 221884 kb
Host smart-4941bf31-f31b-4c77-ac36-48d38f4c3982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397829479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2397829479
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1180311018
Short name T393
Test name
Test status
Simulation time 244148082 ps
CPU time 1.13 seconds
Started Mar 10 01:25:27 PM PDT 24
Finished Mar 10 01:25:28 PM PDT 24
Peak memory 217224 kb
Host smart-aa090532-8188-4e59-8d1f-d7c4303ca7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180311018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1180311018
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2207488869
Short name T528
Test name
Test status
Simulation time 231566560 ps
CPU time 0.92 seconds
Started Mar 10 01:25:21 PM PDT 24
Finished Mar 10 01:25:22 PM PDT 24
Peak memory 200184 kb
Host smart-6c0d69b2-3f5b-4d8e-ba38-7d8fb85675e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207488869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2207488869
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.107678693
Short name T124
Test name
Test status
Simulation time 736495117 ps
CPU time 3.98 seconds
Started Mar 10 01:25:21 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 200604 kb
Host smart-35f559bb-3f2d-4cf6-ac59-9747021c321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107678693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.107678693
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2801426270
Short name T286
Test name
Test status
Simulation time 176200853 ps
CPU time 1.15 seconds
Started Mar 10 01:25:27 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 200440 kb
Host smart-b1e5b96b-1bfc-4b0f-97d6-daca3583223c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801426270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2801426270
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.575427382
Short name T186
Test name
Test status
Simulation time 203788029 ps
CPU time 1.45 seconds
Started Mar 10 01:25:21 PM PDT 24
Finished Mar 10 01:25:23 PM PDT 24
Peak memory 200536 kb
Host smart-dd57ffc6-7d61-43b8-b6ec-39d9119d995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575427382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.575427382
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2924288948
Short name T370
Test name
Test status
Simulation time 1750871337 ps
CPU time 6.3 seconds
Started Mar 10 01:25:27 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 208704 kb
Host smart-df0a5db7-01af-4829-8a7d-a2e5f5ee90a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924288948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2924288948
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.464156963
Short name T27
Test name
Test status
Simulation time 127662275 ps
CPU time 1.58 seconds
Started Mar 10 01:25:22 PM PDT 24
Finished Mar 10 01:25:24 PM PDT 24
Peak memory 208756 kb
Host smart-2c135037-ceb9-4299-a493-44cf03c78964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464156963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.464156963
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.951341456
Short name T525
Test name
Test status
Simulation time 180730860 ps
CPU time 1.25 seconds
Started Mar 10 01:25:19 PM PDT 24
Finished Mar 10 01:25:20 PM PDT 24
Peak memory 200424 kb
Host smart-ea1ef7e8-9241-4684-b92a-2873970aee82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951341456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.951341456
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3165529774
Short name T436
Test name
Test status
Simulation time 58869967 ps
CPU time 0.74 seconds
Started Mar 10 01:25:29 PM PDT 24
Finished Mar 10 01:25:30 PM PDT 24
Peak memory 200316 kb
Host smart-46ed219f-8813-4014-ab6c-76cc8245500c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165529774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3165529774
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.60464051
Short name T45
Test name
Test status
Simulation time 2341100952 ps
CPU time 8.09 seconds
Started Mar 10 01:25:22 PM PDT 24
Finished Mar 10 01:25:30 PM PDT 24
Peak memory 229840 kb
Host smart-c09ec6eb-a444-4eff-978e-b5faeb74356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60464051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.60464051
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2861241530
Short name T170
Test name
Test status
Simulation time 244236354 ps
CPU time 1.07 seconds
Started Mar 10 01:25:29 PM PDT 24
Finished Mar 10 01:25:31 PM PDT 24
Peak memory 217172 kb
Host smart-c4f6b12b-4aee-487d-ba35-af7fd530e896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861241530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2861241530
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.17652017
Short name T244
Test name
Test status
Simulation time 125526471 ps
CPU time 0.84 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 200180 kb
Host smart-b69ce719-747d-42c7-b8c3-aea9a6435660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17652017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.17652017
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.871738517
Short name T258
Test name
Test status
Simulation time 670833342 ps
CPU time 3.46 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:28 PM PDT 24
Peak memory 200648 kb
Host smart-3db4233e-8f2c-481d-84f4-593ca9a23446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871738517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.871738517
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1271177464
Short name T526
Test name
Test status
Simulation time 140206779 ps
CPU time 1.09 seconds
Started Mar 10 01:25:26 PM PDT 24
Finished Mar 10 01:25:27 PM PDT 24
Peak memory 200452 kb
Host smart-07b4a791-ce42-4649-bfd2-dd13410104e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271177464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1271177464
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3811115466
Short name T524
Test name
Test status
Simulation time 115814335 ps
CPU time 1.26 seconds
Started Mar 10 01:25:28 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 200548 kb
Host smart-ea6cda66-0bff-49b4-a6f3-b819d5b5eabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811115466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3811115466
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3920942894
Short name T340
Test name
Test status
Simulation time 6861535996 ps
CPU time 28.31 seconds
Started Mar 10 01:25:27 PM PDT 24
Finished Mar 10 01:25:56 PM PDT 24
Peak memory 209588 kb
Host smart-86812ef2-136a-4fe3-a6db-b183aafe76a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920942894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3920942894
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1984727830
Short name T176
Test name
Test status
Simulation time 488781559 ps
CPU time 2.64 seconds
Started Mar 10 01:25:26 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 200292 kb
Host smart-308618fb-f0ee-4b48-aab5-a686a1289901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984727830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1984727830
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3665530581
Short name T487
Test name
Test status
Simulation time 268910394 ps
CPU time 1.47 seconds
Started Mar 10 01:25:26 PM PDT 24
Finished Mar 10 01:25:28 PM PDT 24
Peak memory 200356 kb
Host smart-dd58e2fe-ca57-4404-9fd7-2506b9f497dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665530581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3665530581
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1424520621
Short name T261
Test name
Test status
Simulation time 90901399 ps
CPU time 0.84 seconds
Started Mar 10 01:24:36 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 200336 kb
Host smart-6a42d402-0ada-47a5-a477-d725bbb58204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424520621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1424520621
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1494380788
Short name T238
Test name
Test status
Simulation time 2355306701 ps
CPU time 8.59 seconds
Started Mar 10 01:24:38 PM PDT 24
Finished Mar 10 01:24:48 PM PDT 24
Peak memory 221916 kb
Host smart-8f68a0a9-2521-4e48-b800-3ce83e19d96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494380788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1494380788
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.584423170
Short name T171
Test name
Test status
Simulation time 243784936 ps
CPU time 1.08 seconds
Started Mar 10 01:24:36 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 217204 kb
Host smart-8654be74-f0ee-4442-b161-ea835bb14689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584423170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.584423170
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1512431327
Short name T16
Test name
Test status
Simulation time 232449170 ps
CPU time 0.9 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:39 PM PDT 24
Peak memory 200244 kb
Host smart-1f7a56dd-9d59-4157-9b40-6490bcc4b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512431327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1512431327
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.235025527
Short name T389
Test name
Test status
Simulation time 1573247415 ps
CPU time 6.39 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:45 PM PDT 24
Peak memory 200448 kb
Host smart-56a7f903-634c-467c-89fd-5507ed97ff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235025527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.235025527
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1072765325
Short name T76
Test name
Test status
Simulation time 16659410787 ps
CPU time 28.49 seconds
Started Mar 10 01:24:36 PM PDT 24
Finished Mar 10 01:25:07 PM PDT 24
Peak memory 217572 kb
Host smart-da18cb40-cd4c-4f51-a82e-c8217744b04a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072765325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1072765325
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4180331510
Short name T329
Test name
Test status
Simulation time 170953029 ps
CPU time 1.18 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:39 PM PDT 24
Peak memory 200456 kb
Host smart-c4446233-f9f0-4448-b67a-8d112f5bb9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180331510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4180331510
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1598300825
Short name T351
Test name
Test status
Simulation time 260326979 ps
CPU time 1.52 seconds
Started Mar 10 01:24:40 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 200576 kb
Host smart-2800d375-d214-4e5d-8b37-42424a72e2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598300825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1598300825
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1897793880
Short name T536
Test name
Test status
Simulation time 4266112624 ps
CPU time 17.79 seconds
Started Mar 10 01:24:36 PM PDT 24
Finished Mar 10 01:24:55 PM PDT 24
Peak memory 208840 kb
Host smart-a2700bc9-d966-4b0f-9d83-bbf28ab2ece6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897793880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1897793880
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2998214412
Short name T86
Test name
Test status
Simulation time 281123720 ps
CPU time 1.96 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 200356 kb
Host smart-06153164-cec0-4c7b-afc8-8c3755348525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998214412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2998214412
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1783077569
Short name T199
Test name
Test status
Simulation time 126413363 ps
CPU time 1.08 seconds
Started Mar 10 01:24:36 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 200460 kb
Host smart-71bce6e1-197b-46ff-86de-5c38a802ccd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783077569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1783077569
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.4134597601
Short name T53
Test name
Test status
Simulation time 104119388 ps
CPU time 0.96 seconds
Started Mar 10 01:25:26 PM PDT 24
Finished Mar 10 01:25:27 PM PDT 24
Peak memory 200212 kb
Host smart-7497fd03-c02e-42d2-845d-ada33dbe9cbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134597601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.4134597601
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2972860854
Short name T392
Test name
Test status
Simulation time 1899747475 ps
CPU time 8.08 seconds
Started Mar 10 01:25:29 PM PDT 24
Finished Mar 10 01:25:38 PM PDT 24
Peak memory 216536 kb
Host smart-964c18b7-fe6a-404b-9edd-136a9c290350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972860854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2972860854
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3215847117
Short name T9
Test name
Test status
Simulation time 243784014 ps
CPU time 1.14 seconds
Started Mar 10 01:25:28 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 217176 kb
Host smart-d1e00ff6-65fb-4eea-9d55-3fa743ece5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215847117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3215847117
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1904775023
Short name T15
Test name
Test status
Simulation time 167700157 ps
CPU time 0.85 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 200092 kb
Host smart-9fa6637a-2de1-4581-8186-ee26e115ded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904775023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1904775023
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.103490989
Short name T116
Test name
Test status
Simulation time 1113334581 ps
CPU time 5.5 seconds
Started Mar 10 01:25:28 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200612 kb
Host smart-4a97eae1-6a42-408b-a456-31cf9adfadfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103490989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.103490989
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1721428229
Short name T311
Test name
Test status
Simulation time 167573591 ps
CPU time 1.21 seconds
Started Mar 10 01:25:29 PM PDT 24
Finished Mar 10 01:25:31 PM PDT 24
Peak memory 200348 kb
Host smart-b3320a1f-e47a-44f8-ad83-93f395e9dd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721428229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1721428229
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3229974811
Short name T543
Test name
Test status
Simulation time 261209522 ps
CPU time 1.52 seconds
Started Mar 10 01:25:25 PM PDT 24
Finished Mar 10 01:25:26 PM PDT 24
Peak memory 200540 kb
Host smart-4426d84f-89a0-4253-88cc-b331755ac5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229974811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3229974811
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3756525796
Short name T142
Test name
Test status
Simulation time 13875220412 ps
CPU time 50.5 seconds
Started Mar 10 01:25:26 PM PDT 24
Finished Mar 10 01:26:17 PM PDT 24
Peak memory 209500 kb
Host smart-6654b35a-fada-469a-bb2a-ec57b00b6fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756525796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3756525796
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3239054029
Short name T354
Test name
Test status
Simulation time 367283740 ps
CPU time 2.43 seconds
Started Mar 10 01:25:25 PM PDT 24
Finished Mar 10 01:25:28 PM PDT 24
Peak memory 200372 kb
Host smart-8e9357b2-507d-4673-9d18-383dcb636768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239054029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3239054029
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2717577287
Short name T539
Test name
Test status
Simulation time 157410017 ps
CPU time 1.11 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 200432 kb
Host smart-e6eaeb35-5949-4890-94b4-279a43176640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717577287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2717577287
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3615030907
Short name T54
Test name
Test status
Simulation time 64565407 ps
CPU time 0.76 seconds
Started Mar 10 01:25:24 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 200320 kb
Host smart-eafc91ed-84e7-4b7e-a8f0-b47f8d3fb156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615030907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3615030907
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3582304604
Short name T29
Test name
Test status
Simulation time 2372091904 ps
CPU time 9.48 seconds
Started Mar 10 01:25:25 PM PDT 24
Finished Mar 10 01:25:34 PM PDT 24
Peak memory 217852 kb
Host smart-e8dd61a3-f9a8-4530-944b-e0238f42c35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582304604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3582304604
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2784986877
Short name T453
Test name
Test status
Simulation time 245950429 ps
CPU time 1.04 seconds
Started Mar 10 01:25:22 PM PDT 24
Finished Mar 10 01:25:24 PM PDT 24
Peak memory 217204 kb
Host smart-ce0f800e-d496-480f-a6ba-572ca6c90bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784986877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2784986877
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.73629435
Short name T20
Test name
Test status
Simulation time 185666810 ps
CPU time 0.85 seconds
Started Mar 10 01:25:22 PM PDT 24
Finished Mar 10 01:25:23 PM PDT 24
Peak memory 200236 kb
Host smart-27503699-47a7-4817-976b-08bb067e5a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73629435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.73629435
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1930532805
Short name T173
Test name
Test status
Simulation time 1111917483 ps
CPU time 4.61 seconds
Started Mar 10 01:25:28 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200648 kb
Host smart-a9bd99bc-6153-44ba-bc98-a52aa7ed189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930532805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1930532805
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3297417706
Short name T492
Test name
Test status
Simulation time 148524979 ps
CPU time 1.12 seconds
Started Mar 10 01:25:30 PM PDT 24
Finished Mar 10 01:25:32 PM PDT 24
Peak memory 200400 kb
Host smart-41ef5ad4-cc5b-42cc-b89f-31570632829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297417706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3297417706
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1502153416
Short name T333
Test name
Test status
Simulation time 192250202 ps
CPU time 1.4 seconds
Started Mar 10 01:25:23 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 200484 kb
Host smart-80fcb648-5186-4b8d-bf87-1e098e7291d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502153416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1502153416
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.799326300
Short name T424
Test name
Test status
Simulation time 6316129178 ps
CPU time 23.54 seconds
Started Mar 10 01:25:29 PM PDT 24
Finished Mar 10 01:25:53 PM PDT 24
Peak memory 200616 kb
Host smart-68554a2c-30d1-46cc-b697-ca122bf76bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799326300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.799326300
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1804274005
Short name T283
Test name
Test status
Simulation time 298777442 ps
CPU time 1.94 seconds
Started Mar 10 01:25:30 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 208640 kb
Host smart-b8d124e4-fffc-4424-81db-6434fee78a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804274005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1804274005
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.648319135
Short name T481
Test name
Test status
Simulation time 92412236 ps
CPU time 0.9 seconds
Started Mar 10 01:25:28 PM PDT 24
Finished Mar 10 01:25:30 PM PDT 24
Peak memory 200392 kb
Host smart-cd2b78c2-26c3-4c8f-802f-ec073c6cdd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648319135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.648319135
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3340953972
Short name T447
Test name
Test status
Simulation time 62613416 ps
CPU time 0.85 seconds
Started Mar 10 01:25:30 PM PDT 24
Finished Mar 10 01:25:31 PM PDT 24
Peak memory 200232 kb
Host smart-720ed73c-2ae3-42d2-a0df-c4e772e6fee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340953972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3340953972
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.4187893736
Short name T405
Test name
Test status
Simulation time 1231491022 ps
CPU time 5.22 seconds
Started Mar 10 01:25:34 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 216516 kb
Host smart-72a0878b-1650-4a5c-a592-3f9be11a51ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187893736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4187893736
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1401366145
Short name T205
Test name
Test status
Simulation time 244206125 ps
CPU time 1.25 seconds
Started Mar 10 01:25:32 PM PDT 24
Finished Mar 10 01:25:34 PM PDT 24
Peak memory 217296 kb
Host smart-db47bddb-7b38-436b-8296-50295cb25a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401366145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1401366145
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4196682513
Short name T19
Test name
Test status
Simulation time 194072875 ps
CPU time 0.97 seconds
Started Mar 10 01:25:25 PM PDT 24
Finished Mar 10 01:25:27 PM PDT 24
Peak memory 200252 kb
Host smart-3a74d464-85c5-4c23-8cf9-a8d54a4895cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196682513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4196682513
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.179843529
Short name T356
Test name
Test status
Simulation time 1613594455 ps
CPU time 6.87 seconds
Started Mar 10 01:25:30 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200548 kb
Host smart-7abd9c98-701d-40ae-ab05-b79b9c366f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179843529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.179843529
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1350416516
Short name T153
Test name
Test status
Simulation time 150203954 ps
CPU time 1.18 seconds
Started Mar 10 01:25:32 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200444 kb
Host smart-51ea542c-1336-4c48-a4fd-71b8159cd8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350416516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1350416516
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3255936759
Short name T250
Test name
Test status
Simulation time 119703881 ps
CPU time 1.19 seconds
Started Mar 10 01:25:29 PM PDT 24
Finished Mar 10 01:25:31 PM PDT 24
Peak memory 200544 kb
Host smart-c39c4d76-fe13-41ba-ae01-4b0a32706042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255936759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3255936759
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2594402788
Short name T300
Test name
Test status
Simulation time 2119390898 ps
CPU time 7.9 seconds
Started Mar 10 01:25:31 PM PDT 24
Finished Mar 10 01:25:40 PM PDT 24
Peak memory 200560 kb
Host smart-f7ea4ebc-b859-48f8-b138-4128b088f97d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594402788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2594402788
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.792735242
Short name T233
Test name
Test status
Simulation time 421865941 ps
CPU time 2.35 seconds
Started Mar 10 01:25:26 PM PDT 24
Finished Mar 10 01:25:29 PM PDT 24
Peak memory 208552 kb
Host smart-8fc01e2d-76f0-4c39-a710-528c07e206a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792735242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.792735242
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3658329949
Short name T497
Test name
Test status
Simulation time 81991253 ps
CPU time 0.83 seconds
Started Mar 10 01:25:31 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200288 kb
Host smart-496a6a5d-bdac-49fe-ab0e-9bde94fc0cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658329949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3658329949
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.168736970
Short name T31
Test name
Test status
Simulation time 1225947763 ps
CPU time 5.75 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:40 PM PDT 24
Peak memory 217168 kb
Host smart-9db0ac01-f328-41cb-b396-b63bb8517c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168736970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.168736970
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1189407168
Short name T175
Test name
Test status
Simulation time 244032220 ps
CPU time 1.02 seconds
Started Mar 10 01:25:34 PM PDT 24
Finished Mar 10 01:25:35 PM PDT 24
Peak memory 217120 kb
Host smart-9db6df95-cbaf-4044-ba67-8a9bf0f8798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189407168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1189407168
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1971033960
Short name T239
Test name
Test status
Simulation time 183444116 ps
CPU time 0.92 seconds
Started Mar 10 01:25:29 PM PDT 24
Finished Mar 10 01:25:30 PM PDT 24
Peak memory 200232 kb
Host smart-f952d7b1-cffa-444b-b339-bad07441d2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971033960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1971033960
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3288187462
Short name T414
Test name
Test status
Simulation time 636000375 ps
CPU time 3.71 seconds
Started Mar 10 01:25:28 PM PDT 24
Finished Mar 10 01:25:32 PM PDT 24
Peak memory 200548 kb
Host smart-565de639-6950-461b-aaa9-0e771a39ef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288187462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3288187462
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.572860503
Short name T371
Test name
Test status
Simulation time 163033573 ps
CPU time 1.19 seconds
Started Mar 10 01:25:31 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200396 kb
Host smart-694aa840-0633-4b6e-b975-3554628e0a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572860503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.572860503
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3969457421
Short name T500
Test name
Test status
Simulation time 115367042 ps
CPU time 1.31 seconds
Started Mar 10 01:25:30 PM PDT 24
Finished Mar 10 01:25:32 PM PDT 24
Peak memory 200580 kb
Host smart-1e35e90f-6259-4ff9-9217-1eeca0e5e7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969457421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3969457421
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.449731549
Short name T141
Test name
Test status
Simulation time 8523231729 ps
CPU time 29.29 seconds
Started Mar 10 01:25:29 PM PDT 24
Finished Mar 10 01:25:59 PM PDT 24
Peak memory 208872 kb
Host smart-35a65ad8-2c7e-4465-9370-241585d271ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449731549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.449731549
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2428791232
Short name T299
Test name
Test status
Simulation time 137449282 ps
CPU time 1.86 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:35 PM PDT 24
Peak memory 200312 kb
Host smart-a1668d20-0199-457f-a395-07836b128ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428791232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2428791232
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2376859269
Short name T28
Test name
Test status
Simulation time 124579420 ps
CPU time 0.99 seconds
Started Mar 10 01:25:30 PM PDT 24
Finished Mar 10 01:25:32 PM PDT 24
Peak memory 200460 kb
Host smart-6b2d30ab-c4ea-45af-b014-b8e7c5b05571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376859269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2376859269
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.845622796
Short name T60
Test name
Test status
Simulation time 64749107 ps
CPU time 0.76 seconds
Started Mar 10 01:25:31 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200296 kb
Host smart-05318a3d-eea4-4522-88ce-e70a15029676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845622796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.845622796
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3618683873
Short name T44
Test name
Test status
Simulation time 1220743923 ps
CPU time 5.69 seconds
Started Mar 10 01:25:32 PM PDT 24
Finished Mar 10 01:25:38 PM PDT 24
Peak memory 221796 kb
Host smart-1bde0da6-8ae6-42ae-83e7-e7d5aa23f07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618683873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3618683873
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2070345366
Short name T514
Test name
Test status
Simulation time 244358603 ps
CPU time 1.16 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:35 PM PDT 24
Peak memory 217208 kb
Host smart-5261b5b8-6321-45cf-91e4-2aea2f7b6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070345366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2070345366
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2328603479
Short name T218
Test name
Test status
Simulation time 130735983 ps
CPU time 0.81 seconds
Started Mar 10 01:25:31 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200264 kb
Host smart-8b842063-80a7-4bae-9233-33e5026c6137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328603479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2328603479
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3199230431
Short name T207
Test name
Test status
Simulation time 1251879099 ps
CPU time 4.99 seconds
Started Mar 10 01:25:35 PM PDT 24
Finished Mar 10 01:25:41 PM PDT 24
Peak memory 200596 kb
Host smart-9b672150-83c2-4061-8d57-0ccdfb5eab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199230431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3199230431
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2921114937
Short name T225
Test name
Test status
Simulation time 176530816 ps
CPU time 1.27 seconds
Started Mar 10 01:25:32 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200428 kb
Host smart-3d9b9427-6f68-4768-94ed-cb69e3ee089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921114937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2921114937
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1565757187
Short name T383
Test name
Test status
Simulation time 122822736 ps
CPU time 1.19 seconds
Started Mar 10 01:25:32 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200548 kb
Host smart-b9bc1b42-f3f1-4d32-a3bf-c519d6e692ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565757187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1565757187
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2291757391
Short name T109
Test name
Test status
Simulation time 460748498 ps
CPU time 2.73 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:36 PM PDT 24
Peak memory 200144 kb
Host smart-d3a00c44-4c47-42c8-baa4-485457f48e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291757391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2291757391
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.318234509
Short name T366
Test name
Test status
Simulation time 244875634 ps
CPU time 1.52 seconds
Started Mar 10 01:25:31 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200356 kb
Host smart-06b86d5f-a75e-4791-93e1-a2a6ca1868a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318234509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.318234509
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1652023356
Short name T490
Test name
Test status
Simulation time 59941351 ps
CPU time 0.74 seconds
Started Mar 10 01:25:30 PM PDT 24
Finished Mar 10 01:25:31 PM PDT 24
Peak memory 200292 kb
Host smart-4e97dcea-ceb9-4dcb-9ae3-5330116de6e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652023356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1652023356
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3950015663
Short name T32
Test name
Test status
Simulation time 1223578754 ps
CPU time 5.73 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 220828 kb
Host smart-a92458e5-2fee-472e-8294-e01a401c00f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950015663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3950015663
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4131507343
Short name T290
Test name
Test status
Simulation time 244523933 ps
CPU time 1.07 seconds
Started Mar 10 01:25:30 PM PDT 24
Finished Mar 10 01:25:32 PM PDT 24
Peak memory 217256 kb
Host smart-c60e8290-8646-44fd-8683-6b3a1a1d8551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131507343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4131507343
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1207259805
Short name T181
Test name
Test status
Simulation time 213831367 ps
CPU time 0.93 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:34 PM PDT 24
Peak memory 200224 kb
Host smart-77f9dc22-4836-4311-a274-03ea8446b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207259805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1207259805
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.822875693
Short name T442
Test name
Test status
Simulation time 1425717459 ps
CPU time 6.15 seconds
Started Mar 10 01:25:30 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200632 kb
Host smart-10b0c475-8836-469c-bb77-4cbd64d2d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822875693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.822875693
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1629505767
Short name T284
Test name
Test status
Simulation time 115398942 ps
CPU time 1.04 seconds
Started Mar 10 01:25:31 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200420 kb
Host smart-791d77e6-0da5-4081-874b-78551fe962d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629505767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1629505767
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3986747946
Short name T47
Test name
Test status
Simulation time 221915626 ps
CPU time 1.55 seconds
Started Mar 10 01:25:31 PM PDT 24
Finished Mar 10 01:25:33 PM PDT 24
Peak memory 200572 kb
Host smart-956cb5b1-409e-4786-9310-ca1b70906bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986747946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3986747946
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.4176644871
Short name T228
Test name
Test status
Simulation time 7643051530 ps
CPU time 29.58 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:26:03 PM PDT 24
Peak memory 200708 kb
Host smart-980b659d-05e0-4ae2-9731-5e8fbef1d17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176644871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.4176644871
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3813943577
Short name T185
Test name
Test status
Simulation time 356418040 ps
CPU time 2.13 seconds
Started Mar 10 01:25:31 PM PDT 24
Finished Mar 10 01:25:34 PM PDT 24
Peak memory 200284 kb
Host smart-bdebae6d-8d93-47d7-94fb-a9ad130a76e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813943577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3813943577
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.4232050037
Short name T508
Test name
Test status
Simulation time 147038383 ps
CPU time 1.25 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:34 PM PDT 24
Peak memory 200232 kb
Host smart-afac1ec9-1550-4f8e-9ad8-fbe53adcc08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232050037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.4232050037
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3930132058
Short name T459
Test name
Test status
Simulation time 70067745 ps
CPU time 0.79 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 200232 kb
Host smart-34cb11a9-381e-43ee-9244-4036fd39761f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930132058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3930132058
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3700663819
Short name T204
Test name
Test status
Simulation time 257370903 ps
CPU time 1.06 seconds
Started Mar 10 01:25:35 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 217288 kb
Host smart-65e89b14-e50b-496f-996f-5f240f95fb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700663819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3700663819
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.674381734
Short name T227
Test name
Test status
Simulation time 157402788 ps
CPU time 0.93 seconds
Started Mar 10 01:25:35 PM PDT 24
Finished Mar 10 01:25:36 PM PDT 24
Peak memory 200208 kb
Host smart-4273ac19-151e-4dc7-8035-29c6dbef950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674381734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.674381734
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3339526892
Short name T448
Test name
Test status
Simulation time 845753855 ps
CPU time 4.59 seconds
Started Mar 10 01:25:35 PM PDT 24
Finished Mar 10 01:25:40 PM PDT 24
Peak memory 200568 kb
Host smart-a07c7bb7-7407-4af3-8d80-1169c2c9a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339526892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3339526892
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1590432916
Short name T108
Test name
Test status
Simulation time 160408056 ps
CPU time 1.16 seconds
Started Mar 10 01:25:34 PM PDT 24
Finished Mar 10 01:25:35 PM PDT 24
Peak memory 200332 kb
Host smart-65be4dbd-b301-40d6-9972-ecbe45011fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590432916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1590432916
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2123902132
Short name T369
Test name
Test status
Simulation time 231317727 ps
CPU time 1.41 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:35 PM PDT 24
Peak memory 200520 kb
Host smart-ae0a5475-dc70-4a8d-aba2-d8b847da9134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123902132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2123902132
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3124792861
Short name T380
Test name
Test status
Simulation time 11085866494 ps
CPU time 45.08 seconds
Started Mar 10 01:25:34 PM PDT 24
Finished Mar 10 01:26:20 PM PDT 24
Peak memory 200644 kb
Host smart-3c129b0c-c72c-45d7-a451-0ae4f088ac44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124792861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3124792861
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1876017732
Short name T412
Test name
Test status
Simulation time 124194556 ps
CPU time 1.64 seconds
Started Mar 10 01:25:37 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 208448 kb
Host smart-b7d5030c-d5a0-40f0-a079-bb9fa6f5f5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876017732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1876017732
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.339124672
Short name T518
Test name
Test status
Simulation time 227082860 ps
CPU time 1.47 seconds
Started Mar 10 01:25:35 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200436 kb
Host smart-3c37550d-f963-4135-b5eb-41cf33acbc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339124672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.339124672
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.201917282
Short name T421
Test name
Test status
Simulation time 67247660 ps
CPU time 0.76 seconds
Started Mar 10 01:25:35 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200316 kb
Host smart-070c6ab6-64ba-4691-a4e2-4236e605346a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201917282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.201917282
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1883080672
Short name T367
Test name
Test status
Simulation time 2349639206 ps
CPU time 8.35 seconds
Started Mar 10 01:25:35 PM PDT 24
Finished Mar 10 01:25:44 PM PDT 24
Peak memory 217824 kb
Host smart-773a12e9-f3ef-42c5-999e-ff839523be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883080672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1883080672
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2180260367
Short name T464
Test name
Test status
Simulation time 244958300 ps
CPU time 1.08 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:35 PM PDT 24
Peak memory 217172 kb
Host smart-e1008ecc-655b-4bcd-9dfe-84a7a19b09bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180260367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2180260367
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2977059510
Short name T23
Test name
Test status
Simulation time 77660454 ps
CPU time 0.71 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 200188 kb
Host smart-837ba30b-4dde-4f7d-95b6-aac48007fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977059510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2977059510
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1661852242
Short name T193
Test name
Test status
Simulation time 1777327699 ps
CPU time 7.28 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:25:46 PM PDT 24
Peak memory 200400 kb
Host smart-ed6ef35e-6bd6-4d63-8558-cc0ebe58bc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661852242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1661852242
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1519689161
Short name T359
Test name
Test status
Simulation time 152442937 ps
CPU time 1.17 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:25:40 PM PDT 24
Peak memory 200424 kb
Host smart-f1a56e83-3676-432a-9d33-58f5ced63f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519689161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1519689161
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1868212337
Short name T327
Test name
Test status
Simulation time 253654902 ps
CPU time 1.49 seconds
Started Mar 10 01:25:35 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200516 kb
Host smart-5ed4b35e-5dcf-4e1c-95f7-0308b3122ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868212337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1868212337
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4158616944
Short name T306
Test name
Test status
Simulation time 6808007734 ps
CPU time 26.91 seconds
Started Mar 10 01:25:37 PM PDT 24
Finished Mar 10 01:26:04 PM PDT 24
Peak memory 210448 kb
Host smart-0f1a6aa9-d94a-4edf-a60f-90dd45a9201c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158616944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4158616944
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.4260515687
Short name T345
Test name
Test status
Simulation time 151233294 ps
CPU time 1.89 seconds
Started Mar 10 01:25:41 PM PDT 24
Finished Mar 10 01:25:43 PM PDT 24
Peak memory 200276 kb
Host smart-d4086215-2674-48a9-a1a2-5e6235d4520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260515687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.4260515687
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3752387191
Short name T245
Test name
Test status
Simulation time 155327982 ps
CPU time 1.24 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 200364 kb
Host smart-7e403052-1cfe-445a-b0ab-70b32b8fa393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752387191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3752387191
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2619128115
Short name T1
Test name
Test status
Simulation time 55198729 ps
CPU time 0.72 seconds
Started Mar 10 01:25:39 PM PDT 24
Finished Mar 10 01:25:41 PM PDT 24
Peak memory 200296 kb
Host smart-2db979df-700a-4a4c-8135-b6841ec0a99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619128115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2619128115
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1558942117
Short name T357
Test name
Test status
Simulation time 2368722993 ps
CPU time 8.34 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:25:47 PM PDT 24
Peak memory 217440 kb
Host smart-7a8e9fbb-ccaa-473d-883b-8f294b351772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558942117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1558942117
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3944356091
Short name T388
Test name
Test status
Simulation time 244864894 ps
CPU time 1.06 seconds
Started Mar 10 01:25:33 PM PDT 24
Finished Mar 10 01:25:35 PM PDT 24
Peak memory 217296 kb
Host smart-4c2ebbcc-0f28-4158-bfa1-82c45492025f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944356091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3944356091
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1607004602
Short name T17
Test name
Test status
Simulation time 101327160 ps
CPU time 0.81 seconds
Started Mar 10 01:25:36 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200228 kb
Host smart-791a0e27-0f30-41da-9636-aeb2bfa39ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607004602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1607004602
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1795250066
Short name T304
Test name
Test status
Simulation time 1886165511 ps
CPU time 7.26 seconds
Started Mar 10 01:25:36 PM PDT 24
Finished Mar 10 01:25:43 PM PDT 24
Peak memory 200620 kb
Host smart-a6323bed-ab3b-4568-81ec-04c6b249b77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795250066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1795250066
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.548616568
Short name T404
Test name
Test status
Simulation time 176282089 ps
CPU time 1.18 seconds
Started Mar 10 01:25:43 PM PDT 24
Finished Mar 10 01:25:45 PM PDT 24
Peak memory 200412 kb
Host smart-ed7dd916-0b83-4613-8c96-dcfd69c5e00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548616568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.548616568
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.618029929
Short name T111
Test name
Test status
Simulation time 259568258 ps
CPU time 1.67 seconds
Started Mar 10 01:25:34 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200520 kb
Host smart-402f277e-df5f-44bf-af43-948b2e84eaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618029929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.618029929
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.639847249
Short name T437
Test name
Test status
Simulation time 5831115521 ps
CPU time 22.34 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:26:00 PM PDT 24
Peak memory 208784 kb
Host smart-fb28a96b-64e1-4545-a618-d16b484545e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639847249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.639847249
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2162520439
Short name T471
Test name
Test status
Simulation time 359526994 ps
CPU time 2.35 seconds
Started Mar 10 01:25:34 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200352 kb
Host smart-91565ae7-6467-48b3-8386-c61d51c2831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162520439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2162520439
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1721689343
Short name T252
Test name
Test status
Simulation time 69870179 ps
CPU time 0.82 seconds
Started Mar 10 01:25:36 PM PDT 24
Finished Mar 10 01:25:37 PM PDT 24
Peak memory 200436 kb
Host smart-b52ebeda-445c-4298-9d78-611b06e3bf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721689343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1721689343
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3686106342
Short name T165
Test name
Test status
Simulation time 71189518 ps
CPU time 0.83 seconds
Started Mar 10 01:25:40 PM PDT 24
Finished Mar 10 01:25:42 PM PDT 24
Peak memory 200312 kb
Host smart-4ca01833-f886-4e8c-a650-a406c982b01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686106342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3686106342
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3346509124
Short name T502
Test name
Test status
Simulation time 2153797890 ps
CPU time 8.24 seconds
Started Mar 10 01:25:39 PM PDT 24
Finished Mar 10 01:25:48 PM PDT 24
Peak memory 218384 kb
Host smart-2493e637-9bdd-43e2-9966-ac80c607ba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346509124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3346509124
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3050944912
Short name T262
Test name
Test status
Simulation time 246704826 ps
CPU time 1.05 seconds
Started Mar 10 01:25:40 PM PDT 24
Finished Mar 10 01:25:42 PM PDT 24
Peak memory 217276 kb
Host smart-8d597514-b2e6-4449-ad32-21e11cfdea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050944912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3050944912
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2360571099
Short name T443
Test name
Test status
Simulation time 205737000 ps
CPU time 0.93 seconds
Started Mar 10 01:25:40 PM PDT 24
Finished Mar 10 01:25:42 PM PDT 24
Peak memory 200232 kb
Host smart-6ca58d08-c883-4097-a1c9-e1999cfb8f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360571099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2360571099
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1269947707
Short name T374
Test name
Test status
Simulation time 1637456014 ps
CPU time 6.43 seconds
Started Mar 10 01:25:32 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 200828 kb
Host smart-23f7ed63-1207-42e8-9928-4753d277c089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269947707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1269947707
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.159926376
Short name T278
Test name
Test status
Simulation time 182739772 ps
CPU time 1.35 seconds
Started Mar 10 01:25:39 PM PDT 24
Finished Mar 10 01:25:41 PM PDT 24
Peak memory 200444 kb
Host smart-1d28b66a-63ea-4900-b784-3dda44a6e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159926376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.159926376
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1426161746
Short name T255
Test name
Test status
Simulation time 130374667 ps
CPU time 1.22 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:25:40 PM PDT 24
Peak memory 200320 kb
Host smart-7b0de7df-e4e4-4e02-89b6-3a2bd94f4ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426161746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1426161746
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2426367628
Short name T426
Test name
Test status
Simulation time 3353440611 ps
CPU time 13.51 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:58 PM PDT 24
Peak memory 208848 kb
Host smart-4692ab8f-2bee-403a-91e9-4cc5e88c8ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426367628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2426367628
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2078175315
Short name T222
Test name
Test status
Simulation time 389453557 ps
CPU time 2.48 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:25:41 PM PDT 24
Peak memory 200304 kb
Host smart-54281ffd-ffc5-4bd1-9954-10f22453c3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078175315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2078175315
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1459435703
Short name T334
Test name
Test status
Simulation time 86355975 ps
CPU time 0.94 seconds
Started Mar 10 01:25:38 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 200360 kb
Host smart-1bfea39b-a974-4a9c-9eec-cc82125fc6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459435703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1459435703
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1611985222
Short name T267
Test name
Test status
Simulation time 76441491 ps
CPU time 0.78 seconds
Started Mar 10 01:24:41 PM PDT 24
Finished Mar 10 01:24:43 PM PDT 24
Peak memory 200324 kb
Host smart-3caf11ba-5d99-4e70-9b54-1745e01f6923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611985222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1611985222
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1379643936
Short name T57
Test name
Test status
Simulation time 1882790503 ps
CPU time 7.7 seconds
Started Mar 10 01:24:40 PM PDT 24
Finished Mar 10 01:24:49 PM PDT 24
Peak memory 217168 kb
Host smart-3ae66d22-b2ee-4365-8c61-becb569ed865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379643936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1379643936
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1051361691
Short name T479
Test name
Test status
Simulation time 244371541 ps
CPU time 1.08 seconds
Started Mar 10 01:24:39 PM PDT 24
Finished Mar 10 01:24:41 PM PDT 24
Peak memory 217296 kb
Host smart-cea26e08-fef9-4e8c-966f-d9b0f468cb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051361691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1051361691
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2180128125
Short name T355
Test name
Test status
Simulation time 191231637 ps
CPU time 0.91 seconds
Started Mar 10 01:24:36 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 200220 kb
Host smart-a12df9c7-8c01-495d-a027-309687eb38a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180128125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2180128125
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1707402286
Short name T65
Test name
Test status
Simulation time 1134745623 ps
CPU time 5.41 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:44 PM PDT 24
Peak memory 200536 kb
Host smart-55c97587-90a5-4aa4-91a0-b333b7313539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707402286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1707402286
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1891762044
Short name T75
Test name
Test status
Simulation time 8524019912 ps
CPU time 13.01 seconds
Started Mar 10 01:24:43 PM PDT 24
Finished Mar 10 01:24:57 PM PDT 24
Peak memory 216892 kb
Host smart-f5045e87-3e33-4e3d-83ef-34254b02fc5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891762044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1891762044
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.328552196
Short name T425
Test name
Test status
Simulation time 172488892 ps
CPU time 1.27 seconds
Started Mar 10 01:24:40 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 200352 kb
Host smart-97f9d6fd-9315-40f8-85fa-fc9c40f36ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328552196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.328552196
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.570973641
Short name T275
Test name
Test status
Simulation time 197694551 ps
CPU time 1.39 seconds
Started Mar 10 01:24:36 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 200512 kb
Host smart-64538770-a6f6-4b49-b71a-9ab04ebf619b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570973641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.570973641
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2519031613
Short name T123
Test name
Test status
Simulation time 7687214582 ps
CPU time 28.84 seconds
Started Mar 10 01:24:41 PM PDT 24
Finished Mar 10 01:25:11 PM PDT 24
Peak memory 209444 kb
Host smart-e002cbbb-9b20-438c-80c9-16d9f661ed41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519031613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2519031613
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.16773364
Short name T256
Test name
Test status
Simulation time 295285726 ps
CPU time 2.14 seconds
Started Mar 10 01:24:37 PM PDT 24
Finished Mar 10 01:24:40 PM PDT 24
Peak memory 208528 kb
Host smart-5a850cc1-63d6-4d19-bd29-a59b64faac1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16773364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.16773364
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.967130347
Short name T14
Test name
Test status
Simulation time 131536766 ps
CPU time 1.01 seconds
Started Mar 10 01:24:36 PM PDT 24
Finished Mar 10 01:24:38 PM PDT 24
Peak memory 200360 kb
Host smart-0cbbb3b7-332a-4d52-9cc6-6d5f8c74e5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967130347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.967130347
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2264630652
Short name T263
Test name
Test status
Simulation time 69859205 ps
CPU time 0.76 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:45 PM PDT 24
Peak memory 200312 kb
Host smart-48cc0b83-8a25-4b09-b513-5d3cc22c2bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264630652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2264630652
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1426942442
Short name T272
Test name
Test status
Simulation time 2352932298 ps
CPU time 8.55 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:53 PM PDT 24
Peak memory 221588 kb
Host smart-3d85c4f6-52bb-4215-bb4a-25a159ede571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426942442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1426942442
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.976873933
Short name T534
Test name
Test status
Simulation time 244076417 ps
CPU time 1.16 seconds
Started Mar 10 01:25:41 PM PDT 24
Finished Mar 10 01:25:42 PM PDT 24
Peak memory 217148 kb
Host smart-f7885aaf-0c8a-470e-babf-59e6395dc80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976873933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.976873933
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4148485675
Short name T203
Test name
Test status
Simulation time 72614415 ps
CPU time 0.75 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:25:48 PM PDT 24
Peak memory 200208 kb
Host smart-5e3ae589-9716-4a94-b1c4-a1efb1a17340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148485675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4148485675
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2201906689
Short name T260
Test name
Test status
Simulation time 889575338 ps
CPU time 4.27 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200512 kb
Host smart-01e3d0f3-094e-4345-91ed-0158bc511c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201906689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2201906689
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2600730555
Short name T372
Test name
Test status
Simulation time 100276817 ps
CPU time 1.05 seconds
Started Mar 10 01:25:42 PM PDT 24
Finished Mar 10 01:25:43 PM PDT 24
Peak memory 200412 kb
Host smart-14b348cf-c975-409c-82c8-a629962180e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600730555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2600730555
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3917547831
Short name T418
Test name
Test status
Simulation time 248489043 ps
CPU time 1.52 seconds
Started Mar 10 01:25:46 PM PDT 24
Finished Mar 10 01:25:48 PM PDT 24
Peak memory 200596 kb
Host smart-6ead6755-5291-43a4-b9e5-026aa9ebf6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917547831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3917547831
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2807691479
Short name T530
Test name
Test status
Simulation time 1725540106 ps
CPU time 6.42 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:50 PM PDT 24
Peak memory 200604 kb
Host smart-c175b1a4-8b2e-4799-8a89-7278785dda6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807691479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2807691479
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3206878362
Short name T320
Test name
Test status
Simulation time 474319983 ps
CPU time 2.48 seconds
Started Mar 10 01:25:40 PM PDT 24
Finished Mar 10 01:25:43 PM PDT 24
Peak memory 200364 kb
Host smart-14d8fb45-b32d-4af1-a66b-929d22116c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206878362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3206878362
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.969728082
Short name T188
Test name
Test status
Simulation time 125660349 ps
CPU time 1.13 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:46 PM PDT 24
Peak memory 200412 kb
Host smart-f297ca3f-2943-410c-ab8d-5de4eec4374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969728082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.969728082
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3620449001
Short name T150
Test name
Test status
Simulation time 68951925 ps
CPU time 0.72 seconds
Started Mar 10 01:25:43 PM PDT 24
Finished Mar 10 01:25:44 PM PDT 24
Peak memory 200240 kb
Host smart-d3a35134-0d56-4d9f-9d65-50bd72eb0fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620449001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3620449001
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2104526845
Short name T363
Test name
Test status
Simulation time 1238297531 ps
CPU time 5.24 seconds
Started Mar 10 01:25:43 PM PDT 24
Finished Mar 10 01:25:48 PM PDT 24
Peak memory 216592 kb
Host smart-146c6c4a-0b8c-4f94-9ba1-fb2648a7756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104526845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2104526845
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2598251459
Short name T315
Test name
Test status
Simulation time 244868252 ps
CPU time 1.18 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 217276 kb
Host smart-42383d3c-9ceb-46e7-a073-8549a67d92e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598251459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2598251459
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1673752292
Short name T531
Test name
Test status
Simulation time 162898472 ps
CPU time 0.81 seconds
Started Mar 10 01:25:40 PM PDT 24
Finished Mar 10 01:25:42 PM PDT 24
Peak memory 200232 kb
Host smart-af6d2769-2f38-4acf-b245-40e25dda9b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673752292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1673752292
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.4072955456
Short name T505
Test name
Test status
Simulation time 1397954864 ps
CPU time 5.88 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:50 PM PDT 24
Peak memory 200512 kb
Host smart-a1715138-1364-486a-b593-ae85f1c42b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072955456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.4072955456
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2727772860
Short name T63
Test name
Test status
Simulation time 176740572 ps
CPU time 1.15 seconds
Started Mar 10 01:25:41 PM PDT 24
Finished Mar 10 01:25:43 PM PDT 24
Peak memory 200392 kb
Host smart-faa9d1f9-5405-48cd-aaeb-fd80577f7d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727772860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2727772860
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1032948918
Short name T282
Test name
Test status
Simulation time 126786288 ps
CPU time 1.23 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200564 kb
Host smart-817a687c-8441-4f84-839f-cd5448ebdad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032948918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1032948918
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2071497480
Short name T308
Test name
Test status
Simulation time 6610374831 ps
CPU time 30.25 seconds
Started Mar 10 01:25:41 PM PDT 24
Finished Mar 10 01:26:11 PM PDT 24
Peak memory 208792 kb
Host smart-7ac832f7-65ef-4616-9bac-4d93bb3ee614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071497480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2071497480
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2835517438
Short name T419
Test name
Test status
Simulation time 317577243 ps
CPU time 2.24 seconds
Started Mar 10 01:25:42 PM PDT 24
Finished Mar 10 01:25:45 PM PDT 24
Peak memory 208548 kb
Host smart-c69167a6-dd5d-4836-8448-a67a7bb02393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835517438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2835517438
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3778732477
Short name T305
Test name
Test status
Simulation time 124154938 ps
CPU time 1.07 seconds
Started Mar 10 01:25:42 PM PDT 24
Finished Mar 10 01:25:43 PM PDT 24
Peak memory 200336 kb
Host smart-157ebfea-8c36-4dd5-9782-4837288d0ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778732477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3778732477
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1447772232
Short name T151
Test name
Test status
Simulation time 86997413 ps
CPU time 0.85 seconds
Started Mar 10 01:25:48 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200272 kb
Host smart-8e528f5a-2263-45ba-9c90-16f2710d42ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447772232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1447772232
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.4224895925
Short name T58
Test name
Test status
Simulation time 1227405824 ps
CPU time 5.7 seconds
Started Mar 10 01:25:45 PM PDT 24
Finished Mar 10 01:25:50 PM PDT 24
Peak memory 217044 kb
Host smart-2f747029-e76a-4600-8ac1-9c4ba2d70b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224895925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4224895925
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3807986952
Short name T184
Test name
Test status
Simulation time 244195910 ps
CPU time 1.13 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 217192 kb
Host smart-bcb77627-70f4-4295-b27b-220a25055e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807986952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3807986952
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.491799152
Short name T489
Test name
Test status
Simulation time 153065927 ps
CPU time 0.87 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:45 PM PDT 24
Peak memory 200152 kb
Host smart-79cfbc0a-7611-4d99-b599-498afd3c35b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491799152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.491799152
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.859972635
Short name T381
Test name
Test status
Simulation time 869295284 ps
CPU time 4.51 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200636 kb
Host smart-b89c9301-ab0d-4b7c-9849-de01b16abd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859972635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.859972635
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1896164560
Short name T178
Test name
Test status
Simulation time 151817829 ps
CPU time 1.08 seconds
Started Mar 10 01:25:45 PM PDT 24
Finished Mar 10 01:25:46 PM PDT 24
Peak memory 200444 kb
Host smart-2debe623-66f2-48e3-9135-8e55b21da231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896164560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1896164560
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3899563508
Short name T347
Test name
Test status
Simulation time 190868770 ps
CPU time 1.43 seconds
Started Mar 10 01:25:42 PM PDT 24
Finished Mar 10 01:25:43 PM PDT 24
Peak memory 200548 kb
Host smart-8888e22f-475f-4fa1-9fb1-1ed38ff0e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899563508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3899563508
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2314308310
Short name T451
Test name
Test status
Simulation time 2193631862 ps
CPU time 7.99 seconds
Started Mar 10 01:25:43 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 200660 kb
Host smart-689a994f-57cc-4c07-933a-9567e18bcb13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314308310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2314308310
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2898268000
Short name T427
Test name
Test status
Simulation time 339902694 ps
CPU time 2.28 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:46 PM PDT 24
Peak memory 200376 kb
Host smart-968789fe-970b-4d73-9a06-b60f4757e79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898268000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2898268000
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3575424324
Short name T271
Test name
Test status
Simulation time 228822119 ps
CPU time 1.4 seconds
Started Mar 10 01:25:43 PM PDT 24
Finished Mar 10 01:25:45 PM PDT 24
Peak memory 200444 kb
Host smart-b7c5d6ea-8d30-4c0c-8ca4-16ea617315e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575424324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3575424324
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3393157005
Short name T338
Test name
Test status
Simulation time 106242072 ps
CPU time 0.81 seconds
Started Mar 10 01:25:48 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200272 kb
Host smart-b8341f79-862a-4ea5-9a62-fb13d9d64dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393157005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3393157005
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3675811177
Short name T40
Test name
Test status
Simulation time 1228172946 ps
CPU time 5.78 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:25:54 PM PDT 24
Peak memory 221788 kb
Host smart-134aa1a3-8ea2-41cb-a842-9dd6c7753bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675811177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3675811177
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.86221050
Short name T313
Test name
Test status
Simulation time 243531152 ps
CPU time 1.08 seconds
Started Mar 10 01:25:46 PM PDT 24
Finished Mar 10 01:25:48 PM PDT 24
Peak memory 217188 kb
Host smart-78bcae64-8e76-44c3-8606-d1cc916b4c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86221050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.86221050
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.408621633
Short name T177
Test name
Test status
Simulation time 142580852 ps
CPU time 0.8 seconds
Started Mar 10 01:25:45 PM PDT 24
Finished Mar 10 01:25:46 PM PDT 24
Peak memory 200236 kb
Host smart-5a4c32b5-5feb-49d9-ac55-a413f150c941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408621633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.408621633
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.922212345
Short name T364
Test name
Test status
Simulation time 1706843638 ps
CPU time 6.11 seconds
Started Mar 10 01:25:45 PM PDT 24
Finished Mar 10 01:25:52 PM PDT 24
Peak memory 200584 kb
Host smart-7f517cf6-ad92-40e6-9904-6455d8eb8150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922212345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.922212345
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1191213293
Short name T516
Test name
Test status
Simulation time 99160592 ps
CPU time 1.1 seconds
Started Mar 10 01:25:50 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 200436 kb
Host smart-768b0cc9-eb0a-4019-90b7-3e0a59b5a914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191213293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1191213293
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3907833455
Short name T394
Test name
Test status
Simulation time 233791392 ps
CPU time 1.43 seconds
Started Mar 10 01:25:45 PM PDT 24
Finished Mar 10 01:25:46 PM PDT 24
Peak memory 200440 kb
Host smart-d3b3430e-df87-40e7-ab43-8ae9a43e57bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907833455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3907833455
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1422263342
Short name T522
Test name
Test status
Simulation time 2228430910 ps
CPU time 7.62 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:25:55 PM PDT 24
Peak memory 200660 kb
Host smart-92f62408-ed77-4fdf-ad27-a3c131d8f133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422263342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1422263342
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.411096736
Short name T113
Test name
Test status
Simulation time 150732181 ps
CPU time 1.85 seconds
Started Mar 10 01:25:46 PM PDT 24
Finished Mar 10 01:25:48 PM PDT 24
Peak memory 200360 kb
Host smart-f1469005-efd6-422c-8faa-ae08cf50196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411096736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.411096736
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3075626576
Short name T480
Test name
Test status
Simulation time 93190866 ps
CPU time 0.84 seconds
Started Mar 10 01:25:43 PM PDT 24
Finished Mar 10 01:25:45 PM PDT 24
Peak memory 200468 kb
Host smart-c6994444-b70e-40a6-9921-f560ce53cb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075626576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3075626576
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3103543559
Short name T335
Test name
Test status
Simulation time 64492972 ps
CPU time 0.8 seconds
Started Mar 10 01:25:48 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200260 kb
Host smart-80942711-4e95-4131-83eb-037ca316610b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103543559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3103543559
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2369993843
Short name T504
Test name
Test status
Simulation time 1222752279 ps
CPU time 5.85 seconds
Started Mar 10 01:25:45 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 218328 kb
Host smart-2b02d2a4-8767-47f9-ac2a-55dcc11c2614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369993843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2369993843
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.10949273
Short name T402
Test name
Test status
Simulation time 244333562 ps
CPU time 1.01 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 217252 kb
Host smart-db128cbc-894a-41cb-a063-a17332c381f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10949273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.10949273
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.693874656
Short name T422
Test name
Test status
Simulation time 168955316 ps
CPU time 0.86 seconds
Started Mar 10 01:25:49 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 200240 kb
Host smart-633086f6-42c0-40d6-938d-1f15acfe759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693874656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.693874656
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1514020408
Short name T293
Test name
Test status
Simulation time 1351576070 ps
CPU time 5.16 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:57 PM PDT 24
Peak memory 200616 kb
Host smart-4f0e3632-9ae7-4206-8be4-645842cccc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514020408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1514020408
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.188180030
Short name T215
Test name
Test status
Simulation time 156737854 ps
CPU time 1.13 seconds
Started Mar 10 01:25:48 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200360 kb
Host smart-d5a78957-d9a9-4ed7-95c4-80e4800a2a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188180030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.188180030
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1453790558
Short name T224
Test name
Test status
Simulation time 197998706 ps
CPU time 1.4 seconds
Started Mar 10 01:25:45 PM PDT 24
Finished Mar 10 01:25:47 PM PDT 24
Peak memory 200516 kb
Host smart-ed7e7922-05cf-436f-8012-8c1fb8d5baf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453790558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1453790558
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1813179007
Short name T240
Test name
Test status
Simulation time 2251915648 ps
CPU time 8.8 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:26:02 PM PDT 24
Peak memory 200564 kb
Host smart-3025fc84-fd04-4794-9490-69fec59d048b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813179007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1813179007
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4079417551
Short name T403
Test name
Test status
Simulation time 298162199 ps
CPU time 2.12 seconds
Started Mar 10 01:25:48 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 208588 kb
Host smart-d8e7508f-50ed-47a1-89c9-2e32b6acf9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079417551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4079417551
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.885834716
Short name T163
Test name
Test status
Simulation time 133445589 ps
CPU time 1.04 seconds
Started Mar 10 01:25:48 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200360 kb
Host smart-0435e55c-4d9b-4b5b-bdc6-84ad2a62e95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885834716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.885834716
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4180803873
Short name T180
Test name
Test status
Simulation time 64775570 ps
CPU time 0.78 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:45 PM PDT 24
Peak memory 200324 kb
Host smart-5a8737b5-77fc-437d-a1e1-029b0ec4cf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180803873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4180803873
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2776258761
Short name T42
Test name
Test status
Simulation time 1890335459 ps
CPU time 7.09 seconds
Started Mar 10 01:25:45 PM PDT 24
Finished Mar 10 01:25:53 PM PDT 24
Peak memory 216676 kb
Host smart-cc7b7cb0-a14e-4e73-9ed9-afb47f62424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776258761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2776258761
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1627843351
Short name T411
Test name
Test status
Simulation time 244776886 ps
CPU time 1.16 seconds
Started Mar 10 01:25:52 PM PDT 24
Finished Mar 10 01:25:53 PM PDT 24
Peak memory 217228 kb
Host smart-e7fe2aae-7eb3-422f-b28d-5325f8fcf46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627843351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1627843351
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1946669445
Short name T361
Test name
Test status
Simulation time 108646825 ps
CPU time 0.8 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:52 PM PDT 24
Peak memory 200236 kb
Host smart-ff9a4fbb-d045-423c-bb39-2dff8f028f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946669445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1946669445
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2159826448
Short name T360
Test name
Test status
Simulation time 895662395 ps
CPU time 4.97 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200596 kb
Host smart-d96bd9f0-a382-4775-bd9b-6dae776e8e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159826448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2159826448
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2982924425
Short name T482
Test name
Test status
Simulation time 166030956 ps
CPU time 1.21 seconds
Started Mar 10 01:25:46 PM PDT 24
Finished Mar 10 01:25:48 PM PDT 24
Peak memory 200444 kb
Host smart-23d22eed-3432-4620-b8f9-5ded45b73dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982924425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2982924425
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.160747284
Short name T192
Test name
Test status
Simulation time 227488896 ps
CPU time 1.49 seconds
Started Mar 10 01:25:43 PM PDT 24
Finished Mar 10 01:25:45 PM PDT 24
Peak memory 200540 kb
Host smart-2e84c68c-dfd7-47dc-bae0-db45931f7caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160747284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.160747284
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3057622924
Short name T119
Test name
Test status
Simulation time 4443934171 ps
CPU time 18.9 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:26:07 PM PDT 24
Peak memory 208912 kb
Host smart-bfb74279-2c32-4465-abba-24140d4b6a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057622924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3057622924
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.628476803
Short name T26
Test name
Test status
Simulation time 414743745 ps
CPU time 2.46 seconds
Started Mar 10 01:25:46 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200328 kb
Host smart-7dd3d26d-f2fe-4ab8-9009-5c59e082b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628476803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.628476803
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.472315887
Short name T148
Test name
Test status
Simulation time 247149177 ps
CPU time 1.4 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200416 kb
Host smart-d28b771d-96e7-4b1f-9b0b-c629c2b2a952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472315887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.472315887
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3440872798
Short name T187
Test name
Test status
Simulation time 67739981 ps
CPU time 0.81 seconds
Started Mar 10 01:25:50 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 200256 kb
Host smart-2921f236-265e-441a-8a1f-73bb3ac1e9b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440872798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3440872798
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3681507696
Short name T454
Test name
Test status
Simulation time 1899720857 ps
CPU time 7.28 seconds
Started Mar 10 01:25:44 PM PDT 24
Finished Mar 10 01:25:52 PM PDT 24
Peak memory 217108 kb
Host smart-fc8dc188-8458-4dcf-9714-a7b2a036ce06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681507696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3681507696
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3564489815
Short name T277
Test name
Test status
Simulation time 243999794 ps
CPU time 1.08 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:53 PM PDT 24
Peak memory 217224 kb
Host smart-a2cadef6-aa8f-4c97-bc29-6299920fd5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564489815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3564489815
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3270014074
Short name T197
Test name
Test status
Simulation time 88196025 ps
CPU time 0.72 seconds
Started Mar 10 01:25:46 PM PDT 24
Finished Mar 10 01:25:47 PM PDT 24
Peak memory 200180 kb
Host smart-1db73991-fbc4-4ac1-9b48-a86a7bbebe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270014074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3270014074
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2759272444
Short name T478
Test name
Test status
Simulation time 1414452404 ps
CPU time 5.36 seconds
Started Mar 10 01:25:47 PM PDT 24
Finished Mar 10 01:25:53 PM PDT 24
Peak memory 200608 kb
Host smart-ed3c05f8-0e32-4635-8169-274c725e9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759272444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2759272444
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.20442951
Short name T477
Test name
Test status
Simulation time 97776183 ps
CPU time 1.01 seconds
Started Mar 10 01:25:49 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 200440 kb
Host smart-6ec77d20-fb9e-4754-9a52-da5c3a5e0d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20442951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.20442951
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2733907487
Short name T83
Test name
Test status
Simulation time 121122818 ps
CPU time 1.33 seconds
Started Mar 10 01:25:48 PM PDT 24
Finished Mar 10 01:25:49 PM PDT 24
Peak memory 200500 kb
Host smart-e945ee68-c4b0-4ec2-8278-3be3aa601156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733907487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2733907487
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2303922531
Short name T483
Test name
Test status
Simulation time 6326127003 ps
CPU time 22.22 seconds
Started Mar 10 01:25:49 PM PDT 24
Finished Mar 10 01:26:12 PM PDT 24
Peak memory 208880 kb
Host smart-a4c991f1-d725-4905-8c98-9366e3906ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303922531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2303922531
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.441968881
Short name T158
Test name
Test status
Simulation time 438287770 ps
CPU time 2.37 seconds
Started Mar 10 01:25:52 PM PDT 24
Finished Mar 10 01:25:54 PM PDT 24
Peak memory 200352 kb
Host smart-51134a64-39ce-4aa9-98d8-1261428e0fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441968881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.441968881
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.795476587
Short name T8
Test name
Test status
Simulation time 136954804 ps
CPU time 1.13 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:53 PM PDT 24
Peak memory 200440 kb
Host smart-f117f4b6-5d25-4bdc-a699-d7db93e8b53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795476587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.795476587
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3401897350
Short name T473
Test name
Test status
Simulation time 66913953 ps
CPU time 0.85 seconds
Started Mar 10 01:25:55 PM PDT 24
Finished Mar 10 01:25:56 PM PDT 24
Peak memory 200320 kb
Host smart-c570e167-595b-44bd-b81f-14382cda5ac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401897350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3401897350
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2383798510
Short name T387
Test name
Test status
Simulation time 2338805332 ps
CPU time 9.03 seconds
Started Mar 10 01:25:50 PM PDT 24
Finished Mar 10 01:25:59 PM PDT 24
Peak memory 217792 kb
Host smart-bbb469e7-537d-42a0-8da4-3b0f263d1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383798510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2383798510
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1417733832
Short name T301
Test name
Test status
Simulation time 243816817 ps
CPU time 1.09 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:52 PM PDT 24
Peak memory 217196 kb
Host smart-f2e7cff6-e164-410d-a26f-c37bb3848737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417733832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1417733832
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4276673956
Short name T296
Test name
Test status
Simulation time 126696124 ps
CPU time 0.79 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:53 PM PDT 24
Peak memory 200252 kb
Host smart-2efbdd4f-3b54-4f71-bb5d-0f615e9df549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276673956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4276673956
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.906611567
Short name T125
Test name
Test status
Simulation time 946333669 ps
CPU time 4.64 seconds
Started Mar 10 01:25:50 PM PDT 24
Finished Mar 10 01:25:55 PM PDT 24
Peak memory 200540 kb
Host smart-30865e3f-1c8d-495c-ac6e-e402a7a8f9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906611567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.906611567
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.817722492
Short name T467
Test name
Test status
Simulation time 150493633 ps
CPU time 1.12 seconds
Started Mar 10 01:25:49 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 200396 kb
Host smart-3e4d5b62-0297-4ede-9dd9-16173c14aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817722492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.817722492
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3269807850
Short name T266
Test name
Test status
Simulation time 114029377 ps
CPU time 1.11 seconds
Started Mar 10 01:25:53 PM PDT 24
Finished Mar 10 01:25:54 PM PDT 24
Peak memory 200536 kb
Host smart-1c6f768d-94c2-463a-8b09-917fbab1e1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269807850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3269807850
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.4046288082
Short name T509
Test name
Test status
Simulation time 4096103154 ps
CPU time 15.73 seconds
Started Mar 10 01:26:08 PM PDT 24
Finished Mar 10 01:26:24 PM PDT 24
Peak memory 208848 kb
Host smart-fa10e13d-e96d-47f9-bb22-5b097d2f9728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046288082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4046288082
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3072396488
Short name T319
Test name
Test status
Simulation time 154783932 ps
CPU time 1.75 seconds
Started Mar 10 01:25:49 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 200332 kb
Host smart-b9e88ff5-f6ef-4a44-923d-ed37a16c1209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072396488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3072396488
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2256719674
Short name T183
Test name
Test status
Simulation time 193080675 ps
CPU time 1.25 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:52 PM PDT 24
Peak memory 200440 kb
Host smart-398e99ce-baab-4ad2-845f-e9a1399cfa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256719674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2256719674
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1093473355
Short name T24
Test name
Test status
Simulation time 65735090 ps
CPU time 0.77 seconds
Started Mar 10 01:25:58 PM PDT 24
Finished Mar 10 01:25:59 PM PDT 24
Peak memory 200268 kb
Host smart-f9a40a7a-3366-4065-bad2-ea5992969d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093473355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1093473355
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3853722825
Short name T41
Test name
Test status
Simulation time 1217997137 ps
CPU time 5.67 seconds
Started Mar 10 01:25:53 PM PDT 24
Finished Mar 10 01:25:59 PM PDT 24
Peak memory 216576 kb
Host smart-e692edbb-f464-49c9-bd80-4963beef72b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853722825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3853722825
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2270303423
Short name T2
Test name
Test status
Simulation time 245280959 ps
CPU time 1.12 seconds
Started Mar 10 01:25:52 PM PDT 24
Finished Mar 10 01:25:54 PM PDT 24
Peak memory 217220 kb
Host smart-dccb6884-9480-4f53-acfe-3aa4464cfa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270303423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2270303423
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2027534847
Short name T415
Test name
Test status
Simulation time 122745077 ps
CPU time 0.82 seconds
Started Mar 10 01:25:56 PM PDT 24
Finished Mar 10 01:25:57 PM PDT 24
Peak memory 200236 kb
Host smart-89741a50-da63-4b5e-8973-38f43432b56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027534847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2027534847
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3100276644
Short name T25
Test name
Test status
Simulation time 1824498369 ps
CPU time 6.99 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:59 PM PDT 24
Peak memory 200584 kb
Host smart-0b13121d-64a0-4478-86ac-31f2f839e5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100276644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3100276644
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2479537539
Short name T529
Test name
Test status
Simulation time 178659244 ps
CPU time 1.2 seconds
Started Mar 10 01:25:54 PM PDT 24
Finished Mar 10 01:25:55 PM PDT 24
Peak memory 200428 kb
Host smart-5540b1f8-c83e-40aa-a793-78c48556bb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479537539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2479537539
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1493359683
Short name T242
Test name
Test status
Simulation time 251744231 ps
CPU time 1.49 seconds
Started Mar 10 01:25:48 PM PDT 24
Finished Mar 10 01:25:50 PM PDT 24
Peak memory 200536 kb
Host smart-d7115215-77ca-401b-b067-098acb644897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493359683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1493359683
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2546280662
Short name T396
Test name
Test status
Simulation time 10335354039 ps
CPU time 40.87 seconds
Started Mar 10 01:25:57 PM PDT 24
Finished Mar 10 01:26:39 PM PDT 24
Peak memory 208864 kb
Host smart-adf0f150-7919-4b45-b097-ba03ed0f9f42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546280662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2546280662
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1006795506
Short name T373
Test name
Test status
Simulation time 264858740 ps
CPU time 1.83 seconds
Started Mar 10 01:25:52 PM PDT 24
Finished Mar 10 01:25:54 PM PDT 24
Peak memory 200376 kb
Host smart-1d317228-83b1-4e70-b493-999492d99240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006795506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1006795506
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.4172461303
Short name T219
Test name
Test status
Simulation time 161242535 ps
CPU time 1.31 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:52 PM PDT 24
Peak memory 200436 kb
Host smart-7a09cca6-55c6-4e47-b56b-34f545015f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172461303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4172461303
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1068576472
Short name T214
Test name
Test status
Simulation time 69479864 ps
CPU time 0.82 seconds
Started Mar 10 01:26:01 PM PDT 24
Finished Mar 10 01:26:03 PM PDT 24
Peak memory 200300 kb
Host smart-19e005fc-8431-4028-8e83-ae44341e4d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068576472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1068576472
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1986719383
Short name T37
Test name
Test status
Simulation time 1225545592 ps
CPU time 5.52 seconds
Started Mar 10 01:25:50 PM PDT 24
Finished Mar 10 01:25:56 PM PDT 24
Peak memory 217768 kb
Host smart-482cf4c2-e601-4356-8cb7-a9fe648f0701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986719383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1986719383
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2621587019
Short name T507
Test name
Test status
Simulation time 249494043 ps
CPU time 1.04 seconds
Started Mar 10 01:25:51 PM PDT 24
Finished Mar 10 01:25:52 PM PDT 24
Peak memory 217212 kb
Host smart-ab333589-bc0c-4bde-810f-f3fc84c364cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621587019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2621587019
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.54711528
Short name T501
Test name
Test status
Simulation time 207610866 ps
CPU time 1.02 seconds
Started Mar 10 01:25:53 PM PDT 24
Finished Mar 10 01:25:54 PM PDT 24
Peak memory 200208 kb
Host smart-1abaef6d-5eab-4def-ad2e-5b59bccea0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54711528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.54711528
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3647529495
Short name T139
Test name
Test status
Simulation time 1857715291 ps
CPU time 6.74 seconds
Started Mar 10 01:25:54 PM PDT 24
Finished Mar 10 01:26:01 PM PDT 24
Peak memory 200648 kb
Host smart-c701f603-631f-4ef4-b87b-029679ae97c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647529495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3647529495
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3132346215
Short name T433
Test name
Test status
Simulation time 154157024 ps
CPU time 1.19 seconds
Started Mar 10 01:26:01 PM PDT 24
Finished Mar 10 01:26:03 PM PDT 24
Peak memory 200444 kb
Host smart-bc91a915-6b1f-43cf-b917-b7ffae1d87eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132346215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3132346215
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.813494529
Short name T323
Test name
Test status
Simulation time 214067040 ps
CPU time 1.4 seconds
Started Mar 10 01:25:50 PM PDT 24
Finished Mar 10 01:25:51 PM PDT 24
Peak memory 200484 kb
Host smart-fca95a9f-6cfd-4146-a201-48f33a0bd528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813494529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.813494529
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.4217757901
Short name T288
Test name
Test status
Simulation time 1379712867 ps
CPU time 5.95 seconds
Started Mar 10 01:25:55 PM PDT 24
Finished Mar 10 01:26:01 PM PDT 24
Peak memory 208760 kb
Host smart-a7f264c0-210e-4c51-9fda-aeb1621cce1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217757901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.4217757901
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2694509306
Short name T540
Test name
Test status
Simulation time 136701294 ps
CPU time 1.78 seconds
Started Mar 10 01:25:55 PM PDT 24
Finished Mar 10 01:25:58 PM PDT 24
Peak memory 200360 kb
Host smart-7f9b86b8-5a63-4b38-96bb-437e181e3b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694509306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2694509306
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2923140981
Short name T168
Test name
Test status
Simulation time 146773522 ps
CPU time 1.08 seconds
Started Mar 10 01:25:54 PM PDT 24
Finished Mar 10 01:25:55 PM PDT 24
Peak memory 200432 kb
Host smart-18ce27f4-0d22-40c2-b103-ac87987081ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923140981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2923140981
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.4361049
Short name T379
Test name
Test status
Simulation time 73531864 ps
CPU time 0.81 seconds
Started Mar 10 01:24:42 PM PDT 24
Finished Mar 10 01:24:43 PM PDT 24
Peak memory 200316 kb
Host smart-287660f5-e846-4427-9efa-e9308bec2376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4361049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4361049
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.751088995
Short name T533
Test name
Test status
Simulation time 2361166605 ps
CPU time 9.01 seconds
Started Mar 10 01:24:40 PM PDT 24
Finished Mar 10 01:24:50 PM PDT 24
Peak memory 217564 kb
Host smart-bdb0dc53-5ae8-4347-8337-eac9536da3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751088995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.751088995
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3722884989
Short name T213
Test name
Test status
Simulation time 245949306 ps
CPU time 1.09 seconds
Started Mar 10 01:24:40 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 217184 kb
Host smart-05c06d7d-9c9a-452a-9495-924bbe0ff78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722884989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3722884989
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1013829445
Short name T196
Test name
Test status
Simulation time 137579424 ps
CPU time 0.82 seconds
Started Mar 10 01:24:41 PM PDT 24
Finished Mar 10 01:24:43 PM PDT 24
Peak memory 200120 kb
Host smart-367d394a-4df4-4cc1-b952-89b19677fee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013829445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1013829445
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2014813160
Short name T485
Test name
Test status
Simulation time 1638286901 ps
CPU time 6.94 seconds
Started Mar 10 01:24:46 PM PDT 24
Finished Mar 10 01:24:53 PM PDT 24
Peak memory 200528 kb
Host smart-1e449fbb-40f0-4e10-b1fe-af861093a3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014813160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2014813160
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1731302817
Short name T6
Test name
Test status
Simulation time 106707893 ps
CPU time 1 seconds
Started Mar 10 01:24:40 PM PDT 24
Finished Mar 10 01:24:41 PM PDT 24
Peak memory 200472 kb
Host smart-442051f6-d6bb-44a1-ab9f-5eeedee44730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731302817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1731302817
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2177720290
Short name T160
Test name
Test status
Simulation time 227191157 ps
CPU time 1.43 seconds
Started Mar 10 01:24:40 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 200536 kb
Host smart-11fe550e-e138-4d75-a565-1867873554db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177720290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2177720290
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1684895453
Short name T368
Test name
Test status
Simulation time 8066181323 ps
CPU time 29.12 seconds
Started Mar 10 01:24:42 PM PDT 24
Finished Mar 10 01:25:12 PM PDT 24
Peak memory 200648 kb
Host smart-d07956df-ee10-4fb0-8554-4c6def9702e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684895453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1684895453
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1237302612
Short name T276
Test name
Test status
Simulation time 136202135 ps
CPU time 1.8 seconds
Started Mar 10 01:24:42 PM PDT 24
Finished Mar 10 01:24:45 PM PDT 24
Peak memory 200272 kb
Host smart-6a733d1d-92cd-44c4-8603-aaedcf0629e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237302612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1237302612
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2951748583
Short name T243
Test name
Test status
Simulation time 86822778 ps
CPU time 0.94 seconds
Started Mar 10 01:24:45 PM PDT 24
Finished Mar 10 01:24:46 PM PDT 24
Peak memory 200440 kb
Host smart-8f3f4e38-0359-4bc4-b450-b9481b218df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951748583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2951748583
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.12633268
Short name T322
Test name
Test status
Simulation time 77160036 ps
CPU time 0.78 seconds
Started Mar 10 01:24:46 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 200252 kb
Host smart-816b05e9-0228-4b10-a5ac-259d6e290b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12633268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.12633268
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2726987517
Short name T34
Test name
Test status
Simulation time 1224372131 ps
CPU time 6.3 seconds
Started Mar 10 01:24:45 PM PDT 24
Finished Mar 10 01:24:52 PM PDT 24
Peak memory 217128 kb
Host smart-c639aca6-a611-4783-a3cc-5469c07d8822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726987517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2726987517
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3323889825
Short name T162
Test name
Test status
Simulation time 244576757 ps
CPU time 1.08 seconds
Started Mar 10 01:24:43 PM PDT 24
Finished Mar 10 01:24:45 PM PDT 24
Peak memory 217132 kb
Host smart-75768f61-6ff0-4f8b-97a7-77b1f6ad88a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323889825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3323889825
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.4289602475
Short name T10
Test name
Test status
Simulation time 91567171 ps
CPU time 0.86 seconds
Started Mar 10 01:25:03 PM PDT 24
Finished Mar 10 01:25:04 PM PDT 24
Peak memory 200232 kb
Host smart-005451b4-d97d-4a0d-a35c-f774674beae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289602475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.4289602475
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.922763022
Short name T269
Test name
Test status
Simulation time 1406085953 ps
CPU time 5.78 seconds
Started Mar 10 01:24:43 PM PDT 24
Finished Mar 10 01:24:50 PM PDT 24
Peak memory 200524 kb
Host smart-28a4e3ea-1549-4bb0-89c2-fc1afe7c1738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922763022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.922763022
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3458774865
Short name T455
Test name
Test status
Simulation time 138614131 ps
CPU time 1.13 seconds
Started Mar 10 01:24:39 PM PDT 24
Finished Mar 10 01:24:42 PM PDT 24
Peak memory 200384 kb
Host smart-99935df8-2340-4090-becd-915dcdbb48ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458774865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3458774865
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1001944310
Short name T513
Test name
Test status
Simulation time 109816075 ps
CPU time 1.22 seconds
Started Mar 10 01:24:45 PM PDT 24
Finished Mar 10 01:24:46 PM PDT 24
Peak memory 200484 kb
Host smart-a6aba811-f365-435f-b7e0-6a0c584c5b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001944310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1001944310
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3373633744
Short name T339
Test name
Test status
Simulation time 5849123128 ps
CPU time 20.6 seconds
Started Mar 10 01:24:45 PM PDT 24
Finished Mar 10 01:25:06 PM PDT 24
Peak memory 200696 kb
Host smart-6adbde2a-36fb-4f9d-84a1-b3c1ddfe765d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373633744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3373633744
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1429004992
Short name T434
Test name
Test status
Simulation time 144780797 ps
CPU time 1.78 seconds
Started Mar 10 01:24:42 PM PDT 24
Finished Mar 10 01:24:45 PM PDT 24
Peak memory 200320 kb
Host smart-e40867bb-af2b-43da-a0f0-475668d4e977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429004992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1429004992
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3963383404
Short name T408
Test name
Test status
Simulation time 88414463 ps
CPU time 0.88 seconds
Started Mar 10 01:24:46 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 200376 kb
Host smart-9f753ca5-9892-413c-87ad-cbe1bea69430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963383404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3963383404
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.267986101
Short name T400
Test name
Test status
Simulation time 67249542 ps
CPU time 0.76 seconds
Started Mar 10 01:24:47 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 200264 kb
Host smart-48209c03-4dad-45c9-afb0-463a35999b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267986101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.267986101
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2457052952
Short name T449
Test name
Test status
Simulation time 1222161772 ps
CPU time 5.84 seconds
Started Mar 10 01:24:48 PM PDT 24
Finished Mar 10 01:24:54 PM PDT 24
Peak memory 217120 kb
Host smart-5e69b87d-233c-448c-bf20-007f7c587432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457052952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2457052952
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.138262598
Short name T55
Test name
Test status
Simulation time 244614338 ps
CPU time 1.07 seconds
Started Mar 10 01:24:46 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 217212 kb
Host smart-b0e8130d-ac7b-4407-a519-0686acc4c30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138262598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.138262598
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2235079785
Short name T346
Test name
Test status
Simulation time 237741991 ps
CPU time 1.03 seconds
Started Mar 10 01:24:47 PM PDT 24
Finished Mar 10 01:24:48 PM PDT 24
Peak memory 200252 kb
Host smart-e9ca34d5-b263-4ebe-a6b3-313ebb1e2626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235079785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2235079785
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1723762003
Short name T417
Test name
Test status
Simulation time 1436575086 ps
CPU time 6.04 seconds
Started Mar 10 01:24:46 PM PDT 24
Finished Mar 10 01:24:52 PM PDT 24
Peak memory 200584 kb
Host smart-4ba86c3e-3b10-46f7-84bc-5057d1e4f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723762003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1723762003
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2849884917
Short name T195
Test name
Test status
Simulation time 102695674 ps
CPU time 0.98 seconds
Started Mar 10 01:24:48 PM PDT 24
Finished Mar 10 01:24:49 PM PDT 24
Peak memory 200408 kb
Host smart-c67bb1cf-e1a5-442a-a4c5-54c5abc6e785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849884917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2849884917
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3378533997
Short name T223
Test name
Test status
Simulation time 248913787 ps
CPU time 1.46 seconds
Started Mar 10 01:24:45 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 200568 kb
Host smart-727520af-4261-4b7e-ac85-244d61084f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378533997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3378533997
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2740988071
Short name T498
Test name
Test status
Simulation time 15973619195 ps
CPU time 52.19 seconds
Started Mar 10 01:24:47 PM PDT 24
Finished Mar 10 01:25:39 PM PDT 24
Peak memory 200684 kb
Host smart-ad7dd42a-999b-4a57-993c-1e04a71bf237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740988071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2740988071
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1453699940
Short name T542
Test name
Test status
Simulation time 472319139 ps
CPU time 2.82 seconds
Started Mar 10 01:24:48 PM PDT 24
Finished Mar 10 01:24:51 PM PDT 24
Peak memory 208532 kb
Host smart-ad786c8e-6541-4ecf-a45d-e6c5e8eb6d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453699940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1453699940
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2347242305
Short name T12
Test name
Test status
Simulation time 190199767 ps
CPU time 1.27 seconds
Started Mar 10 01:24:47 PM PDT 24
Finished Mar 10 01:24:48 PM PDT 24
Peak memory 200352 kb
Host smart-c5bf34f7-b16b-4e7e-933e-b1c9d088ca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347242305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2347242305
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1779529975
Short name T401
Test name
Test status
Simulation time 71540390 ps
CPU time 0.74 seconds
Started Mar 10 01:24:49 PM PDT 24
Finished Mar 10 01:24:49 PM PDT 24
Peak memory 200336 kb
Host smart-9fabf26c-c54f-4945-b412-3a98e3befb44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779529975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1779529975
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.555497843
Short name T438
Test name
Test status
Simulation time 1888128876 ps
CPU time 7.16 seconds
Started Mar 10 01:24:48 PM PDT 24
Finished Mar 10 01:24:55 PM PDT 24
Peak memory 217124 kb
Host smart-dcbe5002-f4a3-4f4e-bade-a6ec6b85c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555497843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.555497843
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1133413994
Short name T491
Test name
Test status
Simulation time 249035915 ps
CPU time 1.02 seconds
Started Mar 10 01:24:47 PM PDT 24
Finished Mar 10 01:24:48 PM PDT 24
Peak memory 217212 kb
Host smart-afe1bf50-440a-4c1b-be01-1eef6ea55a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133413994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1133413994
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1358314946
Short name T349
Test name
Test status
Simulation time 97288858 ps
CPU time 0.77 seconds
Started Mar 10 01:24:45 PM PDT 24
Finished Mar 10 01:24:46 PM PDT 24
Peak memory 200244 kb
Host smart-f90efa64-072b-4911-b453-ee3a29972a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358314946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1358314946
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2741025623
Short name T127
Test name
Test status
Simulation time 1203618741 ps
CPU time 5.02 seconds
Started Mar 10 01:24:47 PM PDT 24
Finished Mar 10 01:24:52 PM PDT 24
Peak memory 200620 kb
Host smart-dbcc313f-365e-42a6-b61e-b12cd6c9a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741025623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2741025623
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2400999259
Short name T517
Test name
Test status
Simulation time 108116870 ps
CPU time 0.99 seconds
Started Mar 10 01:24:48 PM PDT 24
Finished Mar 10 01:24:49 PM PDT 24
Peak memory 200420 kb
Host smart-da042769-2a99-4e3c-b413-ff4570be0a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400999259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2400999259
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.4206406335
Short name T143
Test name
Test status
Simulation time 225779016 ps
CPU time 1.43 seconds
Started Mar 10 01:24:48 PM PDT 24
Finished Mar 10 01:24:50 PM PDT 24
Peak memory 200460 kb
Host smart-7a616d9f-73bf-4d1b-8668-d3cce561ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206406335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4206406335
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2529864375
Short name T350
Test name
Test status
Simulation time 2775877116 ps
CPU time 12.69 seconds
Started Mar 10 01:24:48 PM PDT 24
Finished Mar 10 01:25:00 PM PDT 24
Peak memory 208836 kb
Host smart-f2bb760e-d396-4f50-adaf-91a79cda5426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529864375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2529864375
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2284081427
Short name T246
Test name
Test status
Simulation time 372032496 ps
CPU time 2.16 seconds
Started Mar 10 01:24:49 PM PDT 24
Finished Mar 10 01:24:51 PM PDT 24
Peak memory 208720 kb
Host smart-216fa1f6-3e5a-4731-b0ce-4bb65d336c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284081427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2284081427
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.313209100
Short name T336
Test name
Test status
Simulation time 103279540 ps
CPU time 0.97 seconds
Started Mar 10 01:24:47 PM PDT 24
Finished Mar 10 01:24:48 PM PDT 24
Peak memory 200432 kb
Host smart-99af98b4-b3e8-4dde-9240-7dca3e8b94d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313209100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.313209100
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.4252122691
Short name T519
Test name
Test status
Simulation time 88696078 ps
CPU time 0.83 seconds
Started Mar 10 01:24:59 PM PDT 24
Finished Mar 10 01:25:00 PM PDT 24
Peak memory 200252 kb
Host smart-64889e5f-3c85-480e-bc15-610f9372b0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252122691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.4252122691
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.4179713210
Short name T43
Test name
Test status
Simulation time 1891709183 ps
CPU time 7.7 seconds
Started Mar 10 01:24:52 PM PDT 24
Finished Mar 10 01:25:00 PM PDT 24
Peak memory 221852 kb
Host smart-d8dce199-2e12-44dc-aedd-a43a2fc6d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179713210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4179713210
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1203113321
Short name T270
Test name
Test status
Simulation time 244856133 ps
CPU time 1.13 seconds
Started Mar 10 01:24:52 PM PDT 24
Finished Mar 10 01:24:53 PM PDT 24
Peak memory 217204 kb
Host smart-78ec4bd1-8d2d-4586-87ff-6fe3d52328d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203113321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1203113321
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3155563723
Short name T303
Test name
Test status
Simulation time 123069211 ps
CPU time 0.87 seconds
Started Mar 10 01:24:46 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 200232 kb
Host smart-3063fd6d-988d-4aa0-828a-1fd6dbf939fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155563723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3155563723
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3262717207
Short name T384
Test name
Test status
Simulation time 1220953255 ps
CPU time 4.88 seconds
Started Mar 10 01:24:46 PM PDT 24
Finished Mar 10 01:24:51 PM PDT 24
Peak memory 200616 kb
Host smart-ea889baa-bb8c-4d80-b328-e01b85f2cd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262717207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3262717207
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2854170896
Short name T460
Test name
Test status
Simulation time 106653871 ps
CPU time 1.1 seconds
Started Mar 10 01:24:59 PM PDT 24
Finished Mar 10 01:25:01 PM PDT 24
Peak memory 200352 kb
Host smart-4eef5284-0d78-435f-aa40-5b90695d9afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854170896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2854170896
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2767510805
Short name T317
Test name
Test status
Simulation time 187691767 ps
CPU time 1.38 seconds
Started Mar 10 01:24:49 PM PDT 24
Finished Mar 10 01:24:50 PM PDT 24
Peak memory 200568 kb
Host smart-eece5d86-b474-462c-a2bc-f4768048f187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767510805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2767510805
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1509874959
Short name T461
Test name
Test status
Simulation time 6319169388 ps
CPU time 23.02 seconds
Started Mar 10 01:24:51 PM PDT 24
Finished Mar 10 01:25:14 PM PDT 24
Peak memory 200700 kb
Host smart-a4bfb7c2-47fb-490d-ac28-9f395bc9ee69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509874959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1509874959
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2436533063
Short name T198
Test name
Test status
Simulation time 375778904 ps
CPU time 2.33 seconds
Started Mar 10 01:24:50 PM PDT 24
Finished Mar 10 01:24:52 PM PDT 24
Peak memory 208528 kb
Host smart-c50d0fbc-2eed-482d-a02a-9eaf72d5df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436533063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2436533063
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3101634179
Short name T493
Test name
Test status
Simulation time 150897178 ps
CPU time 1.37 seconds
Started Mar 10 01:24:53 PM PDT 24
Finished Mar 10 01:24:55 PM PDT 24
Peak memory 200460 kb
Host smart-febc14ad-2fc8-426e-b7fd-c968bbd2a1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101634179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3101634179
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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