Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8375

1

T1

19

T3

26

T4

169

auto[1]

11579

1

T1

82

T3

31

T4

186

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6113	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6809	1			T1	27		T2	1		T3	20
reset_info_cp[2]	3057	1			T1	16		T3	10		T4	65
reset_info_cp[4]	4019	1			T1	16		T3	9		T4	64
reset_info_cp[8]	124	1			T1	1		T3	2		T4	3
reset_info_cp[16]	117	1			T3	1		T4	4		T5	3
reset_info_cp[32]	114	1			T3	1		T4	1		T5	2
reset_info_cp[64]	114	1			T3	2		T4	1		T7	1
reset_info_cp[128]	107	1			T1	1		T3	1		T4	3

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3234	1			T1	19		T3	7		T4	64
reset_info_cp[1]	auto[1]	2955	1			T1	7		T3	12		T4	67
reset_info_cp[2]	auto[0]	966	1			T3	3		T4	30		T5	30
reset_info_cp[2]	auto[1]	2091	1			T1	16		T3	7		T4	35
reset_info_cp[4]	auto[0]	1431	1			T3	5		T4	23		T5	42
reset_info_cp[4]	auto[1]	2588	1			T1	16		T3	4		T4	41
reset_info_cp[8]	auto[0]	49	1			T3	1		T4	1		T5	2
reset_info_cp[8]	auto[1]	75	1			T1	1		T3	1		T4	2
reset_info_cp[16]	auto[0]	47	1			T3	1		T4	2		T5	1
reset_info_cp[16]	auto[1]	70	1			T4	2		T5	2		T22	1
reset_info_cp[32]	auto[0]	46	1			T3	1		T45	1		T95	1
reset_info_cp[32]	auto[1]	68	1			T4	1		T5	2		T10	1
reset_info_cp[64]	auto[0]	47	1			T3	2		T10	1		T45	1
reset_info_cp[64]	auto[1]	67	1			T4	1		T7	1		T11	1
reset_info_cp[128]	auto[0]	31	1			T4	2		T5	2		T45	1
reset_info_cp[128]	auto[1]	76	1			T1	1		T3	1		T4	1