Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T539 /workspace/coverage/default/45.rstmgr_alert_test.1070132751 Mar 12 12:45:14 PM PDT 24 Mar 12 12:45:17 PM PDT 24 77276657 ps
T540 /workspace/coverage/default/5.rstmgr_smoke.3193423714 Mar 12 12:43:49 PM PDT 24 Mar 12 12:43:51 PM PDT 24 192611654 ps
T541 /workspace/coverage/default/38.rstmgr_stress_all.3256112717 Mar 12 12:44:55 PM PDT 24 Mar 12 12:44:57 PM PDT 24 165151872 ps
T542 /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1532171520 Mar 12 12:44:27 PM PDT 24 Mar 12 12:44:28 PM PDT 24 112609535 ps
T543 /workspace/coverage/default/3.rstmgr_por_stretcher.2735487022 Mar 12 12:43:37 PM PDT 24 Mar 12 12:43:38 PM PDT 24 129415999 ps
T56 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3378691227 Mar 12 01:01:30 PM PDT 24 Mar 12 01:01:32 PM PDT 24 148949272 ps
T61 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.408350343 Mar 12 01:01:05 PM PDT 24 Mar 12 01:01:08 PM PDT 24 173783985 ps
T57 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3640186349 Mar 12 01:00:57 PM PDT 24 Mar 12 01:01:01 PM PDT 24 1228795202 ps
T58 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1287120957 Mar 12 01:00:55 PM PDT 24 Mar 12 01:00:56 PM PDT 24 167733159 ps
T59 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3051347881 Mar 12 01:00:57 PM PDT 24 Mar 12 01:00:59 PM PDT 24 418736718 ps
T79 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1496284584 Mar 12 01:01:10 PM PDT 24 Mar 12 01:01:12 PM PDT 24 229317254 ps
T80 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.441456387 Mar 12 01:01:07 PM PDT 24 Mar 12 01:01:09 PM PDT 24 126361498 ps
T132 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2313850729 Mar 12 01:01:14 PM PDT 24 Mar 12 01:01:17 PM PDT 24 278744353 ps
T107 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1404331932 Mar 12 01:00:56 PM PDT 24 Mar 12 01:01:02 PM PDT 24 110238592 ps
T108 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3543323965 Mar 12 01:01:01 PM PDT 24 Mar 12 01:01:02 PM PDT 24 77900880 ps
T77 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2339575544 Mar 12 01:01:27 PM PDT 24 Mar 12 01:01:29 PM PDT 24 170650225 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.552456316 Mar 12 01:01:26 PM PDT 24 Mar 12 01:01:28 PM PDT 24 215358087 ps
T545 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.578145755 Mar 12 01:00:58 PM PDT 24 Mar 12 01:01:00 PM PDT 24 201237418 ps
T78 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3993212618 Mar 12 01:01:04 PM PDT 24 Mar 12 01:01:06 PM PDT 24 113815877 ps
T76 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.837214376 Mar 12 01:00:59 PM PDT 24 Mar 12 01:01:01 PM PDT 24 455317404 ps
T96 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3328503356 Mar 12 01:01:05 PM PDT 24 Mar 12 01:01:06 PM PDT 24 161083313 ps
T109 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.546427847 Mar 12 01:00:55 PM PDT 24 Mar 12 01:00:56 PM PDT 24 70855527 ps
T110 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1895202357 Mar 12 01:01:00 PM PDT 24 Mar 12 01:01:01 PM PDT 24 94952587 ps
T83 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.730956095 Mar 12 01:01:14 PM PDT 24 Mar 12 01:01:17 PM PDT 24 160775512 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1175269757 Mar 12 01:00:56 PM PDT 24 Mar 12 01:00:57 PM PDT 24 106948963 ps
T111 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2382518527 Mar 12 01:01:07 PM PDT 24 Mar 12 01:01:08 PM PDT 24 226523916 ps
T85 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1899998575 Mar 12 01:00:52 PM PDT 24 Mar 12 01:00:55 PM PDT 24 830044489 ps
T97 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1476492912 Mar 12 01:00:56 PM PDT 24 Mar 12 01:00:57 PM PDT 24 134328583 ps
T91 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.552215145 Mar 12 01:01:37 PM PDT 24 Mar 12 01:01:39 PM PDT 24 187619433 ps
T112 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1656914498 Mar 12 01:01:11 PM PDT 24 Mar 12 01:01:12 PM PDT 24 88230244 ps
T92 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3017966240 Mar 12 01:00:57 PM PDT 24 Mar 12 01:00:59 PM PDT 24 435573205 ps
T81 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2405787102 Mar 12 01:01:06 PM PDT 24 Mar 12 01:01:07 PM PDT 24 95234005 ps
T82 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3527908529 Mar 12 01:01:04 PM PDT 24 Mar 12 01:01:06 PM PDT 24 261239630 ps
T113 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.474712008 Mar 12 01:01:09 PM PDT 24 Mar 12 01:01:11 PM PDT 24 125698817 ps
T114 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3911641689 Mar 12 01:01:06 PM PDT 24 Mar 12 01:01:06 PM PDT 24 68446515 ps
T84 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2073864643 Mar 12 01:01:05 PM PDT 24 Mar 12 01:01:09 PM PDT 24 548195145 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1061349957 Mar 12 01:00:59 PM PDT 24 Mar 12 01:01:02 PM PDT 24 181615020 ps
T548 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2364542240 Mar 12 01:01:12 PM PDT 24 Mar 12 01:01:13 PM PDT 24 116288857 ps
T549 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3274340886 Mar 12 01:01:30 PM PDT 24 Mar 12 01:01:32 PM PDT 24 192951222 ps
T550 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.870227410 Mar 12 01:00:57 PM PDT 24 Mar 12 01:00:59 PM PDT 24 239950373 ps
T551 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3052242491 Mar 12 01:01:12 PM PDT 24 Mar 12 01:01:14 PM PDT 24 225441935 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.549004050 Mar 12 01:01:20 PM PDT 24 Mar 12 01:01:24 PM PDT 24 416869923 ps
T553 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3377520428 Mar 12 01:01:14 PM PDT 24 Mar 12 01:01:16 PM PDT 24 352985791 ps
T554 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3721656627 Mar 12 01:00:53 PM PDT 24 Mar 12 01:00:54 PM PDT 24 55203559 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.337374671 Mar 12 01:00:56 PM PDT 24 Mar 12 01:00:57 PM PDT 24 110074554 ps
T556 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3937104389 Mar 12 01:00:59 PM PDT 24 Mar 12 01:01:00 PM PDT 24 172316300 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2020680215 Mar 12 01:00:56 PM PDT 24 Mar 12 01:00:57 PM PDT 24 209408150 ps
T558 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2226479561 Mar 12 01:01:15 PM PDT 24 Mar 12 01:01:16 PM PDT 24 204442549 ps
T559 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.33508887 Mar 12 01:01:09 PM PDT 24 Mar 12 01:01:10 PM PDT 24 72063197 ps
T560 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1749261836 Mar 12 01:01:13 PM PDT 24 Mar 12 01:01:14 PM PDT 24 135913437 ps
T561 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3715507925 Mar 12 01:01:29 PM PDT 24 Mar 12 01:01:31 PM PDT 24 129648155 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2534924745 Mar 12 01:01:10 PM PDT 24 Mar 12 01:01:11 PM PDT 24 108205249 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2867146599 Mar 12 01:01:20 PM PDT 24 Mar 12 01:01:22 PM PDT 24 129493859 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.530336155 Mar 12 01:01:01 PM PDT 24 Mar 12 01:01:04 PM PDT 24 464494664 ps
T565 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1747266245 Mar 12 01:01:23 PM PDT 24 Mar 12 01:01:24 PM PDT 24 130194703 ps
T566 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.258219264 Mar 12 01:00:55 PM PDT 24 Mar 12 01:00:56 PM PDT 24 90277088 ps
T127 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4291482458 Mar 12 01:01:36 PM PDT 24 Mar 12 01:01:40 PM PDT 24 900833232 ps
T567 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1066371079 Mar 12 01:00:56 PM PDT 24 Mar 12 01:01:04 PM PDT 24 353785360 ps
T568 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.677889254 Mar 12 01:01:42 PM PDT 24 Mar 12 01:01:43 PM PDT 24 192527108 ps
T569 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2560079782 Mar 12 01:01:16 PM PDT 24 Mar 12 01:01:18 PM PDT 24 75021411 ps
T570 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2423970471 Mar 12 01:01:34 PM PDT 24 Mar 12 01:01:35 PM PDT 24 91286495 ps
T86 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.396611046 Mar 12 01:01:08 PM PDT 24 Mar 12 01:01:12 PM PDT 24 924123257 ps
T128 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2959404214 Mar 12 01:01:06 PM PDT 24 Mar 12 01:01:08 PM PDT 24 499071930 ps
T571 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3482621889 Mar 12 01:00:57 PM PDT 24 Mar 12 01:00:59 PM PDT 24 226691077 ps
T572 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1777191146 Mar 12 01:01:01 PM PDT 24 Mar 12 01:01:03 PM PDT 24 167529791 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3471016014 Mar 12 01:00:59 PM PDT 24 Mar 12 01:01:00 PM PDT 24 98482877 ps
T574 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1957257541 Mar 12 01:01:10 PM PDT 24 Mar 12 01:01:11 PM PDT 24 121820992 ps
T129 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3098210986 Mar 12 01:01:15 PM PDT 24 Mar 12 01:01:17 PM PDT 24 472833769 ps
T575 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.730900761 Mar 12 01:01:01 PM PDT 24 Mar 12 01:01:03 PM PDT 24 186281692 ps
T576 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2113205417 Mar 12 01:01:25 PM PDT 24 Mar 12 01:01:28 PM PDT 24 444495068 ps
T577 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3521762172 Mar 12 01:01:29 PM PDT 24 Mar 12 01:01:30 PM PDT 24 76230076 ps
T578 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.761905492 Mar 12 01:01:07 PM PDT 24 Mar 12 01:01:08 PM PDT 24 57285021 ps
T579 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.625083419 Mar 12 01:00:57 PM PDT 24 Mar 12 01:00:58 PM PDT 24 59372750 ps
T580 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1376777881 Mar 12 01:01:30 PM PDT 24 Mar 12 01:01:31 PM PDT 24 158614914 ps
T581 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2389967009 Mar 12 01:00:59 PM PDT 24 Mar 12 01:01:01 PM PDT 24 147943195 ps
T582 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2068824838 Mar 12 01:01:43 PM PDT 24 Mar 12 01:01:44 PM PDT 24 67954131 ps
T583 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2216458302 Mar 12 01:01:09 PM PDT 24 Mar 12 01:01:12 PM PDT 24 172788375 ps
T584 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3193735334 Mar 12 01:00:56 PM PDT 24 Mar 12 01:00:57 PM PDT 24 122867460 ps
T585 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4280474460 Mar 12 01:00:59 PM PDT 24 Mar 12 01:01:00 PM PDT 24 78772290 ps
T586 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1508842495 Mar 12 01:00:56 PM PDT 24 Mar 12 01:00:58 PM PDT 24 227445439 ps
T87 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2502990621 Mar 12 01:01:14 PM PDT 24 Mar 12 01:01:17 PM PDT 24 954743966 ps
T587 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2896629585 Mar 12 01:01:26 PM PDT 24 Mar 12 01:01:27 PM PDT 24 64026266 ps
T588 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1731057333 Mar 12 01:01:43 PM PDT 24 Mar 12 01:01:54 PM PDT 24 154164814 ps
T589 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1621394652 Mar 12 01:01:07 PM PDT 24 Mar 12 01:01:08 PM PDT 24 90026762 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3488431074 Mar 12 01:00:57 PM PDT 24 Mar 12 01:00:59 PM PDT 24 136149144 ps
T591 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.752655742 Mar 12 01:01:22 PM PDT 24 Mar 12 01:01:25 PM PDT 24 192450348 ps
T89 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1933962293 Mar 12 01:01:11 PM PDT 24 Mar 12 01:01:13 PM PDT 24 586908877 ps
T90 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2905996159 Mar 12 01:01:15 PM PDT 24 Mar 12 01:01:18 PM PDT 24 1040169591 ps
T592 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2264459965 Mar 12 01:01:31 PM PDT 24 Mar 12 01:01:32 PM PDT 24 139031057 ps
T593 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3242192533 Mar 12 01:01:31 PM PDT 24 Mar 12 01:01:32 PM PDT 24 134956247 ps
T594 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3462841794 Mar 12 01:00:57 PM PDT 24 Mar 12 01:01:00 PM PDT 24 372164928 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3668153851 Mar 12 01:01:14 PM PDT 24 Mar 12 01:01:20 PM PDT 24 480832925 ps
T596 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1109367839 Mar 12 01:01:16 PM PDT 24 Mar 12 01:01:19 PM PDT 24 419442546 ps
T597 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1472585583 Mar 12 01:01:07 PM PDT 24 Mar 12 01:01:08 PM PDT 24 60070484 ps
T598 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2011935724 Mar 12 01:01:07 PM PDT 24 Mar 12 01:01:08 PM PDT 24 65657896 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.26858360 Mar 12 01:01:24 PM PDT 24 Mar 12 01:01:25 PM PDT 24 67611565 ps
T130 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3749440859 Mar 12 01:01:02 PM PDT 24 Mar 12 01:01:05 PM PDT 24 867825106 ps
T600 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3638749271 Mar 12 01:01:04 PM PDT 24 Mar 12 01:01:07 PM PDT 24 818166959 ps
T601 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1533363112 Mar 12 01:01:15 PM PDT 24 Mar 12 01:01:19 PM PDT 24 904540564 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1691157050 Mar 12 01:00:55 PM PDT 24 Mar 12 01:00:56 PM PDT 24 75370355 ps
T603 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3468437680 Mar 12 01:00:57 PM PDT 24 Mar 12 01:00:59 PM PDT 24 183859845 ps
T604 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1542380725 Mar 12 01:01:30 PM PDT 24 Mar 12 01:01:34 PM PDT 24 924839325 ps
T605 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2786485731 Mar 12 01:01:23 PM PDT 24 Mar 12 01:01:25 PM PDT 24 262411070 ps
T606 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1650446692 Mar 12 01:00:54 PM PDT 24 Mar 12 01:00:56 PM PDT 24 439996395 ps
T607 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3680420568 Mar 12 01:00:56 PM PDT 24 Mar 12 01:00:57 PM PDT 24 100160547 ps
T608 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3881860768 Mar 12 01:01:10 PM PDT 24 Mar 12 01:01:11 PM PDT 24 134108660 ps
T609 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2161813768 Mar 12 01:01:01 PM PDT 24 Mar 12 01:01:06 PM PDT 24 798278546 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.808335281 Mar 12 01:01:00 PM PDT 24 Mar 12 01:01:05 PM PDT 24 801332128 ps
T611 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.115998061 Mar 12 01:00:58 PM PDT 24 Mar 12 01:01:00 PM PDT 24 195658076 ps
T612 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3217457896 Mar 12 01:01:31 PM PDT 24 Mar 12 01:01:34 PM PDT 24 215157990 ps
T613 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2733349129 Mar 12 01:00:56 PM PDT 24 Mar 12 01:01:04 PM PDT 24 1556914341 ps
T88 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2954361708 Mar 12 01:01:10 PM PDT 24 Mar 12 01:01:13 PM PDT 24 905046947 ps
T131 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2436238572 Mar 12 01:01:15 PM PDT 24 Mar 12 01:01:18 PM PDT 24 500409923 ps
T614 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1966920347 Mar 12 01:01:28 PM PDT 24 Mar 12 01:01:30 PM PDT 24 165573535 ps
T615 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3373009321 Mar 12 01:00:57 PM PDT 24 Mar 12 01:01:00 PM PDT 24 551369825 ps
T616 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.699575019 Mar 12 01:00:55 PM PDT 24 Mar 12 01:00:57 PM PDT 24 162500202 ps
T617 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1757761339 Mar 12 01:01:07 PM PDT 24 Mar 12 01:01:09 PM PDT 24 174664184 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1297116762 Mar 12 01:01:05 PM PDT 24 Mar 12 01:01:07 PM PDT 24 212364438 ps
T619 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3948378926 Mar 12 01:01:09 PM PDT 24 Mar 12 01:01:10 PM PDT 24 131323011 ps
T620 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3308164548 Mar 12 01:00:59 PM PDT 24 Mar 12 01:01:00 PM PDT 24 105954276 ps

Test location /workspace/coverage/default/29.rstmgr_stress_all.1856643993
Short name T4
Test name
Test status
Simulation time 9990660864 ps
CPU time 39.26 seconds
Started Mar 12 12:44:34 PM PDT 24
Finished Mar 12 12:45:14 PM PDT 24
Peak memory 208764 kb
Host smart-e2b4c22a-3a0a-4b27-8a80-12867869fe4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856643993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1856643993
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.666855609
Short name T36
Test name
Test status
Simulation time 562445561 ps
CPU time 2.7 seconds
Started Mar 12 12:43:38 PM PDT 24
Finished Mar 12 12:43:41 PM PDT 24
Peak memory 200188 kb
Host smart-bc55de16-2dc0-4261-9ce7-56699a1f4a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666855609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.666855609
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2339575544
Short name T77
Test name
Test status
Simulation time 170650225 ps
CPU time 1.53 seconds
Started Mar 12 01:01:27 PM PDT 24
Finished Mar 12 01:01:29 PM PDT 24
Peak memory 208716 kb
Host smart-545cdf41-a2ec-4d4a-8e7e-a621236daed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339575544 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2339575544
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.935668151
Short name T66
Test name
Test status
Simulation time 16534159174 ps
CPU time 26.11 seconds
Started Mar 12 12:43:14 PM PDT 24
Finished Mar 12 12:43:41 PM PDT 24
Peak memory 217080 kb
Host smart-b7588461-bdeb-4c33-9470-065385af3ffb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935668151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.935668151
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.770042727
Short name T25
Test name
Test status
Simulation time 2360718249 ps
CPU time 8.93 seconds
Started Mar 12 12:45:08 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 217364 kb
Host smart-b886008a-ac64-4062-9c83-f9c82edc8bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770042727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.770042727
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3640186349
Short name T57
Test name
Test status
Simulation time 1228795202 ps
CPU time 3.52 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:01:01 PM PDT 24
Peak memory 200480 kb
Host smart-da008d62-0d92-49fa-a193-5b7e1be5562c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640186349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3640186349
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.712938034
Short name T2
Test name
Test status
Simulation time 60815347 ps
CPU time 0.82 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:02 PM PDT 24
Peak memory 200136 kb
Host smart-97cda47f-7113-42ee-b82d-5dd288f6d6ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712938034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.712938034
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2766529609
Short name T169
Test name
Test status
Simulation time 210198430 ps
CPU time 1.32 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:48 PM PDT 24
Peak memory 200412 kb
Host smart-b847415f-9469-4f78-9523-e02c88964b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766529609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2766529609
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.408350343
Short name T61
Test name
Test status
Simulation time 173783985 ps
CPU time 2.49 seconds
Started Mar 12 01:01:05 PM PDT 24
Finished Mar 12 01:01:08 PM PDT 24
Peak memory 216776 kb
Host smart-90c40cb6-2013-4eb3-ae77-320731e7f3e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408350343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.408350343
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.875663436
Short name T134
Test name
Test status
Simulation time 175286926 ps
CPU time 1.27 seconds
Started Mar 12 12:44:07 PM PDT 24
Finished Mar 12 12:44:09 PM PDT 24
Peak memory 200324 kb
Host smart-60009602-239c-43ca-b520-68e4181b6e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875663436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.875663436
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3749440859
Short name T130
Test name
Test status
Simulation time 867825106 ps
CPU time 2.74 seconds
Started Mar 12 01:01:02 PM PDT 24
Finished Mar 12 01:01:05 PM PDT 24
Peak memory 200520 kb
Host smart-acb1bdd7-0d2a-413f-91e4-541c9127a3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749440859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3749440859
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.520718546
Short name T9
Test name
Test status
Simulation time 1888300022 ps
CPU time 7.9 seconds
Started Mar 12 12:44:38 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 221812 kb
Host smart-9c28d221-48c0-4e48-b6c0-97a80e77a8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520718546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.520718546
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3081156621
Short name T100
Test name
Test status
Simulation time 6138743749 ps
CPU time 19.58 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:20 PM PDT 24
Peak memory 200520 kb
Host smart-818d3d7c-5ed0-4522-aeae-e2574794882d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081156621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3081156621
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2502990621
Short name T87
Test name
Test status
Simulation time 954743966 ps
CPU time 3 seconds
Started Mar 12 01:01:14 PM PDT 24
Finished Mar 12 01:01:17 PM PDT 24
Peak memory 200304 kb
Host smart-0e12e915-747b-46ef-8c80-f5448e88aa98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502990621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2502990621
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3911641689
Short name T114
Test name
Test status
Simulation time 68446515 ps
CPU time 0.82 seconds
Started Mar 12 01:01:06 PM PDT 24
Finished Mar 12 01:01:06 PM PDT 24
Peak memory 200280 kb
Host smart-64e2b9ec-ef6c-4fe6-a506-064af7990baa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911641689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3911641689
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2291420847
Short name T21
Test name
Test status
Simulation time 149445775 ps
CPU time 0.89 seconds
Started Mar 12 12:43:55 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 200180 kb
Host smart-31300726-cc90-4050-9129-b7ceb1408804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291420847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2291420847
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1903790399
Short name T34
Test name
Test status
Simulation time 1221870572 ps
CPU time 5.74 seconds
Started Mar 12 12:44:16 PM PDT 24
Finished Mar 12 12:44:22 PM PDT 24
Peak memory 221124 kb
Host smart-a287aa71-fdab-4158-bdf5-6006e20679a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903790399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1903790399
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2954361708
Short name T88
Test name
Test status
Simulation time 905046947 ps
CPU time 2.9 seconds
Started Mar 12 01:01:10 PM PDT 24
Finished Mar 12 01:01:13 PM PDT 24
Peak memory 200416 kb
Host smart-490d6e96-3ddc-4802-9550-8812be97c14f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954361708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2954361708
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.566040562
Short name T285
Test name
Test status
Simulation time 126658898 ps
CPU time 1.52 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:50 PM PDT 24
Peak memory 208544 kb
Host smart-4740e010-9d9e-4c99-a44a-9a196c30c9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566040562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.566040562
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.552456316
Short name T544
Test name
Test status
Simulation time 215358087 ps
CPU time 1.68 seconds
Started Mar 12 01:01:26 PM PDT 24
Finished Mar 12 01:01:28 PM PDT 24
Peak memory 200488 kb
Host smart-4bd8efa3-2cbc-4968-b05c-95531c5a6cdf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552456316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.552456316
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3668153851
Short name T595
Test name
Test status
Simulation time 480832925 ps
CPU time 5.62 seconds
Started Mar 12 01:01:14 PM PDT 24
Finished Mar 12 01:01:20 PM PDT 24
Peak memory 200528 kb
Host smart-1be6f1e8-e8f6-45aa-b152-7bc9b6b52d65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668153851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
668153851
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3881860768
Short name T608
Test name
Test status
Simulation time 134108660 ps
CPU time 0.88 seconds
Started Mar 12 01:01:10 PM PDT 24
Finished Mar 12 01:01:11 PM PDT 24
Peak memory 200244 kb
Host smart-8772f597-6b6f-41ad-aadb-9b1a9d1aaf70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881860768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
881860768
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.115998061
Short name T611
Test name
Test status
Simulation time 195658076 ps
CPU time 1.83 seconds
Started Mar 12 01:00:58 PM PDT 24
Finished Mar 12 01:01:00 PM PDT 24
Peak memory 216764 kb
Host smart-a56d4eb9-68a7-468d-b247-d2697b4f79b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115998061 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.115998061
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.26858360
Short name T599
Test name
Test status
Simulation time 67611565 ps
CPU time 0.78 seconds
Started Mar 12 01:01:24 PM PDT 24
Finished Mar 12 01:01:25 PM PDT 24
Peak memory 200312 kb
Host smart-ec4478ed-6076-4e4d-b198-751cd3913712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26858360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.26858360
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1297116762
Short name T618
Test name
Test status
Simulation time 212364438 ps
CPU time 1.46 seconds
Started Mar 12 01:01:05 PM PDT 24
Finished Mar 12 01:01:07 PM PDT 24
Peak memory 200476 kb
Host smart-f885a13f-23d8-4a17-af7d-3e162b0d4331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297116762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1297116762
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3373009321
Short name T615
Test name
Test status
Simulation time 551369825 ps
CPU time 3.24 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:01:00 PM PDT 24
Peak memory 208712 kb
Host smart-bdcc48a2-2978-4fa4-8e2a-ae4e7f527894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373009321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3373009321
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1650446692
Short name T606
Test name
Test status
Simulation time 439996395 ps
CPU time 1.82 seconds
Started Mar 12 01:00:54 PM PDT 24
Finished Mar 12 01:00:56 PM PDT 24
Peak memory 200412 kb
Host smart-b249e02d-b72c-48a9-9d49-76bb8a1e78dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650446692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1650446692
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3377520428
Short name T553
Test name
Test status
Simulation time 352985791 ps
CPU time 2.51 seconds
Started Mar 12 01:01:14 PM PDT 24
Finished Mar 12 01:01:16 PM PDT 24
Peak memory 208728 kb
Host smart-94470463-e93c-4905-af33-47a9c4626445
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377520428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
377520428
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2733349129
Short name T613
Test name
Test status
Simulation time 1556914341 ps
CPU time 8.13 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:01:04 PM PDT 24
Peak memory 200492 kb
Host smart-b0d4d0f2-5ede-4f66-a9b8-8698682fcec0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733349129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
733349129
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2534924745
Short name T562
Test name
Test status
Simulation time 108205249 ps
CPU time 0.8 seconds
Started Mar 12 01:01:10 PM PDT 24
Finished Mar 12 01:01:11 PM PDT 24
Peak memory 200168 kb
Host smart-42ee14b9-fe70-4c4d-ae5f-15828a789599
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534924745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
534924745
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1287120957
Short name T58
Test name
Test status
Simulation time 167733159 ps
CPU time 1.51 seconds
Started Mar 12 01:00:55 PM PDT 24
Finished Mar 12 01:00:56 PM PDT 24
Peak memory 208652 kb
Host smart-40d0f9ba-9fe3-4a71-9126-065cfc3182d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287120957 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1287120957
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2011935724
Short name T598
Test name
Test status
Simulation time 65657896 ps
CPU time 0.76 seconds
Started Mar 12 01:01:07 PM PDT 24
Finished Mar 12 01:01:08 PM PDT 24
Peak memory 200240 kb
Host smart-878b2275-f4ab-4fb1-b26b-e8d4958b56bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011935724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2011935724
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.337374671
Short name T555
Test name
Test status
Simulation time 110074554 ps
CPU time 1.26 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:00:57 PM PDT 24
Peak memory 200492 kb
Host smart-c9f920c1-5350-44e4-8e10-ad58d625187a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337374671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.337374671
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3471016014
Short name T573
Test name
Test status
Simulation time 98482877 ps
CPU time 1.22 seconds
Started Mar 12 01:00:59 PM PDT 24
Finished Mar 12 01:01:00 PM PDT 24
Peak memory 200272 kb
Host smart-ce93a4ca-608f-4a93-9b34-a0dfc9a7d288
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471016014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3471016014
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2959404214
Short name T128
Test name
Test status
Simulation time 499071930 ps
CPU time 1.91 seconds
Started Mar 12 01:01:06 PM PDT 24
Finished Mar 12 01:01:08 PM PDT 24
Peak memory 200416 kb
Host smart-a0da5a63-0209-4d65-877d-94b8456de07d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959404214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2959404214
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2867146599
Short name T563
Test name
Test status
Simulation time 129493859 ps
CPU time 1.04 seconds
Started Mar 12 01:01:20 PM PDT 24
Finished Mar 12 01:01:22 PM PDT 24
Peak memory 200352 kb
Host smart-bdd2b726-851f-443b-b38f-33c1d4375dde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867146599 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2867146599
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1496284584
Short name T79
Test name
Test status
Simulation time 229317254 ps
CPU time 1.43 seconds
Started Mar 12 01:01:10 PM PDT 24
Finished Mar 12 01:01:12 PM PDT 24
Peak memory 200484 kb
Host smart-8d430130-d763-42cc-bd04-43a99158972f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496284584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1496284584
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3462841794
Short name T594
Test name
Test status
Simulation time 372164928 ps
CPU time 2.71 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:01:00 PM PDT 24
Peak memory 208648 kb
Host smart-c2843f64-6c5a-4377-9030-3b4e47aaab89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462841794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3462841794
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.396611046
Short name T86
Test name
Test status
Simulation time 924123257 ps
CPU time 3.1 seconds
Started Mar 12 01:01:08 PM PDT 24
Finished Mar 12 01:01:12 PM PDT 24
Peak memory 200444 kb
Host smart-8893122c-80a1-41b5-af93-f5684a00ecf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396611046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.396611046
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.677889254
Short name T568
Test name
Test status
Simulation time 192527108 ps
CPU time 1.37 seconds
Started Mar 12 01:01:42 PM PDT 24
Finished Mar 12 01:01:43 PM PDT 24
Peak memory 208552 kb
Host smart-a23f869c-881f-4c9b-bdc3-9de0a39ad65c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677889254 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.677889254
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.625083419
Short name T579
Test name
Test status
Simulation time 59372750 ps
CPU time 0.76 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:00:58 PM PDT 24
Peak memory 200276 kb
Host smart-7f5a517c-e54c-4200-bce6-cf8fd4e2d167
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625083419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.625083419
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1376777881
Short name T580
Test name
Test status
Simulation time 158614914 ps
CPU time 1.17 seconds
Started Mar 12 01:01:30 PM PDT 24
Finished Mar 12 01:01:31 PM PDT 24
Peak memory 200312 kb
Host smart-ccf79f91-25af-4706-809c-85dbe2eb512f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376777881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1376777881
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3217457896
Short name T612
Test name
Test status
Simulation time 215157990 ps
CPU time 1.79 seconds
Started Mar 12 01:01:31 PM PDT 24
Finished Mar 12 01:01:34 PM PDT 24
Peak memory 208528 kb
Host smart-3e91b9f5-3fd2-4e1e-ae93-ed9a288ad4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217457896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3217457896
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1109367839
Short name T596
Test name
Test status
Simulation time 419442546 ps
CPU time 1.74 seconds
Started Mar 12 01:01:16 PM PDT 24
Finished Mar 12 01:01:19 PM PDT 24
Peak memory 200460 kb
Host smart-8d28c0ef-1173-41a5-8ab9-a46b7c969e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109367839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1109367839
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3308164548
Short name T620
Test name
Test status
Simulation time 105954276 ps
CPU time 1 seconds
Started Mar 12 01:00:59 PM PDT 24
Finished Mar 12 01:01:00 PM PDT 24
Peak memory 208564 kb
Host smart-d3b9231c-623a-4b7f-9bcf-3f08b95342c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308164548 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3308164548
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.258219264
Short name T566
Test name
Test status
Simulation time 90277088 ps
CPU time 0.89 seconds
Started Mar 12 01:00:55 PM PDT 24
Finished Mar 12 01:00:56 PM PDT 24
Peak memory 200260 kb
Host smart-895f4d1c-9148-4056-851e-20b11edad645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258219264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.258219264
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1404331932
Short name T107
Test name
Test status
Simulation time 110238592 ps
CPU time 1.28 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:01:02 PM PDT 24
Peak memory 208668 kb
Host smart-b3349d2d-ab66-4c97-946a-eb31c242fd8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404331932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1404331932
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2364542240
Short name T548
Test name
Test status
Simulation time 116288857 ps
CPU time 1.63 seconds
Started Mar 12 01:01:12 PM PDT 24
Finished Mar 12 01:01:13 PM PDT 24
Peak memory 216820 kb
Host smart-ca569152-3da9-47cd-9dd6-74322ec83105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364542240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2364542240
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1533363112
Short name T601
Test name
Test status
Simulation time 904540564 ps
CPU time 3.36 seconds
Started Mar 12 01:01:15 PM PDT 24
Finished Mar 12 01:01:19 PM PDT 24
Peak memory 200456 kb
Host smart-34e8dcf6-e011-456b-95f6-82f7099fdc44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533363112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1533363112
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3274340886
Short name T549
Test name
Test status
Simulation time 192951222 ps
CPU time 1.73 seconds
Started Mar 12 01:01:30 PM PDT 24
Finished Mar 12 01:01:32 PM PDT 24
Peak memory 208704 kb
Host smart-9468918c-8b0f-42fd-9617-77af3af33579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274340886 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3274340886
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1472585583
Short name T597
Test name
Test status
Simulation time 60070484 ps
CPU time 0.75 seconds
Started Mar 12 01:01:07 PM PDT 24
Finished Mar 12 01:01:08 PM PDT 24
Peak memory 200232 kb
Host smart-ed8f4365-3c2e-478e-9277-d098a24dfcb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472585583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1472585583
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1731057333
Short name T588
Test name
Test status
Simulation time 154164814 ps
CPU time 1.14 seconds
Started Mar 12 01:01:43 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 200304 kb
Host smart-5e3125c8-6fb7-45ce-9609-474abe32e783
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731057333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1731057333
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.530336155
Short name T564
Test name
Test status
Simulation time 464494664 ps
CPU time 3.12 seconds
Started Mar 12 01:01:01 PM PDT 24
Finished Mar 12 01:01:04 PM PDT 24
Peak memory 216808 kb
Host smart-448a3f92-430f-498c-974d-52867fee4270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530336155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.530336155
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1933962293
Short name T89
Test name
Test status
Simulation time 586908877 ps
CPU time 2.09 seconds
Started Mar 12 01:01:11 PM PDT 24
Finished Mar 12 01:01:13 PM PDT 24
Peak memory 200476 kb
Host smart-8963a07c-9fd5-4c34-a196-f501ca01282c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933962293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1933962293
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3468437680
Short name T603
Test name
Test status
Simulation time 183859845 ps
CPU time 1.11 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:00:59 PM PDT 24
Peak memory 200300 kb
Host smart-3b4cbf37-dde5-4486-b1cf-56eb6c246aa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468437680 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3468437680
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2423970471
Short name T570
Test name
Test status
Simulation time 91286495 ps
CPU time 0.88 seconds
Started Mar 12 01:01:34 PM PDT 24
Finished Mar 12 01:01:35 PM PDT 24
Peak memory 200300 kb
Host smart-37f2586b-0464-4262-b8bb-4b486f9981ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423970471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2423970471
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1957257541
Short name T574
Test name
Test status
Simulation time 121820992 ps
CPU time 1 seconds
Started Mar 12 01:01:10 PM PDT 24
Finished Mar 12 01:01:11 PM PDT 24
Peak memory 200248 kb
Host smart-04973255-8172-468f-90b8-a72acab4da0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957257541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1957257541
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2073864643
Short name T84
Test name
Test status
Simulation time 548195145 ps
CPU time 3.55 seconds
Started Mar 12 01:01:05 PM PDT 24
Finished Mar 12 01:01:09 PM PDT 24
Peak memory 200456 kb
Host smart-9297ff4f-e545-4cbb-9775-caebcadacef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073864643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2073864643
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3638749271
Short name T600
Test name
Test status
Simulation time 818166959 ps
CPU time 2.75 seconds
Started Mar 12 01:01:04 PM PDT 24
Finished Mar 12 01:01:07 PM PDT 24
Peak memory 200464 kb
Host smart-93af3db5-c9e7-46f2-9fa9-57dfda2a92e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638749271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3638749271
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1966920347
Short name T614
Test name
Test status
Simulation time 165573535 ps
CPU time 1.54 seconds
Started Mar 12 01:01:28 PM PDT 24
Finished Mar 12 01:01:30 PM PDT 24
Peak memory 212196 kb
Host smart-44da076c-2c13-4b36-a5eb-0af5d28b1b60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966920347 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1966920347
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.761905492
Short name T578
Test name
Test status
Simulation time 57285021 ps
CPU time 0.73 seconds
Started Mar 12 01:01:07 PM PDT 24
Finished Mar 12 01:01:08 PM PDT 24
Peak memory 200164 kb
Host smart-6ed1b856-d516-4684-bab5-654399f1eed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761905492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.761905492
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1656914498
Short name T112
Test name
Test status
Simulation time 88230244 ps
CPU time 0.96 seconds
Started Mar 12 01:01:11 PM PDT 24
Finished Mar 12 01:01:12 PM PDT 24
Peak memory 200264 kb
Host smart-075e6805-cfde-44aa-a2ba-c7a94167226a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656914498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1656914498
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1066371079
Short name T567
Test name
Test status
Simulation time 353785360 ps
CPU time 2.81 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:01:04 PM PDT 24
Peak memory 208476 kb
Host smart-5ec39cdd-58eb-495f-bb73-151669136a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066371079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1066371079
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.552215145
Short name T91
Test name
Test status
Simulation time 187619433 ps
CPU time 1.34 seconds
Started Mar 12 01:01:37 PM PDT 24
Finished Mar 12 01:01:39 PM PDT 24
Peak memory 208544 kb
Host smart-9ff22e13-b316-4a06-858c-cb812eb461c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552215145 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.552215145
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1621394652
Short name T589
Test name
Test status
Simulation time 90026762 ps
CPU time 0.87 seconds
Started Mar 12 01:01:07 PM PDT 24
Finished Mar 12 01:01:08 PM PDT 24
Peak memory 200248 kb
Host smart-d2715e8f-3265-4545-9725-008509323a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621394652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1621394652
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.870227410
Short name T550
Test name
Test status
Simulation time 239950373 ps
CPU time 1.47 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:00:59 PM PDT 24
Peak memory 200404 kb
Host smart-a3d0722b-2e30-4467-93a2-8ba1beb3e475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870227410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.870227410
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3378691227
Short name T56
Test name
Test status
Simulation time 148949272 ps
CPU time 1.13 seconds
Started Mar 12 01:01:30 PM PDT 24
Finished Mar 12 01:01:32 PM PDT 24
Peak memory 200448 kb
Host smart-552e4288-ea06-4265-83a6-fbe41fc9a9d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378691227 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3378691227
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3721656627
Short name T554
Test name
Test status
Simulation time 55203559 ps
CPU time 0.72 seconds
Started Mar 12 01:00:53 PM PDT 24
Finished Mar 12 01:00:54 PM PDT 24
Peak memory 200264 kb
Host smart-149c29b5-4c26-400d-8cf7-3153db0bc497
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721656627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3721656627
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.441456387
Short name T80
Test name
Test status
Simulation time 126361498 ps
CPU time 1.27 seconds
Started Mar 12 01:01:07 PM PDT 24
Finished Mar 12 01:01:09 PM PDT 24
Peak memory 200436 kb
Host smart-a500eabe-584a-40fa-a74c-dc0daaff0fc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441456387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.441456387
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3993212618
Short name T78
Test name
Test status
Simulation time 113815877 ps
CPU time 1.5 seconds
Started Mar 12 01:01:04 PM PDT 24
Finished Mar 12 01:01:06 PM PDT 24
Peak memory 208592 kb
Host smart-ae569c45-04f1-4bb5-aa40-e0df1037a93f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993212618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3993212618
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2068824838
Short name T582
Test name
Test status
Simulation time 67954131 ps
CPU time 0.76 seconds
Started Mar 12 01:01:43 PM PDT 24
Finished Mar 12 01:01:44 PM PDT 24
Peak memory 200144 kb
Host smart-f563b355-52c6-42f1-b55b-7d9a262b7301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068824838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2068824838
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3715507925
Short name T561
Test name
Test status
Simulation time 129648155 ps
CPU time 1.44 seconds
Started Mar 12 01:01:29 PM PDT 24
Finished Mar 12 01:01:31 PM PDT 24
Peak memory 200496 kb
Host smart-cb801e9b-648d-4f4f-90f6-3383fa0614c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715507925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3715507925
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3052242491
Short name T551
Test name
Test status
Simulation time 225441935 ps
CPU time 1.76 seconds
Started Mar 12 01:01:12 PM PDT 24
Finished Mar 12 01:01:14 PM PDT 24
Peak memory 208476 kb
Host smart-6da58b8a-a02e-4e78-aa8e-40f67e5c1415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052242491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3052242491
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4291482458
Short name T127
Test name
Test status
Simulation time 900833232 ps
CPU time 3.07 seconds
Started Mar 12 01:01:36 PM PDT 24
Finished Mar 12 01:01:40 PM PDT 24
Peak memory 200416 kb
Host smart-9e803d27-f3f6-42ee-9481-e22fa85dce14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291482458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.4291482458
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1777191146
Short name T572
Test name
Test status
Simulation time 167529791 ps
CPU time 1.65 seconds
Started Mar 12 01:01:01 PM PDT 24
Finished Mar 12 01:01:03 PM PDT 24
Peak memory 208668 kb
Host smart-3f2d057f-acf6-456f-800b-dcbfeb1bbea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777191146 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1777191146
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2560079782
Short name T569
Test name
Test status
Simulation time 75021411 ps
CPU time 0.79 seconds
Started Mar 12 01:01:16 PM PDT 24
Finished Mar 12 01:01:18 PM PDT 24
Peak memory 200280 kb
Host smart-02e444b3-8781-4287-9c4c-951d1fd837a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560079782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2560079782
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1749261836
Short name T560
Test name
Test status
Simulation time 135913437 ps
CPU time 1.06 seconds
Started Mar 12 01:01:13 PM PDT 24
Finished Mar 12 01:01:14 PM PDT 24
Peak memory 200312 kb
Host smart-738ec763-08c7-4732-9f68-4a7f60921059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749261836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1749261836
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.699575019
Short name T616
Test name
Test status
Simulation time 162500202 ps
CPU time 2.21 seconds
Started Mar 12 01:00:55 PM PDT 24
Finished Mar 12 01:00:57 PM PDT 24
Peak memory 211776 kb
Host smart-21826588-c6f8-4127-bb06-a3749df92db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699575019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.699575019
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2436238572
Short name T131
Test name
Test status
Simulation time 500409923 ps
CPU time 2.07 seconds
Started Mar 12 01:01:15 PM PDT 24
Finished Mar 12 01:01:18 PM PDT 24
Peak memory 200432 kb
Host smart-085cad7c-21c6-4cf8-83d1-4102126dbb97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436238572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2436238572
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.578145755
Short name T545
Test name
Test status
Simulation time 201237418 ps
CPU time 1.58 seconds
Started Mar 12 01:00:58 PM PDT 24
Finished Mar 12 01:01:00 PM PDT 24
Peak memory 200448 kb
Host smart-ff0f506e-d694-4b21-a8f7-494d941638d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578145755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.578145755
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2313850729
Short name T132
Test name
Test status
Simulation time 278744353 ps
CPU time 3.3 seconds
Started Mar 12 01:01:14 PM PDT 24
Finished Mar 12 01:01:17 PM PDT 24
Peak memory 200480 kb
Host smart-48784c29-83f2-487a-9c99-05b20f36e0aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313850729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
313850729
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3680420568
Short name T607
Test name
Test status
Simulation time 100160547 ps
CPU time 0.81 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:00:57 PM PDT 24
Peak memory 200264 kb
Host smart-f97a86ac-7458-46ed-9374-7187b23ffde5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680420568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
680420568
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3937104389
Short name T556
Test name
Test status
Simulation time 172316300 ps
CPU time 1.14 seconds
Started Mar 12 01:00:59 PM PDT 24
Finished Mar 12 01:01:00 PM PDT 24
Peak memory 209792 kb
Host smart-1a6da863-7126-448d-bdda-b503dc41385c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937104389 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3937104389
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3521762172
Short name T577
Test name
Test status
Simulation time 76230076 ps
CPU time 0.8 seconds
Started Mar 12 01:01:29 PM PDT 24
Finished Mar 12 01:01:30 PM PDT 24
Peak memory 200088 kb
Host smart-bb86c8e3-e7a4-4511-b737-600e1efa4043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521762172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3521762172
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3488431074
Short name T590
Test name
Test status
Simulation time 136149144 ps
CPU time 1.26 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:00:59 PM PDT 24
Peak memory 200396 kb
Host smart-d81b38fc-d8bb-4ef6-906b-3a91f5060cc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488431074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3488431074
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.549004050
Short name T552
Test name
Test status
Simulation time 416869923 ps
CPU time 3.18 seconds
Started Mar 12 01:01:20 PM PDT 24
Finished Mar 12 01:01:24 PM PDT 24
Peak memory 208668 kb
Host smart-96460c45-a042-427f-b761-2f7d43e8aabe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549004050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.549004050
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1542380725
Short name T604
Test name
Test status
Simulation time 924839325 ps
CPU time 3.1 seconds
Started Mar 12 01:01:30 PM PDT 24
Finished Mar 12 01:01:34 PM PDT 24
Peak memory 200508 kb
Host smart-7a65fdd2-8b3f-4ca0-a916-f851ffaab17d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542380725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1542380725
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2389967009
Short name T581
Test name
Test status
Simulation time 147943195 ps
CPU time 1.86 seconds
Started Mar 12 01:00:59 PM PDT 24
Finished Mar 12 01:01:01 PM PDT 24
Peak memory 200416 kb
Host smart-f91dd7dc-2176-4bb2-8b6f-775b8cd93633
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389967009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
389967009
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.808335281
Short name T610
Test name
Test status
Simulation time 801332128 ps
CPU time 4.41 seconds
Started Mar 12 01:01:00 PM PDT 24
Finished Mar 12 01:01:05 PM PDT 24
Peak memory 215944 kb
Host smart-62c914f7-07f2-4c00-a461-da3ad2a94b84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808335281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.808335281
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1175269757
Short name T546
Test name
Test status
Simulation time 106948963 ps
CPU time 0.81 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:00:57 PM PDT 24
Peak memory 200196 kb
Host smart-e735db4c-0172-45a5-b994-3a6edd60a764
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175269757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
175269757
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2020680215
Short name T557
Test name
Test status
Simulation time 209408150 ps
CPU time 1.38 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:00:57 PM PDT 24
Peak memory 208440 kb
Host smart-24df8e32-8159-41d7-a802-a45b25e939ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020680215 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2020680215
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.546427847
Short name T109
Test name
Test status
Simulation time 70855527 ps
CPU time 0.81 seconds
Started Mar 12 01:00:55 PM PDT 24
Finished Mar 12 01:00:56 PM PDT 24
Peak memory 200288 kb
Host smart-76fb21bb-6ffb-4554-adae-e80954a3d953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546427847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.546427847
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.474712008
Short name T113
Test name
Test status
Simulation time 125698817 ps
CPU time 1.32 seconds
Started Mar 12 01:01:09 PM PDT 24
Finished Mar 12 01:01:11 PM PDT 24
Peak memory 200452 kb
Host smart-ab04080a-7a0c-44a7-8ec7-f167d5a51836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474712008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.474712008
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2216458302
Short name T583
Test name
Test status
Simulation time 172788375 ps
CPU time 2.52 seconds
Started Mar 12 01:01:09 PM PDT 24
Finished Mar 12 01:01:12 PM PDT 24
Peak memory 211728 kb
Host smart-6a517e8c-8225-40fe-a5fe-dfc90e9084ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216458302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2216458302
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1899998575
Short name T85
Test name
Test status
Simulation time 830044489 ps
CPU time 3.15 seconds
Started Mar 12 01:00:52 PM PDT 24
Finished Mar 12 01:00:55 PM PDT 24
Peak memory 200400 kb
Host smart-eb7842e5-c3c6-4b12-8772-45b9d9c334ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899998575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1899998575
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2786485731
Short name T605
Test name
Test status
Simulation time 262411070 ps
CPU time 1.87 seconds
Started Mar 12 01:01:23 PM PDT 24
Finished Mar 12 01:01:25 PM PDT 24
Peak memory 200452 kb
Host smart-7bc21e74-2f44-4bc4-9e1c-c336520974bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786485731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
786485731
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2161813768
Short name T609
Test name
Test status
Simulation time 798278546 ps
CPU time 4.39 seconds
Started Mar 12 01:01:01 PM PDT 24
Finished Mar 12 01:01:06 PM PDT 24
Peak memory 200468 kb
Host smart-407c68d8-fa31-46d4-b794-026afc4b2588
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161813768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
161813768
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1747266245
Short name T565
Test name
Test status
Simulation time 130194703 ps
CPU time 0.9 seconds
Started Mar 12 01:01:23 PM PDT 24
Finished Mar 12 01:01:24 PM PDT 24
Peak memory 200300 kb
Host smart-7b46b253-de57-4252-97ae-43d13e678e2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747266245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
747266245
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1476492912
Short name T97
Test name
Test status
Simulation time 134328583 ps
CPU time 1.06 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:00:57 PM PDT 24
Peak memory 208532 kb
Host smart-efd37e14-6982-4436-9bd6-be4dd8c8532c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476492912 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1476492912
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1691157050
Short name T602
Test name
Test status
Simulation time 75370355 ps
CPU time 0.84 seconds
Started Mar 12 01:00:55 PM PDT 24
Finished Mar 12 01:00:56 PM PDT 24
Peak memory 200300 kb
Host smart-4c64ff97-4865-41ea-b4e3-3bb00b13b1e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691157050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1691157050
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3482621889
Short name T571
Test name
Test status
Simulation time 226691077 ps
CPU time 1.5 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:00:59 PM PDT 24
Peak memory 200468 kb
Host smart-9b1ad999-810a-4f2d-a033-88b591161fc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482621889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3482621889
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1061349957
Short name T547
Test name
Test status
Simulation time 181615020 ps
CPU time 2.54 seconds
Started Mar 12 01:00:59 PM PDT 24
Finished Mar 12 01:01:02 PM PDT 24
Peak memory 208612 kb
Host smart-469a6788-cba6-4c4d-83e3-9e95cff12eb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061349957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1061349957
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3098210986
Short name T129
Test name
Test status
Simulation time 472833769 ps
CPU time 1.86 seconds
Started Mar 12 01:01:15 PM PDT 24
Finished Mar 12 01:01:17 PM PDT 24
Peak memory 200416 kb
Host smart-ea1381a7-4640-4f28-99b2-77bfd5de51da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098210986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3098210986
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2226479561
Short name T558
Test name
Test status
Simulation time 204442549 ps
CPU time 1.46 seconds
Started Mar 12 01:01:15 PM PDT 24
Finished Mar 12 01:01:16 PM PDT 24
Peak memory 208552 kb
Host smart-c1c395a8-df19-4d79-971e-272d87ac9665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226479561 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2226479561
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3543323965
Short name T108
Test name
Test status
Simulation time 77900880 ps
CPU time 0.92 seconds
Started Mar 12 01:01:01 PM PDT 24
Finished Mar 12 01:01:02 PM PDT 24
Peak memory 200248 kb
Host smart-134ee860-0f1e-4fc7-bf75-62a42e27aa14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543323965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3543323965
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1508842495
Short name T586
Test name
Test status
Simulation time 227445439 ps
CPU time 1.43 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:00:58 PM PDT 24
Peak memory 200444 kb
Host smart-a3dff491-905e-4293-b0b0-2f8ec15b0b6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508842495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1508842495
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.730956095
Short name T83
Test name
Test status
Simulation time 160775512 ps
CPU time 2.27 seconds
Started Mar 12 01:01:14 PM PDT 24
Finished Mar 12 01:01:17 PM PDT 24
Peak memory 208668 kb
Host smart-557076df-5bef-48d9-9b79-3a3600a1c6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730956095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.730956095
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.837214376
Short name T76
Test name
Test status
Simulation time 455317404 ps
CPU time 1.73 seconds
Started Mar 12 01:00:59 PM PDT 24
Finished Mar 12 01:01:01 PM PDT 24
Peak memory 200468 kb
Host smart-d9ab6f26-9706-4643-8a99-182a8830a15c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837214376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
837214376
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2264459965
Short name T592
Test name
Test status
Simulation time 139031057 ps
CPU time 1.12 seconds
Started Mar 12 01:01:31 PM PDT 24
Finished Mar 12 01:01:32 PM PDT 24
Peak memory 208532 kb
Host smart-514ef487-06f1-4a5f-8158-ecc1d108be74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264459965 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2264459965
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1895202357
Short name T110
Test name
Test status
Simulation time 94952587 ps
CPU time 0.89 seconds
Started Mar 12 01:01:00 PM PDT 24
Finished Mar 12 01:01:01 PM PDT 24
Peak memory 200240 kb
Host smart-cc286a45-2b31-493d-96c0-5cff3318a05e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895202357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1895202357
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3948378926
Short name T619
Test name
Test status
Simulation time 131323011 ps
CPU time 1.07 seconds
Started Mar 12 01:01:09 PM PDT 24
Finished Mar 12 01:01:10 PM PDT 24
Peak memory 200312 kb
Host smart-04b06add-ba48-49ee-a5ac-0f1b5e9132a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948378926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3948378926
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2405787102
Short name T81
Test name
Test status
Simulation time 95234005 ps
CPU time 1.29 seconds
Started Mar 12 01:01:06 PM PDT 24
Finished Mar 12 01:01:07 PM PDT 24
Peak memory 208664 kb
Host smart-089719cb-db32-4917-a71a-8fd5f4b706f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405787102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2405787102
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2905996159
Short name T90
Test name
Test status
Simulation time 1040169591 ps
CPU time 3.17 seconds
Started Mar 12 01:01:15 PM PDT 24
Finished Mar 12 01:01:18 PM PDT 24
Peak memory 200540 kb
Host smart-ad2b7a23-2302-4bab-8fca-3adfa3c4a242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905996159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2905996159
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3242192533
Short name T593
Test name
Test status
Simulation time 134956247 ps
CPU time 1.06 seconds
Started Mar 12 01:01:31 PM PDT 24
Finished Mar 12 01:01:32 PM PDT 24
Peak memory 208544 kb
Host smart-6a8df276-83c0-466b-b74b-dee87f07bfd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242192533 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3242192533
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4280474460
Short name T585
Test name
Test status
Simulation time 78772290 ps
CPU time 0.83 seconds
Started Mar 12 01:00:59 PM PDT 24
Finished Mar 12 01:01:00 PM PDT 24
Peak memory 200288 kb
Host smart-3b21dbe9-8cf1-49d8-af1c-566c8873417f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280474460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4280474460
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3193735334
Short name T584
Test name
Test status
Simulation time 122867460 ps
CPU time 1.09 seconds
Started Mar 12 01:00:56 PM PDT 24
Finished Mar 12 01:00:57 PM PDT 24
Peak memory 200248 kb
Host smart-b150ad01-81d4-4652-a8a2-f1f3d06d3a89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193735334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3193735334
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2113205417
Short name T576
Test name
Test status
Simulation time 444495068 ps
CPU time 3.16 seconds
Started Mar 12 01:01:25 PM PDT 24
Finished Mar 12 01:01:28 PM PDT 24
Peak memory 208688 kb
Host smart-f09d2520-2719-4f7a-80ca-d0dd955e0848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113205417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2113205417
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3328503356
Short name T96
Test name
Test status
Simulation time 161083313 ps
CPU time 1.13 seconds
Started Mar 12 01:01:05 PM PDT 24
Finished Mar 12 01:01:06 PM PDT 24
Peak memory 200352 kb
Host smart-3bc95b70-565a-4a9d-8001-f726ea41685e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328503356 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3328503356
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2896629585
Short name T587
Test name
Test status
Simulation time 64026266 ps
CPU time 0.79 seconds
Started Mar 12 01:01:26 PM PDT 24
Finished Mar 12 01:01:27 PM PDT 24
Peak memory 200228 kb
Host smart-c47673f4-f803-4f79-a938-e6f4eb1a22a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896629585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2896629585
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.752655742
Short name T591
Test name
Test status
Simulation time 192450348 ps
CPU time 1.5 seconds
Started Mar 12 01:01:22 PM PDT 24
Finished Mar 12 01:01:25 PM PDT 24
Peak memory 200424 kb
Host smart-54e3b1b2-23af-4cb5-8ad0-ffc5bf5844bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752655742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.752655742
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1757761339
Short name T617
Test name
Test status
Simulation time 174664184 ps
CPU time 1.43 seconds
Started Mar 12 01:01:07 PM PDT 24
Finished Mar 12 01:01:09 PM PDT 24
Peak memory 208464 kb
Host smart-45a26762-f1ef-4ff1-bff0-686578c56a06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757761339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1757761339
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3017966240
Short name T92
Test name
Test status
Simulation time 435573205 ps
CPU time 1.88 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:00:59 PM PDT 24
Peak memory 200492 kb
Host smart-b8063a38-67b2-4696-ae8e-8d382b7d4987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017966240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3017966240
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.730900761
Short name T575
Test name
Test status
Simulation time 186281692 ps
CPU time 1.77 seconds
Started Mar 12 01:01:01 PM PDT 24
Finished Mar 12 01:01:03 PM PDT 24
Peak memory 208672 kb
Host smart-279774ae-ae4a-4dd7-b5cc-922eeaa205f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730900761 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.730900761
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.33508887
Short name T559
Test name
Test status
Simulation time 72063197 ps
CPU time 0.74 seconds
Started Mar 12 01:01:09 PM PDT 24
Finished Mar 12 01:01:10 PM PDT 24
Peak memory 200208 kb
Host smart-d9f48c33-854c-41d2-a18d-fdfbb862d8a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33508887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.33508887
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2382518527
Short name T111
Test name
Test status
Simulation time 226523916 ps
CPU time 1.42 seconds
Started Mar 12 01:01:07 PM PDT 24
Finished Mar 12 01:01:08 PM PDT 24
Peak memory 200416 kb
Host smart-b7abfc02-54c3-42da-8afb-5d13cdbb6179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382518527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2382518527
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3527908529
Short name T82
Test name
Test status
Simulation time 261239630 ps
CPU time 1.83 seconds
Started Mar 12 01:01:04 PM PDT 24
Finished Mar 12 01:01:06 PM PDT 24
Peak memory 200492 kb
Host smart-f657e9d8-3a56-45fc-b81a-f30eca6c705d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527908529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3527908529
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3051347881
Short name T59
Test name
Test status
Simulation time 418736718 ps
CPU time 1.73 seconds
Started Mar 12 01:00:57 PM PDT 24
Finished Mar 12 01:00:59 PM PDT 24
Peak memory 200456 kb
Host smart-344f0dde-270a-4834-9c55-4d1d52c413c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051347881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3051347881
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.591599643
Short name T529
Test name
Test status
Simulation time 53114939 ps
CPU time 0.7 seconds
Started Mar 12 12:43:15 PM PDT 24
Finished Mar 12 12:43:15 PM PDT 24
Peak memory 200212 kb
Host smart-32b2c8db-20c3-4481-872a-c631a3a7de94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591599643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.591599643
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.595487368
Short name T363
Test name
Test status
Simulation time 1229578636 ps
CPU time 5.82 seconds
Started Mar 12 12:43:13 PM PDT 24
Finished Mar 12 12:43:19 PM PDT 24
Peak memory 221816 kb
Host smart-582fbf82-2598-4422-a96e-62112a7e6a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595487368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.595487368
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.395645556
Short name T278
Test name
Test status
Simulation time 244358654 ps
CPU time 1.07 seconds
Started Mar 12 12:43:16 PM PDT 24
Finished Mar 12 12:43:19 PM PDT 24
Peak memory 217168 kb
Host smart-2ddf8182-8014-48e9-9185-65edbf816756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395645556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.395645556
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.879489299
Short name T350
Test name
Test status
Simulation time 137403613 ps
CPU time 0.81 seconds
Started Mar 12 12:43:16 PM PDT 24
Finished Mar 12 12:43:17 PM PDT 24
Peak memory 200068 kb
Host smart-63d5132f-da60-4651-9828-5ef68ff4f5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879489299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.879489299
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3715891573
Short name T172
Test name
Test status
Simulation time 1622340525 ps
CPU time 6.56 seconds
Started Mar 12 12:43:13 PM PDT 24
Finished Mar 12 12:43:20 PM PDT 24
Peak memory 200588 kb
Host smart-f083a59a-c0dc-4382-aaf1-be682ee9dcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715891573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3715891573
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4029341221
Short name T241
Test name
Test status
Simulation time 97317652 ps
CPU time 0.93 seconds
Started Mar 12 12:43:23 PM PDT 24
Finished Mar 12 12:43:24 PM PDT 24
Peak memory 200260 kb
Host smart-d3079dbc-a167-452e-8284-acb7eb07ea56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029341221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4029341221
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.663766285
Short name T499
Test name
Test status
Simulation time 197079034 ps
CPU time 1.25 seconds
Started Mar 12 12:43:14 PM PDT 24
Finished Mar 12 12:43:15 PM PDT 24
Peak memory 200448 kb
Host smart-ed50a80c-f05b-445d-a503-6274b5be121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663766285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.663766285
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3907676310
Short name T291
Test name
Test status
Simulation time 426250021 ps
CPU time 1.91 seconds
Started Mar 12 12:43:14 PM PDT 24
Finished Mar 12 12:43:16 PM PDT 24
Peak memory 200432 kb
Host smart-54d15dfc-ecc6-4537-82dd-9258244daf27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907676310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3907676310
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1695312683
Short name T481
Test name
Test status
Simulation time 424245765 ps
CPU time 2.26 seconds
Started Mar 12 12:43:15 PM PDT 24
Finished Mar 12 12:43:17 PM PDT 24
Peak memory 208384 kb
Host smart-ea8d58a2-bfa9-460b-a085-a960301f4b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695312683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1695312683
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3409227356
Short name T468
Test name
Test status
Simulation time 78664592 ps
CPU time 0.83 seconds
Started Mar 12 12:43:14 PM PDT 24
Finished Mar 12 12:43:15 PM PDT 24
Peak memory 200300 kb
Host smart-662c39a2-8f26-4f2c-b9f0-39187087ed05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409227356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3409227356
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2857668713
Short name T342
Test name
Test status
Simulation time 77822379 ps
CPU time 0.85 seconds
Started Mar 12 12:43:39 PM PDT 24
Finished Mar 12 12:43:40 PM PDT 24
Peak memory 200108 kb
Host smart-c3c9f27c-a845-4bfe-b35e-a76db3fa13ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857668713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2857668713
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.57004775
Short name T29
Test name
Test status
Simulation time 2364390945 ps
CPU time 7.57 seconds
Started Mar 12 12:43:23 PM PDT 24
Finished Mar 12 12:43:31 PM PDT 24
Peak memory 221812 kb
Host smart-1c0bf050-a3a9-4562-9cda-ab8f21e1cf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57004775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.57004775
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1496801466
Short name T313
Test name
Test status
Simulation time 244162776 ps
CPU time 1.1 seconds
Started Mar 12 12:43:23 PM PDT 24
Finished Mar 12 12:43:24 PM PDT 24
Peak memory 217164 kb
Host smart-7174b2e4-25f4-4793-9eca-634796c6150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496801466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1496801466
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.416414756
Short name T400
Test name
Test status
Simulation time 105022619 ps
CPU time 0.75 seconds
Started Mar 12 12:43:23 PM PDT 24
Finished Mar 12 12:43:24 PM PDT 24
Peak memory 200004 kb
Host smart-ccc09f07-062f-4acb-ad5f-dff589ee35a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416414756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.416414756
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2889464992
Short name T104
Test name
Test status
Simulation time 814166206 ps
CPU time 4.33 seconds
Started Mar 12 12:43:24 PM PDT 24
Finished Mar 12 12:43:29 PM PDT 24
Peak memory 200424 kb
Host smart-6a4f7d56-808a-4692-ae5b-10543112b91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889464992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2889464992
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3617522705
Short name T63
Test name
Test status
Simulation time 16793546216 ps
CPU time 26.2 seconds
Started Mar 12 12:43:22 PM PDT 24
Finished Mar 12 12:43:48 PM PDT 24
Peak memory 216824 kb
Host smart-92b4981f-ad7e-4492-bd83-929c4e759afc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617522705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3617522705
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3668937109
Short name T455
Test name
Test status
Simulation time 95828465 ps
CPU time 0.96 seconds
Started Mar 12 12:43:23 PM PDT 24
Finished Mar 12 12:43:25 PM PDT 24
Peak memory 200240 kb
Host smart-6094864c-a234-4edf-bbd0-6df7ffcb46e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668937109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3668937109
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3897698082
Short name T504
Test name
Test status
Simulation time 220113854 ps
CPU time 1.46 seconds
Started Mar 12 12:43:23 PM PDT 24
Finished Mar 12 12:43:25 PM PDT 24
Peak memory 200356 kb
Host smart-439f5eab-cdf5-448f-8242-0aa958191665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897698082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3897698082
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3073317428
Short name T11
Test name
Test status
Simulation time 7874545642 ps
CPU time 28.68 seconds
Started Mar 12 12:43:26 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 200488 kb
Host smart-1519de9d-4795-49e6-b50d-dc4575019ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073317428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3073317428
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3519950361
Short name T463
Test name
Test status
Simulation time 267581758 ps
CPU time 1.71 seconds
Started Mar 12 12:43:22 PM PDT 24
Finished Mar 12 12:43:24 PM PDT 24
Peak memory 200104 kb
Host smart-3a244a65-502e-4d6a-ac51-688724d6f1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519950361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3519950361
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2883392454
Short name T73
Test name
Test status
Simulation time 86359483 ps
CPU time 0.85 seconds
Started Mar 12 12:43:23 PM PDT 24
Finished Mar 12 12:43:24 PM PDT 24
Peak memory 200360 kb
Host smart-418de6bd-148b-40fd-983b-a032d50dbb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883392454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2883392454
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2405451741
Short name T519
Test name
Test status
Simulation time 60442824 ps
CPU time 0.71 seconds
Started Mar 12 12:43:53 PM PDT 24
Finished Mar 12 12:43:54 PM PDT 24
Peak memory 200260 kb
Host smart-563aad2a-36df-46d1-8dbd-e59d58ca8a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405451741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2405451741
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1228728336
Short name T476
Test name
Test status
Simulation time 1893417853 ps
CPU time 6.97 seconds
Started Mar 12 12:43:57 PM PDT 24
Finished Mar 12 12:44:04 PM PDT 24
Peak memory 217632 kb
Host smart-b851be9b-db48-46c3-8448-b10b03f957da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228728336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1228728336
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1562488317
Short name T365
Test name
Test status
Simulation time 243774427 ps
CPU time 1.02 seconds
Started Mar 12 12:43:55 PM PDT 24
Finished Mar 12 12:43:56 PM PDT 24
Peak memory 217040 kb
Host smart-551f8c2d-b868-46ea-8f66-b7c161a602e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562488317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1562488317
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.223994432
Short name T461
Test name
Test status
Simulation time 1517092710 ps
CPU time 5.67 seconds
Started Mar 12 12:43:55 PM PDT 24
Finished Mar 12 12:44:01 PM PDT 24
Peak memory 200576 kb
Host smart-b79d4f7e-b1ce-4a5a-8ef5-f0e29bff4c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223994432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.223994432
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3638640765
Short name T242
Test name
Test status
Simulation time 181703001 ps
CPU time 1.25 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 200372 kb
Host smart-aeff2d1b-3349-40bd-a731-a6e97cbb9c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638640765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3638640765
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1224048651
Short name T271
Test name
Test status
Simulation time 257446301 ps
CPU time 1.47 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:43:56 PM PDT 24
Peak memory 200320 kb
Host smart-293b2f47-c9aa-46fd-b1c8-5b63c4b58bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224048651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1224048651
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1547615965
Short name T95
Test name
Test status
Simulation time 5355317501 ps
CPU time 19.98 seconds
Started Mar 12 12:43:53 PM PDT 24
Finished Mar 12 12:44:14 PM PDT 24
Peak memory 208788 kb
Host smart-74ad7c1e-172c-47f2-bc10-f7d0611d4600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547615965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1547615965
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.4118767641
Short name T75
Test name
Test status
Simulation time 471706043 ps
CPU time 2.49 seconds
Started Mar 12 12:43:52 PM PDT 24
Finished Mar 12 12:43:54 PM PDT 24
Peak memory 200212 kb
Host smart-8ba9ff1e-8162-4a52-932a-811314d052b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118767641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.4118767641
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4071148913
Short name T518
Test name
Test status
Simulation time 112941757 ps
CPU time 0.9 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 200364 kb
Host smart-409f3379-d3b6-4295-a0c6-75abd2a39f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071148913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4071148913
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1359268844
Short name T258
Test name
Test status
Simulation time 1218841601 ps
CPU time 5.6 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 218180 kb
Host smart-c0484609-9df9-433e-b6da-073b9dbfc71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359268844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1359268844
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3738502945
Short name T176
Test name
Test status
Simulation time 244070713 ps
CPU time 1.03 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:53 PM PDT 24
Peak memory 217132 kb
Host smart-bb93ca0c-c8f3-4a85-99d0-82616e7fb613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738502945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3738502945
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.684240611
Short name T15
Test name
Test status
Simulation time 197579903 ps
CPU time 0.88 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:50 PM PDT 24
Peak memory 200176 kb
Host smart-fd17028f-8198-4fe8-bc8e-20db3c41092b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684240611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.684240611
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.979725427
Short name T371
Test name
Test status
Simulation time 736075911 ps
CPU time 4.04 seconds
Started Mar 12 12:43:58 PM PDT 24
Finished Mar 12 12:44:02 PM PDT 24
Peak memory 200564 kb
Host smart-16aa8f7f-1334-4bed-b9a1-45493e21b6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979725427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.979725427
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2832889123
Short name T228
Test name
Test status
Simulation time 179994483 ps
CPU time 1.14 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 200216 kb
Host smart-0331ff4a-1ae7-49b4-85ed-85c8c2632937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832889123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2832889123
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3344200785
Short name T247
Test name
Test status
Simulation time 261106351 ps
CPU time 1.49 seconds
Started Mar 12 12:43:55 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 200460 kb
Host smart-78811099-d612-4d4d-9e0a-e911dddf3f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344200785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3344200785
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3049584448
Short name T409
Test name
Test status
Simulation time 10094105665 ps
CPU time 34.22 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:44:29 PM PDT 24
Peak memory 200496 kb
Host smart-491249cc-02e4-494e-867f-8f28ecd384a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049584448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3049584448
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2660517189
Short name T246
Test name
Test status
Simulation time 159532709 ps
CPU time 1.14 seconds
Started Mar 12 12:43:52 PM PDT 24
Finished Mar 12 12:43:53 PM PDT 24
Peak memory 200368 kb
Host smart-da367b8b-7481-4b03-8bd2-585c858a2b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660517189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2660517189
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2011206714
Short name T262
Test name
Test status
Simulation time 79118523 ps
CPU time 0.8 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:01 PM PDT 24
Peak memory 200252 kb
Host smart-e2c19cab-d033-4b21-801c-b7d57c668fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011206714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2011206714
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3758062909
Short name T538
Test name
Test status
Simulation time 2358420787 ps
CPU time 8.18 seconds
Started Mar 12 12:44:05 PM PDT 24
Finished Mar 12 12:44:13 PM PDT 24
Peak memory 221904 kb
Host smart-8743353a-8592-4e37-ae3b-545b9ac57327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758062909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3758062909
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.342912962
Short name T74
Test name
Test status
Simulation time 247912427 ps
CPU time 0.99 seconds
Started Mar 12 12:43:58 PM PDT 24
Finished Mar 12 12:44:00 PM PDT 24
Peak memory 217052 kb
Host smart-a901b023-f3ff-480b-a975-f2d139ae1f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342912962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.342912962
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2720394823
Short name T205
Test name
Test status
Simulation time 152079363 ps
CPU time 0.79 seconds
Started Mar 12 12:44:03 PM PDT 24
Finished Mar 12 12:44:04 PM PDT 24
Peak memory 200024 kb
Host smart-63fd4da5-f2f1-45f1-ad46-80b6372df5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720394823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2720394823
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3726096805
Short name T516
Test name
Test status
Simulation time 1876919592 ps
CPU time 6.93 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:07 PM PDT 24
Peak memory 200524 kb
Host smart-0094cbbc-d8f6-470b-b40a-f5fe01059cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726096805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3726096805
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1711315794
Short name T414
Test name
Test status
Simulation time 102064306 ps
CPU time 1.06 seconds
Started Mar 12 12:44:02 PM PDT 24
Finished Mar 12 12:44:03 PM PDT 24
Peak memory 200272 kb
Host smart-6c467f57-b077-49cd-8e28-0dc7fcda589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711315794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1711315794
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2860687333
Short name T439
Test name
Test status
Simulation time 115860435 ps
CPU time 1.24 seconds
Started Mar 12 12:44:01 PM PDT 24
Finished Mar 12 12:44:03 PM PDT 24
Peak memory 200392 kb
Host smart-3384c5ac-a333-47ba-8ea0-3a297f5e1607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860687333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2860687333
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.833324236
Short name T328
Test name
Test status
Simulation time 3380015463 ps
CPU time 14.46 seconds
Started Mar 12 12:44:01 PM PDT 24
Finished Mar 12 12:44:15 PM PDT 24
Peak memory 209560 kb
Host smart-608aee9b-c892-418f-971c-474cb8f980a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833324236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.833324236
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2779970697
Short name T317
Test name
Test status
Simulation time 124034481 ps
CPU time 1.57 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:02 PM PDT 24
Peak memory 208476 kb
Host smart-20905fa4-1426-464c-b65a-bcc761157484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779970697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2779970697
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1963090706
Short name T332
Test name
Test status
Simulation time 164241852 ps
CPU time 1.07 seconds
Started Mar 12 12:44:03 PM PDT 24
Finished Mar 12 12:44:04 PM PDT 24
Peak memory 200216 kb
Host smart-65df1e63-ab20-45b2-bac4-418301f09e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963090706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1963090706
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1985529400
Short name T181
Test name
Test status
Simulation time 82024210 ps
CPU time 0.82 seconds
Started Mar 12 12:43:56 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 200284 kb
Host smart-41e34100-a232-4351-9722-242867ddf335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985529400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1985529400
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.855765442
Short name T348
Test name
Test status
Simulation time 1225839833 ps
CPU time 5.6 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:44:00 PM PDT 24
Peak memory 229468 kb
Host smart-dd38997f-f2d2-4758-9b4f-6db97b01c52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855765442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.855765442
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.848466803
Short name T161
Test name
Test status
Simulation time 243704379 ps
CPU time 1.03 seconds
Started Mar 12 12:44:03 PM PDT 24
Finished Mar 12 12:44:04 PM PDT 24
Peak memory 217096 kb
Host smart-fcd7aa2b-d4e6-4b1f-801b-061397c66405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848466803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.848466803
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2927507964
Short name T526
Test name
Test status
Simulation time 122360179 ps
CPU time 0.76 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:01 PM PDT 24
Peak memory 200168 kb
Host smart-049b53ed-024b-4fd1-b62b-597c64eab875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927507964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2927507964
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3373137198
Short name T257
Test name
Test status
Simulation time 1025750839 ps
CPU time 4.84 seconds
Started Mar 12 12:44:01 PM PDT 24
Finished Mar 12 12:44:06 PM PDT 24
Peak memory 200520 kb
Host smart-09d8464f-09f3-40f3-b612-f4c8afc79626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373137198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3373137198
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4121032243
Short name T517
Test name
Test status
Simulation time 111858736 ps
CPU time 0.98 seconds
Started Mar 12 12:44:02 PM PDT 24
Finished Mar 12 12:44:03 PM PDT 24
Peak memory 200220 kb
Host smart-ab40979b-5ff7-48df-b3ef-b80cc2797309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121032243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4121032243
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3949530082
Short name T422
Test name
Test status
Simulation time 202611162 ps
CPU time 1.32 seconds
Started Mar 12 12:43:57 PM PDT 24
Finished Mar 12 12:43:58 PM PDT 24
Peak memory 200464 kb
Host smart-1ff41415-a527-4661-8e21-038629921c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949530082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3949530082
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2210718737
Short name T106
Test name
Test status
Simulation time 2283879009 ps
CPU time 9.91 seconds
Started Mar 12 12:44:02 PM PDT 24
Finished Mar 12 12:44:12 PM PDT 24
Peak memory 209944 kb
Host smart-de68f7b1-f29b-4b3b-a933-50ce96d66312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210718737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2210718737
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1522353540
Short name T388
Test name
Test status
Simulation time 145952371 ps
CPU time 1.81 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:02 PM PDT 24
Peak memory 200156 kb
Host smart-d388c432-a5c3-4bb9-9997-25408d141697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522353540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1522353540
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2410584592
Short name T153
Test name
Test status
Simulation time 71998147 ps
CPU time 0.79 seconds
Started Mar 12 12:43:55 PM PDT 24
Finished Mar 12 12:43:56 PM PDT 24
Peak memory 200332 kb
Host smart-064fe6ff-58b3-4916-bddf-1aab853ff5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410584592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2410584592
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.555563746
Short name T256
Test name
Test status
Simulation time 84242053 ps
CPU time 0.8 seconds
Started Mar 12 12:44:03 PM PDT 24
Finished Mar 12 12:44:04 PM PDT 24
Peak memory 200200 kb
Host smart-297b348a-10f1-4409-a4a0-87965c04bcc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555563746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.555563746
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1494695169
Short name T212
Test name
Test status
Simulation time 1226708963 ps
CPU time 5.22 seconds
Started Mar 12 12:44:03 PM PDT 24
Finished Mar 12 12:44:08 PM PDT 24
Peak memory 217216 kb
Host smart-acbd7977-9602-4e46-976d-6e40fcbc72ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494695169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1494695169
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2443742888
Short name T264
Test name
Test status
Simulation time 243525865 ps
CPU time 1.05 seconds
Started Mar 12 12:44:03 PM PDT 24
Finished Mar 12 12:44:04 PM PDT 24
Peak memory 217160 kb
Host smart-952db49b-4135-4bab-8fff-754b3bdaee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443742888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2443742888
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2999452201
Short name T17
Test name
Test status
Simulation time 179243765 ps
CPU time 0.82 seconds
Started Mar 12 12:43:58 PM PDT 24
Finished Mar 12 12:43:59 PM PDT 24
Peak memory 200156 kb
Host smart-a95623c6-9dee-44d2-b0ae-1dd035d9095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999452201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2999452201
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.721719196
Short name T284
Test name
Test status
Simulation time 1001570504 ps
CPU time 4.76 seconds
Started Mar 12 12:44:02 PM PDT 24
Finished Mar 12 12:44:07 PM PDT 24
Peak memory 200352 kb
Host smart-d2e695b3-0dc9-459d-8f41-cb7a9052aa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721719196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.721719196
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1572688737
Short name T482
Test name
Test status
Simulation time 100620166 ps
CPU time 0.96 seconds
Started Mar 12 12:44:03 PM PDT 24
Finished Mar 12 12:44:04 PM PDT 24
Peak memory 200208 kb
Host smart-4f853f5c-5c3e-4436-965c-a4e41a091d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572688737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1572688737
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3761906278
Short name T495
Test name
Test status
Simulation time 194403829 ps
CPU time 1.39 seconds
Started Mar 12 12:43:57 PM PDT 24
Finished Mar 12 12:43:59 PM PDT 24
Peak memory 200496 kb
Host smart-fa2c3b76-e825-47d5-883e-8b630265c177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761906278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3761906278
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1232285539
Short name T180
Test name
Test status
Simulation time 517323614 ps
CPU time 2.56 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:03 PM PDT 24
Peak memory 200192 kb
Host smart-d00dd41b-8051-4bd7-b82c-ab56adb281f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232285539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1232285539
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3740791634
Short name T416
Test name
Test status
Simulation time 134980687 ps
CPU time 1.1 seconds
Started Mar 12 12:44:01 PM PDT 24
Finished Mar 12 12:44:02 PM PDT 24
Peak memory 200368 kb
Host smart-10b73d14-61a7-4b74-b19c-da53434b21d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740791634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3740791634
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.128047318
Short name T155
Test name
Test status
Simulation time 78614877 ps
CPU time 0.75 seconds
Started Mar 12 12:43:56 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 200148 kb
Host smart-deeda1d6-ddba-4e8c-a944-db6467e1a256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128047318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.128047318
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1299665882
Short name T374
Test name
Test status
Simulation time 1893383686 ps
CPU time 7.12 seconds
Started Mar 12 12:43:56 PM PDT 24
Finished Mar 12 12:44:03 PM PDT 24
Peak memory 216540 kb
Host smart-080d2d3f-212d-49f0-a833-c0e0e6ff170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299665882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1299665882
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1710276420
Short name T299
Test name
Test status
Simulation time 244573594 ps
CPU time 1.06 seconds
Started Mar 12 12:44:01 PM PDT 24
Finished Mar 12 12:44:03 PM PDT 24
Peak memory 217108 kb
Host smart-754ab4f6-bf1f-45c7-b5f7-047f2b69f7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710276420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1710276420
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3201631168
Short name T527
Test name
Test status
Simulation time 145829984 ps
CPU time 0.81 seconds
Started Mar 12 12:43:59 PM PDT 24
Finished Mar 12 12:43:59 PM PDT 24
Peak memory 200064 kb
Host smart-cb343834-46ac-49ac-a014-1b4824ca223f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201631168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3201631168
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3523887722
Short name T501
Test name
Test status
Simulation time 1651761730 ps
CPU time 6.84 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:07 PM PDT 24
Peak memory 200460 kb
Host smart-e9a01d6e-d23f-46c4-8799-c98652536974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523887722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3523887722
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.421590158
Short name T294
Test name
Test status
Simulation time 148733668 ps
CPU time 1.13 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:02 PM PDT 24
Peak memory 200276 kb
Host smart-e20f0b05-adf5-4afe-a17a-c51f5d765131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421590158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.421590158
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2662573568
Short name T437
Test name
Test status
Simulation time 115290510 ps
CPU time 1.16 seconds
Started Mar 12 12:43:59 PM PDT 24
Finished Mar 12 12:44:01 PM PDT 24
Peak memory 200432 kb
Host smart-d4c7db93-812e-479f-869f-cbc70134c4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662573568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2662573568
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.734133517
Short name T381
Test name
Test status
Simulation time 2597759959 ps
CPU time 9.38 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:09 PM PDT 24
Peak memory 200604 kb
Host smart-7e69add8-64d2-4a29-a7fc-42627c1190b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734133517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.734133517
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1485850874
Short name T502
Test name
Test status
Simulation time 138622959 ps
CPU time 1.66 seconds
Started Mar 12 12:44:00 PM PDT 24
Finished Mar 12 12:44:01 PM PDT 24
Peak memory 208396 kb
Host smart-4f3d9409-ffb7-4eb0-b88e-29346f89228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485850874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1485850874
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.4167841066
Short name T324
Test name
Test status
Simulation time 253040569 ps
CPU time 1.45 seconds
Started Mar 12 12:43:57 PM PDT 24
Finished Mar 12 12:43:59 PM PDT 24
Peak memory 200376 kb
Host smart-a1281ccc-0802-456c-8758-e274fa304a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167841066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.4167841066
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1243803025
Short name T301
Test name
Test status
Simulation time 63038889 ps
CPU time 0.74 seconds
Started Mar 12 12:44:10 PM PDT 24
Finished Mar 12 12:44:11 PM PDT 24
Peak memory 200240 kb
Host smart-f4e553a4-fb9c-4ec7-919a-43f7e41460a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243803025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1243803025
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.546613712
Short name T362
Test name
Test status
Simulation time 2352501428 ps
CPU time 8.03 seconds
Started Mar 12 12:44:06 PM PDT 24
Finished Mar 12 12:44:14 PM PDT 24
Peak memory 217352 kb
Host smart-aed4743f-d02d-404d-9b57-0f956db663cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546613712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.546613712
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.925560180
Short name T442
Test name
Test status
Simulation time 243742178 ps
CPU time 1.03 seconds
Started Mar 12 12:44:05 PM PDT 24
Finished Mar 12 12:44:06 PM PDT 24
Peak memory 217168 kb
Host smart-018eb79f-6ff4-4fb5-be0c-79ab178f5bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925560180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.925560180
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1961022124
Short name T19
Test name
Test status
Simulation time 90943379 ps
CPU time 0.73 seconds
Started Mar 12 12:44:04 PM PDT 24
Finished Mar 12 12:44:05 PM PDT 24
Peak memory 200180 kb
Host smart-7d71e0a5-8d96-4348-9759-bac88a3657a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961022124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1961022124
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.172487505
Short name T118
Test name
Test status
Simulation time 1687215890 ps
CPU time 6.24 seconds
Started Mar 12 12:44:03 PM PDT 24
Finished Mar 12 12:44:09 PM PDT 24
Peak memory 200348 kb
Host smart-49922cc2-6ce3-43a5-9c68-164c9ead4aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172487505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.172487505
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.4014804189
Short name T389
Test name
Test status
Simulation time 150065334 ps
CPU time 1.11 seconds
Started Mar 12 12:44:09 PM PDT 24
Finished Mar 12 12:44:10 PM PDT 24
Peak memory 200364 kb
Host smart-65589a3f-2cba-4960-bdc7-cbd8d46d264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014804189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.4014804189
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1791750611
Short name T240
Test name
Test status
Simulation time 181332741 ps
CPU time 1.26 seconds
Started Mar 12 12:44:01 PM PDT 24
Finished Mar 12 12:44:02 PM PDT 24
Peak memory 200364 kb
Host smart-e09fe917-f3be-4d02-a565-cd138af938bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791750611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1791750611
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2260172560
Short name T503
Test name
Test status
Simulation time 198791913 ps
CPU time 1.23 seconds
Started Mar 12 12:44:05 PM PDT 24
Finished Mar 12 12:44:06 PM PDT 24
Peak memory 200164 kb
Host smart-4b0668b4-038a-467a-b7ce-560a4eb21058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260172560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2260172560
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.553773298
Short name T450
Test name
Test status
Simulation time 147986305 ps
CPU time 1.84 seconds
Started Mar 12 12:44:05 PM PDT 24
Finished Mar 12 12:44:07 PM PDT 24
Peak memory 200232 kb
Host smart-482fd368-6f11-4256-8eaa-d7e1bedfa322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553773298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.553773298
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.424618813
Short name T393
Test name
Test status
Simulation time 75576460 ps
CPU time 0.77 seconds
Started Mar 12 12:44:04 PM PDT 24
Finished Mar 12 12:44:05 PM PDT 24
Peak memory 200208 kb
Host smart-758d6f87-689c-4d92-93f2-44d8a716243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424618813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.424618813
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2807347597
Short name T255
Test name
Test status
Simulation time 79820170 ps
CPU time 0.77 seconds
Started Mar 12 12:44:05 PM PDT 24
Finished Mar 12 12:44:06 PM PDT 24
Peak memory 200056 kb
Host smart-39997cdb-3e09-43d2-be21-03115ffcef29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807347597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2807347597
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3284159788
Short name T1
Test name
Test status
Simulation time 1224374595 ps
CPU time 5.54 seconds
Started Mar 12 12:44:07 PM PDT 24
Finished Mar 12 12:44:13 PM PDT 24
Peak memory 221752 kb
Host smart-7b3d72ef-c0cc-4f2a-932f-07e85bd00f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284159788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3284159788
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.271217665
Short name T491
Test name
Test status
Simulation time 243913496 ps
CPU time 1.16 seconds
Started Mar 12 12:44:10 PM PDT 24
Finished Mar 12 12:44:11 PM PDT 24
Peak memory 217068 kb
Host smart-ae671a53-1610-416e-9a26-1ed29d43190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271217665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.271217665
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1412591178
Short name T432
Test name
Test status
Simulation time 230865966 ps
CPU time 1.01 seconds
Started Mar 12 12:44:06 PM PDT 24
Finished Mar 12 12:44:07 PM PDT 24
Peak memory 200112 kb
Host smart-aa299628-4ec1-4086-af61-ee4ba1a0d232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412591178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1412591178
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2432489455
Short name T173
Test name
Test status
Simulation time 1108783121 ps
CPU time 5.08 seconds
Started Mar 12 12:44:05 PM PDT 24
Finished Mar 12 12:44:10 PM PDT 24
Peak memory 200508 kb
Host smart-85b7d6c4-14de-4d3f-952e-282a71ccc848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432489455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2432489455
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.615337913
Short name T384
Test name
Test status
Simulation time 197489525 ps
CPU time 1.29 seconds
Started Mar 12 12:44:09 PM PDT 24
Finished Mar 12 12:44:10 PM PDT 24
Peak memory 200508 kb
Host smart-63127eb1-931e-4991-a05c-91c4fc3c64a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615337913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.615337913
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.939983289
Short name T302
Test name
Test status
Simulation time 3081230450 ps
CPU time 10.88 seconds
Started Mar 12 12:44:08 PM PDT 24
Finished Mar 12 12:44:20 PM PDT 24
Peak memory 200564 kb
Host smart-f215e80d-e314-4430-afc8-a6915786f720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939983289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.939983289
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4272026232
Short name T54
Test name
Test status
Simulation time 129951187 ps
CPU time 1.73 seconds
Started Mar 12 12:44:06 PM PDT 24
Finished Mar 12 12:44:08 PM PDT 24
Peak memory 200308 kb
Host smart-7dc15ffa-445b-48c7-aaf2-e5a1bdc94813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272026232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4272026232
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3232514028
Short name T510
Test name
Test status
Simulation time 121787358 ps
CPU time 0.9 seconds
Started Mar 12 12:44:04 PM PDT 24
Finished Mar 12 12:44:05 PM PDT 24
Peak memory 200348 kb
Host smart-1557d2f1-eeff-434f-8fb4-cd87c1779c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232514028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3232514028
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3546907623
Short name T209
Test name
Test status
Simulation time 90451804 ps
CPU time 0.78 seconds
Started Mar 12 12:44:16 PM PDT 24
Finished Mar 12 12:44:17 PM PDT 24
Peak memory 200280 kb
Host smart-bd0dc5fe-2ba9-45e8-8f83-afa2b0cda08c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546907623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3546907623
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.438601428
Short name T520
Test name
Test status
Simulation time 1223547811 ps
CPU time 5.94 seconds
Started Mar 12 12:44:17 PM PDT 24
Finished Mar 12 12:44:24 PM PDT 24
Peak memory 217672 kb
Host smart-a2c67036-e928-4a50-9f64-c870fd37c425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438601428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.438601428
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.720056313
Short name T243
Test name
Test status
Simulation time 243083218 ps
CPU time 1.04 seconds
Started Mar 12 12:44:15 PM PDT 24
Finished Mar 12 12:44:16 PM PDT 24
Peak memory 217128 kb
Host smart-a2dfbd6a-3a7d-44af-943f-ef83ae57b124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720056313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.720056313
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1786479029
Short name T280
Test name
Test status
Simulation time 104621546 ps
CPU time 0.78 seconds
Started Mar 12 12:44:06 PM PDT 24
Finished Mar 12 12:44:07 PM PDT 24
Peak memory 200056 kb
Host smart-d9959883-3b83-4249-843f-2bafa7374c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786479029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1786479029
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.157573408
Short name T425
Test name
Test status
Simulation time 1016280062 ps
CPU time 4.66 seconds
Started Mar 12 12:44:05 PM PDT 24
Finished Mar 12 12:44:10 PM PDT 24
Peak memory 200516 kb
Host smart-5bcc3443-e8dc-4de4-8a54-ae1ab776730e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157573408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.157573408
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.153281145
Short name T150
Test name
Test status
Simulation time 104283444 ps
CPU time 0.95 seconds
Started Mar 12 12:44:18 PM PDT 24
Finished Mar 12 12:44:19 PM PDT 24
Peak memory 200404 kb
Host smart-12c27e0d-9ceb-44ac-8b6c-6ee80d9fd9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153281145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.153281145
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3772174575
Short name T486
Test name
Test status
Simulation time 116665000 ps
CPU time 1.11 seconds
Started Mar 12 12:44:08 PM PDT 24
Finished Mar 12 12:44:10 PM PDT 24
Peak memory 200408 kb
Host smart-ccf6524a-b598-449e-a957-b885e18fb12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772174575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3772174575
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.197193283
Short name T368
Test name
Test status
Simulation time 1198617252 ps
CPU time 5.4 seconds
Started Mar 12 12:44:15 PM PDT 24
Finished Mar 12 12:44:21 PM PDT 24
Peak memory 200536 kb
Host smart-7f534962-bc4e-49fe-ac28-3cff118e25b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197193283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.197193283
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1609092650
Short name T485
Test name
Test status
Simulation time 436243227 ps
CPU time 2.38 seconds
Started Mar 12 12:44:19 PM PDT 24
Finished Mar 12 12:44:22 PM PDT 24
Peak memory 200252 kb
Host smart-13de4132-cb75-4b2b-9804-196bda46a18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609092650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1609092650
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2031526358
Short name T137
Test name
Test status
Simulation time 79996612 ps
CPU time 0.79 seconds
Started Mar 12 12:44:07 PM PDT 24
Finished Mar 12 12:44:08 PM PDT 24
Peak memory 200368 kb
Host smart-00804bc2-fa17-4cdc-9146-d30e2e362e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031526358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2031526358
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.656547814
Short name T168
Test name
Test status
Simulation time 73814308 ps
CPU time 0.77 seconds
Started Mar 12 12:44:15 PM PDT 24
Finished Mar 12 12:44:16 PM PDT 24
Peak memory 200268 kb
Host smart-c06d5a9a-4c77-4c22-9168-c2c8a552abde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656547814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.656547814
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2712024466
Short name T259
Test name
Test status
Simulation time 247733883 ps
CPU time 1.04 seconds
Started Mar 12 12:44:16 PM PDT 24
Finished Mar 12 12:44:17 PM PDT 24
Peak memory 217172 kb
Host smart-41304dc1-0c14-4064-860c-d9697efcc233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712024466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2712024466
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2500550327
Short name T426
Test name
Test status
Simulation time 204161370 ps
CPU time 0.95 seconds
Started Mar 12 12:44:17 PM PDT 24
Finished Mar 12 12:44:18 PM PDT 24
Peak memory 200056 kb
Host smart-f5f9c4a0-47b3-478e-8858-7fee9ab4481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500550327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2500550327
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3984727533
Short name T431
Test name
Test status
Simulation time 918831661 ps
CPU time 4.61 seconds
Started Mar 12 12:44:17 PM PDT 24
Finished Mar 12 12:44:22 PM PDT 24
Peak memory 200528 kb
Host smart-186d0770-392e-4d73-82de-ac59bdd9627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984727533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3984727533
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2569371368
Short name T347
Test name
Test status
Simulation time 181528388 ps
CPU time 1.24 seconds
Started Mar 12 12:44:18 PM PDT 24
Finished Mar 12 12:44:19 PM PDT 24
Peak memory 200320 kb
Host smart-619446bc-e0c8-49bf-bba4-822ebbc45e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569371368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2569371368
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.905160677
Short name T304
Test name
Test status
Simulation time 196455195 ps
CPU time 1.29 seconds
Started Mar 12 12:44:15 PM PDT 24
Finished Mar 12 12:44:16 PM PDT 24
Peak memory 200436 kb
Host smart-a8c9c264-2cff-4a75-b44a-fa5d47136d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905160677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.905160677
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.20463306
Short name T182
Test name
Test status
Simulation time 1467635100 ps
CPU time 7.39 seconds
Started Mar 12 12:44:19 PM PDT 24
Finished Mar 12 12:44:27 PM PDT 24
Peak memory 200524 kb
Host smart-ac370bda-8305-4ad5-90d6-4b75b434d95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20463306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.20463306
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3708602547
Short name T457
Test name
Test status
Simulation time 127024942 ps
CPU time 1.46 seconds
Started Mar 12 12:44:16 PM PDT 24
Finished Mar 12 12:44:18 PM PDT 24
Peak memory 200156 kb
Host smart-972bdf31-1140-4aba-a25e-39dfdd99d8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708602547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3708602547
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3490911979
Short name T533
Test name
Test status
Simulation time 118995048 ps
CPU time 0.94 seconds
Started Mar 12 12:44:16 PM PDT 24
Finished Mar 12 12:44:18 PM PDT 24
Peak memory 200368 kb
Host smart-c6bdd76e-bd88-4105-9333-1e291478be97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490911979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3490911979
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2683982037
Short name T141
Test name
Test status
Simulation time 80065659 ps
CPU time 0.85 seconds
Started Mar 12 12:43:38 PM PDT 24
Finished Mar 12 12:43:39 PM PDT 24
Peak memory 200112 kb
Host smart-a3eafbe8-c98f-4ef3-baf4-35089324c364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683982037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2683982037
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2985679274
Short name T43
Test name
Test status
Simulation time 1217245299 ps
CPU time 6 seconds
Started Mar 12 12:43:39 PM PDT 24
Finished Mar 12 12:43:45 PM PDT 24
Peak memory 218112 kb
Host smart-10569692-cd85-4967-a0f2-d43b41428e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985679274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2985679274
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2261899591
Short name T154
Test name
Test status
Simulation time 249997730 ps
CPU time 1.08 seconds
Started Mar 12 12:43:38 PM PDT 24
Finished Mar 12 12:43:39 PM PDT 24
Peak memory 217096 kb
Host smart-3cc5666b-a22d-4163-8ba7-37ce5253c471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261899591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2261899591
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.679088775
Short name T6
Test name
Test status
Simulation time 220819571 ps
CPU time 0.98 seconds
Started Mar 12 12:43:40 PM PDT 24
Finished Mar 12 12:43:41 PM PDT 24
Peak memory 200016 kb
Host smart-529ff474-99ca-40f9-a7ba-f5bcec59fee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679088775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.679088775
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.745188383
Short name T308
Test name
Test status
Simulation time 1902761970 ps
CPU time 6.81 seconds
Started Mar 12 12:43:38 PM PDT 24
Finished Mar 12 12:43:45 PM PDT 24
Peak memory 200476 kb
Host smart-c759891e-bec2-4dd9-a907-5b4418612be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745188383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.745188383
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3146817150
Short name T64
Test name
Test status
Simulation time 16534445717 ps
CPU time 30.4 seconds
Started Mar 12 12:43:40 PM PDT 24
Finished Mar 12 12:44:10 PM PDT 24
Peak memory 216760 kb
Host smart-3fda4b73-40ea-4208-aa63-fcb6da055fcc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146817150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3146817150
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1673339375
Short name T367
Test name
Test status
Simulation time 171064641 ps
CPU time 1.13 seconds
Started Mar 12 12:43:35 PM PDT 24
Finished Mar 12 12:43:36 PM PDT 24
Peak memory 200396 kb
Host smart-4c883939-9373-414e-b519-362ec60a17bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673339375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1673339375
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.193753418
Short name T513
Test name
Test status
Simulation time 251822267 ps
CPU time 1.52 seconds
Started Mar 12 12:43:36 PM PDT 24
Finished Mar 12 12:43:38 PM PDT 24
Peak memory 200352 kb
Host smart-0b81df17-b4c3-419d-b3b0-fc5dd9aac13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193753418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.193753418
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.642289857
Short name T50
Test name
Test status
Simulation time 2074512247 ps
CPU time 7.03 seconds
Started Mar 12 12:43:40 PM PDT 24
Finished Mar 12 12:43:47 PM PDT 24
Peak memory 200408 kb
Host smart-b92cb3d3-850b-46f2-9600-ea000dfa4bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642289857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.642289857
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.231947182
Short name T68
Test name
Test status
Simulation time 119442119 ps
CPU time 0.97 seconds
Started Mar 12 12:43:37 PM PDT 24
Finished Mar 12 12:43:38 PM PDT 24
Peak memory 200380 kb
Host smart-20a17141-fe62-4548-8805-b640399afc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231947182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.231947182
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2399783927
Short name T436
Test name
Test status
Simulation time 62739596 ps
CPU time 0.76 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:25 PM PDT 24
Peak memory 200200 kb
Host smart-f7dc77f8-a0ac-4546-99d8-05ed4021ec8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399783927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2399783927
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1577823942
Short name T411
Test name
Test status
Simulation time 1892044676 ps
CPU time 7.27 seconds
Started Mar 12 12:44:26 PM PDT 24
Finished Mar 12 12:44:33 PM PDT 24
Peak memory 217060 kb
Host smart-200a9753-cab2-42db-8d71-2cf0a73eb13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577823942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1577823942
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2741288999
Short name T166
Test name
Test status
Simulation time 245791000 ps
CPU time 0.99 seconds
Started Mar 12 12:44:26 PM PDT 24
Finished Mar 12 12:44:27 PM PDT 24
Peak memory 217124 kb
Host smart-6820894f-4166-472a-9b85-aeea7e40de9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741288999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2741288999
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3068100379
Short name T199
Test name
Test status
Simulation time 106072798 ps
CPU time 0.79 seconds
Started Mar 12 12:44:14 PM PDT 24
Finished Mar 12 12:44:15 PM PDT 24
Peak memory 200180 kb
Host smart-85d4d084-905c-4d12-b05c-37a19803ba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068100379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3068100379
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2047397011
Short name T397
Test name
Test status
Simulation time 1850369943 ps
CPU time 6.58 seconds
Started Mar 12 12:44:17 PM PDT 24
Finished Mar 12 12:44:24 PM PDT 24
Peak memory 200380 kb
Host smart-da814aea-f85c-49a2-8087-181bffc71cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047397011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2047397011
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4144131498
Short name T261
Test name
Test status
Simulation time 96401776 ps
CPU time 1.02 seconds
Started Mar 12 12:44:27 PM PDT 24
Finished Mar 12 12:44:28 PM PDT 24
Peak memory 200372 kb
Host smart-e8e3d776-d2aa-4d40-a48c-e507da03fb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144131498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4144131498
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.4253575289
Short name T338
Test name
Test status
Simulation time 228291780 ps
CPU time 1.44 seconds
Started Mar 12 12:44:18 PM PDT 24
Finished Mar 12 12:44:20 PM PDT 24
Peak memory 200400 kb
Host smart-fc983c05-eaf7-4e9b-b257-db53d8931b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253575289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4253575289
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3305583915
Short name T186
Test name
Test status
Simulation time 2175997340 ps
CPU time 7.71 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:33 PM PDT 24
Peak memory 208828 kb
Host smart-0ee25533-54b2-4168-a910-c9c7b9ac3630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305583915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3305583915
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3392280754
Short name T143
Test name
Test status
Simulation time 124775914 ps
CPU time 1.69 seconds
Started Mar 12 12:44:26 PM PDT 24
Finished Mar 12 12:44:28 PM PDT 24
Peak memory 200176 kb
Host smart-d4afa215-70c6-4973-acd2-0d832126f12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392280754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3392280754
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.102844622
Short name T390
Test name
Test status
Simulation time 86320135 ps
CPU time 0.88 seconds
Started Mar 12 12:44:17 PM PDT 24
Finished Mar 12 12:44:18 PM PDT 24
Peak memory 200304 kb
Host smart-f6277269-fa91-449e-94e9-a27d2efbb771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102844622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.102844622
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.4124106282
Short name T534
Test name
Test status
Simulation time 68408131 ps
CPU time 0.78 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:26 PM PDT 24
Peak memory 200120 kb
Host smart-78cf9583-73b5-459b-811f-b4fc5279daa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124106282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.4124106282
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1629412277
Short name T488
Test name
Test status
Simulation time 1225698085 ps
CPU time 6 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:31 PM PDT 24
Peak memory 220840 kb
Host smart-8ff05a69-10aa-4d8c-ae48-fbde02f0a6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629412277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1629412277
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3347652685
Short name T492
Test name
Test status
Simulation time 243998416 ps
CPU time 1.03 seconds
Started Mar 12 12:44:24 PM PDT 24
Finished Mar 12 12:44:25 PM PDT 24
Peak memory 217096 kb
Host smart-e4f1ce95-1a83-4456-98e6-6426730477ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347652685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3347652685
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3760095434
Short name T298
Test name
Test status
Simulation time 77497107 ps
CPU time 0.83 seconds
Started Mar 12 12:44:23 PM PDT 24
Finished Mar 12 12:44:24 PM PDT 24
Peak memory 200056 kb
Host smart-ffcb657e-5458-474e-b524-974a2478cf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760095434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3760095434
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.115056916
Short name T428
Test name
Test status
Simulation time 1187822593 ps
CPU time 4.94 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:30 PM PDT 24
Peak memory 200528 kb
Host smart-8b15dfcb-2a6c-40f1-99fa-d3acd206a797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115056916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.115056916
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1532171520
Short name T542
Test name
Test status
Simulation time 112609535 ps
CPU time 0.99 seconds
Started Mar 12 12:44:27 PM PDT 24
Finished Mar 12 12:44:28 PM PDT 24
Peak memory 200272 kb
Host smart-f155b1fc-a20a-4f17-b071-3bb02d880b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532171520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1532171520
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3486190149
Short name T142
Test name
Test status
Simulation time 186357927 ps
CPU time 1.32 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:26 PM PDT 24
Peak memory 200452 kb
Host smart-e7009283-00bd-436f-ad7c-cb6e4eeac20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486190149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3486190149
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.654709871
Short name T458
Test name
Test status
Simulation time 97323572 ps
CPU time 1.03 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:26 PM PDT 24
Peak memory 200224 kb
Host smart-c367e9ee-84af-4354-b87f-2999c2e7264a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654709871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.654709871
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2526417733
Short name T252
Test name
Test status
Simulation time 406529180 ps
CPU time 2.26 seconds
Started Mar 12 12:44:26 PM PDT 24
Finished Mar 12 12:44:29 PM PDT 24
Peak memory 200088 kb
Host smart-d7175b35-eec5-4800-945e-0855f89d1632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526417733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2526417733
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2844117440
Short name T311
Test name
Test status
Simulation time 66649547 ps
CPU time 0.77 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:26 PM PDT 24
Peak memory 200216 kb
Host smart-22c3857d-46e4-4fb0-a782-794d4c78f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844117440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2844117440
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2317284507
Short name T385
Test name
Test status
Simulation time 68069092 ps
CPU time 0.74 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:26 PM PDT 24
Peak memory 200292 kb
Host smart-4b19d0b5-52b4-4b60-bf26-db44cb194f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317284507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2317284507
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.160673823
Short name T480
Test name
Test status
Simulation time 2168132559 ps
CPU time 7.71 seconds
Started Mar 12 12:44:26 PM PDT 24
Finished Mar 12 12:44:34 PM PDT 24
Peak memory 217156 kb
Host smart-aacafd69-1154-47fc-9681-257b84f03db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160673823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.160673823
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.395402016
Short name T460
Test name
Test status
Simulation time 244616435 ps
CPU time 1.02 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:26 PM PDT 24
Peak memory 217220 kb
Host smart-478147bb-63b5-4820-b9c4-3cfb1098ed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395402016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.395402016
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3825290545
Short name T417
Test name
Test status
Simulation time 93576424 ps
CPU time 0.74 seconds
Started Mar 12 12:44:23 PM PDT 24
Finished Mar 12 12:44:24 PM PDT 24
Peak memory 200140 kb
Host smart-b8f3d733-199e-455f-89fd-d6e6aa987bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825290545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3825290545
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1849608693
Short name T3
Test name
Test status
Simulation time 1905757866 ps
CPU time 7.3 seconds
Started Mar 12 12:44:23 PM PDT 24
Finished Mar 12 12:44:30 PM PDT 24
Peak memory 200544 kb
Host smart-542a5f19-6d80-4b82-9dc0-1823de79611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849608693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1849608693
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1660112004
Short name T320
Test name
Test status
Simulation time 104499772 ps
CPU time 1.01 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:26 PM PDT 24
Peak memory 200344 kb
Host smart-fab1c8de-acbf-4aee-9982-e5067fda7bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660112004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1660112004
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1220953248
Short name T177
Test name
Test status
Simulation time 257916680 ps
CPU time 1.47 seconds
Started Mar 12 12:44:25 PM PDT 24
Finished Mar 12 12:44:26 PM PDT 24
Peak memory 200488 kb
Host smart-ebea746e-5c19-4dab-8af9-bde142d69ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220953248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1220953248
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2126005925
Short name T221
Test name
Test status
Simulation time 4947577712 ps
CPU time 17.84 seconds
Started Mar 12 12:44:28 PM PDT 24
Finished Mar 12 12:44:46 PM PDT 24
Peak memory 210196 kb
Host smart-d3646d00-ba45-4d01-839e-05f7505b8a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126005925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2126005925
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2362650163
Short name T413
Test name
Test status
Simulation time 134323801 ps
CPU time 1.64 seconds
Started Mar 12 12:44:23 PM PDT 24
Finished Mar 12 12:44:25 PM PDT 24
Peak memory 208504 kb
Host smart-75d02504-27c1-4264-a7d8-78409b9ddfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362650163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2362650163
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1262720361
Short name T178
Test name
Test status
Simulation time 131453259 ps
CPU time 1.04 seconds
Started Mar 12 12:44:26 PM PDT 24
Finished Mar 12 12:44:27 PM PDT 24
Peak memory 200184 kb
Host smart-dc3d3878-3e28-424b-9043-3fdcdc688849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262720361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1262720361
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3277748200
Short name T175
Test name
Test status
Simulation time 72946011 ps
CPU time 0.75 seconds
Started Mar 12 12:44:33 PM PDT 24
Finished Mar 12 12:44:34 PM PDT 24
Peak memory 200168 kb
Host smart-e6b6bb1e-b65a-45d3-9710-a3c68b6cce38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277748200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3277748200
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2531067346
Short name T429
Test name
Test status
Simulation time 1230877317 ps
CPU time 5.41 seconds
Started Mar 12 12:44:34 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 218068 kb
Host smart-5caa3d93-ddeb-4d71-8eac-8fdd62886035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531067346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2531067346
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1968535584
Short name T296
Test name
Test status
Simulation time 245031294 ps
CPU time 1.09 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:37 PM PDT 24
Peak memory 217212 kb
Host smart-888947e4-3be5-46c4-a950-0c64b8e4adbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968535584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1968535584
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3570852250
Short name T16
Test name
Test status
Simulation time 81867476 ps
CPU time 0.72 seconds
Started Mar 12 12:44:34 PM PDT 24
Finished Mar 12 12:44:35 PM PDT 24
Peak memory 200192 kb
Host smart-bcdb3d95-f14a-4595-a77a-8ec6a089cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570852250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3570852250
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1413124704
Short name T366
Test name
Test status
Simulation time 1525741595 ps
CPU time 5.71 seconds
Started Mar 12 12:44:33 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 200496 kb
Host smart-05f5d213-16bc-46ab-b405-b33e8b76da96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413124704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1413124704
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.35019249
Short name T465
Test name
Test status
Simulation time 106022683 ps
CPU time 1.06 seconds
Started Mar 12 12:44:34 PM PDT 24
Finished Mar 12 12:44:35 PM PDT 24
Peak memory 200364 kb
Host smart-0e595bff-21e2-43c2-a009-124c13e7a5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35019249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.35019249
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3672053658
Short name T70
Test name
Test status
Simulation time 262947355 ps
CPU time 1.47 seconds
Started Mar 12 12:44:34 PM PDT 24
Finished Mar 12 12:44:36 PM PDT 24
Peak memory 200456 kb
Host smart-d89d2534-6f4d-4366-b602-5fe31cdb4254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672053658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3672053658
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.98519635
Short name T383
Test name
Test status
Simulation time 1694219468 ps
CPU time 6.27 seconds
Started Mar 12 12:44:33 PM PDT 24
Finished Mar 12 12:44:39 PM PDT 24
Peak memory 200512 kb
Host smart-5d5728d9-c573-4d8d-8474-e56f9ab265e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98519635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.98519635
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2523096785
Short name T349
Test name
Test status
Simulation time 419410893 ps
CPU time 2.33 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:39 PM PDT 24
Peak memory 200316 kb
Host smart-64af61c9-fb93-462b-a9c7-e54efd08d4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523096785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2523096785
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.748553357
Short name T293
Test name
Test status
Simulation time 163735910 ps
CPU time 1.08 seconds
Started Mar 12 12:44:33 PM PDT 24
Finished Mar 12 12:44:34 PM PDT 24
Peak memory 200368 kb
Host smart-8afc5cdc-cb8b-4b0f-9d83-063a408f7d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748553357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.748553357
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.840707601
Short name T8
Test name
Test status
Simulation time 83528158 ps
CPU time 0.81 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 200220 kb
Host smart-c94fa18a-29bd-43c7-b5c9-f0cabb3c7bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840707601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.840707601
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3191202989
Short name T274
Test name
Test status
Simulation time 2338505727 ps
CPU time 8.38 seconds
Started Mar 12 12:44:33 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 217444 kb
Host smart-9f40077b-a5e6-4e3b-8dd8-852054f2f617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191202989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3191202989
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.424430462
Short name T149
Test name
Test status
Simulation time 243832240 ps
CPU time 1.05 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:36 PM PDT 24
Peak memory 217224 kb
Host smart-57f31d22-42f4-4843-ac34-3b5b871b4262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424430462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.424430462
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3621686412
Short name T382
Test name
Test status
Simulation time 175910599 ps
CPU time 0.92 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 200120 kb
Host smart-d7271a59-a5cb-4957-a507-17590a16a3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621686412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3621686412
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.571356789
Short name T292
Test name
Test status
Simulation time 1733928323 ps
CPU time 6.64 seconds
Started Mar 12 12:44:37 PM PDT 24
Finished Mar 12 12:44:45 PM PDT 24
Peak memory 200424 kb
Host smart-c66b47cc-c4de-4807-beab-6b695b5af575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571356789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.571356789
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.105646705
Short name T133
Test name
Test status
Simulation time 144785296 ps
CPU time 1.15 seconds
Started Mar 12 12:44:34 PM PDT 24
Finished Mar 12 12:44:35 PM PDT 24
Peak memory 200356 kb
Host smart-99b63733-20aa-4bae-a6a2-48601ce72121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105646705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.105646705
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.917491959
Short name T210
Test name
Test status
Simulation time 191984182 ps
CPU time 1.38 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:37 PM PDT 24
Peak memory 200388 kb
Host smart-071b95f3-1b17-42dd-93ab-4587fdd401f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917491959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.917491959
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1437230655
Short name T440
Test name
Test status
Simulation time 5741586366 ps
CPU time 20.87 seconds
Started Mar 12 12:44:33 PM PDT 24
Finished Mar 12 12:44:54 PM PDT 24
Peak memory 200604 kb
Host smart-557b1482-7829-4422-9f1c-7253a7faf44c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437230655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1437230655
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1714224155
Short name T329
Test name
Test status
Simulation time 384694844 ps
CPU time 2.07 seconds
Started Mar 12 12:44:32 PM PDT 24
Finished Mar 12 12:44:35 PM PDT 24
Peak memory 200272 kb
Host smart-b62ae999-a88d-4c40-8b53-f7f4cecb48dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714224155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1714224155
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2641552397
Short name T290
Test name
Test status
Simulation time 72201015 ps
CPU time 0.76 seconds
Started Mar 12 12:44:34 PM PDT 24
Finished Mar 12 12:44:35 PM PDT 24
Peak memory 200380 kb
Host smart-f82155e2-1f3c-4b61-bf14-cd271f23b736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641552397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2641552397
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3667131901
Short name T500
Test name
Test status
Simulation time 87862422 ps
CPU time 0.79 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 200256 kb
Host smart-d24a82d6-de71-4933-80a0-fefdcbe58796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667131901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3667131901
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3698379238
Short name T454
Test name
Test status
Simulation time 1234414471 ps
CPU time 5.38 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 221784 kb
Host smart-908eed06-5cbc-4d89-936b-3dc91d3f6efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698379238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3698379238
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2238613188
Short name T451
Test name
Test status
Simulation time 244064908 ps
CPU time 1.13 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:36 PM PDT 24
Peak memory 217140 kb
Host smart-0331f8d9-4623-4bfe-b97d-f2b0dfcfb4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238613188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2238613188
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3860255994
Short name T200
Test name
Test status
Simulation time 102415616 ps
CPU time 0.76 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:37 PM PDT 24
Peak memory 200064 kb
Host smart-bd959e77-c61e-4146-ad9e-4d6549920032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860255994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3860255994
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.640574056
Short name T477
Test name
Test status
Simulation time 2113667488 ps
CPU time 7.99 seconds
Started Mar 12 12:44:34 PM PDT 24
Finished Mar 12 12:44:42 PM PDT 24
Peak memory 200604 kb
Host smart-43950251-2428-44bd-9e34-81a9b1cfd3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640574056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.640574056
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1993802989
Short name T159
Test name
Test status
Simulation time 106495209 ps
CPU time 1 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 200404 kb
Host smart-ee33b824-910e-4910-8c8e-5441aa571221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993802989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1993802989
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.773854733
Short name T392
Test name
Test status
Simulation time 120574298 ps
CPU time 1.16 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:37 PM PDT 24
Peak memory 200424 kb
Host smart-65348c65-8590-463d-abab-2acd56cd331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773854733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.773854733
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3838271120
Short name T103
Test name
Test status
Simulation time 9627186892 ps
CPU time 30.21 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:45:07 PM PDT 24
Peak memory 200616 kb
Host smart-a4d50385-e402-4c44-a806-b2e3dc34f51d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838271120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3838271120
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.666197984
Short name T506
Test name
Test status
Simulation time 329078411 ps
CPU time 2.26 seconds
Started Mar 12 12:44:38 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 200200 kb
Host smart-537057c0-dfc3-494d-86c6-c8f00966d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666197984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.666197984
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2064068803
Short name T158
Test name
Test status
Simulation time 74564381 ps
CPU time 0.74 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:35 PM PDT 24
Peak memory 200216 kb
Host smart-0f6c5631-e26b-41d3-8a4f-2b185323419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064068803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2064068803
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1345051988
Short name T216
Test name
Test status
Simulation time 83776400 ps
CPU time 0.79 seconds
Started Mar 12 12:44:39 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 200240 kb
Host smart-1df9a8b6-4e8d-4115-986c-7831a1d04624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345051988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1345051988
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1130242463
Short name T236
Test name
Test status
Simulation time 2358512423 ps
CPU time 7.88 seconds
Started Mar 12 12:44:38 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 218436 kb
Host smart-da19a6be-829a-4001-98a4-7777a2c5ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130242463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1130242463
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1428305444
Short name T23
Test name
Test status
Simulation time 243565126 ps
CPU time 1.05 seconds
Started Mar 12 12:44:37 PM PDT 24
Finished Mar 12 12:44:39 PM PDT 24
Peak memory 217232 kb
Host smart-a861e5b6-9486-40a2-bdce-a3681a356c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428305444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1428305444
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2314138313
Short name T379
Test name
Test status
Simulation time 197941201 ps
CPU time 0.87 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:37 PM PDT 24
Peak memory 200196 kb
Host smart-9ed24e4e-59a8-4b79-b298-49a9649f22b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314138313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2314138313
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2149515568
Short name T496
Test name
Test status
Simulation time 1743211718 ps
CPU time 7.27 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:44 PM PDT 24
Peak memory 200540 kb
Host smart-4789be0e-3e35-4a92-ac76-626a0a3cea3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149515568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2149515568
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1264081116
Short name T269
Test name
Test status
Simulation time 158857961 ps
CPU time 1.09 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:37 PM PDT 24
Peak memory 200364 kb
Host smart-299f38cf-4da7-4a4d-aa2f-7f0d38118b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264081116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1264081116
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3329467687
Short name T260
Test name
Test status
Simulation time 233239307 ps
CPU time 1.53 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 200432 kb
Host smart-2567644b-d95d-4d6c-a2cf-9b6fe6909c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329467687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3329467687
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2264391040
Short name T464
Test name
Test status
Simulation time 10409238506 ps
CPU time 37.61 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:45:13 PM PDT 24
Peak memory 200652 kb
Host smart-38da48b3-e118-42c9-93ac-f4180c7fc853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264391040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2264391040
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3791569661
Short name T266
Test name
Test status
Simulation time 325954962 ps
CPU time 2.11 seconds
Started Mar 12 12:44:37 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 200280 kb
Host smart-92036b45-b5ea-4d38-8dfa-b110d1644d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791569661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3791569661
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2087280331
Short name T333
Test name
Test status
Simulation time 87775289 ps
CPU time 0.84 seconds
Started Mar 12 12:44:40 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 200364 kb
Host smart-9a21d979-f0c5-42ae-84ae-480b3abfa6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087280331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2087280331
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2477212589
Short name T218
Test name
Test status
Simulation time 78285587 ps
CPU time 0.78 seconds
Started Mar 12 12:44:38 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 200196 kb
Host smart-4c2d5317-5d7e-4aea-9eac-1afaf66167a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477212589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2477212589
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.118589067
Short name T423
Test name
Test status
Simulation time 1228166732 ps
CPU time 5.32 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:42 PM PDT 24
Peak memory 220652 kb
Host smart-755a2334-6421-4dc3-a20f-7c33505dec7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118589067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.118589067
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1522274757
Short name T473
Test name
Test status
Simulation time 244617213 ps
CPU time 1.1 seconds
Started Mar 12 12:44:39 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 217156 kb
Host smart-e243728e-0ffd-4c56-aa6d-c4b1903bfa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522274757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1522274757
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2257725763
Short name T396
Test name
Test status
Simulation time 149650995 ps
CPU time 0.85 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 200180 kb
Host smart-d1f7f611-d7fb-44ff-8c0c-b768d0a86658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257725763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2257725763
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.589205133
Short name T35
Test name
Test status
Simulation time 1437588343 ps
CPU time 5.67 seconds
Started Mar 12 12:44:37 PM PDT 24
Finished Mar 12 12:44:43 PM PDT 24
Peak memory 200564 kb
Host smart-652535b5-c643-47c1-8976-3dc97b216b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589205133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.589205133
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2825675923
Short name T282
Test name
Test status
Simulation time 175358298 ps
CPU time 1.2 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 200380 kb
Host smart-51ac20d8-8142-4b25-a8cb-4667d19c4bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825675923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2825675923
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.475920083
Short name T276
Test name
Test status
Simulation time 200525842 ps
CPU time 1.42 seconds
Started Mar 12 12:44:38 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 200512 kb
Host smart-1808ee58-7014-4fa7-b9d1-cedf2563087f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475920083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.475920083
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3853482001
Short name T10
Test name
Test status
Simulation time 5684403676 ps
CPU time 20.84 seconds
Started Mar 12 12:44:39 PM PDT 24
Finished Mar 12 12:45:01 PM PDT 24
Peak memory 200648 kb
Host smart-15852ee9-315f-4b3a-a8c0-01c917975bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853482001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3853482001
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.422401708
Short name T122
Test name
Test status
Simulation time 437323432 ps
CPU time 2.37 seconds
Started Mar 12 12:44:38 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 200356 kb
Host smart-17c6c08e-629a-4608-8b46-cffa3c9757d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422401708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.422401708
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2389822332
Short name T279
Test name
Test status
Simulation time 90773602 ps
CPU time 0.93 seconds
Started Mar 12 12:44:37 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 200304 kb
Host smart-26c392d2-a531-48d0-9537-0b0d715dabf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389822332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2389822332
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.439934529
Short name T222
Test name
Test status
Simulation time 66081819 ps
CPU time 0.75 seconds
Started Mar 12 12:44:35 PM PDT 24
Finished Mar 12 12:44:36 PM PDT 24
Peak memory 200232 kb
Host smart-de2d5f2d-f01c-452c-9611-fed4bfceb655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439934529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.439934529
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1609825900
Short name T157
Test name
Test status
Simulation time 244041521 ps
CPU time 1.13 seconds
Started Mar 12 12:44:37 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 217220 kb
Host smart-d09827fe-6783-4b16-9217-941c05d5818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609825900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1609825900
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2501089342
Short name T487
Test name
Test status
Simulation time 136749133 ps
CPU time 0.85 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 200208 kb
Host smart-d4fadc1e-efcb-4630-9d48-84db71d46cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501089342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2501089342
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1986058522
Short name T326
Test name
Test status
Simulation time 2257765065 ps
CPU time 8.68 seconds
Started Mar 12 12:44:40 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200640 kb
Host smart-70e69620-afa9-4a6d-97d7-bd095c06dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986058522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1986058522
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2520335997
Short name T361
Test name
Test status
Simulation time 100748065 ps
CPU time 0.97 seconds
Started Mar 12 12:44:42 PM PDT 24
Finished Mar 12 12:44:44 PM PDT 24
Peak memory 200324 kb
Host smart-18a60813-adb5-48f1-b54d-30d3218efb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520335997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2520335997
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1272519327
Short name T220
Test name
Test status
Simulation time 114691122 ps
CPU time 1.17 seconds
Started Mar 12 12:44:38 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 200464 kb
Host smart-a52b248b-98e0-4e86-8825-b2187939e9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272519327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1272519327
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.809425410
Short name T434
Test name
Test status
Simulation time 8787967765 ps
CPU time 37.54 seconds
Started Mar 12 12:44:40 PM PDT 24
Finished Mar 12 12:45:18 PM PDT 24
Peak memory 208844 kb
Host smart-712485d5-c9ac-4dc5-9cfe-bcb5a24cf5e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809425410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.809425410
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2941370336
Short name T147
Test name
Test status
Simulation time 135734263 ps
CPU time 1.61 seconds
Started Mar 12 12:44:33 PM PDT 24
Finished Mar 12 12:44:36 PM PDT 24
Peak memory 208480 kb
Host smart-b6fbb1e5-b4eb-4175-aa41-631cbb90a391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941370336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2941370336
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2917786518
Short name T135
Test name
Test status
Simulation time 197362752 ps
CPU time 1.23 seconds
Started Mar 12 12:44:38 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 200340 kb
Host smart-dc961809-da69-4b4d-99b1-7e7825a9aaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917786518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2917786518
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3960493278
Short name T433
Test name
Test status
Simulation time 75457978 ps
CPU time 0.8 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:45 PM PDT 24
Peak memory 200228 kb
Host smart-83a37e69-9079-49cd-a30f-cf071751a46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960493278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3960493278
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2761645953
Short name T49
Test name
Test status
Simulation time 1222381236 ps
CPU time 5.67 seconds
Started Mar 12 12:44:39 PM PDT 24
Finished Mar 12 12:44:46 PM PDT 24
Peak memory 216864 kb
Host smart-49dd286e-6e6d-4459-abd8-396e19cfac31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761645953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2761645953
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3388068351
Short name T420
Test name
Test status
Simulation time 244123106 ps
CPU time 1.11 seconds
Started Mar 12 12:44:42 PM PDT 24
Finished Mar 12 12:44:44 PM PDT 24
Peak memory 217204 kb
Host smart-dc3e2dd2-1f36-436a-a120-cde81ce1f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388068351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3388068351
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2496139201
Short name T20
Test name
Test status
Simulation time 227584028 ps
CPU time 0.92 seconds
Started Mar 12 12:44:40 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 200184 kb
Host smart-bb568c8a-838f-49d3-b692-e04d6b4288b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496139201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2496139201
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.141298581
Short name T45
Test name
Test status
Simulation time 1022916835 ps
CPU time 5.25 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200520 kb
Host smart-f588854e-ef43-4b81-965f-1ea577d46f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141298581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.141298581
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.245305197
Short name T223
Test name
Test status
Simulation time 103243178 ps
CPU time 1.05 seconds
Started Mar 12 12:44:39 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 200404 kb
Host smart-573e9d52-da62-4e48-bc78-8e9b6653d5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245305197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.245305197
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3213838042
Short name T192
Test name
Test status
Simulation time 254988512 ps
CPU time 1.47 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:45 PM PDT 24
Peak memory 200412 kb
Host smart-3add306e-8af8-4d92-8644-068a7113f6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213838042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3213838042
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2732792333
Short name T441
Test name
Test status
Simulation time 129907123 ps
CPU time 1.52 seconds
Started Mar 12 12:44:37 PM PDT 24
Finished Mar 12 12:44:39 PM PDT 24
Peak memory 208456 kb
Host smart-a35e9d55-3235-4fd4-be66-8881c9dacdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732792333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2732792333
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2604724574
Short name T493
Test name
Test status
Simulation time 110287979 ps
CPU time 0.94 seconds
Started Mar 12 12:44:36 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 200368 kb
Host smart-598282d4-95b2-4ef2-9b9d-27d1a5f1429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604724574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2604724574
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3457955425
Short name T268
Test name
Test status
Simulation time 86194761 ps
CPU time 0.77 seconds
Started Mar 12 12:43:48 PM PDT 24
Finished Mar 12 12:43:49 PM PDT 24
Peak memory 200140 kb
Host smart-ef9ffc15-0509-47b0-b610-5e933386bff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457955425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3457955425
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1579192804
Short name T46
Test name
Test status
Simulation time 1229205205 ps
CPU time 5.47 seconds
Started Mar 12 12:43:36 PM PDT 24
Finished Mar 12 12:43:42 PM PDT 24
Peak memory 221708 kb
Host smart-cec7077d-2253-4141-890a-d3125f6845dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579192804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1579192804
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1820623570
Short name T356
Test name
Test status
Simulation time 243708855 ps
CPU time 1.15 seconds
Started Mar 12 12:43:38 PM PDT 24
Finished Mar 12 12:43:40 PM PDT 24
Peak memory 217096 kb
Host smart-23cf6012-e887-4816-afdc-07b68ea793ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820623570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1820623570
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2735487022
Short name T543
Test name
Test status
Simulation time 129415999 ps
CPU time 0.84 seconds
Started Mar 12 12:43:37 PM PDT 24
Finished Mar 12 12:43:38 PM PDT 24
Peak memory 200104 kb
Host smart-c76f8ed1-0fba-481f-93a6-7b820fe9e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735487022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2735487022
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2837506543
Short name T102
Test name
Test status
Simulation time 1085453690 ps
CPU time 4.97 seconds
Started Mar 12 12:43:38 PM PDT 24
Finished Mar 12 12:43:43 PM PDT 24
Peak memory 200576 kb
Host smart-41867536-cb82-4450-81a9-084fb9958e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837506543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2837506543
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2428784952
Short name T62
Test name
Test status
Simulation time 16565124353 ps
CPU time 26.4 seconds
Started Mar 12 12:43:38 PM PDT 24
Finished Mar 12 12:44:04 PM PDT 24
Peak memory 217756 kb
Host smart-f51eb292-7533-46ac-b060-dffc3bf3ea1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428784952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2428784952
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2619371246
Short name T456
Test name
Test status
Simulation time 98483085 ps
CPU time 0.99 seconds
Started Mar 12 12:43:37 PM PDT 24
Finished Mar 12 12:43:38 PM PDT 24
Peak memory 200232 kb
Host smart-8441060b-ec76-438b-83b3-a4561d4b01da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619371246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2619371246
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4036848006
Short name T469
Test name
Test status
Simulation time 121860864 ps
CPU time 1.19 seconds
Started Mar 12 12:43:37 PM PDT 24
Finished Mar 12 12:43:38 PM PDT 24
Peak memory 200400 kb
Host smart-5539de16-cb4f-4239-a43c-d9331a04dccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036848006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4036848006
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3803008449
Short name T410
Test name
Test status
Simulation time 5249450504 ps
CPU time 22.01 seconds
Started Mar 12 12:43:37 PM PDT 24
Finished Mar 12 12:43:59 PM PDT 24
Peak memory 208756 kb
Host smart-b3a3bc13-2a07-4bbe-bb12-561f6e0f863b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803008449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3803008449
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1644645404
Short name T191
Test name
Test status
Simulation time 342111682 ps
CPU time 2.15 seconds
Started Mar 12 12:43:36 PM PDT 24
Finished Mar 12 12:43:38 PM PDT 24
Peak memory 208448 kb
Host smart-d31feb1c-9042-46a5-aa83-9e48f935049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644645404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1644645404
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1436032123
Short name T335
Test name
Test status
Simulation time 159371695 ps
CPU time 1.11 seconds
Started Mar 12 12:43:38 PM PDT 24
Finished Mar 12 12:43:39 PM PDT 24
Peak memory 200216 kb
Host smart-bcccdb48-e853-4c48-bc23-260cbd5ff1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436032123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1436032123
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.832066409
Short name T234
Test name
Test status
Simulation time 113156479 ps
CPU time 0.82 seconds
Started Mar 12 12:44:44 PM PDT 24
Finished Mar 12 12:44:46 PM PDT 24
Peak memory 200260 kb
Host smart-0df94598-450f-4035-b6c9-a1d51b4ace77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832066409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.832066409
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.886384870
Short name T28
Test name
Test status
Simulation time 2160374091 ps
CPU time 8.16 seconds
Started Mar 12 12:44:41 PM PDT 24
Finished Mar 12 12:44:50 PM PDT 24
Peak memory 218272 kb
Host smart-573d04c7-29b7-4605-8e16-d570eb906cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886384870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.886384870
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1916150307
Short name T281
Test name
Test status
Simulation time 244538404 ps
CPU time 1.18 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:46 PM PDT 24
Peak memory 217128 kb
Host smart-11cbba54-e079-4d74-b421-522d5844f0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916150307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1916150307
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3665601818
Short name T401
Test name
Test status
Simulation time 117774725 ps
CPU time 0.77 seconds
Started Mar 12 12:44:38 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 200028 kb
Host smart-a05e2f1a-d66d-4be7-a69c-70e137bd76b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665601818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3665601818
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2646234559
Short name T512
Test name
Test status
Simulation time 948494824 ps
CPU time 4.03 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:48 PM PDT 24
Peak memory 200560 kb
Host smart-f1d19884-c37d-4b02-88e3-496495738d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646234559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2646234559
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.721531602
Short name T352
Test name
Test status
Simulation time 151491314 ps
CPU time 1.15 seconds
Started Mar 12 12:44:44 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 200364 kb
Host smart-34bf8e0f-55c4-4dae-88ed-610772c95568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721531602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.721531602
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.58416037
Short name T7
Test name
Test status
Simulation time 188620971 ps
CPU time 1.51 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:45 PM PDT 24
Peak memory 200460 kb
Host smart-1d2cd5aa-2df9-48b7-80ea-68ff5a3490ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58416037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.58416037
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3395905861
Short name T466
Test name
Test status
Simulation time 4252354118 ps
CPU time 14.32 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:45:00 PM PDT 24
Peak memory 208832 kb
Host smart-109cffea-d8ca-456b-b619-3af3e140b3ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395905861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3395905861
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4281123745
Short name T171
Test name
Test status
Simulation time 284858982 ps
CPU time 1.95 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 200260 kb
Host smart-a7f39e58-7576-4611-b139-96b8faa39681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281123745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4281123745
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1618729368
Short name T341
Test name
Test status
Simulation time 141276202 ps
CPU time 1.17 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:45 PM PDT 24
Peak memory 200452 kb
Host smart-b6e58a4f-5aa4-4b7c-b337-2613fb956fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618729368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1618729368
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1551910583
Short name T475
Test name
Test status
Simulation time 63950098 ps
CPU time 0.78 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 200220 kb
Host smart-c6d2a962-1461-4926-ad7b-602350bc4be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551910583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1551910583
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3070655258
Short name T288
Test name
Test status
Simulation time 1239534665 ps
CPU time 6 seconds
Started Mar 12 12:44:46 PM PDT 24
Finished Mar 12 12:44:53 PM PDT 24
Peak memory 217604 kb
Host smart-492939e2-5129-4439-b7a3-9c5a3bf1cb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070655258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3070655258
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1642972829
Short name T40
Test name
Test status
Simulation time 245245018 ps
CPU time 1.16 seconds
Started Mar 12 12:44:41 PM PDT 24
Finished Mar 12 12:44:43 PM PDT 24
Peak memory 217176 kb
Host smart-eb48250d-79fd-4592-9774-4791ec1e6c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642972829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1642972829
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.3698044151
Short name T521
Test name
Test status
Simulation time 165111888 ps
CPU time 0.86 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:46 PM PDT 24
Peak memory 200180 kb
Host smart-69d52bda-d924-4016-8896-e6aaacd9cda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698044151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3698044151
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1236799725
Short name T67
Test name
Test status
Simulation time 1791672752 ps
CPU time 6.09 seconds
Started Mar 12 12:44:49 PM PDT 24
Finished Mar 12 12:44:56 PM PDT 24
Peak memory 200512 kb
Host smart-a45d2a69-36fa-4a37-95ea-b95bccfc73dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236799725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1236799725
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2313383986
Short name T217
Test name
Test status
Simulation time 148237856 ps
CPU time 1.1 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200376 kb
Host smart-090a872c-0b58-40d9-93bb-61cb43a060a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313383986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2313383986
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2503920744
Short name T201
Test name
Test status
Simulation time 203195026 ps
CPU time 1.35 seconds
Started Mar 12 12:44:46 PM PDT 24
Finished Mar 12 12:44:48 PM PDT 24
Peak memory 200416 kb
Host smart-5d59871b-9051-49f1-be95-ed8728711f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503920744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2503920744
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1859963332
Short name T287
Test name
Test status
Simulation time 4364193891 ps
CPU time 16.16 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:45:02 PM PDT 24
Peak memory 208820 kb
Host smart-2efa26e9-8bdb-4f2c-bb63-d37ba27429a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859963332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1859963332
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3842878922
Short name T375
Test name
Test status
Simulation time 295957223 ps
CPU time 2.04 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:46 PM PDT 24
Peak memory 208508 kb
Host smart-0fd320b6-0591-4ea5-b94d-acca4bfdd418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842878922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3842878922
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.967703296
Short name T314
Test name
Test status
Simulation time 174028655 ps
CPU time 1.34 seconds
Started Mar 12 12:44:53 PM PDT 24
Finished Mar 12 12:44:55 PM PDT 24
Peak memory 200528 kb
Host smart-20322ee4-a0da-4d8a-8796-cd950131da8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967703296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.967703296
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2570525880
Short name T370
Test name
Test status
Simulation time 89653637 ps
CPU time 0.79 seconds
Started Mar 12 12:44:48 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200232 kb
Host smart-a204a43f-64ed-40e3-8f23-684e4f8a50e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570525880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2570525880
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3499975050
Short name T48
Test name
Test status
Simulation time 1230880023 ps
CPU time 5.73 seconds
Started Mar 12 12:44:46 PM PDT 24
Finished Mar 12 12:44:53 PM PDT 24
Peak memory 217164 kb
Host smart-22b84df4-0615-4787-b4eb-3e3297b2c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499975050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3499975050
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.270844515
Short name T219
Test name
Test status
Simulation time 244695993 ps
CPU time 1.07 seconds
Started Mar 12 12:44:50 PM PDT 24
Finished Mar 12 12:44:51 PM PDT 24
Peak memory 217172 kb
Host smart-09ab2f00-5bbb-4d45-8164-b420fab6653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270844515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.270844515
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3560941422
Short name T14
Test name
Test status
Simulation time 156105774 ps
CPU time 0.83 seconds
Started Mar 12 12:44:44 PM PDT 24
Finished Mar 12 12:44:46 PM PDT 24
Peak memory 200156 kb
Host smart-087286d6-9057-4927-b23d-454c439c15e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560941422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3560941422
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3322747653
Short name T369
Test name
Test status
Simulation time 1727842467 ps
CPU time 5.91 seconds
Started Mar 12 12:44:46 PM PDT 24
Finished Mar 12 12:44:52 PM PDT 24
Peak memory 200504 kb
Host smart-c60aadaa-211c-4997-990a-7818b0d954ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322747653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3322747653
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.364357540
Short name T398
Test name
Test status
Simulation time 185363567 ps
CPU time 1.23 seconds
Started Mar 12 12:44:42 PM PDT 24
Finished Mar 12 12:44:44 PM PDT 24
Peak memory 200416 kb
Host smart-933feb88-0cd8-453c-bae5-30c5483d56f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364357540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.364357540
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.436681055
Short name T148
Test name
Test status
Simulation time 112288753 ps
CPU time 1.14 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 200500 kb
Host smart-4950ddd7-d737-4204-81c1-774f828fe9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436681055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.436681055
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2700455933
Short name T94
Test name
Test status
Simulation time 2142378613 ps
CPU time 10.46 seconds
Started Mar 12 12:44:44 PM PDT 24
Finished Mar 12 12:44:56 PM PDT 24
Peak memory 200496 kb
Host smart-be56698e-1576-4c97-89e9-b8e15100ccda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700455933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2700455933
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.318586813
Short name T195
Test name
Test status
Simulation time 473415937 ps
CPU time 2.75 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:48 PM PDT 24
Peak memory 200332 kb
Host smart-012abfc6-03e9-4b2e-ae6d-2de941932213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318586813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.318586813
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2921591138
Short name T124
Test name
Test status
Simulation time 123740994 ps
CPU time 0.93 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 200184 kb
Host smart-0cc30bc5-0d93-4aba-b79a-209f58ff74d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921591138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2921591138
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2599544525
Short name T316
Test name
Test status
Simulation time 58896561 ps
CPU time 0.76 seconds
Started Mar 12 12:44:49 PM PDT 24
Finished Mar 12 12:44:50 PM PDT 24
Peak memory 200228 kb
Host smart-85f495b2-0048-4a66-b60f-7f5fb0dfb15f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599544525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2599544525
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.149937497
Short name T497
Test name
Test status
Simulation time 2184920406 ps
CPU time 7.93 seconds
Started Mar 12 12:44:44 PM PDT 24
Finished Mar 12 12:44:53 PM PDT 24
Peak memory 217780 kb
Host smart-a75b9ac1-7cfc-4b6c-8720-f606dda962ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149937497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.149937497
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.638668579
Short name T69
Test name
Test status
Simulation time 244361784 ps
CPU time 1.2 seconds
Started Mar 12 12:44:49 PM PDT 24
Finished Mar 12 12:44:51 PM PDT 24
Peak memory 217172 kb
Host smart-0b5905d0-7a4b-4097-a22a-6d17c59d5ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638668579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.638668579
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.599443979
Short name T536
Test name
Test status
Simulation time 187570188 ps
CPU time 0.92 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:45 PM PDT 24
Peak memory 200140 kb
Host smart-92abb1be-8277-4b61-b371-2204e52bcb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599443979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.599443979
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2413723474
Short name T249
Test name
Test status
Simulation time 719373032 ps
CPU time 3.76 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:44:50 PM PDT 24
Peak memory 200548 kb
Host smart-b651a949-ab08-4d65-b3ee-aa9612163e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413723474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2413723474
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2159573007
Short name T254
Test name
Test status
Simulation time 110160122 ps
CPU time 0.95 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 200396 kb
Host smart-e99bd687-e72e-40e9-b25e-42368df8abca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159573007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2159573007
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2706523214
Short name T471
Test name
Test status
Simulation time 229367939 ps
CPU time 1.37 seconds
Started Mar 12 12:44:43 PM PDT 24
Finished Mar 12 12:44:46 PM PDT 24
Peak memory 200460 kb
Host smart-4dc3bfb3-949a-43be-8cb1-323c3be98010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706523214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2706523214
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3346390186
Short name T116
Test name
Test status
Simulation time 8556730268 ps
CPU time 28.02 seconds
Started Mar 12 12:44:51 PM PDT 24
Finished Mar 12 12:45:19 PM PDT 24
Peak memory 200612 kb
Host smart-568a65aa-6436-472e-af61-8d65cc7c50f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346390186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3346390186
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.514421158
Short name T462
Test name
Test status
Simulation time 260647897 ps
CPU time 1.91 seconds
Started Mar 12 12:44:50 PM PDT 24
Finished Mar 12 12:44:52 PM PDT 24
Peak memory 200216 kb
Host smart-b85bea99-a3a6-4ae6-b3f0-9226fbc4037f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514421158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.514421158
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1554040710
Short name T286
Test name
Test status
Simulation time 235656256 ps
CPU time 1.3 seconds
Started Mar 12 12:44:50 PM PDT 24
Finished Mar 12 12:44:52 PM PDT 24
Peak memory 200268 kb
Host smart-afcb5c03-a252-4750-b194-b9323ba1a361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554040710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1554040710
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3665242126
Short name T145
Test name
Test status
Simulation time 65702232 ps
CPU time 0.73 seconds
Started Mar 12 12:44:48 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200228 kb
Host smart-ddfbb8f3-3d17-49f3-b20d-c975ae86589f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665242126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3665242126
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3629296097
Short name T322
Test name
Test status
Simulation time 1221750517 ps
CPU time 5.34 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:53 PM PDT 24
Peak memory 216536 kb
Host smart-9e9d9a06-6b93-447f-beb6-b81071b756e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629296097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3629296097
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.979078825
Short name T238
Test name
Test status
Simulation time 244161956 ps
CPU time 1.04 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 217164 kb
Host smart-26c21834-dee1-487e-a5f9-c603f61cb5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979078825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.979078825
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.4150200909
Short name T211
Test name
Test status
Simulation time 98326082 ps
CPU time 0.77 seconds
Started Mar 12 12:44:48 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200212 kb
Host smart-7277fbba-0bfe-42a9-bc3e-dde796a2fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150200909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.4150200909
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2944533592
Short name T164
Test name
Test status
Simulation time 1284867223 ps
CPU time 5.27 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:53 PM PDT 24
Peak memory 200576 kb
Host smart-60da5519-012d-439b-8dde-a5e75c08b36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944533592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2944533592
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1329517753
Short name T250
Test name
Test status
Simulation time 105189618 ps
CPU time 1 seconds
Started Mar 12 12:44:50 PM PDT 24
Finished Mar 12 12:44:51 PM PDT 24
Peak memory 200364 kb
Host smart-b0b84c35-5ec1-4d1d-950d-0258fc5603d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329517753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1329517753
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2417377453
Short name T204
Test name
Test status
Simulation time 254569260 ps
CPU time 1.64 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200544 kb
Host smart-698ed270-be04-4376-96da-c69c8d2f30ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417377453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2417377453
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.238482317
Short name T215
Test name
Test status
Simulation time 2158962164 ps
CPU time 7.91 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:56 PM PDT 24
Peak memory 200568 kb
Host smart-28b35461-4e59-445b-8763-2fdd79e55b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238482317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.238482317
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3858430600
Short name T297
Test name
Test status
Simulation time 286074422 ps
CPU time 1.82 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:44:48 PM PDT 24
Peak memory 200332 kb
Host smart-6445f463-a653-40a8-b895-344870f6b31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858430600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3858430600
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2323940865
Short name T24
Test name
Test status
Simulation time 75575032 ps
CPU time 0.81 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200220 kb
Host smart-873a1304-6e11-4291-90da-f0d4a1953491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323940865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2323940865
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1320446966
Short name T275
Test name
Test status
Simulation time 2355498172 ps
CPU time 7.69 seconds
Started Mar 12 12:44:46 PM PDT 24
Finished Mar 12 12:44:54 PM PDT 24
Peak memory 221820 kb
Host smart-4ce59a56-126f-438a-8f8d-3a8f79b18bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320446966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1320446966
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1117696931
Short name T230
Test name
Test status
Simulation time 243907958 ps
CPU time 1.08 seconds
Started Mar 12 12:44:49 PM PDT 24
Finished Mar 12 12:44:50 PM PDT 24
Peak memory 217040 kb
Host smart-f4b8f94e-07c2-4f4f-af83-35baee643c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117696931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1117696931
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3303530628
Short name T327
Test name
Test status
Simulation time 120412378 ps
CPU time 0.75 seconds
Started Mar 12 12:44:48 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200168 kb
Host smart-b46a50bd-73f9-448b-b9b3-cbbfe775abd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303530628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3303530628
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1906917625
Short name T295
Test name
Test status
Simulation time 806654122 ps
CPU time 3.96 seconds
Started Mar 12 12:44:48 PM PDT 24
Finished Mar 12 12:44:52 PM PDT 24
Peak memory 200516 kb
Host smart-d5251aac-9769-4c35-98e5-f198618e499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906917625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1906917625
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2948549539
Short name T470
Test name
Test status
Simulation time 144450350 ps
CPU time 1.12 seconds
Started Mar 12 12:44:48 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200372 kb
Host smart-46010893-aca3-4602-b71e-cbf94d50dfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948549539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2948549539
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2701797111
Short name T272
Test name
Test status
Simulation time 254828519 ps
CPU time 1.53 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 200444 kb
Host smart-df74dc5f-4e46-41f5-840f-eebb1f05469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701797111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2701797111
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2633949620
Short name T190
Test name
Test status
Simulation time 3902523242 ps
CPU time 18.24 seconds
Started Mar 12 12:44:48 PM PDT 24
Finished Mar 12 12:45:07 PM PDT 24
Peak memory 200500 kb
Host smart-c1b1fe68-6097-4aec-97b0-46a71863b883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633949620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2633949620
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.327133216
Short name T408
Test name
Test status
Simulation time 119948595 ps
CPU time 1.53 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:50 PM PDT 24
Peak memory 208760 kb
Host smart-7f35e109-c9fc-438a-babc-857dc0ad52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327133216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.327133216
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2930898370
Short name T435
Test name
Test status
Simulation time 167748863 ps
CPU time 1.18 seconds
Started Mar 12 12:44:47 PM PDT 24
Finished Mar 12 12:44:49 PM PDT 24
Peak memory 200496 kb
Host smart-8949e66c-0bea-42df-919d-b64e6e372dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930898370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2930898370
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3044212582
Short name T421
Test name
Test status
Simulation time 55821502 ps
CPU time 0.68 seconds
Started Mar 12 12:44:56 PM PDT 24
Finished Mar 12 12:44:56 PM PDT 24
Peak memory 200236 kb
Host smart-64c15ffe-e43c-4867-a853-4dee2f293867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044212582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3044212582
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1463241001
Short name T459
Test name
Test status
Simulation time 1235031110 ps
CPU time 5.4 seconds
Started Mar 12 12:44:58 PM PDT 24
Finished Mar 12 12:45:04 PM PDT 24
Peak memory 217748 kb
Host smart-a2956a85-8aee-4eff-b158-a0fa07ee7c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463241001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1463241001
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.432049718
Short name T511
Test name
Test status
Simulation time 244122893 ps
CPU time 1.17 seconds
Started Mar 12 12:44:56 PM PDT 24
Finished Mar 12 12:44:57 PM PDT 24
Peak memory 217256 kb
Host smart-45332af2-ed85-4b6e-9e5f-735c49554497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432049718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.432049718
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.4233145220
Short name T378
Test name
Test status
Simulation time 129121139 ps
CPU time 0.85 seconds
Started Mar 12 12:44:49 PM PDT 24
Finished Mar 12 12:44:50 PM PDT 24
Peak memory 200128 kb
Host smart-c98bcb5a-eecb-4336-96c5-8be42d67b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233145220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.4233145220
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.857431090
Short name T105
Test name
Test status
Simulation time 778668524 ps
CPU time 3.96 seconds
Started Mar 12 12:44:49 PM PDT 24
Finished Mar 12 12:44:53 PM PDT 24
Peak memory 200388 kb
Host smart-6d1d1db7-ec5b-4d5d-bb72-3ea7037a2909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857431090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.857431090
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3701263646
Short name T359
Test name
Test status
Simulation time 147189356 ps
CPU time 1.15 seconds
Started Mar 12 12:44:54 PM PDT 24
Finished Mar 12 12:44:55 PM PDT 24
Peak memory 200304 kb
Host smart-b346dbdc-da24-4d34-9009-8a4c498ae349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701263646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3701263646
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1767249005
Short name T203
Test name
Test status
Simulation time 116317723 ps
CPU time 1.17 seconds
Started Mar 12 12:44:45 PM PDT 24
Finished Mar 12 12:44:47 PM PDT 24
Peak memory 200496 kb
Host smart-51e009e4-ac15-4705-b774-6afe011e5357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767249005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1767249005
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3741126816
Short name T115
Test name
Test status
Simulation time 2194836191 ps
CPU time 7.46 seconds
Started Mar 12 12:44:53 PM PDT 24
Finished Mar 12 12:45:01 PM PDT 24
Peak memory 200560 kb
Host smart-f01b8e78-4ab8-46eb-a18a-bcd56e2ab806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741126816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3741126816
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.527349062
Short name T188
Test name
Test status
Simulation time 542197155 ps
CPU time 2.74 seconds
Started Mar 12 12:44:54 PM PDT 24
Finished Mar 12 12:44:57 PM PDT 24
Peak memory 200312 kb
Host smart-88f75374-6df1-498c-ad9d-f5ea6ade9f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527349062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.527349062
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1892772651
Short name T193
Test name
Test status
Simulation time 211411109 ps
CPU time 1.3 seconds
Started Mar 12 12:44:49 PM PDT 24
Finished Mar 12 12:44:51 PM PDT 24
Peak memory 200328 kb
Host smart-72e9ff1d-c9dd-418d-8a9e-81bd9996af2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892772651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1892772651
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.106845371
Short name T245
Test name
Test status
Simulation time 60112112 ps
CPU time 0.73 seconds
Started Mar 12 12:44:53 PM PDT 24
Finished Mar 12 12:44:53 PM PDT 24
Peak memory 200176 kb
Host smart-2580d739-fb88-4dac-8057-c54d501a3f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106845371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.106845371
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3382524301
Short name T239
Test name
Test status
Simulation time 243535982 ps
CPU time 1.16 seconds
Started Mar 12 12:44:59 PM PDT 24
Finished Mar 12 12:45:00 PM PDT 24
Peak memory 217196 kb
Host smart-1a911d3f-597b-4aa8-8c30-e8eb4192b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382524301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3382524301
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.709436156
Short name T198
Test name
Test status
Simulation time 127065753 ps
CPU time 0.88 seconds
Started Mar 12 12:44:59 PM PDT 24
Finished Mar 12 12:45:00 PM PDT 24
Peak memory 200116 kb
Host smart-7d7f7af1-53d7-4644-845e-cdfa3b60b3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709436156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.709436156
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.806620350
Short name T163
Test name
Test status
Simulation time 1455246271 ps
CPU time 6.04 seconds
Started Mar 12 12:44:58 PM PDT 24
Finished Mar 12 12:45:04 PM PDT 24
Peak memory 200568 kb
Host smart-061b6aef-8b6c-4131-9490-3dffe74732e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806620350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.806620350
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3655399374
Short name T452
Test name
Test status
Simulation time 103956299 ps
CPU time 0.96 seconds
Started Mar 12 12:44:55 PM PDT 24
Finished Mar 12 12:44:56 PM PDT 24
Peak memory 200412 kb
Host smart-36bed1ca-ff2c-4bf5-9df9-5daf9db7d12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655399374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3655399374
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2467884475
Short name T38
Test name
Test status
Simulation time 112856393 ps
CPU time 1.15 seconds
Started Mar 12 12:45:08 PM PDT 24
Finished Mar 12 12:45:09 PM PDT 24
Peak memory 200432 kb
Host smart-231d3c5b-1504-4ec4-9a1c-00ba6670b1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467884475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2467884475
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.132125949
Short name T394
Test name
Test status
Simulation time 9534364562 ps
CPU time 36.97 seconds
Started Mar 12 12:44:58 PM PDT 24
Finished Mar 12 12:45:36 PM PDT 24
Peak memory 208816 kb
Host smart-acbf8043-ea1f-443c-a279-0cb9f198f56e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132125949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.132125949
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3546571584
Short name T121
Test name
Test status
Simulation time 493738199 ps
CPU time 2.69 seconds
Started Mar 12 12:44:56 PM PDT 24
Finished Mar 12 12:44:59 PM PDT 24
Peak memory 200316 kb
Host smart-523b90a5-899e-4480-b072-401b93832c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546571584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3546571584
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3869124740
Short name T472
Test name
Test status
Simulation time 148367835 ps
CPU time 1.06 seconds
Started Mar 12 12:44:54 PM PDT 24
Finished Mar 12 12:44:56 PM PDT 24
Peak memory 200400 kb
Host smart-548c176c-44e6-4bc5-b084-97f0c3408e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869124740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3869124740
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2076891419
Short name T184
Test name
Test status
Simulation time 67149194 ps
CPU time 0.73 seconds
Started Mar 12 12:44:57 PM PDT 24
Finished Mar 12 12:44:58 PM PDT 24
Peak memory 200248 kb
Host smart-8ee9aec4-3f15-481b-9f5a-8bd946270789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076891419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2076891419
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3663325998
Short name T33
Test name
Test status
Simulation time 2372348464 ps
CPU time 8.49 seconds
Started Mar 12 12:44:55 PM PDT 24
Finished Mar 12 12:45:04 PM PDT 24
Peak memory 221032 kb
Host smart-eb881d4f-6832-4573-a22e-daa4b0ccca92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663325998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3663325998
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1345899556
Short name T140
Test name
Test status
Simulation time 244315247 ps
CPU time 1.22 seconds
Started Mar 12 12:45:05 PM PDT 24
Finished Mar 12 12:45:07 PM PDT 24
Peak memory 217192 kb
Host smart-ba466901-c45b-4613-922e-bf88023af942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345899556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1345899556
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1311342511
Short name T318
Test name
Test status
Simulation time 233860659 ps
CPU time 0.94 seconds
Started Mar 12 12:44:56 PM PDT 24
Finished Mar 12 12:44:57 PM PDT 24
Peak memory 200168 kb
Host smart-0c909fb5-4588-49e5-9355-eeadbb10f0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311342511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1311342511
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2578240630
Short name T448
Test name
Test status
Simulation time 1658412411 ps
CPU time 6.13 seconds
Started Mar 12 12:44:58 PM PDT 24
Finished Mar 12 12:45:05 PM PDT 24
Peak memory 200548 kb
Host smart-ae692384-e1d5-47a7-b6bb-87a22069f9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578240630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2578240630
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1703881361
Short name T310
Test name
Test status
Simulation time 98909045 ps
CPU time 1 seconds
Started Mar 12 12:44:56 PM PDT 24
Finished Mar 12 12:44:58 PM PDT 24
Peak memory 200356 kb
Host smart-52f3c15a-4bc8-4948-9570-b4f110bb52e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703881361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1703881361
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4033398204
Short name T224
Test name
Test status
Simulation time 198914445 ps
CPU time 1.37 seconds
Started Mar 12 12:44:55 PM PDT 24
Finished Mar 12 12:44:57 PM PDT 24
Peak memory 200472 kb
Host smart-fb6774d9-e219-436d-bfae-2ce58e041d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033398204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4033398204
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3256112717
Short name T541
Test name
Test status
Simulation time 165151872 ps
CPU time 1.43 seconds
Started Mar 12 12:44:55 PM PDT 24
Finished Mar 12 12:44:57 PM PDT 24
Peak memory 200252 kb
Host smart-ce46cb22-d38a-4670-8ba7-c19534ba6ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256112717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3256112717
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1308994273
Short name T528
Test name
Test status
Simulation time 117328538 ps
CPU time 1.52 seconds
Started Mar 12 12:44:55 PM PDT 24
Finished Mar 12 12:44:57 PM PDT 24
Peak memory 200120 kb
Host smart-f15b9e0b-1ac7-4bcf-8d82-dae126d13179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308994273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1308994273
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1543047556
Short name T418
Test name
Test status
Simulation time 120105982 ps
CPU time 1.03 seconds
Started Mar 12 12:44:56 PM PDT 24
Finished Mar 12 12:44:57 PM PDT 24
Peak memory 200360 kb
Host smart-4586a4a9-91a8-45fd-b67d-c2d356533f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543047556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1543047556
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.611872484
Short name T415
Test name
Test status
Simulation time 67624616 ps
CPU time 0.81 seconds
Started Mar 12 12:44:58 PM PDT 24
Finished Mar 12 12:44:59 PM PDT 24
Peak memory 200224 kb
Host smart-b15003cf-9282-4890-be47-6cd581c7bfb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611872484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.611872484
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.423847111
Short name T505
Test name
Test status
Simulation time 1876014014 ps
CPU time 7.14 seconds
Started Mar 12 12:45:01 PM PDT 24
Finished Mar 12 12:45:08 PM PDT 24
Peak memory 216936 kb
Host smart-d2b5a7f9-bf4c-458c-815a-7536e5bd955b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423847111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.423847111
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1529969418
Short name T194
Test name
Test status
Simulation time 243992012 ps
CPU time 1.08 seconds
Started Mar 12 12:44:57 PM PDT 24
Finished Mar 12 12:44:58 PM PDT 24
Peak memory 217216 kb
Host smart-0b464541-9831-4abb-b47a-2ed57c315ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529969418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1529969418
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2885232786
Short name T489
Test name
Test status
Simulation time 88704793 ps
CPU time 0.74 seconds
Started Mar 12 12:44:55 PM PDT 24
Finished Mar 12 12:44:56 PM PDT 24
Peak memory 200196 kb
Host smart-d7226e33-2d96-46fb-a7cd-aaee216c0d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885232786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2885232786
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3260712608
Short name T174
Test name
Test status
Simulation time 1084115122 ps
CPU time 4.57 seconds
Started Mar 12 12:44:58 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 200528 kb
Host smart-b694f7ac-2fc7-4cc5-af1b-d7fabaea25a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260712608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3260712608
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.899042104
Short name T179
Test name
Test status
Simulation time 142326750 ps
CPU time 1.07 seconds
Started Mar 12 12:44:59 PM PDT 24
Finished Mar 12 12:45:01 PM PDT 24
Peak memory 200324 kb
Host smart-d430f5a9-9e00-410b-871e-7ca003706fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899042104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.899042104
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2478923091
Short name T146
Test name
Test status
Simulation time 120374031 ps
CPU time 1.19 seconds
Started Mar 12 12:44:59 PM PDT 24
Finished Mar 12 12:45:00 PM PDT 24
Peak memory 200424 kb
Host smart-13c9947f-4078-4f30-9aed-dafb95c52caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478923091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2478923091
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3763232475
Short name T277
Test name
Test status
Simulation time 6766001697 ps
CPU time 30.26 seconds
Started Mar 12 12:44:55 PM PDT 24
Finished Mar 12 12:45:26 PM PDT 24
Peak memory 200580 kb
Host smart-87677eef-8d23-452b-bece-38c46859c9cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763232475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3763232475
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1352825307
Short name T196
Test name
Test status
Simulation time 297027442 ps
CPU time 2.07 seconds
Started Mar 12 12:44:58 PM PDT 24
Finished Mar 12 12:45:01 PM PDT 24
Peak memory 208464 kb
Host smart-c9676d07-eeec-45ec-a0fb-7a4a97be48ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352825307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1352825307
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3389956248
Short name T12
Test name
Test status
Simulation time 130570707 ps
CPU time 0.96 seconds
Started Mar 12 12:44:59 PM PDT 24
Finished Mar 12 12:45:00 PM PDT 24
Peak memory 200344 kb
Host smart-aa382816-8a3e-4b18-b4e9-a5f85e9864a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389956248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3389956248
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3821672409
Short name T244
Test name
Test status
Simulation time 66319724 ps
CPU time 0.75 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:50 PM PDT 24
Peak memory 200212 kb
Host smart-912671d1-6412-4601-80a2-3fe9575287ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821672409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3821672409
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1639189387
Short name T406
Test name
Test status
Simulation time 1222123242 ps
CPU time 5.36 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:54 PM PDT 24
Peak memory 217600 kb
Host smart-630e33e9-fc54-400e-b145-218b10e84103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639189387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1639189387
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1351538069
Short name T438
Test name
Test status
Simulation time 245608822 ps
CPU time 1.11 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:50 PM PDT 24
Peak memory 217148 kb
Host smart-7b45c165-cbbe-460d-8a37-83f0272bbbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351538069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1351538069
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3364157477
Short name T399
Test name
Test status
Simulation time 205499788 ps
CPU time 0.92 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:51 PM PDT 24
Peak memory 200116 kb
Host smart-34c4252d-c04c-4475-a4c1-c796551ea520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364157477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3364157477
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3774841308
Short name T509
Test name
Test status
Simulation time 1763711182 ps
CPU time 6.1 seconds
Started Mar 12 12:43:47 PM PDT 24
Finished Mar 12 12:43:54 PM PDT 24
Peak memory 200568 kb
Host smart-e396a164-3757-4bb0-9a23-d558442859c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774841308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3774841308
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4043086230
Short name T65
Test name
Test status
Simulation time 16635579173 ps
CPU time 23.78 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:44:13 PM PDT 24
Peak memory 216992 kb
Host smart-21f3ea20-12e6-4694-9137-76f8f218fb31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043086230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4043086230
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1329669874
Short name T532
Test name
Test status
Simulation time 108569738 ps
CPU time 1 seconds
Started Mar 12 12:43:48 PM PDT 24
Finished Mar 12 12:43:49 PM PDT 24
Peak memory 200340 kb
Host smart-bc29c7da-d766-4f7d-9010-35c3c60c67bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329669874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1329669874
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.281189178
Short name T445
Test name
Test status
Simulation time 249875732 ps
CPU time 1.4 seconds
Started Mar 12 12:43:47 PM PDT 24
Finished Mar 12 12:43:49 PM PDT 24
Peak memory 200484 kb
Host smart-56e25dbd-e03e-4894-90ea-cf6e7512282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281189178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.281189178
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3920888043
Short name T101
Test name
Test status
Simulation time 5912153139 ps
CPU time 26.54 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:44:16 PM PDT 24
Peak memory 200568 kb
Host smart-9bf84062-a09d-4a36-8383-16286ea30e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920888043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3920888043
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2840155017
Short name T235
Test name
Test status
Simulation time 130785020 ps
CPU time 1.63 seconds
Started Mar 12 12:43:57 PM PDT 24
Finished Mar 12 12:43:59 PM PDT 24
Peak memory 208340 kb
Host smart-cbeb0580-3545-4954-b9d1-9f3768a45489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840155017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2840155017
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2077182237
Short name T312
Test name
Test status
Simulation time 209832682 ps
CPU time 1.27 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:51 PM PDT 24
Peak memory 200416 kb
Host smart-b4078ae9-b11e-4f82-9d91-ed81f1b0c9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077182237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2077182237
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1887358154
Short name T265
Test name
Test status
Simulation time 78243378 ps
CPU time 0.77 seconds
Started Mar 12 12:45:01 PM PDT 24
Finished Mar 12 12:45:02 PM PDT 24
Peak memory 200208 kb
Host smart-27404080-9f3d-4046-ba9e-5a61090fe19b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887358154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1887358154
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1594812937
Short name T30
Test name
Test status
Simulation time 1223754054 ps
CPU time 5.86 seconds
Started Mar 12 12:45:03 PM PDT 24
Finished Mar 12 12:45:09 PM PDT 24
Peak memory 221800 kb
Host smart-683c35b9-1dbc-4385-8be2-56b8c4150667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594812937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1594812937
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1767752410
Short name T289
Test name
Test status
Simulation time 244568156 ps
CPU time 0.99 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 217088 kb
Host smart-99acd3b2-adca-49dd-a7ec-b873d3dbd0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767752410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1767752410
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1537619149
Short name T214
Test name
Test status
Simulation time 151398018 ps
CPU time 0.86 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:14 PM PDT 24
Peak memory 200076 kb
Host smart-43915b72-b17b-443a-9db9-13e967edf2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537619149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1537619149
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.800239332
Short name T330
Test name
Test status
Simulation time 1467785359 ps
CPU time 5.66 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:08 PM PDT 24
Peak memory 200420 kb
Host smart-a474fe07-0d5c-4538-9190-138753fd7039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800239332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.800239332
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.182136494
Short name T162
Test name
Test status
Simulation time 172871655 ps
CPU time 1.28 seconds
Started Mar 12 12:45:03 PM PDT 24
Finished Mar 12 12:45:05 PM PDT 24
Peak memory 200372 kb
Host smart-0b222fc8-bb72-432b-ba30-36892ea547b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182136494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.182136494
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3421412398
Short name T138
Test name
Test status
Simulation time 128665396 ps
CPU time 1.17 seconds
Started Mar 12 12:44:54 PM PDT 24
Finished Mar 12 12:44:55 PM PDT 24
Peak memory 200356 kb
Host smart-403c966e-4416-49a6-99f7-16431eb985fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421412398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3421412398
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.4024447059
Short name T305
Test name
Test status
Simulation time 6743159523 ps
CPU time 21.75 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:35 PM PDT 24
Peak memory 200492 kb
Host smart-b20b9010-1c8c-43b9-9fe2-e28913ed29cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024447059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4024447059
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.784148678
Short name T446
Test name
Test status
Simulation time 560620932 ps
CPU time 2.9 seconds
Started Mar 12 12:45:09 PM PDT 24
Finished Mar 12 12:45:12 PM PDT 24
Peak memory 200184 kb
Host smart-ce56ef7c-67f5-493b-81bb-20c9977b27c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784148678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.784148678
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.51912108
Short name T395
Test name
Test status
Simulation time 291654156 ps
CPU time 1.59 seconds
Started Mar 12 12:45:03 PM PDT 24
Finished Mar 12 12:45:05 PM PDT 24
Peak memory 200312 kb
Host smart-97f79163-73d4-4a77-93d9-0a24cc2fce90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51912108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.51912108
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1026238622
Short name T170
Test name
Test status
Simulation time 57785772 ps
CPU time 0.71 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 200136 kb
Host smart-5b28c43a-d43a-4f5f-b47a-2ef530527afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026238622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1026238622
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3431741397
Short name T44
Test name
Test status
Simulation time 1886037503 ps
CPU time 7.4 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:09 PM PDT 24
Peak memory 218136 kb
Host smart-6b4e781f-66d8-4554-8775-0caa1893d11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431741397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3431741397
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.740214388
Short name T151
Test name
Test status
Simulation time 244500975 ps
CPU time 1.25 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 217140 kb
Host smart-e90242b5-6653-43dd-95d4-1b5c79e1d24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740214388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.740214388
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3301061309
Short name T13
Test name
Test status
Simulation time 181916617 ps
CPU time 0.82 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 200112 kb
Host smart-3cd50bcb-d8d8-4fc1-a002-9d58c843aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301061309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3301061309
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2431184101
Short name T99
Test name
Test status
Simulation time 706910540 ps
CPU time 3.47 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:16 PM PDT 24
Peak memory 200428 kb
Host smart-f8402898-ca2b-4252-8cab-31119d9465dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431184101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2431184101
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4024194571
Short name T208
Test name
Test status
Simulation time 113248593 ps
CPU time 1.01 seconds
Started Mar 12 12:45:03 PM PDT 24
Finished Mar 12 12:45:05 PM PDT 24
Peak memory 200416 kb
Host smart-835e52e7-bc2b-43bc-9055-fc72fa60a5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024194571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4024194571
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2605526830
Short name T364
Test name
Test status
Simulation time 230360323 ps
CPU time 1.41 seconds
Started Mar 12 12:45:03 PM PDT 24
Finished Mar 12 12:45:04 PM PDT 24
Peak memory 200308 kb
Host smart-aefbbb15-47d0-41c9-a53f-6154dcc838b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605526830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2605526830
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.510154828
Short name T323
Test name
Test status
Simulation time 6867205380 ps
CPU time 22.73 seconds
Started Mar 12 12:45:04 PM PDT 24
Finished Mar 12 12:45:26 PM PDT 24
Peak memory 200676 kb
Host smart-c0cb5c4b-6979-4a96-a7b6-e0f4ae90a6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510154828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.510154828
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.907997661
Short name T530
Test name
Test status
Simulation time 426902936 ps
CPU time 2.33 seconds
Started Mar 12 12:45:03 PM PDT 24
Finished Mar 12 12:45:06 PM PDT 24
Peak memory 208492 kb
Host smart-dfc991c1-88e1-4aed-9449-bde8deb2fc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907997661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.907997661
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2177230764
Short name T251
Test name
Test status
Simulation time 146567012 ps
CPU time 1.17 seconds
Started Mar 12 12:45:11 PM PDT 24
Finished Mar 12 12:45:14 PM PDT 24
Peak memory 200248 kb
Host smart-c81cfc41-a017-4179-88a7-c1ced6307aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177230764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2177230764
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2053471335
Short name T51
Test name
Test status
Simulation time 60492784 ps
CPU time 0.76 seconds
Started Mar 12 12:45:03 PM PDT 24
Finished Mar 12 12:45:04 PM PDT 24
Peak memory 200116 kb
Host smart-fed58871-1b1e-4a11-b190-5a9a642193dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053471335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2053471335
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2944680918
Short name T498
Test name
Test status
Simulation time 1886666673 ps
CPU time 6.72 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:20 PM PDT 24
Peak memory 218128 kb
Host smart-1d8e88e1-5a67-4301-8b23-8f1dbb1bbeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944680918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2944680918
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3624917846
Short name T351
Test name
Test status
Simulation time 244610149 ps
CPU time 1.12 seconds
Started Mar 12 12:45:06 PM PDT 24
Finished Mar 12 12:45:07 PM PDT 24
Peak memory 217088 kb
Host smart-52f8499e-d274-40e8-ae2b-b3f2d53d4778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624917846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3624917846
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3010951423
Short name T325
Test name
Test status
Simulation time 173481860 ps
CPU time 0.84 seconds
Started Mar 12 12:45:07 PM PDT 24
Finished Mar 12 12:45:08 PM PDT 24
Peak memory 200164 kb
Host smart-ac41237c-40b4-48ed-9c88-2c5e38e8e68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010951423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3010951423
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2640177180
Short name T474
Test name
Test status
Simulation time 1441705310 ps
CPU time 5.55 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:19 PM PDT 24
Peak memory 200408 kb
Host smart-2d398af4-5b90-48fd-a3dd-74348811cf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640177180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2640177180
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.544228115
Short name T427
Test name
Test status
Simulation time 99991285 ps
CPU time 1 seconds
Started Mar 12 12:45:03 PM PDT 24
Finished Mar 12 12:45:04 PM PDT 24
Peak memory 200180 kb
Host smart-f5292b00-c2d6-40fd-92ff-9d3caf8247b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544228115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.544228115
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.943717256
Short name T386
Test name
Test status
Simulation time 244150324 ps
CPU time 1.39 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 200428 kb
Host smart-1fecb0d5-a0a5-44dd-a2a2-cd7b9a88e36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943717256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.943717256
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.251828434
Short name T336
Test name
Test status
Simulation time 7432299662 ps
CPU time 29.86 seconds
Started Mar 12 12:45:05 PM PDT 24
Finished Mar 12 12:45:35 PM PDT 24
Peak memory 200592 kb
Host smart-98d5ff48-9a58-42c8-980d-05bc0086a996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251828434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.251828434
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1102982840
Short name T60
Test name
Test status
Simulation time 297958715 ps
CPU time 1.97 seconds
Started Mar 12 12:45:01 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 208476 kb
Host smart-b01d3ae0-f94b-43bf-b124-9010488cda7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102982840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1102982840
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4179676700
Short name T206
Test name
Test status
Simulation time 130070074 ps
CPU time 1.13 seconds
Started Mar 12 12:45:04 PM PDT 24
Finished Mar 12 12:45:05 PM PDT 24
Peak memory 200356 kb
Host smart-ab801159-f403-4c45-97bf-d410d442b1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179676700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4179676700
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3301059487
Short name T202
Test name
Test status
Simulation time 69815373 ps
CPU time 0.79 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 200236 kb
Host smart-7c41829b-3e27-48d8-89e2-955ed62fd010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301059487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3301059487
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1897799859
Short name T443
Test name
Test status
Simulation time 1220870302 ps
CPU time 5.35 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:08 PM PDT 24
Peak memory 216500 kb
Host smart-baf99d01-36dc-47d8-84f9-f8f64c02bbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897799859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1897799859
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.602612181
Short name T525
Test name
Test status
Simulation time 244614814 ps
CPU time 1 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 217240 kb
Host smart-f8c3d16c-d896-4f3d-a3df-86d51ec8387e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602612181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.602612181
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3242603159
Short name T490
Test name
Test status
Simulation time 204701425 ps
CPU time 0.85 seconds
Started Mar 12 12:45:11 PM PDT 24
Finished Mar 12 12:45:13 PM PDT 24
Peak memory 200076 kb
Host smart-6046d88d-f99d-4812-9da4-53bd8436a64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242603159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3242603159
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2086008893
Short name T306
Test name
Test status
Simulation time 761165088 ps
CPU time 4.08 seconds
Started Mar 12 12:45:03 PM PDT 24
Finished Mar 12 12:45:07 PM PDT 24
Peak memory 200596 kb
Host smart-3108c473-d700-4bc0-928a-eb9e0bea30e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086008893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2086008893
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1632630611
Short name T357
Test name
Test status
Simulation time 95235083 ps
CPU time 1.12 seconds
Started Mar 12 12:45:09 PM PDT 24
Finished Mar 12 12:45:10 PM PDT 24
Peak memory 200160 kb
Host smart-4dbe1909-c750-46b7-a5d8-f201b4b6af43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632630611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1632630611
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3677558254
Short name T41
Test name
Test status
Simulation time 192951815 ps
CPU time 1.36 seconds
Started Mar 12 12:45:09 PM PDT 24
Finished Mar 12 12:45:11 PM PDT 24
Peak memory 200272 kb
Host smart-a509fc51-915f-453b-a023-76268da05744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677558254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3677558254
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.4140106492
Short name T42
Test name
Test status
Simulation time 3265850261 ps
CPU time 15.68 seconds
Started Mar 12 12:45:09 PM PDT 24
Finished Mar 12 12:45:25 PM PDT 24
Peak memory 200516 kb
Host smart-ba454260-4954-48b2-a611-be07440fb077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140106492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.4140106492
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3451108465
Short name T453
Test name
Test status
Simulation time 138162161 ps
CPU time 1.71 seconds
Started Mar 12 12:45:07 PM PDT 24
Finished Mar 12 12:45:09 PM PDT 24
Peak memory 200260 kb
Host smart-4f323488-049e-404a-962a-d8693e04bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451108465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3451108465
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2574580036
Short name T353
Test name
Test status
Simulation time 164620467 ps
CPU time 1.19 seconds
Started Mar 12 12:45:02 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 200380 kb
Host smart-e7ea0aa5-d0bf-4e52-a0f9-b754f5f831c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574580036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2574580036
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3359335216
Short name T321
Test name
Test status
Simulation time 72403896 ps
CPU time 0.75 seconds
Started Mar 12 12:45:16 PM PDT 24
Finished Mar 12 12:45:19 PM PDT 24
Peak memory 200272 kb
Host smart-426530aa-bb44-4b50-bb89-50eb805e5184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359335216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3359335216
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1391354008
Short name T404
Test name
Test status
Simulation time 1221963834 ps
CPU time 5.58 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:19 PM PDT 24
Peak memory 216600 kb
Host smart-3da4a75b-071e-4686-82d3-01455f64a5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391354008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1391354008
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4285367851
Short name T447
Test name
Test status
Simulation time 243947280 ps
CPU time 1.08 seconds
Started Mar 12 12:45:15 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 216980 kb
Host smart-2caccd90-c8a8-4e47-a763-6ecff07f08d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285367851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4285367851
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.760565954
Short name T267
Test name
Test status
Simulation time 107537228 ps
CPU time 0.74 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:16 PM PDT 24
Peak memory 200208 kb
Host smart-72bcf34e-beac-458d-bd61-d59019707d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760565954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.760565954
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2142284016
Short name T273
Test name
Test status
Simulation time 1851709856 ps
CPU time 6.37 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:22 PM PDT 24
Peak memory 200548 kb
Host smart-24839d1e-8652-45e6-bf98-a3bd5461aa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142284016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2142284016
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3217812719
Short name T300
Test name
Test status
Simulation time 164867270 ps
CPU time 1.24 seconds
Started Mar 12 12:45:11 PM PDT 24
Finished Mar 12 12:45:13 PM PDT 24
Peak memory 200372 kb
Host smart-a9578c2f-c5a5-485f-9a98-c4a129af7c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217812719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3217812719
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3182513088
Short name T537
Test name
Test status
Simulation time 114539184 ps
CPU time 1.18 seconds
Started Mar 12 12:45:16 PM PDT 24
Finished Mar 12 12:45:18 PM PDT 24
Peak memory 200440 kb
Host smart-52a95df9-606d-4c1e-a23c-f98363b89ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182513088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3182513088
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1719271827
Short name T315
Test name
Test status
Simulation time 12318055864 ps
CPU time 42.09 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:55 PM PDT 24
Peak memory 208848 kb
Host smart-22638a3e-5f0c-4765-af95-a143f8e3641e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719271827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1719271827
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3853179280
Short name T419
Test name
Test status
Simulation time 268610580 ps
CPU time 1.87 seconds
Started Mar 12 12:45:13 PM PDT 24
Finished Mar 12 12:45:15 PM PDT 24
Peak memory 200280 kb
Host smart-b26f7175-036f-4623-8b63-919db8a5b462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853179280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3853179280
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3119893516
Short name T507
Test name
Test status
Simulation time 209280100 ps
CPU time 1.3 seconds
Started Mar 12 12:45:15 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 200288 kb
Host smart-fd8540f8-7734-412b-b589-571756ba74a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119893516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3119893516
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1070132751
Short name T539
Test name
Test status
Simulation time 77276657 ps
CPU time 0.82 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 200180 kb
Host smart-d0b273b9-41f6-4dad-b9e4-14c4bc653f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070132751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1070132751
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2138325185
Short name T303
Test name
Test status
Simulation time 1229756071 ps
CPU time 5.61 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:22 PM PDT 24
Peak memory 221796 kb
Host smart-4a202548-ad19-4d6b-8934-3ad5ad784651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138325185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2138325185
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1466421324
Short name T225
Test name
Test status
Simulation time 254440373 ps
CPU time 1.03 seconds
Started Mar 12 12:45:15 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 217216 kb
Host smart-7d11af9e-03be-40a5-b81e-9c246cbfd350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466421324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1466421324
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1113428747
Short name T233
Test name
Test status
Simulation time 108832326 ps
CPU time 0.75 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 200180 kb
Host smart-f88b1869-36e8-4125-b4f9-4cc78c59202e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113428747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1113428747
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.920427974
Short name T340
Test name
Test status
Simulation time 870197206 ps
CPU time 4.11 seconds
Started Mar 12 12:45:15 PM PDT 24
Finished Mar 12 12:45:21 PM PDT 24
Peak memory 200452 kb
Host smart-8372ab84-d172-44da-993d-2ab6ab99b0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920427974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.920427974
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3626358936
Short name T93
Test name
Test status
Simulation time 106124581 ps
CPU time 1.01 seconds
Started Mar 12 12:45:15 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 200376 kb
Host smart-72b4b0c4-aa17-4971-941b-77d3e1086268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626358936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3626358936
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3433693417
Short name T514
Test name
Test status
Simulation time 125580809 ps
CPU time 1.15 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 200436 kb
Host smart-7f9aecf1-c810-40d2-9e9a-3dddc12956d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433693417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3433693417
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.633643979
Short name T197
Test name
Test status
Simulation time 3877309050 ps
CPU time 18.02 seconds
Started Mar 12 12:45:10 PM PDT 24
Finished Mar 12 12:45:29 PM PDT 24
Peak memory 200608 kb
Host smart-ffcb1c80-d294-4533-a41c-e26e944021f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633643979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.633643979
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3299974267
Short name T430
Test name
Test status
Simulation time 131404613 ps
CPU time 1.54 seconds
Started Mar 12 12:45:15 PM PDT 24
Finished Mar 12 12:45:18 PM PDT 24
Peak memory 200256 kb
Host smart-42ac0fac-65aa-48bb-8046-342c7f01f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299974267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3299974267
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.108797768
Short name T346
Test name
Test status
Simulation time 102993953 ps
CPU time 0.89 seconds
Started Mar 12 12:45:17 PM PDT 24
Finished Mar 12 12:45:20 PM PDT 24
Peak memory 200360 kb
Host smart-13b440f3-6894-4c95-9c31-4e02aff88506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108797768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.108797768
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.865914672
Short name T345
Test name
Test status
Simulation time 84749555 ps
CPU time 0.78 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 200276 kb
Host smart-2825a8ff-c097-4c32-9363-3818329d7aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865914672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.865914672
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.441320634
Short name T47
Test name
Test status
Simulation time 1225170274 ps
CPU time 5.36 seconds
Started Mar 12 12:45:11 PM PDT 24
Finished Mar 12 12:45:18 PM PDT 24
Peak memory 221736 kb
Host smart-667a9cd5-7992-4836-9e45-ec9f7a6a8b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441320634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.441320634
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1843325274
Short name T331
Test name
Test status
Simulation time 243404513 ps
CPU time 1.14 seconds
Started Mar 12 12:45:16 PM PDT 24
Finished Mar 12 12:45:18 PM PDT 24
Peak memory 217048 kb
Host smart-635bda2e-ebe8-4bf4-b2c8-a05f72cc7036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843325274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1843325274
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2832787543
Short name T226
Test name
Test status
Simulation time 207189287 ps
CPU time 0.86 seconds
Started Mar 12 12:45:15 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 200156 kb
Host smart-d1d7d57c-b922-44b8-9eef-7090e9224c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832787543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2832787543
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.854306244
Short name T402
Test name
Test status
Simulation time 1634052752 ps
CPU time 5.95 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:19 PM PDT 24
Peak memory 200536 kb
Host smart-0bf56b58-73dd-4185-ad06-243c765d5b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854306244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.854306244
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.4190435769
Short name T334
Test name
Test status
Simulation time 104124472 ps
CPU time 0.94 seconds
Started Mar 12 12:45:13 PM PDT 24
Finished Mar 12 12:45:14 PM PDT 24
Peak memory 200352 kb
Host smart-70e6312b-ad96-4456-bd0c-0753281cc758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190435769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.4190435769
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1977782659
Short name T319
Test name
Test status
Simulation time 124037054 ps
CPU time 1.24 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:16 PM PDT 24
Peak memory 200436 kb
Host smart-d456ad5b-839b-45bf-9261-91bb948b6dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977782659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1977782659
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1142585361
Short name T307
Test name
Test status
Simulation time 8526512317 ps
CPU time 29.02 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:42 PM PDT 24
Peak memory 200572 kb
Host smart-bab416c8-f815-4d39-921a-abfcb69d78ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142585361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1142585361
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3798078559
Short name T354
Test name
Test status
Simulation time 467123278 ps
CPU time 2.51 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:16 PM PDT 24
Peak memory 200320 kb
Host smart-d16abb21-4eef-4c6c-8c80-5f5863f5e7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798078559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3798078559
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2696351827
Short name T283
Test name
Test status
Simulation time 208125723 ps
CPU time 1.3 seconds
Started Mar 12 12:45:11 PM PDT 24
Finished Mar 12 12:45:14 PM PDT 24
Peak memory 200372 kb
Host smart-7a6c8f67-3798-4183-9bdd-e7635a07a162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696351827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2696351827
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.180640404
Short name T449
Test name
Test status
Simulation time 64540605 ps
CPU time 0.77 seconds
Started Mar 12 12:45:25 PM PDT 24
Finished Mar 12 12:45:26 PM PDT 24
Peak memory 200292 kb
Host smart-a55425b1-d6df-4068-ad98-2a22ba44718d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180640404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.180640404
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.823228509
Short name T27
Test name
Test status
Simulation time 2366715853 ps
CPU time 8.34 seconds
Started Mar 12 12:45:28 PM PDT 24
Finished Mar 12 12:45:36 PM PDT 24
Peak memory 221020 kb
Host smart-ca06eae8-9831-4b18-a40a-b0cf08ac37c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823228509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.823228509
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2592231769
Short name T403
Test name
Test status
Simulation time 245321086 ps
CPU time 1.09 seconds
Started Mar 12 12:45:25 PM PDT 24
Finished Mar 12 12:45:26 PM PDT 24
Peak memory 217264 kb
Host smart-951dbcd7-a467-4de8-b23d-c7b4bbce16e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592231769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2592231769
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3590197617
Short name T18
Test name
Test status
Simulation time 192444761 ps
CPU time 0.92 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:16 PM PDT 24
Peak memory 200160 kb
Host smart-8d306916-fcb0-494e-811a-84443e04ec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590197617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3590197617
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2815694426
Short name T119
Test name
Test status
Simulation time 1778259573 ps
CPU time 6.41 seconds
Started Mar 12 12:45:14 PM PDT 24
Finished Mar 12 12:45:22 PM PDT 24
Peak memory 200532 kb
Host smart-b81c5091-489f-4184-ab4e-bf6c97eae356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815694426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2815694426
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2784231237
Short name T391
Test name
Test status
Simulation time 110773559 ps
CPU time 1.03 seconds
Started Mar 12 12:45:32 PM PDT 24
Finished Mar 12 12:45:33 PM PDT 24
Peak memory 200228 kb
Host smart-321e6618-e6c2-4108-a7dd-e75c5c7f6641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784231237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2784231237
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2432465824
Short name T189
Test name
Test status
Simulation time 115023835 ps
CPU time 1.13 seconds
Started Mar 12 12:45:11 PM PDT 24
Finished Mar 12 12:45:14 PM PDT 24
Peak memory 200480 kb
Host smart-bb1c24e3-88cf-4f2d-a5a9-cbe39e39f10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432465824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2432465824
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2673232354
Short name T494
Test name
Test status
Simulation time 7887675512 ps
CPU time 34.09 seconds
Started Mar 12 12:45:26 PM PDT 24
Finished Mar 12 12:46:00 PM PDT 24
Peak memory 208796 kb
Host smart-bb52a5a7-5757-404c-ad07-9aedb0a69ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673232354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2673232354
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3758158832
Short name T120
Test name
Test status
Simulation time 382944197 ps
CPU time 1.98 seconds
Started Mar 12 12:45:12 PM PDT 24
Finished Mar 12 12:45:15 PM PDT 24
Peak memory 200316 kb
Host smart-0b745676-1cb2-4a8a-936b-77e5cf6bb444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758158832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3758158832
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.4223483309
Short name T522
Test name
Test status
Simulation time 144606432 ps
CPU time 1.19 seconds
Started Mar 12 12:45:16 PM PDT 24
Finished Mar 12 12:45:18 PM PDT 24
Peak memory 200408 kb
Host smart-19275f6f-3c95-43bd-9583-9d5fd53af99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223483309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4223483309
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2848559297
Short name T152
Test name
Test status
Simulation time 68606487 ps
CPU time 0.8 seconds
Started Mar 12 12:45:24 PM PDT 24
Finished Mar 12 12:45:25 PM PDT 24
Peak memory 200248 kb
Host smart-8c145b3d-1d4f-4b71-960d-90f7e1a98f33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848559297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2848559297
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3781097751
Short name T53
Test name
Test status
Simulation time 1236840611 ps
CPU time 5.72 seconds
Started Mar 12 12:45:24 PM PDT 24
Finished Mar 12 12:45:30 PM PDT 24
Peak memory 221576 kb
Host smart-9feeccc9-1f4d-4d75-93c6-e50914e0aead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781097751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3781097751
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1903205622
Short name T372
Test name
Test status
Simulation time 244453611 ps
CPU time 1.02 seconds
Started Mar 12 12:45:21 PM PDT 24
Finished Mar 12 12:45:23 PM PDT 24
Peak memory 217092 kb
Host smart-a46f9b5a-a561-4f09-9a55-2025c5ecf030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903205622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1903205622
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3466395653
Short name T524
Test name
Test status
Simulation time 155860713 ps
CPU time 0.89 seconds
Started Mar 12 12:45:25 PM PDT 24
Finished Mar 12 12:45:26 PM PDT 24
Peak memory 200212 kb
Host smart-bbfb622b-3b51-4dbd-8efd-3ef0084293de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466395653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3466395653
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3403318225
Short name T144
Test name
Test status
Simulation time 1451664192 ps
CPU time 5.54 seconds
Started Mar 12 12:45:29 PM PDT 24
Finished Mar 12 12:45:34 PM PDT 24
Peak memory 200528 kb
Host smart-a7628fe0-15b3-41d2-b0a8-bb66483b9d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403318225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3403318225
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2215184610
Short name T309
Test name
Test status
Simulation time 106657301 ps
CPU time 1.01 seconds
Started Mar 12 12:45:24 PM PDT 24
Finished Mar 12 12:45:25 PM PDT 24
Peak memory 200376 kb
Host smart-13de4d12-86c4-4599-ad5b-b1c4ba234a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215184610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2215184610
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1399972558
Short name T531
Test name
Test status
Simulation time 191360870 ps
CPU time 1.38 seconds
Started Mar 12 12:45:25 PM PDT 24
Finished Mar 12 12:45:26 PM PDT 24
Peak memory 200404 kb
Host smart-1e133e8e-6fbe-4cbc-abf7-d32958ff3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399972558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1399972558
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1885487614
Short name T98
Test name
Test status
Simulation time 11762287754 ps
CPU time 44.11 seconds
Started Mar 12 12:45:24 PM PDT 24
Finished Mar 12 12:46:09 PM PDT 24
Peak memory 208828 kb
Host smart-bdfd4ced-2f45-4697-9ace-612ccae2c684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885487614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1885487614
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.4239817617
Short name T344
Test name
Test status
Simulation time 290241083 ps
CPU time 2.08 seconds
Started Mar 12 12:45:25 PM PDT 24
Finished Mar 12 12:45:28 PM PDT 24
Peak memory 208468 kb
Host smart-fa70a932-24cf-449e-96c7-51f6e1fc1325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239817617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.4239817617
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1512691106
Short name T22
Test name
Test status
Simulation time 71400929 ps
CPU time 0.78 seconds
Started Mar 12 12:45:24 PM PDT 24
Finished Mar 12 12:45:25 PM PDT 24
Peak memory 200364 kb
Host smart-4d7a2840-df8e-4fec-be4b-103a3e55c80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512691106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1512691106
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1060408633
Short name T483
Test name
Test status
Simulation time 68611605 ps
CPU time 0.78 seconds
Started Mar 12 12:45:27 PM PDT 24
Finished Mar 12 12:45:27 PM PDT 24
Peak memory 200236 kb
Host smart-99c6ed36-8d53-4bfd-abed-dbe201460eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060408633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1060408633
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.762239988
Short name T126
Test name
Test status
Simulation time 1232199512 ps
CPU time 5.57 seconds
Started Mar 12 12:45:28 PM PDT 24
Finished Mar 12 12:45:34 PM PDT 24
Peak memory 217096 kb
Host smart-856a9845-9a17-4922-a956-0dac04919016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762239988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.762239988
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.441759561
Short name T405
Test name
Test status
Simulation time 244190307 ps
CPU time 1.12 seconds
Started Mar 12 12:45:23 PM PDT 24
Finished Mar 12 12:45:25 PM PDT 24
Peak memory 217112 kb
Host smart-4944d50d-3ca9-40db-baec-920bf245a058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441759561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.441759561
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.174627816
Short name T207
Test name
Test status
Simulation time 161494779 ps
CPU time 0.89 seconds
Started Mar 12 12:45:26 PM PDT 24
Finished Mar 12 12:45:27 PM PDT 24
Peak memory 200164 kb
Host smart-55df75e6-5196-404d-982a-709f837b212c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174627816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.174627816
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.762738020
Short name T37
Test name
Test status
Simulation time 1366634115 ps
CPU time 5.38 seconds
Started Mar 12 12:45:25 PM PDT 24
Finished Mar 12 12:45:30 PM PDT 24
Peak memory 200396 kb
Host smart-115cc9e1-9194-474e-8ad6-39ca39c69b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762738020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.762738020
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.555565868
Short name T508
Test name
Test status
Simulation time 176286671 ps
CPU time 1.16 seconds
Started Mar 12 12:45:29 PM PDT 24
Finished Mar 12 12:45:31 PM PDT 24
Peak memory 200380 kb
Host smart-b8c830ff-515a-4f1b-9a62-10859ebfe241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555565868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.555565868
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.240548491
Short name T479
Test name
Test status
Simulation time 243078790 ps
CPU time 1.41 seconds
Started Mar 12 12:45:23 PM PDT 24
Finished Mar 12 12:45:24 PM PDT 24
Peak memory 200428 kb
Host smart-efb8a5a9-4371-4a92-9006-d738a5c136e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240548491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.240548491
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.931635897
Short name T187
Test name
Test status
Simulation time 12526080293 ps
CPU time 43.94 seconds
Started Mar 12 12:45:32 PM PDT 24
Finished Mar 12 12:46:16 PM PDT 24
Peak memory 209448 kb
Host smart-c10f2c1f-6c98-4b69-8d51-767ee6f661e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931635897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.931635897
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.4131191304
Short name T160
Test name
Test status
Simulation time 327493415 ps
CPU time 2.06 seconds
Started Mar 12 12:45:24 PM PDT 24
Finished Mar 12 12:45:26 PM PDT 24
Peak memory 200236 kb
Host smart-d7ca7cdf-adef-4b4e-a21a-e20a79161dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131191304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.4131191304
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1887891534
Short name T355
Test name
Test status
Simulation time 90488457 ps
CPU time 0.95 seconds
Started Mar 12 12:45:29 PM PDT 24
Finished Mar 12 12:45:30 PM PDT 24
Peak memory 200368 kb
Host smart-61ed1c48-0938-4421-bd42-f1c69cc9a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887891534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1887891534
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3809138188
Short name T253
Test name
Test status
Simulation time 80244596 ps
CPU time 0.78 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:50 PM PDT 24
Peak memory 200160 kb
Host smart-52f209f5-433b-4955-9b50-ba70d0d8cb95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809138188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3809138188
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.241381157
Short name T52
Test name
Test status
Simulation time 2343641797 ps
CPU time 8.3 seconds
Started Mar 12 12:43:46 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 216872 kb
Host smart-aae509b5-6ce9-499d-a196-713d9c00f98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241381157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.241381157
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3638373634
Short name T72
Test name
Test status
Simulation time 243832769 ps
CPU time 1.05 seconds
Started Mar 12 12:43:57 PM PDT 24
Finished Mar 12 12:43:58 PM PDT 24
Peak memory 217056 kb
Host smart-cdda1ed9-566f-49f6-9995-1088e9df5f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638373634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3638373634
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.286934013
Short name T444
Test name
Test status
Simulation time 87319063 ps
CPU time 0.73 seconds
Started Mar 12 12:43:52 PM PDT 24
Finished Mar 12 12:43:53 PM PDT 24
Peak memory 200068 kb
Host smart-55828718-3f15-45b2-8efe-c1025c9daf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286934013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.286934013
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.526302736
Short name T167
Test name
Test status
Simulation time 835613568 ps
CPU time 4.06 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:53 PM PDT 24
Peak memory 200380 kb
Host smart-53041b54-a37f-4868-91be-2ea3241aa76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526302736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.526302736
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1621545905
Short name T139
Test name
Test status
Simulation time 98990900 ps
CPU time 0.96 seconds
Started Mar 12 12:43:53 PM PDT 24
Finished Mar 12 12:43:54 PM PDT 24
Peak memory 200276 kb
Host smart-485f1ea8-4d40-4e75-b5d6-98ae6e12fe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621545905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1621545905
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3193423714
Short name T540
Test name
Test status
Simulation time 192611654 ps
CPU time 1.45 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:51 PM PDT 24
Peak memory 200492 kb
Host smart-837c706c-792f-4244-b5f2-4e2afecabc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193423714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3193423714
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3633929039
Short name T515
Test name
Test status
Simulation time 6197792177 ps
CPU time 27.67 seconds
Started Mar 12 12:43:52 PM PDT 24
Finished Mar 12 12:44:20 PM PDT 24
Peak memory 200608 kb
Host smart-b41f90d2-b3e8-4b80-b978-c8f3d721f43a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633929039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3633929039
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3262058157
Short name T343
Test name
Test status
Simulation time 361398738 ps
CPU time 2.24 seconds
Started Mar 12 12:43:47 PM PDT 24
Finished Mar 12 12:43:50 PM PDT 24
Peak memory 200304 kb
Host smart-e23ce1ef-bc24-40d1-b371-e10d15ca36e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262058157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3262058157
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.4247375633
Short name T156
Test name
Test status
Simulation time 59866926 ps
CPU time 0.76 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:49 PM PDT 24
Peak memory 200256 kb
Host smart-2f50b838-9960-4b3c-b500-ab862b20b93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247375633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4247375633
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3352285939
Short name T237
Test name
Test status
Simulation time 67280411 ps
CPU time 0.77 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:50 PM PDT 24
Peak memory 200200 kb
Host smart-034e870d-251a-4f14-a9d9-65339cb94eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352285939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3352285939
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3140865277
Short name T31
Test name
Test status
Simulation time 2356296999 ps
CPU time 7.82 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 217492 kb
Host smart-672b2a95-1ab6-4f21-9ec1-030aafebc378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140865277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3140865277
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4100818320
Short name T213
Test name
Test status
Simulation time 244832738 ps
CPU time 1.03 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 217132 kb
Host smart-979d841d-8ea1-4e5e-a66a-c8a75422fdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100818320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.4100818320
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3917320900
Short name T270
Test name
Test status
Simulation time 158458532 ps
CPU time 0.81 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:51 PM PDT 24
Peak memory 200160 kb
Host smart-728fd054-1fee-4a49-8a99-cb0a60b59b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917320900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3917320900
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.829830836
Short name T407
Test name
Test status
Simulation time 1444157674 ps
CPU time 5.84 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 200532 kb
Host smart-bd9437de-545e-479f-b663-9352178e5835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829830836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.829830836
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3201725692
Short name T412
Test name
Test status
Simulation time 151910651 ps
CPU time 1.12 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:50 PM PDT 24
Peak memory 200228 kb
Host smart-860ec6af-188c-437f-a84f-e48905d7dcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201725692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3201725692
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.906868825
Short name T185
Test name
Test status
Simulation time 110524617 ps
CPU time 1.14 seconds
Started Mar 12 12:43:53 PM PDT 24
Finished Mar 12 12:43:54 PM PDT 24
Peak memory 200360 kb
Host smart-dd29a138-9bc8-4c4f-b852-6c3f82c9b396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906868825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.906868825
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3936376987
Short name T373
Test name
Test status
Simulation time 4121058013 ps
CPU time 19.95 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:44:11 PM PDT 24
Peak memory 208712 kb
Host smart-3a1aa47b-cbfa-4c08-9bdd-742b9ada285e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936376987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3936376987
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.37925772
Short name T535
Test name
Test status
Simulation time 271274606 ps
CPU time 1.81 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 200348 kb
Host smart-af8d5496-636b-468c-9a37-c4fc72ba6f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37925772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.37925772
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3725004118
Short name T71
Test name
Test status
Simulation time 140529022 ps
CPU time 1.11 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:51 PM PDT 24
Peak memory 200256 kb
Host smart-12cf07fd-8531-45bc-91b7-e5754879055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725004118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3725004118
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2520025732
Short name T360
Test name
Test status
Simulation time 63537919 ps
CPU time 0.8 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 200124 kb
Host smart-bb7346b6-6cb0-4310-b2dc-62d5a86cb23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520025732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2520025732
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3859571219
Short name T32
Test name
Test status
Simulation time 1218288858 ps
CPU time 5.52 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 217720 kb
Host smart-253715c4-e789-4701-b17c-9510d4b548d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859571219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3859571219
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2719883471
Short name T380
Test name
Test status
Simulation time 244234933 ps
CPU time 1.07 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 217052 kb
Host smart-c4fade85-62e2-4676-9b10-aa08582cd6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719883471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2719883471
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3992502192
Short name T231
Test name
Test status
Simulation time 156197821 ps
CPU time 0.82 seconds
Started Mar 12 12:43:48 PM PDT 24
Finished Mar 12 12:43:49 PM PDT 24
Peak memory 200112 kb
Host smart-e17ad91c-dd78-4153-91c8-2c8cb36a4a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992502192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3992502192
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1769186889
Short name T227
Test name
Test status
Simulation time 1562284816 ps
CPU time 6.2 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:44:00 PM PDT 24
Peak memory 200420 kb
Host smart-cac40cc8-618e-4b1e-b9cb-7360615f3e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769186889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1769186889
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1873425467
Short name T165
Test name
Test status
Simulation time 180438980 ps
CPU time 1.17 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 200400 kb
Host smart-7b5e7101-8fc7-425c-b2d2-ce0515531932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873425467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1873425467
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.381993035
Short name T39
Test name
Test status
Simulation time 130956796 ps
CPU time 1.22 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:51 PM PDT 24
Peak memory 200400 kb
Host smart-07662470-85aa-4044-aa44-989ce33b321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381993035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.381993035
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3279715959
Short name T523
Test name
Test status
Simulation time 7428553284 ps
CPU time 28.64 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:44:17 PM PDT 24
Peak memory 208720 kb
Host smart-fe690916-b1f6-4f92-ad38-2b17dfa93112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279715959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3279715959
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.4023652654
Short name T387
Test name
Test status
Simulation time 112656707 ps
CPU time 1.35 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:51 PM PDT 24
Peak memory 200248 kb
Host smart-66c51dbd-ec0f-4969-bf4b-53630bb7285d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023652654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.4023652654
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1269023849
Short name T478
Test name
Test status
Simulation time 243199445 ps
CPU time 1.44 seconds
Started Mar 12 12:43:57 PM PDT 24
Finished Mar 12 12:43:59 PM PDT 24
Peak memory 200388 kb
Host smart-a5132d16-ea58-4849-a1a7-d4f113b9c0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269023849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1269023849
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2085291840
Short name T232
Test name
Test status
Simulation time 76205833 ps
CPU time 0.84 seconds
Started Mar 12 12:43:55 PM PDT 24
Finished Mar 12 12:43:56 PM PDT 24
Peak memory 200140 kb
Host smart-248f8265-d66c-47ab-b931-8d3e293836ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085291840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2085291840
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2540965887
Short name T26
Test name
Test status
Simulation time 1236832354 ps
CPU time 5.15 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:56 PM PDT 24
Peak memory 218256 kb
Host smart-31853911-a0cb-4fd3-9aca-b0ede4648455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540965887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2540965887
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3751360965
Short name T339
Test name
Test status
Simulation time 245291934 ps
CPU time 1.01 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 217176 kb
Host smart-5c0f26ab-7600-4b6d-b02f-fca4ee2898f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751360965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3751360965
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1969047406
Short name T424
Test name
Test status
Simulation time 170330116 ps
CPU time 0.82 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 200164 kb
Host smart-7db39ddc-3b51-4c8f-a7d4-0981ee5867c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969047406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1969047406
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.257232519
Short name T263
Test name
Test status
Simulation time 1593250319 ps
CPU time 6.05 seconds
Started Mar 12 12:43:48 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 200548 kb
Host smart-a38cb7fd-e775-444c-b647-687ead3f57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257232519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.257232519
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.475902935
Short name T358
Test name
Test status
Simulation time 180953865 ps
CPU time 1.16 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 200356 kb
Host smart-d34dbc86-6dda-4c09-ae7b-f596d836b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475902935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.475902935
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.4262961253
Short name T55
Test name
Test status
Simulation time 123116855 ps
CPU time 1.12 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:43:55 PM PDT 24
Peak memory 200496 kb
Host smart-d877d9ed-4673-4447-9c3a-df24f04886e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262961253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4262961253
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2967377137
Short name T117
Test name
Test status
Simulation time 14215147841 ps
CPU time 45.34 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:44:36 PM PDT 24
Peak memory 200560 kb
Host smart-456fad84-b1fd-4dc6-add9-cc0142d0b1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967377137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2967377137
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.4011854631
Short name T123
Test name
Test status
Simulation time 482955309 ps
CPU time 2.58 seconds
Started Mar 12 12:43:49 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 200356 kb
Host smart-e9ea6ef7-052a-4f4b-b24a-eba5b53eba97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011854631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.4011854631
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2106342219
Short name T136
Test name
Test status
Simulation time 112529620 ps
CPU time 0.91 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 200392 kb
Host smart-1c2ea99e-0e72-445b-a25a-34e81d9997c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106342219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2106342219
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.31492723
Short name T183
Test name
Test status
Simulation time 74565037 ps
CPU time 0.76 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:51 PM PDT 24
Peak memory 200244 kb
Host smart-5560c4e2-c33e-453a-a153-46b4a6367dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31492723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.31492723
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.704931897
Short name T337
Test name
Test status
Simulation time 1217085896 ps
CPU time 5.5 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:44:00 PM PDT 24
Peak memory 217720 kb
Host smart-66c8c241-a978-4fab-bc3e-9af931aebe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704931897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.704931897
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2632495930
Short name T467
Test name
Test status
Simulation time 244492470 ps
CPU time 1.01 seconds
Started Mar 12 12:43:55 PM PDT 24
Finished Mar 12 12:43:56 PM PDT 24
Peak memory 217068 kb
Host smart-b72549ef-3aa1-4dcd-8aec-10cc8fd348ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632495930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2632495930
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1874292013
Short name T376
Test name
Test status
Simulation time 195691603 ps
CPU time 0.91 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:51 PM PDT 24
Peak memory 200056 kb
Host smart-f4506e9e-d5ce-4dcf-a384-3d4f08ea2b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874292013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1874292013
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3213370033
Short name T229
Test name
Test status
Simulation time 1482626158 ps
CPU time 5.79 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 200500 kb
Host smart-d32dd158-c782-475a-a6ed-65ad1014d876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213370033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3213370033
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4229694434
Short name T484
Test name
Test status
Simulation time 176782619 ps
CPU time 1.24 seconds
Started Mar 12 12:43:58 PM PDT 24
Finished Mar 12 12:43:59 PM PDT 24
Peak memory 200332 kb
Host smart-aa6ef037-8140-4352-9e91-d0b070fd4aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229694434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.4229694434
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1736176144
Short name T125
Test name
Test status
Simulation time 254080267 ps
CPU time 1.57 seconds
Started Mar 12 12:43:50 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 200392 kb
Host smart-f9dbb84e-68d1-454e-865d-1ee4b4637ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736176144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1736176144
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3408887748
Short name T5
Test name
Test status
Simulation time 10767619233 ps
CPU time 39.54 seconds
Started Mar 12 12:43:54 PM PDT 24
Finished Mar 12 12:44:33 PM PDT 24
Peak memory 200632 kb
Host smart-7149c58d-bcab-4270-993d-2557feb28f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408887748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3408887748
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.939596518
Short name T248
Test name
Test status
Simulation time 142329310 ps
CPU time 1.76 seconds
Started Mar 12 12:43:51 PM PDT 24
Finished Mar 12 12:43:53 PM PDT 24
Peak memory 200268 kb
Host smart-d1dee30d-46c9-443d-a082-0076c88ca0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939596518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.939596518
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.620686255
Short name T377
Test name
Test status
Simulation time 276084427 ps
CPU time 1.48 seconds
Started Mar 12 12:43:55 PM PDT 24
Finished Mar 12 12:43:56 PM PDT 24
Peak memory 200356 kb
Host smart-046b5e2b-c4cb-4198-8354-e8f5d102ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620686255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.620686255
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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