Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7850

1

T2

61

T5

158

T6

18

auto[1]

10924

1

T2

67

T3

4

T5

181

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5861	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6341	1			T1	1		T2	38		T3	2
reset_info_cp[2]	2866	1			T2	22		T3	1		T5	43
reset_info_cp[4]	3770	1			T2	32		T3	1		T5	80
reset_info_cp[8]	113	1			T5	1		T24	1		T41	2
reset_info_cp[16]	103	1			T5	2		T6	1		T8	1
reset_info_cp[32]	112	1			T5	3		T9	1		T12	2
reset_info_cp[64]	109	1			T5	2		T9	1		T10	2
reset_info_cp[128]	119	1			T2	2		T5	5		T9	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2997	1			T2	16		T5	52		T6	18
reset_info_cp[1]	auto[1]	2724	1			T2	21		T3	1		T5	55
reset_info_cp[2]	auto[0]	894	1			T2	12		T5	16		T24	7
reset_info_cp[2]	auto[1]	1972	1			T2	10		T3	1		T5	27
reset_info_cp[4]	auto[0]	1310	1			T2	15		T5	38		T24	6
reset_info_cp[4]	auto[1]	2460	1			T2	17		T3	1		T5	42
reset_info_cp[8]	auto[0]	41	1			T41	1		T87	1		T91	1
reset_info_cp[8]	auto[1]	72	1			T5	1		T24	1		T41	1
reset_info_cp[16]	auto[0]	38	1			T90	1		T91	1		T126	1
reset_info_cp[16]	auto[1]	65	1			T5	2		T6	1		T8	1
reset_info_cp[32]	auto[0]	51	1			T5	2		T9	1		T24	1
reset_info_cp[32]	auto[1]	61	1			T5	1		T12	2		T72	1
reset_info_cp[64]	auto[0]	46	1			T9	1		T10	2		T41	2
reset_info_cp[64]	auto[1]	63	1			T5	2		T42	1		T28	1
reset_info_cp[128]	auto[0]	59	1			T5	1		T9	1		T72	1
reset_info_cp[128]	auto[1]	60	1			T2	2		T5	4		T36	2