Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspace/coverage/default/3.rstmgr_sw_rst.309469701 Mar 14 12:31:23 PM PDT 24 Mar 14 12:31:25 PM PDT 24 124035594 ps
T541 /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4244447187 Mar 14 12:31:52 PM PDT 24 Mar 14 12:31:54 PM PDT 24 186749301 ps
T542 /workspace/coverage/default/26.rstmgr_por_stretcher.751788551 Mar 14 12:31:44 PM PDT 24 Mar 14 12:31:45 PM PDT 24 149148530 ps
T543 /workspace/coverage/default/27.rstmgr_reset.3801628650 Mar 14 12:32:02 PM PDT 24 Mar 14 12:32:07 PM PDT 24 888115600 ps
T544 /workspace/coverage/default/44.rstmgr_reset.3723739850 Mar 14 12:32:14 PM PDT 24 Mar 14 12:32:21 PM PDT 24 1930420698 ps
T48 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4093389579 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:56 PM PDT 24 201164920 ps
T49 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3383538610 Mar 14 12:25:38 PM PDT 24 Mar 14 12:25:40 PM PDT 24 149111130 ps
T50 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2909719682 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:48 PM PDT 24 180149238 ps
T51 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.284374158 Mar 14 12:25:42 PM PDT 24 Mar 14 12:25:44 PM PDT 24 379039428 ps
T52 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1466906009 Mar 14 12:25:17 PM PDT 24 Mar 14 12:25:18 PM PDT 24 125784727 ps
T94 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1137563245 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:34 PM PDT 24 65316208 ps
T124 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1708252537 Mar 14 12:25:26 PM PDT 24 Mar 14 12:25:27 PM PDT 24 83154078 ps
T53 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2665905622 Mar 14 12:25:56 PM PDT 24 Mar 14 12:26:00 PM PDT 24 505744581 ps
T95 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1215240630 Mar 14 12:25:38 PM PDT 24 Mar 14 12:25:39 PM PDT 24 146536073 ps
T123 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.616488198 Mar 14 12:19:44 PM PDT 24 Mar 14 12:19:46 PM PDT 24 225398131 ps
T101 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3964213569 Mar 14 12:22:39 PM PDT 24 Mar 14 12:22:40 PM PDT 24 98069739 ps
T102 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2546556711 Mar 14 12:25:14 PM PDT 24 Mar 14 12:25:22 PM PDT 24 1537910666 ps
T54 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3252821842 Mar 14 12:25:53 PM PDT 24 Mar 14 12:25:56 PM PDT 24 896333487 ps
T59 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2580409460 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:47 PM PDT 24 170406917 ps
T76 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4095495989 Mar 14 12:25:28 PM PDT 24 Mar 14 12:25:30 PM PDT 24 165694407 ps
T77 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2328618795 Mar 14 12:25:29 PM PDT 24 Mar 14 12:25:31 PM PDT 24 107409973 ps
T96 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2037280294 Mar 14 12:25:57 PM PDT 24 Mar 14 12:25:59 PM PDT 24 201530975 ps
T545 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1768154924 Mar 14 12:25:18 PM PDT 24 Mar 14 12:25:24 PM PDT 24 482166423 ps
T97 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3971566505 Mar 14 12:23:46 PM PDT 24 Mar 14 12:23:47 PM PDT 24 82370331 ps
T82 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.747185332 Mar 14 12:25:30 PM PDT 24 Mar 14 12:25:32 PM PDT 24 466236987 ps
T78 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.996374449 Mar 14 12:25:29 PM PDT 24 Mar 14 12:25:31 PM PDT 24 259620852 ps
T98 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3939783332 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:44 PM PDT 24 137160374 ps
T546 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2109955704 Mar 14 12:25:23 PM PDT 24 Mar 14 12:25:24 PM PDT 24 63158843 ps
T83 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3957976312 Mar 14 12:21:28 PM PDT 24 Mar 14 12:21:31 PM PDT 24 973793678 ps
T84 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3671264173 Mar 14 12:25:26 PM PDT 24 Mar 14 12:25:28 PM PDT 24 498817463 ps
T89 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3460418920 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:42 PM PDT 24 72361906 ps
T79 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.973570262 Mar 14 12:25:35 PM PDT 24 Mar 14 12:25:36 PM PDT 24 102993821 ps
T80 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4057205865 Mar 14 12:25:35 PM PDT 24 Mar 14 12:25:36 PM PDT 24 104107051 ps
T99 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4044601370 Mar 14 12:20:00 PM PDT 24 Mar 14 12:20:02 PM PDT 24 249078272 ps
T81 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2994519351 Mar 14 12:25:26 PM PDT 24 Mar 14 12:25:28 PM PDT 24 208156853 ps
T547 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.718253213 Mar 14 12:25:29 PM PDT 24 Mar 14 12:25:29 PM PDT 24 66790006 ps
T100 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2475159604 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:34 PM PDT 24 227732002 ps
T548 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2712507244 Mar 14 12:25:29 PM PDT 24 Mar 14 12:25:30 PM PDT 24 136121250 ps
T108 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2672153778 Mar 14 12:25:29 PM PDT 24 Mar 14 12:25:31 PM PDT 24 132158961 ps
T105 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1094371011 Mar 14 12:25:15 PM PDT 24 Mar 14 12:25:20 PM PDT 24 629695610 ps
T103 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.736730151 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:36 PM PDT 24 879963126 ps
T549 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.718100331 Mar 14 12:25:25 PM PDT 24 Mar 14 12:25:26 PM PDT 24 139658191 ps
T550 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3356146213 Mar 14 12:25:27 PM PDT 24 Mar 14 12:25:28 PM PDT 24 203036011 ps
T551 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.604144351 Mar 14 12:25:27 PM PDT 24 Mar 14 12:25:28 PM PDT 24 82024162 ps
T552 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2976964423 Mar 14 12:25:12 PM PDT 24 Mar 14 12:25:14 PM PDT 24 224692287 ps
T553 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3059234564 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:56 PM PDT 24 443245438 ps
T554 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.141885918 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:34 PM PDT 24 126397513 ps
T555 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3834541277 Mar 14 12:25:26 PM PDT 24 Mar 14 12:25:31 PM PDT 24 610574125 ps
T556 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2913932402 Mar 14 12:25:30 PM PDT 24 Mar 14 12:25:31 PM PDT 24 60862908 ps
T557 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4112726999 Mar 14 12:25:25 PM PDT 24 Mar 14 12:25:27 PM PDT 24 504489537 ps
T558 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2145730292 Mar 14 12:25:38 PM PDT 24 Mar 14 12:25:40 PM PDT 24 424036599 ps
T559 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.466674714 Mar 14 12:25:20 PM PDT 24 Mar 14 12:25:22 PM PDT 24 112871979 ps
T560 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3705869118 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:48 PM PDT 24 154024515 ps
T104 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2661703797 Mar 14 12:25:16 PM PDT 24 Mar 14 12:25:19 PM PDT 24 473987387 ps
T561 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4209885040 Mar 14 12:25:23 PM PDT 24 Mar 14 12:25:26 PM PDT 24 199984672 ps
T562 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1955228982 Mar 14 12:25:48 PM PDT 24 Mar 14 12:25:49 PM PDT 24 122414761 ps
T563 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3871711089 Mar 14 12:25:44 PM PDT 24 Mar 14 12:25:46 PM PDT 24 184451973 ps
T564 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1858127488 Mar 14 12:25:29 PM PDT 24 Mar 14 12:25:32 PM PDT 24 324856879 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1576366253 Mar 14 12:25:13 PM PDT 24 Mar 14 12:25:17 PM PDT 24 272819285 ps
T566 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3985649415 Mar 14 12:25:18 PM PDT 24 Mar 14 12:25:21 PM PDT 24 470043744 ps
T567 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2016564699 Mar 14 12:23:30 PM PDT 24 Mar 14 12:23:31 PM PDT 24 156232984 ps
T106 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2021350107 Mar 14 12:25:34 PM PDT 24 Mar 14 12:25:37 PM PDT 24 869794510 ps
T568 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1706053645 Mar 14 12:25:36 PM PDT 24 Mar 14 12:25:37 PM PDT 24 238406284 ps
T569 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2579062483 Mar 14 12:25:38 PM PDT 24 Mar 14 12:25:40 PM PDT 24 189361958 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4113361916 Mar 14 12:25:01 PM PDT 24 Mar 14 12:25:02 PM PDT 24 83124680 ps
T571 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2163888926 Mar 14 12:25:39 PM PDT 24 Mar 14 12:25:40 PM PDT 24 246071594 ps
T572 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3412535321 Mar 14 12:25:19 PM PDT 24 Mar 14 12:25:20 PM PDT 24 68456175 ps
T573 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4124281579 Mar 14 12:25:15 PM PDT 24 Mar 14 12:25:17 PM PDT 24 356038620 ps
T574 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.903088367 Mar 14 12:25:44 PM PDT 24 Mar 14 12:25:46 PM PDT 24 156569807 ps
T575 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2355826919 Mar 14 12:25:30 PM PDT 24 Mar 14 12:25:31 PM PDT 24 121287871 ps
T119 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3976600140 Mar 14 12:25:34 PM PDT 24 Mar 14 12:25:37 PM PDT 24 807782971 ps
T576 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2640814595 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:42 PM PDT 24 167946994 ps
T577 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3846133626 Mar 14 12:23:41 PM PDT 24 Mar 14 12:23:42 PM PDT 24 73688794 ps
T578 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3557368706 Mar 14 12:25:11 PM PDT 24 Mar 14 12:25:12 PM PDT 24 87568352 ps
T579 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2474614068 Mar 14 12:24:26 PM PDT 24 Mar 14 12:24:28 PM PDT 24 224994834 ps
T580 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2359568176 Mar 14 12:25:29 PM PDT 24 Mar 14 12:25:31 PM PDT 24 274822984 ps
T581 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3926055336 Mar 14 12:23:58 PM PDT 24 Mar 14 12:23:59 PM PDT 24 121158630 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2428173613 Mar 14 12:24:55 PM PDT 24 Mar 14 12:24:57 PM PDT 24 182243344 ps
T120 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2924466111 Mar 14 12:24:57 PM PDT 24 Mar 14 12:25:00 PM PDT 24 879083208 ps
T583 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3715057422 Mar 14 12:25:49 PM PDT 24 Mar 14 12:25:50 PM PDT 24 105708198 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2380826744 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:37 PM PDT 24 957080645 ps
T585 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3158612557 Mar 14 12:25:22 PM PDT 24 Mar 14 12:25:24 PM PDT 24 215902530 ps
T586 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2174380416 Mar 14 12:25:25 PM PDT 24 Mar 14 12:25:26 PM PDT 24 57609582 ps
T587 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2617828591 Mar 14 12:19:12 PM PDT 24 Mar 14 12:19:13 PM PDT 24 55067233 ps
T588 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3329403572 Mar 14 12:25:23 PM PDT 24 Mar 14 12:25:25 PM PDT 24 228735834 ps
T589 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2420517461 Mar 14 12:25:15 PM PDT 24 Mar 14 12:25:16 PM PDT 24 110483958 ps
T590 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3689226022 Mar 14 12:23:18 PM PDT 24 Mar 14 12:23:24 PM PDT 24 796416647 ps
T591 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2217217146 Mar 14 12:21:19 PM PDT 24 Mar 14 12:21:23 PM PDT 24 455320083 ps
T592 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3276011395 Mar 14 12:25:28 PM PDT 24 Mar 14 12:25:29 PM PDT 24 130070203 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4289628094 Mar 14 12:22:15 PM PDT 24 Mar 14 12:22:17 PM PDT 24 102740344 ps
T594 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3287171911 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:34 PM PDT 24 92749113 ps
T595 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2808913535 Mar 14 12:25:17 PM PDT 24 Mar 14 12:25:19 PM PDT 24 175774371 ps
T596 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3716493990 Mar 14 12:25:31 PM PDT 24 Mar 14 12:25:32 PM PDT 24 74161931 ps
T597 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.132861836 Mar 14 12:25:32 PM PDT 24 Mar 14 12:25:33 PM PDT 24 87564942 ps
T598 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2649411854 Mar 14 12:25:40 PM PDT 24 Mar 14 12:25:41 PM PDT 24 68786168 ps
T599 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1988506543 Mar 14 12:25:49 PM PDT 24 Mar 14 12:25:50 PM PDT 24 70580994 ps
T107 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1181337610 Mar 14 12:25:34 PM PDT 24 Mar 14 12:25:38 PM PDT 24 933339504 ps
T600 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1277939738 Mar 14 12:25:25 PM PDT 24 Mar 14 12:25:29 PM PDT 24 558741417 ps
T601 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2496102806 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:51 PM PDT 24 94245299 ps
T602 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3240083855 Mar 14 12:25:26 PM PDT 24 Mar 14 12:25:29 PM PDT 24 187869400 ps
T603 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4187214789 Mar 14 12:25:38 PM PDT 24 Mar 14 12:25:39 PM PDT 24 64914802 ps
T604 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.744069364 Mar 14 12:25:30 PM PDT 24 Mar 14 12:25:32 PM PDT 24 176106803 ps
T605 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2608065477 Mar 14 12:21:45 PM PDT 24 Mar 14 12:21:48 PM PDT 24 299482224 ps
T606 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3641631314 Mar 14 12:25:22 PM PDT 24 Mar 14 12:25:25 PM PDT 24 777127576 ps
T121 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2967570932 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:35 PM PDT 24 463125109 ps
T607 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3344554988 Mar 14 12:25:15 PM PDT 24 Mar 14 12:25:17 PM PDT 24 130278725 ps
T608 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1564331486 Mar 14 12:25:18 PM PDT 24 Mar 14 12:25:20 PM PDT 24 139206186 ps
T609 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3751695678 Mar 14 12:19:41 PM PDT 24 Mar 14 12:19:51 PM PDT 24 2322891198 ps
T610 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1479218730 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:34 PM PDT 24 127693746 ps
T611 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.853126139 Mar 14 12:25:28 PM PDT 24 Mar 14 12:25:31 PM PDT 24 433956483 ps
T612 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2214667007 Mar 14 12:25:32 PM PDT 24 Mar 14 12:25:34 PM PDT 24 495876189 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1667577658 Mar 14 12:25:11 PM PDT 24 Mar 14 12:25:14 PM PDT 24 358155529 ps
T614 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2615096188 Mar 14 12:25:36 PM PDT 24 Mar 14 12:25:38 PM PDT 24 471663182 ps
T615 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3603453798 Mar 14 12:25:45 PM PDT 24 Mar 14 12:25:46 PM PDT 24 146908809 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4595741 Mar 14 12:25:01 PM PDT 24 Mar 14 12:25:02 PM PDT 24 114360035 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2075611264 Mar 14 12:25:13 PM PDT 24 Mar 14 12:25:15 PM PDT 24 486410891 ps
T618 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4132285512 Mar 14 12:25:31 PM PDT 24 Mar 14 12:25:32 PM PDT 24 101162766 ps
T122 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1781474339 Mar 14 12:25:40 PM PDT 24 Mar 14 12:25:42 PM PDT 24 484404092 ps
T619 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3214460201 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:34 PM PDT 24 70081396 ps
T620 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1432644593 Mar 14 12:19:34 PM PDT 24 Mar 14 12:19:35 PM PDT 24 58783026 ps

Test location /workspace/coverage/default/21.rstmgr_stress_all.3917279706
Short name T5
Test name
Test status
Simulation time 11326542558 ps
CPU time 40.6 seconds
Started Mar 14 12:31:47 PM PDT 24
Finished Mar 14 12:32:28 PM PDT 24
Peak memory 201148 kb
Host smart-f1b15366-9293-4d39-b2e5-daf8e32c6b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917279706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3917279706
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.531409065
Short name T3
Test name
Test status
Simulation time 204105961 ps
CPU time 1.4 seconds
Started Mar 14 12:31:48 PM PDT 24
Finished Mar 14 12:31:49 PM PDT 24
Peak memory 201076 kb
Host smart-e05b4703-b1ea-49e2-802e-ea5e7ce7be39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531409065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.531409065
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.284374158
Short name T51
Test name
Test status
Simulation time 379039428 ps
CPU time 2.57 seconds
Started Mar 14 12:25:42 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 209164 kb
Host smart-f2ced4e6-2cec-4f19-8cab-9d62f9a9742d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284374158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.284374158
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.319180620
Short name T55
Test name
Test status
Simulation time 8883968072 ps
CPU time 13.47 seconds
Started Mar 14 12:31:17 PM PDT 24
Finished Mar 14 12:31:31 PM PDT 24
Peak memory 217856 kb
Host smart-a68dd8bc-1731-4953-9e25-7d4df7680900
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319180620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.319180620
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1298103877
Short name T26
Test name
Test status
Simulation time 146859306 ps
CPU time 1.86 seconds
Started Mar 14 12:31:48 PM PDT 24
Finished Mar 14 12:31:50 PM PDT 24
Peak memory 200732 kb
Host smart-4c257983-f958-4a5d-92ae-3e457669a0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298103877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1298103877
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.748627594
Short name T8
Test name
Test status
Simulation time 2355225946 ps
CPU time 9.15 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:39 PM PDT 24
Peak memory 222636 kb
Host smart-2835192b-9155-424d-9051-f3f467b77cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748627594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.748627594
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3252821842
Short name T54
Test name
Test status
Simulation time 896333487 ps
CPU time 3.19 seconds
Started Mar 14 12:25:53 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 200916 kb
Host smart-1fcba6da-586e-4d0b-b715-483ee5437c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252821842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3252821842
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2635713752
Short name T160
Test name
Test status
Simulation time 80859725 ps
CPU time 0.82 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:25 PM PDT 24
Peak memory 200612 kb
Host smart-b7c1606e-7185-417c-9cdb-867b454e82af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635713752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2635713752
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1137563245
Short name T94
Test name
Test status
Simulation time 65316208 ps
CPU time 0.75 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 200680 kb
Host smart-71a975e2-1a15-4530-a2b1-bc9d65e94679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137563245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1137563245
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2353893108
Short name T42
Test name
Test status
Simulation time 1219713889 ps
CPU time 5.58 seconds
Started Mar 14 12:32:19 PM PDT 24
Finished Mar 14 12:32:25 PM PDT 24
Peak memory 218328 kb
Host smart-665e946d-731d-48fe-857b-4dd40100b2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353893108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2353893108
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1373103725
Short name T148
Test name
Test status
Simulation time 96999243 ps
CPU time 1.01 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 200840 kb
Host smart-c2a295c1-579c-4dd9-bf46-006421759b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373103725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1373103725
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.916849970
Short name T91
Test name
Test status
Simulation time 3028630037 ps
CPU time 15.17 seconds
Started Mar 14 12:31:51 PM PDT 24
Finished Mar 14 12:32:06 PM PDT 24
Peak memory 209380 kb
Host smart-fd7badd7-e976-4aa8-a50b-0ae47298f541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916849970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.916849970
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2967570932
Short name T121
Test name
Test status
Simulation time 463125109 ps
CPU time 1.97 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:35 PM PDT 24
Peak memory 200872 kb
Host smart-c7341c32-97ba-4731-9cad-2847bc84870d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967570932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2967570932
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.281857463
Short name T12
Test name
Test status
Simulation time 1892421987 ps
CPU time 6.68 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:39 PM PDT 24
Peak memory 217496 kb
Host smart-6db7721f-3eda-468c-82c2-afa4f278f1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281857463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.281857463
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3288282409
Short name T198
Test name
Test status
Simulation time 69372223 ps
CPU time 0.75 seconds
Started Mar 14 12:31:23 PM PDT 24
Finished Mar 14 12:31:24 PM PDT 24
Peak memory 200752 kb
Host smart-8635ee15-1d2a-4a9d-9bc4-6e8206aa46e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288282409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3288282409
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1094371011
Short name T105
Test name
Test status
Simulation time 629695610 ps
CPU time 3.85 seconds
Started Mar 14 12:25:15 PM PDT 24
Finished Mar 14 12:25:20 PM PDT 24
Peak memory 209172 kb
Host smart-f589d514-9219-4ca7-81d8-44b8c0ed328a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094371011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1094371011
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3957976312
Short name T83
Test name
Test status
Simulation time 973793678 ps
CPU time 3.34 seconds
Started Mar 14 12:21:28 PM PDT 24
Finished Mar 14 12:21:31 PM PDT 24
Peak memory 201028 kb
Host smart-cc48c08b-2195-4bf1-bab0-8ce50b18975b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957976312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3957976312
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3815898835
Short name T11
Test name
Test status
Simulation time 154038269 ps
CPU time 0.83 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 200636 kb
Host smart-d84efae0-d94c-420d-89f3-4274eeb25322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815898835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3815898835
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.747185332
Short name T82
Test name
Test status
Simulation time 466236987 ps
CPU time 2.01 seconds
Started Mar 14 12:25:30 PM PDT 24
Finished Mar 14 12:25:32 PM PDT 24
Peak memory 201124 kb
Host smart-f5f37e93-c610-41b6-a940-da02c25a05c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747185332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.747185332
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.736730151
Short name T103
Test name
Test status
Simulation time 879963126 ps
CPU time 2.9 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:36 PM PDT 24
Peak memory 200908 kb
Host smart-4be9feec-3965-4c98-a552-87e5be926730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736730151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
736730151
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2217217146
Short name T591
Test name
Test status
Simulation time 455320083 ps
CPU time 2.81 seconds
Started Mar 14 12:21:19 PM PDT 24
Finished Mar 14 12:21:23 PM PDT 24
Peak memory 201052 kb
Host smart-2b12a73d-655a-4e2f-8b8b-8b8a5bbe6721
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217217146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
217217146
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3689226022
Short name T590
Test name
Test status
Simulation time 796416647 ps
CPU time 4.63 seconds
Started Mar 14 12:23:18 PM PDT 24
Finished Mar 14 12:23:24 PM PDT 24
Peak memory 198896 kb
Host smart-0064338f-b225-4b4a-8d25-e4aa8334ec65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689226022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
689226022
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3964213569
Short name T101
Test name
Test status
Simulation time 98069739 ps
CPU time 0.86 seconds
Started Mar 14 12:22:39 PM PDT 24
Finished Mar 14 12:22:40 PM PDT 24
Peak memory 200812 kb
Host smart-c071f19d-4bc5-42bb-ad62-97c985052301
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964213569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
964213569
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2428173613
Short name T582
Test name
Test status
Simulation time 182243344 ps
CPU time 1.17 seconds
Started Mar 14 12:24:55 PM PDT 24
Finished Mar 14 12:24:57 PM PDT 24
Peak memory 199480 kb
Host smart-98fabb12-fd5f-4677-a6e7-da83022bf244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428173613 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2428173613
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1432644593
Short name T620
Test name
Test status
Simulation time 58783026 ps
CPU time 0.72 seconds
Started Mar 14 12:19:34 PM PDT 24
Finished Mar 14 12:19:35 PM PDT 24
Peak memory 200808 kb
Host smart-ffca44f0-eff6-4ce0-8bf0-88b2389c7fa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432644593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1432644593
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4044601370
Short name T99
Test name
Test status
Simulation time 249078272 ps
CPU time 1.55 seconds
Started Mar 14 12:20:00 PM PDT 24
Finished Mar 14 12:20:02 PM PDT 24
Peak memory 200984 kb
Host smart-10bb0566-3a98-4eec-918c-543bb4c6cd61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044601370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.4044601370
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2474614068
Short name T579
Test name
Test status
Simulation time 224994834 ps
CPU time 1.67 seconds
Started Mar 14 12:24:26 PM PDT 24
Finished Mar 14 12:24:28 PM PDT 24
Peak memory 208304 kb
Host smart-443ef1d8-9bcc-4d84-9866-efb1868f6661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474614068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2474614068
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2380826744
Short name T584
Test name
Test status
Simulation time 957080645 ps
CPU time 3.07 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:37 PM PDT 24
Peak memory 200956 kb
Host smart-5800bbb9-96d5-4a5a-bb27-8f099024ce40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380826744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2380826744
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.616488198
Short name T123
Test name
Test status
Simulation time 225398131 ps
CPU time 1.61 seconds
Started Mar 14 12:19:44 PM PDT 24
Finished Mar 14 12:19:46 PM PDT 24
Peak memory 200996 kb
Host smart-19867b50-fca9-4abc-9ffb-790b66ded1f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616488198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.616488198
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3751695678
Short name T609
Test name
Test status
Simulation time 2322891198 ps
CPU time 9.91 seconds
Started Mar 14 12:19:41 PM PDT 24
Finished Mar 14 12:19:51 PM PDT 24
Peak memory 200996 kb
Host smart-8621761d-adce-4564-aad6-224145a45694
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751695678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
751695678
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3287171911
Short name T594
Test name
Test status
Simulation time 92749113 ps
CPU time 0.77 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:34 PM PDT 24
Peak memory 200684 kb
Host smart-b5909712-7cb9-4542-a5d3-34c49018df82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287171911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
287171911
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2016564699
Short name T567
Test name
Test status
Simulation time 156232984 ps
CPU time 1.21 seconds
Started Mar 14 12:23:30 PM PDT 24
Finished Mar 14 12:23:31 PM PDT 24
Peak memory 208856 kb
Host smart-f9ab530b-8a02-4a67-b1c1-4241c8661519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016564699 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2016564699
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2617828591
Short name T587
Test name
Test status
Simulation time 55067233 ps
CPU time 0.81 seconds
Started Mar 14 12:19:12 PM PDT 24
Finished Mar 14 12:19:13 PM PDT 24
Peak memory 200676 kb
Host smart-3348fab5-283a-4e91-a9b7-1a7562b7b270
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617828591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2617828591
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3971566505
Short name T97
Test name
Test status
Simulation time 82370331 ps
CPU time 0.92 seconds
Started Mar 14 12:23:46 PM PDT 24
Finished Mar 14 12:23:47 PM PDT 24
Peak memory 200396 kb
Host smart-e3c85689-8a49-4d46-a30c-9c7ef24c8f59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971566505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3971566505
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3926055336
Short name T581
Test name
Test status
Simulation time 121158630 ps
CPU time 1.55 seconds
Started Mar 14 12:23:58 PM PDT 24
Finished Mar 14 12:23:59 PM PDT 24
Peak memory 211612 kb
Host smart-776fd7a1-9338-4a0f-a2f2-e34c144be1ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926055336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3926055336
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2924466111
Short name T120
Test name
Test status
Simulation time 879083208 ps
CPU time 3.01 seconds
Started Mar 14 12:24:57 PM PDT 24
Finished Mar 14 12:25:00 PM PDT 24
Peak memory 200016 kb
Host smart-84ae41ef-360f-470e-9e86-057299ba7805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924466111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2924466111
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3356146213
Short name T550
Test name
Test status
Simulation time 203036011 ps
CPU time 1.19 seconds
Started Mar 14 12:25:27 PM PDT 24
Finished Mar 14 12:25:28 PM PDT 24
Peak memory 200952 kb
Host smart-4fa9d242-ef17-48fe-8d9b-c2e5b69de887
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356146213 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3356146213
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1708252537
Short name T124
Test name
Test status
Simulation time 83154078 ps
CPU time 0.84 seconds
Started Mar 14 12:25:26 PM PDT 24
Finished Mar 14 12:25:27 PM PDT 24
Peak memory 200704 kb
Host smart-7a6b0b6f-c788-44ba-82f8-7003159d4e88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708252537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1708252537
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2976964423
Short name T552
Test name
Test status
Simulation time 224692287 ps
CPU time 1.44 seconds
Started Mar 14 12:25:12 PM PDT 24
Finished Mar 14 12:25:14 PM PDT 24
Peak memory 200900 kb
Host smart-e4f68cbc-de21-4c7d-964e-625efac10543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976964423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2976964423
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3240083855
Short name T602
Test name
Test status
Simulation time 187869400 ps
CPU time 2.64 seconds
Started Mar 14 12:25:26 PM PDT 24
Finished Mar 14 12:25:29 PM PDT 24
Peak memory 209240 kb
Host smart-524345f0-1ab9-4b04-adde-1913b7a8b7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240083855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3240083855
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4112726999
Short name T557
Test name
Test status
Simulation time 504489537 ps
CPU time 1.88 seconds
Started Mar 14 12:25:25 PM PDT 24
Finished Mar 14 12:25:27 PM PDT 24
Peak memory 200908 kb
Host smart-939b59c8-7c66-446d-b370-c6d155bd68f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112726999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.4112726999
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3705869118
Short name T560
Test name
Test status
Simulation time 154024515 ps
CPU time 1.53 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 209032 kb
Host smart-edbb9cf8-2e1f-4d82-a4be-777b28b431c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705869118 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3705869118
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3716493990
Short name T596
Test name
Test status
Simulation time 74161931 ps
CPU time 0.8 seconds
Started Mar 14 12:25:31 PM PDT 24
Finished Mar 14 12:25:32 PM PDT 24
Peak memory 200648 kb
Host smart-97bc1f78-032d-40f2-b51a-0d434a86c8f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716493990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3716493990
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2475159604
Short name T100
Test name
Test status
Simulation time 227732002 ps
CPU time 1.51 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 200908 kb
Host smart-f82c2d82-96da-49bd-986f-1b5d024de6ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475159604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2475159604
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.903088367
Short name T574
Test name
Test status
Simulation time 156569807 ps
CPU time 1.4 seconds
Started Mar 14 12:25:44 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 209052 kb
Host smart-532da7fb-12bf-4aec-b79b-0534d8832e21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903088367 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.903088367
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2649411854
Short name T598
Test name
Test status
Simulation time 68786168 ps
CPU time 0.73 seconds
Started Mar 14 12:25:40 PM PDT 24
Finished Mar 14 12:25:41 PM PDT 24
Peak memory 200656 kb
Host smart-db0c4e6a-1a40-4eb7-8e6e-0fffc0d293a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649411854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2649411854
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2355826919
Short name T575
Test name
Test status
Simulation time 121287871 ps
CPU time 1.05 seconds
Started Mar 14 12:25:30 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 200768 kb
Host smart-f5207a3b-d018-4c8a-b86f-3c9b46fbc8f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355826919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2355826919
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4209885040
Short name T561
Test name
Test status
Simulation time 199984672 ps
CPU time 2.7 seconds
Started Mar 14 12:25:23 PM PDT 24
Finished Mar 14 12:25:26 PM PDT 24
Peak memory 209140 kb
Host smart-7747f8f0-246f-4d92-ac0a-b3b288fe58c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209885040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4209885040
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3976600140
Short name T119
Test name
Test status
Simulation time 807782971 ps
CPU time 2.66 seconds
Started Mar 14 12:25:34 PM PDT 24
Finished Mar 14 12:25:37 PM PDT 24
Peak memory 200956 kb
Host smart-c3b37316-757c-4dff-9fef-5deb6c15a249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976600140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3976600140
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2579062483
Short name T569
Test name
Test status
Simulation time 189361958 ps
CPU time 1.72 seconds
Started Mar 14 12:25:38 PM PDT 24
Finished Mar 14 12:25:40 PM PDT 24
Peak memory 209104 kb
Host smart-1d6d466b-2ff1-42a0-805c-a7170a03bc17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579062483 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2579062483
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3460418920
Short name T89
Test name
Test status
Simulation time 72361906 ps
CPU time 0.76 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:42 PM PDT 24
Peak memory 200684 kb
Host smart-4a7ba248-038f-483f-b578-a7b9e18b04b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460418920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3460418920
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2037280294
Short name T96
Test name
Test status
Simulation time 201530975 ps
CPU time 1.43 seconds
Started Mar 14 12:25:57 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 200960 kb
Host smart-30054b0e-062e-4ec0-bd15-54983333650a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037280294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2037280294
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.744069364
Short name T604
Test name
Test status
Simulation time 176106803 ps
CPU time 2.45 seconds
Started Mar 14 12:25:30 PM PDT 24
Finished Mar 14 12:25:32 PM PDT 24
Peak memory 212820 kb
Host smart-3cd2b509-11b2-4d69-8c4f-9f10388320c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744069364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.744069364
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2640814595
Short name T576
Test name
Test status
Simulation time 167946994 ps
CPU time 1.14 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:42 PM PDT 24
Peak memory 210212 kb
Host smart-7ead848e-2ecf-457d-9c0a-6399378e0eb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640814595 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2640814595
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3214460201
Short name T619
Test name
Test status
Simulation time 70081396 ps
CPU time 0.79 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 200720 kb
Host smart-db3b1786-e719-4e8f-a8db-9511b00a13f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214460201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3214460201
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1479218730
Short name T610
Test name
Test status
Simulation time 127693746 ps
CPU time 1.05 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 200756 kb
Host smart-4cc3f0b3-bbd6-4061-8a73-9aa8cf995f49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479218730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1479218730
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3834541277
Short name T555
Test name
Test status
Simulation time 610574125 ps
CPU time 4.5 seconds
Started Mar 14 12:25:26 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 217248 kb
Host smart-2f4dfc2e-bef3-4f44-b03d-caf7890d6ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834541277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3834541277
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2145730292
Short name T558
Test name
Test status
Simulation time 424036599 ps
CPU time 1.84 seconds
Started Mar 14 12:25:38 PM PDT 24
Finished Mar 14 12:25:40 PM PDT 24
Peak memory 200860 kb
Host smart-93d2370f-11c7-44cf-afd0-1192280a4d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145730292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2145730292
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.141885918
Short name T554
Test name
Test status
Simulation time 126397513 ps
CPU time 0.98 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 200736 kb
Host smart-a5452ba4-1c21-4d58-be42-14a3ed1bbf20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141885918 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.141885918
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3939783332
Short name T98
Test name
Test status
Simulation time 137160374 ps
CPU time 1.33 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 200908 kb
Host smart-8f13750c-82ab-4840-95d7-4f817123838c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939783332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3939783332
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2214667007
Short name T612
Test name
Test status
Simulation time 495876189 ps
CPU time 1.92 seconds
Started Mar 14 12:25:32 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 200896 kb
Host smart-40222056-b23e-4c59-9f8a-95bf5a14367c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214667007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2214667007
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2328618795
Short name T77
Test name
Test status
Simulation time 107409973 ps
CPU time 1.14 seconds
Started Mar 14 12:25:29 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 208956 kb
Host smart-d746df30-27ce-4db1-b2b6-2115f3339b76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328618795 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2328618795
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1988506543
Short name T599
Test name
Test status
Simulation time 70580994 ps
CPU time 0.82 seconds
Started Mar 14 12:25:49 PM PDT 24
Finished Mar 14 12:25:50 PM PDT 24
Peak memory 200708 kb
Host smart-930e4eb0-f5c9-47bb-9209-7802ab2a2fdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988506543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1988506543
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2163888926
Short name T571
Test name
Test status
Simulation time 246071594 ps
CPU time 1.4 seconds
Started Mar 14 12:25:39 PM PDT 24
Finished Mar 14 12:25:40 PM PDT 24
Peak memory 200956 kb
Host smart-5d42b633-b173-44a8-8929-965ad24aecaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163888926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2163888926
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2994519351
Short name T81
Test name
Test status
Simulation time 208156853 ps
CPU time 1.58 seconds
Started Mar 14 12:25:26 PM PDT 24
Finished Mar 14 12:25:28 PM PDT 24
Peak memory 209140 kb
Host smart-56fd3f1f-5549-4139-910e-97ea9ee89762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994519351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2994519351
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.4132285512
Short name T618
Test name
Test status
Simulation time 101162766 ps
CPU time 1 seconds
Started Mar 14 12:25:31 PM PDT 24
Finished Mar 14 12:25:32 PM PDT 24
Peak memory 200848 kb
Host smart-0d0d4edc-8e6c-4a60-baba-9de9421ac14e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132285512 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.4132285512
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2109955704
Short name T546
Test name
Test status
Simulation time 63158843 ps
CPU time 0.75 seconds
Started Mar 14 12:25:23 PM PDT 24
Finished Mar 14 12:25:24 PM PDT 24
Peak memory 200700 kb
Host smart-76dade34-450f-4925-a371-4fbfbcbc54a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109955704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2109955704
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2909719682
Short name T50
Test name
Test status
Simulation time 180149238 ps
CPU time 1.45 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 200856 kb
Host smart-4b783399-b5ba-468c-9523-e67afadb600b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909719682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2909719682
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1858127488
Short name T564
Test name
Test status
Simulation time 324856879 ps
CPU time 2.38 seconds
Started Mar 14 12:25:29 PM PDT 24
Finished Mar 14 12:25:32 PM PDT 24
Peak memory 209112 kb
Host smart-6bf150a3-13ba-4b7c-b5c2-a37e4b717e39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858127488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1858127488
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3059234564
Short name T553
Test name
Test status
Simulation time 443245438 ps
CPU time 1.74 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 200832 kb
Host smart-0a312c07-565d-4075-ab01-2c1ecf8fd5e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059234564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3059234564
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2712507244
Short name T548
Test name
Test status
Simulation time 136121250 ps
CPU time 1.03 seconds
Started Mar 14 12:25:29 PM PDT 24
Finished Mar 14 12:25:30 PM PDT 24
Peak memory 200828 kb
Host smart-33e88764-c484-4b8c-8df5-24adb8bcd729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712507244 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2712507244
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.718253213
Short name T547
Test name
Test status
Simulation time 66790006 ps
CPU time 0.75 seconds
Started Mar 14 12:25:29 PM PDT 24
Finished Mar 14 12:25:29 PM PDT 24
Peak memory 200648 kb
Host smart-971736f7-4458-46e9-9e7d-a759005e5b83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718253213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.718253213
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3383538610
Short name T49
Test name
Test status
Simulation time 149111130 ps
CPU time 1.12 seconds
Started Mar 14 12:25:38 PM PDT 24
Finished Mar 14 12:25:40 PM PDT 24
Peak memory 200708 kb
Host smart-111a4822-213c-4674-a09d-0026048b136f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383538610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3383538610
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1277939738
Short name T600
Test name
Test status
Simulation time 558741417 ps
CPU time 4 seconds
Started Mar 14 12:25:25 PM PDT 24
Finished Mar 14 12:25:29 PM PDT 24
Peak memory 200884 kb
Host smart-c9719210-c070-4fe4-8985-874479269270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277939738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1277939738
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1781474339
Short name T122
Test name
Test status
Simulation time 484404092 ps
CPU time 1.91 seconds
Started Mar 14 12:25:40 PM PDT 24
Finished Mar 14 12:25:42 PM PDT 24
Peak memory 200908 kb
Host smart-79684d3b-17f5-40ad-a647-1f82cb9662a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781474339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1781474339
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4095495989
Short name T76
Test name
Test status
Simulation time 165694407 ps
CPU time 1.47 seconds
Started Mar 14 12:25:28 PM PDT 24
Finished Mar 14 12:25:30 PM PDT 24
Peak memory 214264 kb
Host smart-51c1999f-51b6-47f9-8a75-03e9f173f426
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095495989 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4095495989
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2913932402
Short name T556
Test name
Test status
Simulation time 60862908 ps
CPU time 0.74 seconds
Started Mar 14 12:25:30 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 200776 kb
Host smart-33241284-75bf-4f7f-a593-5d9017a4c0d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913932402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2913932402
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3715057422
Short name T583
Test name
Test status
Simulation time 105708198 ps
CPU time 1.25 seconds
Started Mar 14 12:25:49 PM PDT 24
Finished Mar 14 12:25:50 PM PDT 24
Peak memory 200868 kb
Host smart-144be9b9-8800-4ffb-9c5f-fb70fca2161d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715057422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3715057422
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3871711089
Short name T563
Test name
Test status
Simulation time 184451973 ps
CPU time 2.62 seconds
Started Mar 14 12:25:44 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 209224 kb
Host smart-868cfeb6-5970-41d8-9371-a6ac80b6d83b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871711089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3871711089
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2615096188
Short name T614
Test name
Test status
Simulation time 471663182 ps
CPU time 1.96 seconds
Started Mar 14 12:25:36 PM PDT 24
Finished Mar 14 12:25:38 PM PDT 24
Peak memory 200964 kb
Host smart-b6e6bed5-52cc-4d40-8a5e-dfb28dc465bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615096188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2615096188
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3985649415
Short name T566
Test name
Test status
Simulation time 470043744 ps
CPU time 2.74 seconds
Started Mar 14 12:25:18 PM PDT 24
Finished Mar 14 12:25:21 PM PDT 24
Peak memory 200816 kb
Host smart-a8d07019-97c5-4bfc-ada0-8f34a01181ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985649415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
985649415
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1768154924
Short name T545
Test name
Test status
Simulation time 482166423 ps
CPU time 5.6 seconds
Started Mar 14 12:25:18 PM PDT 24
Finished Mar 14 12:25:24 PM PDT 24
Peak memory 200800 kb
Host smart-1e004aa4-89fb-46b2-8d61-2fe14f088278
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768154924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
768154924
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4289628094
Short name T593
Test name
Test status
Simulation time 102740344 ps
CPU time 0.87 seconds
Started Mar 14 12:22:15 PM PDT 24
Finished Mar 14 12:22:17 PM PDT 24
Peak memory 200704 kb
Host smart-9524b204-dbac-459f-bbd4-171118813481
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289628094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4
289628094
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2808913535
Short name T595
Test name
Test status
Simulation time 175774371 ps
CPU time 1.19 seconds
Started Mar 14 12:25:17 PM PDT 24
Finished Mar 14 12:25:19 PM PDT 24
Peak memory 208980 kb
Host smart-5d37b2fa-a50f-45de-8b23-a230f5a4c74d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808913535 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2808913535
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3846133626
Short name T577
Test name
Test status
Simulation time 73688794 ps
CPU time 0.79 seconds
Started Mar 14 12:23:41 PM PDT 24
Finished Mar 14 12:23:42 PM PDT 24
Peak memory 200056 kb
Host smart-3bad4da8-f964-4661-91d0-8444e1781983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846133626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3846133626
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2420517461
Short name T589
Test name
Test status
Simulation time 110483958 ps
CPU time 1.15 seconds
Started Mar 14 12:25:15 PM PDT 24
Finished Mar 14 12:25:16 PM PDT 24
Peak memory 200904 kb
Host smart-77d10dc2-41fe-4599-8ee2-73b5c94090d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420517461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2420517461
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2608065477
Short name T605
Test name
Test status
Simulation time 299482224 ps
CPU time 2.16 seconds
Started Mar 14 12:21:45 PM PDT 24
Finished Mar 14 12:21:48 PM PDT 24
Peak memory 209244 kb
Host smart-2eeb6679-b005-4bed-9318-5bd65d8f9480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608065477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2608065477
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4124281579
Short name T573
Test name
Test status
Simulation time 356038620 ps
CPU time 2.24 seconds
Started Mar 14 12:25:15 PM PDT 24
Finished Mar 14 12:25:17 PM PDT 24
Peak memory 200852 kb
Host smart-22d49288-911b-4b7b-bfaf-9088cb9bdf1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124281579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
124281579
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1576366253
Short name T565
Test name
Test status
Simulation time 272819285 ps
CPU time 3.26 seconds
Started Mar 14 12:25:13 PM PDT 24
Finished Mar 14 12:25:17 PM PDT 24
Peak memory 200936 kb
Host smart-4fdabf53-4491-4897-88e7-75c09711d934
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576366253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
576366253
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4595741
Short name T616
Test name
Test status
Simulation time 114360035 ps
CPU time 0.92 seconds
Started Mar 14 12:25:01 PM PDT 24
Finished Mar 14 12:25:02 PM PDT 24
Peak memory 200692 kb
Host smart-be48b1a8-7a41-4fd8-8b60-28afb9a87bd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4595741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4595741
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1466906009
Short name T52
Test name
Test status
Simulation time 125784727 ps
CPU time 0.94 seconds
Started Mar 14 12:25:17 PM PDT 24
Finished Mar 14 12:25:18 PM PDT 24
Peak memory 200784 kb
Host smart-f2cd5377-5d1f-4621-8993-084e6f6861db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466906009 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1466906009
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4113361916
Short name T570
Test name
Test status
Simulation time 83124680 ps
CPU time 0.82 seconds
Started Mar 14 12:25:01 PM PDT 24
Finished Mar 14 12:25:02 PM PDT 24
Peak memory 200704 kb
Host smart-c7bef14d-1719-4ae2-9ebf-82d4d115e868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113361916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4113361916
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3344554988
Short name T607
Test name
Test status
Simulation time 130278725 ps
CPU time 1.12 seconds
Started Mar 14 12:25:15 PM PDT 24
Finished Mar 14 12:25:17 PM PDT 24
Peak memory 200712 kb
Host smart-45956b9f-1076-42ee-8ee7-dde2ddeb38ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344554988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3344554988
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.996374449
Short name T78
Test name
Test status
Simulation time 259620852 ps
CPU time 2.06 seconds
Started Mar 14 12:25:29 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 211500 kb
Host smart-793aa9ec-5fdc-4316-9694-7d7e848c8918
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996374449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.996374449
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2075611264
Short name T617
Test name
Test status
Simulation time 486410891 ps
CPU time 1.84 seconds
Started Mar 14 12:25:13 PM PDT 24
Finished Mar 14 12:25:15 PM PDT 24
Peak memory 200872 kb
Host smart-1e546ebd-7f33-4567-8a43-deed831ad9fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075611264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2075611264
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1667577658
Short name T613
Test name
Test status
Simulation time 358155529 ps
CPU time 2.38 seconds
Started Mar 14 12:25:11 PM PDT 24
Finished Mar 14 12:25:14 PM PDT 24
Peak memory 209020 kb
Host smart-1fdad476-8419-46b2-9cce-a71721248ece
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667577658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
667577658
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2546556711
Short name T102
Test name
Test status
Simulation time 1537910666 ps
CPU time 7.65 seconds
Started Mar 14 12:25:14 PM PDT 24
Finished Mar 14 12:25:22 PM PDT 24
Peak memory 200780 kb
Host smart-04d9f892-cd1e-47e3-967b-3546635e6de0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546556711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
546556711
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.718100331
Short name T549
Test name
Test status
Simulation time 139658191 ps
CPU time 0.96 seconds
Started Mar 14 12:25:25 PM PDT 24
Finished Mar 14 12:25:26 PM PDT 24
Peak memory 200700 kb
Host smart-6c34816b-0ae3-4f57-b713-e415b032a2a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718100331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.718100331
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.466674714
Short name T559
Test name
Test status
Simulation time 112871979 ps
CPU time 1.09 seconds
Started Mar 14 12:25:20 PM PDT 24
Finished Mar 14 12:25:22 PM PDT 24
Peak memory 208936 kb
Host smart-dfafc81e-ac54-4d51-b827-36149fa85ed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466674714 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.466674714
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3412535321
Short name T572
Test name
Test status
Simulation time 68456175 ps
CPU time 0.75 seconds
Started Mar 14 12:25:19 PM PDT 24
Finished Mar 14 12:25:20 PM PDT 24
Peak memory 200616 kb
Host smart-c0791b1f-8397-4141-909c-c957fed8d54e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412535321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3412535321
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3557368706
Short name T578
Test name
Test status
Simulation time 87568352 ps
CPU time 0.94 seconds
Started Mar 14 12:25:11 PM PDT 24
Finished Mar 14 12:25:12 PM PDT 24
Peak memory 200672 kb
Host smart-84124387-ccdf-44fb-94af-025d51158b06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557368706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3557368706
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2359568176
Short name T580
Test name
Test status
Simulation time 274822984 ps
CPU time 2.16 seconds
Started Mar 14 12:25:29 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 211152 kb
Host smart-5b44f4ba-1f71-4d54-a0e2-e1a374ecaaf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359568176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2359568176
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2661703797
Short name T104
Test name
Test status
Simulation time 473987387 ps
CPU time 1.75 seconds
Started Mar 14 12:25:16 PM PDT 24
Finished Mar 14 12:25:19 PM PDT 24
Peak memory 200972 kb
Host smart-97eeade7-2c0d-4c07-b4c7-5bc0470b8a87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661703797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2661703797
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3276011395
Short name T592
Test name
Test status
Simulation time 130070203 ps
CPU time 1.03 seconds
Started Mar 14 12:25:28 PM PDT 24
Finished Mar 14 12:25:29 PM PDT 24
Peak memory 200896 kb
Host smart-5f512ae1-b727-4eae-9ee6-919f8eb95edc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276011395 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3276011395
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2496102806
Short name T601
Test name
Test status
Simulation time 94245299 ps
CPU time 0.92 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 200572 kb
Host smart-f1bea52e-9835-4c3e-b900-85761211022c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496102806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2496102806
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3603453798
Short name T615
Test name
Test status
Simulation time 146908809 ps
CPU time 1.11 seconds
Started Mar 14 12:25:45 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 200732 kb
Host smart-8c765219-70dc-4f67-bc6d-828d9e9b55c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603453798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3603453798
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3158612557
Short name T585
Test name
Test status
Simulation time 215902530 ps
CPU time 1.57 seconds
Started Mar 14 12:25:22 PM PDT 24
Finished Mar 14 12:25:24 PM PDT 24
Peak memory 211576 kb
Host smart-4d649638-bf09-469c-bbe2-5eeb994dab1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158612557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3158612557
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3671264173
Short name T84
Test name
Test status
Simulation time 498817463 ps
CPU time 2 seconds
Started Mar 14 12:25:26 PM PDT 24
Finished Mar 14 12:25:28 PM PDT 24
Peak memory 200948 kb
Host smart-cd24ceaa-6a05-4ff3-a56c-8829fd19425d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671264173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3671264173
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2580409460
Short name T59
Test name
Test status
Simulation time 170406917 ps
CPU time 1.67 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:47 PM PDT 24
Peak memory 209220 kb
Host smart-f4b7dfcf-5bba-48dc-9c58-395cf251f42b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580409460 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2580409460
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4187214789
Short name T603
Test name
Test status
Simulation time 64914802 ps
CPU time 0.76 seconds
Started Mar 14 12:25:38 PM PDT 24
Finished Mar 14 12:25:39 PM PDT 24
Peak memory 200608 kb
Host smart-a35cfac2-0dd8-4a1b-a0ab-f4fd2db2d5c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187214789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.4187214789
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4093389579
Short name T48
Test name
Test status
Simulation time 201164920 ps
CPU time 1.51 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 200920 kb
Host smart-c3fdc073-c268-41c6-80a2-55908db800fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093389579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.4093389579
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.853126139
Short name T611
Test name
Test status
Simulation time 433956483 ps
CPU time 2.88 seconds
Started Mar 14 12:25:28 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 217376 kb
Host smart-54535cbd-dc83-48cb-9ce7-7a38dd399032
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853126139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.853126139
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1564331486
Short name T608
Test name
Test status
Simulation time 139206186 ps
CPU time 1.43 seconds
Started Mar 14 12:25:18 PM PDT 24
Finished Mar 14 12:25:20 PM PDT 24
Peak memory 209188 kb
Host smart-11d415b0-f0b4-4f3a-95b5-b98b857f7334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564331486 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1564331486
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.132861836
Short name T597
Test name
Test status
Simulation time 87564942 ps
CPU time 0.83 seconds
Started Mar 14 12:25:32 PM PDT 24
Finished Mar 14 12:25:33 PM PDT 24
Peak memory 200720 kb
Host smart-d247de33-989f-4198-a868-9e2ca5782af6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132861836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.132861836
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3329403572
Short name T588
Test name
Test status
Simulation time 228735834 ps
CPU time 1.5 seconds
Started Mar 14 12:25:23 PM PDT 24
Finished Mar 14 12:25:25 PM PDT 24
Peak memory 200936 kb
Host smart-955958c6-aa54-4dc5-a6c6-9d0ac1334bb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329403572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3329403572
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4057205865
Short name T80
Test name
Test status
Simulation time 104107051 ps
CPU time 1.4 seconds
Started Mar 14 12:25:35 PM PDT 24
Finished Mar 14 12:25:36 PM PDT 24
Peak memory 209168 kb
Host smart-b60bdd34-6eee-4c01-9ac9-30aabe0551bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057205865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4057205865
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3641631314
Short name T606
Test name
Test status
Simulation time 777127576 ps
CPU time 2.87 seconds
Started Mar 14 12:25:22 PM PDT 24
Finished Mar 14 12:25:25 PM PDT 24
Peak memory 200888 kb
Host smart-52b14982-fcf8-4857-a359-51a34b15e0ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641631314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3641631314
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1955228982
Short name T562
Test name
Test status
Simulation time 122414761 ps
CPU time 0.93 seconds
Started Mar 14 12:25:48 PM PDT 24
Finished Mar 14 12:25:49 PM PDT 24
Peak memory 200764 kb
Host smart-b2d69307-219f-4ed5-b629-fd8cb9ad7642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955228982 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1955228982
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.604144351
Short name T551
Test name
Test status
Simulation time 82024162 ps
CPU time 0.84 seconds
Started Mar 14 12:25:27 PM PDT 24
Finished Mar 14 12:25:28 PM PDT 24
Peak memory 200816 kb
Host smart-f261c01f-6468-444a-929f-9ebc26277198
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604144351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.604144351
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1215240630
Short name T95
Test name
Test status
Simulation time 146536073 ps
CPU time 1.03 seconds
Started Mar 14 12:25:38 PM PDT 24
Finished Mar 14 12:25:39 PM PDT 24
Peak memory 200776 kb
Host smart-5c0a1bd9-8482-435c-b70e-11a91ee14f77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215240630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1215240630
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2672153778
Short name T108
Test name
Test status
Simulation time 132158961 ps
CPU time 1.81 seconds
Started Mar 14 12:25:29 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 209176 kb
Host smart-df8c7ab3-23c8-44b7-849d-9fcddf79fdb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672153778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2672153778
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1181337610
Short name T107
Test name
Test status
Simulation time 933339504 ps
CPU time 3.49 seconds
Started Mar 14 12:25:34 PM PDT 24
Finished Mar 14 12:25:38 PM PDT 24
Peak memory 200972 kb
Host smart-e562acee-de16-448e-946b-ea02c1f3b02d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181337610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1181337610
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.973570262
Short name T79
Test name
Test status
Simulation time 102993821 ps
CPU time 0.93 seconds
Started Mar 14 12:25:35 PM PDT 24
Finished Mar 14 12:25:36 PM PDT 24
Peak memory 200772 kb
Host smart-e1832c7e-cd05-4039-91c1-87375e1d8fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973570262 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.973570262
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2174380416
Short name T586
Test name
Test status
Simulation time 57609582 ps
CPU time 0.74 seconds
Started Mar 14 12:25:25 PM PDT 24
Finished Mar 14 12:25:26 PM PDT 24
Peak memory 200696 kb
Host smart-ac0e20fd-3231-4306-8450-56b57b74b9ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174380416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2174380416
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1706053645
Short name T568
Test name
Test status
Simulation time 238406284 ps
CPU time 1.5 seconds
Started Mar 14 12:25:36 PM PDT 24
Finished Mar 14 12:25:37 PM PDT 24
Peak memory 200912 kb
Host smart-c73e286b-4c76-4fc1-a45b-05804a2fc53c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706053645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1706053645
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2665905622
Short name T53
Test name
Test status
Simulation time 505744581 ps
CPU time 3.48 seconds
Started Mar 14 12:25:56 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 212852 kb
Host smart-0f92a87b-4645-481b-8a30-b6b960e09337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665905622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2665905622
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2021350107
Short name T106
Test name
Test status
Simulation time 869794510 ps
CPU time 2.99 seconds
Started Mar 14 12:25:34 PM PDT 24
Finished Mar 14 12:25:37 PM PDT 24
Peak memory 201012 kb
Host smart-0a858479-c9fe-472b-9737-1e2a1a35f41a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021350107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2021350107
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.556978932
Short name T45
Test name
Test status
Simulation time 1223659067 ps
CPU time 5.78 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 218020 kb
Host smart-f74988e9-8d3e-4b39-891d-66edaeba9e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556978932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.556978932
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.255221667
Short name T414
Test name
Test status
Simulation time 244332805 ps
CPU time 1.15 seconds
Started Mar 14 12:31:23 PM PDT 24
Finished Mar 14 12:31:24 PM PDT 24
Peak memory 218004 kb
Host smart-bf115d8e-b63b-4a4d-86ae-113b135983be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255221667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.255221667
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3219824595
Short name T477
Test name
Test status
Simulation time 198613675 ps
CPU time 0.86 seconds
Started Mar 14 12:31:23 PM PDT 24
Finished Mar 14 12:31:24 PM PDT 24
Peak memory 200548 kb
Host smart-4be9e628-730f-4441-94c8-7a9aef81e921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219824595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3219824595
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.520085991
Short name T63
Test name
Test status
Simulation time 734709865 ps
CPU time 3.97 seconds
Started Mar 14 12:31:07 PM PDT 24
Finished Mar 14 12:31:11 PM PDT 24
Peak memory 200936 kb
Host smart-f122c106-f7a8-4c03-a786-9cbb597db96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520085991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.520085991
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2759100150
Short name T236
Test name
Test status
Simulation time 173541244 ps
CPU time 1.26 seconds
Started Mar 14 12:31:00 PM PDT 24
Finished Mar 14 12:31:01 PM PDT 24
Peak memory 200828 kb
Host smart-0df7752f-5de3-4d9e-ae25-79b2422413c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759100150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2759100150
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.163343604
Short name T532
Test name
Test status
Simulation time 203325320 ps
CPU time 1.41 seconds
Started Mar 14 12:31:13 PM PDT 24
Finished Mar 14 12:31:15 PM PDT 24
Peak memory 200988 kb
Host smart-aa942a07-50c5-4245-a083-7a8ed1f5b4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163343604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.163343604
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1414593319
Short name T519
Test name
Test status
Simulation time 1985999653 ps
CPU time 9.21 seconds
Started Mar 14 12:31:22 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 209264 kb
Host smart-6dcc5426-403f-419a-904d-5a363946a970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414593319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1414593319
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.4146057675
Short name T470
Test name
Test status
Simulation time 117233131 ps
CPU time 1.42 seconds
Started Mar 14 12:31:20 PM PDT 24
Finished Mar 14 12:31:21 PM PDT 24
Peak memory 200752 kb
Host smart-76aaa841-236a-4d44-81db-12f3d9736482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146057675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4146057675
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4073994653
Short name T4
Test name
Test status
Simulation time 78692794 ps
CPU time 0.79 seconds
Started Mar 14 12:31:05 PM PDT 24
Finished Mar 14 12:31:06 PM PDT 24
Peak memory 200584 kb
Host smart-ee16f287-5e63-4b07-a164-6502be67d7da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073994653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4073994653
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.4127241737
Short name T36
Test name
Test status
Simulation time 1907762201 ps
CPU time 6.92 seconds
Started Mar 14 12:31:00 PM PDT 24
Finished Mar 14 12:31:08 PM PDT 24
Peak memory 218020 kb
Host smart-a74803fa-77ea-4a71-adc3-a5956e578eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127241737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4127241737
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.854326556
Short name T484
Test name
Test status
Simulation time 244610863 ps
CPU time 1.03 seconds
Started Mar 14 12:31:03 PM PDT 24
Finished Mar 14 12:31:04 PM PDT 24
Peak memory 218008 kb
Host smart-2ac280b4-9769-4b34-a934-617e76ed3a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854326556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.854326556
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.4255805841
Short name T452
Test name
Test status
Simulation time 80732073 ps
CPU time 0.77 seconds
Started Mar 14 12:31:21 PM PDT 24
Finished Mar 14 12:31:21 PM PDT 24
Peak memory 200544 kb
Host smart-ffe2e785-3dc8-486c-a63e-67c6e043bd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255805841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.4255805841
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1849243917
Short name T296
Test name
Test status
Simulation time 1221417987 ps
CPU time 4.99 seconds
Started Mar 14 12:31:09 PM PDT 24
Finished Mar 14 12:31:14 PM PDT 24
Peak memory 200944 kb
Host smart-1a0d0228-5ea7-4b36-a2be-deb1b0503555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849243917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1849243917
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2282484621
Short name T56
Test name
Test status
Simulation time 16521613486 ps
CPU time 27.73 seconds
Started Mar 14 12:31:17 PM PDT 24
Finished Mar 14 12:31:45 PM PDT 24
Peak memory 218620 kb
Host smart-cee29a28-fe8d-4c8c-86d3-95764f5b726e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282484621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2282484621
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1790094556
Short name T260
Test name
Test status
Simulation time 148912368 ps
CPU time 1.23 seconds
Started Mar 14 12:31:11 PM PDT 24
Finished Mar 14 12:31:13 PM PDT 24
Peak memory 200748 kb
Host smart-ceb23e67-9b76-482d-b2d1-cc9a96a19ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790094556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1790094556
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.4116878301
Short name T137
Test name
Test status
Simulation time 193860171 ps
CPU time 1.4 seconds
Started Mar 14 12:31:20 PM PDT 24
Finished Mar 14 12:31:21 PM PDT 24
Peak memory 200904 kb
Host smart-ba81b87e-8419-4898-a771-0ac49b7ed976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116878301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4116878301
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2909467155
Short name T141
Test name
Test status
Simulation time 7240051792 ps
CPU time 27.54 seconds
Started Mar 14 12:31:23 PM PDT 24
Finished Mar 14 12:31:51 PM PDT 24
Peak memory 201136 kb
Host smart-1bb407dc-78a3-487b-99a4-50fe41e36a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909467155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2909467155
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3994627977
Short name T487
Test name
Test status
Simulation time 130073072 ps
CPU time 1.55 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 208932 kb
Host smart-04a97110-af49-4b16-a828-f54a22497c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994627977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3994627977
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.490265684
Short name T154
Test name
Test status
Simulation time 114191230 ps
CPU time 1.07 seconds
Started Mar 14 12:31:19 PM PDT 24
Finished Mar 14 12:31:20 PM PDT 24
Peak memory 200736 kb
Host smart-161f9a2b-cee9-4dfb-9411-c02b0cb3177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490265684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.490265684
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3978575232
Short name T229
Test name
Test status
Simulation time 74780581 ps
CPU time 0.84 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 200564 kb
Host smart-f7a4b737-458a-4fb2-9f26-46f4954384bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978575232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3978575232
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.945676740
Short name T280
Test name
Test status
Simulation time 2358476245 ps
CPU time 9.24 seconds
Started Mar 14 12:31:26 PM PDT 24
Finished Mar 14 12:31:36 PM PDT 24
Peak memory 222588 kb
Host smart-2565e565-c3f6-4ec1-aa77-1ac562ed25f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945676740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.945676740
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.967457755
Short name T140
Test name
Test status
Simulation time 244408006 ps
CPU time 1.09 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 218168 kb
Host smart-33de5c35-7ba2-4787-b290-0cddf43eab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967457755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.967457755
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.138355662
Short name T456
Test name
Test status
Simulation time 1020999490 ps
CPU time 5.55 seconds
Started Mar 14 12:31:37 PM PDT 24
Finished Mar 14 12:31:43 PM PDT 24
Peak memory 201072 kb
Host smart-d5ccc5d4-b8c3-4ecf-a63b-5f79a8341db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138355662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.138355662
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1773375844
Short name T471
Test name
Test status
Simulation time 156649593 ps
CPU time 1.15 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 200756 kb
Host smart-736411dd-3d2e-4ea5-a4a0-18754ed15aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773375844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1773375844
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2292645416
Short name T533
Test name
Test status
Simulation time 190024591 ps
CPU time 1.44 seconds
Started Mar 14 12:31:29 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 201000 kb
Host smart-1ed5a44b-743c-4ed8-b411-cac235a334d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292645416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2292645416
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2568565430
Short name T195
Test name
Test status
Simulation time 5625585316 ps
CPU time 20.21 seconds
Started Mar 14 12:31:29 PM PDT 24
Finished Mar 14 12:31:50 PM PDT 24
Peak memory 201108 kb
Host smart-4316fd45-1175-4e9e-9a8d-26a67862e386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568565430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2568565430
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2195026908
Short name T288
Test name
Test status
Simulation time 262243413 ps
CPU time 1.82 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 200752 kb
Host smart-f1a8fb8f-8011-4938-89a6-60687808ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195026908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2195026908
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3303465078
Short name T289
Test name
Test status
Simulation time 80784000 ps
CPU time 0.9 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:25 PM PDT 24
Peak memory 200732 kb
Host smart-1b4b00d1-14eb-447d-b778-02eb854db8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303465078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3303465078
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2155446453
Short name T438
Test name
Test status
Simulation time 93702659 ps
CPU time 0.81 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:28 PM PDT 24
Peak memory 200668 kb
Host smart-2d038ce4-a478-4b16-86f6-7ed95948bb42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155446453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2155446453
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.84409271
Short name T44
Test name
Test status
Simulation time 2360753464 ps
CPU time 8.09 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:39 PM PDT 24
Peak memory 217896 kb
Host smart-a185829f-1c85-4860-b51e-2689b0ede1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84409271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.84409271
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.109766442
Short name T455
Test name
Test status
Simulation time 244615661 ps
CPU time 1.03 seconds
Started Mar 14 12:31:29 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 218040 kb
Host smart-ee89236e-678f-46ab-9f23-207364ee30fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109766442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.109766442
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.951509865
Short name T422
Test name
Test status
Simulation time 240983548 ps
CPU time 1.03 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 200548 kb
Host smart-ab939984-cb9a-4562-8441-4c99cc65dc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951509865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.951509865
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4112826472
Short name T439
Test name
Test status
Simulation time 1154950310 ps
CPU time 4.89 seconds
Started Mar 14 12:31:29 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 201068 kb
Host smart-1efdcf34-17c8-4020-b7a7-3696a99e7708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112826472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4112826472
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2143491524
Short name T125
Test name
Test status
Simulation time 109736538 ps
CPU time 1.03 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 200844 kb
Host smart-5565705b-d1cc-4a1c-aaed-e487a999059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143491524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2143491524
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.757865424
Short name T234
Test name
Test status
Simulation time 225654344 ps
CPU time 1.49 seconds
Started Mar 14 12:31:26 PM PDT 24
Finished Mar 14 12:31:27 PM PDT 24
Peak memory 200876 kb
Host smart-a099c89c-44aa-42cf-a872-f9f41b51967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757865424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.757865424
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1500837507
Short name T109
Test name
Test status
Simulation time 2148513174 ps
CPU time 8.45 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:40 PM PDT 24
Peak memory 209220 kb
Host smart-38ee1f5d-a5d5-41a4-a16c-b929c560bf57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500837507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1500837507
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3182550507
Short name T488
Test name
Test status
Simulation time 140790338 ps
CPU time 1.77 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200792 kb
Host smart-8ac2465c-b1ce-4bc5-8f1e-d51154a08670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182550507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3182550507
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.410030506
Short name T474
Test name
Test status
Simulation time 219981774 ps
CPU time 1.34 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:28 PM PDT 24
Peak memory 200796 kb
Host smart-c962d42d-35be-4200-b6f0-8790a3bdbc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410030506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.410030506
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1059271065
Short name T364
Test name
Test status
Simulation time 71871303 ps
CPU time 0.76 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:28 PM PDT 24
Peak memory 200496 kb
Host smart-2f4ccdef-d21d-40c6-b767-0b9fd0aaba07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059271065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1059271065
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3768850662
Short name T301
Test name
Test status
Simulation time 1894665009 ps
CPU time 7.2 seconds
Started Mar 14 12:31:25 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 218424 kb
Host smart-129bba48-f430-4f77-a305-6aa40d6827a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768850662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3768850662
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2796429360
Short name T497
Test name
Test status
Simulation time 246699805 ps
CPU time 1.01 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 218068 kb
Host smart-fc042af2-6706-4761-b5db-a8561f1ce7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796429360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2796429360
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1064986664
Short name T299
Test name
Test status
Simulation time 90779791 ps
CPU time 0.79 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 200648 kb
Host smart-73b59b56-d90f-4930-8acf-7804acaddabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064986664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1064986664
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2163546175
Short name T306
Test name
Test status
Simulation time 938208323 ps
CPU time 4.23 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:28 PM PDT 24
Peak memory 200972 kb
Host smart-deebb7b1-4979-44ae-ae3f-6f846cec7bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163546175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2163546175
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2379358978
Short name T345
Test name
Test status
Simulation time 99944462 ps
CPU time 0.99 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 200816 kb
Host smart-d567d80c-540f-4619-b3c6-129a04121213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379358978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2379358978
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.696231636
Short name T321
Test name
Test status
Simulation time 114788813 ps
CPU time 1.14 seconds
Started Mar 14 12:31:25 PM PDT 24
Finished Mar 14 12:31:26 PM PDT 24
Peak memory 201028 kb
Host smart-383ef6a3-61aa-4f80-83a8-deb0a81ce661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696231636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.696231636
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3558419400
Short name T230
Test name
Test status
Simulation time 2790634027 ps
CPU time 11.99 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:45 PM PDT 24
Peak memory 209408 kb
Host smart-a4203600-a46f-48c9-b09f-c9a37115e01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558419400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3558419400
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.291865119
Short name T385
Test name
Test status
Simulation time 127414469 ps
CPU time 1.73 seconds
Started Mar 14 12:31:34 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 209152 kb
Host smart-0decb5c7-b9ba-41ed-a528-af7f8e53d940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291865119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.291865119
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2031511639
Short name T128
Test name
Test status
Simulation time 169041808 ps
CPU time 1.18 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 200884 kb
Host smart-c16f8a01-4953-42a4-9974-9006a978793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031511639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2031511639
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3019241055
Short name T240
Test name
Test status
Simulation time 69581738 ps
CPU time 0.8 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200548 kb
Host smart-458cdeb9-854f-4e8f-98eb-a1dd394f15e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019241055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3019241055
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2451312867
Short name T244
Test name
Test status
Simulation time 1227756424 ps
CPU time 5.57 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:37 PM PDT 24
Peak memory 222656 kb
Host smart-d8a4ea83-8315-4b32-93fa-81b35fd7b0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451312867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2451312867
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2691445375
Short name T353
Test name
Test status
Simulation time 243982100 ps
CPU time 1.14 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 217988 kb
Host smart-c8f0e9ab-2a64-4908-b92a-9c6f671c5a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691445375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2691445375
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1005974778
Short name T176
Test name
Test status
Simulation time 133822436 ps
CPU time 0.82 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200548 kb
Host smart-1818494d-84c7-4f5c-b7d3-8a5b1f8c92b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005974778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1005974778
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1987819741
Short name T183
Test name
Test status
Simulation time 1113118862 ps
CPU time 5.14 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 201032 kb
Host smart-2ee40bde-ba6c-43b0-8169-b404de3cc0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987819741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1987819741
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1148810198
Short name T436
Test name
Test status
Simulation time 183147529 ps
CPU time 1.16 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 200812 kb
Host smart-853df24c-bf25-40bf-abc0-2d3534f425dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148810198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1148810198
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2167248534
Short name T285
Test name
Test status
Simulation time 195064419 ps
CPU time 1.4 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 201016 kb
Host smart-ad176dbf-3517-474d-b0d9-34afc8a81c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167248534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2167248534
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2421191958
Short name T238
Test name
Test status
Simulation time 12368376340 ps
CPU time 41.72 seconds
Started Mar 14 12:31:25 PM PDT 24
Finished Mar 14 12:32:07 PM PDT 24
Peak memory 201128 kb
Host smart-cdd28aad-6e4c-4d1b-9f42-58c52599d9b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421191958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2421191958
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3640527373
Short name T186
Test name
Test status
Simulation time 136664980 ps
CPU time 1.69 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200740 kb
Host smart-92e4f041-96c7-4b15-b196-9a8da1d7fef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640527373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3640527373
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.940206229
Short name T271
Test name
Test status
Simulation time 227456180 ps
CPU time 1.33 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200832 kb
Host smart-4e80c7bc-38a7-4179-9f55-5b8d88e8c8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940206229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.940206229
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3011917962
Short name T210
Test name
Test status
Simulation time 70485744 ps
CPU time 0.74 seconds
Started Mar 14 12:31:34 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 200688 kb
Host smart-4aa62a08-c156-4f98-a5de-74d91036e749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011917962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3011917962
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1126627385
Short name T400
Test name
Test status
Simulation time 243875383 ps
CPU time 1.21 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:31 PM PDT 24
Peak memory 218064 kb
Host smart-d1329da1-9c0a-48f0-bdf3-c4527b92eaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126627385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1126627385
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.464804042
Short name T15
Test name
Test status
Simulation time 84824029 ps
CPU time 0.74 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:38 PM PDT 24
Peak memory 200656 kb
Host smart-23b7d9dd-1d16-41c4-b284-cd478a5b8358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464804042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.464804042
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1032605325
Short name T112
Test name
Test status
Simulation time 2008511516 ps
CPU time 6.81 seconds
Started Mar 14 12:31:43 PM PDT 24
Finished Mar 14 12:31:54 PM PDT 24
Peak memory 201088 kb
Host smart-cd243273-7ad2-4b07-b203-106aecb96a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032605325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1032605325
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1432092561
Short name T214
Test name
Test status
Simulation time 110446554 ps
CPU time 0.98 seconds
Started Mar 14 12:31:41 PM PDT 24
Finished Mar 14 12:31:42 PM PDT 24
Peak memory 200896 kb
Host smart-49d189ba-33ef-4d69-9ad2-87949a45fdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432092561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1432092561
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3273600628
Short name T251
Test name
Test status
Simulation time 120946373 ps
CPU time 1.22 seconds
Started Mar 14 12:31:34 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 201112 kb
Host smart-e688419b-9b1a-463a-9777-85d7da94cff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273600628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3273600628
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2873178314
Short name T427
Test name
Test status
Simulation time 10940418280 ps
CPU time 37.5 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:32:09 PM PDT 24
Peak memory 209244 kb
Host smart-146cd129-7359-4854-a6c0-4652d04f218e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873178314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2873178314
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2099285126
Short name T506
Test name
Test status
Simulation time 476032867 ps
CPU time 2.42 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 200800 kb
Host smart-0bf3d880-1c34-47f8-bdc5-e45eb8d8ce03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099285126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2099285126
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1788156851
Short name T314
Test name
Test status
Simulation time 208285342 ps
CPU time 1.21 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 200888 kb
Host smart-b408c106-1f43-47c8-a847-bfba672248e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788156851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1788156851
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3997744741
Short name T67
Test name
Test status
Simulation time 98690721 ps
CPU time 0.88 seconds
Started Mar 14 12:31:36 PM PDT 24
Finished Mar 14 12:31:37 PM PDT 24
Peak memory 200692 kb
Host smart-a7f49b4f-589e-4ec7-8a5d-c2ca938848ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997744741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3997744741
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.4106503453
Short name T440
Test name
Test status
Simulation time 1227117868 ps
CPU time 5.52 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:38 PM PDT 24
Peak memory 222656 kb
Host smart-ad385ffa-dbee-42f0-95b8-1437b3aa2c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106503453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4106503453
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2757213499
Short name T367
Test name
Test status
Simulation time 244576114 ps
CPU time 1.08 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 217988 kb
Host smart-f90e801f-528e-40dc-b1ae-782df06fc8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757213499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2757213499
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1969690043
Short name T252
Test name
Test status
Simulation time 217822240 ps
CPU time 0.88 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200688 kb
Host smart-71cfaf19-26cf-480b-91d0-30e5644fb837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969690043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1969690043
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3533352284
Short name T92
Test name
Test status
Simulation time 875623423 ps
CPU time 4.56 seconds
Started Mar 14 12:31:36 PM PDT 24
Finished Mar 14 12:31:41 PM PDT 24
Peak memory 201104 kb
Host smart-0f15aed4-eeb0-4263-a239-06a4031c6451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533352284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3533352284
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1411232310
Short name T505
Test name
Test status
Simulation time 180040807 ps
CPU time 1.15 seconds
Started Mar 14 12:31:38 PM PDT 24
Finished Mar 14 12:31:39 PM PDT 24
Peak memory 200896 kb
Host smart-ef31ecd7-d66c-4976-9c97-24caed942fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411232310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1411232310
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3199010741
Short name T520
Test name
Test status
Simulation time 246951840 ps
CPU time 1.42 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 201064 kb
Host smart-aaf94cf8-5edd-4c11-9edb-34dcd02d08e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199010741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3199010741
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1607255510
Short name T421
Test name
Test status
Simulation time 2873095949 ps
CPU time 13.38 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:47 PM PDT 24
Peak memory 209248 kb
Host smart-e639e909-2ecc-4d9a-8a5b-cef9b30df9e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607255510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1607255510
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2954642429
Short name T139
Test name
Test status
Simulation time 268748893 ps
CPU time 1.78 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200784 kb
Host smart-269b2335-37d0-44ea-9878-3a4a453fc3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954642429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2954642429
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2634150385
Short name T350
Test name
Test status
Simulation time 243911022 ps
CPU time 1.37 seconds
Started Mar 14 12:31:48 PM PDT 24
Finished Mar 14 12:31:50 PM PDT 24
Peak memory 201108 kb
Host smart-420f2cc4-b159-4087-be61-157d64743611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634150385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2634150385
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3834758222
Short name T185
Test name
Test status
Simulation time 83038954 ps
CPU time 0.82 seconds
Started Mar 14 12:31:53 PM PDT 24
Finished Mar 14 12:31:54 PM PDT 24
Peak memory 200668 kb
Host smart-5bef801d-957e-48ea-8f01-37cb2fc9657f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834758222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3834758222
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.947468688
Short name T492
Test name
Test status
Simulation time 2353169588 ps
CPU time 8 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:39 PM PDT 24
Peak memory 218588 kb
Host smart-342359d6-1ed8-46bb-8cc1-260ebee68804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947468688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.947468688
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1320639495
Short name T144
Test name
Test status
Simulation time 245041464 ps
CPU time 1.09 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 218220 kb
Host smart-ca2b25f4-e84d-4e48-a154-c8b16c3bfd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320639495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1320639495
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2309942859
Short name T425
Test name
Test status
Simulation time 176733576 ps
CPU time 0.87 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 200528 kb
Host smart-364ba039-c68d-4f66-8d92-0fcbf1d9d350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309942859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2309942859
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3311367410
Short name T460
Test name
Test status
Simulation time 1424213449 ps
CPU time 5.46 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:39 PM PDT 24
Peak memory 200968 kb
Host smart-af78bb57-6e6a-4910-998f-77c77ddfbd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311367410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3311367410
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2416522017
Short name T249
Test name
Test status
Simulation time 104455210 ps
CPU time 1 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 200744 kb
Host smart-ad0d0447-ee58-4768-9954-10aac958a8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416522017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2416522017
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.933569966
Short name T316
Test name
Test status
Simulation time 194570642 ps
CPU time 1.31 seconds
Started Mar 14 12:31:36 PM PDT 24
Finished Mar 14 12:31:37 PM PDT 24
Peak memory 201072 kb
Host smart-c6c14128-3daf-4d73-8908-61e6b46b088a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933569966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.933569966
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3158872418
Short name T126
Test name
Test status
Simulation time 4878871252 ps
CPU time 18.14 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:51 PM PDT 24
Peak memory 209372 kb
Host smart-9665d71b-a1d4-4da7-8b71-9f631c2ba1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158872418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3158872418
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3886427159
Short name T524
Test name
Test status
Simulation time 495913123 ps
CPU time 2.64 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:36 PM PDT 24
Peak memory 200744 kb
Host smart-2d55f8ef-b2d1-46aa-8173-b0ec8eb78d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886427159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3886427159
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3967253896
Short name T211
Test name
Test status
Simulation time 140788258 ps
CPU time 1.05 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 200740 kb
Host smart-0fe4c06e-5768-4c6f-a98e-10fd57382b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967253896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3967253896
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3437820936
Short name T47
Test name
Test status
Simulation time 77525022 ps
CPU time 0.78 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 200656 kb
Host smart-57733a15-3309-4399-ba48-1c59ad48df2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437820936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3437820936
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2121405952
Short name T437
Test name
Test status
Simulation time 1884553360 ps
CPU time 6.78 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:37 PM PDT 24
Peak memory 222628 kb
Host smart-cd951981-d947-4106-b3ce-65b3dc12c1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121405952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2121405952
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.423646974
Short name T302
Test name
Test status
Simulation time 244540161 ps
CPU time 1.05 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 218120 kb
Host smart-bb4232e8-62e7-4884-ad89-64e9b043ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423646974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.423646974
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3219333370
Short name T472
Test name
Test status
Simulation time 117734461 ps
CPU time 0.81 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 200676 kb
Host smart-1a77fe45-f709-46aa-8bf0-749a375ec018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219333370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3219333370
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.966943509
Short name T70
Test name
Test status
Simulation time 918047647 ps
CPU time 3.98 seconds
Started Mar 14 12:31:26 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 200856 kb
Host smart-47ae588e-46ff-47d8-a8d4-001c9a52ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966943509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.966943509
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3575622841
Short name T259
Test name
Test status
Simulation time 161535704 ps
CPU time 1.11 seconds
Started Mar 14 12:32:11 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 200684 kb
Host smart-b50b4629-c4fd-40d1-92a0-368ce0df6c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575622841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3575622841
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1477848118
Short name T372
Test name
Test status
Simulation time 260237104 ps
CPU time 1.6 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200972 kb
Host smart-d1d809c4-e173-43b5-9c63-704c7008a464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477848118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1477848118
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2359467338
Short name T435
Test name
Test status
Simulation time 9104519048 ps
CPU time 31.68 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 209248 kb
Host smart-1d117b40-29f3-4d55-ab0d-1267ce58a5cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359467338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2359467338
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2795695380
Short name T164
Test name
Test status
Simulation time 329459865 ps
CPU time 1.95 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200780 kb
Host smart-5ad307e1-c4b2-4949-870d-754f97803b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795695380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2795695380
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.67210970
Short name T327
Test name
Test status
Simulation time 175152363 ps
CPU time 1.33 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:28 PM PDT 24
Peak memory 200932 kb
Host smart-dc06d8d9-02f7-4417-ae29-3740d65c3fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67210970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.67210970
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1026181658
Short name T162
Test name
Test status
Simulation time 70065542 ps
CPU time 0.81 seconds
Started Mar 14 12:31:26 PM PDT 24
Finished Mar 14 12:31:27 PM PDT 24
Peak memory 200704 kb
Host smart-4456e781-d79b-4c19-a4a2-b4cda3679c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026181658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1026181658
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.325925974
Short name T268
Test name
Test status
Simulation time 1230498427 ps
CPU time 5.36 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:39 PM PDT 24
Peak memory 222048 kb
Host smart-4dffba09-b6f8-450e-81f4-07b2e8414a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325925974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.325925974
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2135130251
Short name T130
Test name
Test status
Simulation time 243662272 ps
CPU time 1.12 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 217960 kb
Host smart-0ac8cca5-049c-4926-a1a1-f499623a29e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135130251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2135130251
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.140711051
Short name T351
Test name
Test status
Simulation time 159948084 ps
CPU time 0.83 seconds
Started Mar 14 12:31:35 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 200656 kb
Host smart-ffde1ab1-d64c-4548-8011-082494e1fd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140711051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.140711051
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.4231930264
Short name T182
Test name
Test status
Simulation time 1264296337 ps
CPU time 5.15 seconds
Started Mar 14 12:31:36 PM PDT 24
Finished Mar 14 12:31:42 PM PDT 24
Peak memory 201044 kb
Host smart-72843ab5-d139-439a-a0cf-18c8036f31d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231930264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.4231930264
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.482484534
Short name T194
Test name
Test status
Simulation time 104122027 ps
CPU time 1.04 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 200816 kb
Host smart-c96db93a-a47b-4bb6-82c6-b784de263487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482484534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.482484534
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3037627319
Short name T397
Test name
Test status
Simulation time 196991427 ps
CPU time 1.43 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200928 kb
Host smart-e65fd660-5590-418e-90cf-861cf90512ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037627319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3037627319
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1300217152
Short name T93
Test name
Test status
Simulation time 2933768129 ps
CPU time 14.3 seconds
Started Mar 14 12:31:57 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 201356 kb
Host smart-a78be9a3-67b7-4550-8bc4-124a0f3faad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300217152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1300217152
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1014534603
Short name T282
Test name
Test status
Simulation time 125536578 ps
CPU time 1.6 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 208812 kb
Host smart-e8854c0a-38aa-4869-96ca-d88dc8015a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014534603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1014534603
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1467529761
Short name T212
Test name
Test status
Simulation time 236994104 ps
CPU time 1.45 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 200740 kb
Host smart-f8274bf4-4774-4866-ad16-f381626ac944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467529761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1467529761
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.514935646
Short name T222
Test name
Test status
Simulation time 57533929 ps
CPU time 0.74 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200688 kb
Host smart-1d0e4917-931e-4cde-89d6-c7739e342536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514935646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.514935646
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3304738991
Short name T428
Test name
Test status
Simulation time 2345999130 ps
CPU time 8.64 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:39 PM PDT 24
Peak memory 222364 kb
Host smart-6c3944ee-9c95-4cdd-823a-b666ea818f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304738991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3304738991
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1982475037
Short name T368
Test name
Test status
Simulation time 243860692 ps
CPU time 1.01 seconds
Started Mar 14 12:31:48 PM PDT 24
Finished Mar 14 12:31:49 PM PDT 24
Peak memory 218144 kb
Host smart-92a46d11-def0-4ddf-af26-bb6029017e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982475037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1982475037
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3086993853
Short name T393
Test name
Test status
Simulation time 100781408 ps
CPU time 0.81 seconds
Started Mar 14 12:31:41 PM PDT 24
Finished Mar 14 12:31:42 PM PDT 24
Peak memory 200492 kb
Host smart-e3f5ac8f-8c75-47b2-9127-16379149aeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086993853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3086993853
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3872951986
Short name T464
Test name
Test status
Simulation time 1704079724 ps
CPU time 6.09 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:39 PM PDT 24
Peak memory 201072 kb
Host smart-5cfff0d6-4355-418f-927d-462aa5c9b8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872951986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3872951986
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1708079286
Short name T294
Test name
Test status
Simulation time 178742404 ps
CPU time 1.24 seconds
Started Mar 14 12:31:26 PM PDT 24
Finished Mar 14 12:31:27 PM PDT 24
Peak memory 200832 kb
Host smart-f670bdb3-c500-46d2-8765-ad8980d1afd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708079286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1708079286
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2776356569
Short name T509
Test name
Test status
Simulation time 205567599 ps
CPU time 1.42 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 201052 kb
Host smart-a29c0358-fa5e-4b81-a01a-b3c70a066f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776356569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2776356569
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.404791847
Short name T253
Test name
Test status
Simulation time 5804525921 ps
CPU time 20.98 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:52 PM PDT 24
Peak memory 201176 kb
Host smart-f31d516f-a37d-429c-89f0-51f0b67a6251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404791847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.404791847
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2885885642
Short name T279
Test name
Test status
Simulation time 146486989 ps
CPU time 1.83 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200852 kb
Host smart-4e9f1e76-ab5d-4a7e-b5e8-00aedb5ee556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885885642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2885885642
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.425170722
Short name T149
Test name
Test status
Simulation time 140483722 ps
CPU time 1.01 seconds
Started Mar 14 12:31:44 PM PDT 24
Finished Mar 14 12:31:45 PM PDT 24
Peak memory 200880 kb
Host smart-e7ad8992-79dd-4783-9c16-496696f6d4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425170722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.425170722
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4059020736
Short name T329
Test name
Test status
Simulation time 81063156 ps
CPU time 0.75 seconds
Started Mar 14 12:31:06 PM PDT 24
Finished Mar 14 12:31:07 PM PDT 24
Peak memory 200704 kb
Host smart-c70a20ad-9823-4d4f-8a56-d78c800a60d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059020736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4059020736
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1897206631
Short name T516
Test name
Test status
Simulation time 1224076252 ps
CPU time 5.88 seconds
Started Mar 14 12:31:07 PM PDT 24
Finished Mar 14 12:31:13 PM PDT 24
Peak memory 217916 kb
Host smart-f65d45f6-d57f-4552-a74d-54d88e91627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897206631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1897206631
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.302873566
Short name T489
Test name
Test status
Simulation time 243445508 ps
CPU time 1.13 seconds
Started Mar 14 12:31:25 PM PDT 24
Finished Mar 14 12:31:26 PM PDT 24
Peak memory 217948 kb
Host smart-f9a3a7b8-0b13-4ac6-9b66-bd0749308c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302873566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.302873566
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2106206714
Short name T459
Test name
Test status
Simulation time 136159879 ps
CPU time 0.8 seconds
Started Mar 14 12:31:19 PM PDT 24
Finished Mar 14 12:31:20 PM PDT 24
Peak memory 200592 kb
Host smart-af1d3caf-07a0-46a5-9342-d6016e954fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106206714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2106206714
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2545993229
Short name T522
Test name
Test status
Simulation time 1029048613 ps
CPU time 4.66 seconds
Started Mar 14 12:31:25 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 201084 kb
Host smart-48475f8b-a6e2-40cc-8e9d-b8d6fdb75a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545993229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2545993229
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.932022405
Short name T61
Test name
Test status
Simulation time 17821330581 ps
CPU time 27.16 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:51 PM PDT 24
Peak memory 217868 kb
Host smart-6a6b3aea-b0f2-4e0d-b3fd-a92cb2ba5545
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932022405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.932022405
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1014882966
Short name T263
Test name
Test status
Simulation time 152948492 ps
CPU time 1.06 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200796 kb
Host smart-e3393ce2-3670-4e23-b919-0cae768e6f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014882966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1014882966
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.642319732
Short name T219
Test name
Test status
Simulation time 115396815 ps
CPU time 1.23 seconds
Started Mar 14 12:31:09 PM PDT 24
Finished Mar 14 12:31:11 PM PDT 24
Peak memory 200976 kb
Host smart-8cc7a1a6-9955-44c8-8b28-61bc23919ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642319732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.642319732
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1086463676
Short name T72
Test name
Test status
Simulation time 5237988749 ps
CPU time 17.54 seconds
Started Mar 14 12:31:32 PM PDT 24
Finished Mar 14 12:31:49 PM PDT 24
Peak memory 201048 kb
Host smart-5f80a61e-47cf-4322-889e-e7b1fd211880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086463676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1086463676
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2031186019
Short name T536
Test name
Test status
Simulation time 127481102 ps
CPU time 1.6 seconds
Started Mar 14 12:31:20 PM PDT 24
Finished Mar 14 12:31:22 PM PDT 24
Peak memory 208976 kb
Host smart-f5da94d4-dbd5-40af-b137-a24e0d46f9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031186019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2031186019
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2814559545
Short name T202
Test name
Test status
Simulation time 253242604 ps
CPU time 1.5 seconds
Started Mar 14 12:31:01 PM PDT 24
Finished Mar 14 12:31:02 PM PDT 24
Peak memory 200932 kb
Host smart-69cfb04a-5433-46e1-962c-577fa8f8aaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814559545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2814559545
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3271705100
Short name T341
Test name
Test status
Simulation time 94747707 ps
CPU time 0.83 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:31:57 PM PDT 24
Peak memory 200672 kb
Host smart-530c836b-87ac-4690-9f40-8b408de67b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271705100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3271705100
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2921094332
Short name T46
Test name
Test status
Simulation time 1225956877 ps
CPU time 6.04 seconds
Started Mar 14 12:31:34 PM PDT 24
Finished Mar 14 12:31:40 PM PDT 24
Peak memory 218016 kb
Host smart-f0316b6f-526c-4409-9941-a396b6f45025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921094332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2921094332
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.206399634
Short name T257
Test name
Test status
Simulation time 253622698 ps
CPU time 1.04 seconds
Started Mar 14 12:31:37 PM PDT 24
Finished Mar 14 12:31:38 PM PDT 24
Peak memory 218148 kb
Host smart-9bdfd7f3-c200-46c0-bb00-5285582f1fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206399634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.206399634
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1106245617
Short name T14
Test name
Test status
Simulation time 100657297 ps
CPU time 0.8 seconds
Started Mar 14 12:31:26 PM PDT 24
Finished Mar 14 12:31:27 PM PDT 24
Peak memory 200540 kb
Host smart-90294bd9-6480-4d88-b04c-a97f3cc0faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106245617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1106245617
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.112942824
Short name T65
Test name
Test status
Simulation time 1931453572 ps
CPU time 6.63 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 200948 kb
Host smart-99decf4d-bdf1-4159-b0b4-c66d7e0df668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112942824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.112942824
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2624590225
Short name T277
Test name
Test status
Simulation time 170202028 ps
CPU time 1.21 seconds
Started Mar 14 12:31:29 PM PDT 24
Finished Mar 14 12:31:31 PM PDT 24
Peak memory 200880 kb
Host smart-8482b35d-542c-44b8-a820-f1d983f788b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624590225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2624590225
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1915843536
Short name T517
Test name
Test status
Simulation time 203414215 ps
CPU time 1.36 seconds
Started Mar 14 12:31:44 PM PDT 24
Finished Mar 14 12:31:45 PM PDT 24
Peak memory 201008 kb
Host smart-df86fa8d-eb36-4b54-8362-5062baf861e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915843536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1915843536
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.204844801
Short name T504
Test name
Test status
Simulation time 7088553198 ps
CPU time 29.42 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:32:01 PM PDT 24
Peak memory 209348 kb
Host smart-f837f83a-e168-4ee5-bda4-8dd7777b8db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204844801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.204844801
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.596869558
Short name T334
Test name
Test status
Simulation time 345655935 ps
CPU time 2.25 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:36 PM PDT 24
Peak memory 200876 kb
Host smart-428a5d16-cf59-4174-b894-5983a8ad130d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596869558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.596869558
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.58561723
Short name T239
Test name
Test status
Simulation time 79272554 ps
CPU time 0.81 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 200844 kb
Host smart-07e8230a-9075-4263-ada9-ce424e85294d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58561723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.58561723
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1802859058
Short name T226
Test name
Test status
Simulation time 54824988 ps
CPU time 0.73 seconds
Started Mar 14 12:32:07 PM PDT 24
Finished Mar 14 12:32:08 PM PDT 24
Peak memory 200580 kb
Host smart-fb6bcc3f-51d5-4957-8d58-1e86ece38290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802859058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1802859058
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3170563054
Short name T463
Test name
Test status
Simulation time 2161509724 ps
CPU time 8.39 seconds
Started Mar 14 12:31:55 PM PDT 24
Finished Mar 14 12:32:04 PM PDT 24
Peak memory 218152 kb
Host smart-157bfb5d-b1ec-4464-a187-ce112338c4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170563054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3170563054
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3681491290
Short name T473
Test name
Test status
Simulation time 243816811 ps
CPU time 1.21 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 218240 kb
Host smart-f234ecac-a066-41c4-bf1a-88f51e5ed728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681491290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3681491290
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.31936797
Short name T382
Test name
Test status
Simulation time 158902743 ps
CPU time 0.82 seconds
Started Mar 14 12:31:47 PM PDT 24
Finished Mar 14 12:31:48 PM PDT 24
Peak memory 200676 kb
Host smart-a29546db-5b2e-4f1b-965c-a372b800b403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31936797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.31936797
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3376413509
Short name T454
Test name
Test status
Simulation time 942072828 ps
CPU time 4.44 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:19 PM PDT 24
Peak memory 201056 kb
Host smart-27d02e7d-36c8-4458-9424-962037ee8bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376413509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3376413509
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4244447187
Short name T541
Test name
Test status
Simulation time 186749301 ps
CPU time 1.24 seconds
Started Mar 14 12:31:52 PM PDT 24
Finished Mar 14 12:31:54 PM PDT 24
Peak memory 200856 kb
Host smart-77a1d4a8-e11f-40a2-85d4-82af9d56fa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244447187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4244447187
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.301890298
Short name T326
Test name
Test status
Simulation time 116660718 ps
CPU time 1.17 seconds
Started Mar 14 12:31:52 PM PDT 24
Finished Mar 14 12:31:53 PM PDT 24
Peak memory 200944 kb
Host smart-182138f1-02b6-4586-86ed-699bad8efc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301890298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.301890298
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1628802041
Short name T241
Test name
Test status
Simulation time 143662590 ps
CPU time 1.76 seconds
Started Mar 14 12:31:49 PM PDT 24
Finished Mar 14 12:31:50 PM PDT 24
Peak memory 209012 kb
Host smart-035f2d66-1a35-4acb-b013-584d0bf404e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628802041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1628802041
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.349945318
Short name T248
Test name
Test status
Simulation time 143607234 ps
CPU time 1.09 seconds
Started Mar 14 12:32:07 PM PDT 24
Finished Mar 14 12:32:08 PM PDT 24
Peak memory 200752 kb
Host smart-37fe45d3-433b-4d7c-bd13-37c0ed764ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349945318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.349945318
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3543643256
Short name T512
Test name
Test status
Simulation time 83903577 ps
CPU time 0.82 seconds
Started Mar 14 12:31:45 PM PDT 24
Finished Mar 14 12:31:46 PM PDT 24
Peak memory 200636 kb
Host smart-56354c23-837a-4deb-bb60-28ca99616e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543643256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3543643256
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.4255741101
Short name T528
Test name
Test status
Simulation time 1216868399 ps
CPU time 5.32 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:32:02 PM PDT 24
Peak memory 218564 kb
Host smart-581baebb-39ef-4666-8b30-f5d602dbf2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255741101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4255741101
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3348385218
Short name T27
Test name
Test status
Simulation time 244694313 ps
CPU time 1.08 seconds
Started Mar 14 12:31:52 PM PDT 24
Finished Mar 14 12:31:53 PM PDT 24
Peak memory 217936 kb
Host smart-32a43bd5-2c7d-458a-988a-7c871c44825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348385218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3348385218
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3939174952
Short name T18
Test name
Test status
Simulation time 116326046 ps
CPU time 0.78 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 200604 kb
Host smart-0305aee0-ca41-410e-a99c-993653e8143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939174952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3939174952
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2592943108
Short name T462
Test name
Test status
Simulation time 1759577324 ps
CPU time 6.4 seconds
Started Mar 14 12:32:11 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 201020 kb
Host smart-3be234a1-2a05-492d-b159-7afeccc85f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592943108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2592943108
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1644721198
Short name T206
Test name
Test status
Simulation time 104035598 ps
CPU time 0.96 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 200800 kb
Host smart-56df348e-adb9-460e-a053-8cc737e5dedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644721198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1644721198
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2888795631
Short name T526
Test name
Test status
Simulation time 244204128 ps
CPU time 1.5 seconds
Started Mar 14 12:31:46 PM PDT 24
Finished Mar 14 12:31:48 PM PDT 24
Peak memory 201088 kb
Host smart-3ee3c246-05e3-43e3-b716-dd35534b00bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888795631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2888795631
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.831035085
Short name T273
Test name
Test status
Simulation time 7503390447 ps
CPU time 31.96 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:46 PM PDT 24
Peak memory 209392 kb
Host smart-4b35b85e-77d0-4e83-b439-c6e14936ea08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831035085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.831035085
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2717693029
Short name T433
Test name
Test status
Simulation time 370911828 ps
CPU time 2.54 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:09 PM PDT 24
Peak memory 200840 kb
Host smart-156e7a6e-9685-4d67-8be0-a6c89764ed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717693029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2717693029
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.327706034
Short name T391
Test name
Test status
Simulation time 98331081 ps
CPU time 0.86 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:31:57 PM PDT 24
Peak memory 200880 kb
Host smart-70f714a2-0995-4629-9f9b-212755eb1b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327706034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.327706034
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1870097566
Short name T502
Test name
Test status
Simulation time 61995685 ps
CPU time 0.74 seconds
Started Mar 14 12:31:44 PM PDT 24
Finished Mar 14 12:31:45 PM PDT 24
Peak memory 200564 kb
Host smart-60fcb213-e963-4b45-a568-695f68be1b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870097566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1870097566
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1194105809
Short name T490
Test name
Test status
Simulation time 2173299422 ps
CPU time 8.54 seconds
Started Mar 14 12:31:54 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 222768 kb
Host smart-6d5082b8-7a20-42e4-94b0-f44d7e323064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194105809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1194105809
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3577962494
Short name T179
Test name
Test status
Simulation time 243983884 ps
CPU time 1.11 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:31:57 PM PDT 24
Peak memory 217972 kb
Host smart-6d182a83-8530-4ae3-9758-83762ea16cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577962494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3577962494
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2512872509
Short name T381
Test name
Test status
Simulation time 195953800 ps
CPU time 0.9 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:07 PM PDT 24
Peak memory 200612 kb
Host smart-3a55ce74-f8b8-48bf-914a-674f86c74d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512872509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2512872509
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.310486463
Short name T493
Test name
Test status
Simulation time 1531163364 ps
CPU time 5.9 seconds
Started Mar 14 12:31:50 PM PDT 24
Finished Mar 14 12:31:55 PM PDT 24
Peak memory 200924 kb
Host smart-70f85757-2040-4d02-bb00-31b256181187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310486463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.310486463
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.976073030
Short name T507
Test name
Test status
Simulation time 110282908 ps
CPU time 1.01 seconds
Started Mar 14 12:32:07 PM PDT 24
Finished Mar 14 12:32:08 PM PDT 24
Peak memory 200768 kb
Host smart-04b62258-8fcd-4e35-89fc-44397877cb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976073030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.976073030
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.193230623
Short name T336
Test name
Test status
Simulation time 259780468 ps
CPU time 1.53 seconds
Started Mar 14 12:31:55 PM PDT 24
Finished Mar 14 12:31:57 PM PDT 24
Peak memory 201108 kb
Host smart-f3062e56-9185-404f-bbf8-8bb024f8ebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193230623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.193230623
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1222402925
Short name T309
Test name
Test status
Simulation time 2219926613 ps
CPU time 10.39 seconds
Started Mar 14 12:31:48 PM PDT 24
Finished Mar 14 12:31:58 PM PDT 24
Peak memory 201064 kb
Host smart-0f2c9010-f19e-437a-a412-06b73f2863af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222402925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1222402925
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3469257576
Short name T530
Test name
Test status
Simulation time 145195074 ps
CPU time 1.98 seconds
Started Mar 14 12:32:03 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 200880 kb
Host smart-003b9dcb-8504-4dca-825f-22b54ee2aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469257576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3469257576
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.10119055
Short name T135
Test name
Test status
Simulation time 204870598 ps
CPU time 1.25 seconds
Started Mar 14 12:31:40 PM PDT 24
Finished Mar 14 12:31:42 PM PDT 24
Peak memory 200868 kb
Host smart-efc7fa40-1db4-486d-ad91-2daec04d2464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10119055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.10119055
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2297983431
Short name T166
Test name
Test status
Simulation time 59647690 ps
CPU time 0.81 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 200668 kb
Host smart-e88dbf31-b63a-4b9d-bc7d-0c34648597e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297983431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2297983431
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3874698215
Short name T34
Test name
Test status
Simulation time 2169763817 ps
CPU time 7.6 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 218452 kb
Host smart-fff54cb6-df45-4e28-ad08-e0c8cca78c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874698215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3874698215
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.444900511
Short name T390
Test name
Test status
Simulation time 243899179 ps
CPU time 1.08 seconds
Started Mar 14 12:31:43 PM PDT 24
Finished Mar 14 12:31:44 PM PDT 24
Peak memory 217984 kb
Host smart-2f9fe454-8670-4f83-a585-d68da9d8c349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444900511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.444900511
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2121245724
Short name T510
Test name
Test status
Simulation time 125855819 ps
CPU time 0.85 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 200652 kb
Host smart-cf706920-209a-4388-a9cf-a242a8d00716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121245724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2121245724
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2837624886
Short name T255
Test name
Test status
Simulation time 1684703347 ps
CPU time 6.31 seconds
Started Mar 14 12:31:47 PM PDT 24
Finished Mar 14 12:31:53 PM PDT 24
Peak memory 201032 kb
Host smart-6511fe0f-1c13-4ea5-b877-48f5eadd6467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837624886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2837624886
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2217960661
Short name T467
Test name
Test status
Simulation time 159537631 ps
CPU time 1.14 seconds
Started Mar 14 12:31:57 PM PDT 24
Finished Mar 14 12:31:58 PM PDT 24
Peak memory 200888 kb
Host smart-e7b03aff-6d4a-4fb7-8540-f5c2368318a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217960661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2217960661
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2191266380
Short name T276
Test name
Test status
Simulation time 114285891 ps
CPU time 1.16 seconds
Started Mar 14 12:31:55 PM PDT 24
Finished Mar 14 12:31:57 PM PDT 24
Peak memory 201080 kb
Host smart-029f864c-8abc-40c8-905b-6825f82605f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191266380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2191266380
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.958072910
Short name T503
Test name
Test status
Simulation time 17098927512 ps
CPU time 55.84 seconds
Started Mar 14 12:31:48 PM PDT 24
Finished Mar 14 12:32:43 PM PDT 24
Peak memory 209344 kb
Host smart-3b55b5bc-f260-4611-833f-ac7542b6ff7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958072910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.958072910
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1057060922
Short name T416
Test name
Test status
Simulation time 155036703 ps
CPU time 1.05 seconds
Started Mar 14 12:32:10 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 200848 kb
Host smart-2f02098d-3e56-4136-90b0-8e9d059bf8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057060922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1057060922
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.877214934
Short name T529
Test name
Test status
Simulation time 68332077 ps
CPU time 0.76 seconds
Started Mar 14 12:32:00 PM PDT 24
Finished Mar 14 12:32:01 PM PDT 24
Peak memory 200652 kb
Host smart-a0255026-eba4-427d-ba70-ff8abb21e139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877214934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.877214934
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.4194890755
Short name T401
Test name
Test status
Simulation time 1225925118 ps
CPU time 5.33 seconds
Started Mar 14 12:31:54 PM PDT 24
Finished Mar 14 12:32:00 PM PDT 24
Peak memory 222496 kb
Host smart-2c6b0bba-6331-4ac9-9555-abb1f8336ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194890755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.4194890755
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.26392193
Short name T150
Test name
Test status
Simulation time 244037143 ps
CPU time 1.08 seconds
Started Mar 14 12:31:47 PM PDT 24
Finished Mar 14 12:31:49 PM PDT 24
Peak memory 218060 kb
Host smart-15428fac-6591-4eed-80a6-7e5cb76ac9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26392193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.26392193
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.25770117
Short name T411
Test name
Test status
Simulation time 151957361 ps
CPU time 0.81 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200592 kb
Host smart-5f53a291-60f7-4be9-a76b-0f362f7b3290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25770117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.25770117
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1964934020
Short name T514
Test name
Test status
Simulation time 1432534565 ps
CPU time 6.24 seconds
Started Mar 14 12:31:50 PM PDT 24
Finished Mar 14 12:31:56 PM PDT 24
Peak memory 201020 kb
Host smart-0e624f83-5572-4cd2-ac2f-05bc62809a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964934020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1964934020
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3194386073
Short name T7
Test name
Test status
Simulation time 101612630 ps
CPU time 1.04 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 200812 kb
Host smart-003729c6-ad24-40bf-a28e-5dafacb44473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194386073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3194386073
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2302164179
Short name T111
Test name
Test status
Simulation time 18291216716 ps
CPU time 58.31 seconds
Started Mar 14 12:31:40 PM PDT 24
Finished Mar 14 12:32:38 PM PDT 24
Peak memory 209372 kb
Host smart-8afe4bcb-dad1-4b18-8467-0295f3d60493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302164179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2302164179
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.4092355447
Short name T243
Test name
Test status
Simulation time 554737231 ps
CPU time 2.67 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200800 kb
Host smart-25c62bab-fa55-4bfe-b1e7-b21d5e89413c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092355447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.4092355447
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.95033161
Short name T413
Test name
Test status
Simulation time 136941793 ps
CPU time 1.2 seconds
Started Mar 14 12:31:54 PM PDT 24
Finished Mar 14 12:31:55 PM PDT 24
Peak memory 200748 kb
Host smart-391cbafc-6308-4f93-beb8-a5bf62ec0649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95033161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.95033161
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.433400246
Short name T450
Test name
Test status
Simulation time 56707201 ps
CPU time 0.73 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 200644 kb
Host smart-08571d5b-3b7b-4adc-ad7e-e33fa8d2f888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433400246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.433400246
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.317110284
Short name T161
Test name
Test status
Simulation time 1219043839 ps
CPU time 5.6 seconds
Started Mar 14 12:31:54 PM PDT 24
Finished Mar 14 12:32:00 PM PDT 24
Peak memory 217916 kb
Host smart-e80200ec-d820-484b-92eb-6e8a10e2e69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317110284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.317110284
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2399402452
Short name T366
Test name
Test status
Simulation time 244941624 ps
CPU time 1.14 seconds
Started Mar 14 12:31:51 PM PDT 24
Finished Mar 14 12:31:52 PM PDT 24
Peak memory 218068 kb
Host smart-7aaf3b39-973c-412d-826f-7c991daf8d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399402452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2399402452
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.751788551
Short name T542
Test name
Test status
Simulation time 149148530 ps
CPU time 0.82 seconds
Started Mar 14 12:31:44 PM PDT 24
Finished Mar 14 12:31:45 PM PDT 24
Peak memory 200688 kb
Host smart-6835fbd3-e1d2-45dd-97dd-dd3366d55327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751788551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.751788551
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1204075260
Short name T86
Test name
Test status
Simulation time 1948970451 ps
CPU time 6.54 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 201044 kb
Host smart-acfd1bb0-88a6-45ee-8727-8d8c099223dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204075260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1204075260
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1825044665
Short name T247
Test name
Test status
Simulation time 103569223 ps
CPU time 1 seconds
Started Mar 14 12:32:01 PM PDT 24
Finished Mar 14 12:32:02 PM PDT 24
Peak memory 200840 kb
Host smart-35257c53-fa15-48bd-aab0-b999e6ff4bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825044665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1825044665
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2028536908
Short name T333
Test name
Test status
Simulation time 224651612 ps
CPU time 1.42 seconds
Started Mar 14 12:31:57 PM PDT 24
Finished Mar 14 12:31:59 PM PDT 24
Peak memory 201060 kb
Host smart-410d0e63-3204-47c6-b279-a0c2b62cdd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028536908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2028536908
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2070577864
Short name T335
Test name
Test status
Simulation time 699369905 ps
CPU time 4.06 seconds
Started Mar 14 12:31:59 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 201044 kb
Host smart-5320230a-13f9-49e9-8c48-ff8fac10c3bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070577864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2070577864
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3607635540
Short name T25
Test name
Test status
Simulation time 141650217 ps
CPU time 1.68 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:25 PM PDT 24
Peak memory 209116 kb
Host smart-ea4e8df2-e97f-4672-8848-d07f736af034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607635540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3607635540
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2401533822
Short name T539
Test name
Test status
Simulation time 242735193 ps
CPU time 1.37 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:04 PM PDT 24
Peak memory 200936 kb
Host smart-6db9f23c-cece-4595-b4e7-f8e414259e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401533822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2401533822
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.516228521
Short name T396
Test name
Test status
Simulation time 66733574 ps
CPU time 0.76 seconds
Started Mar 14 12:32:07 PM PDT 24
Finished Mar 14 12:32:07 PM PDT 24
Peak memory 200596 kb
Host smart-b63aab69-7d1c-4a94-b250-8f4d4956b032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516228521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.516228521
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3327918445
Short name T356
Test name
Test status
Simulation time 1232876227 ps
CPU time 5.81 seconds
Started Mar 14 12:32:09 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 222580 kb
Host smart-64e5c372-0856-4981-9ab8-ca1367ce24d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327918445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3327918445
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.965164151
Short name T371
Test name
Test status
Simulation time 244494374 ps
CPU time 1.03 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 218140 kb
Host smart-f8f11092-a646-4755-b1dc-18b1a36a4cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965164151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.965164151
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.4276418250
Short name T446
Test name
Test status
Simulation time 108872292 ps
CPU time 0.78 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200628 kb
Host smart-097d9a00-cf06-44dc-beba-2d07c956d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276418250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.4276418250
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3801628650
Short name T543
Test name
Test status
Simulation time 888115600 ps
CPU time 4.21 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:07 PM PDT 24
Peak memory 200904 kb
Host smart-6e244eaa-7601-4809-924f-316b37a2acd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801628650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3801628650
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3039576714
Short name T311
Test name
Test status
Simulation time 108064173 ps
CPU time 1.07 seconds
Started Mar 14 12:31:59 PM PDT 24
Finished Mar 14 12:32:01 PM PDT 24
Peak memory 200856 kb
Host smart-adf5edce-2fdb-4bfa-9f1f-5873b6736e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039576714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3039576714
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1484744541
Short name T207
Test name
Test status
Simulation time 124498956 ps
CPU time 1.24 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 201020 kb
Host smart-cbd164e8-7ead-4659-b1d5-6f7df2eb2394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484744541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1484744541
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3497259992
Short name T362
Test name
Test status
Simulation time 6137297998 ps
CPU time 22.71 seconds
Started Mar 14 12:31:57 PM PDT 24
Finished Mar 14 12:32:20 PM PDT 24
Peak memory 201464 kb
Host smart-8f1b7a4e-b911-4624-95ee-c9216d86663a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497259992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3497259992
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.393726710
Short name T22
Test name
Test status
Simulation time 553069952 ps
CPU time 2.76 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 200784 kb
Host smart-01b8b6b6-f682-4493-a115-841b3715f047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393726710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.393726710
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3164009935
Short name T254
Test name
Test status
Simulation time 173448178 ps
CPU time 1.19 seconds
Started Mar 14 12:32:01 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 200828 kb
Host smart-0a77c688-1c3d-42ef-bf77-90a7a9fea62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164009935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3164009935
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2796310229
Short name T431
Test name
Test status
Simulation time 74913578 ps
CPU time 0.74 seconds
Started Mar 14 12:31:57 PM PDT 24
Finished Mar 14 12:31:58 PM PDT 24
Peak memory 200732 kb
Host smart-f333b277-56e0-4c1f-b087-d3c36fafcd71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796310229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2796310229
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2248369743
Short name T318
Test name
Test status
Simulation time 1898955328 ps
CPU time 6.73 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:21 PM PDT 24
Peak memory 217800 kb
Host smart-52b2edb6-7bd3-4869-a040-2561d0a26eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248369743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2248369743
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1823186447
Short name T419
Test name
Test status
Simulation time 243481169 ps
CPU time 1.14 seconds
Started Mar 14 12:31:50 PM PDT 24
Finished Mar 14 12:31:52 PM PDT 24
Peak memory 218232 kb
Host smart-e0403794-a84a-427d-9d54-f42b932ad65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823186447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1823186447
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3027586154
Short name T347
Test name
Test status
Simulation time 107366647 ps
CPU time 0.76 seconds
Started Mar 14 12:31:55 PM PDT 24
Finished Mar 14 12:31:56 PM PDT 24
Peak memory 200564 kb
Host smart-71271e75-db7d-4fa6-9316-3df2fd4d0659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027586154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3027586154
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.968099535
Short name T224
Test name
Test status
Simulation time 1302450262 ps
CPU time 5.15 seconds
Started Mar 14 12:31:42 PM PDT 24
Finished Mar 14 12:31:47 PM PDT 24
Peak memory 201056 kb
Host smart-0d3fcd4b-e35a-4a02-8510-0d108729e1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968099535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.968099535
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2787449422
Short name T129
Test name
Test status
Simulation time 184569945 ps
CPU time 1.37 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 200848 kb
Host smart-bf68d835-eda7-4bfc-9d13-2254c19aa261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787449422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2787449422
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2728759086
Short name T346
Test name
Test status
Simulation time 116904742 ps
CPU time 1.22 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 201068 kb
Host smart-dc9e90a5-c2f9-4969-a750-1dc8513ec2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728759086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2728759086
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2029487474
Short name T349
Test name
Test status
Simulation time 6627616064 ps
CPU time 22 seconds
Started Mar 14 12:31:55 PM PDT 24
Finished Mar 14 12:32:23 PM PDT 24
Peak memory 210156 kb
Host smart-121234a4-6d2d-4bc0-8e6c-15f506d12dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029487474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2029487474
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1528822431
Short name T444
Test name
Test status
Simulation time 361405158 ps
CPU time 2.31 seconds
Started Mar 14 12:32:08 PM PDT 24
Finished Mar 14 12:32:10 PM PDT 24
Peak memory 200880 kb
Host smart-93a45e15-935a-462d-a899-773ccabc6675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528822431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1528822431
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1736812866
Short name T127
Test name
Test status
Simulation time 171569975 ps
CPU time 1.13 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:31:57 PM PDT 24
Peak memory 200736 kb
Host smart-84de857b-50b4-4c85-a3c0-ee33fd97f7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736812866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1736812866
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2261036414
Short name T308
Test name
Test status
Simulation time 73107498 ps
CPU time 0.81 seconds
Started Mar 14 12:31:52 PM PDT 24
Finished Mar 14 12:31:52 PM PDT 24
Peak memory 200704 kb
Host smart-d70a428a-4e92-4187-8f3c-a85924083c72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261036414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2261036414
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3955730581
Short name T449
Test name
Test status
Simulation time 1895138663 ps
CPU time 7.54 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:21 PM PDT 24
Peak memory 218488 kb
Host smart-1b7b0c29-217a-4fdd-b714-5a22430228a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955730581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3955730581
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3640060871
Short name T178
Test name
Test status
Simulation time 243575197 ps
CPU time 1.08 seconds
Started Mar 14 12:31:54 PM PDT 24
Finished Mar 14 12:31:56 PM PDT 24
Peak memory 218076 kb
Host smart-220593c9-efb6-46fc-8b2f-69f1a4d31b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640060871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3640060871
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.831085561
Short name T197
Test name
Test status
Simulation time 143403545 ps
CPU time 0.86 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200596 kb
Host smart-a4226a14-df61-40a1-a36e-34e443abc8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831085561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.831085561
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.52639204
Short name T88
Test name
Test status
Simulation time 1167916275 ps
CPU time 4.83 seconds
Started Mar 14 12:31:59 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 201044 kb
Host smart-35d1fb40-6cb7-46d4-b4c4-c8c96ff0fcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52639204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.52639204
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.630974347
Short name T132
Test name
Test status
Simulation time 179816240 ps
CPU time 1.22 seconds
Started Mar 14 12:32:01 PM PDT 24
Finished Mar 14 12:32:02 PM PDT 24
Peak memory 200836 kb
Host smart-0f5899ac-f508-4c94-8f01-7253ad61bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630974347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.630974347
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1875242453
Short name T479
Test name
Test status
Simulation time 252955165 ps
CPU time 1.54 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:06 PM PDT 24
Peak memory 201000 kb
Host smart-2784ae98-c923-4639-a6ca-871ffa91d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875242453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1875242453
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1491614496
Short name T293
Test name
Test status
Simulation time 3872474440 ps
CPU time 16.92 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:30 PM PDT 24
Peak memory 209316 kb
Host smart-38628e24-9211-49f3-9eb0-f7edda650629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491614496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1491614496
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1662848007
Short name T315
Test name
Test status
Simulation time 380529317 ps
CPU time 1.97 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:08 PM PDT 24
Peak memory 200824 kb
Host smart-290c05eb-dc44-489a-b3b1-adb4818b7ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662848007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1662848007
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.4188884389
Short name T232
Test name
Test status
Simulation time 75234463 ps
CPU time 0.76 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 200788 kb
Host smart-e62f1a97-10d8-455c-9be2-22955ae91779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188884389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.4188884389
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1429838
Short name T373
Test name
Test status
Simulation time 83828129 ps
CPU time 0.79 seconds
Started Mar 14 12:31:07 PM PDT 24
Finished Mar 14 12:31:08 PM PDT 24
Peak memory 200560 kb
Host smart-c3588397-8152-4f5a-902a-b302086dbba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1429838
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3449860792
Short name T317
Test name
Test status
Simulation time 1897457618 ps
CPU time 7.32 seconds
Started Mar 14 12:30:59 PM PDT 24
Finished Mar 14 12:31:07 PM PDT 24
Peak memory 217348 kb
Host smart-3f935554-5ddb-4801-975b-55d968a49912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449860792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3449860792
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1378566968
Short name T379
Test name
Test status
Simulation time 244324439 ps
CPU time 1.02 seconds
Started Mar 14 12:31:21 PM PDT 24
Finished Mar 14 12:31:22 PM PDT 24
Peak memory 217980 kb
Host smart-b18777b3-9526-464f-a1a3-0413cac9895e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378566968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1378566968
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2523841219
Short name T359
Test name
Test status
Simulation time 216583054 ps
CPU time 0.93 seconds
Started Mar 14 12:31:04 PM PDT 24
Finished Mar 14 12:31:05 PM PDT 24
Peak memory 200532 kb
Host smart-9864c60a-3419-401a-986e-da38f5c09975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523841219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2523841219
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1949859035
Short name T213
Test name
Test status
Simulation time 1293785222 ps
CPU time 4.62 seconds
Started Mar 14 12:31:29 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200856 kb
Host smart-4f40b54f-dc40-415a-b38c-31f5182db091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949859035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1949859035
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3704106089
Short name T57
Test name
Test status
Simulation time 8326896225 ps
CPU time 13.03 seconds
Started Mar 14 12:31:12 PM PDT 24
Finished Mar 14 12:31:26 PM PDT 24
Peak memory 217708 kb
Host smart-a453cc50-35a1-42c7-8b26-a3b6f4c002d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704106089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3704106089
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3932094246
Short name T165
Test name
Test status
Simulation time 148272895 ps
CPU time 1.15 seconds
Started Mar 14 12:31:11 PM PDT 24
Finished Mar 14 12:31:13 PM PDT 24
Peak memory 200856 kb
Host smart-170a8fd7-7342-404f-8c34-beac23cba74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932094246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3932094246
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2359440129
Short name T377
Test name
Test status
Simulation time 191984860 ps
CPU time 1.34 seconds
Started Mar 14 12:31:23 PM PDT 24
Finished Mar 14 12:31:25 PM PDT 24
Peak memory 201080 kb
Host smart-1250916a-e1e4-49a4-9d0c-aa318cb60218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359440129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2359440129
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.315418189
Short name T208
Test name
Test status
Simulation time 2372892867 ps
CPU time 10.29 seconds
Started Mar 14 12:31:03 PM PDT 24
Finished Mar 14 12:31:14 PM PDT 24
Peak memory 201124 kb
Host smart-4ff37ade-d43f-4273-a14e-61690fa0e017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315418189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.315418189
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.309469701
Short name T540
Test name
Test status
Simulation time 124035594 ps
CPU time 1.53 seconds
Started Mar 14 12:31:23 PM PDT 24
Finished Mar 14 12:31:25 PM PDT 24
Peak memory 209008 kb
Host smart-543cc414-431f-4376-b367-31f53b4c716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309469701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.309469701
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3828615448
Short name T395
Test name
Test status
Simulation time 118943430 ps
CPU time 1.16 seconds
Started Mar 14 12:31:01 PM PDT 24
Finished Mar 14 12:31:02 PM PDT 24
Peak memory 200828 kb
Host smart-1dcebbf3-bf97-4656-8961-02160008c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828615448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3828615448
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1543478112
Short name T217
Test name
Test status
Simulation time 73398439 ps
CPU time 0.77 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:17 PM PDT 24
Peak memory 200508 kb
Host smart-4fd0a1b5-73c3-4513-b8c5-d22b5e9e62b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543478112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1543478112
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2787425980
Short name T354
Test name
Test status
Simulation time 2335390594 ps
CPU time 8.21 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 218672 kb
Host smart-114ce3e5-4f62-4ec8-8ed7-512f4d97f76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787425980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2787425980
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2699016367
Short name T523
Test name
Test status
Simulation time 244159532 ps
CPU time 1.02 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 218124 kb
Host smart-55bd87bf-759c-4cfe-8200-cdda417471b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699016367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2699016367
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2731121387
Short name T200
Test name
Test status
Simulation time 125871454 ps
CPU time 0.81 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 200668 kb
Host smart-51cf7a49-e2dc-4b13-b3e8-7192e793e662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731121387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2731121387
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2597553748
Short name T486
Test name
Test status
Simulation time 1081076795 ps
CPU time 5.02 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:32:02 PM PDT 24
Peak memory 200924 kb
Host smart-e9ffd839-2597-48db-8f8b-ba7b856be039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597553748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2597553748
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2466848737
Short name T305
Test name
Test status
Simulation time 178607916 ps
CPU time 1.09 seconds
Started Mar 14 12:31:54 PM PDT 24
Finished Mar 14 12:31:56 PM PDT 24
Peak memory 200880 kb
Host smart-77d3c1e2-961e-4557-8860-89fde9fe1794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466848737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2466848737
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.756931640
Short name T118
Test name
Test status
Simulation time 254232349 ps
CPU time 1.56 seconds
Started Mar 14 12:32:11 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200968 kb
Host smart-d8c68eca-0c13-40af-aa98-2f2e784783a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756931640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.756931640
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.121696829
Short name T386
Test name
Test status
Simulation time 132112711 ps
CPU time 1.04 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 200852 kb
Host smart-591f2d8a-7ee5-4d8b-b437-51672c3af10a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121696829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.121696829
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3338087624
Short name T275
Test name
Test status
Simulation time 126901047 ps
CPU time 1.55 seconds
Started Mar 14 12:31:54 PM PDT 24
Finished Mar 14 12:31:56 PM PDT 24
Peak memory 209092 kb
Host smart-3c271acf-3e3a-486a-b72c-48556281741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338087624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3338087624
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3661869301
Short name T339
Test name
Test status
Simulation time 82286125 ps
CPU time 0.82 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200788 kb
Host smart-2eb20c1e-f897-412a-9820-dcb92be01e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661869301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3661869301
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.4193926909
Short name T246
Test name
Test status
Simulation time 64988513 ps
CPU time 0.73 seconds
Started Mar 14 12:31:57 PM PDT 24
Finished Mar 14 12:31:58 PM PDT 24
Peak memory 200936 kb
Host smart-b1636bbc-1605-495d-bbe2-e114853f5ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193926909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.4193926909
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3886630434
Short name T500
Test name
Test status
Simulation time 1893835250 ps
CPU time 7.41 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:10 PM PDT 24
Peak memory 218132 kb
Host smart-124897e3-559c-4e26-aea6-7d4fd19211ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886630434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3886630434
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.237262895
Short name T476
Test name
Test status
Simulation time 244292381 ps
CPU time 1.03 seconds
Started Mar 14 12:32:08 PM PDT 24
Finished Mar 14 12:32:09 PM PDT 24
Peak memory 218096 kb
Host smart-975d50bd-e2fa-4e64-8e75-61ebb378c8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237262895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.237262895
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1027010187
Short name T16
Test name
Test status
Simulation time 114064700 ps
CPU time 0.78 seconds
Started Mar 14 12:32:10 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 200592 kb
Host smart-86e7a396-7d83-422e-93ea-08abadb83855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027010187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1027010187
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.4126484872
Short name T511
Test name
Test status
Simulation time 756072434 ps
CPU time 4.06 seconds
Started Mar 14 12:31:54 PM PDT 24
Finished Mar 14 12:31:58 PM PDT 24
Peak memory 201076 kb
Host smart-342ed459-e0ed-4829-a79b-4b1f4ad73d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126484872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4126484872
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1248904475
Short name T378
Test name
Test status
Simulation time 158616000 ps
CPU time 1.2 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 201152 kb
Host smart-15a0a760-f44a-457d-a603-dd6dd499800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248904475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1248904475
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2773133714
Short name T146
Test name
Test status
Simulation time 125610976 ps
CPU time 1.21 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 201048 kb
Host smart-06c8432f-8804-461b-bc3e-d8982ab3617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773133714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2773133714
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.4002049150
Short name T286
Test name
Test status
Simulation time 115449141 ps
CPU time 1.4 seconds
Started Mar 14 12:31:55 PM PDT 24
Finished Mar 14 12:31:56 PM PDT 24
Peak memory 200880 kb
Host smart-92f73490-3ca2-4c5e-8bd1-b1c4c4480238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002049150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.4002049150
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.4275598791
Short name T483
Test name
Test status
Simulation time 71403806 ps
CPU time 0.78 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:07 PM PDT 24
Peak memory 200692 kb
Host smart-c14a6184-9eb0-4e56-99d8-507a81739495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275598791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.4275598791
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3671535838
Short name T343
Test name
Test status
Simulation time 87747237 ps
CPU time 0.84 seconds
Started Mar 14 12:31:48 PM PDT 24
Finished Mar 14 12:31:49 PM PDT 24
Peak memory 200584 kb
Host smart-b50e0679-f792-42d1-9bbc-898d815e53fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671535838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3671535838
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3691372027
Short name T535
Test name
Test status
Simulation time 1912425418 ps
CPU time 8.16 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 222592 kb
Host smart-3426a3d5-1a22-4e42-8a40-90714a3500b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691372027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3691372027
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2979163481
Short name T142
Test name
Test status
Simulation time 245323160 ps
CPU time 1.06 seconds
Started Mar 14 12:31:58 PM PDT 24
Finished Mar 14 12:32:00 PM PDT 24
Peak memory 217980 kb
Host smart-69fb2a61-8721-4d96-b673-58093880ccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979163481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2979163481
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1788075559
Short name T20
Test name
Test status
Simulation time 207161349 ps
CPU time 0.86 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 200632 kb
Host smart-ebff0b7c-021b-4de1-9ba6-e63485515b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788075559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1788075559
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.266703605
Short name T192
Test name
Test status
Simulation time 855668282 ps
CPU time 4.45 seconds
Started Mar 14 12:32:01 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 200940 kb
Host smart-9e0d0fdc-17f9-4a3a-be58-48a11384b768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266703605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.266703605
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2716412104
Short name T187
Test name
Test status
Simulation time 96411391 ps
CPU time 1 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200892 kb
Host smart-22c463c2-8cdc-4070-a1e7-95fc62b3f222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716412104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2716412104
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3208147714
Short name T403
Test name
Test status
Simulation time 248412539 ps
CPU time 1.79 seconds
Started Mar 14 12:32:01 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 200936 kb
Host smart-c6d0f960-976c-43f0-973c-941adffa0fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208147714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3208147714
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.4285658541
Short name T434
Test name
Test status
Simulation time 3446148285 ps
CPU time 12.43 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:26 PM PDT 24
Peak memory 201188 kb
Host smart-447b8f06-3014-496d-bba9-47584ec3c0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285658541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4285658541
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.690374625
Short name T491
Test name
Test status
Simulation time 384150768 ps
CPU time 2.42 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:31:58 PM PDT 24
Peak memory 200740 kb
Host smart-0fc111e5-b7f8-481a-b95c-0de54415934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690374625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.690374625
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.386488258
Short name T272
Test name
Test status
Simulation time 147735788 ps
CPU time 1.08 seconds
Started Mar 14 12:31:58 PM PDT 24
Finished Mar 14 12:31:59 PM PDT 24
Peak memory 200828 kb
Host smart-9b851131-bf47-4cf1-a18e-310566fc5616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386488258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.386488258
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.4106617586
Short name T375
Test name
Test status
Simulation time 66832940 ps
CPU time 0.75 seconds
Started Mar 14 12:32:01 PM PDT 24
Finished Mar 14 12:32:02 PM PDT 24
Peak memory 200584 kb
Host smart-91d232ea-1764-48ed-98f8-753529ca67bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106617586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.4106617586
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1221838446
Short name T6
Test name
Test status
Simulation time 1237748557 ps
CPU time 5.92 seconds
Started Mar 14 12:31:57 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 218428 kb
Host smart-a8da9cd7-5328-4c8a-ae92-33f8eda11de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221838446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1221838446
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1901944232
Short name T155
Test name
Test status
Simulation time 244278537 ps
CPU time 1.09 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:06 PM PDT 24
Peak memory 218040 kb
Host smart-37faa410-f74b-4711-8211-f6577c9b7094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901944232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1901944232
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2849845650
Short name T380
Test name
Test status
Simulation time 179776508 ps
CPU time 0.89 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 200604 kb
Host smart-64d764d7-4d61-470d-a74b-cb0b9c9193e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849845650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2849845650
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1142266034
Short name T113
Test name
Test status
Simulation time 2204334144 ps
CPU time 8.47 seconds
Started Mar 14 12:32:03 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 201080 kb
Host smart-a1b4ce0d-2089-4cb5-b1f5-082ab205afb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142266034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1142266034
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.987153947
Short name T325
Test name
Test status
Simulation time 96285582 ps
CPU time 1.03 seconds
Started Mar 14 12:31:53 PM PDT 24
Finished Mar 14 12:31:54 PM PDT 24
Peak memory 200924 kb
Host smart-7d8892d7-e830-4ab9-bbee-4ff8d4149c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987153947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.987153947
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3304807609
Short name T458
Test name
Test status
Simulation time 238204628 ps
CPU time 1.44 seconds
Started Mar 14 12:32:09 PM PDT 24
Finished Mar 14 12:32:11 PM PDT 24
Peak memory 200988 kb
Host smart-2e673e82-eb5f-470c-91ca-33551d7ebd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304807609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3304807609
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.180092015
Short name T1
Test name
Test status
Simulation time 268786126 ps
CPU time 1.41 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:31:58 PM PDT 24
Peak memory 200588 kb
Host smart-4865734e-8ec6-4f59-b75a-adb99a06ba8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180092015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.180092015
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3711601804
Short name T114
Test name
Test status
Simulation time 497868128 ps
CPU time 2.7 seconds
Started Mar 14 12:32:09 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 200836 kb
Host smart-20a771fb-72ee-46a1-aa62-82137574e3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711601804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3711601804
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1264629458
Short name T237
Test name
Test status
Simulation time 100457594 ps
CPU time 0.89 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 200884 kb
Host smart-8dff338f-cd48-46d2-804a-171993cc2eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264629458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1264629458
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.356305008
Short name T156
Test name
Test status
Simulation time 83415893 ps
CPU time 0.81 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 200540 kb
Host smart-aa508692-12fc-4f00-a900-4b2a2a6c5a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356305008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.356305008
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.406713995
Short name T39
Test name
Test status
Simulation time 1227365889 ps
CPU time 5.95 seconds
Started Mar 14 12:31:59 PM PDT 24
Finished Mar 14 12:32:06 PM PDT 24
Peak memory 222636 kb
Host smart-f4b01c2a-906e-445f-9f99-94a28e50c93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406713995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.406713995
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1406884575
Short name T445
Test name
Test status
Simulation time 244623461 ps
CPU time 1.22 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 218208 kb
Host smart-d814e2b1-08f4-4b31-9490-ab5978f743e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406884575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1406884575
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.4004793831
Short name T175
Test name
Test status
Simulation time 94903827 ps
CPU time 0.76 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 200580 kb
Host smart-25315643-1333-437e-8f88-fe48e4bd3056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004793831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.4004793831
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3204657220
Short name T513
Test name
Test status
Simulation time 1862085730 ps
CPU time 6.47 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200964 kb
Host smart-61bda91b-d200-4449-91c2-faf0397ac15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204657220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3204657220
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.8242013
Short name T180
Test name
Test status
Simulation time 170158505 ps
CPU time 1.14 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 200864 kb
Host smart-2efa18c2-4767-484c-9638-884186a10655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8242013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.8242013
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.251750969
Short name T389
Test name
Test status
Simulation time 197860251 ps
CPU time 1.34 seconds
Started Mar 14 12:31:54 PM PDT 24
Finished Mar 14 12:31:55 PM PDT 24
Peak memory 200960 kb
Host smart-53b0ce80-8c40-4b41-bc2a-c3c1bd5ebcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251750969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.251750969
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3434371379
Short name T410
Test name
Test status
Simulation time 1797957219 ps
CPU time 7.11 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:21 PM PDT 24
Peak memory 200920 kb
Host smart-7b07844d-9f36-40df-8b04-fc0276369e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434371379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3434371379
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3484009143
Short name T295
Test name
Test status
Simulation time 327243973 ps
CPU time 2.07 seconds
Started Mar 14 12:32:08 PM PDT 24
Finished Mar 14 12:32:10 PM PDT 24
Peak memory 208960 kb
Host smart-7de23b68-3b34-4861-8dd0-2202807bd21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484009143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3484009143
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2211111613
Short name T498
Test name
Test status
Simulation time 128789270 ps
CPU time 1.08 seconds
Started Mar 14 12:32:08 PM PDT 24
Finished Mar 14 12:32:09 PM PDT 24
Peak memory 200872 kb
Host smart-3947f57d-5b00-4a19-8d5d-ca6c128c7057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211111613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2211111613
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.132595826
Short name T409
Test name
Test status
Simulation time 84320347 ps
CPU time 0.82 seconds
Started Mar 14 12:32:05 PM PDT 24
Finished Mar 14 12:32:06 PM PDT 24
Peak memory 200540 kb
Host smart-0e01bfa5-34f6-4698-a26f-e6e2d8a93133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132595826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.132595826
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1446096698
Short name T38
Test name
Test status
Simulation time 1221781571 ps
CPU time 5.82 seconds
Started Mar 14 12:31:59 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 222656 kb
Host smart-b911ebcf-b511-4fda-93d4-901cd3da8b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446096698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1446096698
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.510610575
Short name T465
Test name
Test status
Simulation time 243816391 ps
CPU time 1.12 seconds
Started Mar 14 12:32:00 PM PDT 24
Finished Mar 14 12:32:02 PM PDT 24
Peak memory 218084 kb
Host smart-578a342e-7e3c-423a-9694-0276677ad629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510610575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.510610575
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2167231710
Short name T17
Test name
Test status
Simulation time 212831312 ps
CPU time 0.98 seconds
Started Mar 14 12:32:03 PM PDT 24
Finished Mar 14 12:32:04 PM PDT 24
Peak memory 200668 kb
Host smart-3bc7e500-903b-4c61-92fa-335d1bf6d18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167231710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2167231710
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.627214315
Short name T475
Test name
Test status
Simulation time 1499201320 ps
CPU time 6.01 seconds
Started Mar 14 12:32:03 PM PDT 24
Finished Mar 14 12:32:09 PM PDT 24
Peak memory 200912 kb
Host smart-254e0a48-47dd-4e21-a860-571e6cb7c6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627214315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.627214315
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4026328053
Short name T250
Test name
Test status
Simulation time 184239465 ps
CPU time 1.18 seconds
Started Mar 14 12:32:00 PM PDT 24
Finished Mar 14 12:32:02 PM PDT 24
Peak memory 200832 kb
Host smart-7a978c2e-a587-4b0f-bca7-16a6c59c9a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026328053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4026328053
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.540618295
Short name T205
Test name
Test status
Simulation time 119743776 ps
CPU time 1.13 seconds
Started Mar 14 12:32:09 PM PDT 24
Finished Mar 14 12:32:11 PM PDT 24
Peak memory 200908 kb
Host smart-a2ce1898-ea7d-4769-b7d3-7639b7e5ac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540618295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.540618295
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1044858942
Short name T313
Test name
Test status
Simulation time 5252661581 ps
CPU time 18.6 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:35 PM PDT 24
Peak memory 201136 kb
Host smart-e4ce3492-602b-4a93-9521-80c3e1edbbe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044858942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1044858942
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.94388981
Short name T75
Test name
Test status
Simulation time 144147741 ps
CPU time 1.78 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:31:59 PM PDT 24
Peak memory 200756 kb
Host smart-6dece9cc-9e0e-479f-8971-bbe5deadca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94388981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.94388981
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1998846825
Short name T331
Test name
Test status
Simulation time 230064473 ps
CPU time 1.31 seconds
Started Mar 14 12:32:11 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200916 kb
Host smart-d75c3a73-c5ab-4e27-b823-4cf351e06952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998846825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1998846825
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1565579800
Short name T538
Test name
Test status
Simulation time 76314225 ps
CPU time 0.84 seconds
Started Mar 14 12:31:59 PM PDT 24
Finished Mar 14 12:32:00 PM PDT 24
Peak memory 200576 kb
Host smart-0f667089-7a5b-4fc9-8e8d-6f32c1e7d59a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565579800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1565579800
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3753566159
Short name T360
Test name
Test status
Simulation time 1896211539 ps
CPU time 6.84 seconds
Started Mar 14 12:31:49 PM PDT 24
Finished Mar 14 12:31:55 PM PDT 24
Peak memory 219584 kb
Host smart-deb22347-045c-4b07-a9f3-76ae55271d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753566159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3753566159
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.553813759
Short name T190
Test name
Test status
Simulation time 244451089 ps
CPU time 1.07 seconds
Started Mar 14 12:31:59 PM PDT 24
Finished Mar 14 12:32:01 PM PDT 24
Peak memory 218080 kb
Host smart-c6292c4c-5fe3-4699-9b5d-bd1eb416cbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553813759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.553813759
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3842915872
Short name T278
Test name
Test status
Simulation time 176356612 ps
CPU time 0.89 seconds
Started Mar 14 12:32:08 PM PDT 24
Finished Mar 14 12:32:09 PM PDT 24
Peak memory 200568 kb
Host smart-2822852f-c3c7-48c3-a834-a38421e35ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842915872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3842915872
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.460488216
Short name T420
Test name
Test status
Simulation time 1689872000 ps
CPU time 5.99 seconds
Started Mar 14 12:32:03 PM PDT 24
Finished Mar 14 12:32:10 PM PDT 24
Peak memory 200944 kb
Host smart-09067ecc-29df-433f-916b-86d86feabf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460488216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.460488216
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2317716724
Short name T159
Test name
Test status
Simulation time 150031126 ps
CPU time 1.1 seconds
Started Mar 14 12:32:10 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 200840 kb
Host smart-9472c607-3158-4443-a8b0-9c907734016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317716724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2317716724
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1508287782
Short name T158
Test name
Test status
Simulation time 119040652 ps
CPU time 1.2 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 201084 kb
Host smart-d931c1ea-e21a-45d4-941c-741ef77ccfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508287782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1508287782
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.408601411
Short name T518
Test name
Test status
Simulation time 1047044056 ps
CPU time 5.32 seconds
Started Mar 14 12:32:07 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200948 kb
Host smart-46a30d62-61ca-4035-a259-e110e1512fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408601411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.408601411
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.549127108
Short name T290
Test name
Test status
Simulation time 322369172 ps
CPU time 1.9 seconds
Started Mar 14 12:32:07 PM PDT 24
Finished Mar 14 12:32:09 PM PDT 24
Peak memory 200748 kb
Host smart-6d857183-97eb-488b-84ad-1af84287f453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549127108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.549127108
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3054350368
Short name T169
Test name
Test status
Simulation time 158245885 ps
CPU time 1.1 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 200756 kb
Host smart-82e2539e-ae2f-47a6-90c6-b855105933fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054350368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3054350368
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1085363365
Short name T348
Test name
Test status
Simulation time 60945364 ps
CPU time 0.8 seconds
Started Mar 14 12:32:03 PM PDT 24
Finished Mar 14 12:32:04 PM PDT 24
Peak memory 200696 kb
Host smart-b632bdbc-076e-4625-95b3-2465906124bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085363365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1085363365
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2755278380
Short name T33
Test name
Test status
Simulation time 1223827221 ps
CPU time 5.54 seconds
Started Mar 14 12:31:59 PM PDT 24
Finished Mar 14 12:32:04 PM PDT 24
Peak memory 230136 kb
Host smart-4f56c139-07bc-4e16-93b5-0443d3dc2db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755278380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2755278380
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1545390120
Short name T258
Test name
Test status
Simulation time 244397976 ps
CPU time 1.02 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:07 PM PDT 24
Peak memory 218068 kb
Host smart-31160182-ef94-4c98-bd11-2b49bf6acf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545390120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1545390120
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2750453326
Short name T19
Test name
Test status
Simulation time 169565016 ps
CPU time 0.83 seconds
Started Mar 14 12:31:57 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 200692 kb
Host smart-44431683-c49f-49ed-a481-35a0b8ee34ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750453326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2750453326
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1839429563
Short name T153
Test name
Test status
Simulation time 1246955259 ps
CPU time 5.78 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:08 PM PDT 24
Peak memory 200940 kb
Host smart-06df8418-1b8d-422c-a486-ecea6082b583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839429563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1839429563
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1238425101
Short name T283
Test name
Test status
Simulation time 171828550 ps
CPU time 1.12 seconds
Started Mar 14 12:32:31 PM PDT 24
Finished Mar 14 12:32:32 PM PDT 24
Peak memory 200756 kb
Host smart-b2f6610f-4f84-490e-8ac9-be8a22afdc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238425101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1238425101
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1555275369
Short name T117
Test name
Test status
Simulation time 235785008 ps
CPU time 1.54 seconds
Started Mar 14 12:31:53 PM PDT 24
Finished Mar 14 12:32:00 PM PDT 24
Peak memory 201076 kb
Host smart-d4d28a57-1b24-45aa-90d8-bac5feda759b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555275369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1555275369
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.780888088
Short name T204
Test name
Test status
Simulation time 7110252294 ps
CPU time 32.01 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:47 PM PDT 24
Peak memory 201144 kb
Host smart-6375067e-5247-4571-96cd-3ba24802bd7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780888088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.780888088
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1404461869
Short name T398
Test name
Test status
Simulation time 310168204 ps
CPU time 2.11 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 200912 kb
Host smart-402ee7f8-c134-4c8a-a3b6-9c6ef9a52282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404461869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1404461869
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1857751869
Short name T453
Test name
Test status
Simulation time 83865443 ps
CPU time 0.88 seconds
Started Mar 14 12:32:28 PM PDT 24
Finished Mar 14 12:32:29 PM PDT 24
Peak memory 200888 kb
Host smart-006ea398-eb5a-4a02-af3e-8e6433278798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857751869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1857751869
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3158687444
Short name T66
Test name
Test status
Simulation time 62440434 ps
CPU time 0.74 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 200612 kb
Host smart-e903626c-30b4-43a1-8a9e-2028d9e47196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158687444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3158687444
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1256452692
Short name T432
Test name
Test status
Simulation time 2368673182 ps
CPU time 7.89 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 218524 kb
Host smart-e0733519-a1b1-48dc-b6f0-f15d57b6aa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256452692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1256452692
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.301685084
Short name T270
Test name
Test status
Simulation time 244565409 ps
CPU time 1.02 seconds
Started Mar 14 12:32:05 PM PDT 24
Finished Mar 14 12:32:07 PM PDT 24
Peak memory 218096 kb
Host smart-f958ea49-b0af-4797-a6e5-243f148d4518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301685084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.301685084
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.468901930
Short name T392
Test name
Test status
Simulation time 163030067 ps
CPU time 0.98 seconds
Started Mar 14 12:32:03 PM PDT 24
Finished Mar 14 12:32:04 PM PDT 24
Peak memory 200676 kb
Host smart-cae8ddd1-ad94-42bf-895e-ba6e4fafeb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468901930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.468901930
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1668135934
Short name T441
Test name
Test status
Simulation time 808546785 ps
CPU time 3.97 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 201036 kb
Host smart-95d961e5-f831-45bb-b821-440be9beee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668135934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1668135934
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.468810107
Short name T337
Test name
Test status
Simulation time 178691014 ps
CPU time 1.28 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200848 kb
Host smart-2d7112bc-aba9-4e05-9002-ac63aeca5307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468810107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.468810107
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3580563249
Short name T499
Test name
Test status
Simulation time 251615111 ps
CPU time 1.61 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:19 PM PDT 24
Peak memory 200940 kb
Host smart-41bcb67b-d110-448b-92bc-9922848ebd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580563249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3580563249
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.522605513
Short name T527
Test name
Test status
Simulation time 3894525972 ps
CPU time 15.96 seconds
Started Mar 14 12:32:02 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 201204 kb
Host smart-218bb989-5ad8-47fa-81ab-034d5fcfeb26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522605513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.522605513
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1739478197
Short name T287
Test name
Test status
Simulation time 132874806 ps
CPU time 1.53 seconds
Started Mar 14 12:32:11 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 209108 kb
Host smart-339e78b1-aa90-4676-8631-c7aaacd2aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739478197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1739478197
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1843332668
Short name T131
Test name
Test status
Simulation time 127569222 ps
CPU time 1.1 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 200848 kb
Host smart-3b90c127-e5d9-495e-8744-69e1949f055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843332668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1843332668
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1301919515
Short name T196
Test name
Test status
Simulation time 67526517 ps
CPU time 0.77 seconds
Started Mar 14 12:32:08 PM PDT 24
Finished Mar 14 12:32:09 PM PDT 24
Peak memory 200672 kb
Host smart-b6c4de20-9ea8-4685-8f66-99cc9ebd1ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301919515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1301919515
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1800784607
Short name T29
Test name
Test status
Simulation time 1899091320 ps
CPU time 6.7 seconds
Started Mar 14 12:32:32 PM PDT 24
Finished Mar 14 12:32:38 PM PDT 24
Peak memory 222644 kb
Host smart-957eab45-620f-47ac-b10f-60a5be69ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800784607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1800784607
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.4262061689
Short name T310
Test name
Test status
Simulation time 244161866 ps
CPU time 1.07 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 218036 kb
Host smart-f3bebf46-b5bc-46cc-a896-31a00a04a5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262061689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.4262061689
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2519639709
Short name T355
Test name
Test status
Simulation time 150238862 ps
CPU time 0.83 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:17 PM PDT 24
Peak memory 200648 kb
Host smart-e79b1fc8-2467-47aa-927e-5bdc5565864b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519639709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2519639709
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.168827838
Short name T110
Test name
Test status
Simulation time 1571367510 ps
CPU time 5.67 seconds
Started Mar 14 12:32:09 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 201020 kb
Host smart-9686bcff-1995-402f-9601-f1a1a299cbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168827838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.168827838
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1889923707
Short name T370
Test name
Test status
Simulation time 157730907 ps
CPU time 1.11 seconds
Started Mar 14 12:32:09 PM PDT 24
Finished Mar 14 12:32:11 PM PDT 24
Peak memory 200856 kb
Host smart-37c4aaee-ab1e-49c7-b4df-26803c0eeb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889923707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1889923707
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2028590081
Short name T157
Test name
Test status
Simulation time 200442042 ps
CPU time 1.42 seconds
Started Mar 14 12:32:18 PM PDT 24
Finished Mar 14 12:32:20 PM PDT 24
Peak memory 201072 kb
Host smart-57f9915e-4ea5-4280-936d-2d635869e779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028590081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2028590081
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1377071608
Short name T404
Test name
Test status
Simulation time 6490757373 ps
CPU time 28.12 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:32 PM PDT 24
Peak memory 217576 kb
Host smart-e42a3ff1-946c-4565-aa4e-7a5479256a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377071608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1377071608
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.990424944
Short name T136
Test name
Test status
Simulation time 129944221 ps
CPU time 1.69 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:19 PM PDT 24
Peak memory 208948 kb
Host smart-022e0038-26fd-43f3-b5fa-d5e8aad602c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990424944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.990424944
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.481030265
Short name T365
Test name
Test status
Simulation time 147897019 ps
CPU time 1.01 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 200824 kb
Host smart-6a0cab22-eb43-49e2-8c2c-ad91934a1465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481030265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.481030265
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4158253901
Short name T173
Test name
Test status
Simulation time 65289393 ps
CPU time 0.81 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:25 PM PDT 24
Peak memory 200500 kb
Host smart-524ebf24-e162-4860-a9e6-cf9610edcb9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158253901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4158253901
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1260638708
Short name T261
Test name
Test status
Simulation time 1221996822 ps
CPU time 5.24 seconds
Started Mar 14 12:31:19 PM PDT 24
Finished Mar 14 12:31:25 PM PDT 24
Peak memory 222620 kb
Host smart-0e65e4a5-6179-4f37-a00a-3975e407a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260638708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1260638708
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.622001219
Short name T221
Test name
Test status
Simulation time 244290472 ps
CPU time 1.03 seconds
Started Mar 14 12:31:04 PM PDT 24
Finished Mar 14 12:31:05 PM PDT 24
Peak memory 218004 kb
Host smart-e2081450-0ff2-4a49-acd6-03c6b463e87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622001219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.622001219
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1724979874
Short name T245
Test name
Test status
Simulation time 81372272 ps
CPU time 0.79 seconds
Started Mar 14 12:31:05 PM PDT 24
Finished Mar 14 12:31:06 PM PDT 24
Peak memory 200668 kb
Host smart-595f5b3a-04dc-48a6-a190-8461ad6b6d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724979874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1724979874
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.506698804
Short name T69
Test name
Test status
Simulation time 777872636 ps
CPU time 4.03 seconds
Started Mar 14 12:31:21 PM PDT 24
Finished Mar 14 12:31:25 PM PDT 24
Peak memory 200844 kb
Host smart-6fb6437d-55cd-4125-a76a-46476385720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506698804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.506698804
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2215524843
Short name T60
Test name
Test status
Simulation time 8582259717 ps
CPU time 12.74 seconds
Started Mar 14 12:31:07 PM PDT 24
Finished Mar 14 12:31:20 PM PDT 24
Peak memory 217832 kb
Host smart-0a8726c4-2fac-46db-bf29-1277ab5683e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215524843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2215524843
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2810664360
Short name T151
Test name
Test status
Simulation time 98697342 ps
CPU time 1.05 seconds
Started Mar 14 12:31:12 PM PDT 24
Finished Mar 14 12:31:13 PM PDT 24
Peak memory 200760 kb
Host smart-6edfcb58-1356-480f-bfd6-cdbc9106faa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810664360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2810664360
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1427989962
Short name T116
Test name
Test status
Simulation time 253369698 ps
CPU time 1.44 seconds
Started Mar 14 12:31:22 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 201028 kb
Host smart-632e5ec4-a39a-42d4-aead-9ab10deb02b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427989962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1427989962
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1660204606
Short name T134
Test name
Test status
Simulation time 144236469 ps
CPU time 1.05 seconds
Started Mar 14 12:31:25 PM PDT 24
Finished Mar 14 12:31:26 PM PDT 24
Peak memory 200808 kb
Host smart-4d910005-cd57-42af-8ddc-37561a6625ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660204606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1660204606
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2183046557
Short name T297
Test name
Test status
Simulation time 275991127 ps
CPU time 1.9 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 200836 kb
Host smart-0b123093-83f5-45b1-a380-cdf049ec39cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183046557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2183046557
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2446566016
Short name T406
Test name
Test status
Simulation time 86910638 ps
CPU time 0.81 seconds
Started Mar 14 12:31:09 PM PDT 24
Finished Mar 14 12:31:10 PM PDT 24
Peak memory 200864 kb
Host smart-e590b095-a9c1-4054-b897-e331ae4bfaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446566016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2446566016
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2479781850
Short name T332
Test name
Test status
Simulation time 55276601 ps
CPU time 0.71 seconds
Started Mar 14 12:33:04 PM PDT 24
Finished Mar 14 12:33:05 PM PDT 24
Peak memory 200580 kb
Host smart-68dc595f-63b4-47c1-8684-0714f72b8988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479781850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2479781850
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.893924843
Short name T35
Test name
Test status
Simulation time 2340508523 ps
CPU time 8.2 seconds
Started Mar 14 12:32:21 PM PDT 24
Finished Mar 14 12:32:29 PM PDT 24
Peak memory 218680 kb
Host smart-8473e68a-338d-46be-a5ee-9462a44a8dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893924843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.893924843
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.4237461222
Short name T423
Test name
Test status
Simulation time 247583867 ps
CPU time 1.09 seconds
Started Mar 14 12:32:29 PM PDT 24
Finished Mar 14 12:32:31 PM PDT 24
Peak memory 218108 kb
Host smart-41acc990-1c15-426a-8122-5dd73cd5c2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237461222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.4237461222
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2938959865
Short name T218
Test name
Test status
Simulation time 155664057 ps
CPU time 0.82 seconds
Started Mar 14 12:32:19 PM PDT 24
Finished Mar 14 12:32:20 PM PDT 24
Peak memory 200672 kb
Host smart-a075b6ae-1ae8-4f31-9bca-4be63b0babc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938959865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2938959865
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.863513052
Short name T264
Test name
Test status
Simulation time 831487303 ps
CPU time 4.2 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:11 PM PDT 24
Peak memory 201076 kb
Host smart-7f883637-8e2f-4f3a-9551-76b642149d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863513052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.863513052
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.233194162
Short name T71
Test name
Test status
Simulation time 102282109 ps
CPU time 1.03 seconds
Started Mar 14 12:31:58 PM PDT 24
Finished Mar 14 12:32:00 PM PDT 24
Peak memory 200872 kb
Host smart-13e67d35-293b-4e14-b17c-0aef74d6a950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233194162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.233194162
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3383051672
Short name T319
Test name
Test status
Simulation time 185277975 ps
CPU time 1.3 seconds
Started Mar 14 12:32:11 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200948 kb
Host smart-57bfe098-ce2d-4a0b-8627-706008f5aa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383051672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3383051672
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3198569254
Short name T90
Test name
Test status
Simulation time 2679594028 ps
CPU time 12.24 seconds
Started Mar 14 12:32:38 PM PDT 24
Finished Mar 14 12:32:51 PM PDT 24
Peak memory 201332 kb
Host smart-a23c60ee-4ff2-4ede-a1c3-a029967f6520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198569254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3198569254
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.4134799196
Short name T201
Test name
Test status
Simulation time 145456221 ps
CPU time 1.72 seconds
Started Mar 14 12:32:03 PM PDT 24
Finished Mar 14 12:32:05 PM PDT 24
Peak memory 200896 kb
Host smart-36be4ef0-b09c-41d8-b085-30c0d0dbac38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134799196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4134799196
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2973252707
Short name T521
Test name
Test status
Simulation time 167078652 ps
CPU time 1.19 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 201028 kb
Host smart-73e61999-92ce-4d5b-bdac-e28a3dfa1b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973252707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2973252707
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.761633378
Short name T424
Test name
Test status
Simulation time 71818342 ps
CPU time 0.75 seconds
Started Mar 14 12:32:07 PM PDT 24
Finished Mar 14 12:32:07 PM PDT 24
Peak memory 200696 kb
Host smart-2a58d62e-1ae9-4b30-9668-40bb9d78ac41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761633378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.761633378
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1923945605
Short name T383
Test name
Test status
Simulation time 1223668191 ps
CPU time 5.6 seconds
Started Mar 14 12:32:11 PM PDT 24
Finished Mar 14 12:32:22 PM PDT 24
Peak memory 218556 kb
Host smart-12834d76-65bd-465f-88b2-a021c54ea6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923945605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1923945605
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2900077849
Short name T267
Test name
Test status
Simulation time 244444324 ps
CPU time 0.97 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:17 PM PDT 24
Peak memory 218136 kb
Host smart-1a4c220c-1249-478d-aa87-dd819936e7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900077849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2900077849
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.513166485
Short name T443
Test name
Test status
Simulation time 151616011 ps
CPU time 0.83 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:17 PM PDT 24
Peak memory 200696 kb
Host smart-9a009ec1-93cf-49a3-841d-2513506c40ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513166485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.513166485
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1549105314
Short name T328
Test name
Test status
Simulation time 737957586 ps
CPU time 3.65 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:19 PM PDT 24
Peak memory 201072 kb
Host smart-e80dc6fd-b69e-4ecd-b5a2-2d259577e23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549105314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1549105314
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2763620287
Short name T324
Test name
Test status
Simulation time 139907407 ps
CPU time 1.08 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:19 PM PDT 24
Peak memory 200880 kb
Host smart-7c70db83-9f5a-426f-a180-ca8744cfc21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763620287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2763620287
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1808902467
Short name T525
Test name
Test status
Simulation time 124648186 ps
CPU time 1.16 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200976 kb
Host smart-2b9c29da-e5c0-4da6-a843-5fa70284c40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808902467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1808902467
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1393318873
Short name T482
Test name
Test status
Simulation time 5809025924 ps
CPU time 21.47 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:39 PM PDT 24
Peak memory 210796 kb
Host smart-c08853ff-02ba-4853-a946-a588b5f4ca2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393318873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1393318873
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3935652082
Short name T74
Test name
Test status
Simulation time 309957167 ps
CPU time 2.01 seconds
Started Mar 14 12:32:19 PM PDT 24
Finished Mar 14 12:32:21 PM PDT 24
Peak memory 209080 kb
Host smart-ec7a18bd-80d3-4630-a50a-62cd96796404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935652082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3935652082
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2068803744
Short name T399
Test name
Test status
Simulation time 68817156 ps
CPU time 0.82 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:14 PM PDT 24
Peak memory 200828 kb
Host smart-736afd30-a75d-47b3-bcfe-eb05651b7630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068803744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2068803744
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1285496703
Short name T220
Test name
Test status
Simulation time 88814305 ps
CPU time 0.79 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 200580 kb
Host smart-dd9bbd33-6e66-4623-b131-25ca25b80dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285496703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1285496703
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2512918251
Short name T407
Test name
Test status
Simulation time 1887953946 ps
CPU time 7.39 seconds
Started Mar 14 12:32:20 PM PDT 24
Finished Mar 14 12:32:28 PM PDT 24
Peak memory 222632 kb
Host smart-87aa3fce-4aed-48fd-bd9c-3921f949eab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512918251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2512918251
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2553367353
Short name T68
Test name
Test status
Simulation time 244449328 ps
CPU time 1.17 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 217976 kb
Host smart-8bce416f-99d0-4350-b742-8fc9019476e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553367353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2553367353
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2370091917
Short name T21
Test name
Test status
Simulation time 120707992 ps
CPU time 0.82 seconds
Started Mar 14 12:31:58 PM PDT 24
Finished Mar 14 12:31:59 PM PDT 24
Peak memory 200564 kb
Host smart-f935be3a-d9b1-439a-8388-68a09ea3877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370091917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2370091917
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2107374980
Short name T352
Test name
Test status
Simulation time 826330920 ps
CPU time 4.3 seconds
Started Mar 14 12:32:44 PM PDT 24
Finished Mar 14 12:32:50 PM PDT 24
Peak memory 201036 kb
Host smart-d1497a60-07d7-42de-805f-1bf7caf29290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107374980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2107374980
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1076429753
Short name T62
Test name
Test status
Simulation time 116482745 ps
CPU time 1.03 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200896 kb
Host smart-bb2b1843-d5aa-4033-80fb-408ef25db0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076429753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1076429753
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3593793797
Short name T181
Test name
Test status
Simulation time 195113891 ps
CPU time 1.31 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200908 kb
Host smart-e692ec2b-e979-4410-924e-e10bc65808f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593793797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3593793797
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1959963398
Short name T323
Test name
Test status
Simulation time 269732193 ps
CPU time 1.43 seconds
Started Mar 14 12:32:08 PM PDT 24
Finished Mar 14 12:32:09 PM PDT 24
Peak memory 200856 kb
Host smart-26bb438c-c134-4a73-9a44-4d7e76dae4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959963398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1959963398
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2203076864
Short name T171
Test name
Test status
Simulation time 423864006 ps
CPU time 2.21 seconds
Started Mar 14 12:32:18 PM PDT 24
Finished Mar 14 12:32:20 PM PDT 24
Peak memory 209040 kb
Host smart-109466ef-537b-4201-b84e-d69c2f9d3894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203076864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2203076864
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.799668340
Short name T515
Test name
Test status
Simulation time 218738548 ps
CPU time 1.26 seconds
Started Mar 14 12:32:09 PM PDT 24
Finished Mar 14 12:32:11 PM PDT 24
Peak memory 200860 kb
Host smart-e433c0a1-922c-461a-aeff-ef81e0e44793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799668340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.799668340
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.122376049
Short name T138
Test name
Test status
Simulation time 68940387 ps
CPU time 0.77 seconds
Started Mar 14 12:32:21 PM PDT 24
Finished Mar 14 12:32:22 PM PDT 24
Peak memory 200696 kb
Host smart-6f2f89c3-be43-4384-997d-689c7643f011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122376049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.122376049
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3291137690
Short name T40
Test name
Test status
Simulation time 2357054211 ps
CPU time 8.33 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:23 PM PDT 24
Peak memory 222760 kb
Host smart-9e3c75f5-c1ae-4add-ae79-25077b2b70f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291137690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3291137690
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2925411702
Short name T466
Test name
Test status
Simulation time 244625081 ps
CPU time 1.01 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 217896 kb
Host smart-3bed3d74-da31-429e-9e53-27cdc2417c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925411702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2925411702
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3826442415
Short name T199
Test name
Test status
Simulation time 89981807 ps
CPU time 0.75 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 200672 kb
Host smart-dc721a1a-8999-4694-9220-3c60404e74aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826442415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3826442415
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1081652902
Short name T342
Test name
Test status
Simulation time 852028626 ps
CPU time 4.43 seconds
Started Mar 14 12:32:04 PM PDT 24
Finished Mar 14 12:32:08 PM PDT 24
Peak memory 201056 kb
Host smart-f4606d73-e9f8-4281-8f2f-865ba3e45cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081652902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1081652902
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.351988159
Short name T168
Test name
Test status
Simulation time 109208274 ps
CPU time 1 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 200940 kb
Host smart-47d97712-a771-4854-9b6c-f2d85ab26f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351988159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.351988159
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1196943484
Short name T145
Test name
Test status
Simulation time 250118156 ps
CPU time 1.53 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:08 PM PDT 24
Peak memory 201016 kb
Host smart-343f645e-86ea-466b-af14-d91046546aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196943484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1196943484
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2120553091
Short name T177
Test name
Test status
Simulation time 126441040 ps
CPU time 1.02 seconds
Started Mar 14 12:32:18 PM PDT 24
Finished Mar 14 12:32:19 PM PDT 24
Peak memory 200796 kb
Host smart-99d54d67-f1cd-4844-91be-63850b93c289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120553091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2120553091
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1647450328
Short name T496
Test name
Test status
Simulation time 429581724 ps
CPU time 2.23 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:19 PM PDT 24
Peak memory 209080 kb
Host smart-6136a2d5-e351-4956-9646-7e0087cb54b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647450328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1647450328
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1342368406
Short name T376
Test name
Test status
Simulation time 92068136 ps
CPU time 0.81 seconds
Started Mar 14 12:32:23 PM PDT 24
Finished Mar 14 12:32:24 PM PDT 24
Peak memory 200880 kb
Host smart-7bd5c352-fdc3-4f71-a873-9b0473c4a8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342368406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1342368406
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2081474485
Short name T170
Test name
Test status
Simulation time 89774699 ps
CPU time 0.79 seconds
Started Mar 14 12:32:21 PM PDT 24
Finished Mar 14 12:32:22 PM PDT 24
Peak memory 200632 kb
Host smart-8ee029a1-6182-44c9-be2f-e0e12cc3e9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081474485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2081474485
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2162803957
Short name T37
Test name
Test status
Simulation time 2347934359 ps
CPU time 8.08 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:22 PM PDT 24
Peak memory 218660 kb
Host smart-d9b47972-f22b-406d-96cc-cce3cc77b28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162803957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2162803957
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.759351078
Short name T408
Test name
Test status
Simulation time 245574577 ps
CPU time 1.16 seconds
Started Mar 14 12:32:25 PM PDT 24
Finished Mar 14 12:32:27 PM PDT 24
Peak memory 218012 kb
Host smart-874a91ee-9391-45fb-801d-5f0695ba462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759351078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.759351078
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2138890068
Short name T320
Test name
Test status
Simulation time 81864756 ps
CPU time 0.77 seconds
Started Mar 14 12:32:18 PM PDT 24
Finished Mar 14 12:32:19 PM PDT 24
Peak memory 200604 kb
Host smart-ecc81f7f-6780-42f1-9ed9-339f232a2815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138890068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2138890068
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3723739850
Short name T544
Test name
Test status
Simulation time 1930420698 ps
CPU time 6.98 seconds
Started Mar 14 12:32:14 PM PDT 24
Finished Mar 14 12:32:21 PM PDT 24
Peak memory 201052 kb
Host smart-4b48d863-2c19-49e7-bc09-4b2c4bfbc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723739850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3723739850
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2015927500
Short name T508
Test name
Test status
Simulation time 97619831 ps
CPU time 1.03 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200844 kb
Host smart-50c28835-8345-44e8-85e4-a30734ed9e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015927500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2015927500
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3294730987
Short name T152
Test name
Test status
Simulation time 121197572 ps
CPU time 1.14 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 201028 kb
Host smart-3b84688d-6b21-4e5c-8af8-15f440365df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294730987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3294730987
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2921573299
Short name T225
Test name
Test status
Simulation time 4454780054 ps
CPU time 15.15 seconds
Started Mar 14 12:32:05 PM PDT 24
Finished Mar 14 12:32:20 PM PDT 24
Peak memory 201172 kb
Host smart-208056a5-e1f1-4b71-bbc9-39a4012d9c07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921573299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2921573299
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4022502480
Short name T115
Test name
Test status
Simulation time 416542007 ps
CPU time 2.28 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:15 PM PDT 24
Peak memory 209024 kb
Host smart-c69e2413-f554-4a08-b242-8405580d457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022502480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4022502480
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1763222630
Short name T209
Test name
Test status
Simulation time 75275714 ps
CPU time 0.78 seconds
Started Mar 14 12:32:18 PM PDT 24
Finished Mar 14 12:32:19 PM PDT 24
Peak memory 200840 kb
Host smart-2ca91fb0-085c-4e3b-bf99-e254c824ff87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763222630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1763222630
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3415267146
Short name T191
Test name
Test status
Simulation time 66607204 ps
CPU time 0.74 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 200692 kb
Host smart-814ff689-072c-4fe8-b4d0-b304983daeae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415267146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3415267146
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3685929373
Short name T448
Test name
Test status
Simulation time 2351915562 ps
CPU time 7.98 seconds
Started Mar 14 12:32:24 PM PDT 24
Finished Mar 14 12:32:33 PM PDT 24
Peak memory 222520 kb
Host smart-94732d0c-11f6-4201-96d8-7cf6e5438354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685929373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3685929373
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2639010714
Short name T501
Test name
Test status
Simulation time 244360581 ps
CPU time 1.07 seconds
Started Mar 14 12:32:32 PM PDT 24
Finished Mar 14 12:32:33 PM PDT 24
Peak memory 218072 kb
Host smart-6328f682-729c-453e-9d47-fcaaf4a518fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639010714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2639010714
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.4267264193
Short name T274
Test name
Test status
Simulation time 189916196 ps
CPU time 0.86 seconds
Started Mar 14 12:32:30 PM PDT 24
Finished Mar 14 12:32:31 PM PDT 24
Peak memory 200644 kb
Host smart-1db7b566-c412-449f-9eba-8698686a9941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267264193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.4267264193
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3799913755
Short name T24
Test name
Test status
Simulation time 1674130337 ps
CPU time 6.12 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:20 PM PDT 24
Peak memory 201020 kb
Host smart-e1f056cf-7124-47e2-afca-922ff2247d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799913755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3799913755
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2943966943
Short name T415
Test name
Test status
Simulation time 169656157 ps
CPU time 1.12 seconds
Started Mar 14 12:32:23 PM PDT 24
Finished Mar 14 12:32:24 PM PDT 24
Peak memory 200752 kb
Host smart-e6cbd23c-f523-4326-a423-7d1901cc0c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943966943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2943966943
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1609869616
Short name T235
Test name
Test status
Simulation time 189698459 ps
CPU time 1.34 seconds
Started Mar 14 12:32:05 PM PDT 24
Finished Mar 14 12:32:06 PM PDT 24
Peak memory 201032 kb
Host smart-dcdb97c4-5498-489c-86a1-88d6844823bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609869616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1609869616
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1197353895
Short name T223
Test name
Test status
Simulation time 253231872 ps
CPU time 1.6 seconds
Started Mar 14 12:32:01 PM PDT 24
Finished Mar 14 12:32:03 PM PDT 24
Peak memory 201028 kb
Host smart-63b83b28-0a28-40d9-8a54-a955457e5659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197353895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1197353895
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1537796651
Short name T469
Test name
Test status
Simulation time 116832073 ps
CPU time 1.5 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:17 PM PDT 24
Peak memory 200828 kb
Host smart-24c5aae5-6c14-4c50-a1db-b89d50d35293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537796651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1537796651
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3454777680
Short name T330
Test name
Test status
Simulation time 136831390 ps
CPU time 0.98 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:16 PM PDT 24
Peak memory 200804 kb
Host smart-686d540e-cc29-40e7-ae38-173879ec78a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454777680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3454777680
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3923082461
Short name T298
Test name
Test status
Simulation time 73358149 ps
CPU time 0.78 seconds
Started Mar 14 12:32:12 PM PDT 24
Finished Mar 14 12:32:13 PM PDT 24
Peak memory 200564 kb
Host smart-6e459f6d-13b7-45b5-8da3-f16de15c65cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923082461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3923082461
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1300162396
Short name T388
Test name
Test status
Simulation time 1222456651 ps
CPU time 5.43 seconds
Started Mar 14 12:32:22 PM PDT 24
Finished Mar 14 12:32:28 PM PDT 24
Peak memory 222176 kb
Host smart-f98a02ff-d765-4e51-9af7-6b188d82764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300162396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1300162396
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.4132130008
Short name T387
Test name
Test status
Simulation time 244407853 ps
CPU time 1.01 seconds
Started Mar 14 12:32:09 PM PDT 24
Finished Mar 14 12:32:10 PM PDT 24
Peak memory 218192 kb
Host smart-17ad8ba8-4fdf-43f0-aa44-29ede3fa3b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132130008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.4132130008
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.431853142
Short name T531
Test name
Test status
Simulation time 161916351 ps
CPU time 0.85 seconds
Started Mar 14 12:32:23 PM PDT 24
Finished Mar 14 12:32:29 PM PDT 24
Peak memory 200620 kb
Host smart-1977e25f-2cdd-4fdd-acee-48807ec5b920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431853142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.431853142
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3607739866
Short name T87
Test name
Test status
Simulation time 911543200 ps
CPU time 4.09 seconds
Started Mar 14 12:32:08 PM PDT 24
Finished Mar 14 12:32:17 PM PDT 24
Peak memory 201064 kb
Host smart-04ce74cc-7ab6-4fca-9b52-05e97e12e1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607739866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3607739866
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1703378490
Short name T193
Test name
Test status
Simulation time 253857051 ps
CPU time 1.61 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200876 kb
Host smart-3d33858f-cc46-4cc6-b592-378a12e2d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703378490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1703378490
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3199630952
Short name T203
Test name
Test status
Simulation time 5438445762 ps
CPU time 19.18 seconds
Started Mar 14 12:32:13 PM PDT 24
Finished Mar 14 12:32:38 PM PDT 24
Peak memory 201044 kb
Host smart-2ed6ff9d-c6ee-4cc1-bdea-1b334bf344ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199630952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3199630952
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.504659166
Short name T269
Test name
Test status
Simulation time 272202589 ps
CPU time 1.85 seconds
Started Mar 14 12:32:09 PM PDT 24
Finished Mar 14 12:32:11 PM PDT 24
Peak memory 200828 kb
Host smart-01e64a9b-96a6-40e1-98ce-71d11b44c812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504659166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.504659166
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.238424626
Short name T442
Test name
Test status
Simulation time 99197273 ps
CPU time 0.83 seconds
Started Mar 14 12:32:23 PM PDT 24
Finished Mar 14 12:32:24 PM PDT 24
Peak memory 200736 kb
Host smart-6fc5dbf0-04a8-4a02-a2f0-c92879294fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238424626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.238424626
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3535629703
Short name T358
Test name
Test status
Simulation time 99329308 ps
CPU time 0.87 seconds
Started Mar 14 12:32:11 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 200660 kb
Host smart-72674f48-f548-41f2-973e-1353d71ebf25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535629703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3535629703
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.424848304
Short name T32
Test name
Test status
Simulation time 1233004583 ps
CPU time 5.65 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:22 PM PDT 24
Peak memory 230392 kb
Host smart-4d370fd6-f287-4015-b7f6-c2f6f90465e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424848304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.424848304
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2783806016
Short name T430
Test name
Test status
Simulation time 244118325 ps
CPU time 1.04 seconds
Started Mar 14 12:32:24 PM PDT 24
Finished Mar 14 12:32:26 PM PDT 24
Peak memory 217916 kb
Host smart-bce8862a-3178-4a05-a474-64c4c04fd99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783806016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2783806016
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2347206996
Short name T265
Test name
Test status
Simulation time 157116281 ps
CPU time 0.82 seconds
Started Mar 14 12:32:24 PM PDT 24
Finished Mar 14 12:32:31 PM PDT 24
Peak memory 200264 kb
Host smart-4d742229-e95d-4005-b922-50a35d51bfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347206996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2347206996
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2075471369
Short name T147
Test name
Test status
Simulation time 880614664 ps
CPU time 4.75 seconds
Started Mar 14 12:32:18 PM PDT 24
Finished Mar 14 12:32:23 PM PDT 24
Peak memory 200928 kb
Host smart-1031dd7d-43ec-4a97-86b4-a6cce14b32b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075471369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2075471369
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3444714998
Short name T215
Test name
Test status
Simulation time 98166408 ps
CPU time 0.99 seconds
Started Mar 14 12:32:24 PM PDT 24
Finished Mar 14 12:32:26 PM PDT 24
Peak memory 200604 kb
Host smart-05174584-fac2-4a0a-a656-97c6aacb601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444714998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3444714998
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.459910042
Short name T262
Test name
Test status
Simulation time 120490951 ps
CPU time 1.19 seconds
Started Mar 14 12:32:26 PM PDT 24
Finished Mar 14 12:32:28 PM PDT 24
Peak memory 201028 kb
Host smart-c1ef974c-b98d-4bae-8585-b774f2489720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459910042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.459910042
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2989044917
Short name T41
Test name
Test status
Simulation time 5528575649 ps
CPU time 20.64 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:36 PM PDT 24
Peak memory 210784 kb
Host smart-e9bd31ed-8156-49b9-a3c5-9b70b88d4b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989044917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2989044917
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3412670220
Short name T369
Test name
Test status
Simulation time 391787984 ps
CPU time 2.16 seconds
Started Mar 14 12:32:18 PM PDT 24
Finished Mar 14 12:32:20 PM PDT 24
Peak memory 200736 kb
Host smart-0cc0851f-6eea-4efa-b6cc-0977e752c06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412670220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3412670220
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1626509242
Short name T9
Test name
Test status
Simulation time 137317754 ps
CPU time 1.08 seconds
Started Mar 14 12:32:24 PM PDT 24
Finished Mar 14 12:32:31 PM PDT 24
Peak memory 200500 kb
Host smart-50b76179-1431-4ae8-8aff-b1dccef1ba04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626509242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1626509242
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1223925493
Short name T478
Test name
Test status
Simulation time 63734078 ps
CPU time 0.73 seconds
Started Mar 14 12:32:05 PM PDT 24
Finished Mar 14 12:32:07 PM PDT 24
Peak memory 200544 kb
Host smart-cadd812e-4e52-4cc0-bac9-f908f7fc9708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223925493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1223925493
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1501833904
Short name T307
Test name
Test status
Simulation time 244448161 ps
CPU time 1.08 seconds
Started Mar 14 12:32:21 PM PDT 24
Finished Mar 14 12:32:22 PM PDT 24
Peak memory 218064 kb
Host smart-626062f6-b985-4a8c-b4c0-6da4cdad073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501833904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1501833904
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1208303366
Short name T167
Test name
Test status
Simulation time 147244495 ps
CPU time 0.8 seconds
Started Mar 14 12:32:38 PM PDT 24
Finished Mar 14 12:32:39 PM PDT 24
Peak memory 200608 kb
Host smart-61084c39-77fe-4a39-aac0-45db6b66e5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208303366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1208303366
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3188342904
Short name T447
Test name
Test status
Simulation time 1874712001 ps
CPU time 6.59 seconds
Started Mar 14 12:32:22 PM PDT 24
Finished Mar 14 12:32:29 PM PDT 24
Peak memory 200992 kb
Host smart-37430654-fb9b-4a33-ae51-16f699b81e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188342904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3188342904
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2972082538
Short name T429
Test name
Test status
Simulation time 147734507 ps
CPU time 1.16 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200880 kb
Host smart-fdda2db1-bc46-4209-af05-c530bfe06ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972082538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2972082538
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3889756005
Short name T133
Test name
Test status
Simulation time 124827512 ps
CPU time 1.17 seconds
Started Mar 14 12:32:19 PM PDT 24
Finished Mar 14 12:32:20 PM PDT 24
Peak memory 200956 kb
Host smart-9f1f9870-709c-46ec-89cd-9045bdd03846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889756005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3889756005
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4108774463
Short name T304
Test name
Test status
Simulation time 3280093454 ps
CPU time 14.49 seconds
Started Mar 14 12:32:21 PM PDT 24
Finished Mar 14 12:32:36 PM PDT 24
Peak memory 201144 kb
Host smart-d3f68050-6f59-40fa-903b-bdc4e2f44392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108774463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4108774463
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.214169886
Short name T73
Test name
Test status
Simulation time 341407552 ps
CPU time 2.2 seconds
Started Mar 14 12:32:32 PM PDT 24
Finished Mar 14 12:32:34 PM PDT 24
Peak memory 200884 kb
Host smart-4790e148-9317-4f20-bbbc-a39aa50cba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214169886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.214169886
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3824494791
Short name T451
Test name
Test status
Simulation time 92288503 ps
CPU time 0.83 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200840 kb
Host smart-198b4458-0f71-44e2-8e50-dc6826f6841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824494791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3824494791
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.294120136
Short name T58
Test name
Test status
Simulation time 67775761 ps
CPU time 0.71 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:12 PM PDT 24
Peak memory 200652 kb
Host smart-70f8710d-a43c-4fdf-9de8-d4ef31022657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294120136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.294120136
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.4202131334
Short name T30
Test name
Test status
Simulation time 2362001308 ps
CPU time 7.98 seconds
Started Mar 14 12:32:15 PM PDT 24
Finished Mar 14 12:32:33 PM PDT 24
Peak memory 223016 kb
Host smart-5389157e-1ee9-4307-ac51-9626c212a8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202131334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4202131334
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3497172941
Short name T256
Test name
Test status
Simulation time 244708459 ps
CPU time 1.08 seconds
Started Mar 14 12:32:16 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 218176 kb
Host smart-56544794-6b65-4d6b-836b-67d75a577b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497172941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3497172941
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2038395290
Short name T303
Test name
Test status
Simulation time 112073277 ps
CPU time 0.76 seconds
Started Mar 14 12:32:40 PM PDT 24
Finished Mar 14 12:32:41 PM PDT 24
Peak memory 200608 kb
Host smart-4f98e5b0-68a2-4192-9b94-7702683db2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038395290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2038395290
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1428351789
Short name T143
Test name
Test status
Simulation time 948368318 ps
CPU time 4.54 seconds
Started Mar 14 12:32:06 PM PDT 24
Finished Mar 14 12:32:11 PM PDT 24
Peak memory 201080 kb
Host smart-a8e066fa-451b-4c8b-9497-75a64e50d1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428351789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1428351789
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3093333465
Short name T384
Test name
Test status
Simulation time 103232704 ps
CPU time 0.98 seconds
Started Mar 14 12:32:24 PM PDT 24
Finished Mar 14 12:32:26 PM PDT 24
Peak memory 200752 kb
Host smart-db81d8f8-39af-41e7-9d6e-3e5a3f5dede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093333465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3093333465
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3552660310
Short name T233
Test name
Test status
Simulation time 238532967 ps
CPU time 1.54 seconds
Started Mar 14 12:32:05 PM PDT 24
Finished Mar 14 12:32:06 PM PDT 24
Peak memory 200960 kb
Host smart-2a1df503-e8d5-4710-bab9-4352d5549c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552660310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3552660310
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1238323250
Short name T468
Test name
Test status
Simulation time 2996883679 ps
CPU time 10.34 seconds
Started Mar 14 12:32:26 PM PDT 24
Finished Mar 14 12:32:37 PM PDT 24
Peak memory 201140 kb
Host smart-fcf4f07e-a3ff-4cf1-abf1-bfdf8e913349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238323250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1238323250
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2135843545
Short name T242
Test name
Test status
Simulation time 345917007 ps
CPU time 2.18 seconds
Started Mar 14 12:32:18 PM PDT 24
Finished Mar 14 12:32:20 PM PDT 24
Peak memory 200796 kb
Host smart-9f84fc29-e765-44a8-92ee-804ce4389a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135843545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2135843545
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3746785623
Short name T188
Test name
Test status
Simulation time 91942215 ps
CPU time 0.92 seconds
Started Mar 14 12:32:17 PM PDT 24
Finished Mar 14 12:32:18 PM PDT 24
Peak memory 200804 kb
Host smart-a9d7a9da-bf5f-4782-a8f2-2689076bd746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746785623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3746785623
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.4172203448
Short name T189
Test name
Test status
Simulation time 75249450 ps
CPU time 0.78 seconds
Started Mar 14 12:31:07 PM PDT 24
Finished Mar 14 12:31:08 PM PDT 24
Peak memory 200692 kb
Host smart-a90bcee2-1fb4-4905-a06a-4439a77ade62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172203448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4172203448
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3724216932
Short name T418
Test name
Test status
Simulation time 1214672458 ps
CPU time 5.8 seconds
Started Mar 14 12:31:10 PM PDT 24
Finished Mar 14 12:31:16 PM PDT 24
Peak memory 217684 kb
Host smart-eb2cd123-205f-4b64-b053-f588c729ed02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724216932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3724216932
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.647751456
Short name T184
Test name
Test status
Simulation time 243985364 ps
CPU time 1.07 seconds
Started Mar 14 12:31:08 PM PDT 24
Finished Mar 14 12:31:09 PM PDT 24
Peak memory 218148 kb
Host smart-5d3aff74-62f3-4f97-b8c8-7b899e0c939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647751456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.647751456
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2483321887
Short name T174
Test name
Test status
Simulation time 143575657 ps
CPU time 0.81 seconds
Started Mar 14 12:31:12 PM PDT 24
Finished Mar 14 12:31:14 PM PDT 24
Peak memory 200556 kb
Host smart-f4b59a03-481a-487b-810b-df0d5bac6efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483321887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2483321887
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.495095174
Short name T85
Test name
Test status
Simulation time 862127091 ps
CPU time 4.03 seconds
Started Mar 14 12:31:20 PM PDT 24
Finished Mar 14 12:31:24 PM PDT 24
Peak memory 200884 kb
Host smart-078c2f29-f438-4e83-b6e0-67897c81ab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495095174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.495095174
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2786168320
Short name T534
Test name
Test status
Simulation time 141733109 ps
CPU time 1.02 seconds
Started Mar 14 12:31:23 PM PDT 24
Finished Mar 14 12:31:24 PM PDT 24
Peak memory 200684 kb
Host smart-712e37a7-c740-4fbd-b706-badc7f393f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786168320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2786168320
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.775072588
Short name T537
Test name
Test status
Simulation time 119657093 ps
CPU time 1.15 seconds
Started Mar 14 12:31:13 PM PDT 24
Finished Mar 14 12:31:15 PM PDT 24
Peak memory 200928 kb
Host smart-3befb2cd-0f73-422f-b2fb-fb7f486b366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775072588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.775072588
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.677779804
Short name T322
Test name
Test status
Simulation time 9063644552 ps
CPU time 29.89 seconds
Started Mar 14 12:31:22 PM PDT 24
Finished Mar 14 12:31:52 PM PDT 24
Peak memory 209332 kb
Host smart-158fdc9b-b8df-4865-a7cb-3b9e3eb87e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677779804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.677779804
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1471750028
Short name T338
Test name
Test status
Simulation time 493491323 ps
CPU time 2.52 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:27 PM PDT 24
Peak memory 200684 kb
Host smart-2dc8f93a-9ec3-4f1c-a796-ab8aff33e96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471750028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1471750028
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2179692257
Short name T480
Test name
Test status
Simulation time 165706081 ps
CPU time 1.3 seconds
Started Mar 14 12:31:08 PM PDT 24
Finished Mar 14 12:31:09 PM PDT 24
Peak memory 200944 kb
Host smart-518360dd-0c9e-4e79-829d-7ce788845897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179692257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2179692257
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3559802740
Short name T340
Test name
Test status
Simulation time 79148437 ps
CPU time 0.8 seconds
Started Mar 14 12:31:25 PM PDT 24
Finished Mar 14 12:31:26 PM PDT 24
Peak memory 200560 kb
Host smart-50eb7c44-4658-4714-a90a-24c7995155b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559802740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3559802740
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1437663325
Short name T31
Test name
Test status
Simulation time 1226542867 ps
CPU time 5.9 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 217632 kb
Host smart-a2688786-4266-4f1d-9500-37e2cf9fc581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437663325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1437663325
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2725208699
Short name T163
Test name
Test status
Simulation time 244208799 ps
CPU time 1.1 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 218112 kb
Host smart-0d34abf6-1934-4326-8841-66d4a14f0f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725208699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2725208699
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3308824040
Short name T13
Test name
Test status
Simulation time 194291844 ps
CPU time 0.88 seconds
Started Mar 14 12:31:12 PM PDT 24
Finished Mar 14 12:31:14 PM PDT 24
Peak memory 200608 kb
Host smart-fc22a4a5-5e6f-43ea-ab58-86e536cf9bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308824040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3308824040
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1638648145
Short name T412
Test name
Test status
Simulation time 1598784194 ps
CPU time 6.02 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 201032 kb
Host smart-d0b173d4-3cbc-47b0-881b-c51f0194b8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638648145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1638648145
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1989951725
Short name T292
Test name
Test status
Simulation time 169531729 ps
CPU time 1.18 seconds
Started Mar 14 12:31:22 PM PDT 24
Finished Mar 14 12:31:24 PM PDT 24
Peak memory 200772 kb
Host smart-715effc8-0eae-493a-a73b-957bcdcd881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989951725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1989951725
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2443705316
Short name T231
Test name
Test status
Simulation time 250622951 ps
CPU time 1.41 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:26 PM PDT 24
Peak memory 200980 kb
Host smart-9c8ab5cc-1af2-4a11-b578-a86aba93f3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443705316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2443705316
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1594490380
Short name T2
Test name
Test status
Simulation time 3496851833 ps
CPU time 12.74 seconds
Started Mar 14 12:31:43 PM PDT 24
Finished Mar 14 12:31:56 PM PDT 24
Peak memory 201088 kb
Host smart-d519bbaa-6937-40c1-9a10-96068912320c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594490380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1594490380
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.897301328
Short name T461
Test name
Test status
Simulation time 140576717 ps
CPU time 1.71 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:26 PM PDT 24
Peak memory 208948 kb
Host smart-d6d0a4e3-b312-48b4-a4b5-afe2042aaad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897301328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.897301328
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4284955313
Short name T481
Test name
Test status
Simulation time 89821148 ps
CPU time 0.85 seconds
Started Mar 14 12:31:23 PM PDT 24
Finished Mar 14 12:31:24 PM PDT 24
Peak memory 200800 kb
Host smart-61c51938-9d89-4c06-85a1-67aa070f23bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284955313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4284955313
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1939034597
Short name T312
Test name
Test status
Simulation time 64619939 ps
CPU time 0.73 seconds
Started Mar 14 12:31:25 PM PDT 24
Finished Mar 14 12:31:26 PM PDT 24
Peak memory 200560 kb
Host smart-88db2d91-36c1-4f4d-a954-974dec55200d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939034597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1939034597
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1192631112
Short name T43
Test name
Test status
Simulation time 1888044428 ps
CPU time 7.61 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 218588 kb
Host smart-22bd8ca0-9991-49bf-9a98-2ac6c8b5d09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192631112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1192631112
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3522080427
Short name T344
Test name
Test status
Simulation time 243830712 ps
CPU time 1.06 seconds
Started Mar 14 12:31:33 PM PDT 24
Finished Mar 14 12:31:34 PM PDT 24
Peak memory 217904 kb
Host smart-efea8272-968b-4a94-895d-3a9e8f4deb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522080427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3522080427
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.4059611179
Short name T426
Test name
Test status
Simulation time 115660158 ps
CPU time 0.84 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:31 PM PDT 24
Peak memory 200592 kb
Host smart-b218b503-ceab-4340-809f-07424be33190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059611179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.4059611179
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2682663726
Short name T405
Test name
Test status
Simulation time 1188874376 ps
CPU time 4.96 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 200952 kb
Host smart-0be51892-16f0-4de5-985c-e517cdeb8d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682663726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2682663726
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.773564163
Short name T417
Test name
Test status
Simulation time 145827876 ps
CPU time 1.07 seconds
Started Mar 14 12:31:29 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 200876 kb
Host smart-98b268e7-4736-4dd4-a159-bc8c00babea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773564163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.773564163
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2050880636
Short name T374
Test name
Test status
Simulation time 251816554 ps
CPU time 1.53 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 200988 kb
Host smart-66968ad0-ed8a-4b8e-a755-e8da960dccf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050880636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2050880636
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.878012331
Short name T357
Test name
Test status
Simulation time 11640712388 ps
CPU time 40.78 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:32:08 PM PDT 24
Peak memory 201100 kb
Host smart-6d547ad3-9a69-475a-920e-253dff959e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878012331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.878012331
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.832746394
Short name T300
Test name
Test status
Simulation time 345165561 ps
CPU time 2.28 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:35 PM PDT 24
Peak memory 200800 kb
Host smart-da1f8551-4eef-46c0-844c-e220b5a274ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832746394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.832746394
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1201195926
Short name T10
Test name
Test status
Simulation time 219539262 ps
CPU time 1.35 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200756 kb
Host smart-4482985b-8304-4511-923d-0b2a1dafeb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201195926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1201195926
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1794428152
Short name T228
Test name
Test status
Simulation time 59707356 ps
CPU time 0.74 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:31 PM PDT 24
Peak memory 200572 kb
Host smart-483d47f9-8fad-4f49-a567-cd7740b34a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794428152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1794428152
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.652452796
Short name T28
Test name
Test status
Simulation time 2365926101 ps
CPU time 8.11 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:36 PM PDT 24
Peak memory 222416 kb
Host smart-fb5f39f1-f663-46b9-912d-07014c366460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652452796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.652452796
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2629109841
Short name T23
Test name
Test status
Simulation time 243654206 ps
CPU time 1.04 seconds
Started Mar 14 12:31:41 PM PDT 24
Finished Mar 14 12:31:48 PM PDT 24
Peak memory 218024 kb
Host smart-d38625c6-73b1-4aba-8da9-3b0994fab1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629109841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2629109841
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3234633448
Short name T361
Test name
Test status
Simulation time 73575178 ps
CPU time 0.77 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:31 PM PDT 24
Peak memory 200520 kb
Host smart-a74c10aa-e376-477d-9058-e34cd9f3d2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234633448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3234633448
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.686096352
Short name T402
Test name
Test status
Simulation time 1057622572 ps
CPU time 5.45 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:30 PM PDT 24
Peak memory 201000 kb
Host smart-e6708db0-e7a1-477d-aedc-f9f36b204f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686096352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.686096352
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2691221094
Short name T394
Test name
Test status
Simulation time 177405926 ps
CPU time 1.19 seconds
Started Mar 14 12:31:28 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 200720 kb
Host smart-1afd2685-919d-49b0-bc5f-e9eb6169a649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691221094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2691221094
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.473318165
Short name T494
Test name
Test status
Simulation time 181982536 ps
CPU time 1.3 seconds
Started Mar 14 12:31:14 PM PDT 24
Finished Mar 14 12:31:15 PM PDT 24
Peak memory 201076 kb
Host smart-95e2fbb6-d64a-49f8-bcc3-a023c0985335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473318165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.473318165
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1787557319
Short name T227
Test name
Test status
Simulation time 1878750628 ps
CPU time 8.32 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:36 PM PDT 24
Peak memory 200956 kb
Host smart-d82058e2-3055-42ee-8dee-b5d8427d6b5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787557319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1787557319
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1126350758
Short name T457
Test name
Test status
Simulation time 291996204 ps
CPU time 2 seconds
Started Mar 14 12:31:56 PM PDT 24
Finished Mar 14 12:31:59 PM PDT 24
Peak memory 208996 kb
Host smart-6e10824f-4adb-4f61-8160-2f84dc2d737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126350758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1126350758
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3714106734
Short name T64
Test name
Test status
Simulation time 200493858 ps
CPU time 1.26 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 200864 kb
Host smart-bae996e7-a6e1-4c1a-91c4-81a3b7a00d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714106734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3714106734
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1325831464
Short name T485
Test name
Test status
Simulation time 74195210 ps
CPU time 0.76 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 200696 kb
Host smart-42ac14c6-0338-4f68-943a-6d7e67af675c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325831464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1325831464
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1152655811
Short name T172
Test name
Test status
Simulation time 243531439 ps
CPU time 1.22 seconds
Started Mar 14 12:31:27 PM PDT 24
Finished Mar 14 12:31:28 PM PDT 24
Peak memory 218068 kb
Host smart-a21a35bc-68e1-4d36-9e8a-e63c787a50b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152655811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1152655811
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1628074246
Short name T216
Test name
Test status
Simulation time 138412764 ps
CPU time 0.79 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:31 PM PDT 24
Peak memory 200628 kb
Host smart-d5936def-9ee0-4297-a6a5-5cdf73c53ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628074246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1628074246
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3241572267
Short name T281
Test name
Test status
Simulation time 954292629 ps
CPU time 4.65 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:29 PM PDT 24
Peak memory 201012 kb
Host smart-d5afb74a-8d9f-48b5-b3e5-65c81d60717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241572267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3241572267
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1502293110
Short name T363
Test name
Test status
Simulation time 161910295 ps
CPU time 1.12 seconds
Started Mar 14 12:31:31 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 200844 kb
Host smart-aa48ae0a-6f0e-46e5-8a1e-dce0c4499c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502293110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1502293110
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3075455658
Short name T284
Test name
Test status
Simulation time 205366707 ps
CPU time 1.4 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 201072 kb
Host smart-70997691-b5fa-4988-bf13-17e87a895486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075455658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3075455658
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.825134520
Short name T495
Test name
Test status
Simulation time 10633578049 ps
CPU time 38.87 seconds
Started Mar 14 12:31:25 PM PDT 24
Finished Mar 14 12:32:04 PM PDT 24
Peak memory 201060 kb
Host smart-35e16690-08a6-4ea2-8a5e-3ac89101fa14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825134520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.825134520
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.20774647
Short name T291
Test name
Test status
Simulation time 373652809 ps
CPU time 2.48 seconds
Started Mar 14 12:31:30 PM PDT 24
Finished Mar 14 12:31:33 PM PDT 24
Peak memory 200752 kb
Host smart-eb18927c-5072-4d6a-99aa-b89533581c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20774647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.20774647
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1990589322
Short name T266
Test name
Test status
Simulation time 154610052 ps
CPU time 1.2 seconds
Started Mar 14 12:31:24 PM PDT 24
Finished Mar 14 12:31:25 PM PDT 24
Peak memory 201012 kb
Host smart-f3e88eab-c831-441e-b25e-893779ff8599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990589322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1990589322
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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