Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7960

1

T2

19

T3

17

T5

196

auto[1]

10878

1

T2

82

T3

1

T5

171

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5858	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6357	1			T1	1		T2	27		T3	1
reset_info_cp[2]	2913	1			T2	19		T5	64		T7	1
reset_info_cp[4]	3740	1			T2	13		T5	82		T7	1
reset_info_cp[8]	106	1			T5	3		T12	4		T13	1
reset_info_cp[16]	124	1			T5	2		T12	1		T14	2
reset_info_cp[32]	120	1			T3	1		T5	1		T7	1
reset_info_cp[64]	113	1			T2	1		T14	2		T23	1
reset_info_cp[128]	127	1			T2	2		T5	2		T12	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3083	1			T2	19		T5	63		T12	29
reset_info_cp[1]	auto[1]	2654	1			T2	7		T5	52		T7	1
reset_info_cp[2]	auto[0]	885	1			T5	28		T12	13		T14	15
reset_info_cp[2]	auto[1]	2028	1			T2	19		T5	36		T7	1
reset_info_cp[4]	auto[0]	1296	1			T5	35		T12	17		T14	28
reset_info_cp[4]	auto[1]	2444	1			T2	13		T5	47		T7	1
reset_info_cp[8]	auto[0]	33	1			T5	3		T12	1		T83	1
reset_info_cp[8]	auto[1]	73	1			T12	3		T13	1		T75	1
reset_info_cp[16]	auto[0]	53	1			T5	1		T14	1		T83	1
reset_info_cp[16]	auto[1]	71	1			T5	1		T12	1		T14	1
reset_info_cp[32]	auto[0]	41	1			T3	1		T12	1		T129	1
reset_info_cp[32]	auto[1]	79	1			T5	1		T7	1		T12	1
reset_info_cp[64]	auto[0]	49	1			T14	2		T45	1		T85	2
reset_info_cp[64]	auto[1]	64	1			T2	1		T23	1		T27	1
reset_info_cp[128]	auto[0]	49	1			T5	2		T14	1		T23	1
reset_info_cp[128]	auto[1]	78	1			T2	2		T12	2		T45	1