Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T541 /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2724447924 Mar 17 03:04:47 PM PDT 24 Mar 17 03:04:49 PM PDT 24 128527284 ps
T542 /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1407286899 Mar 17 03:04:37 PM PDT 24 Mar 17 03:04:38 PM PDT 24 244446745 ps
T543 /workspace/coverage/default/48.rstmgr_stress_all.34682146 Mar 17 03:05:30 PM PDT 24 Mar 17 03:05:47 PM PDT 24 3711191916 ps
T544 /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1330863497 Mar 17 03:05:13 PM PDT 24 Mar 17 03:05:15 PM PDT 24 95246667 ps
T545 /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3004233949 Mar 17 03:05:17 PM PDT 24 Mar 17 03:05:18 PM PDT 24 113991311 ps
T50 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3978404222 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:33 PM PDT 24 84742102 ps
T51 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3485990841 Mar 17 12:57:25 PM PDT 24 Mar 17 12:57:29 PM PDT 24 1408885324 ps
T52 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1012165901 Mar 17 12:57:26 PM PDT 24 Mar 17 12:57:29 PM PDT 24 865569411 ps
T546 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1494661748 Mar 17 12:57:28 PM PDT 24 Mar 17 12:57:29 PM PDT 24 77984130 ps
T53 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2972234807 Mar 17 12:57:30 PM PDT 24 Mar 17 12:57:33 PM PDT 24 244042696 ps
T61 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1641675514 Mar 17 12:57:22 PM PDT 24 Mar 17 12:57:24 PM PDT 24 479114320 ps
T93 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3459127523 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:32 PM PDT 24 75690338 ps
T54 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3744069616 Mar 17 12:57:35 PM PDT 24 Mar 17 12:57:37 PM PDT 24 248988069 ps
T55 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1111787319 Mar 17 12:57:34 PM PDT 24 Mar 17 12:57:35 PM PDT 24 124994356 ps
T77 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.812195276 Mar 17 12:57:27 PM PDT 24 Mar 17 12:57:29 PM PDT 24 101990372 ps
T94 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.366630978 Mar 17 12:57:37 PM PDT 24 Mar 17 12:57:38 PM PDT 24 82907403 ps
T78 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3322169 Mar 17 12:57:37 PM PDT 24 Mar 17 12:57:39 PM PDT 24 204241350 ps
T79 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.861095239 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:32 PM PDT 24 129497253 ps
T547 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1776522147 Mar 17 12:57:21 PM PDT 24 Mar 17 12:57:22 PM PDT 24 99399751 ps
T80 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3137210810 Mar 17 12:57:21 PM PDT 24 Mar 17 12:57:24 PM PDT 24 493779963 ps
T95 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2043308476 Mar 17 12:57:24 PM PDT 24 Mar 17 12:57:26 PM PDT 24 195565692 ps
T96 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1555390251 Mar 17 12:57:33 PM PDT 24 Mar 17 12:57:34 PM PDT 24 102455979 ps
T97 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2214999308 Mar 17 12:57:34 PM PDT 24 Mar 17 12:57:36 PM PDT 24 249529908 ps
T548 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2243447284 Mar 17 12:57:25 PM PDT 24 Mar 17 12:57:26 PM PDT 24 65487967 ps
T81 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3159095123 Mar 17 12:57:23 PM PDT 24 Mar 17 12:57:25 PM PDT 24 190953466 ps
T549 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3180118291 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:29 PM PDT 24 101529154 ps
T550 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3357672026 Mar 17 12:57:20 PM PDT 24 Mar 17 12:57:26 PM PDT 24 1173040694 ps
T98 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3559194783 Mar 17 12:57:33 PM PDT 24 Mar 17 12:57:34 PM PDT 24 58938678 ps
T105 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.220978936 Mar 17 12:57:34 PM PDT 24 Mar 17 12:57:37 PM PDT 24 876114673 ps
T551 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.52658209 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:33 PM PDT 24 64405085 ps
T99 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2285850239 Mar 17 12:57:28 PM PDT 24 Mar 17 12:57:29 PM PDT 24 82538893 ps
T82 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2955950844 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:33 PM PDT 24 210033492 ps
T552 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3697246547 Mar 17 12:57:22 PM PDT 24 Mar 17 12:57:25 PM PDT 24 265611648 ps
T100 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.225951404 Mar 17 12:57:33 PM PDT 24 Mar 17 12:57:34 PM PDT 24 75570560 ps
T553 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1259234244 Mar 17 12:57:34 PM PDT 24 Mar 17 12:57:35 PM PDT 24 66820808 ps
T101 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.927972528 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:31 PM PDT 24 230114403 ps
T115 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2162712408 Mar 17 12:57:38 PM PDT 24 Mar 17 12:57:40 PM PDT 24 507206396 ps
T554 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.420364573 Mar 17 12:57:21 PM PDT 24 Mar 17 12:57:22 PM PDT 24 65326419 ps
T555 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2434211022 Mar 17 12:57:28 PM PDT 24 Mar 17 12:57:29 PM PDT 24 86369879 ps
T111 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.914259868 Mar 17 12:57:33 PM PDT 24 Mar 17 12:57:35 PM PDT 24 98828965 ps
T556 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1189641039 Mar 17 12:57:39 PM PDT 24 Mar 17 12:57:40 PM PDT 24 108734730 ps
T112 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4214422862 Mar 17 12:57:22 PM PDT 24 Mar 17 12:57:23 PM PDT 24 114771894 ps
T557 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2703552084 Mar 17 12:57:37 PM PDT 24 Mar 17 12:57:38 PM PDT 24 68232532 ps
T558 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1419075518 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:33 PM PDT 24 67897910 ps
T106 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.539622654 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:33 PM PDT 24 598567865 ps
T559 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2038655701 Mar 17 12:57:37 PM PDT 24 Mar 17 12:57:39 PM PDT 24 113238854 ps
T560 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.459035759 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:34 PM PDT 24 275619560 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1707415752 Mar 17 12:57:25 PM PDT 24 Mar 17 12:57:31 PM PDT 24 476900648 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4006104789 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:31 PM PDT 24 132951717 ps
T563 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3165721985 Mar 17 12:57:33 PM PDT 24 Mar 17 12:57:36 PM PDT 24 390696501 ps
T114 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1097263089 Mar 17 12:57:25 PM PDT 24 Mar 17 12:57:27 PM PDT 24 173696085 ps
T113 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1348537733 Mar 17 12:57:28 PM PDT 24 Mar 17 12:57:31 PM PDT 24 795337613 ps
T564 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2562016262 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:34 PM PDT 24 801879441 ps
T565 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2771120266 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:33 PM PDT 24 90080722 ps
T110 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.298576811 Mar 17 12:57:24 PM PDT 24 Mar 17 12:57:27 PM PDT 24 379317498 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3581553300 Mar 17 12:57:26 PM PDT 24 Mar 17 12:57:28 PM PDT 24 195656854 ps
T127 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1172207162 Mar 17 12:57:27 PM PDT 24 Mar 17 12:57:30 PM PDT 24 823124685 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2051988090 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:38 PM PDT 24 1184040011 ps
T568 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2877849509 Mar 17 12:57:24 PM PDT 24 Mar 17 12:57:26 PM PDT 24 130606202 ps
T108 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4126275477 Mar 17 12:57:24 PM PDT 24 Mar 17 12:57:27 PM PDT 24 790962636 ps
T569 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3615923121 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:33 PM PDT 24 71826240 ps
T570 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2182122336 Mar 17 12:57:27 PM PDT 24 Mar 17 12:57:29 PM PDT 24 107151219 ps
T571 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1780293455 Mar 17 12:57:30 PM PDT 24 Mar 17 12:57:32 PM PDT 24 134196053 ps
T572 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.660185647 Mar 17 12:57:28 PM PDT 24 Mar 17 12:57:29 PM PDT 24 82114713 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3292651446 Mar 17 12:57:25 PM PDT 24 Mar 17 12:57:26 PM PDT 24 147648451 ps
T574 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.519801361 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:31 PM PDT 24 103205102 ps
T575 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1448559612 Mar 17 12:57:39 PM PDT 24 Mar 17 12:57:41 PM PDT 24 259280564 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3629063375 Mar 17 12:57:23 PM PDT 24 Mar 17 12:57:25 PM PDT 24 134580778 ps
T577 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3710243242 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:32 PM PDT 24 60525207 ps
T578 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2606696126 Mar 17 12:57:37 PM PDT 24 Mar 17 12:57:39 PM PDT 24 188064936 ps
T126 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1872279995 Mar 17 12:57:22 PM PDT 24 Mar 17 12:57:24 PM PDT 24 493781589 ps
T579 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.168855942 Mar 17 12:57:36 PM PDT 24 Mar 17 12:57:37 PM PDT 24 78858269 ps
T580 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3664567595 Mar 17 12:57:34 PM PDT 24 Mar 17 12:57:35 PM PDT 24 139107419 ps
T581 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2655285477 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:33 PM PDT 24 219441072 ps
T582 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1279364641 Mar 17 12:57:25 PM PDT 24 Mar 17 12:57:27 PM PDT 24 235907225 ps
T86 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1584238040 Mar 17 12:57:25 PM PDT 24 Mar 17 12:57:27 PM PDT 24 149785625 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3876560690 Mar 17 12:57:28 PM PDT 24 Mar 17 12:57:29 PM PDT 24 83203683 ps
T584 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.571387458 Mar 17 12:57:34 PM PDT 24 Mar 17 12:57:34 PM PDT 24 60365463 ps
T585 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3263200360 Mar 17 12:57:27 PM PDT 24 Mar 17 12:57:29 PM PDT 24 82236196 ps
T586 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2101762649 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:30 PM PDT 24 131484505 ps
T102 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3763041612 Mar 17 12:57:37 PM PDT 24 Mar 17 12:57:40 PM PDT 24 891287464 ps
T587 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3113043101 Mar 17 12:57:21 PM PDT 24 Mar 17 12:57:22 PM PDT 24 113493830 ps
T588 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.74990300 Mar 17 12:57:24 PM PDT 24 Mar 17 12:57:25 PM PDT 24 84773606 ps
T589 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1060766898 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:34 PM PDT 24 187738955 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3084600382 Mar 17 12:57:25 PM PDT 24 Mar 17 12:57:26 PM PDT 24 80533432 ps
T103 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2113220202 Mar 17 12:57:35 PM PDT 24 Mar 17 12:57:37 PM PDT 24 460415585 ps
T104 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1645344404 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:34 PM PDT 24 794910120 ps
T128 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3334656049 Mar 17 12:57:33 PM PDT 24 Mar 17 12:57:35 PM PDT 24 500117389 ps
T591 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.735138943 Mar 17 12:57:22 PM PDT 24 Mar 17 12:57:23 PM PDT 24 78658633 ps
T109 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.270020712 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:35 PM PDT 24 891459685 ps
T592 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1385789028 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:32 PM PDT 24 107828807 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3825892546 Mar 17 12:57:21 PM PDT 24 Mar 17 12:57:22 PM PDT 24 103324872 ps
T594 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1674083826 Mar 17 12:57:42 PM PDT 24 Mar 17 12:57:44 PM PDT 24 136522994 ps
T595 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1064043809 Mar 17 12:57:33 PM PDT 24 Mar 17 12:57:35 PM PDT 24 185190373 ps
T596 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.804860629 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:33 PM PDT 24 67112313 ps
T597 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1099503007 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:32 PM PDT 24 129695279 ps
T598 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1953757082 Mar 17 12:57:37 PM PDT 24 Mar 17 12:57:38 PM PDT 24 59989872 ps
T599 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3648797754 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:30 PM PDT 24 184166785 ps
T107 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3770203731 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:32 PM PDT 24 787493337 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3786421328 Mar 17 12:57:27 PM PDT 24 Mar 17 12:57:28 PM PDT 24 68026864 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3147643972 Mar 17 12:57:24 PM PDT 24 Mar 17 12:57:26 PM PDT 24 105827273 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.473672113 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:32 PM PDT 24 361913629 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2677296508 Mar 17 12:57:29 PM PDT 24 Mar 17 12:57:30 PM PDT 24 121369287 ps
T604 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2519571984 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:34 PM PDT 24 267083864 ps
T605 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.465783998 Mar 17 12:57:24 PM PDT 24 Mar 17 12:57:26 PM PDT 24 504822596 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1707827313 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:34 PM PDT 24 174648082 ps
T607 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2291452342 Mar 17 12:57:37 PM PDT 24 Mar 17 12:57:39 PM PDT 24 220739585 ps
T608 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2445919198 Mar 17 12:57:20 PM PDT 24 Mar 17 12:57:21 PM PDT 24 91330943 ps
T609 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1424341922 Mar 17 12:57:21 PM PDT 24 Mar 17 12:57:25 PM PDT 24 808081943 ps
T610 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3667336704 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:32 PM PDT 24 74283450 ps
T611 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3179138496 Mar 17 12:57:26 PM PDT 24 Mar 17 12:57:29 PM PDT 24 137030616 ps
T612 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3979452538 Mar 17 12:57:24 PM PDT 24 Mar 17 12:57:27 PM PDT 24 354200831 ps
T613 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3116535226 Mar 17 12:57:32 PM PDT 24 Mar 17 12:57:34 PM PDT 24 481582229 ps
T614 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3123115422 Mar 17 12:57:34 PM PDT 24 Mar 17 12:57:36 PM PDT 24 261317653 ps
T615 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3735753830 Mar 17 12:57:33 PM PDT 24 Mar 17 12:57:36 PM PDT 24 187482790 ps
T616 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.108192588 Mar 17 12:57:33 PM PDT 24 Mar 17 12:57:36 PM PDT 24 941406432 ps
T617 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2636318707 Mar 17 12:57:34 PM PDT 24 Mar 17 12:57:36 PM PDT 24 180738237 ps
T618 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.979826132 Mar 17 12:57:31 PM PDT 24 Mar 17 12:57:32 PM PDT 24 182867336 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1314494869 Mar 17 12:57:30 PM PDT 24 Mar 17 12:57:31 PM PDT 24 138778569 ps
T620 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4099884181 Mar 17 12:57:25 PM PDT 24 Mar 17 12:57:28 PM PDT 24 436411204 ps

Test location /workspace/coverage/default/24.rstmgr_stress_all.255999089
Short name T5
Test name
Test status
Simulation time 6047621548 ps
CPU time 27.84 seconds
Started Mar 17 03:04:43 PM PDT 24
Finished Mar 17 03:05:11 PM PDT 24
Peak memory 201216 kb
Host smart-7e91c69e-05e0-4d02-af06-3aa9f09e28fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255999089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.255999089
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3575713022
Short name T123
Test name
Test status
Simulation time 327695628 ps
CPU time 1.99 seconds
Started Mar 17 03:05:00 PM PDT 24
Finished Mar 17 03:05:03 PM PDT 24
Peak memory 200984 kb
Host smart-11c4f793-a5f6-40de-906b-0a6d55555df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575713022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3575713022
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2050783593
Short name T13
Test name
Test status
Simulation time 1215199313 ps
CPU time 6.3 seconds
Started Mar 17 03:05:19 PM PDT 24
Finished Mar 17 03:05:26 PM PDT 24
Peak memory 218584 kb
Host smart-2abeb530-921a-4f87-a370-827f5036ab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050783593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2050783593
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1012165901
Short name T52
Test name
Test status
Simulation time 865569411 ps
CPU time 2.96 seconds
Started Mar 17 12:57:26 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 200564 kb
Host smart-c695a855-ca65-4e3e-864a-9e2f1348b01f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012165901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1012165901
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3999244411
Short name T56
Test name
Test status
Simulation time 18210053063 ps
CPU time 26.66 seconds
Started Mar 17 03:04:00 PM PDT 24
Finished Mar 17 03:04:28 PM PDT 24
Peak memory 217856 kb
Host smart-6c981a2d-299f-4bd1-b35f-04e3984539e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999244411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3999244411
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3137210810
Short name T80
Test name
Test status
Simulation time 493779963 ps
CPU time 3.26 seconds
Started Mar 17 12:57:21 PM PDT 24
Finished Mar 17 12:57:24 PM PDT 24
Peak memory 208712 kb
Host smart-0b97daab-5b3b-451b-ad19-77e7b5e71b91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137210810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3137210810
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.4062429996
Short name T2
Test name
Test status
Simulation time 1223549814 ps
CPU time 5.59 seconds
Started Mar 17 03:04:32 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 218612 kb
Host smart-55cefe8d-cc53-49be-bbd7-e15d627c656c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062429996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4062429996
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2026859307
Short name T64
Test name
Test status
Simulation time 105738519 ps
CPU time 0.98 seconds
Started Mar 17 03:03:56 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 200880 kb
Host smart-8c2097e1-2e52-4029-956d-ae22b22fcc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026859307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2026859307
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3301662646
Short name T147
Test name
Test status
Simulation time 214409000 ps
CPU time 1.23 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:40 PM PDT 24
Peak memory 200860 kb
Host smart-cc7989da-d78c-4e6b-84af-9ac3d5f87762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301662646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3301662646
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3888162811
Short name T187
Test name
Test status
Simulation time 64618643 ps
CPU time 0.76 seconds
Started Mar 17 03:04:27 PM PDT 24
Finished Mar 17 03:04:27 PM PDT 24
Peak memory 200676 kb
Host smart-7316368b-4121-4ebb-b38e-f36937aac8b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888162811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3888162811
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1872279995
Short name T126
Test name
Test status
Simulation time 493781589 ps
CPU time 1.98 seconds
Started Mar 17 12:57:22 PM PDT 24
Finished Mar 17 12:57:24 PM PDT 24
Peak memory 200588 kb
Host smart-c5e9f354-d0c2-415f-b885-b378b1e24741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872279995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1872279995
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.298576811
Short name T110
Test name
Test status
Simulation time 379317498 ps
CPU time 2.48 seconds
Started Mar 17 12:57:24 PM PDT 24
Finished Mar 17 12:57:27 PM PDT 24
Peak memory 216832 kb
Host smart-07c51c7f-fb11-42d9-b066-94aab2337e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298576811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.298576811
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1496688908
Short name T31
Test name
Test status
Simulation time 2367500393 ps
CPU time 9.1 seconds
Started Mar 17 03:04:22 PM PDT 24
Finished Mar 17 03:04:31 PM PDT 24
Peak memory 217956 kb
Host smart-d87f65af-94e4-4a38-9caa-a72031cb10b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496688908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1496688908
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4142103444
Short name T117
Test name
Test status
Simulation time 1667910811 ps
CPU time 5.89 seconds
Started Mar 17 03:04:31 PM PDT 24
Finished Mar 17 03:04:37 PM PDT 24
Peak memory 201100 kb
Host smart-2addc583-d5ee-47ed-85c2-4d5381c8102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142103444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4142103444
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3485990841
Short name T51
Test name
Test status
Simulation time 1408885324 ps
CPU time 3.81 seconds
Started Mar 17 12:57:25 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 200480 kb
Host smart-013edc56-5f93-47b6-9044-0a05e7dc2d85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485990841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3485990841
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.366630978
Short name T94
Test name
Test status
Simulation time 82907403 ps
CPU time 0.86 seconds
Started Mar 17 12:57:37 PM PDT 24
Finished Mar 17 12:57:38 PM PDT 24
Peak memory 200256 kb
Host smart-12b3d032-5615-4b5b-ba0e-8e8f2a859a29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366630978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.366630978
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3027263636
Short name T16
Test name
Test status
Simulation time 194484587 ps
CPU time 0.88 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:40 PM PDT 24
Peak memory 200712 kb
Host smart-c57d53d9-5b6a-47a3-990a-340ef4c9aac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027263636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3027263636
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3692231321
Short name T36
Test name
Test status
Simulation time 2185881265 ps
CPU time 8.62 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:42 PM PDT 24
Peak memory 218180 kb
Host smart-596f7cb3-682e-4afb-b084-3933e43ece19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692231321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3692231321
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1641675514
Short name T61
Test name
Test status
Simulation time 479114320 ps
CPU time 1.95 seconds
Started Mar 17 12:57:22 PM PDT 24
Finished Mar 17 12:57:24 PM PDT 24
Peak memory 200552 kb
Host smart-1e709a94-0bf2-419c-b327-f832f08f9754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641675514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1641675514
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.220978936
Short name T105
Test name
Test status
Simulation time 876114673 ps
CPU time 3.12 seconds
Started Mar 17 12:57:34 PM PDT 24
Finished Mar 17 12:57:37 PM PDT 24
Peak memory 200560 kb
Host smart-109b9738-02fe-4b22-a720-edd3443fa2bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220978936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.220978936
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2291452342
Short name T607
Test name
Test status
Simulation time 220739585 ps
CPU time 1.79 seconds
Started Mar 17 12:57:37 PM PDT 24
Finished Mar 17 12:57:39 PM PDT 24
Peak memory 216848 kb
Host smart-e967410b-c901-4bd0-8103-285dd401c768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291452342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2291452342
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3979452538
Short name T612
Test name
Test status
Simulation time 354200831 ps
CPU time 2.41 seconds
Started Mar 17 12:57:24 PM PDT 24
Finished Mar 17 12:57:27 PM PDT 24
Peak memory 208688 kb
Host smart-2211826b-20de-4926-8800-3322b08d276f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979452538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
979452538
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1707415752
Short name T561
Test name
Test status
Simulation time 476900648 ps
CPU time 5.79 seconds
Started Mar 17 12:57:25 PM PDT 24
Finished Mar 17 12:57:31 PM PDT 24
Peak memory 200376 kb
Host smart-2b1b07f7-d5e4-46de-854c-a7f7e59b5913
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707415752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
707415752
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3292651446
Short name T573
Test name
Test status
Simulation time 147648451 ps
CPU time 0.95 seconds
Started Mar 17 12:57:25 PM PDT 24
Finished Mar 17 12:57:26 PM PDT 24
Peak memory 200324 kb
Host smart-653746c1-9a9c-4311-91d1-62e34e89058e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292651446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
292651446
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3159095123
Short name T81
Test name
Test status
Simulation time 190953466 ps
CPU time 1.31 seconds
Started Mar 17 12:57:23 PM PDT 24
Finished Mar 17 12:57:25 PM PDT 24
Peak memory 208668 kb
Host smart-d6d1942a-26a2-4486-a49f-e58d7c1719eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159095123 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3159095123
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.735138943
Short name T591
Test name
Test status
Simulation time 78658633 ps
CPU time 0.88 seconds
Started Mar 17 12:57:22 PM PDT 24
Finished Mar 17 12:57:23 PM PDT 24
Peak memory 200232 kb
Host smart-3b7a113c-4d80-4c65-921e-ee5ae1a690b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735138943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.735138943
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2445919198
Short name T608
Test name
Test status
Simulation time 91330943 ps
CPU time 1.01 seconds
Started Mar 17 12:57:20 PM PDT 24
Finished Mar 17 12:57:21 PM PDT 24
Peak memory 200436 kb
Host smart-11615c47-98dc-4007-bd75-d6dcae9233c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445919198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2445919198
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1780293455
Short name T571
Test name
Test status
Simulation time 134196053 ps
CPU time 1.88 seconds
Started Mar 17 12:57:30 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 208684 kb
Host smart-a5f6ae9d-ea3f-4df1-8e0c-794b150a9d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780293455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1780293455
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.465783998
Short name T605
Test name
Test status
Simulation time 504822596 ps
CPU time 2.08 seconds
Started Mar 17 12:57:24 PM PDT 24
Finished Mar 17 12:57:26 PM PDT 24
Peak memory 200536 kb
Host smart-e36f9e83-3f1f-4ed1-bb27-cd4387988d20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465783998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.
465783998
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.519801361
Short name T574
Test name
Test status
Simulation time 103205102 ps
CPU time 1.27 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:31 PM PDT 24
Peak memory 200508 kb
Host smart-d1c0a410-bbc4-40b4-8f18-6f3d2d1c2cba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519801361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.519801361
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3697246547
Short name T552
Test name
Test status
Simulation time 265611648 ps
CPU time 3.13 seconds
Started Mar 17 12:57:22 PM PDT 24
Finished Mar 17 12:57:25 PM PDT 24
Peak memory 200540 kb
Host smart-fa36b2e3-a579-4b26-b2b2-559cdbe529a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697246547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
697246547
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2877849509
Short name T568
Test name
Test status
Simulation time 130606202 ps
CPU time 0.97 seconds
Started Mar 17 12:57:24 PM PDT 24
Finished Mar 17 12:57:26 PM PDT 24
Peak memory 200292 kb
Host smart-bb3b94fe-7f0e-4a22-a55c-07858a33551a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877849509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
877849509
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3113043101
Short name T587
Test name
Test status
Simulation time 113493830 ps
CPU time 1.17 seconds
Started Mar 17 12:57:21 PM PDT 24
Finished Mar 17 12:57:22 PM PDT 24
Peak memory 208672 kb
Host smart-99663ba1-2c37-464e-9323-ebd17399701c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113043101 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3113043101
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3786421328
Short name T600
Test name
Test status
Simulation time 68026864 ps
CPU time 0.76 seconds
Started Mar 17 12:57:27 PM PDT 24
Finished Mar 17 12:57:28 PM PDT 24
Peak memory 200216 kb
Host smart-45833bf8-86b4-4480-9232-157e7b9f2229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786421328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3786421328
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3629063375
Short name T576
Test name
Test status
Simulation time 134580778 ps
CPU time 1.16 seconds
Started Mar 17 12:57:23 PM PDT 24
Finished Mar 17 12:57:25 PM PDT 24
Peak memory 200392 kb
Host smart-f1b5ee94-7908-43bc-89b8-ab65309127d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629063375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3629063375
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.812195276
Short name T77
Test name
Test status
Simulation time 101990372 ps
CPU time 1.27 seconds
Started Mar 17 12:57:27 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 208524 kb
Host smart-9f5cedb1-9e8d-4308-a207-ca84375f6879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812195276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.812195276
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1385789028
Short name T592
Test name
Test status
Simulation time 107828807 ps
CPU time 0.95 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 200440 kb
Host smart-02ed32eb-67bb-42fd-b41a-39d5c5479ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385789028 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1385789028
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1259234244
Short name T553
Test name
Test status
Simulation time 66820808 ps
CPU time 0.81 seconds
Started Mar 17 12:57:34 PM PDT 24
Finished Mar 17 12:57:35 PM PDT 24
Peak memory 200152 kb
Host smart-343e59ce-b780-42cb-b882-87612a1d2151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259234244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1259234244
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1099503007
Short name T597
Test name
Test status
Simulation time 129695279 ps
CPU time 1.21 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 200488 kb
Host smart-cce6122b-e3c6-4fb5-881b-f7d60629c2ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099503007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1099503007
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2955950844
Short name T82
Test name
Test status
Simulation time 210033492 ps
CPU time 1.3 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 208812 kb
Host smart-04e6fd2b-e82d-448d-9c39-9369e660f071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955950844 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2955950844
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2655285477
Short name T581
Test name
Test status
Simulation time 219441072 ps
CPU time 1.6 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 200604 kb
Host smart-ed0e437b-ff36-4cca-a86f-f48d7fd328ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655285477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2655285477
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2038655701
Short name T559
Test name
Test status
Simulation time 113238854 ps
CPU time 1.46 seconds
Started Mar 17 12:57:37 PM PDT 24
Finished Mar 17 12:57:39 PM PDT 24
Peak memory 208748 kb
Host smart-e027d20a-4f4c-4643-a496-d48ff975cdf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038655701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2038655701
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.270020712
Short name T109
Test name
Test status
Simulation time 891459685 ps
CPU time 2.96 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:35 PM PDT 24
Peak memory 200592 kb
Host smart-ec6db347-be07-4253-89a1-c158819e5523
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270020712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.270020712
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1111787319
Short name T55
Test name
Test status
Simulation time 124994356 ps
CPU time 1.25 seconds
Started Mar 17 12:57:34 PM PDT 24
Finished Mar 17 12:57:35 PM PDT 24
Peak memory 208628 kb
Host smart-3557076d-915f-41c8-9ead-dc25eb772fd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111787319 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1111787319
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.571387458
Short name T584
Test name
Test status
Simulation time 60365463 ps
CPU time 0.79 seconds
Started Mar 17 12:57:34 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200300 kb
Host smart-4077d7e0-3e02-4853-9aee-e1e4b850e8e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571387458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.571387458
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2214999308
Short name T97
Test name
Test status
Simulation time 249529908 ps
CPU time 1.47 seconds
Started Mar 17 12:57:34 PM PDT 24
Finished Mar 17 12:57:36 PM PDT 24
Peak memory 200296 kb
Host smart-fc461f4b-b91e-46d0-82c6-460428b519bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214999308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2214999308
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.914259868
Short name T111
Test name
Test status
Simulation time 98828965 ps
CPU time 1.47 seconds
Started Mar 17 12:57:33 PM PDT 24
Finished Mar 17 12:57:35 PM PDT 24
Peak memory 211356 kb
Host smart-49a86030-c523-47a2-8e18-a15815c3c2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914259868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.914259868
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2606696126
Short name T578
Test name
Test status
Simulation time 188064936 ps
CPU time 1.28 seconds
Started Mar 17 12:57:37 PM PDT 24
Finished Mar 17 12:57:39 PM PDT 24
Peak memory 208460 kb
Host smart-ff733b84-1739-4230-a3cb-a1c70b340029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606696126 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2606696126
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3459127523
Short name T93
Test name
Test status
Simulation time 75690338 ps
CPU time 0.84 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 200376 kb
Host smart-755f71af-2f94-49e3-ab94-0eaf94c724e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459127523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3459127523
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.168855942
Short name T579
Test name
Test status
Simulation time 78858269 ps
CPU time 0.99 seconds
Started Mar 17 12:57:36 PM PDT 24
Finished Mar 17 12:57:37 PM PDT 24
Peak memory 200320 kb
Host smart-6ab44fef-a44d-4fb9-91bb-c532eff373ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168855942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.168855942
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2113220202
Short name T103
Test name
Test status
Simulation time 460415585 ps
CPU time 1.97 seconds
Started Mar 17 12:57:35 PM PDT 24
Finished Mar 17 12:57:37 PM PDT 24
Peak memory 200604 kb
Host smart-4a5c813a-fe11-4a6b-a624-9b8f23d7ecd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113220202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2113220202
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.861095239
Short name T79
Test name
Test status
Simulation time 129497253 ps
CPU time 1.01 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 208628 kb
Host smart-d8bde1bc-52e6-4613-8dd4-08a72abe7987
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861095239 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.861095239
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3710243242
Short name T577
Test name
Test status
Simulation time 60525207 ps
CPU time 0.76 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 200296 kb
Host smart-ba5575b4-853a-4f7b-869b-e8a6a5907371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710243242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3710243242
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3978404222
Short name T50
Test name
Test status
Simulation time 84742102 ps
CPU time 0.95 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 200352 kb
Host smart-03672cab-5d4c-45bc-8a34-3558d68cb006
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978404222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3978404222
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1064043809
Short name T595
Test name
Test status
Simulation time 185190373 ps
CPU time 1.57 seconds
Started Mar 17 12:57:33 PM PDT 24
Finished Mar 17 12:57:35 PM PDT 24
Peak memory 208792 kb
Host smart-ba392a83-2dd0-41b4-b3bb-41efa2a8730d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064043809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1064043809
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1645344404
Short name T104
Test name
Test status
Simulation time 794910120 ps
CPU time 2.98 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200568 kb
Host smart-2ab3b5f5-fac2-4f2d-97af-b5195e99c0d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645344404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1645344404
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3664567595
Short name T580
Test name
Test status
Simulation time 139107419 ps
CPU time 1.13 seconds
Started Mar 17 12:57:34 PM PDT 24
Finished Mar 17 12:57:35 PM PDT 24
Peak memory 200476 kb
Host smart-c44462a7-3ce0-46b1-8e56-60e0e3700e37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664567595 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3664567595
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3559194783
Short name T98
Test name
Test status
Simulation time 58938678 ps
CPU time 0.79 seconds
Started Mar 17 12:57:33 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200280 kb
Host smart-222c26af-5610-4adc-b756-9c188b97ff21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559194783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3559194783
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1189641039
Short name T556
Test name
Test status
Simulation time 108734730 ps
CPU time 1.33 seconds
Started Mar 17 12:57:39 PM PDT 24
Finished Mar 17 12:57:40 PM PDT 24
Peak memory 200636 kb
Host smart-100e9b6f-8d69-4d7d-b8ee-a3db4c31dbc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189641039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1189641039
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3744069616
Short name T54
Test name
Test status
Simulation time 248988069 ps
CPU time 2.03 seconds
Started Mar 17 12:57:35 PM PDT 24
Finished Mar 17 12:57:37 PM PDT 24
Peak memory 216788 kb
Host smart-e2375425-6f6d-49ed-bf28-7844ea080aed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744069616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3744069616
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3334656049
Short name T128
Test name
Test status
Simulation time 500117389 ps
CPU time 2.02 seconds
Started Mar 17 12:57:33 PM PDT 24
Finished Mar 17 12:57:35 PM PDT 24
Peak memory 200728 kb
Host smart-ce396d8a-1f76-4826-937b-770ef76a89d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334656049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3334656049
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3322169
Short name T78
Test name
Test status
Simulation time 204241350 ps
CPU time 1.31 seconds
Started Mar 17 12:57:37 PM PDT 24
Finished Mar 17 12:57:39 PM PDT 24
Peak memory 208564 kb
Host smart-6b429364-723a-4f42-966a-287e30acbf2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322169 -assert nopostproc +UVM_TESTNAME=rs
tmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3322169
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.52658209
Short name T551
Test name
Test status
Simulation time 64405085 ps
CPU time 0.75 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 200216 kb
Host smart-d6fad461-c553-4887-aa7b-e7529b2964e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52658209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.52658209
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3667336704
Short name T610
Test name
Test status
Simulation time 74283450 ps
CPU time 0.92 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 200340 kb
Host smart-c1a54724-082e-4653-9165-5172935c0eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667336704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3667336704
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3165721985
Short name T563
Test name
Test status
Simulation time 390696501 ps
CPU time 2.46 seconds
Started Mar 17 12:57:33 PM PDT 24
Finished Mar 17 12:57:36 PM PDT 24
Peak memory 208716 kb
Host smart-c47b799c-b09f-40ae-b6a8-a897d00b404a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165721985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3165721985
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.108192588
Short name T616
Test name
Test status
Simulation time 941406432 ps
CPU time 3.36 seconds
Started Mar 17 12:57:33 PM PDT 24
Finished Mar 17 12:57:36 PM PDT 24
Peak memory 200604 kb
Host smart-cf0c4a23-dbe5-4f8f-99d9-497791e0da94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108192588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.108192588
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.979826132
Short name T618
Test name
Test status
Simulation time 182867336 ps
CPU time 1.19 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 208624 kb
Host smart-8206ee77-e4e2-4a69-be4e-15f711235783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979826132 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.979826132
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.804860629
Short name T596
Test name
Test status
Simulation time 67112313 ps
CPU time 0.8 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 200328 kb
Host smart-581a2ab0-8b88-4bd9-bc55-73d75978b3a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804860629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.804860629
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2519571984
Short name T604
Test name
Test status
Simulation time 267083864 ps
CPU time 1.61 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200528 kb
Host smart-b8809b97-b3a3-4d9d-b536-de575e25c470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519571984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2519571984
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1060766898
Short name T589
Test name
Test status
Simulation time 187738955 ps
CPU time 1.53 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200340 kb
Host smart-4bf6925f-e9b6-40d2-95ea-a30855024cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060766898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1060766898
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2562016262
Short name T564
Test name
Test status
Simulation time 801879441 ps
CPU time 2.6 seconds
Started Mar 17 12:57:31 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200608 kb
Host smart-4e30f3e4-d96f-4244-abd5-626d0b425cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562016262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2562016262
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1707827313
Short name T606
Test name
Test status
Simulation time 174648082 ps
CPU time 1.17 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200424 kb
Host smart-47cc1673-9f44-4f0b-ad84-e4d40c8d5a5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707827313 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1707827313
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3615923121
Short name T569
Test name
Test status
Simulation time 71826240 ps
CPU time 0.84 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 200276 kb
Host smart-22e0ea1a-d49c-4bea-84e7-ddddd2dee01e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615923121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3615923121
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1419075518
Short name T558
Test name
Test status
Simulation time 67897910 ps
CPU time 0.87 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 200360 kb
Host smart-c6845e2b-02ab-4521-95f6-0f5ae66c43d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419075518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1419075518
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1448559612
Short name T575
Test name
Test status
Simulation time 259280564 ps
CPU time 1.98 seconds
Started Mar 17 12:57:39 PM PDT 24
Finished Mar 17 12:57:41 PM PDT 24
Peak memory 208836 kb
Host smart-ea4c04c1-725b-455e-8e14-423f24feaf60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448559612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1448559612
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3116535226
Short name T613
Test name
Test status
Simulation time 481582229 ps
CPU time 1.86 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200532 kb
Host smart-ca5a4d3b-d047-48d7-8b41-037851fd9fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116535226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3116535226
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1674083826
Short name T594
Test name
Test status
Simulation time 136522994 ps
CPU time 1.1 seconds
Started Mar 17 12:57:42 PM PDT 24
Finished Mar 17 12:57:44 PM PDT 24
Peak memory 201068 kb
Host smart-a16363bb-8c9f-4075-9144-162fb1e0305f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674083826 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1674083826
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1953757082
Short name T598
Test name
Test status
Simulation time 59989872 ps
CPU time 0.77 seconds
Started Mar 17 12:57:37 PM PDT 24
Finished Mar 17 12:57:38 PM PDT 24
Peak memory 200352 kb
Host smart-0f437b24-9684-447c-8767-94f5ed23602b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953757082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1953757082
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2703552084
Short name T557
Test name
Test status
Simulation time 68232532 ps
CPU time 0.9 seconds
Started Mar 17 12:57:37 PM PDT 24
Finished Mar 17 12:57:38 PM PDT 24
Peak memory 200376 kb
Host smart-658e72f7-9b83-42b6-a437-0385d3b8c4e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703552084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2703552084
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.459035759
Short name T560
Test name
Test status
Simulation time 275619560 ps
CPU time 2.12 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 208692 kb
Host smart-e89812f2-cc5d-4519-b4ff-fddb87b0daef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459035759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.459035759
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2162712408
Short name T115
Test name
Test status
Simulation time 507206396 ps
CPU time 2.06 seconds
Started Mar 17 12:57:38 PM PDT 24
Finished Mar 17 12:57:40 PM PDT 24
Peak memory 200584 kb
Host smart-7ef8bf4d-3fb4-480e-8414-8c06a669bdc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162712408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2162712408
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3825892546
Short name T593
Test name
Test status
Simulation time 103324872 ps
CPU time 1.3 seconds
Started Mar 17 12:57:21 PM PDT 24
Finished Mar 17 12:57:22 PM PDT 24
Peak memory 200464 kb
Host smart-518c01cc-6633-4918-b5dc-a4e2075422a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825892546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
825892546
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1424341922
Short name T609
Test name
Test status
Simulation time 808081943 ps
CPU time 4.26 seconds
Started Mar 17 12:57:21 PM PDT 24
Finished Mar 17 12:57:25 PM PDT 24
Peak memory 200412 kb
Host smart-1b33172e-74d9-4ac7-a477-d40901332432
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424341922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
424341922
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3180118291
Short name T549
Test name
Test status
Simulation time 101529154 ps
CPU time 0.82 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 200212 kb
Host smart-2746660d-75fd-4e32-a162-fca7e85e5f61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180118291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
180118291
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4214422862
Short name T112
Test name
Test status
Simulation time 114771894 ps
CPU time 0.98 seconds
Started Mar 17 12:57:22 PM PDT 24
Finished Mar 17 12:57:23 PM PDT 24
Peak memory 200392 kb
Host smart-67d90f98-a953-4ff4-ba2e-a4da9f24d276
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214422862 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.4214422862
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3876560690
Short name T583
Test name
Test status
Simulation time 83203683 ps
CPU time 0.76 seconds
Started Mar 17 12:57:28 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 200232 kb
Host smart-59fca8d8-6869-4a75-b622-9a778ab00aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876560690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3876560690
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2043308476
Short name T95
Test name
Test status
Simulation time 195565692 ps
CPU time 1.46 seconds
Started Mar 17 12:57:24 PM PDT 24
Finished Mar 17 12:57:26 PM PDT 24
Peak memory 200472 kb
Host smart-1133a152-111d-4862-bf0c-6a16e744f6f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043308476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2043308476
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3147643972
Short name T601
Test name
Test status
Simulation time 105827273 ps
CPU time 1.38 seconds
Started Mar 17 12:57:24 PM PDT 24
Finished Mar 17 12:57:26 PM PDT 24
Peak memory 208704 kb
Host smart-796f9004-82fc-4617-808b-9b6d05a90713
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147643972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3147643972
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1584238040
Short name T86
Test name
Test status
Simulation time 149785625 ps
CPU time 2.01 seconds
Started Mar 17 12:57:25 PM PDT 24
Finished Mar 17 12:57:27 PM PDT 24
Peak memory 208696 kb
Host smart-52cd15c0-a070-4265-bc96-aded38821429
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584238040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
584238040
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3357672026
Short name T550
Test name
Test status
Simulation time 1173040694 ps
CPU time 5.63 seconds
Started Mar 17 12:57:20 PM PDT 24
Finished Mar 17 12:57:26 PM PDT 24
Peak memory 200524 kb
Host smart-30e0ce3a-f1d3-4858-a56f-c2d573328628
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357672026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
357672026
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1776522147
Short name T547
Test name
Test status
Simulation time 99399751 ps
CPU time 0.91 seconds
Started Mar 17 12:57:21 PM PDT 24
Finished Mar 17 12:57:22 PM PDT 24
Peak memory 200264 kb
Host smart-d6a6532d-1616-4673-ad52-2f2ce8f921b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776522147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
776522147
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3648797754
Short name T599
Test name
Test status
Simulation time 184166785 ps
CPU time 1.24 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:30 PM PDT 24
Peak memory 200436 kb
Host smart-5b324cc2-9773-46c3-b83b-764e53ce19ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648797754 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3648797754
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.420364573
Short name T554
Test name
Test status
Simulation time 65326419 ps
CPU time 0.78 seconds
Started Mar 17 12:57:21 PM PDT 24
Finished Mar 17 12:57:22 PM PDT 24
Peak memory 200408 kb
Host smart-57306352-7fd8-43ef-a942-321299261bad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420364573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.420364573
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3084600382
Short name T590
Test name
Test status
Simulation time 80533432 ps
CPU time 0.99 seconds
Started Mar 17 12:57:25 PM PDT 24
Finished Mar 17 12:57:26 PM PDT 24
Peak memory 200360 kb
Host smart-b0814454-ee62-4eb8-96ee-038c0bee4931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084600382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3084600382
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3179138496
Short name T611
Test name
Test status
Simulation time 137030616 ps
CPU time 1.98 seconds
Started Mar 17 12:57:26 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 208640 kb
Host smart-29addd0c-d4d1-4adf-aa00-7129942a8ac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179138496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3179138496
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.473672113
Short name T602
Test name
Test status
Simulation time 361913629 ps
CPU time 2.64 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 200540 kb
Host smart-3e1c2c4c-289e-4dfb-a918-e9b404cc9bbc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473672113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.473672113
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2051988090
Short name T567
Test name
Test status
Simulation time 1184040011 ps
CPU time 5.7 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:38 PM PDT 24
Peak memory 200472 kb
Host smart-3fb83bbc-37b1-4ecc-b61a-bd21c4236ea6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051988090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
051988090
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1314494869
Short name T619
Test name
Test status
Simulation time 138778569 ps
CPU time 0.93 seconds
Started Mar 17 12:57:30 PM PDT 24
Finished Mar 17 12:57:31 PM PDT 24
Peak memory 200328 kb
Host smart-03102572-ca10-4bf0-8448-b7b65cb7cf64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314494869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
314494869
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1097263089
Short name T114
Test name
Test status
Simulation time 173696085 ps
CPU time 1.62 seconds
Started Mar 17 12:57:25 PM PDT 24
Finished Mar 17 12:57:27 PM PDT 24
Peak memory 208816 kb
Host smart-1dccf25c-b49b-4255-8ace-1ffd261afb6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097263089 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1097263089
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.660185647
Short name T572
Test name
Test status
Simulation time 82114713 ps
CPU time 0.91 seconds
Started Mar 17 12:57:28 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 200288 kb
Host smart-c811afc5-1c40-4a89-b8e4-4bba775e0078
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660185647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.660185647
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3263200360
Short name T585
Test name
Test status
Simulation time 82236196 ps
CPU time 0.95 seconds
Started Mar 17 12:57:27 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 200288 kb
Host smart-8b60e40d-6882-4fb6-b7ce-924927f11f93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263200360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3263200360
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4126275477
Short name T108
Test name
Test status
Simulation time 790962636 ps
CPU time 2.9 seconds
Started Mar 17 12:57:24 PM PDT 24
Finished Mar 17 12:57:27 PM PDT 24
Peak memory 200604 kb
Host smart-959da088-cc7b-4f32-be26-3b9525c58057
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126275477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.4126275477
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2677296508
Short name T603
Test name
Test status
Simulation time 121369287 ps
CPU time 1.26 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:30 PM PDT 24
Peak memory 208384 kb
Host smart-770d1296-fd83-4264-815a-b52f795ff2dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677296508 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2677296508
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2285850239
Short name T99
Test name
Test status
Simulation time 82538893 ps
CPU time 0.85 seconds
Started Mar 17 12:57:28 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 200288 kb
Host smart-4902e008-c771-4846-8a45-137ffa674ede
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285850239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2285850239
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1555390251
Short name T96
Test name
Test status
Simulation time 102455979 ps
CPU time 1.22 seconds
Started Mar 17 12:57:33 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200544 kb
Host smart-e7f747f9-d62e-4973-81dd-ab3303df076b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555390251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1555390251
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1279364641
Short name T582
Test name
Test status
Simulation time 235907225 ps
CPU time 2.02 seconds
Started Mar 17 12:57:25 PM PDT 24
Finished Mar 17 12:57:27 PM PDT 24
Peak memory 216872 kb
Host smart-a49ede16-cb42-49a7-aedf-4608cd59cb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279364641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1279364641
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1348537733
Short name T113
Test name
Test status
Simulation time 795337613 ps
CPU time 2.88 seconds
Started Mar 17 12:57:28 PM PDT 24
Finished Mar 17 12:57:31 PM PDT 24
Peak memory 200544 kb
Host smart-f07c34ad-3e30-41b4-b37c-bf06f8e2492e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348537733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1348537733
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2636318707
Short name T617
Test name
Test status
Simulation time 180738237 ps
CPU time 1.69 seconds
Started Mar 17 12:57:34 PM PDT 24
Finished Mar 17 12:57:36 PM PDT 24
Peak memory 208804 kb
Host smart-8dd71692-dd76-44de-b3a8-8e866bfff0ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636318707 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2636318707
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2243447284
Short name T548
Test name
Test status
Simulation time 65487967 ps
CPU time 0.77 seconds
Started Mar 17 12:57:25 PM PDT 24
Finished Mar 17 12:57:26 PM PDT 24
Peak memory 200276 kb
Host smart-aac9324c-492d-4124-b44f-09d80d7c0f10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243447284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2243447284
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.225951404
Short name T100
Test name
Test status
Simulation time 75570560 ps
CPU time 0.87 seconds
Started Mar 17 12:57:33 PM PDT 24
Finished Mar 17 12:57:34 PM PDT 24
Peak memory 200404 kb
Host smart-2ef0b42d-7db1-4e27-a81f-d235eeb47339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225951404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.225951404
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.539622654
Short name T106
Test name
Test status
Simulation time 598567865 ps
CPU time 3.7 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 208820 kb
Host smart-80460f16-be76-420e-8449-3183ddf93a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539622654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.539622654
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4099884181
Short name T620
Test name
Test status
Simulation time 436411204 ps
CPU time 1.81 seconds
Started Mar 17 12:57:25 PM PDT 24
Finished Mar 17 12:57:28 PM PDT 24
Peak memory 200456 kb
Host smart-e318370b-724f-4ec3-bc17-ed77a3387f79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099884181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.4099884181
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4006104789
Short name T562
Test name
Test status
Simulation time 132951717 ps
CPU time 1.1 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:31 PM PDT 24
Peak memory 208644 kb
Host smart-df424a05-c610-4ef6-bd65-4e4eedbbe156
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006104789 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4006104789
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2771120266
Short name T565
Test name
Test status
Simulation time 90080722 ps
CPU time 0.9 seconds
Started Mar 17 12:57:32 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 200296 kb
Host smart-22e7d029-357a-4a5e-b301-64aa5a6681f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771120266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2771120266
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.927972528
Short name T101
Test name
Test status
Simulation time 230114403 ps
CPU time 1.5 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:31 PM PDT 24
Peak memory 200248 kb
Host smart-563237d4-8dfc-4825-a5f4-8d862bdba920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927972528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.927972528
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2972234807
Short name T53
Test name
Test status
Simulation time 244042696 ps
CPU time 3.4 seconds
Started Mar 17 12:57:30 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 212108 kb
Host smart-309b783c-259c-4fc7-91ea-e572899d5f81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972234807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2972234807
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1172207162
Short name T127
Test name
Test status
Simulation time 823124685 ps
CPU time 2.77 seconds
Started Mar 17 12:57:27 PM PDT 24
Finished Mar 17 12:57:30 PM PDT 24
Peak memory 200600 kb
Host smart-cceef739-8b65-4c65-b03a-5c727b38dcd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172207162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1172207162
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3581553300
Short name T566
Test name
Test status
Simulation time 195656854 ps
CPU time 1.37 seconds
Started Mar 17 12:57:26 PM PDT 24
Finished Mar 17 12:57:28 PM PDT 24
Peak memory 210516 kb
Host smart-5e204e3a-9968-498f-9821-ff404bf58b0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581553300 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3581553300
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2434211022
Short name T555
Test name
Test status
Simulation time 86369879 ps
CPU time 0.84 seconds
Started Mar 17 12:57:28 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 200284 kb
Host smart-a675ab80-06c1-453e-9fa8-f884adb47269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434211022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2434211022
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3123115422
Short name T614
Test name
Test status
Simulation time 261317653 ps
CPU time 1.59 seconds
Started Mar 17 12:57:34 PM PDT 24
Finished Mar 17 12:57:36 PM PDT 24
Peak memory 200532 kb
Host smart-1c635ad0-9845-4bb2-b82c-b97febdc7bd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123115422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3123115422
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3735753830
Short name T615
Test name
Test status
Simulation time 187482790 ps
CPU time 2.94 seconds
Started Mar 17 12:57:33 PM PDT 24
Finished Mar 17 12:57:36 PM PDT 24
Peak memory 211704 kb
Host smart-f3325f9d-065e-4866-9990-6307bc9c848a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735753830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3735753830
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3763041612
Short name T102
Test name
Test status
Simulation time 891287464 ps
CPU time 2.71 seconds
Started Mar 17 12:57:37 PM PDT 24
Finished Mar 17 12:57:40 PM PDT 24
Peak memory 200560 kb
Host smart-3f392285-0520-420c-8991-dba1d0d307d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763041612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3763041612
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2101762649
Short name T586
Test name
Test status
Simulation time 131484505 ps
CPU time 1.44 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:30 PM PDT 24
Peak memory 208664 kb
Host smart-06d16b42-2bee-4e78-8f37-59079d973a92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101762649 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2101762649
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1494661748
Short name T546
Test name
Test status
Simulation time 77984130 ps
CPU time 0.78 seconds
Started Mar 17 12:57:28 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 200216 kb
Host smart-910fe47d-eff4-4281-a2ad-d50732dea0cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494661748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1494661748
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.74990300
Short name T588
Test name
Test status
Simulation time 84773606 ps
CPU time 0.95 seconds
Started Mar 17 12:57:24 PM PDT 24
Finished Mar 17 12:57:25 PM PDT 24
Peak memory 200388 kb
Host smart-c4d362e2-0630-492c-b39e-710fec3f3428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74990300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same
_csr_outstanding.74990300
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2182122336
Short name T570
Test name
Test status
Simulation time 107151219 ps
CPU time 1.34 seconds
Started Mar 17 12:57:27 PM PDT 24
Finished Mar 17 12:57:29 PM PDT 24
Peak memory 216716 kb
Host smart-a501bf1d-697c-48e4-8395-9b13f690f735
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182122336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2182122336
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3770203731
Short name T107
Test name
Test status
Simulation time 787493337 ps
CPU time 2.62 seconds
Started Mar 17 12:57:29 PM PDT 24
Finished Mar 17 12:57:32 PM PDT 24
Peak memory 200580 kb
Host smart-846b6c0f-e8e9-40ad-b465-4efc8a202bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770203731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3770203731
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2361382526
Short name T498
Test name
Test status
Simulation time 71574749 ps
CPU time 0.79 seconds
Started Mar 17 03:03:57 PM PDT 24
Finished Mar 17 03:03:59 PM PDT 24
Peak memory 200696 kb
Host smart-64913db3-e9e8-4b30-a5b2-47e09143a8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361382526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2361382526
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1177413219
Short name T49
Test name
Test status
Simulation time 2356431262 ps
CPU time 9.49 seconds
Started Mar 17 03:03:57 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 218356 kb
Host smart-b92474ef-c4af-4492-83b5-a677deb072f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177413219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1177413219
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2425062843
Short name T344
Test name
Test status
Simulation time 244780560 ps
CPU time 1.06 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:03:52 PM PDT 24
Peak memory 218276 kb
Host smart-daccc9af-5be9-4965-aff5-c896e45828b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425062843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2425062843
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.4067991434
Short name T393
Test name
Test status
Simulation time 177574718 ps
CPU time 0.83 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:03:52 PM PDT 24
Peak memory 200800 kb
Host smart-727eb902-8f67-45f2-8ef4-d14192b19665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067991434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.4067991434
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3609012117
Short name T436
Test name
Test status
Simulation time 1664034147 ps
CPU time 6.41 seconds
Started Mar 17 03:03:52 PM PDT 24
Finished Mar 17 03:03:59 PM PDT 24
Peak memory 201072 kb
Host smart-72924b2d-d18d-4357-b8e9-80ef864800ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609012117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3609012117
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2201994592
Short name T63
Test name
Test status
Simulation time 16923376828 ps
CPU time 25.46 seconds
Started Mar 17 03:03:49 PM PDT 24
Finished Mar 17 03:04:15 PM PDT 24
Peak memory 222508 kb
Host smart-b14712cb-92c0-4377-ab97-5a7cffb5769f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201994592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2201994592
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2841307043
Short name T134
Test name
Test status
Simulation time 106533558 ps
CPU time 0.97 seconds
Started Mar 17 03:03:49 PM PDT 24
Finished Mar 17 03:03:50 PM PDT 24
Peak memory 200864 kb
Host smart-7ed6ed16-a262-47a9-a6bb-8100e703f3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841307043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2841307043
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.34052604
Short name T200
Test name
Test status
Simulation time 249163060 ps
CPU time 1.63 seconds
Started Mar 17 03:03:53 PM PDT 24
Finished Mar 17 03:03:55 PM PDT 24
Peak memory 201112 kb
Host smart-d6ab71f5-9d56-4678-920e-78ffebd62815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34052604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.34052604
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3798103904
Short name T92
Test name
Test status
Simulation time 8041085899 ps
CPU time 31.51 seconds
Started Mar 17 03:03:53 PM PDT 24
Finished Mar 17 03:04:25 PM PDT 24
Peak memory 209448 kb
Host smart-73983100-5598-4b87-8e54-c142ce9e067f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798103904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3798103904
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2995445187
Short name T314
Test name
Test status
Simulation time 306500731 ps
CPU time 2.02 seconds
Started Mar 17 03:03:57 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 200908 kb
Host smart-c8a4cefa-6da2-474b-ba15-0b3bee427105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995445187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2995445187
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.230123655
Short name T265
Test name
Test status
Simulation time 204898571 ps
CPU time 1.37 seconds
Started Mar 17 03:03:57 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 200824 kb
Host smart-0f45b185-eae0-4d0c-9948-a958e1778288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230123655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.230123655
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4031201969
Short name T427
Test name
Test status
Simulation time 75569992 ps
CPU time 0.83 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:03:57 PM PDT 24
Peak memory 200680 kb
Host smart-d2120e7f-233b-47ae-8c64-5db0f62ffd32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031201969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4031201969
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3351211443
Short name T402
Test name
Test status
Simulation time 1226499596 ps
CPU time 5.77 seconds
Started Mar 17 03:03:54 PM PDT 24
Finished Mar 17 03:04:01 PM PDT 24
Peak memory 222136 kb
Host smart-97ea3e0b-6681-4166-af75-674d6aae6bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351211443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3351211443
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1418952328
Short name T320
Test name
Test status
Simulation time 244328296 ps
CPU time 1.07 seconds
Started Mar 17 03:03:52 PM PDT 24
Finished Mar 17 03:03:54 PM PDT 24
Peak memory 218272 kb
Host smart-1773f508-0691-4ead-954d-be7431678a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418952328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1418952328
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2862547881
Short name T201
Test name
Test status
Simulation time 141731886 ps
CPU time 0.84 seconds
Started Mar 17 03:03:49 PM PDT 24
Finished Mar 17 03:03:50 PM PDT 24
Peak memory 200704 kb
Host smart-de529164-c47f-4516-bd80-b5973fb50f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862547881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2862547881
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3648217285
Short name T345
Test name
Test status
Simulation time 729202282 ps
CPU time 3.78 seconds
Started Mar 17 03:03:49 PM PDT 24
Finished Mar 17 03:03:53 PM PDT 24
Peak memory 201108 kb
Host smart-b2df3454-b4ba-4330-8442-179fb378cd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648217285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3648217285
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.693207605
Short name T62
Test name
Test status
Simulation time 8287224268 ps
CPU time 15.24 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:04:12 PM PDT 24
Peak memory 218036 kb
Host smart-66dcc68a-3750-467c-9629-bc9218688211
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693207605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.693207605
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2377032030
Short name T401
Test name
Test status
Simulation time 145029186 ps
CPU time 1.12 seconds
Started Mar 17 03:03:54 PM PDT 24
Finished Mar 17 03:03:56 PM PDT 24
Peak memory 200912 kb
Host smart-f0819374-db48-4c96-9f9a-0268cb2ef683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377032030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2377032030
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1542623660
Short name T300
Test name
Test status
Simulation time 126151924 ps
CPU time 1.18 seconds
Started Mar 17 03:03:57 PM PDT 24
Finished Mar 17 03:03:59 PM PDT 24
Peak memory 200976 kb
Host smart-e635fb2b-41e3-4de0-8fe2-f3137e839529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542623660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1542623660
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.4139962881
Short name T221
Test name
Test status
Simulation time 15052601280 ps
CPU time 54.34 seconds
Started Mar 17 03:03:54 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 201228 kb
Host smart-1b104787-98d8-4926-9a66-43a49b2e4a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139962881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4139962881
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.924320298
Short name T144
Test name
Test status
Simulation time 152990530 ps
CPU time 1.96 seconds
Started Mar 17 03:03:57 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 200868 kb
Host smart-d6fe9636-be75-411e-bbb6-66b8bc75a879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924320298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.924320298
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2369466513
Short name T121
Test name
Test status
Simulation time 210614135 ps
CPU time 1.28 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:03:52 PM PDT 24
Peak memory 200908 kb
Host smart-31cd11ad-9907-4d7c-be0a-eb28ba59e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369466513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2369466513
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.4124680531
Short name T266
Test name
Test status
Simulation time 63163145 ps
CPU time 0.77 seconds
Started Mar 17 03:04:20 PM PDT 24
Finished Mar 17 03:04:21 PM PDT 24
Peak memory 200688 kb
Host smart-a14b83d4-a165-4e09-8678-5df8d9395b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124680531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4124680531
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1142148215
Short name T270
Test name
Test status
Simulation time 244152737 ps
CPU time 1.05 seconds
Started Mar 17 03:04:21 PM PDT 24
Finished Mar 17 03:04:22 PM PDT 24
Peak memory 218168 kb
Host smart-37f71f11-9ad8-4244-ab34-50691f5a0e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142148215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1142148215
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2965905882
Short name T239
Test name
Test status
Simulation time 139194266 ps
CPU time 0.86 seconds
Started Mar 17 03:04:21 PM PDT 24
Finished Mar 17 03:04:22 PM PDT 24
Peak memory 200768 kb
Host smart-2c1d0f19-ba99-4fee-9aae-8f5251786539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965905882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2965905882
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.4178979568
Short name T539
Test name
Test status
Simulation time 1419297732 ps
CPU time 5.83 seconds
Started Mar 17 03:04:19 PM PDT 24
Finished Mar 17 03:04:25 PM PDT 24
Peak memory 201092 kb
Host smart-b18dfabb-5b23-4dc1-8488-515fda797eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178979568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.4178979568
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1329673866
Short name T155
Test name
Test status
Simulation time 147363283 ps
CPU time 1.14 seconds
Started Mar 17 03:04:22 PM PDT 24
Finished Mar 17 03:04:23 PM PDT 24
Peak memory 200888 kb
Host smart-910da8ba-ff70-4b81-9337-93b7e6921b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329673866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1329673866
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3115342680
Short name T273
Test name
Test status
Simulation time 109749567 ps
CPU time 1.19 seconds
Started Mar 17 03:04:21 PM PDT 24
Finished Mar 17 03:04:22 PM PDT 24
Peak memory 201104 kb
Host smart-cfc0a259-fe03-42b9-8308-cd8c74d1bf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115342680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3115342680
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1065857718
Short name T364
Test name
Test status
Simulation time 2275462546 ps
CPU time 9.21 seconds
Started Mar 17 03:04:22 PM PDT 24
Finished Mar 17 03:04:31 PM PDT 24
Peak memory 201204 kb
Host smart-6139660b-5116-4175-bed0-ca7ad557df9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065857718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1065857718
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.602062022
Short name T395
Test name
Test status
Simulation time 368910811 ps
CPU time 2.05 seconds
Started Mar 17 03:04:22 PM PDT 24
Finished Mar 17 03:04:24 PM PDT 24
Peak memory 209380 kb
Host smart-a4fdf5d2-735a-4665-b16c-b9fd2cae1e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602062022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.602062022
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.87909371
Short name T514
Test name
Test status
Simulation time 116730901 ps
CPU time 0.96 seconds
Started Mar 17 03:04:22 PM PDT 24
Finished Mar 17 03:04:23 PM PDT 24
Peak memory 200848 kb
Host smart-653ed2cc-a937-4bde-9c54-ee8ee1c2a512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87909371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.87909371
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1621384509
Short name T198
Test name
Test status
Simulation time 99955406 ps
CPU time 0.87 seconds
Started Mar 17 03:04:27 PM PDT 24
Finished Mar 17 03:04:28 PM PDT 24
Peak memory 200728 kb
Host smart-c98492ee-79ca-4015-bc3b-d09d0027b306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621384509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1621384509
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4205013311
Short name T38
Test name
Test status
Simulation time 1910873151 ps
CPU time 8.05 seconds
Started Mar 17 03:04:26 PM PDT 24
Finished Mar 17 03:04:34 PM PDT 24
Peak memory 218532 kb
Host smart-f84b7131-7fb2-4e54-a589-77ed58f991d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205013311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4205013311
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2338008370
Short name T46
Test name
Test status
Simulation time 243819022 ps
CPU time 1.14 seconds
Started Mar 17 03:04:26 PM PDT 24
Finished Mar 17 03:04:27 PM PDT 24
Peak memory 218248 kb
Host smart-ef1986c9-888f-4f5e-9838-2b3cf33e0fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338008370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2338008370
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2691172297
Short name T351
Test name
Test status
Simulation time 104191584 ps
CPU time 0.84 seconds
Started Mar 17 03:04:21 PM PDT 24
Finished Mar 17 03:04:22 PM PDT 24
Peak memory 200744 kb
Host smart-eaa281a3-ff71-4b04-84f6-a0c93dca750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691172297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2691172297
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.205893824
Short name T142
Test name
Test status
Simulation time 800168468 ps
CPU time 4.08 seconds
Started Mar 17 03:04:27 PM PDT 24
Finished Mar 17 03:04:31 PM PDT 24
Peak memory 200984 kb
Host smart-292000b1-0031-4ce2-9be9-0e0d511323ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205893824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.205893824
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1714341172
Short name T199
Test name
Test status
Simulation time 173701196 ps
CPU time 1.17 seconds
Started Mar 17 03:04:26 PM PDT 24
Finished Mar 17 03:04:27 PM PDT 24
Peak memory 201068 kb
Host smart-8dcc555a-55bb-4f99-b50f-e4176a6dbef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714341172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1714341172
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.140962107
Short name T133
Test name
Test status
Simulation time 118206089 ps
CPU time 1.22 seconds
Started Mar 17 03:04:21 PM PDT 24
Finished Mar 17 03:04:22 PM PDT 24
Peak memory 201104 kb
Host smart-55fe9237-433a-4af1-8d8f-8b1cdf1371c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140962107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.140962107
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2446247738
Short name T234
Test name
Test status
Simulation time 3207554271 ps
CPU time 14.56 seconds
Started Mar 17 03:04:26 PM PDT 24
Finished Mar 17 03:04:41 PM PDT 24
Peak memory 201208 kb
Host smart-448bb223-1083-43a1-8078-72e967f0b0eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446247738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2446247738
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1002185491
Short name T456
Test name
Test status
Simulation time 128398159 ps
CPU time 1.59 seconds
Started Mar 17 03:04:25 PM PDT 24
Finished Mar 17 03:04:27 PM PDT 24
Peak memory 200840 kb
Host smart-aac2e5a4-1d6b-4239-8f43-2b6c9198b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002185491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1002185491
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3936072706
Short name T141
Test name
Test status
Simulation time 85065347 ps
CPU time 0.89 seconds
Started Mar 17 03:04:22 PM PDT 24
Finished Mar 17 03:04:22 PM PDT 24
Peak memory 200884 kb
Host smart-bf440751-8900-4507-8ce9-d445f11ace3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936072706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3936072706
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1947389168
Short name T232
Test name
Test status
Simulation time 244696595 ps
CPU time 1.06 seconds
Started Mar 17 03:04:27 PM PDT 24
Finished Mar 17 03:04:28 PM PDT 24
Peak memory 218108 kb
Host smart-563352ad-e5d6-4517-8473-da3b48e2230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947389168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1947389168
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.51338678
Short name T255
Test name
Test status
Simulation time 132700473 ps
CPU time 0.79 seconds
Started Mar 17 03:04:27 PM PDT 24
Finished Mar 17 03:04:28 PM PDT 24
Peak memory 200744 kb
Host smart-1cfb0cc7-b84f-4c37-8c5e-45f3aeac9ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51338678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.51338678
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1769965938
Short name T474
Test name
Test status
Simulation time 901284434 ps
CPU time 4.43 seconds
Started Mar 17 03:04:27 PM PDT 24
Finished Mar 17 03:04:31 PM PDT 24
Peak memory 201040 kb
Host smart-76efd316-fe91-4787-97c6-d4e04b9e5083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769965938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1769965938
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.373724083
Short name T203
Test name
Test status
Simulation time 147949638 ps
CPU time 1.19 seconds
Started Mar 17 03:04:28 PM PDT 24
Finished Mar 17 03:04:29 PM PDT 24
Peak memory 200920 kb
Host smart-276c2841-13d2-4c45-b469-010c7b6a8af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373724083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.373724083
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1824696288
Short name T309
Test name
Test status
Simulation time 116022848 ps
CPU time 1.14 seconds
Started Mar 17 03:04:26 PM PDT 24
Finished Mar 17 03:04:27 PM PDT 24
Peak memory 201032 kb
Host smart-1f9722d1-87a2-4bd2-adf2-be11308d5cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824696288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1824696288
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.4054159175
Short name T480
Test name
Test status
Simulation time 6007712256 ps
CPU time 25.19 seconds
Started Mar 17 03:04:34 PM PDT 24
Finished Mar 17 03:04:59 PM PDT 24
Peak memory 201248 kb
Host smart-bcb901ea-0226-4a53-ba84-4f1704ab1480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054159175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.4054159175
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.4239755820
Short name T343
Test name
Test status
Simulation time 126857853 ps
CPU time 1.53 seconds
Started Mar 17 03:04:27 PM PDT 24
Finished Mar 17 03:04:29 PM PDT 24
Peak memory 200956 kb
Host smart-09dc5a27-dc5d-4c93-9088-f8e2d88f484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239755820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.4239755820
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3734042230
Short name T209
Test name
Test status
Simulation time 176455216 ps
CPU time 1.11 seconds
Started Mar 17 03:04:32 PM PDT 24
Finished Mar 17 03:04:33 PM PDT 24
Peak memory 200912 kb
Host smart-f0b46602-c305-4f77-815b-6318a23a5a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734042230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3734042230
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3059241025
Short name T214
Test name
Test status
Simulation time 73660592 ps
CPU time 0.8 seconds
Started Mar 17 03:04:31 PM PDT 24
Finished Mar 17 03:04:32 PM PDT 24
Peak memory 200732 kb
Host smart-532866b5-e8d8-4e49-9629-9b85262e3f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059241025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3059241025
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.842455538
Short name T475
Test name
Test status
Simulation time 2155094724 ps
CPU time 8.32 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:41 PM PDT 24
Peak memory 230520 kb
Host smart-a5643aea-9a91-4f3f-b51b-6ceb9fcff5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842455538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.842455538
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1407286899
Short name T542
Test name
Test status
Simulation time 244446745 ps
CPU time 1.06 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 218316 kb
Host smart-4f4d9fb9-2e9a-4520-9a14-f5c8ae989ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407286899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1407286899
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1081735148
Short name T257
Test name
Test status
Simulation time 237037769 ps
CPU time 0.93 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:35 PM PDT 24
Peak memory 200788 kb
Host smart-574228ac-8a83-4f0a-b5aa-f941c19c8ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081735148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1081735148
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2018051843
Short name T83
Test name
Test status
Simulation time 958950574 ps
CPU time 5.04 seconds
Started Mar 17 03:04:25 PM PDT 24
Finished Mar 17 03:04:30 PM PDT 24
Peak memory 201048 kb
Host smart-23f1db4e-bcf7-4930-abea-d56a4c9cda60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018051843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2018051843
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.196734219
Short name T317
Test name
Test status
Simulation time 181580487 ps
CPU time 1.24 seconds
Started Mar 17 03:04:31 PM PDT 24
Finished Mar 17 03:04:33 PM PDT 24
Peak memory 200920 kb
Host smart-ea985a2f-c198-4b2e-a1df-0833009979d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196734219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.196734219
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1143079999
Short name T331
Test name
Test status
Simulation time 252038116 ps
CPU time 1.54 seconds
Started Mar 17 03:04:25 PM PDT 24
Finished Mar 17 03:04:27 PM PDT 24
Peak memory 201016 kb
Host smart-6b150908-ecf0-42d1-b834-b2cf3043b3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143079999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1143079999
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1950262372
Short name T518
Test name
Test status
Simulation time 4738728218 ps
CPU time 21.65 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:55 PM PDT 24
Peak memory 209368 kb
Host smart-f2ec9d44-3b65-438c-b137-353cc57bfb45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950262372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1950262372
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.77900383
Short name T4
Test name
Test status
Simulation time 366536288 ps
CPU time 2.09 seconds
Started Mar 17 03:04:35 PM PDT 24
Finished Mar 17 03:04:37 PM PDT 24
Peak memory 200880 kb
Host smart-ae587121-f3f4-4995-856d-32a356708146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77900383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.77900383
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2380118436
Short name T167
Test name
Test status
Simulation time 118442273 ps
CPU time 0.99 seconds
Started Mar 17 03:04:25 PM PDT 24
Finished Mar 17 03:04:26 PM PDT 24
Peak memory 200876 kb
Host smart-2121db0d-c82e-4e98-9954-81d1f2436dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380118436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2380118436
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2160868372
Short name T230
Test name
Test status
Simulation time 86195008 ps
CPU time 0.9 seconds
Started Mar 17 03:04:34 PM PDT 24
Finished Mar 17 03:04:35 PM PDT 24
Peak memory 200776 kb
Host smart-0e8c8abf-2881-4b1b-ab23-6b0bb7de4d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160868372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2160868372
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1273241220
Short name T319
Test name
Test status
Simulation time 2368837281 ps
CPU time 8.06 seconds
Started Mar 17 03:04:29 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 218700 kb
Host smart-1e4623b7-9664-41e7-a5d0-25700e3de1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273241220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1273241220
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1654033426
Short name T249
Test name
Test status
Simulation time 244414282 ps
CPU time 1.04 seconds
Started Mar 17 03:04:31 PM PDT 24
Finished Mar 17 03:04:32 PM PDT 24
Peak memory 218184 kb
Host smart-95b64e3a-f811-4b73-a575-4d3de50b9ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654033426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1654033426
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2366375405
Short name T171
Test name
Test status
Simulation time 177784535 ps
CPU time 0.83 seconds
Started Mar 17 03:04:34 PM PDT 24
Finished Mar 17 03:04:35 PM PDT 24
Peak memory 200756 kb
Host smart-aa406ae0-ca10-43d8-823a-1ea8b9cdbe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366375405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2366375405
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3004229138
Short name T538
Test name
Test status
Simulation time 146114749 ps
CPU time 1.13 seconds
Started Mar 17 03:04:34 PM PDT 24
Finished Mar 17 03:04:35 PM PDT 24
Peak memory 200856 kb
Host smart-37cbb1af-aa03-4029-b7bc-51a3ba65c375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004229138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3004229138
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2090327762
Short name T404
Test name
Test status
Simulation time 200239554 ps
CPU time 1.33 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:34 PM PDT 24
Peak memory 201036 kb
Host smart-0a9fcf50-f61a-4379-8b2b-767b825821f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090327762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2090327762
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1030576860
Short name T503
Test name
Test status
Simulation time 4805660355 ps
CPU time 18.02 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:58 PM PDT 24
Peak memory 201220 kb
Host smart-6a3bc670-065b-4110-9261-08582d768c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030576860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1030576860
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.940524456
Short name T494
Test name
Test status
Simulation time 114326324 ps
CPU time 1.5 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:35 PM PDT 24
Peak memory 200952 kb
Host smart-645c4aa0-e7eb-4a35-b2e0-a7bdcc54db80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940524456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.940524456
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2468263165
Short name T129
Test name
Test status
Simulation time 123111645 ps
CPU time 1.06 seconds
Started Mar 17 03:04:32 PM PDT 24
Finished Mar 17 03:04:33 PM PDT 24
Peak memory 200932 kb
Host smart-61bb9d55-e9b3-4d05-98a6-db1e57114cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468263165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2468263165
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3613417465
Short name T529
Test name
Test status
Simulation time 90614153 ps
CPU time 1.01 seconds
Started Mar 17 03:04:34 PM PDT 24
Finished Mar 17 03:04:35 PM PDT 24
Peak memory 200716 kb
Host smart-a9515738-f97f-41bd-853f-f20c555c0c7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613417465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3613417465
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1023241406
Short name T131
Test name
Test status
Simulation time 244733656 ps
CPU time 1.04 seconds
Started Mar 17 03:04:36 PM PDT 24
Finished Mar 17 03:04:37 PM PDT 24
Peak memory 218312 kb
Host smart-f09da3bc-fc4f-4070-a44c-aeddfceafacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023241406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1023241406
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.4234266642
Short name T386
Test name
Test status
Simulation time 86408374 ps
CPU time 0.78 seconds
Started Mar 17 03:04:31 PM PDT 24
Finished Mar 17 03:04:32 PM PDT 24
Peak memory 200716 kb
Host smart-8a91a538-69da-4b9d-b5ba-049f14846bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234266642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.4234266642
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.119254755
Short name T165
Test name
Test status
Simulation time 1366618818 ps
CPU time 5.66 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 201060 kb
Host smart-080550bf-48ff-485c-aa01-99e27d63ec25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119254755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.119254755
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3811997175
Short name T296
Test name
Test status
Simulation time 109567924 ps
CPU time 1.03 seconds
Started Mar 17 03:04:31 PM PDT 24
Finished Mar 17 03:04:32 PM PDT 24
Peak memory 200848 kb
Host smart-8194e2f7-60b8-4c95-948c-262fe01150a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811997175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3811997175
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1169969808
Short name T122
Test name
Test status
Simulation time 229983579 ps
CPU time 1.53 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:35 PM PDT 24
Peak memory 201024 kb
Host smart-6ac9a0d8-86a1-47b0-819a-ad81cc8ce0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169969808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1169969808
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1866211065
Short name T512
Test name
Test status
Simulation time 1464828964 ps
CPU time 7.8 seconds
Started Mar 17 03:04:35 PM PDT 24
Finished Mar 17 03:04:43 PM PDT 24
Peak memory 210420 kb
Host smart-e9cded9a-0e4a-4044-934f-f03d7938c495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866211065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1866211065
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1077869602
Short name T525
Test name
Test status
Simulation time 546454318 ps
CPU time 2.87 seconds
Started Mar 17 03:04:34 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 200944 kb
Host smart-2e56dcff-8911-4578-a346-ca54b938e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077869602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1077869602
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2049294867
Short name T446
Test name
Test status
Simulation time 111611005 ps
CPU time 0.93 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:34 PM PDT 24
Peak memory 200860 kb
Host smart-f40438bc-d072-4ac3-9d94-6bd40f17fdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049294867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2049294867
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3112814026
Short name T293
Test name
Test status
Simulation time 90036289 ps
CPU time 0.85 seconds
Started Mar 17 03:04:35 PM PDT 24
Finished Mar 17 03:04:36 PM PDT 24
Peak memory 200712 kb
Host smart-af301f99-af58-46e9-afcb-b963339666e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112814026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3112814026
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.528523833
Short name T48
Test name
Test status
Simulation time 1237032607 ps
CPU time 5.55 seconds
Started Mar 17 03:04:34 PM PDT 24
Finished Mar 17 03:04:40 PM PDT 24
Peak memory 230396 kb
Host smart-dfe88fcf-4e14-4abf-ade4-216ee28105c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528523833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.528523833
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3948128901
Short name T254
Test name
Test status
Simulation time 244321325 ps
CPU time 1.2 seconds
Started Mar 17 03:04:35 PM PDT 24
Finished Mar 17 03:04:36 PM PDT 24
Peak memory 218212 kb
Host smart-92e045af-7625-404a-8aa0-cd3a4865061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948128901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3948128901
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1427168745
Short name T185
Test name
Test status
Simulation time 95455187 ps
CPU time 0.79 seconds
Started Mar 17 03:04:32 PM PDT 24
Finished Mar 17 03:04:33 PM PDT 24
Peak memory 200760 kb
Host smart-b8d1d869-063f-4809-9197-ea36906ae7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427168745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1427168745
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4059198161
Short name T333
Test name
Test status
Simulation time 759074952 ps
CPU time 3.99 seconds
Started Mar 17 03:04:35 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 201140 kb
Host smart-87dcff77-30be-459e-98d4-98996b136a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059198161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4059198161
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.665152204
Short name T502
Test name
Test status
Simulation time 108480946 ps
CPU time 0.97 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:35 PM PDT 24
Peak memory 200904 kb
Host smart-cd025fee-c90a-48ab-876b-e40729d2d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665152204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.665152204
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3871028872
Short name T424
Test name
Test status
Simulation time 260284532 ps
CPU time 1.43 seconds
Started Mar 17 03:04:33 PM PDT 24
Finished Mar 17 03:04:34 PM PDT 24
Peak memory 201064 kb
Host smart-6fe91dc9-90cf-4a60-a629-02f815b8e3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871028872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3871028872
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2466078054
Short name T330
Test name
Test status
Simulation time 4209612694 ps
CPU time 15 seconds
Started Mar 17 03:04:35 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 209328 kb
Host smart-04037530-6f72-4203-8267-f7951c621a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466078054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2466078054
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3419557078
Short name T398
Test name
Test status
Simulation time 322371787 ps
CPU time 2.07 seconds
Started Mar 17 03:04:35 PM PDT 24
Finished Mar 17 03:04:37 PM PDT 24
Peak memory 200972 kb
Host smart-ab31f0bf-5bcf-474a-8abe-3a38ddd07af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419557078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3419557078
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1062220366
Short name T189
Test name
Test status
Simulation time 291037179 ps
CPU time 1.52 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:41 PM PDT 24
Peak memory 201096 kb
Host smart-82f621aa-fb12-490c-af4d-3a62e3222e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062220366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1062220366
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.94337286
Short name T341
Test name
Test status
Simulation time 72196834 ps
CPU time 0.78 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 200760 kb
Host smart-ead8c4dc-eaa0-4422-9c9a-7cd6ecf8159f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94337286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.94337286
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2921264545
Short name T33
Test name
Test status
Simulation time 1896053184 ps
CPU time 6.96 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 218568 kb
Host smart-0f607d2c-c5d3-47cf-9f58-86b1ca9d8e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921264545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2921264545
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1657484269
Short name T352
Test name
Test status
Simulation time 243943174 ps
CPU time 1.05 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 218208 kb
Host smart-dfccf3d6-c247-47e2-836d-068a2621e43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657484269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1657484269
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3285996622
Short name T490
Test name
Test status
Simulation time 185787829 ps
CPU time 0.85 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:41 PM PDT 24
Peak memory 200792 kb
Host smart-e4dc57bd-f82b-4179-ac8f-6da3a790b9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285996622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3285996622
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3322228742
Short name T90
Test name
Test status
Simulation time 1903754301 ps
CPU time 7.7 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:47 PM PDT 24
Peak memory 201056 kb
Host smart-ee1139d0-21fa-49cd-959f-c54e0b27553b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322228742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3322228742
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.539902982
Short name T432
Test name
Test status
Simulation time 94696853 ps
CPU time 1.02 seconds
Started Mar 17 03:04:38 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 200888 kb
Host smart-c1e3401f-6377-45c7-876f-beded3b46d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539902982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.539902982
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2944099869
Short name T288
Test name
Test status
Simulation time 188536691 ps
CPU time 1.41 seconds
Started Mar 17 03:04:35 PM PDT 24
Finished Mar 17 03:04:37 PM PDT 24
Peak memory 201124 kb
Host smart-48c4177a-ea58-40f7-9ebc-1eb721ecc672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944099869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2944099869
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.586980485
Short name T207
Test name
Test status
Simulation time 9623658931 ps
CPU time 37.93 seconds
Started Mar 17 03:04:38 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 201164 kb
Host smart-a44d5e3f-8d9f-495c-811e-61c4dcf976c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586980485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.586980485
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4229660322
Short name T482
Test name
Test status
Simulation time 338318247 ps
CPU time 2.25 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:41 PM PDT 24
Peak memory 209264 kb
Host smart-717d2b6f-86b0-4f34-a4fe-9eb049f6e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229660322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4229660322
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.708046568
Short name T381
Test name
Test status
Simulation time 73524050 ps
CPU time 0.76 seconds
Started Mar 17 03:04:41 PM PDT 24
Finished Mar 17 03:04:42 PM PDT 24
Peak memory 200780 kb
Host smart-faa685b9-5674-497c-9cb3-e0576a3ebabc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708046568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.708046568
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3118396702
Short name T403
Test name
Test status
Simulation time 2366000178 ps
CPU time 8.75 seconds
Started Mar 17 03:04:38 PM PDT 24
Finished Mar 17 03:04:47 PM PDT 24
Peak memory 218372 kb
Host smart-cc9d26c9-7557-4377-ba0d-fe08995aaa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118396702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3118396702
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2407028177
Short name T177
Test name
Test status
Simulation time 244248895 ps
CPU time 1.13 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:40 PM PDT 24
Peak memory 218172 kb
Host smart-5c8c2290-aafe-4ec6-890e-39ac548ae1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407028177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2407028177
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3575393519
Short name T376
Test name
Test status
Simulation time 1754000544 ps
CPU time 6.37 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:43 PM PDT 24
Peak memory 201248 kb
Host smart-4791ff32-fa77-4ac4-ab39-d1d74c0ae5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575393519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3575393519
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.4149364637
Short name T444
Test name
Test status
Simulation time 152413482 ps
CPU time 1.16 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 200860 kb
Host smart-d2cc808f-19ae-493b-9c21-962369fabbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149364637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.4149364637
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3067371691
Short name T453
Test name
Test status
Simulation time 259527365 ps
CPU time 1.55 seconds
Started Mar 17 03:04:36 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 201116 kb
Host smart-1c145942-0102-4998-8215-027b4d88beb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067371691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3067371691
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2547709404
Short name T224
Test name
Test status
Simulation time 152113493 ps
CPU time 1.43 seconds
Started Mar 17 03:04:41 PM PDT 24
Finished Mar 17 03:04:43 PM PDT 24
Peak memory 200964 kb
Host smart-8d6734a4-88b3-4fa4-a76c-25095899f431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547709404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2547709404
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3900251491
Short name T452
Test name
Test status
Simulation time 294578594 ps
CPU time 2.06 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:41 PM PDT 24
Peak memory 209352 kb
Host smart-c3a82d82-5306-4b12-9451-93dc2695daf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900251491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3900251491
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3215179596
Short name T347
Test name
Test status
Simulation time 256084190 ps
CPU time 1.39 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 200784 kb
Host smart-c3b0b0cc-f516-44b9-b15e-dfe982928631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215179596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3215179596
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4287371161
Short name T179
Test name
Test status
Simulation time 69950690 ps
CPU time 0.78 seconds
Started Mar 17 03:04:36 PM PDT 24
Finished Mar 17 03:04:37 PM PDT 24
Peak memory 200768 kb
Host smart-d09b3dc1-06d1-49ca-b934-04b0777a009c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287371161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4287371161
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1237650136
Short name T39
Test name
Test status
Simulation time 1225697541 ps
CPU time 5.54 seconds
Started Mar 17 03:04:38 PM PDT 24
Finished Mar 17 03:04:44 PM PDT 24
Peak memory 230460 kb
Host smart-a258a783-db92-47bc-80af-75220a63301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237650136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1237650136
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4273815843
Short name T235
Test name
Test status
Simulation time 243622585 ps
CPU time 1.07 seconds
Started Mar 17 03:04:38 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 218100 kb
Host smart-cfdefee8-f292-46b6-a4f4-85716b69cd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273815843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4273815843
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.579630749
Short name T501
Test name
Test status
Simulation time 115120093 ps
CPU time 0.84 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:40 PM PDT 24
Peak memory 200792 kb
Host smart-11324a79-f9ca-4a06-831e-3a66d4970070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579630749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.579630749
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.478925094
Short name T282
Test name
Test status
Simulation time 1190424776 ps
CPU time 5.18 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:44 PM PDT 24
Peak memory 201088 kb
Host smart-cbfc3d67-dcf1-4ec6-939d-4e111aedfd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478925094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.478925094
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2367044844
Short name T44
Test name
Test status
Simulation time 143662017 ps
CPU time 1.21 seconds
Started Mar 17 03:04:42 PM PDT 24
Finished Mar 17 03:04:44 PM PDT 24
Peak memory 200916 kb
Host smart-f5f87212-f1a4-4368-9c81-62ae10d8bb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367044844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2367044844
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1075424488
Short name T178
Test name
Test status
Simulation time 241454885 ps
CPU time 1.41 seconds
Started Mar 17 03:04:38 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 201088 kb
Host smart-7895a691-18d6-43ee-a005-2199e611be02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075424488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1075424488
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3647488080
Short name T357
Test name
Test status
Simulation time 4323264242 ps
CPU time 18.54 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:58 PM PDT 24
Peak memory 201220 kb
Host smart-82af2e9a-70cc-416a-bd27-2512818733ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647488080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3647488080
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.789701409
Short name T540
Test name
Test status
Simulation time 152992217 ps
CPU time 1.91 seconds
Started Mar 17 03:04:38 PM PDT 24
Finished Mar 17 03:04:40 PM PDT 24
Peak memory 200960 kb
Host smart-378965ad-1e06-4747-a5ab-4b8c1dbb2e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789701409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.789701409
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1380371192
Short name T520
Test name
Test status
Simulation time 66947418 ps
CPU time 0.8 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 200852 kb
Host smart-2cf6aa29-c82c-4e8b-b8f0-0d037163e274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380371192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1380371192
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3244912515
Short name T258
Test name
Test status
Simulation time 79439396 ps
CPU time 0.78 seconds
Started Mar 17 03:03:58 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 200776 kb
Host smart-8586fc5d-ab4e-4621-a05e-9452651305ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244912515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3244912515
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2429851155
Short name T442
Test name
Test status
Simulation time 2363096743 ps
CPU time 8.76 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:04:05 PM PDT 24
Peak memory 222764 kb
Host smart-082e1cb4-2af2-424b-8df4-f4e67f2fc721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429851155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2429851155
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2003834013
Short name T368
Test name
Test status
Simulation time 243900368 ps
CPU time 1.16 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 218144 kb
Host smart-6fa690dc-ad85-4c23-b223-291f3a1e3472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003834013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2003834013
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4042222243
Short name T283
Test name
Test status
Simulation time 207617951 ps
CPU time 0.95 seconds
Started Mar 17 03:03:56 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 200720 kb
Host smart-40ab8e3f-489b-4af4-ba26-89aa9dee2c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042222243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4042222243
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2411289715
Short name T250
Test name
Test status
Simulation time 1600631444 ps
CPU time 6.14 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:04:02 PM PDT 24
Peak memory 201076 kb
Host smart-f099042c-b549-4f9b-b247-4198b3a39814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411289715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2411289715
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2340426057
Short name T58
Test name
Test status
Simulation time 16678048974 ps
CPU time 24.72 seconds
Started Mar 17 03:03:56 PM PDT 24
Finished Mar 17 03:04:23 PM PDT 24
Peak memory 218772 kb
Host smart-31eda1c9-30c2-439b-8a8b-93f9039c6f11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340426057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2340426057
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1834397791
Short name T508
Test name
Test status
Simulation time 224416572 ps
CPU time 1.4 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 200996 kb
Host smart-49eef098-73f0-47c4-89b8-7c0a61d19ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834397791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1834397791
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.651501026
Short name T74
Test name
Test status
Simulation time 5284412061 ps
CPU time 17.65 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:04:14 PM PDT 24
Peak memory 209360 kb
Host smart-3acebea3-33a0-4c64-b550-e5dd622039d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651501026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.651501026
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.100017542
Short name T274
Test name
Test status
Simulation time 119121338 ps
CPU time 1.47 seconds
Started Mar 17 03:03:54 PM PDT 24
Finished Mar 17 03:03:57 PM PDT 24
Peak memory 200988 kb
Host smart-3f97f532-f01b-4f55-958e-b595cea7425c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100017542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.100017542
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1447779320
Short name T370
Test name
Test status
Simulation time 259248870 ps
CPU time 1.45 seconds
Started Mar 17 03:03:56 PM PDT 24
Finished Mar 17 03:03:59 PM PDT 24
Peak memory 200868 kb
Host smart-b7a10371-e9a8-498b-b3c3-17e9098c4c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447779320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1447779320
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.532961985
Short name T522
Test name
Test status
Simulation time 77029312 ps
CPU time 0.81 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 200728 kb
Host smart-1336108c-4391-4eaf-8abd-faa7b31f9ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532961985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.532961985
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2556540990
Short name T29
Test name
Test status
Simulation time 1222330803 ps
CPU time 6.1 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 222644 kb
Host smart-a1155786-18cb-48ec-8ed3-ba48a7d15782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556540990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2556540990
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3928302326
Short name T223
Test name
Test status
Simulation time 245249026 ps
CPU time 1.06 seconds
Started Mar 17 03:04:38 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 218292 kb
Host smart-9ca8de8d-bb22-4fdf-9b88-fb62b7ffa6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928302326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3928302326
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2219957818
Short name T210
Test name
Test status
Simulation time 118272069 ps
CPU time 0.82 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 200744 kb
Host smart-9bd6e5df-1ff2-4c9a-9154-909af5693f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219957818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2219957818
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1102141416
Short name T380
Test name
Test status
Simulation time 1531325291 ps
CPU time 5.98 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 201056 kb
Host smart-5d66abca-0972-4857-b43e-e92580cb6414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102141416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1102141416
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2563272070
Short name T297
Test name
Test status
Simulation time 101275789 ps
CPU time 0.95 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 200812 kb
Host smart-60746b2f-1120-426a-aa61-d4b37155e637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563272070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2563272070
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3658009910
Short name T304
Test name
Test status
Simulation time 116746189 ps
CPU time 1.2 seconds
Started Mar 17 03:04:41 PM PDT 24
Finished Mar 17 03:04:42 PM PDT 24
Peak memory 201088 kb
Host smart-620bfa21-26c4-4296-b77e-9c2dc9beae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658009910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3658009910
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2131239363
Short name T399
Test name
Test status
Simulation time 242529290 ps
CPU time 1.69 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:42 PM PDT 24
Peak memory 201044 kb
Host smart-9aea075b-7c18-4b3c-9407-0538749a8e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131239363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2131239363
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1707762971
Short name T197
Test name
Test status
Simulation time 429282080 ps
CPU time 2.44 seconds
Started Mar 17 03:04:36 PM PDT 24
Finished Mar 17 03:04:39 PM PDT 24
Peak memory 209064 kb
Host smart-bfb15764-8d50-4c74-aff0-299525870c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707762971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1707762971
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3739397559
Short name T138
Test name
Test status
Simulation time 92744775 ps
CPU time 0.98 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:41 PM PDT 24
Peak memory 200880 kb
Host smart-5ec12332-580c-4f8e-aef4-6669126d2d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739397559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3739397559
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3361805344
Short name T248
Test name
Test status
Simulation time 75033964 ps
CPU time 0.78 seconds
Started Mar 17 03:04:43 PM PDT 24
Finished Mar 17 03:04:44 PM PDT 24
Peak memory 200784 kb
Host smart-dce29f5a-32c2-4a81-8670-aa36c2c72efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361805344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3361805344
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1367445295
Short name T27
Test name
Test status
Simulation time 1888460908 ps
CPU time 7.22 seconds
Started Mar 17 03:04:45 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 218560 kb
Host smart-c3797aa5-c46c-4538-bb04-cbf3c9b555ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367445295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1367445295
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2110327058
Short name T231
Test name
Test status
Simulation time 245732299 ps
CPU time 1.02 seconds
Started Mar 17 03:04:42 PM PDT 24
Finished Mar 17 03:04:43 PM PDT 24
Peak memory 218160 kb
Host smart-fe017e8f-aba3-4e83-b464-b741f9209c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110327058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2110327058
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1609202986
Short name T10
Test name
Test status
Simulation time 141981498 ps
CPU time 0.77 seconds
Started Mar 17 03:04:36 PM PDT 24
Finished Mar 17 03:04:37 PM PDT 24
Peak memory 200764 kb
Host smart-4f943884-e557-42ce-8197-685a1676f5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609202986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1609202986
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.4180700362
Short name T190
Test name
Test status
Simulation time 1445467905 ps
CPU time 6.1 seconds
Started Mar 17 03:04:39 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 201052 kb
Host smart-e4792576-0536-4127-af8c-a4f52a78e4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180700362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4180700362
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3261379827
Short name T537
Test name
Test status
Simulation time 109230109 ps
CPU time 1 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:41 PM PDT 24
Peak memory 200884 kb
Host smart-1effdba0-1a9d-471b-a39b-5f4b32ebcc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261379827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3261379827
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1425851111
Short name T271
Test name
Test status
Simulation time 122905629 ps
CPU time 1.18 seconds
Started Mar 17 03:04:41 PM PDT 24
Finished Mar 17 03:04:42 PM PDT 24
Peak memory 201084 kb
Host smart-2297a1fa-15e8-42bd-b7ad-b03231d0c1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425851111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1425851111
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2842999115
Short name T276
Test name
Test status
Simulation time 5382037230 ps
CPU time 19.7 seconds
Started Mar 17 03:04:42 PM PDT 24
Finished Mar 17 03:05:02 PM PDT 24
Peak memory 201200 kb
Host smart-57f98981-abb3-4528-8b7f-61d838120b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842999115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2842999115
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3629007465
Short name T206
Test name
Test status
Simulation time 131569613 ps
CPU time 1.63 seconds
Started Mar 17 03:04:40 PM PDT 24
Finished Mar 17 03:04:42 PM PDT 24
Peak memory 209188 kb
Host smart-1489dbc0-4eb9-41ca-8097-abfd86e76f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629007465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3629007465
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.766340033
Short name T305
Test name
Test status
Simulation time 84829108 ps
CPU time 0.93 seconds
Started Mar 17 03:04:37 PM PDT 24
Finished Mar 17 03:04:38 PM PDT 24
Peak memory 200836 kb
Host smart-a90006fa-a3dc-4818-aebd-9b1b3404ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766340033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.766340033
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1276982483
Short name T193
Test name
Test status
Simulation time 53274345 ps
CPU time 0.75 seconds
Started Mar 17 03:04:44 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 200768 kb
Host smart-584adefc-e2eb-4436-bcfc-f8c7a4d55c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276982483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1276982483
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.293306687
Short name T379
Test name
Test status
Simulation time 1880591776 ps
CPU time 6.85 seconds
Started Mar 17 03:04:42 PM PDT 24
Finished Mar 17 03:04:49 PM PDT 24
Peak memory 217964 kb
Host smart-2f2eab6d-781f-432a-bb3b-7bfff691e1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293306687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.293306687
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1024531148
Short name T488
Test name
Test status
Simulation time 244120524 ps
CPU time 1.05 seconds
Started Mar 17 03:04:44 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 218208 kb
Host smart-25bf9816-a9e7-4037-b7a8-b01f3d39917f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024531148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1024531148
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.158130533
Short name T454
Test name
Test status
Simulation time 127652620 ps
CPU time 0.8 seconds
Started Mar 17 03:04:43 PM PDT 24
Finished Mar 17 03:04:44 PM PDT 24
Peak memory 200760 kb
Host smart-c1dcbb37-d589-415a-892f-f97035432cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158130533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.158130533
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2712999909
Short name T295
Test name
Test status
Simulation time 1392797248 ps
CPU time 5.47 seconds
Started Mar 17 03:04:45 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 201124 kb
Host smart-3579ecaa-c43d-4974-ba01-b35d08ab41d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712999909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2712999909
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2954881199
Short name T470
Test name
Test status
Simulation time 103865356 ps
CPU time 1.01 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 200840 kb
Host smart-e99f28b1-587d-406c-a8b4-a973724685ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954881199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2954881199
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1307430688
Short name T256
Test name
Test status
Simulation time 119273175 ps
CPU time 1.15 seconds
Started Mar 17 03:04:43 PM PDT 24
Finished Mar 17 03:04:44 PM PDT 24
Peak memory 201076 kb
Host smart-163f4966-a343-46dc-b604-8496bc79c9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307430688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1307430688
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.965501415
Short name T227
Test name
Test status
Simulation time 3704066457 ps
CPU time 15.98 seconds
Started Mar 17 03:04:43 PM PDT 24
Finished Mar 17 03:05:01 PM PDT 24
Peak memory 201200 kb
Host smart-c5ef2400-6d93-4b46-a68d-748319430b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965501415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.965501415
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2072486015
Short name T476
Test name
Test status
Simulation time 481034777 ps
CPU time 2.58 seconds
Started Mar 17 03:04:41 PM PDT 24
Finished Mar 17 03:04:44 PM PDT 24
Peak memory 200972 kb
Host smart-e40b8e41-6004-402f-b8bd-47fbe75c564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072486015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2072486015
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1145950191
Short name T181
Test name
Test status
Simulation time 158410196 ps
CPU time 1.16 seconds
Started Mar 17 03:04:42 PM PDT 24
Finished Mar 17 03:04:44 PM PDT 24
Peak memory 200860 kb
Host smart-f6d1fe47-14da-420e-89c3-1becb5adcecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145950191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1145950191
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2601034807
Short name T394
Test name
Test status
Simulation time 85448874 ps
CPU time 0.83 seconds
Started Mar 17 03:04:41 PM PDT 24
Finished Mar 17 03:04:42 PM PDT 24
Peak memory 200756 kb
Host smart-080d01a9-2965-47d4-9bec-cbc36968ded9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601034807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2601034807
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3442572361
Short name T35
Test name
Test status
Simulation time 2355430594 ps
CPU time 8.06 seconds
Started Mar 17 03:04:43 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 218772 kb
Host smart-e18fcadb-5056-42f2-b6dd-657d4991bbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442572361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3442572361
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2813077427
Short name T329
Test name
Test status
Simulation time 244149820 ps
CPU time 1.11 seconds
Started Mar 17 03:04:44 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 218300 kb
Host smart-a969fa6c-38ec-4302-97ea-4e7df559067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813077427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2813077427
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1290557465
Short name T173
Test name
Test status
Simulation time 116741708 ps
CPU time 0.83 seconds
Started Mar 17 03:04:44 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 200776 kb
Host smart-9181ac6c-ae4e-4248-a62d-4016784596ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290557465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1290557465
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2751822961
Short name T491
Test name
Test status
Simulation time 893080619 ps
CPU time 4.61 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 201048 kb
Host smart-880ec875-03f3-479e-9c96-5b37732884a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751822961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2751822961
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.4202702609
Short name T371
Test name
Test status
Simulation time 108023267 ps
CPU time 0.99 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 200868 kb
Host smart-584f94ea-1ea1-4ccc-b7cd-5d85bcef8ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202702609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.4202702609
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1466514710
Short name T225
Test name
Test status
Simulation time 252575596 ps
CPU time 1.68 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 201000 kb
Host smart-1b86ec37-d802-4daa-bdde-6ad08f9d5f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466514710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1466514710
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.430641965
Short name T372
Test name
Test status
Simulation time 8865719476 ps
CPU time 31.61 seconds
Started Mar 17 03:04:43 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 209412 kb
Host smart-9c38547d-f5ec-42be-a355-d25723888e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430641965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.430641965
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.850649886
Short name T6
Test name
Test status
Simulation time 502243188 ps
CPU time 2.57 seconds
Started Mar 17 03:04:53 PM PDT 24
Finished Mar 17 03:04:55 PM PDT 24
Peak memory 200924 kb
Host smart-c1ec003a-c5e6-4aed-a677-46652ff6a3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850649886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.850649886
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.741046023
Short name T415
Test name
Test status
Simulation time 133201892 ps
CPU time 1.19 seconds
Started Mar 17 03:04:46 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 200828 kb
Host smart-c06cffa1-f811-4922-bf17-e4f5a61fe4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741046023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.741046023
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2631338873
Short name T481
Test name
Test status
Simulation time 69539521 ps
CPU time 0.79 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:04:49 PM PDT 24
Peak memory 200716 kb
Host smart-ed26257e-d63f-49f3-ab3d-8615639d6bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631338873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2631338873
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4092438856
Short name T421
Test name
Test status
Simulation time 2173807144 ps
CPU time 7.86 seconds
Started Mar 17 03:04:43 PM PDT 24
Finished Mar 17 03:04:51 PM PDT 24
Peak memory 217644 kb
Host smart-3e32f28a-54a5-4d25-9af6-ffef4e92bc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092438856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4092438856
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3612477111
Short name T130
Test name
Test status
Simulation time 244873642 ps
CPU time 1.12 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 218140 kb
Host smart-94fb79b5-37a8-47c5-a042-41a870ead4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612477111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3612477111
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3443261569
Short name T192
Test name
Test status
Simulation time 78689962 ps
CPU time 0.72 seconds
Started Mar 17 03:04:44 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 200720 kb
Host smart-87fc44e8-59ff-4be0-9a5d-ed2ce9e87229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443261569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3443261569
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1172108722
Short name T23
Test name
Test status
Simulation time 958952330 ps
CPU time 4.89 seconds
Started Mar 17 03:04:43 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 200944 kb
Host smart-64e4de72-f3d2-463d-8cec-d93838153f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172108722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1172108722
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.994510748
Short name T238
Test name
Test status
Simulation time 106068826 ps
CPU time 1.11 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:04:49 PM PDT 24
Peak memory 200852 kb
Host smart-e20f8490-6182-4cdc-806d-335a1afb4369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994510748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.994510748
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.438886644
Short name T485
Test name
Test status
Simulation time 118737181 ps
CPU time 1.22 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 201028 kb
Host smart-8dec4edb-d41c-47d6-a37f-4b02d798844d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438886644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.438886644
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1274903633
Short name T245
Test name
Test status
Simulation time 106538244 ps
CPU time 1.47 seconds
Started Mar 17 03:04:46 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 200996 kb
Host smart-367a7717-7e39-48ed-b91a-0784123a7716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274903633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1274903633
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2724447924
Short name T541
Test name
Test status
Simulation time 128527284 ps
CPU time 0.96 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:04:49 PM PDT 24
Peak memory 200832 kb
Host smart-78017101-6962-48d2-9e47-d4cc3de4dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724447924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2724447924
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2009101305
Short name T59
Test name
Test status
Simulation time 189531455 ps
CPU time 1.08 seconds
Started Mar 17 03:04:44 PM PDT 24
Finished Mar 17 03:04:46 PM PDT 24
Peak memory 200776 kb
Host smart-5291c362-b596-4c2e-ae9d-3a8bcd78adc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009101305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2009101305
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.4082327744
Short name T423
Test name
Test status
Simulation time 1896512241 ps
CPU time 7.34 seconds
Started Mar 17 03:04:45 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 217584 kb
Host smart-5d818bed-0694-4e1b-977b-4919fdd94b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082327744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.4082327744
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1676694131
Short name T269
Test name
Test status
Simulation time 243981752 ps
CPU time 1.1 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 218124 kb
Host smart-b6301101-e9d6-41a2-8f64-1fca6a946953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676694131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1676694131
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.805082529
Short name T9
Test name
Test status
Simulation time 202329055 ps
CPU time 0.93 seconds
Started Mar 17 03:04:53 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 200756 kb
Host smart-4dce706c-7553-4a45-a3ce-3f186b67cdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805082529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.805082529
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.502898650
Short name T348
Test name
Test status
Simulation time 1064911707 ps
CPU time 5.25 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 201012 kb
Host smart-2153a0d7-8986-4299-ab8d-712f17114a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502898650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.502898650
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2057234418
Short name T151
Test name
Test status
Simulation time 110903193 ps
CPU time 1.06 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:04:49 PM PDT 24
Peak memory 200832 kb
Host smart-884092dc-8c84-4209-b6a1-deb1b504be36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057234418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2057234418
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2137500577
Short name T139
Test name
Test status
Simulation time 203162895 ps
CPU time 1.56 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:51 PM PDT 24
Peak memory 201012 kb
Host smart-812ea897-8c13-453f-ada3-a17f0ce4e067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137500577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2137500577
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1454035209
Short name T91
Test name
Test status
Simulation time 9821893636 ps
CPU time 39.82 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:05:27 PM PDT 24
Peak memory 209320 kb
Host smart-96e649f4-8a7a-4f5f-a5b2-1227856a1244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454035209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1454035209
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3418082933
Short name T327
Test name
Test status
Simulation time 140784358 ps
CPU time 1.77 seconds
Started Mar 17 03:04:53 PM PDT 24
Finished Mar 17 03:04:55 PM PDT 24
Peak memory 200976 kb
Host smart-905d402a-5801-4fcc-89c1-52a1930e462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418082933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3418082933
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.4152680678
Short name T532
Test name
Test status
Simulation time 195538062 ps
CPU time 1.26 seconds
Started Mar 17 03:04:46 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 200916 kb
Host smart-0e583f5e-3661-471a-9e44-8c7e0bd06bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152680678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.4152680678
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2745259026
Short name T263
Test name
Test status
Simulation time 59534429 ps
CPU time 0.78 seconds
Started Mar 17 03:04:50 PM PDT 24
Finished Mar 17 03:04:52 PM PDT 24
Peak memory 200768 kb
Host smart-be5fbdf1-3d9e-49b3-9a03-58d8886cdd2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745259026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2745259026
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1614868391
Short name T406
Test name
Test status
Simulation time 1885833999 ps
CPU time 7.25 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:59 PM PDT 24
Peak memory 221856 kb
Host smart-62be5b09-b259-40b2-9717-955bed3cbb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614868391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1614868391
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2209447081
Short name T397
Test name
Test status
Simulation time 244449494 ps
CPU time 1.08 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 218256 kb
Host smart-fb21e61b-0cca-4228-b1f2-f189576f8cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209447081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2209447081
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.34105834
Short name T161
Test name
Test status
Simulation time 225233674 ps
CPU time 0.91 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 200724 kb
Host smart-3a4aacb8-9bb6-4835-9297-36d75333f972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34105834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.34105834
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.817307183
Short name T340
Test name
Test status
Simulation time 899243175 ps
CPU time 4.34 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 201080 kb
Host smart-bdf5013e-1c90-45dd-8ac3-609470137634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817307183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.817307183
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.4096859652
Short name T25
Test name
Test status
Simulation time 113817625 ps
CPU time 1.03 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 200856 kb
Host smart-ddd55a6a-616a-4454-9571-c78fae194218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096859652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.4096859652
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2072874800
Short name T407
Test name
Test status
Simulation time 116941317 ps
CPU time 1.2 seconds
Started Mar 17 03:04:53 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 201048 kb
Host smart-458bd084-815f-444b-b067-e83b8cb83c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072874800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2072874800
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.85492261
Short name T356
Test name
Test status
Simulation time 5499833314 ps
CPU time 26.09 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:05:13 PM PDT 24
Peak memory 201200 kb
Host smart-d7336bb2-f2a9-48a2-a8aa-d9ac00bae753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85492261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.85492261
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3740604904
Short name T350
Test name
Test status
Simulation time 150953117 ps
CPU time 1.96 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 200884 kb
Host smart-c6f2e2fe-3d90-423b-a6f2-2da6b7b156cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740604904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3740604904
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1528470755
Short name T369
Test name
Test status
Simulation time 136745935 ps
CPU time 1.07 seconds
Started Mar 17 03:04:50 PM PDT 24
Finished Mar 17 03:04:52 PM PDT 24
Peak memory 200864 kb
Host smart-5067842a-8ded-4076-a32b-61ae04fe3b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528470755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1528470755
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.631255628
Short name T157
Test name
Test status
Simulation time 72441381 ps
CPU time 0.83 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 200724 kb
Host smart-3adf2011-4fd1-4189-a10d-c88799502270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631255628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.631255628
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.4151646376
Short name T445
Test name
Test status
Simulation time 1226547260 ps
CPU time 5.65 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:58 PM PDT 24
Peak memory 218500 kb
Host smart-3aba87ba-425d-490b-a003-5f65e106c48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151646376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.4151646376
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3136350544
Short name T384
Test name
Test status
Simulation time 244404752 ps
CPU time 1.03 seconds
Started Mar 17 03:04:46 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 218120 kb
Host smart-bb99d981-e773-4ee7-9deb-fc966761175d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136350544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3136350544
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.764972907
Short name T441
Test name
Test status
Simulation time 136200085 ps
CPU time 0.83 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 200776 kb
Host smart-fe4ce2d9-3dba-4bae-a2ad-638731be4183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764972907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.764972907
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1193960704
Short name T253
Test name
Test status
Simulation time 1086580495 ps
CPU time 5.45 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 201108 kb
Host smart-0b7ab4ca-eb40-4c14-99ed-c7d92d631941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193960704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1193960704
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2337878713
Short name T211
Test name
Test status
Simulation time 94373903 ps
CPU time 1.01 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 200840 kb
Host smart-87651d78-8d1b-409c-8668-89ce7bacb11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337878713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2337878713
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2508838390
Short name T534
Test name
Test status
Simulation time 114574487 ps
CPU time 1.21 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:04:49 PM PDT 24
Peak memory 201116 kb
Host smart-0f7fb745-eb80-4fae-a62f-d210cfc79f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508838390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2508838390
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2442530229
Short name T462
Test name
Test status
Simulation time 5127659353 ps
CPU time 25.32 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 201232 kb
Host smart-bf1934f8-6976-4e67-8fcb-44213e4eb0a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442530229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2442530229
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.983662363
Short name T233
Test name
Test status
Simulation time 347738176 ps
CPU time 2.28 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:52 PM PDT 24
Peak memory 200920 kb
Host smart-64e95ed5-5d24-4b3d-9ac6-f4fc952fab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983662363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.983662363
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3739524846
Short name T447
Test name
Test status
Simulation time 180619929 ps
CPU time 1.33 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:04:49 PM PDT 24
Peak memory 200852 kb
Host smart-9b9de874-1cb8-41ab-8a6b-40cbf7cd06d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739524846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3739524846
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4285327785
Short name T299
Test name
Test status
Simulation time 59106800 ps
CPU time 0.77 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 200728 kb
Host smart-84d05289-ae71-4297-83b3-c36432912b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285327785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4285327785
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4287996730
Short name T28
Test name
Test status
Simulation time 1222169453 ps
CPU time 5.87 seconds
Started Mar 17 03:04:50 PM PDT 24
Finished Mar 17 03:04:56 PM PDT 24
Peak memory 222584 kb
Host smart-af35d8ba-143c-4932-ac10-5ce37c989e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287996730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4287996730
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1642228853
Short name T160
Test name
Test status
Simulation time 244702254 ps
CPU time 1.04 seconds
Started Mar 17 03:04:46 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 218196 kb
Host smart-9d288a75-50f3-47bd-83c6-2bce5af7d449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642228853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1642228853
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.414058185
Short name T20
Test name
Test status
Simulation time 174902878 ps
CPU time 0.93 seconds
Started Mar 17 03:04:50 PM PDT 24
Finished Mar 17 03:04:51 PM PDT 24
Peak memory 200780 kb
Host smart-1c24d2a8-0382-4caa-9d4b-70d9f475ec9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414058185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.414058185
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1777411526
Short name T272
Test name
Test status
Simulation time 1036920381 ps
CPU time 5.16 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:55 PM PDT 24
Peak memory 201092 kb
Host smart-594a0a28-a6d0-4d87-b688-99d790712308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777411526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1777411526
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2868556492
Short name T422
Test name
Test status
Simulation time 141824305 ps
CPU time 1.17 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:04:48 PM PDT 24
Peak memory 200812 kb
Host smart-ba9ab686-92ad-4a41-af64-052ebfddbe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868556492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2868556492
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2269860581
Short name T431
Test name
Test status
Simulation time 114451441 ps
CPU time 1.28 seconds
Started Mar 17 03:04:51 PM PDT 24
Finished Mar 17 03:04:52 PM PDT 24
Peak memory 201052 kb
Host smart-e000f31b-8bff-40c3-afa2-b3804db673e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269860581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2269860581
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.745323530
Short name T119
Test name
Test status
Simulation time 1581840582 ps
CPU time 6.46 seconds
Started Mar 17 03:04:50 PM PDT 24
Finished Mar 17 03:04:56 PM PDT 24
Peak memory 201072 kb
Host smart-13f45298-d77f-45d6-b3cd-4053a9a7f87f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745323530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.745323530
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1320670708
Short name T166
Test name
Test status
Simulation time 348159751 ps
CPU time 2.3 seconds
Started Mar 17 03:04:49 PM PDT 24
Finished Mar 17 03:04:51 PM PDT 24
Peak memory 200876 kb
Host smart-4dc2658b-d4fd-4a85-856b-8007e53c8caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320670708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1320670708
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1420594568
Short name T143
Test name
Test status
Simulation time 169111587 ps
CPU time 1.26 seconds
Started Mar 17 03:04:47 PM PDT 24
Finished Mar 17 03:04:49 PM PDT 24
Peak memory 201024 kb
Host smart-ad4917a6-a6e3-4316-af93-dd78f8ffe456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420594568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1420594568
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3912667833
Short name T60
Test name
Test status
Simulation time 84400313 ps
CPU time 0.81 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 200756 kb
Host smart-9cb366b8-dcf5-41e6-aa68-945e725e0300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912667833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3912667833
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2089219862
Short name T460
Test name
Test status
Simulation time 1224127666 ps
CPU time 5.85 seconds
Started Mar 17 03:04:53 PM PDT 24
Finished Mar 17 03:04:59 PM PDT 24
Peak memory 222660 kb
Host smart-63f89fe0-7535-49d4-b5f6-031b0581ab88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089219862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2089219862
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.146375800
Short name T15
Test name
Test status
Simulation time 244906064 ps
CPU time 1.06 seconds
Started Mar 17 03:04:51 PM PDT 24
Finished Mar 17 03:04:52 PM PDT 24
Peak memory 218280 kb
Host smart-edcd251e-abef-4ced-a72e-3c4ab9cfcca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146375800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.146375800
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2235738362
Short name T335
Test name
Test status
Simulation time 106703936 ps
CPU time 0.77 seconds
Started Mar 17 03:04:48 PM PDT 24
Finished Mar 17 03:04:49 PM PDT 24
Peak memory 200716 kb
Host smart-2b94e5e5-9666-410f-87bd-25ab7c3f4f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235738362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2235738362
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2814113663
Short name T71
Test name
Test status
Simulation time 1494083245 ps
CPU time 5.75 seconds
Started Mar 17 03:04:50 PM PDT 24
Finished Mar 17 03:04:55 PM PDT 24
Peak memory 201088 kb
Host smart-0a370e3e-e453-40d8-b59d-13473b40b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814113663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2814113663
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3030165200
Short name T26
Test name
Test status
Simulation time 95486286 ps
CPU time 1 seconds
Started Mar 17 03:04:55 PM PDT 24
Finished Mar 17 03:04:57 PM PDT 24
Peak memory 200920 kb
Host smart-1bf5462b-b8e3-4d23-9b04-2abdb15abd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030165200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3030165200
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.464305584
Short name T176
Test name
Test status
Simulation time 122817754 ps
CPU time 1.23 seconds
Started Mar 17 03:04:50 PM PDT 24
Finished Mar 17 03:04:51 PM PDT 24
Peak memory 201104 kb
Host smart-350e3f91-5435-4f4b-9c9c-8d1eac10d1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464305584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.464305584
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1002651021
Short name T478
Test name
Test status
Simulation time 8435979885 ps
CPU time 34.81 seconds
Started Mar 17 03:04:55 PM PDT 24
Finished Mar 17 03:05:31 PM PDT 24
Peak memory 211124 kb
Host smart-f8ba7c19-8b32-44a3-bad6-9dbd87a24a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002651021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1002651021
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1250953273
Short name T252
Test name
Test status
Simulation time 141072277 ps
CPU time 1.84 seconds
Started Mar 17 03:04:53 PM PDT 24
Finished Mar 17 03:04:55 PM PDT 24
Peak memory 200880 kb
Host smart-3b8a7e83-f219-40b9-a952-ec51055546da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250953273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1250953273
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1418643126
Short name T342
Test name
Test status
Simulation time 211689413 ps
CPU time 1.41 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 200916 kb
Host smart-b188d773-c935-42fe-a807-7029d4d74b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418643126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1418643126
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3359923099
Short name T215
Test name
Test status
Simulation time 57870961 ps
CPU time 0.75 seconds
Started Mar 17 03:04:04 PM PDT 24
Finished Mar 17 03:04:05 PM PDT 24
Peak memory 200784 kb
Host smart-e65cf179-3f54-4c54-a0c6-e029dfc4083e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359923099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3359923099
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2287423635
Short name T536
Test name
Test status
Simulation time 1223550147 ps
CPU time 5.38 seconds
Started Mar 17 03:04:00 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 218496 kb
Host smart-8427ae2a-c545-4d88-9f99-c28700a8e7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287423635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2287423635
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.906423170
Short name T448
Test name
Test status
Simulation time 244036008 ps
CPU time 1.02 seconds
Started Mar 17 03:03:59 PM PDT 24
Finished Mar 17 03:04:01 PM PDT 24
Peak memory 218188 kb
Host smart-63635009-feb0-4033-ae89-b30a69accc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906423170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.906423170
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1700802133
Short name T11
Test name
Test status
Simulation time 93065688 ps
CPU time 0.77 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:03:57 PM PDT 24
Peak memory 200708 kb
Host smart-a22de3ab-1583-4a8f-a8ac-3f48711ca6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700802133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1700802133
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.607854435
Short name T365
Test name
Test status
Simulation time 988654327 ps
CPU time 5.02 seconds
Started Mar 17 03:03:56 PM PDT 24
Finished Mar 17 03:04:02 PM PDT 24
Peak memory 201068 kb
Host smart-9196d938-dd5a-465b-8a6b-ce28cd2da62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607854435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.607854435
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.339238472
Short name T496
Test name
Test status
Simulation time 179778865 ps
CPU time 1.13 seconds
Started Mar 17 03:04:00 PM PDT 24
Finished Mar 17 03:04:03 PM PDT 24
Peak memory 200844 kb
Host smart-8ebb64a6-edc7-4637-9061-068362882014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339238472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.339238472
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3968802386
Short name T391
Test name
Test status
Simulation time 223279598 ps
CPU time 1.58 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 201020 kb
Host smart-9a44b51d-8ae8-42af-a49f-7a8cc61f8b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968802386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3968802386
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1113916669
Short name T208
Test name
Test status
Simulation time 3470217296 ps
CPU time 15.75 seconds
Started Mar 17 03:03:59 PM PDT 24
Finished Mar 17 03:04:16 PM PDT 24
Peak memory 209380 kb
Host smart-a89ba55f-e254-4fda-b148-fd448b24d4b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113916669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1113916669
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3967915988
Short name T500
Test name
Test status
Simulation time 439325034 ps
CPU time 2.43 seconds
Started Mar 17 03:03:59 PM PDT 24
Finished Mar 17 03:04:03 PM PDT 24
Peak memory 200900 kb
Host smart-bc134be8-962a-4b03-b70f-9e5b993856b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967915988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3967915988
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.84625150
Short name T153
Test name
Test status
Simulation time 184625192 ps
CPU time 1.2 seconds
Started Mar 17 03:03:55 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 200916 kb
Host smart-60f74aa7-5a34-4fde-9d46-6666b9f9a922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84625150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.84625150
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3733989688
Short name T146
Test name
Test status
Simulation time 67159780 ps
CPU time 0.8 seconds
Started Mar 17 03:04:56 PM PDT 24
Finished Mar 17 03:04:57 PM PDT 24
Peak memory 200792 kb
Host smart-37bd69a5-87ca-45b3-9282-5f099694b34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733989688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3733989688
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3781847633
Short name T420
Test name
Test status
Simulation time 1906924728 ps
CPU time 7.47 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:05:00 PM PDT 24
Peak memory 218100 kb
Host smart-e6ba9d0f-38f7-4e4c-a3ff-b8d8b8a5a207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781847633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3781847633
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1293179214
Short name T132
Test name
Test status
Simulation time 244356112 ps
CPU time 1.11 seconds
Started Mar 17 03:04:54 PM PDT 24
Finished Mar 17 03:04:55 PM PDT 24
Peak memory 218264 kb
Host smart-c548bb20-4160-4445-b3db-dfdeb2a23bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293179214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1293179214
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.625956161
Short name T220
Test name
Test status
Simulation time 113490367 ps
CPU time 0.79 seconds
Started Mar 17 03:05:06 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 200936 kb
Host smart-c96f6494-7ec8-4f81-8d98-47dec6fc49aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625956161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.625956161
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3831348525
Short name T410
Test name
Test status
Simulation time 1874012587 ps
CPU time 7.29 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:59 PM PDT 24
Peak memory 201080 kb
Host smart-31da63d1-bded-4ec3-943b-89485c0917a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831348525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3831348525
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.300222035
Short name T251
Test name
Test status
Simulation time 170856251 ps
CPU time 1.13 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 200824 kb
Host smart-7e572897-5a78-45da-b2d5-2bc943a12a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300222035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.300222035
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4164680504
Short name T323
Test name
Test status
Simulation time 111616226 ps
CPU time 1.3 seconds
Started Mar 17 03:04:51 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 201016 kb
Host smart-341ee65f-6edf-45b0-8149-a5a3f780c55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164680504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4164680504
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1670359158
Short name T244
Test name
Test status
Simulation time 7102842038 ps
CPU time 26.42 seconds
Started Mar 17 03:04:51 PM PDT 24
Finished Mar 17 03:05:18 PM PDT 24
Peak memory 209404 kb
Host smart-85b1a048-ccff-41dc-8eb5-4aa757449817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670359158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1670359158
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3696168721
Short name T430
Test name
Test status
Simulation time 148033414 ps
CPU time 1.76 seconds
Started Mar 17 03:04:51 PM PDT 24
Finished Mar 17 03:04:53 PM PDT 24
Peak memory 200944 kb
Host smart-78f7341e-656a-4fe2-accb-a536dbd68fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696168721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3696168721
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.412086914
Short name T194
Test name
Test status
Simulation time 77441218 ps
CPU time 0.92 seconds
Started Mar 17 03:04:53 PM PDT 24
Finished Mar 17 03:04:55 PM PDT 24
Peak memory 200924 kb
Host smart-b25e7fb5-c80d-45e8-97c3-2069ea3be4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412086914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.412086914
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2755098212
Short name T353
Test name
Test status
Simulation time 65580967 ps
CPU time 0.74 seconds
Started Mar 17 03:05:02 PM PDT 24
Finished Mar 17 03:05:04 PM PDT 24
Peak memory 200716 kb
Host smart-5a972075-b692-41aa-9523-fe60ede51875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755098212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2755098212
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.797408514
Short name T315
Test name
Test status
Simulation time 1228131515 ps
CPU time 5.95 seconds
Started Mar 17 03:04:59 PM PDT 24
Finished Mar 17 03:05:06 PM PDT 24
Peak memory 218004 kb
Host smart-d42b9e3f-2423-40be-8dad-22f877c33d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797408514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.797408514
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2338863926
Short name T339
Test name
Test status
Simulation time 244861963 ps
CPU time 1.04 seconds
Started Mar 17 03:04:59 PM PDT 24
Finished Mar 17 03:05:01 PM PDT 24
Peak memory 218392 kb
Host smart-be6e1b12-be7b-4fba-8cb0-f60d2cb7ce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338863926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2338863926
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.212559330
Short name T154
Test name
Test status
Simulation time 105830890 ps
CPU time 0.85 seconds
Started Mar 17 03:04:56 PM PDT 24
Finished Mar 17 03:04:57 PM PDT 24
Peak memory 200776 kb
Host smart-0baacd7c-0791-4c71-bf4e-db8db42868b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212559330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.212559330
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1531494657
Short name T473
Test name
Test status
Simulation time 1633536293 ps
CPU time 7.15 seconds
Started Mar 17 03:04:51 PM PDT 24
Finished Mar 17 03:04:59 PM PDT 24
Peak memory 201084 kb
Host smart-16c364b1-dde0-4758-8522-1e52b5819e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531494657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1531494657
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.190054676
Short name T459
Test name
Test status
Simulation time 99822123 ps
CPU time 0.97 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 200844 kb
Host smart-153b47c2-96bf-49d7-be7c-f91cf3fee2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190054676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.190054676
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1544619047
Short name T375
Test name
Test status
Simulation time 252493255 ps
CPU time 1.51 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 201020 kb
Host smart-4ce5fbbf-eb01-48cc-b2fe-7a7f8a3f0f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544619047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1544619047
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.4243988298
Short name T349
Test name
Test status
Simulation time 2799264067 ps
CPU time 12.15 seconds
Started Mar 17 03:05:00 PM PDT 24
Finished Mar 17 03:05:14 PM PDT 24
Peak memory 201220 kb
Host smart-bbd84173-a707-4bde-8ed4-fde031948365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243988298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4243988298
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.523471249
Short name T455
Test name
Test status
Simulation time 137989794 ps
CPU time 1.66 seconds
Started Mar 17 03:04:52 PM PDT 24
Finished Mar 17 03:04:54 PM PDT 24
Peak memory 209176 kb
Host smart-fe95fb5e-e318-4a48-a347-ecb1b8544c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523471249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.523471249
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.871720819
Short name T466
Test name
Test status
Simulation time 213408022 ps
CPU time 1.37 seconds
Started Mar 17 03:04:55 PM PDT 24
Finished Mar 17 03:04:58 PM PDT 24
Peak memory 200924 kb
Host smart-879678e0-a3a0-43ca-9b69-5836d7188299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871720819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.871720819
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1515602069
Short name T504
Test name
Test status
Simulation time 71690501 ps
CPU time 0.8 seconds
Started Mar 17 03:04:57 PM PDT 24
Finished Mar 17 03:04:58 PM PDT 24
Peak memory 200724 kb
Host smart-877bf153-f0ab-4464-a30a-b2d0d7b11ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515602069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1515602069
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2520434422
Short name T378
Test name
Test status
Simulation time 1217117827 ps
CPU time 5.71 seconds
Started Mar 17 03:04:56 PM PDT 24
Finished Mar 17 03:05:02 PM PDT 24
Peak memory 218028 kb
Host smart-613c4198-88b3-4702-a65c-eb83db62a3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520434422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2520434422
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1002145866
Short name T8
Test name
Test status
Simulation time 243824963 ps
CPU time 1.03 seconds
Started Mar 17 03:04:57 PM PDT 24
Finished Mar 17 03:04:59 PM PDT 24
Peak memory 218184 kb
Host smart-56dd0307-8c4d-4a61-8e6b-0c3d128c6747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002145866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1002145866
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2079463721
Short name T437
Test name
Test status
Simulation time 136694783 ps
CPU time 0.82 seconds
Started Mar 17 03:04:57 PM PDT 24
Finished Mar 17 03:04:58 PM PDT 24
Peak memory 200776 kb
Host smart-d78adc0d-a435-44b4-90cc-29bf361dc39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079463721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2079463721
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1323588085
Short name T382
Test name
Test status
Simulation time 1487415881 ps
CPU time 6.09 seconds
Started Mar 17 03:04:58 PM PDT 24
Finished Mar 17 03:05:05 PM PDT 24
Peak memory 201096 kb
Host smart-d810ef7f-ac7d-49ba-83ed-e59771260446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323588085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1323588085
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2033300381
Short name T346
Test name
Test status
Simulation time 179120898 ps
CPU time 1.17 seconds
Started Mar 17 03:05:01 PM PDT 24
Finished Mar 17 03:05:04 PM PDT 24
Peak memory 200912 kb
Host smart-5e7f2a57-3dfc-40f9-a5c8-fbc2462496b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033300381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2033300381
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.831356327
Short name T298
Test name
Test status
Simulation time 108953226 ps
CPU time 1.22 seconds
Started Mar 17 03:04:58 PM PDT 24
Finished Mar 17 03:05:00 PM PDT 24
Peak memory 201104 kb
Host smart-cc4bb47c-0946-428e-9a07-01e5168ccce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831356327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.831356327
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1904636141
Short name T14
Test name
Test status
Simulation time 6955799168 ps
CPU time 26.05 seconds
Started Mar 17 03:04:58 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 201224 kb
Host smart-2e26e923-6087-473e-a828-5c4c9c6023f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904636141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1904636141
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2613413377
Short name T506
Test name
Test status
Simulation time 67874271 ps
CPU time 0.84 seconds
Started Mar 17 03:04:57 PM PDT 24
Finished Mar 17 03:04:59 PM PDT 24
Peak memory 200844 kb
Host smart-3e3ea03e-1f3e-4f78-96f1-32ab6fef792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613413377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2613413377
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2173357172
Short name T172
Test name
Test status
Simulation time 54735415 ps
CPU time 0.73 seconds
Started Mar 17 03:05:08 PM PDT 24
Finished Mar 17 03:05:09 PM PDT 24
Peak memory 200728 kb
Host smart-e4c41591-47be-4da3-9fbf-57325a3979c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173357172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2173357172
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.734099126
Short name T37
Test name
Test status
Simulation time 1221781292 ps
CPU time 5.56 seconds
Started Mar 17 03:04:58 PM PDT 24
Finished Mar 17 03:05:05 PM PDT 24
Peak memory 218016 kb
Host smart-99c15025-d47b-4291-9577-882c22cd008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734099126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.734099126
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2919682110
Short name T294
Test name
Test status
Simulation time 246614751 ps
CPU time 1.04 seconds
Started Mar 17 03:04:59 PM PDT 24
Finished Mar 17 03:05:01 PM PDT 24
Peak memory 218128 kb
Host smart-605dc388-d927-4e9c-b823-341e99f684e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919682110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2919682110
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3500606314
Short name T21
Test name
Test status
Simulation time 89076404 ps
CPU time 0.8 seconds
Started Mar 17 03:05:00 PM PDT 24
Finished Mar 17 03:05:02 PM PDT 24
Peak memory 200768 kb
Host smart-3813e0dd-9eac-4549-aa37-4fb115a5557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500606314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3500606314
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3331005026
Short name T449
Test name
Test status
Simulation time 1540087234 ps
CPU time 6.45 seconds
Started Mar 17 03:04:59 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 201124 kb
Host smart-1f8299ce-6387-4554-a3c4-b87c815e5021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331005026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3331005026
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1125722484
Short name T156
Test name
Test status
Simulation time 106568831 ps
CPU time 1.05 seconds
Started Mar 17 03:05:00 PM PDT 24
Finished Mar 17 03:05:02 PM PDT 24
Peak memory 200900 kb
Host smart-d859293f-faf5-4d1e-975e-53cfd7426590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125722484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1125722484
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3133192648
Short name T7
Test name
Test status
Simulation time 125524392 ps
CPU time 1.18 seconds
Started Mar 17 03:04:59 PM PDT 24
Finished Mar 17 03:05:01 PM PDT 24
Peak memory 201020 kb
Host smart-b686ee0a-9953-4bf8-bb52-35c1e787998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133192648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3133192648
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2053155940
Short name T89
Test name
Test status
Simulation time 2283305784 ps
CPU time 10.39 seconds
Started Mar 17 03:04:59 PM PDT 24
Finished Mar 17 03:05:11 PM PDT 24
Peak memory 201176 kb
Host smart-ff9ea5ce-25f7-4600-9f40-0df7a4003a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053155940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2053155940
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2748915505
Short name T43
Test name
Test status
Simulation time 156120215 ps
CPU time 1.87 seconds
Started Mar 17 03:04:58 PM PDT 24
Finished Mar 17 03:05:00 PM PDT 24
Peak memory 200912 kb
Host smart-6edbe774-b370-4105-897d-12fb51cd99b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748915505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2748915505
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.365581720
Short name T360
Test name
Test status
Simulation time 142908164 ps
CPU time 1.15 seconds
Started Mar 17 03:05:01 PM PDT 24
Finished Mar 17 03:05:03 PM PDT 24
Peak memory 200904 kb
Host smart-d2302aba-3ad2-4dcb-a560-240fae654403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365581720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.365581720
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2071819113
Short name T416
Test name
Test status
Simulation time 80901936 ps
CPU time 0.82 seconds
Started Mar 17 03:05:06 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 200764 kb
Host smart-bd555040-cb47-4ac7-8fe0-71a3bd7d235e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071819113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2071819113
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3310030737
Short name T42
Test name
Test status
Simulation time 1223199861 ps
CPU time 5.88 seconds
Started Mar 17 03:05:03 PM PDT 24
Finished Mar 17 03:05:10 PM PDT 24
Peak memory 217576 kb
Host smart-9c9c0e3a-9831-4ae6-840f-583df9314e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310030737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3310030737
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2506238579
Short name T69
Test name
Test status
Simulation time 244240928 ps
CPU time 1.08 seconds
Started Mar 17 03:05:03 PM PDT 24
Finished Mar 17 03:05:05 PM PDT 24
Peak memory 218152 kb
Host smart-868e098c-fc1a-4848-a67f-164e516d64f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506238579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2506238579
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1027916821
Short name T169
Test name
Test status
Simulation time 111107125 ps
CPU time 0.74 seconds
Started Mar 17 03:05:06 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 200772 kb
Host smart-9bbfbb50-6264-40f8-bc65-022597c0d0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027916821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1027916821
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3778538681
Short name T84
Test name
Test status
Simulation time 1416257622 ps
CPU time 6.17 seconds
Started Mar 17 03:05:07 PM PDT 24
Finished Mar 17 03:05:13 PM PDT 24
Peak memory 201036 kb
Host smart-c7c24ec6-8c67-4f64-ac0e-73bc7710406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778538681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3778538681
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.822193927
Short name T136
Test name
Test status
Simulation time 105289184 ps
CPU time 1.04 seconds
Started Mar 17 03:05:05 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 201064 kb
Host smart-f64f41fc-b1fe-47cc-b96a-bd10d76d1ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822193927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.822193927
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3950474868
Short name T229
Test name
Test status
Simulation time 118993030 ps
CPU time 1.25 seconds
Started Mar 17 03:05:07 PM PDT 24
Finished Mar 17 03:05:08 PM PDT 24
Peak memory 201080 kb
Host smart-e9a3eecb-ffb7-4826-b397-3f8e962e8541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950474868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3950474868
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.4266132825
Short name T85
Test name
Test status
Simulation time 7041174960 ps
CPU time 25.47 seconds
Started Mar 17 03:05:07 PM PDT 24
Finished Mar 17 03:05:32 PM PDT 24
Peak memory 201204 kb
Host smart-f4e98a92-4a99-4483-9a7c-ce77721936b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266132825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.4266132825
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1511746508
Short name T409
Test name
Test status
Simulation time 474206003 ps
CPU time 2.8 seconds
Started Mar 17 03:05:05 PM PDT 24
Finished Mar 17 03:05:09 PM PDT 24
Peak memory 200948 kb
Host smart-71c1f66c-69ce-441e-9550-86e8800dbcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511746508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1511746508
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.4122676354
Short name T3
Test name
Test status
Simulation time 264569291 ps
CPU time 1.52 seconds
Started Mar 17 03:05:06 PM PDT 24
Finished Mar 17 03:05:08 PM PDT 24
Peak memory 200920 kb
Host smart-6ec0f9aa-da46-4f77-bc44-eaceea80d9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122676354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4122676354
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.717661096
Short name T285
Test name
Test status
Simulation time 65415400 ps
CPU time 0.77 seconds
Started Mar 17 03:05:06 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 200620 kb
Host smart-6b9d0594-ce25-498c-b9a9-99d3ad305a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717661096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.717661096
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2605208066
Short name T40
Test name
Test status
Simulation time 1220377902 ps
CPU time 6.03 seconds
Started Mar 17 03:05:04 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 218032 kb
Host smart-401905b3-8ec9-409c-af57-c1e812c050ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605208066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2605208066
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2369721313
Short name T477
Test name
Test status
Simulation time 243859798 ps
CPU time 1.06 seconds
Started Mar 17 03:05:04 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 218180 kb
Host smart-89b6f23f-9a90-4da2-ab9e-d7c83142e6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369721313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2369721313
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2898613349
Short name T396
Test name
Test status
Simulation time 102744938 ps
CPU time 0.88 seconds
Started Mar 17 03:05:06 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 200768 kb
Host smart-6b301288-edbb-4aab-8c86-1e79811f302e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898613349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2898613349
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3251273078
Short name T438
Test name
Test status
Simulation time 1150203340 ps
CPU time 5.29 seconds
Started Mar 17 03:05:07 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 201104 kb
Host smart-aa686368-e63c-4a38-87ec-6acc122e6201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251273078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3251273078
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2719782813
Short name T191
Test name
Test status
Simulation time 162574119 ps
CPU time 1.37 seconds
Started Mar 17 03:05:04 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 200884 kb
Host smart-87c27a13-c908-4b3f-ac7f-9307319f7f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719782813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2719782813
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.669147186
Short name T124
Test name
Test status
Simulation time 248694975 ps
CPU time 1.48 seconds
Started Mar 17 03:05:08 PM PDT 24
Finished Mar 17 03:05:10 PM PDT 24
Peak memory 201116 kb
Host smart-23b06d2f-8a4f-4004-a31d-fc7a023fa1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669147186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.669147186
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3655312760
Short name T162
Test name
Test status
Simulation time 941661702 ps
CPU time 5.56 seconds
Started Mar 17 03:05:05 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 201068 kb
Host smart-a8ef166d-dfe7-4692-b377-57f1dbd985f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655312760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3655312760
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1781676566
Short name T458
Test name
Test status
Simulation time 127572477 ps
CPU time 1.54 seconds
Started Mar 17 03:05:05 PM PDT 24
Finished Mar 17 03:05:08 PM PDT 24
Peak memory 200952 kb
Host smart-d51f7f28-cdbe-456f-8034-552ac6c3f85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781676566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1781676566
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3362321178
Short name T159
Test name
Test status
Simulation time 239942716 ps
CPU time 1.57 seconds
Started Mar 17 03:05:07 PM PDT 24
Finished Mar 17 03:05:09 PM PDT 24
Peak memory 201100 kb
Host smart-14b150c7-8f2d-45ea-a3f4-b4a92ed839fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362321178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3362321178
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2733434605
Short name T1
Test name
Test status
Simulation time 61915649 ps
CPU time 0.76 seconds
Started Mar 17 03:05:10 PM PDT 24
Finished Mar 17 03:05:11 PM PDT 24
Peak memory 200724 kb
Host smart-1e562f30-041b-4770-b574-288fac5df252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733434605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2733434605
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4255476845
Short name T499
Test name
Test status
Simulation time 2355923262 ps
CPU time 8.02 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:23 PM PDT 24
Peak memory 218744 kb
Host smart-5eeb1eaf-34bc-42e4-bb5d-79d1750e475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255476845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4255476845
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1330970235
Short name T186
Test name
Test status
Simulation time 244816329 ps
CPU time 1.06 seconds
Started Mar 17 03:05:13 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 218232 kb
Host smart-a53a4988-00f2-4a40-a62e-1300ac121905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330970235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1330970235
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3844012703
Short name T337
Test name
Test status
Simulation time 201696934 ps
CPU time 0.87 seconds
Started Mar 17 03:05:05 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 200612 kb
Host smart-6848bc26-a724-45b9-8a1c-33513b1ef404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844012703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3844012703
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.388834457
Short name T311
Test name
Test status
Simulation time 1916837555 ps
CPU time 7.07 seconds
Started Mar 17 03:05:10 PM PDT 24
Finished Mar 17 03:05:18 PM PDT 24
Peak memory 201084 kb
Host smart-53446a0f-442c-4c9a-bf29-88d39ae7b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388834457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.388834457
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1330863497
Short name T544
Test name
Test status
Simulation time 95246667 ps
CPU time 1 seconds
Started Mar 17 03:05:13 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 200812 kb
Host smart-02c69812-8732-45ed-8d97-868b2fffc3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330863497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1330863497
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.897409956
Short name T259
Test name
Test status
Simulation time 207080910 ps
CPU time 1.42 seconds
Started Mar 17 03:05:04 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 201096 kb
Host smart-2db99b81-daba-40e8-8adf-8fbcb7b4fb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897409956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.897409956
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1161965119
Short name T377
Test name
Test status
Simulation time 1317627060 ps
CPU time 5.04 seconds
Started Mar 17 03:05:12 PM PDT 24
Finished Mar 17 03:05:18 PM PDT 24
Peak memory 201100 kb
Host smart-35c0445f-a683-4320-a605-6cde907fdf4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161965119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1161965119
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.65455988
Short name T284
Test name
Test status
Simulation time 139105892 ps
CPU time 1.74 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 201004 kb
Host smart-481c1e09-f0eb-4a6a-8ca9-cc49c90f66c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65455988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.65455988
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2929698005
Short name T334
Test name
Test status
Simulation time 134490056 ps
CPU time 1.18 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 200884 kb
Host smart-2cc9f03b-d179-42c8-bff3-c2762778e36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929698005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2929698005
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1242263961
Short name T354
Test name
Test status
Simulation time 74985735 ps
CPU time 0.8 seconds
Started Mar 17 03:05:13 PM PDT 24
Finished Mar 17 03:05:14 PM PDT 24
Peak memory 200780 kb
Host smart-45170530-495f-40dc-a4d6-5d91dd2cebed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242263961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1242263961
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3599635121
Short name T519
Test name
Test status
Simulation time 1874264072 ps
CPU time 7.55 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:22 PM PDT 24
Peak memory 222196 kb
Host smart-c91e88cf-72f3-467e-841e-6dc7d998b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599635121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3599635121
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2043244198
Short name T170
Test name
Test status
Simulation time 247159808 ps
CPU time 1.03 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 218152 kb
Host smart-059f4bb8-4d62-40c0-b86c-3ee712a4a2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043244198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2043244198
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2369401882
Short name T180
Test name
Test status
Simulation time 117982985 ps
CPU time 0.86 seconds
Started Mar 17 03:05:10 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 200764 kb
Host smart-178d5ee6-0eb0-4e31-a984-828dfe1223bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369401882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2369401882
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1070473517
Short name T118
Test name
Test status
Simulation time 1515707204 ps
CPU time 5.41 seconds
Started Mar 17 03:05:13 PM PDT 24
Finished Mar 17 03:05:19 PM PDT 24
Peak memory 201068 kb
Host smart-4c4fc09c-7e01-4efc-8285-376993c63aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070473517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1070473517
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.184327580
Short name T277
Test name
Test status
Simulation time 100355639 ps
CPU time 1.02 seconds
Started Mar 17 03:05:13 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 200936 kb
Host smart-8cc451d2-9b23-42b3-a034-1d4c0359a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184327580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.184327580
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3261269927
Short name T308
Test name
Test status
Simulation time 111656649 ps
CPU time 1.16 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 201092 kb
Host smart-78407e27-1eea-43ee-930e-4f8c8a28ba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261269927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3261269927
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2373317647
Short name T469
Test name
Test status
Simulation time 1888458938 ps
CPU time 7.47 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:22 PM PDT 24
Peak memory 209296 kb
Host smart-12fe91ca-36f1-4bc7-b0dd-3ef0a5e85667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373317647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2373317647
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2311279204
Short name T163
Test name
Test status
Simulation time 132567262 ps
CPU time 1.86 seconds
Started Mar 17 03:05:11 PM PDT 24
Finished Mar 17 03:05:13 PM PDT 24
Peak memory 200972 kb
Host smart-3167f4fb-00a7-4804-ba19-8efb72139a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311279204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2311279204
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2612627985
Short name T72
Test name
Test status
Simulation time 156157398 ps
CPU time 1.11 seconds
Started Mar 17 03:05:13 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 200764 kb
Host smart-ff2723ef-f9f8-4010-91be-d0d012ecd0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612627985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2612627985
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3713469670
Short name T140
Test name
Test status
Simulation time 85953390 ps
CPU time 0.77 seconds
Started Mar 17 03:05:11 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 200732 kb
Host smart-831ca23d-aaac-4a77-a640-b63bde191a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713469670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3713469670
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3318208411
Short name T306
Test name
Test status
Simulation time 2182130774 ps
CPU time 7.73 seconds
Started Mar 17 03:05:10 PM PDT 24
Finished Mar 17 03:05:19 PM PDT 24
Peak memory 222660 kb
Host smart-8917a28f-4a82-47bf-a117-0f57a07e1edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318208411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3318208411
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4046194468
Short name T429
Test name
Test status
Simulation time 244250998 ps
CPU time 1.11 seconds
Started Mar 17 03:05:10 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 218276 kb
Host smart-8b315de7-13fd-41aa-8ad6-4e86dbfa8862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046194468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4046194468
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3066829407
Short name T247
Test name
Test status
Simulation time 191365961 ps
CPU time 0.88 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 200712 kb
Host smart-49976753-03ef-4030-9aea-9b55b32bcd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066829407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3066829407
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.336253493
Short name T426
Test name
Test status
Simulation time 2001137531 ps
CPU time 7.83 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:22 PM PDT 24
Peak memory 201088 kb
Host smart-be280c49-180a-4545-8fd6-7a36869d9c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336253493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.336253493
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2289312897
Short name T414
Test name
Test status
Simulation time 176331584 ps
CPU time 1.15 seconds
Started Mar 17 03:05:13 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 200920 kb
Host smart-4ac53a95-476a-4731-baa3-1a03ddfa0dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289312897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2289312897
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.4255018873
Short name T307
Test name
Test status
Simulation time 126527320 ps
CPU time 1.24 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 201004 kb
Host smart-e6ffa348-d770-4ba6-a831-ad2feacb0fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255018873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.4255018873
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.447343917
Short name T363
Test name
Test status
Simulation time 4929369405 ps
CPU time 19.81 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:35 PM PDT 24
Peak memory 201208 kb
Host smart-f709652d-32b7-46f9-a1f7-daada76cc0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447343917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.447343917
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1490090056
Short name T358
Test name
Test status
Simulation time 534290866 ps
CPU time 2.86 seconds
Started Mar 17 03:05:12 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 200956 kb
Host smart-2ae87c9b-a4a6-49a0-b158-5f60ef1e8ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490090056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1490090056
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1973177031
Short name T509
Test name
Test status
Simulation time 97069236 ps
CPU time 0.94 seconds
Started Mar 17 03:05:11 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 200848 kb
Host smart-fea9d760-0139-42b8-ae41-7753b089d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973177031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1973177031
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.84623511
Short name T465
Test name
Test status
Simulation time 68190331 ps
CPU time 0.78 seconds
Started Mar 17 03:05:19 PM PDT 24
Finished Mar 17 03:05:20 PM PDT 24
Peak memory 200720 kb
Host smart-d33c6327-1868-4b4b-aa2c-456353743a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84623511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.84623511
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1208376145
Short name T286
Test name
Test status
Simulation time 1894083925 ps
CPU time 7.04 seconds
Started Mar 17 03:05:13 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 222560 kb
Host smart-8dae4786-e8d5-4d84-bb09-a91672c4309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208376145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1208376145
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3380673823
Short name T205
Test name
Test status
Simulation time 243869299 ps
CPU time 1.08 seconds
Started Mar 17 03:05:15 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 218244 kb
Host smart-aeca4516-d4d1-4337-9a8b-7f2710e304e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380673823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3380673823
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2328134335
Short name T472
Test name
Test status
Simulation time 154207598 ps
CPU time 0.88 seconds
Started Mar 17 03:05:13 PM PDT 24
Finished Mar 17 03:05:14 PM PDT 24
Peak memory 200660 kb
Host smart-ed44742e-4f1e-4e54-8c31-9cf8358bcfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328134335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2328134335
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2268767319
Short name T362
Test name
Test status
Simulation time 1718585145 ps
CPU time 6.93 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 201080 kb
Host smart-624b41ab-997d-4051-9b95-6212364c09dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268767319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2268767319
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3607149935
Short name T533
Test name
Test status
Simulation time 152532446 ps
CPU time 1.21 seconds
Started Mar 17 03:05:12 PM PDT 24
Finished Mar 17 03:05:13 PM PDT 24
Peak memory 200860 kb
Host smart-6085dc01-f938-42ee-982c-5724163b699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607149935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3607149935
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.817283996
Short name T450
Test name
Test status
Simulation time 120697035 ps
CPU time 1.22 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:20 PM PDT 24
Peak memory 201060 kb
Host smart-a32d9960-af97-49c6-a69e-d77cbc99cc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817283996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.817283996
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1539927732
Short name T87
Test name
Test status
Simulation time 2245170382 ps
CPU time 10.66 seconds
Started Mar 17 03:05:16 PM PDT 24
Finished Mar 17 03:05:27 PM PDT 24
Peak memory 209396 kb
Host smart-358f5199-267b-4c35-bf85-a16d02620047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539927732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1539927732
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3343406348
Short name T125
Test name
Test status
Simulation time 452073737 ps
CPU time 2.43 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 200856 kb
Host smart-3cad78f1-bc4f-40c3-bf3b-30d340ceed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343406348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3343406348
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2796024276
Short name T150
Test name
Test status
Simulation time 152362703 ps
CPU time 1.2 seconds
Started Mar 17 03:05:16 PM PDT 24
Finished Mar 17 03:05:18 PM PDT 24
Peak memory 200888 kb
Host smart-32f663ea-677f-4549-a575-093b101b8114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796024276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2796024276
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3589972914
Short name T202
Test name
Test status
Simulation time 76982305 ps
CPU time 0.78 seconds
Started Mar 17 03:04:05 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 200764 kb
Host smart-4d7d3768-b367-4539-8826-b11b75166522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589972914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3589972914
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.442116501
Short name T517
Test name
Test status
Simulation time 1217547706 ps
CPU time 6.19 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:12 PM PDT 24
Peak memory 218620 kb
Host smart-e41420c2-0907-462c-8360-0fa8364ad482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442116501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.442116501
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4065505254
Short name T149
Test name
Test status
Simulation time 244242621 ps
CPU time 1.13 seconds
Started Mar 17 03:04:10 PM PDT 24
Finished Mar 17 03:04:11 PM PDT 24
Peak memory 218168 kb
Host smart-6d21599d-a512-4514-8c9f-ce86d160fef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065505254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4065505254
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2570740089
Short name T400
Test name
Test status
Simulation time 220440907 ps
CPU time 0.91 seconds
Started Mar 17 03:04:05 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 200780 kb
Host smart-0972a3b7-6dea-47e7-9bb1-d2f8521183ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570740089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2570740089
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2314925592
Short name T236
Test name
Test status
Simulation time 1492200077 ps
CPU time 5.75 seconds
Started Mar 17 03:03:59 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 201036 kb
Host smart-5ed0b572-e7a3-47b5-99aa-f62548bd0b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314925592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2314925592
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2287265545
Short name T57
Test name
Test status
Simulation time 8286882282 ps
CPU time 16.6 seconds
Started Mar 17 03:04:08 PM PDT 24
Finished Mar 17 03:04:25 PM PDT 24
Peak memory 217760 kb
Host smart-d8521920-3fd7-4689-87d6-5297aa4945f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287265545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2287265545
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2531611122
Short name T492
Test name
Test status
Simulation time 109578562 ps
CPU time 1.1 seconds
Started Mar 17 03:04:04 PM PDT 24
Finished Mar 17 03:04:05 PM PDT 24
Peak memory 200876 kb
Host smart-3793a78b-043e-41ec-972a-1d3f377894cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531611122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2531611122
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2395861129
Short name T388
Test name
Test status
Simulation time 229402636 ps
CPU time 1.52 seconds
Started Mar 17 03:03:59 PM PDT 24
Finished Mar 17 03:04:02 PM PDT 24
Peak memory 201008 kb
Host smart-7d8d87ac-d4c2-41f9-a0a4-ff9066455411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395861129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2395861129
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.860637198
Short name T65
Test name
Test status
Simulation time 5203606050 ps
CPU time 18.94 seconds
Started Mar 17 03:04:10 PM PDT 24
Finished Mar 17 03:04:29 PM PDT 24
Peak memory 201196 kb
Host smart-95c328b4-e863-44a1-b6fe-489926793487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860637198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.860637198
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3887731168
Short name T246
Test name
Test status
Simulation time 106029802 ps
CPU time 1.42 seconds
Started Mar 17 03:04:01 PM PDT 24
Finished Mar 17 03:04:03 PM PDT 24
Peak memory 200992 kb
Host smart-c5ccfc86-710b-4809-99b1-2ad503dd7b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887731168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3887731168
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2700961056
Short name T505
Test name
Test status
Simulation time 115656765 ps
CPU time 1.01 seconds
Started Mar 17 03:04:00 PM PDT 24
Finished Mar 17 03:04:02 PM PDT 24
Peak memory 200868 kb
Host smart-38ef37d6-ef16-4e3f-98de-10c010ddc8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700961056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2700961056
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2557150609
Short name T463
Test name
Test status
Simulation time 90874546 ps
CPU time 0.88 seconds
Started Mar 17 03:05:15 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 200720 kb
Host smart-06996dde-e46c-4478-816b-ca9dc9e90ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557150609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2557150609
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2967258179
Short name T34
Test name
Test status
Simulation time 1229543072 ps
CPU time 5.59 seconds
Started Mar 17 03:05:19 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 230408 kb
Host smart-a998f86c-fbb7-41eb-9d13-ef6473dba5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967258179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2967258179
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3349394388
Short name T483
Test name
Test status
Simulation time 244650535 ps
CPU time 1.09 seconds
Started Mar 17 03:05:15 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 218156 kb
Host smart-0c3a53e4-4cd9-4472-8b36-e116562666b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349394388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3349394388
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.441591471
Short name T461
Test name
Test status
Simulation time 87828849 ps
CPU time 0.97 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:26 PM PDT 24
Peak memory 200708 kb
Host smart-5290842f-82b5-4a82-a931-72c4a033e951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441591471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.441591471
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1197632992
Short name T240
Test name
Test status
Simulation time 840003959 ps
CPU time 3.98 seconds
Started Mar 17 03:05:17 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 201040 kb
Host smart-fc72239f-9e7e-4bbe-ac0c-ccfeffb58f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197632992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1197632992
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.516734051
Short name T521
Test name
Test status
Simulation time 154899696 ps
CPU time 1.22 seconds
Started Mar 17 03:05:19 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 200916 kb
Host smart-91ed68b3-ae39-4541-b49f-3370cf13f2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516734051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.516734051
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3523308844
Short name T513
Test name
Test status
Simulation time 188078375 ps
CPU time 1.39 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:20 PM PDT 24
Peak memory 201004 kb
Host smart-8b2b9956-cbdf-4b0f-aebb-14303bd680fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523308844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3523308844
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3344018567
Short name T260
Test name
Test status
Simulation time 1296418473 ps
CPU time 5.78 seconds
Started Mar 17 03:05:15 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 201056 kb
Host smart-77c1cbe7-e48a-497f-9e6f-76a99a66bc56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344018567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3344018567
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3694695794
Short name T413
Test name
Test status
Simulation time 338622489 ps
CPU time 2.21 seconds
Started Mar 17 03:05:15 PM PDT 24
Finished Mar 17 03:05:17 PM PDT 24
Peak memory 200856 kb
Host smart-3f0c39db-af08-452b-b64b-e6e499489a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694695794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3694695794
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2437811848
Short name T471
Test name
Test status
Simulation time 119274477 ps
CPU time 1.16 seconds
Started Mar 17 03:05:17 PM PDT 24
Finished Mar 17 03:05:19 PM PDT 24
Peak memory 200892 kb
Host smart-28bec131-dd8c-4fed-9dac-99342c1d1755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437811848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2437811848
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.745679179
Short name T195
Test name
Test status
Simulation time 93273412 ps
CPU time 0.96 seconds
Started Mar 17 03:05:15 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 200808 kb
Host smart-ac00de5c-3b58-4f1a-8a90-388a3a1a1518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745679179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.745679179
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2567365137
Short name T120
Test name
Test status
Simulation time 243694038 ps
CPU time 1.07 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 218180 kb
Host smart-e9e0e3d8-cc68-4809-b335-9b42f92d5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567365137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2567365137
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.505875598
Short name T18
Test name
Test status
Simulation time 192621494 ps
CPU time 0.89 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:19 PM PDT 24
Peak memory 200768 kb
Host smart-a475461b-3a38-4a88-ab93-2a4bc0c41855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505875598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.505875598
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.745722883
Short name T116
Test name
Test status
Simulation time 1936132353 ps
CPU time 7.19 seconds
Started Mar 17 03:05:15 PM PDT 24
Finished Mar 17 03:05:22 PM PDT 24
Peak memory 201040 kb
Host smart-30e1edb8-e06f-421e-968a-e296fe364be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745722883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.745722883
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2065316800
Short name T184
Test name
Test status
Simulation time 148149897 ps
CPU time 1.18 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:20 PM PDT 24
Peak memory 200900 kb
Host smart-41217438-67f9-4822-8769-673c599fbb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065316800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2065316800
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2715432789
Short name T158
Test name
Test status
Simulation time 121740406 ps
CPU time 1.2 seconds
Started Mar 17 03:05:16 PM PDT 24
Finished Mar 17 03:05:17 PM PDT 24
Peak memory 201128 kb
Host smart-b39aa5f7-0cde-431f-80a5-1199c85abdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715432789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2715432789
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1851833237
Short name T434
Test name
Test status
Simulation time 7684835616 ps
CPU time 26.23 seconds
Started Mar 17 03:05:17 PM PDT 24
Finished Mar 17 03:05:43 PM PDT 24
Peak memory 201188 kb
Host smart-cfb3fd8d-5b34-4a08-8f53-6d8f51cbb106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851833237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1851833237
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.43663011
Short name T486
Test name
Test status
Simulation time 374530290 ps
CPU time 2.17 seconds
Started Mar 17 03:05:17 PM PDT 24
Finished Mar 17 03:05:19 PM PDT 24
Peak memory 209168 kb
Host smart-6b947d7c-da25-4fa0-aaca-5a3c8f8c878b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43663011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.43663011
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2898313865
Short name T526
Test name
Test status
Simulation time 164039685 ps
CPU time 1.21 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:20 PM PDT 24
Peak memory 200852 kb
Host smart-381ec25f-3c69-480c-bc97-3f504355bc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898313865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2898313865
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1513211330
Short name T417
Test name
Test status
Simulation time 61316220 ps
CPU time 0.77 seconds
Started Mar 17 03:05:16 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 200752 kb
Host smart-c8c4c154-e9b4-4b75-b88a-55ed63f35b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513211330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1513211330
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3684118050
Short name T367
Test name
Test status
Simulation time 2348003221 ps
CPU time 8.11 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:33 PM PDT 24
Peak memory 222804 kb
Host smart-49859235-1584-4b4a-9714-099fdd86b39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684118050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3684118050
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.752450880
Short name T443
Test name
Test status
Simulation time 243617850 ps
CPU time 1.06 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:15 PM PDT 24
Peak memory 218128 kb
Host smart-cd6c991c-c3e4-4847-bcf5-074113e963d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752450880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.752450880
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2392998323
Short name T303
Test name
Test status
Simulation time 95490763 ps
CPU time 0.75 seconds
Started Mar 17 03:05:16 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 200716 kb
Host smart-88dd05fc-00a0-41b1-b94d-0cef1ff93a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392998323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2392998323
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1471641548
Short name T45
Test name
Test status
Simulation time 2051798174 ps
CPU time 7.07 seconds
Started Mar 17 03:05:17 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 201072 kb
Host smart-8a1bfcd2-8c55-46c3-97ae-e259bf895269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471641548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1471641548
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2589945406
Short name T515
Test name
Test status
Simulation time 96415730 ps
CPU time 1.04 seconds
Started Mar 17 03:05:15 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 200880 kb
Host smart-8209b9ce-39f6-4dd4-856b-e456277e177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589945406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2589945406
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3106940753
Short name T280
Test name
Test status
Simulation time 122654453 ps
CPU time 1.19 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:20 PM PDT 24
Peak memory 201020 kb
Host smart-28cae9e1-3d17-4f4d-a1e1-b05e82eb2db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106940753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3106940753
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.215120355
Short name T204
Test name
Test status
Simulation time 7839220356 ps
CPU time 32.43 seconds
Started Mar 17 03:05:17 PM PDT 24
Finished Mar 17 03:05:49 PM PDT 24
Peak memory 209428 kb
Host smart-d4e88f81-28eb-4896-bbbd-d88f068fdec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215120355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.215120355
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2731220167
Short name T182
Test name
Test status
Simulation time 124280820 ps
CPU time 1.54 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:20 PM PDT 24
Peak memory 200944 kb
Host smart-f930ecfa-75b9-4094-b554-64abbf9405f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731220167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2731220167
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.173802742
Short name T387
Test name
Test status
Simulation time 241665971 ps
CPU time 1.36 seconds
Started Mar 17 03:05:17 PM PDT 24
Finished Mar 17 03:05:18 PM PDT 24
Peak memory 201100 kb
Host smart-0caf0651-7509-4e48-92d3-a1699f912f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173802742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.173802742
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3337032471
Short name T419
Test name
Test status
Simulation time 72456635 ps
CPU time 0.78 seconds
Started Mar 17 03:05:16 PM PDT 24
Finished Mar 17 03:05:17 PM PDT 24
Peak memory 200764 kb
Host smart-d3befc51-806f-4462-88a7-e46f009dff82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337032471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3337032471
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1023803048
Short name T324
Test name
Test status
Simulation time 1226667722 ps
CPU time 5.54 seconds
Started Mar 17 03:05:17 PM PDT 24
Finished Mar 17 03:05:24 PM PDT 24
Peak memory 218644 kb
Host smart-5e06d1c6-af0f-4c93-a4ca-8cd4da05979b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023803048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1023803048
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2365009231
Short name T405
Test name
Test status
Simulation time 244940414 ps
CPU time 1.04 seconds
Started Mar 17 03:05:16 PM PDT 24
Finished Mar 17 03:05:18 PM PDT 24
Peak memory 218264 kb
Host smart-286c3dc9-ddca-4223-a65a-d872335edede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365009231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2365009231
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.177326863
Short name T19
Test name
Test status
Simulation time 124612460 ps
CPU time 0.8 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:19 PM PDT 24
Peak memory 200748 kb
Host smart-b7293117-59fb-451f-b484-765ad2e57f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177326863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.177326863
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2221208963
Short name T237
Test name
Test status
Simulation time 1503085533 ps
CPU time 6.17 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 201076 kb
Host smart-33572aa0-fd24-4fa2-948c-66b1b4676c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221208963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2221208963
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.464675090
Short name T318
Test name
Test status
Simulation time 141399806 ps
CPU time 1.14 seconds
Started Mar 17 03:05:25 PM PDT 24
Finished Mar 17 03:05:27 PM PDT 24
Peak memory 200920 kb
Host smart-a2f0132b-87b8-41f1-911e-67bfea46537c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464675090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.464675090
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3356893935
Short name T385
Test name
Test status
Simulation time 251663651 ps
CPU time 1.59 seconds
Started Mar 17 03:05:16 PM PDT 24
Finished Mar 17 03:05:18 PM PDT 24
Peak memory 201032 kb
Host smart-b597a61f-f0cb-43e1-8bdc-d67e428774a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356893935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3356893935
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3801385071
Short name T411
Test name
Test status
Simulation time 8246004831 ps
CPU time 31.19 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:50 PM PDT 24
Peak memory 209424 kb
Host smart-08b0606d-dcd0-4214-a710-4176f1a0ab4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801385071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3801385071
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1402819280
Short name T495
Test name
Test status
Simulation time 143200416 ps
CPU time 1.73 seconds
Started Mar 17 03:05:14 PM PDT 24
Finished Mar 17 03:05:17 PM PDT 24
Peak memory 209148 kb
Host smart-b5fae590-ee09-4494-8b78-0724189bfc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402819280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1402819280
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3004233949
Short name T545
Test name
Test status
Simulation time 113991311 ps
CPU time 0.99 seconds
Started Mar 17 03:05:17 PM PDT 24
Finished Mar 17 03:05:18 PM PDT 24
Peak memory 200884 kb
Host smart-9a59a1b9-d1a3-4b46-8722-ee7d992751c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004233949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3004233949
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1904908144
Short name T428
Test name
Test status
Simulation time 88490891 ps
CPU time 0.97 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:26 PM PDT 24
Peak memory 200724 kb
Host smart-1c369f04-a726-4765-ab94-1be546199f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904908144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1904908144
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3262072249
Short name T41
Test name
Test status
Simulation time 1897081411 ps
CPU time 6.85 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:32 PM PDT 24
Peak memory 218604 kb
Host smart-2364ba05-7987-4901-9cc0-fc7e34a9b56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262072249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3262072249
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3723542025
Short name T361
Test name
Test status
Simulation time 244368369 ps
CPU time 1.05 seconds
Started Mar 17 03:05:19 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 218260 kb
Host smart-1a79e7f5-f0ae-4ba5-802b-0d8f853ff293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723542025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3723542025
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.488034564
Short name T316
Test name
Test status
Simulation time 114161732 ps
CPU time 0.78 seconds
Started Mar 17 03:05:27 PM PDT 24
Finished Mar 17 03:05:28 PM PDT 24
Peak memory 200780 kb
Host smart-8c4a88de-a304-4cbd-a2c7-5a8533d4dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488034564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.488034564
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.552050909
Short name T489
Test name
Test status
Simulation time 1622496135 ps
CPU time 6.15 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:24 PM PDT 24
Peak memory 201076 kb
Host smart-534bbe80-178e-4bb1-99ea-6595ebf64eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552050909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.552050909
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4170368054
Short name T511
Test name
Test status
Simulation time 98328380 ps
CPU time 1 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:26 PM PDT 24
Peak memory 200920 kb
Host smart-44440936-1a78-4e90-93c3-9350d02ebacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170368054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.4170368054
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3035977505
Short name T325
Test name
Test status
Simulation time 107688520 ps
CPU time 1.19 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:19 PM PDT 24
Peak memory 201004 kb
Host smart-ac4047fb-0be3-45c1-9308-67663a8e31ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035977505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3035977505
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.546814255
Short name T264
Test name
Test status
Simulation time 3732235951 ps
CPU time 17.08 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:35 PM PDT 24
Peak memory 201196 kb
Host smart-44a9d9e4-60c3-4122-b751-f0aa25911754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546814255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.546814255
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2843241031
Short name T228
Test name
Test status
Simulation time 365946633 ps
CPU time 2.36 seconds
Started Mar 17 03:05:18 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 200908 kb
Host smart-afb57245-c139-43d3-b27e-d5702f04a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843241031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2843241031
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.622548775
Short name T464
Test name
Test status
Simulation time 77695857 ps
CPU time 0.84 seconds
Started Mar 17 03:05:19 PM PDT 24
Finished Mar 17 03:05:20 PM PDT 24
Peak memory 200860 kb
Host smart-0e0e0d9b-8c57-48da-996d-12540103cbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622548775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.622548775
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3309228951
Short name T392
Test name
Test status
Simulation time 65901303 ps
CPU time 0.76 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:26 PM PDT 24
Peak memory 200760 kb
Host smart-4025bb34-cbde-42c8-b9bc-2acd88d20e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309228951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3309228951
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3759617065
Short name T457
Test name
Test status
Simulation time 1226090412 ps
CPU time 5.89 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:30 PM PDT 24
Peak memory 222140 kb
Host smart-5c34c286-1cb9-4ed2-87e4-afb7a3b1ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759617065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3759617065
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1398539322
Short name T468
Test name
Test status
Simulation time 244955499 ps
CPU time 1.12 seconds
Started Mar 17 03:05:25 PM PDT 24
Finished Mar 17 03:05:26 PM PDT 24
Peak memory 218164 kb
Host smart-ba3addbc-96d7-4c0f-8311-633ef39b4bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398539322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1398539322
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1305589455
Short name T213
Test name
Test status
Simulation time 75980004 ps
CPU time 0.72 seconds
Started Mar 17 03:05:19 PM PDT 24
Finished Mar 17 03:05:20 PM PDT 24
Peak memory 200764 kb
Host smart-5231e2bc-76eb-4abb-8a34-bb7c157041d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305589455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1305589455
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1497168314
Short name T487
Test name
Test status
Simulation time 881755920 ps
CPU time 4.84 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:29 PM PDT 24
Peak memory 201248 kb
Host smart-b7acf883-d8cb-443b-a61b-2d6aef7839a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497168314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1497168314
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3323594293
Short name T196
Test name
Test status
Simulation time 172315924 ps
CPU time 1.28 seconds
Started Mar 17 03:05:23 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 200896 kb
Host smart-594bff39-405f-415b-8396-d54a61c95127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323594293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3323594293
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2130061473
Short name T66
Test name
Test status
Simulation time 252359672 ps
CPU time 1.53 seconds
Started Mar 17 03:05:19 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 201104 kb
Host smart-507da784-0a45-4052-a5db-64b50140d89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130061473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2130061473
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.631290617
Short name T412
Test name
Test status
Simulation time 4969996163 ps
CPU time 17.95 seconds
Started Mar 17 03:05:21 PM PDT 24
Finished Mar 17 03:05:40 PM PDT 24
Peak memory 201220 kb
Host smart-f1a25b07-49e4-4cd7-9299-b19371b880bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631290617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.631290617
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2284352168
Short name T292
Test name
Test status
Simulation time 344831403 ps
CPU time 2.06 seconds
Started Mar 17 03:05:21 PM PDT 24
Finished Mar 17 03:05:23 PM PDT 24
Peak memory 200896 kb
Host smart-d015c36c-3344-4bc3-af04-f6ccdc350ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284352168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2284352168
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.79235036
Short name T148
Test name
Test status
Simulation time 142040861 ps
CPU time 1.16 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 200920 kb
Host smart-ca212116-6f2e-4417-b25a-adf21e72a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79235036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.79235036
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3816611950
Short name T137
Test name
Test status
Simulation time 56729636 ps
CPU time 0.74 seconds
Started Mar 17 03:05:20 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 200756 kb
Host smart-ad0b73dd-b973-4b43-971f-534f42a234db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816611950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3816611950
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.726944978
Short name T435
Test name
Test status
Simulation time 1898622536 ps
CPU time 7.3 seconds
Started Mar 17 03:05:20 PM PDT 24
Finished Mar 17 03:05:28 PM PDT 24
Peak memory 218528 kb
Host smart-a58f2c30-c935-4d1b-99a2-395c06ea1cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726944978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.726944978
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1331242416
Short name T366
Test name
Test status
Simulation time 244572889 ps
CPU time 1.14 seconds
Started Mar 17 03:05:26 PM PDT 24
Finished Mar 17 03:05:27 PM PDT 24
Peak memory 218172 kb
Host smart-ddab58a9-5732-47bd-8377-740614c0e2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331242416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1331242416
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1664633843
Short name T290
Test name
Test status
Simulation time 197067537 ps
CPU time 0.91 seconds
Started Mar 17 03:05:26 PM PDT 24
Finished Mar 17 03:05:27 PM PDT 24
Peak memory 200792 kb
Host smart-7a61d28f-0330-48fe-a951-eaa4a3b8f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664633843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1664633843
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1852261590
Short name T243
Test name
Test status
Simulation time 1410659595 ps
CPU time 5.82 seconds
Started Mar 17 03:05:25 PM PDT 24
Finished Mar 17 03:05:31 PM PDT 24
Peak memory 201092 kb
Host smart-8bb22a58-b296-4a9d-96a3-bd3ea9472c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852261590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1852261590
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2334731400
Short name T287
Test name
Test status
Simulation time 146496640 ps
CPU time 1.14 seconds
Started Mar 17 03:05:23 PM PDT 24
Finished Mar 17 03:05:24 PM PDT 24
Peak memory 201064 kb
Host smart-eb36ed28-4269-4b1d-8bcd-321119495133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334731400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2334731400
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2421880576
Short name T241
Test name
Test status
Simulation time 196371209 ps
CPU time 1.37 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:26 PM PDT 24
Peak memory 201088 kb
Host smart-cd08e5cb-7bcb-4beb-b88c-7b72a82877a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421880576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2421880576
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3901977610
Short name T12
Test name
Test status
Simulation time 3823896813 ps
CPU time 17.48 seconds
Started Mar 17 03:05:21 PM PDT 24
Finished Mar 17 03:05:38 PM PDT 24
Peak memory 209440 kb
Host smart-a0cc6bb2-d982-4893-bcb5-6cd224ae1204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901977610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3901977610
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1334701172
Short name T219
Test name
Test status
Simulation time 369234762 ps
CPU time 2.33 seconds
Started Mar 17 03:05:22 PM PDT 24
Finished Mar 17 03:05:24 PM PDT 24
Peak memory 200956 kb
Host smart-4f678863-4244-40a9-a62b-c3af21c7afb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334701172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1334701172
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1984629939
Short name T152
Test name
Test status
Simulation time 141113738 ps
CPU time 1.29 seconds
Started Mar 17 03:05:21 PM PDT 24
Finished Mar 17 03:05:22 PM PDT 24
Peak memory 201060 kb
Host smart-2cfbda70-8c21-4ebb-9f3d-9c8ce40608eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984629939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1984629939
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3037683714
Short name T497
Test name
Test status
Simulation time 87744900 ps
CPU time 0.86 seconds
Started Mar 17 03:05:21 PM PDT 24
Finished Mar 17 03:05:23 PM PDT 24
Peak memory 200776 kb
Host smart-495e92a6-6bb4-480f-88ec-0db67619cc0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037683714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3037683714
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4004317878
Short name T30
Test name
Test status
Simulation time 1223240439 ps
CPU time 5.41 seconds
Started Mar 17 03:05:22 PM PDT 24
Finished Mar 17 03:05:28 PM PDT 24
Peak memory 218008 kb
Host smart-aaaac596-8e7f-41bc-a823-43696fa81478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004317878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4004317878
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1671831190
Short name T222
Test name
Test status
Simulation time 243665184 ps
CPU time 1.06 seconds
Started Mar 17 03:05:26 PM PDT 24
Finished Mar 17 03:05:27 PM PDT 24
Peak memory 218340 kb
Host smart-ffbcb882-3b7a-4315-a19b-1112483b6e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671831190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1671831190
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.230067976
Short name T22
Test name
Test status
Simulation time 102247825 ps
CPU time 0.81 seconds
Started Mar 17 03:05:22 PM PDT 24
Finished Mar 17 03:05:23 PM PDT 24
Peak memory 200720 kb
Host smart-797d080d-1de2-4757-870a-4b268bd2d698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230067976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.230067976
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.973062326
Short name T168
Test name
Test status
Simulation time 818995935 ps
CPU time 4.41 seconds
Started Mar 17 03:05:20 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 201108 kb
Host smart-3b4dc376-ada0-4d39-b3cd-8ae488ef8839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973062326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.973062326
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2635188039
Short name T174
Test name
Test status
Simulation time 156490451 ps
CPU time 1.13 seconds
Started Mar 17 03:05:20 PM PDT 24
Finished Mar 17 03:05:21 PM PDT 24
Peak memory 200884 kb
Host smart-fd0ac8c1-71c6-4fe6-a76b-bfbd075b1bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635188039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2635188039
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3583764660
Short name T135
Test name
Test status
Simulation time 197748345 ps
CPU time 1.34 seconds
Started Mar 17 03:05:21 PM PDT 24
Finished Mar 17 03:05:22 PM PDT 24
Peak memory 201076 kb
Host smart-ad7aba22-8b27-458e-a7d3-e819e244ac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583764660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3583764660
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2116805888
Short name T75
Test name
Test status
Simulation time 2393088024 ps
CPU time 10.38 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:35 PM PDT 24
Peak memory 209396 kb
Host smart-4bcef62c-4621-448a-ab9a-3895721aacbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116805888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2116805888
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2666019918
Short name T527
Test name
Test status
Simulation time 122121963 ps
CPU time 1.45 seconds
Started Mar 17 03:05:22 PM PDT 24
Finished Mar 17 03:05:24 PM PDT 24
Peak memory 200940 kb
Host smart-117ee736-fbbd-4861-a0ef-5729fdaa3f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666019918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2666019918
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1278754488
Short name T467
Test name
Test status
Simulation time 236121975 ps
CPU time 1.56 seconds
Started Mar 17 03:05:20 PM PDT 24
Finished Mar 17 03:05:22 PM PDT 24
Peak memory 201036 kb
Host smart-dcb8c401-d467-41ca-bb8b-9eabacf626f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278754488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1278754488
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.645869608
Short name T451
Test name
Test status
Simulation time 60916094 ps
CPU time 0.74 seconds
Started Mar 17 03:05:28 PM PDT 24
Finished Mar 17 03:05:29 PM PDT 24
Peak memory 200728 kb
Host smart-7280fac7-f6b1-4900-a8d7-cb7f0c595386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645869608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.645869608
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3815565120
Short name T32
Test name
Test status
Simulation time 1889748732 ps
CPU time 7.03 seconds
Started Mar 17 03:05:28 PM PDT 24
Finished Mar 17 03:05:35 PM PDT 24
Peak memory 218044 kb
Host smart-0012a567-872c-4c93-9084-8946ddb1f9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815565120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3815565120
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3681305186
Short name T175
Test name
Test status
Simulation time 244829591 ps
CPU time 1.07 seconds
Started Mar 17 03:05:29 PM PDT 24
Finished Mar 17 03:05:30 PM PDT 24
Peak memory 218300 kb
Host smart-f8fbd81c-2c92-446b-8119-096e5c5fb5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681305186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3681305186
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3078785466
Short name T313
Test name
Test status
Simulation time 156706677 ps
CPU time 0.89 seconds
Started Mar 17 03:05:26 PM PDT 24
Finished Mar 17 03:05:28 PM PDT 24
Peak memory 200752 kb
Host smart-6581170e-143e-4113-8736-d925819f71ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078785466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3078785466
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2539993155
Short name T216
Test name
Test status
Simulation time 1676298442 ps
CPU time 6.68 seconds
Started Mar 17 03:05:26 PM PDT 24
Finished Mar 17 03:05:33 PM PDT 24
Peak memory 201076 kb
Host smart-bb53dd51-d13f-46b2-991f-50e8a2f426a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539993155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2539993155
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2542120737
Short name T523
Test name
Test status
Simulation time 155701795 ps
CPU time 1.13 seconds
Started Mar 17 03:05:28 PM PDT 24
Finished Mar 17 03:05:30 PM PDT 24
Peak memory 200856 kb
Host smart-e8920d09-0390-4e77-80ff-5d0cded94098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542120737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2542120737
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1353904102
Short name T291
Test name
Test status
Simulation time 201285352 ps
CPU time 1.54 seconds
Started Mar 17 03:05:22 PM PDT 24
Finished Mar 17 03:05:23 PM PDT 24
Peak memory 201104 kb
Host smart-8b837f33-e9ca-415d-975b-94436402ac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353904102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1353904102
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.34682146
Short name T543
Test name
Test status
Simulation time 3711191916 ps
CPU time 17.27 seconds
Started Mar 17 03:05:30 PM PDT 24
Finished Mar 17 03:05:47 PM PDT 24
Peak memory 201204 kb
Host smart-0255d79d-aaaa-445c-a050-120763616d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34682146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.34682146
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3853760222
Short name T226
Test name
Test status
Simulation time 131191504 ps
CPU time 1.76 seconds
Started Mar 17 03:05:28 PM PDT 24
Finished Mar 17 03:05:30 PM PDT 24
Peak memory 209156 kb
Host smart-4f16d6a1-d755-4c37-9bdd-1cad83c26abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853760222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3853760222
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3008080580
Short name T373
Test name
Test status
Simulation time 150914311 ps
CPU time 1.23 seconds
Started Mar 17 03:05:35 PM PDT 24
Finished Mar 17 03:05:37 PM PDT 24
Peak memory 200916 kb
Host smart-883b926e-1fa4-49ef-aefc-9faa333436ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008080580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3008080580
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1977867892
Short name T301
Test name
Test status
Simulation time 58237354 ps
CPU time 0.76 seconds
Started Mar 17 03:05:26 PM PDT 24
Finished Mar 17 03:05:27 PM PDT 24
Peak memory 200732 kb
Host smart-755a585e-aa69-48e8-862e-e69c277d0479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977867892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1977867892
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1007077010
Short name T510
Test name
Test status
Simulation time 2348546314 ps
CPU time 8.49 seconds
Started Mar 17 03:05:26 PM PDT 24
Finished Mar 17 03:05:35 PM PDT 24
Peak memory 218676 kb
Host smart-01fc089e-7c96-4a5c-9675-55c49767595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007077010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1007077010
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.4112176299
Short name T530
Test name
Test status
Simulation time 243749882 ps
CPU time 1.09 seconds
Started Mar 17 03:05:28 PM PDT 24
Finished Mar 17 03:05:30 PM PDT 24
Peak memory 218324 kb
Host smart-1d40933b-7aea-49c9-8b86-3059c1051397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112176299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.4112176299
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3431921741
Short name T17
Test name
Test status
Simulation time 192156182 ps
CPU time 0.87 seconds
Started Mar 17 03:05:34 PM PDT 24
Finished Mar 17 03:05:36 PM PDT 24
Peak memory 200780 kb
Host smart-3f0760af-9f34-4a74-b03b-619d2136884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431921741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3431921741
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.483847812
Short name T408
Test name
Test status
Simulation time 900363831 ps
CPU time 4.74 seconds
Started Mar 17 03:05:26 PM PDT 24
Finished Mar 17 03:05:31 PM PDT 24
Peak memory 201060 kb
Host smart-9a504532-23bf-4dcc-b0bf-3718daeff3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483847812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.483847812
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3035259462
Short name T390
Test name
Test status
Simulation time 174078817 ps
CPU time 1.25 seconds
Started Mar 17 03:05:27 PM PDT 24
Finished Mar 17 03:05:29 PM PDT 24
Peak memory 200812 kb
Host smart-e8c78551-ba03-40eb-acbb-2f963bb244c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035259462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3035259462
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2649755011
Short name T267
Test name
Test status
Simulation time 123152947 ps
CPU time 1.18 seconds
Started Mar 17 03:05:24 PM PDT 24
Finished Mar 17 03:05:26 PM PDT 24
Peak memory 201020 kb
Host smart-3d36f0df-11ff-409a-b1a6-3d7eb2b23a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649755011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2649755011
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.130788770
Short name T326
Test name
Test status
Simulation time 6224037010 ps
CPU time 20.8 seconds
Started Mar 17 03:05:31 PM PDT 24
Finished Mar 17 03:05:52 PM PDT 24
Peak memory 201208 kb
Host smart-6addb856-6562-4a00-876b-3caf28070451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130788770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.130788770
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.167796742
Short name T374
Test name
Test status
Simulation time 460986174 ps
CPU time 2.73 seconds
Started Mar 17 03:05:27 PM PDT 24
Finished Mar 17 03:05:30 PM PDT 24
Peak memory 200976 kb
Host smart-847b0de5-30e9-4358-b6e6-e7e546bdc998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167796742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.167796742
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1999820757
Short name T145
Test name
Test status
Simulation time 182330380 ps
CPU time 1.19 seconds
Started Mar 17 03:05:26 PM PDT 24
Finished Mar 17 03:05:27 PM PDT 24
Peak memory 200848 kb
Host smart-6bb54445-918b-48a0-ac31-6e0c486e4682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999820757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1999820757
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3108780291
Short name T242
Test name
Test status
Simulation time 72078502 ps
CPU time 0.77 seconds
Started Mar 17 03:04:04 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 200776 kb
Host smart-408628ad-c246-4190-9192-fd9c4f19a2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108780291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3108780291
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.914552235
Short name T47
Test name
Test status
Simulation time 2154084658 ps
CPU time 7.74 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:14 PM PDT 24
Peak memory 222336 kb
Host smart-11b6044a-2072-4d31-b4f0-f73d383fedd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914552235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.914552235
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.723905359
Short name T183
Test name
Test status
Simulation time 244584148 ps
CPU time 1.08 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 218236 kb
Host smart-1dfaf951-15b6-413a-8cb3-c245a7b1175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723905359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.723905359
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.4094402369
Short name T188
Test name
Test status
Simulation time 162571087 ps
CPU time 0.86 seconds
Started Mar 17 03:04:07 PM PDT 24
Finished Mar 17 03:04:09 PM PDT 24
Peak memory 200696 kb
Host smart-1607361e-ed4b-4e0b-a941-c26ed0dea612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094402369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.4094402369
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1316872503
Short name T439
Test name
Test status
Simulation time 1692330298 ps
CPU time 5.94 seconds
Started Mar 17 03:04:05 PM PDT 24
Finished Mar 17 03:04:11 PM PDT 24
Peak memory 201040 kb
Host smart-305bbcef-37ec-4974-b244-eb5572eb3dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316872503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1316872503
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1494410913
Short name T493
Test name
Test status
Simulation time 145993623 ps
CPU time 1.18 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 200916 kb
Host smart-f2aa16ea-51e4-4632-8041-b9616d365d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494410913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1494410913
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2986430175
Short name T355
Test name
Test status
Simulation time 197331249 ps
CPU time 1.42 seconds
Started Mar 17 03:04:05 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 201124 kb
Host smart-eb200675-8c05-48fa-ba45-d9497faff582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986430175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2986430175
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1040097531
Short name T484
Test name
Test status
Simulation time 2823933796 ps
CPU time 12.5 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:19 PM PDT 24
Peak memory 210640 kb
Host smart-739ecab4-d038-41ac-be55-eab0a5e66a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040097531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1040097531
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2676868963
Short name T24
Test name
Test status
Simulation time 112608412 ps
CPU time 1.46 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 200956 kb
Host smart-89cfc853-7cf4-43b4-bce1-d7382880f1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676868963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2676868963
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2489304872
Short name T332
Test name
Test status
Simulation time 147831934 ps
CPU time 1.28 seconds
Started Mar 17 03:04:07 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 201084 kb
Host smart-54f8b2dc-bb12-41cf-8dcb-848277f3b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489304872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2489304872
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3248228045
Short name T507
Test name
Test status
Simulation time 90857761 ps
CPU time 0.85 seconds
Started Mar 17 03:04:07 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 200768 kb
Host smart-b8ce8aa9-b0f3-4003-98ef-2a1febbf77db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248228045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3248228045
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2731016527
Short name T516
Test name
Test status
Simulation time 2348802209 ps
CPU time 8.59 seconds
Started Mar 17 03:04:07 PM PDT 24
Finished Mar 17 03:04:16 PM PDT 24
Peak memory 222944 kb
Host smart-a775bf4c-1e75-406f-b1d7-93e7458952f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731016527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2731016527
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.616164645
Short name T218
Test name
Test status
Simulation time 244025480 ps
CPU time 1.07 seconds
Started Mar 17 03:04:11 PM PDT 24
Finished Mar 17 03:04:12 PM PDT 24
Peak memory 218256 kb
Host smart-f1936a8d-55ba-4679-afcb-34e9966dae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616164645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.616164645
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2216780689
Short name T524
Test name
Test status
Simulation time 145414250 ps
CPU time 0.84 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 200744 kb
Host smart-fe5f6246-391a-471f-a4e3-9f1ecd127281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216780689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2216780689
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2599935016
Short name T68
Test name
Test status
Simulation time 1294323631 ps
CPU time 5.11 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:11 PM PDT 24
Peak memory 201032 kb
Host smart-fbdafe5d-5e7a-4f4f-86f5-eb6de81635bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599935016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2599935016
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.4171927676
Short name T67
Test name
Test status
Simulation time 154607727 ps
CPU time 1.13 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 200912 kb
Host smart-acd7d395-1c30-45d4-93f7-eb02c159999f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171927676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.4171927676
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.675012225
Short name T212
Test name
Test status
Simulation time 195199431 ps
CPU time 1.41 seconds
Started Mar 17 03:04:07 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 201060 kb
Host smart-86e4dd9c-b4a4-47f6-a897-b82947977d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675012225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.675012225
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2069241287
Short name T262
Test name
Test status
Simulation time 521778646 ps
CPU time 2.49 seconds
Started Mar 17 03:04:05 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 201032 kb
Host smart-24026f67-4b96-4f67-8ad8-a0f0c8d736b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069241287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2069241287
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2758534539
Short name T338
Test name
Test status
Simulation time 293610084 ps
CPU time 2.13 seconds
Started Mar 17 03:04:08 PM PDT 24
Finished Mar 17 03:04:11 PM PDT 24
Peak memory 200904 kb
Host smart-981a14a4-dcbd-404b-a8b6-5bd68cc640dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758534539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2758534539
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.171238105
Short name T322
Test name
Test status
Simulation time 166939939 ps
CPU time 1.17 seconds
Started Mar 17 03:04:05 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 200888 kb
Host smart-a7685d76-4c7e-4053-b574-6a306333d6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171238105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.171238105
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1160917023
Short name T440
Test name
Test status
Simulation time 71287408 ps
CPU time 0.76 seconds
Started Mar 17 03:04:07 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 200812 kb
Host smart-e8279466-6eaa-4403-9670-b2dac4713a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160917023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1160917023
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1023898527
Short name T418
Test name
Test status
Simulation time 1226622402 ps
CPU time 6.05 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:12 PM PDT 24
Peak memory 218624 kb
Host smart-ec830fb7-112c-4a4d-819d-8fe28e78549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023898527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1023898527
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1202254964
Short name T531
Test name
Test status
Simulation time 244700153 ps
CPU time 1.08 seconds
Started Mar 17 03:04:07 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 218300 kb
Host smart-746a45ec-6f72-44dc-8b02-672fefdf5963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202254964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1202254964
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1097084077
Short name T328
Test name
Test status
Simulation time 153647127 ps
CPU time 0.9 seconds
Started Mar 17 03:04:05 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 200724 kb
Host smart-78f80699-9b62-4041-9aaa-ecc1a06a9171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097084077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1097084077
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.208735606
Short name T88
Test name
Test status
Simulation time 1894210920 ps
CPU time 6.65 seconds
Started Mar 17 03:04:08 PM PDT 24
Finished Mar 17 03:04:15 PM PDT 24
Peak memory 201088 kb
Host smart-71f98222-3c62-41b9-9a4c-94337dd121dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208735606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.208735606
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.151014969
Short name T289
Test name
Test status
Simulation time 161827621 ps
CPU time 1.19 seconds
Started Mar 17 03:04:07 PM PDT 24
Finished Mar 17 03:04:09 PM PDT 24
Peak memory 200844 kb
Host smart-48595e52-7669-44ed-9d3a-041893ab15df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151014969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.151014969
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2497199665
Short name T76
Test name
Test status
Simulation time 115331014 ps
CPU time 1.24 seconds
Started Mar 17 03:04:08 PM PDT 24
Finished Mar 17 03:04:10 PM PDT 24
Peak memory 201032 kb
Host smart-afb3eca4-433a-4ddb-81d7-c920f9ee5555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497199665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2497199665
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.4118928954
Short name T336
Test name
Test status
Simulation time 7028301257 ps
CPU time 34.15 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:40 PM PDT 24
Peak memory 209564 kb
Host smart-5ae12bef-1d8f-49ba-a746-b28eb415f84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118928954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.4118928954
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.356067620
Short name T217
Test name
Test status
Simulation time 260447569 ps
CPU time 1.92 seconds
Started Mar 17 03:04:06 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 200932 kb
Host smart-d9641bf3-a2c0-4d2c-a75f-eb6d32cd446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356067620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.356067620
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1947773346
Short name T389
Test name
Test status
Simulation time 162900665 ps
CPU time 1.16 seconds
Started Mar 17 03:04:11 PM PDT 24
Finished Mar 17 03:04:12 PM PDT 24
Peak memory 200916 kb
Host smart-e70eea20-a367-493c-936f-a350090379de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947773346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1947773346
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2281475159
Short name T281
Test name
Test status
Simulation time 83451428 ps
CPU time 0.84 seconds
Started Mar 17 03:04:19 PM PDT 24
Finished Mar 17 03:04:19 PM PDT 24
Peak memory 200732 kb
Host smart-52f5d07b-9484-4662-9b4d-e17e7cad980c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281475159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2281475159
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1860496289
Short name T302
Test name
Test status
Simulation time 1226425267 ps
CPU time 6.01 seconds
Started Mar 17 03:04:11 PM PDT 24
Finished Mar 17 03:04:17 PM PDT 24
Peak memory 222644 kb
Host smart-5c41e4e1-fbd3-4888-b0e9-0899f2a42186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860496289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1860496289
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1815429654
Short name T321
Test name
Test status
Simulation time 244791335 ps
CPU time 1.06 seconds
Started Mar 17 03:04:09 PM PDT 24
Finished Mar 17 03:04:10 PM PDT 24
Peak memory 218152 kb
Host smart-e3bea6c8-c777-49f2-bb1e-f0ed25742777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815429654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1815429654
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3090795681
Short name T278
Test name
Test status
Simulation time 183160931 ps
CPU time 0.88 seconds
Started Mar 17 03:04:19 PM PDT 24
Finished Mar 17 03:04:20 PM PDT 24
Peak memory 200756 kb
Host smart-3f9199f5-0d12-4b26-abf7-2dfa24c6ff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090795681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3090795681
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4094071444
Short name T312
Test name
Test status
Simulation time 1636926600 ps
CPU time 6.24 seconds
Started Mar 17 03:04:23 PM PDT 24
Finished Mar 17 03:04:30 PM PDT 24
Peak memory 201088 kb
Host smart-08c13247-ea62-4a13-8a31-86eada0f18a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094071444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4094071444
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2406521311
Short name T425
Test name
Test status
Simulation time 109781345 ps
CPU time 0.99 seconds
Started Mar 17 03:04:10 PM PDT 24
Finished Mar 17 03:04:11 PM PDT 24
Peak memory 200900 kb
Host smart-4613533f-9d9b-4e07-8b76-354d4fdb8a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406521311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2406521311
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3705728848
Short name T535
Test name
Test status
Simulation time 204916525 ps
CPU time 1.45 seconds
Started Mar 17 03:04:19 PM PDT 24
Finished Mar 17 03:04:21 PM PDT 24
Peak memory 200972 kb
Host smart-2c0226a5-2c1e-4b1d-ba4e-4cad8dbf2a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705728848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3705728848
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.852870177
Short name T275
Test name
Test status
Simulation time 14852441121 ps
CPU time 57.03 seconds
Started Mar 17 03:04:19 PM PDT 24
Finished Mar 17 03:05:17 PM PDT 24
Peak memory 201240 kb
Host smart-7930cb77-2df6-4edd-ad25-822f1f8cafbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852870177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.852870177
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3321609173
Short name T310
Test name
Test status
Simulation time 409540032 ps
CPU time 2.33 seconds
Started Mar 17 03:04:13 PM PDT 24
Finished Mar 17 03:04:15 PM PDT 24
Peak memory 200944 kb
Host smart-a7b6b4b9-9aeb-48bb-b152-4ac25167a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321609173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3321609173
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2764584422
Short name T70
Test name
Test status
Simulation time 168075708 ps
CPU time 1.31 seconds
Started Mar 17 03:04:13 PM PDT 24
Finished Mar 17 03:04:14 PM PDT 24
Peak memory 201068 kb
Host smart-9520a943-f45c-409f-be34-84984078efed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764584422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2764584422
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3655451592
Short name T433
Test name
Test status
Simulation time 62112266 ps
CPU time 0.75 seconds
Started Mar 17 03:04:19 PM PDT 24
Finished Mar 17 03:04:20 PM PDT 24
Peak memory 200780 kb
Host smart-5aab391a-e9e9-42fd-8029-8e263abcaddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655451592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3655451592
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2841039363
Short name T279
Test name
Test status
Simulation time 2349137030 ps
CPU time 9.38 seconds
Started Mar 17 03:04:20 PM PDT 24
Finished Mar 17 03:04:30 PM PDT 24
Peak memory 218652 kb
Host smart-becd8e49-9733-4b29-95ed-b04a3c6e1eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841039363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2841039363
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.66810237
Short name T479
Test name
Test status
Simulation time 243615789 ps
CPU time 1.05 seconds
Started Mar 17 03:04:18 PM PDT 24
Finished Mar 17 03:04:19 PM PDT 24
Peak memory 218220 kb
Host smart-b7576a82-2c23-4c80-a33a-4a114f61300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66810237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.66810237
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1854948510
Short name T359
Test name
Test status
Simulation time 177689151 ps
CPU time 0.94 seconds
Started Mar 17 03:04:22 PM PDT 24
Finished Mar 17 03:04:23 PM PDT 24
Peak memory 200696 kb
Host smart-aa1d32bd-b5b4-422d-88d6-ad798b30cd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854948510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1854948510
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2002486454
Short name T268
Test name
Test status
Simulation time 1606249929 ps
CPU time 6.17 seconds
Started Mar 17 03:04:11 PM PDT 24
Finished Mar 17 03:04:17 PM PDT 24
Peak memory 201020 kb
Host smart-61e66be5-a495-4c34-9c1d-02b2a2cfd81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002486454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2002486454
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1749646334
Short name T261
Test name
Test status
Simulation time 148493220 ps
CPU time 1.11 seconds
Started Mar 17 03:04:20 PM PDT 24
Finished Mar 17 03:04:21 PM PDT 24
Peak memory 200916 kb
Host smart-328aab98-db06-405a-945e-6e342966e981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749646334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1749646334
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2577235213
Short name T528
Test name
Test status
Simulation time 199815749 ps
CPU time 1.39 seconds
Started Mar 17 03:04:11 PM PDT 24
Finished Mar 17 03:04:12 PM PDT 24
Peak memory 201016 kb
Host smart-e0878aa7-b017-4263-a238-ac7139ef3342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577235213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2577235213
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1979950335
Short name T73
Test name
Test status
Simulation time 2193884032 ps
CPU time 9.19 seconds
Started Mar 17 03:04:19 PM PDT 24
Finished Mar 17 03:04:28 PM PDT 24
Peak memory 209400 kb
Host smart-c55eb7ef-aba5-4674-a4e9-830383e08ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979950335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1979950335
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1311603287
Short name T383
Test name
Test status
Simulation time 518490828 ps
CPU time 2.62 seconds
Started Mar 17 03:04:20 PM PDT 24
Finished Mar 17 03:04:23 PM PDT 24
Peak memory 200960 kb
Host smart-935a998a-db79-4872-b50f-ef828dfdbe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311603287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1311603287
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2483066800
Short name T164
Test name
Test status
Simulation time 86239475 ps
CPU time 0.91 seconds
Started Mar 17 03:04:09 PM PDT 24
Finished Mar 17 03:04:10 PM PDT 24
Peak memory 200892 kb
Host smart-dba4f9bf-0e17-4342-9979-f504bf0d89fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483066800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2483066800
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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