Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8099

1

T2

23

T8

17

T9

13

auto[1]

10942

1

T2

26

T6

4

T7

8

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5856	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6380	1			T1	1		T2	18		T3	1
reset_info_cp[2]	3031	1			T2	11		T6	1		T7	2
reset_info_cp[4]	3850	1			T2	9		T6	1		T7	2
reset_info_cp[8]	116	1			T10	1		T12	2		T49	1
reset_info_cp[16]	100	1			T2	1		T9	3		T11	2
reset_info_cp[32]	116	1			T9	1		T10	3		T12	4
reset_info_cp[64]	92	1			T51	1		T35	1		T36	5
reset_info_cp[128]	120	1			T10	4		T12	4		T51	3

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3051	1			T2	6		T8	17		T10	47
reset_info_cp[1]	auto[1]	2709	1			T2	11		T6	1		T7	2
reset_info_cp[2]	auto[0]	982	1			T2	7		T10	24		T12	20
reset_info_cp[2]	auto[1]	2049	1			T2	4		T6	1		T7	2
reset_info_cp[4]	auto[0]	1396	1			T2	4		T10	33		T12	28
reset_info_cp[4]	auto[1]	2454	1			T2	5		T6	1		T7	2
reset_info_cp[8]	auto[0]	46	1			T12	1		T49	1		T104	1
reset_info_cp[8]	auto[1]	70	1			T10	1		T12	1		T108	1
reset_info_cp[16]	auto[0]	40	1			T9	3		T11	2		T12	1
reset_info_cp[16]	auto[1]	60	1			T2	1		T12	1		T51	1
reset_info_cp[32]	auto[0]	50	1			T9	1		T10	1		T12	3
reset_info_cp[32]	auto[1]	66	1			T10	2		T12	1		T25	1
reset_info_cp[64]	auto[0]	37	1			T35	1		T36	1		T106	1
reset_info_cp[64]	auto[1]	55	1			T51	1		T36	4		T41	1
reset_info_cp[128]	auto[0]	58	1			T10	3		T12	1		T51	2
reset_info_cp[128]	auto[1]	62	1			T10	1		T12	3		T51	1