Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/3.rstmgr_sw_rst.2944302045 Mar 19 02:44:53 PM PDT 24 Mar 19 02:44:55 PM PDT 24 252579154 ps
T537 /workspace/coverage/default/43.rstmgr_stress_all.3042082483 Mar 19 02:46:32 PM PDT 24 Mar 19 02:47:02 PM PDT 24 8466316841 ps
T538 /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.572173758 Mar 19 02:44:53 PM PDT 24 Mar 19 02:44:54 PM PDT 24 244665889 ps
T539 /workspace/coverage/default/17.rstmgr_alert_test.3654582293 Mar 19 02:45:43 PM PDT 24 Mar 19 02:45:44 PM PDT 24 63286025 ps
T540 /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1269050311 Mar 19 02:46:17 PM PDT 24 Mar 19 02:46:18 PM PDT 24 102233451 ps
T65 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2118381937 Mar 19 02:47:37 PM PDT 24 Mar 19 02:47:40 PM PDT 24 177958709 ps
T68 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.4189760968 Mar 19 02:47:25 PM PDT 24 Mar 19 02:47:28 PM PDT 24 422332685 ps
T66 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3924443788 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 493034440 ps
T67 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1071627638 Mar 19 02:47:31 PM PDT 24 Mar 19 02:47:33 PM PDT 24 406274948 ps
T69 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.305426653 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:31 PM PDT 24 788871450 ps
T70 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2533621784 Mar 19 02:47:38 PM PDT 24 Mar 19 02:47:39 PM PDT 24 159231963 ps
T71 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3476644149 Mar 19 02:47:38 PM PDT 24 Mar 19 02:47:41 PM PDT 24 882580564 ps
T116 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2267475945 Mar 19 02:47:37 PM PDT 24 Mar 19 02:47:39 PM PDT 24 74197561 ps
T87 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3689834913 Mar 19 02:47:39 PM PDT 24 Mar 19 02:47:42 PM PDT 24 299202729 ps
T91 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2253828228 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:32 PM PDT 24 267417750 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4245519686 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:19 PM PDT 24 221363024 ps
T117 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.598132423 Mar 19 02:47:38 PM PDT 24 Mar 19 02:47:39 PM PDT 24 90956317 ps
T88 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3526221978 Mar 19 02:47:31 PM PDT 24 Mar 19 02:47:33 PM PDT 24 223612405 ps
T118 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4007231425 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 101457164 ps
T96 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4068378614 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:30 PM PDT 24 122814753 ps
T90 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1058475677 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:30 PM PDT 24 740743223 ps
T542 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.534132398 Mar 19 02:47:27 PM PDT 24 Mar 19 02:47:33 PM PDT 24 1174993169 ps
T107 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3516713821 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 409991488 ps
T101 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1429210286 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:28 PM PDT 24 185783689 ps
T119 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3907693665 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 129577181 ps
T120 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3967358167 Mar 19 02:47:42 PM PDT 24 Mar 19 02:47:44 PM PDT 24 82158880 ps
T543 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3163161708 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 174081665 ps
T102 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1444962639 Mar 19 02:47:36 PM PDT 24 Mar 19 02:47:38 PM PDT 24 107787375 ps
T544 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1132890582 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:31 PM PDT 24 116939514 ps
T121 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3282933338 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:31 PM PDT 24 132581030 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3811276345 Mar 19 02:47:32 PM PDT 24 Mar 19 02:47:33 PM PDT 24 138453055 ps
T92 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3913044592 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:30 PM PDT 24 128480640 ps
T546 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2997898033 Mar 19 02:47:18 PM PDT 24 Mar 19 02:47:19 PM PDT 24 93696369 ps
T122 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.611585988 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 125324405 ps
T94 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1397430435 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 188235852 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1892612208 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:27 PM PDT 24 98291039 ps
T548 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1536498855 Mar 19 02:47:31 PM PDT 24 Mar 19 02:47:34 PM PDT 24 792710204 ps
T549 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1936734552 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:27 PM PDT 24 62230096 ps
T89 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.164913938 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:33 PM PDT 24 172740034 ps
T93 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4169567146 Mar 19 02:47:40 PM PDT 24 Mar 19 02:47:42 PM PDT 24 193567269 ps
T550 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.410960049 Mar 19 02:47:32 PM PDT 24 Mar 19 02:47:33 PM PDT 24 84733259 ps
T123 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1137545315 Mar 19 02:47:31 PM PDT 24 Mar 19 02:47:32 PM PDT 24 70072807 ps
T551 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1058901683 Mar 19 02:47:43 PM PDT 24 Mar 19 02:47:44 PM PDT 24 134578126 ps
T124 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.874763980 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:31 PM PDT 24 63496261 ps
T125 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.984381512 Mar 19 02:47:33 PM PDT 24 Mar 19 02:47:35 PM PDT 24 212031596 ps
T97 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1801287643 Mar 19 02:47:38 PM PDT 24 Mar 19 02:47:41 PM PDT 24 778873733 ps
T552 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3000612696 Mar 19 02:47:38 PM PDT 24 Mar 19 02:47:39 PM PDT 24 109159369 ps
T553 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3198559255 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:31 PM PDT 24 433028229 ps
T554 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3126635796 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:29 PM PDT 24 85609642 ps
T555 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1978964816 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:31 PM PDT 24 77866092 ps
T556 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.127920064 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:27 PM PDT 24 74194622 ps
T557 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2176912715 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:29 PM PDT 24 84113991 ps
T558 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1458778191 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 130581139 ps
T559 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1421266864 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:32 PM PDT 24 486282294 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4079044360 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:29 PM PDT 24 434658729 ps
T561 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3766471918 Mar 19 02:47:37 PM PDT 24 Mar 19 02:47:42 PM PDT 24 489793290 ps
T143 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1728682257 Mar 19 02:47:41 PM PDT 24 Mar 19 02:47:43 PM PDT 24 474869630 ps
T562 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3746283755 Mar 19 02:47:27 PM PDT 24 Mar 19 02:47:29 PM PDT 24 478443701 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2350791116 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:33 PM PDT 24 361360210 ps
T564 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2458605619 Mar 19 02:47:37 PM PDT 24 Mar 19 02:47:39 PM PDT 24 126074573 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2179605947 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 115985998 ps
T566 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.362792080 Mar 19 02:47:49 PM PDT 24 Mar 19 02:47:50 PM PDT 24 58904949 ps
T567 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3079576088 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:30 PM PDT 24 69659263 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3600181812 Mar 19 02:47:27 PM PDT 24 Mar 19 02:47:28 PM PDT 24 228118562 ps
T569 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2770917849 Mar 19 02:47:31 PM PDT 24 Mar 19 02:47:33 PM PDT 24 154484327 ps
T570 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2012098648 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:29 PM PDT 24 254611017 ps
T571 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2053196712 Mar 19 02:47:27 PM PDT 24 Mar 19 02:47:28 PM PDT 24 115205290 ps
T572 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1613327 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:22 PM PDT 24 1180655553 ps
T573 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2873820748 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:29 PM PDT 24 135207848 ps
T574 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.528464473 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:32 PM PDT 24 216486859 ps
T100 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3968143280 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:31 PM PDT 24 498989905 ps
T98 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2467040706 Mar 19 02:47:39 PM PDT 24 Mar 19 02:47:44 PM PDT 24 792504651 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1102509911 Mar 19 02:47:25 PM PDT 24 Mar 19 02:47:28 PM PDT 24 442994498 ps
T99 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.373867018 Mar 19 02:47:40 PM PDT 24 Mar 19 02:47:48 PM PDT 24 490234355 ps
T576 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1988258121 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:29 PM PDT 24 146915956 ps
T577 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3452531554 Mar 19 02:47:40 PM PDT 24 Mar 19 02:47:41 PM PDT 24 59233850 ps
T578 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.987451786 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:33 PM PDT 24 331952709 ps
T579 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2376010515 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:31 PM PDT 24 153744801 ps
T580 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3176327788 Mar 19 02:47:38 PM PDT 24 Mar 19 02:47:40 PM PDT 24 206037356 ps
T581 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2951077876 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:30 PM PDT 24 119081429 ps
T582 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1164974404 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:30 PM PDT 24 237689528 ps
T583 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4031997669 Mar 19 02:47:40 PM PDT 24 Mar 19 02:47:41 PM PDT 24 114746300 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3707920548 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:20 PM PDT 24 937946371 ps
T585 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1239951506 Mar 19 02:47:27 PM PDT 24 Mar 19 02:47:32 PM PDT 24 799287643 ps
T586 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1438564168 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:31 PM PDT 24 129653540 ps
T587 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1794451200 Mar 19 02:47:35 PM PDT 24 Mar 19 02:47:36 PM PDT 24 65036091 ps
T588 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2184574906 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:32 PM PDT 24 895614009 ps
T589 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1129071348 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:29 PM PDT 24 102038226 ps
T590 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.237421366 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 136067254 ps
T591 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1434741435 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:31 PM PDT 24 113914205 ps
T592 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1951663130 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:18 PM PDT 24 75905194 ps
T593 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3689064977 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:29 PM PDT 24 492669426 ps
T594 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1646706930 Mar 19 02:47:39 PM PDT 24 Mar 19 02:47:41 PM PDT 24 99827428 ps
T595 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2640119036 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:29 PM PDT 24 103494188 ps
T596 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.744832184 Mar 19 02:47:27 PM PDT 24 Mar 19 02:47:29 PM PDT 24 134024568 ps
T95 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1034170150 Mar 19 02:47:38 PM PDT 24 Mar 19 02:47:41 PM PDT 24 470914353 ps
T597 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.995262627 Mar 19 02:47:38 PM PDT 24 Mar 19 02:47:41 PM PDT 24 197871311 ps
T598 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2106647451 Mar 19 02:47:32 PM PDT 24 Mar 19 02:47:33 PM PDT 24 126743421 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2662374912 Mar 19 02:47:17 PM PDT 24 Mar 19 02:47:20 PM PDT 24 406068355 ps
T600 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3698950943 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:28 PM PDT 24 115282804 ps
T601 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.971500000 Mar 19 02:47:42 PM PDT 24 Mar 19 02:47:44 PM PDT 24 87414704 ps
T602 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3312538945 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 137409994 ps
T603 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2622174552 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:30 PM PDT 24 142823780 ps
T604 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2345426058 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:30 PM PDT 24 69403877 ps
T605 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.574818253 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:29 PM PDT 24 82694201 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3725364525 Mar 19 02:47:27 PM PDT 24 Mar 19 02:47:28 PM PDT 24 207664340 ps
T607 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1917515572 Mar 19 02:47:27 PM PDT 24 Mar 19 02:47:28 PM PDT 24 105196528 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3782932386 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:28 PM PDT 24 258275568 ps
T609 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2594472849 Mar 19 02:47:40 PM PDT 24 Mar 19 02:47:41 PM PDT 24 54982200 ps
T610 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.242857483 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:31 PM PDT 24 66278093 ps
T611 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1233750430 Mar 19 02:47:40 PM PDT 24 Mar 19 02:47:41 PM PDT 24 75998739 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1000322408 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:31 PM PDT 24 58785411 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2644292676 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:33 PM PDT 24 360497070 ps
T614 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3048637674 Mar 19 02:47:39 PM PDT 24 Mar 19 02:47:41 PM PDT 24 82121013 ps
T615 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3949859387 Mar 19 02:47:30 PM PDT 24 Mar 19 02:47:32 PM PDT 24 402082467 ps
T616 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3653932159 Mar 19 02:47:26 PM PDT 24 Mar 19 02:47:29 PM PDT 24 812587018 ps
T617 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2408214997 Mar 19 02:47:39 PM PDT 24 Mar 19 02:47:42 PM PDT 24 394038628 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1569800422 Mar 19 02:47:28 PM PDT 24 Mar 19 02:47:29 PM PDT 24 69948617 ps
T619 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1292002102 Mar 19 02:47:31 PM PDT 24 Mar 19 02:47:32 PM PDT 24 74449858 ps
T620 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3511412470 Mar 19 02:47:29 PM PDT 24 Mar 19 02:47:38 PM PDT 24 1558621305 ps

Test location /workspace/coverage/default/31.rstmgr_stress_all.1734004724
Short name T7
Test name
Test status
Simulation time 343081730 ps
CPU time 2.22 seconds
Started Mar 19 02:46:00 PM PDT 24
Finished Mar 19 02:46:03 PM PDT 24
Peak memory 201088 kb
Host smart-4e86b1e8-236d-43cd-91c1-ed9916f6edbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734004724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1734004724
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1699287041
Short name T50
Test name
Test status
Simulation time 278400591 ps
CPU time 1.88 seconds
Started Mar 19 02:44:55 PM PDT 24
Finished Mar 19 02:44:58 PM PDT 24
Peak memory 200824 kb
Host smart-fbb84b6d-75ba-4afa-a1b1-0d3955ef655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699287041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1699287041
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3447296845
Short name T12
Test name
Test status
Simulation time 11075744696 ps
CPU time 37.02 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:47:06 PM PDT 24
Peak memory 201172 kb
Host smart-a9e586b8-e79b-4b6c-9e77-021ea06b645a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447296845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3447296845
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.305426653
Short name T69
Test name
Test status
Simulation time 788871450 ps
CPU time 2.91 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 200632 kb
Host smart-70577b10-86ef-405e-acf6-44cbbd9f37fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305426653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.305426653
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.950122355
Short name T72
Test name
Test status
Simulation time 16685117575 ps
CPU time 28.09 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:45:22 PM PDT 24
Peak memory 218852 kb
Host smart-f8b1db34-474b-4324-9f85-6d22f6fc673f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950122355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.950122355
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2997115300
Short name T8
Test name
Test status
Simulation time 1904338411 ps
CPU time 8.16 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:44:59 PM PDT 24
Peak memory 217888 kb
Host smart-66e35e38-17b1-42fb-b2fd-2e438ddb59e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997115300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2997115300
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.4189760968
Short name T68
Test name
Test status
Simulation time 422332685 ps
CPU time 2.94 seconds
Started Mar 19 02:47:25 PM PDT 24
Finished Mar 19 02:47:28 PM PDT 24
Peak memory 208712 kb
Host smart-ef8ad1bf-6e9b-4142-ac47-ec5cf7a4948d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189760968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.4189760968
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.208971982
Short name T111
Test name
Test status
Simulation time 6303298554 ps
CPU time 26.98 seconds
Started Mar 19 02:45:11 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 201176 kb
Host smart-e18bea08-2214-4df7-95d5-09439ff1f6bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208971982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.208971982
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3282774676
Short name T75
Test name
Test status
Simulation time 66865099 ps
CPU time 0.79 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 200760 kb
Host smart-1bfb3ca3-4dd7-4f92-b5ee-2e080b5a5dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282774676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3282774676
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2595900754
Short name T28
Test name
Test status
Simulation time 1892827789 ps
CPU time 6.95 seconds
Started Mar 19 02:46:05 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 217752 kb
Host smart-e0aa68d6-2ac2-4436-a77b-017ab44b9890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595900754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2595900754
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2617311073
Short name T164
Test name
Test status
Simulation time 107945208 ps
CPU time 1.01 seconds
Started Mar 19 02:45:08 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 200880 kb
Host smart-232070d7-f3f8-4420-898e-b3823f61ea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617311073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2617311073
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1801287643
Short name T97
Test name
Test status
Simulation time 778873733 ps
CPU time 2.63 seconds
Started Mar 19 02:47:38 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 200636 kb
Host smart-7217711b-f362-45f2-98df-db673a8c8352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801287643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1801287643
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3689834913
Short name T87
Test name
Test status
Simulation time 299202729 ps
CPU time 2.28 seconds
Started Mar 19 02:47:39 PM PDT 24
Finished Mar 19 02:47:42 PM PDT 24
Peak memory 208852 kb
Host smart-8bc3199f-5383-4aa1-ad9f-d3f771d4418b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689834913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3689834913
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1014136476
Short name T59
Test name
Test status
Simulation time 170525051 ps
CPU time 1.22 seconds
Started Mar 19 02:44:55 PM PDT 24
Finished Mar 19 02:44:57 PM PDT 24
Peak memory 200864 kb
Host smart-560652e8-62d1-4eff-ad4d-0780377031df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014136476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1014136476
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3769919729
Short name T26
Test name
Test status
Simulation time 1218083766 ps
CPU time 5.49 seconds
Started Mar 19 02:45:47 PM PDT 24
Finished Mar 19 02:45:53 PM PDT 24
Peak memory 218556 kb
Host smart-0deb5699-a529-41c2-aacb-a008d32dfc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769919729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3769919729
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4007231425
Short name T118
Test name
Test status
Simulation time 101457164 ps
CPU time 1.14 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 200644 kb
Host smart-8d95b10c-d2ed-4d9a-a41c-be3c1087aa8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007231425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.4007231425
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.4121595258
Short name T16
Test name
Test status
Simulation time 157535040 ps
CPU time 0.83 seconds
Started Mar 19 02:45:21 PM PDT 24
Finished Mar 19 02:45:22 PM PDT 24
Peak memory 200756 kb
Host smart-447b8e02-8fed-4c65-9d12-5bc6e1310301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121595258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.4121595258
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3914833482
Short name T166
Test name
Test status
Simulation time 243904865 ps
CPU time 1.1 seconds
Started Mar 19 02:45:26 PM PDT 24
Finished Mar 19 02:45:27 PM PDT 24
Peak memory 218168 kb
Host smart-695df5b4-35b0-42e5-ba19-b23ab86ee0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914833482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3914833482
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3968143280
Short name T100
Test name
Test status
Simulation time 498989905 ps
CPU time 1.98 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 200652 kb
Host smart-b6022931-365d-4318-8ff4-5c0cb15de1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968143280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3968143280
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2350791116
Short name T563
Test name
Test status
Simulation time 361360210 ps
CPU time 2.63 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 216908 kb
Host smart-6126be6e-339d-4a37-899f-97488ec5537c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350791116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2350791116
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1058475677
Short name T90
Test name
Test status
Simulation time 740743223 ps
CPU time 2.97 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:30 PM PDT 24
Peak memory 200508 kb
Host smart-beb7faec-3eaa-4015-b58d-19eca58a94fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058475677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1058475677
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4245519686
Short name T541
Test name
Test status
Simulation time 221363024 ps
CPU time 1.69 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 200560 kb
Host smart-ec4c7f14-db18-4527-b769-58128f544e0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245519686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
245519686
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1613327
Short name T572
Test name
Test status
Simulation time 1180655553 ps
CPU time 5.48 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:22 PM PDT 24
Peak memory 200572 kb
Host smart-02749dd3-d2e7-4ed3-9792-66a07ddfa9f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1613327
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2997898033
Short name T546
Test name
Test status
Simulation time 93696369 ps
CPU time 0.83 seconds
Started Mar 19 02:47:18 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 200356 kb
Host smart-70077998-bdb9-493b-9ac6-e08a700a3163
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997898033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
997898033
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1892612208
Short name T547
Test name
Test status
Simulation time 98291039 ps
CPU time 0.92 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:27 PM PDT 24
Peak memory 200512 kb
Host smart-8053f60c-6616-46fd-9d2d-1c957c264703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892612208 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1892612208
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1951663130
Short name T592
Test name
Test status
Simulation time 75905194 ps
CPU time 0.81 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:18 PM PDT 24
Peak memory 200360 kb
Host smart-48fd3f60-ec3b-4669-bd11-7530c96f0e50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951663130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1951663130
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2662374912
Short name T599
Test name
Test status
Simulation time 406068355 ps
CPU time 3.09 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 208832 kb
Host smart-f6965894-342b-4289-859e-9420f4ea3065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662374912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2662374912
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3707920548
Short name T584
Test name
Test status
Simulation time 937946371 ps
CPU time 3.18 seconds
Started Mar 19 02:47:17 PM PDT 24
Finished Mar 19 02:47:20 PM PDT 24
Peak memory 200604 kb
Host smart-2f418eb4-4e8c-4d40-baf2-78ae63d3b5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707920548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3707920548
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1102509911
Short name T575
Test name
Test status
Simulation time 442994498 ps
CPU time 2.89 seconds
Started Mar 19 02:47:25 PM PDT 24
Finished Mar 19 02:47:28 PM PDT 24
Peak memory 200612 kb
Host smart-c171f024-b05e-42ef-af52-863e5a5d05ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102509911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
102509911
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.534132398
Short name T542
Test name
Test status
Simulation time 1174993169 ps
CPU time 5.19 seconds
Started Mar 19 02:47:27 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 200576 kb
Host smart-fe77a9db-58e8-4ce0-80e1-b66c2c68641b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534132398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.534132398
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3811276345
Short name T545
Test name
Test status
Simulation time 138453055 ps
CPU time 0.94 seconds
Started Mar 19 02:47:32 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 200364 kb
Host smart-16213723-6c32-4cd4-94b7-afb24c4f538e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811276345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
811276345
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2053196712
Short name T571
Test name
Test status
Simulation time 115205290 ps
CPU time 1 seconds
Started Mar 19 02:47:27 PM PDT 24
Finished Mar 19 02:47:28 PM PDT 24
Peak memory 200420 kb
Host smart-5fc7c072-e0e1-412e-adde-ece8ee1560e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053196712 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2053196712
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1569800422
Short name T618
Test name
Test status
Simulation time 69948617 ps
CPU time 0.79 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200316 kb
Host smart-54631be3-cf82-4818-94f9-0a86536fa1ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569800422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1569800422
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2622174552
Short name T603
Test name
Test status
Simulation time 142823780 ps
CPU time 1.17 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:30 PM PDT 24
Peak memory 200428 kb
Host smart-c659fb18-d5f6-4fdd-b417-231d2c9924be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622174552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2622174552
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2770917849
Short name T569
Test name
Test status
Simulation time 154484327 ps
CPU time 2.32 seconds
Started Mar 19 02:47:31 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 216980 kb
Host smart-a0a9b90c-18d3-4e0c-852a-5f8916c8cfca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770917849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2770917849
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3163161708
Short name T543
Test name
Test status
Simulation time 174081665 ps
CPU time 1.22 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200464 kb
Host smart-bf964187-5391-4407-b68b-5642a0c91102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163161708 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3163161708
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.242857483
Short name T610
Test name
Test status
Simulation time 66278093 ps
CPU time 0.78 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 200396 kb
Host smart-c4450ee8-20ce-4a7e-b12e-cdf77ed0eab9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242857483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.242857483
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1978964816
Short name T555
Test name
Test status
Simulation time 77866092 ps
CPU time 1.05 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 199536 kb
Host smart-96e5ac3e-b540-4193-898a-00823fab449f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978964816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1978964816
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3312538945
Short name T602
Test name
Test status
Simulation time 137409994 ps
CPU time 1.46 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 208820 kb
Host smart-a3fe9000-e372-46b3-ba80-695bcc6c9c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312538945 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3312538945
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1292002102
Short name T619
Test name
Test status
Simulation time 74449858 ps
CPU time 0.81 seconds
Started Mar 19 02:47:31 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200380 kb
Host smart-8e0f70a1-76b6-4640-b6a3-3139d833ca13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292002102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1292002102
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3907693665
Short name T119
Test name
Test status
Simulation time 129577181 ps
CPU time 1.23 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200224 kb
Host smart-637493dc-3984-4719-b8ce-b5e12ec1b816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907693665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3907693665
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.164913938
Short name T89
Test name
Test status
Simulation time 172740034 ps
CPU time 2.37 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 200652 kb
Host smart-f77bb0d4-d080-460c-b98e-26cff8b849af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164913938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.164913938
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1071627638
Short name T67
Test name
Test status
Simulation time 406274948 ps
CPU time 1.88 seconds
Started Mar 19 02:47:31 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 200636 kb
Host smart-8c0d8293-daa4-4318-b93a-19a0a6d7b909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071627638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1071627638
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2106647451
Short name T598
Test name
Test status
Simulation time 126743421 ps
CPU time 1.03 seconds
Started Mar 19 02:47:32 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 200464 kb
Host smart-12a44a03-01a5-473d-9ff9-fdca040a9c11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106647451 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2106647451
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.574818253
Short name T605
Test name
Test status
Simulation time 82694201 ps
CPU time 0.84 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200376 kb
Host smart-54f5e529-064a-417f-83a0-876dd6e6f4fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574818253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.574818253
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.611585988
Short name T122
Test name
Test status
Simulation time 125324405 ps
CPU time 1.11 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200420 kb
Host smart-92b63825-a162-466f-b047-81c457c6c57a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611585988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.611585988
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.987451786
Short name T578
Test name
Test status
Simulation time 331952709 ps
CPU time 2.67 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 208388 kb
Host smart-1eafc75d-5c97-4342-a7c1-48d544e88a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987451786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.987451786
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1397430435
Short name T94
Test name
Test status
Simulation time 188235852 ps
CPU time 1.19 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200504 kb
Host smart-058cafe6-0140-4fea-a4b0-5006e82fd4b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397430435 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1397430435
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.410960049
Short name T550
Test name
Test status
Simulation time 84733259 ps
CPU time 0.9 seconds
Started Mar 19 02:47:32 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 200404 kb
Host smart-9ae70a36-194b-4d53-93a2-cb75209abf67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410960049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.410960049
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.984381512
Short name T125
Test name
Test status
Simulation time 212031596 ps
CPU time 1.54 seconds
Started Mar 19 02:47:33 PM PDT 24
Finished Mar 19 02:47:35 PM PDT 24
Peak memory 200612 kb
Host smart-a9f93e75-049c-4135-ac5b-4015ffa4a5b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984381512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.984381512
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1458778191
Short name T558
Test name
Test status
Simulation time 130581139 ps
CPU time 1.89 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 208868 kb
Host smart-ff27defe-a0b2-4904-b8fb-ce0a88a328cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458778191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1458778191
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3516713821
Short name T107
Test name
Test status
Simulation time 409991488 ps
CPU time 1.88 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200632 kb
Host smart-9dfdc6af-3b07-4b10-a7ac-96436f63163a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516713821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3516713821
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2118381937
Short name T65
Test name
Test status
Simulation time 177958709 ps
CPU time 1.83 seconds
Started Mar 19 02:47:37 PM PDT 24
Finished Mar 19 02:47:40 PM PDT 24
Peak memory 208872 kb
Host smart-8b9028c7-ec7e-4f9c-8677-ee86b744f3b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118381937 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2118381937
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.362792080
Short name T566
Test name
Test status
Simulation time 58904949 ps
CPU time 0.74 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:50 PM PDT 24
Peak memory 200404 kb
Host smart-6da1a878-8475-412e-974d-24d3c5d19233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362792080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.362792080
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2458605619
Short name T564
Test name
Test status
Simulation time 126074573 ps
CPU time 1.39 seconds
Started Mar 19 02:47:37 PM PDT 24
Finished Mar 19 02:47:39 PM PDT 24
Peak memory 200612 kb
Host smart-d8956660-4310-4c58-8b1d-c5610706aa65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458605619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2458605619
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.995262627
Short name T597
Test name
Test status
Simulation time 197871311 ps
CPU time 2.94 seconds
Started Mar 19 02:47:38 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 216848 kb
Host smart-c93a0b77-b11d-4e3e-bcb9-ef840ef1c5b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995262627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.995262627
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3176327788
Short name T580
Test name
Test status
Simulation time 206037356 ps
CPU time 1.43 seconds
Started Mar 19 02:47:38 PM PDT 24
Finished Mar 19 02:47:40 PM PDT 24
Peak memory 200464 kb
Host smart-9347fb58-dc34-473c-a327-33768aaff900
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176327788 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3176327788
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3452531554
Short name T577
Test name
Test status
Simulation time 59233850 ps
CPU time 0.8 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 200264 kb
Host smart-fec185dc-cdec-40f7-9425-5b08c07c11d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452531554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3452531554
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.598132423
Short name T117
Test name
Test status
Simulation time 90956317 ps
CPU time 1.05 seconds
Started Mar 19 02:47:38 PM PDT 24
Finished Mar 19 02:47:39 PM PDT 24
Peak memory 200436 kb
Host smart-474cc0af-5918-473d-93c3-d1517260b89f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598132423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.598132423
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1728682257
Short name T143
Test name
Test status
Simulation time 474869630 ps
CPU time 1.79 seconds
Started Mar 19 02:47:41 PM PDT 24
Finished Mar 19 02:47:43 PM PDT 24
Peak memory 200556 kb
Host smart-27a83572-81c5-4286-8a44-dded4d130610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728682257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1728682257
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4031997669
Short name T583
Test name
Test status
Simulation time 114746300 ps
CPU time 0.99 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 200516 kb
Host smart-15a00ec8-0f35-4e43-8d6f-bacb499f8fa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031997669 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.4031997669
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1233750430
Short name T611
Test name
Test status
Simulation time 75998739 ps
CPU time 0.87 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 200408 kb
Host smart-8b45ca88-0541-4696-8f28-f645defeef23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233750430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1233750430
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1646706930
Short name T594
Test name
Test status
Simulation time 99827428 ps
CPU time 1.27 seconds
Started Mar 19 02:47:39 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 200612 kb
Host smart-f232aacc-d071-4f34-9481-9dab08151e66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646706930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1646706930
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1444962639
Short name T102
Test name
Test status
Simulation time 107787375 ps
CPU time 1.65 seconds
Started Mar 19 02:47:36 PM PDT 24
Finished Mar 19 02:47:38 PM PDT 24
Peak memory 210644 kb
Host smart-e9d921b8-f26b-4797-9ebf-50a4b449bcd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444962639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1444962639
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2467040706
Short name T98
Test name
Test status
Simulation time 792504651 ps
CPU time 3.24 seconds
Started Mar 19 02:47:39 PM PDT 24
Finished Mar 19 02:47:44 PM PDT 24
Peak memory 200640 kb
Host smart-d0a3e4b6-9eac-4024-982d-3db0ebeddce8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467040706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2467040706
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1058901683
Short name T551
Test name
Test status
Simulation time 134578126 ps
CPU time 1.11 seconds
Started Mar 19 02:47:43 PM PDT 24
Finished Mar 19 02:47:44 PM PDT 24
Peak memory 208712 kb
Host smart-cd8a09c9-6a2a-4e73-81df-19fd86c80e95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058901683 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1058901683
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3967358167
Short name T120
Test name
Test status
Simulation time 82158880 ps
CPU time 0.87 seconds
Started Mar 19 02:47:42 PM PDT 24
Finished Mar 19 02:47:44 PM PDT 24
Peak memory 200404 kb
Host smart-b6022405-116a-4a94-a5a7-637de4b72b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967358167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3967358167
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.971500000
Short name T601
Test name
Test status
Simulation time 87414704 ps
CPU time 0.97 seconds
Started Mar 19 02:47:42 PM PDT 24
Finished Mar 19 02:47:44 PM PDT 24
Peak memory 200332 kb
Host smart-0199422f-6bff-42f1-b8e6-9bfab082cdca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971500000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.971500000
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2408214997
Short name T617
Test name
Test status
Simulation time 394038628 ps
CPU time 2.88 seconds
Started Mar 19 02:47:39 PM PDT 24
Finished Mar 19 02:47:42 PM PDT 24
Peak memory 211956 kb
Host smart-da693cc5-417a-46c0-8abe-87e9ca9c3697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408214997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2408214997
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1034170150
Short name T95
Test name
Test status
Simulation time 470914353 ps
CPU time 1.92 seconds
Started Mar 19 02:47:38 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 200636 kb
Host smart-3bbdf02f-602b-48e2-9d1c-b636e3ee6116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034170150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1034170150
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3000612696
Short name T552
Test name
Test status
Simulation time 109159369 ps
CPU time 1 seconds
Started Mar 19 02:47:38 PM PDT 24
Finished Mar 19 02:47:39 PM PDT 24
Peak memory 200500 kb
Host smart-452c32da-4e5e-40c3-a3dd-d59dd9da6064
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000612696 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3000612696
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2594472849
Short name T609
Test name
Test status
Simulation time 54982200 ps
CPU time 0.78 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 200388 kb
Host smart-b02c85ed-6c5e-4ace-bdbc-51d256326f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594472849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2594472849
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3048637674
Short name T614
Test name
Test status
Simulation time 82121013 ps
CPU time 1.13 seconds
Started Mar 19 02:47:39 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 200416 kb
Host smart-89e08938-89e2-4ca3-b383-38d70c79dbd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048637674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3048637674
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3766471918
Short name T561
Test name
Test status
Simulation time 489793290 ps
CPU time 3.6 seconds
Started Mar 19 02:47:37 PM PDT 24
Finished Mar 19 02:47:42 PM PDT 24
Peak memory 208820 kb
Host smart-766b5868-7559-445f-b2b6-5370fd2be391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766471918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3766471918
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3476644149
Short name T71
Test name
Test status
Simulation time 882580564 ps
CPU time 3.01 seconds
Started Mar 19 02:47:38 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 200604 kb
Host smart-319cb212-b248-4791-b8da-4b9b4dad623d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476644149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3476644149
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2533621784
Short name T70
Test name
Test status
Simulation time 159231963 ps
CPU time 1.42 seconds
Started Mar 19 02:47:38 PM PDT 24
Finished Mar 19 02:47:39 PM PDT 24
Peak memory 208692 kb
Host smart-f461e4cd-19b4-41e9-a78d-e454917724c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533621784 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2533621784
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1794451200
Short name T587
Test name
Test status
Simulation time 65036091 ps
CPU time 0.84 seconds
Started Mar 19 02:47:35 PM PDT 24
Finished Mar 19 02:47:36 PM PDT 24
Peak memory 200348 kb
Host smart-16c18aa9-327d-4013-b000-0c8e5113abc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794451200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1794451200
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2267475945
Short name T116
Test name
Test status
Simulation time 74197561 ps
CPU time 0.98 seconds
Started Mar 19 02:47:37 PM PDT 24
Finished Mar 19 02:47:39 PM PDT 24
Peak memory 200472 kb
Host smart-98e88e59-e009-4259-8429-3e4a164664b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267475945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2267475945
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4169567146
Short name T93
Test name
Test status
Simulation time 193567269 ps
CPU time 1.75 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:42 PM PDT 24
Peak memory 208784 kb
Host smart-bf882b51-6e88-4c60-a822-5349304c0041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169567146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4169567146
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.373867018
Short name T99
Test name
Test status
Simulation time 490234355 ps
CPU time 2.07 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:48 PM PDT 24
Peak memory 200620 kb
Host smart-3ae36b89-eba9-4e42-b9ea-f9d033930419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373867018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.373867018
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4079044360
Short name T560
Test name
Test status
Simulation time 434658729 ps
CPU time 2.62 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200552 kb
Host smart-a8e7392f-d9d1-4505-b2a8-beca2802fb1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079044360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.4
079044360
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1239951506
Short name T585
Test name
Test status
Simulation time 799287643 ps
CPU time 4.53 seconds
Started Mar 19 02:47:27 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200564 kb
Host smart-acc7a7e3-777f-4fb4-b67e-b814f57c0091
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239951506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
239951506
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1988258121
Short name T576
Test name
Test status
Simulation time 146915956 ps
CPU time 0.93 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200364 kb
Host smart-fc5d0be8-2cf5-4e6e-b780-406863b5c514
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988258121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
988258121
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4068378614
Short name T96
Test name
Test status
Simulation time 122814753 ps
CPU time 1.11 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:30 PM PDT 24
Peak memory 200472 kb
Host smart-f8344717-c252-40f8-99dc-4b6ea80ee8d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068378614 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.4068378614
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2345426058
Short name T604
Test name
Test status
Simulation time 69403877 ps
CPU time 0.78 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:30 PM PDT 24
Peak memory 200292 kb
Host smart-1cf49645-9998-4e3c-a429-0e2be11178eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345426058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2345426058
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.127920064
Short name T556
Test name
Test status
Simulation time 74194622 ps
CPU time 0.98 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:27 PM PDT 24
Peak memory 200468 kb
Host smart-25476c67-1a7b-4603-9c7c-dc31065ae07f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127920064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.127920064
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3913044592
Short name T92
Test name
Test status
Simulation time 128480640 ps
CPU time 1.79 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:30 PM PDT 24
Peak memory 217020 kb
Host smart-807ae1a2-05af-482c-a51f-9c8a8acd40a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913044592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3913044592
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2184574906
Short name T588
Test name
Test status
Simulation time 895614009 ps
CPU time 3.17 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200696 kb
Host smart-415c8428-e8d8-48b8-a8b4-e9d2fab5894a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184574906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2184574906
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2179605947
Short name T565
Test name
Test status
Simulation time 115985998 ps
CPU time 1.35 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200560 kb
Host smart-3f10f333-0ee5-4d7b-a0ed-621f6736aa20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179605947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
179605947
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1421266864
Short name T559
Test name
Test status
Simulation time 486282294 ps
CPU time 5.86 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200560 kb
Host smart-842ff833-de7a-40ea-b618-0c580243506b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421266864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
421266864
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1129071348
Short name T589
Test name
Test status
Simulation time 102038226 ps
CPU time 0.84 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200388 kb
Host smart-04a94c85-b188-4ec1-b13f-6050ebb77317
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129071348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
129071348
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1917515572
Short name T607
Test name
Test status
Simulation time 105196528 ps
CPU time 0.96 seconds
Started Mar 19 02:47:27 PM PDT 24
Finished Mar 19 02:47:28 PM PDT 24
Peak memory 200488 kb
Host smart-036f2289-8e76-45ff-b284-7d4ffee51f09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917515572 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1917515572
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1936734552
Short name T549
Test name
Test status
Simulation time 62230096 ps
CPU time 0.82 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:27 PM PDT 24
Peak memory 200384 kb
Host smart-d670d570-5f1d-4288-96f0-26965e5cf9ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936734552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1936734552
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3725364525
Short name T606
Test name
Test status
Simulation time 207664340 ps
CPU time 1.47 seconds
Started Mar 19 02:47:27 PM PDT 24
Finished Mar 19 02:47:28 PM PDT 24
Peak memory 200624 kb
Host smart-ce16d242-862b-41b9-bc8d-c653492004e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725364525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3725364525
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3526221978
Short name T88
Test name
Test status
Simulation time 223612405 ps
CPU time 1.97 seconds
Started Mar 19 02:47:31 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 208836 kb
Host smart-21dc2ec2-df40-4c69-9ec4-91926703f099
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526221978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3526221978
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3198559255
Short name T553
Test name
Test status
Simulation time 433028229 ps
CPU time 1.81 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 200880 kb
Host smart-417c11f0-970c-4cba-8032-a70c717d09dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198559255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3198559255
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3782932386
Short name T608
Test name
Test status
Simulation time 258275568 ps
CPU time 1.67 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:28 PM PDT 24
Peak memory 200492 kb
Host smart-b74809f0-11d2-4276-989a-f7dff3d06a9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782932386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
782932386
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3511412470
Short name T620
Test name
Test status
Simulation time 1558621305 ps
CPU time 8.63 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:38 PM PDT 24
Peak memory 200536 kb
Host smart-562ff3af-6a87-4c3b-857a-2900ffe9e46a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511412470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
511412470
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3698950943
Short name T600
Test name
Test status
Simulation time 115282804 ps
CPU time 0.99 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:28 PM PDT 24
Peak memory 200368 kb
Host smart-ee03fb54-9466-42be-a4aa-ad7c73c71ee5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698950943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
698950943
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1429210286
Short name T101
Test name
Test status
Simulation time 185783689 ps
CPU time 1.24 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:28 PM PDT 24
Peak memory 210128 kb
Host smart-b4037505-f9a1-459d-aa88-2044312fb1fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429210286 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1429210286
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1000322408
Short name T612
Test name
Test status
Simulation time 58785411 ps
CPU time 0.79 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 200380 kb
Host smart-bc0674b8-326e-440c-b8a5-127e646d900e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000322408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1000322408
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3600181812
Short name T568
Test name
Test status
Simulation time 228118562 ps
CPU time 1.54 seconds
Started Mar 19 02:47:27 PM PDT 24
Finished Mar 19 02:47:28 PM PDT 24
Peak memory 200616 kb
Host smart-eba9b086-f588-42a9-bbe4-edbfe5c5e47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600181812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3600181812
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2644292676
Short name T613
Test name
Test status
Simulation time 360497070 ps
CPU time 2.6 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 208808 kb
Host smart-79f81f1d-c69c-4159-a415-0299e2a8dbf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644292676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2644292676
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3653932159
Short name T616
Test name
Test status
Simulation time 812587018 ps
CPU time 3.03 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200668 kb
Host smart-87ec6f69-8e34-47cc-a638-33ccc8dde15d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653932159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3653932159
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1132890582
Short name T544
Test name
Test status
Simulation time 116939514 ps
CPU time 1.02 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 200484 kb
Host smart-95d289a8-fd25-41b2-8f49-d60cab440877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132890582 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1132890582
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3126635796
Short name T554
Test name
Test status
Simulation time 85609642 ps
CPU time 0.86 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200264 kb
Host smart-2a88d169-89c4-4e9f-9d6e-ed229eb66c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126635796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3126635796
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.744832184
Short name T596
Test name
Test status
Simulation time 134024568 ps
CPU time 1.07 seconds
Started Mar 19 02:47:27 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200452 kb
Host smart-b4291250-bfa4-401d-b921-d8c76fc4a47b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744832184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.744832184
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3746283755
Short name T562
Test name
Test status
Simulation time 478443701 ps
CPU time 2.1 seconds
Started Mar 19 02:47:27 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200704 kb
Host smart-bb0e4a63-a004-4d3c-bb3f-e8ddc7ccf3b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746283755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3746283755
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1434741435
Short name T591
Test name
Test status
Simulation time 113914205 ps
CPU time 1.25 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 211732 kb
Host smart-2e9ab449-3138-45d4-9085-7a81bb6856b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434741435 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1434741435
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2176912715
Short name T557
Test name
Test status
Simulation time 84113991 ps
CPU time 0.93 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200360 kb
Host smart-188695cd-eec2-41ad-90c3-16a69b412d02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176912715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2176912715
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3282933338
Short name T121
Test name
Test status
Simulation time 132581030 ps
CPU time 1.24 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 200584 kb
Host smart-f10fbe03-e332-4302-bf94-585937acf210
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282933338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3282933338
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2253828228
Short name T91
Test name
Test status
Simulation time 267417750 ps
CPU time 2.22 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 208792 kb
Host smart-3dc4e2bb-a473-4771-b969-fd10fa8b87dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253828228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2253828228
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3924443788
Short name T66
Test name
Test status
Simulation time 493034440 ps
CPU time 2.19 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200652 kb
Host smart-a2de7cfb-c1fe-43cd-bb94-0f9573dcfb30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924443788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3924443788
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2376010515
Short name T579
Test name
Test status
Simulation time 153744801 ps
CPU time 1.41 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 208896 kb
Host smart-667e323d-d6d6-47e8-b9c3-aed4ce3b52b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376010515 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2376010515
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.874763980
Short name T124
Test name
Test status
Simulation time 63496261 ps
CPU time 0.88 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 200408 kb
Host smart-3c384f5d-7c9a-45ee-95b9-9e3c9c4a45a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874763980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.874763980
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.237421366
Short name T590
Test name
Test status
Simulation time 136067254 ps
CPU time 1.41 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200656 kb
Host smart-d72ff95b-635f-444c-911e-60819cc346f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237421366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.237421366
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2012098648
Short name T570
Test name
Test status
Simulation time 254611017 ps
CPU time 1.96 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200608 kb
Host smart-048923c3-a05f-4b8e-82ab-a01e2934f976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012098648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2012098648
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3689064977
Short name T593
Test name
Test status
Simulation time 492669426 ps
CPU time 2.16 seconds
Started Mar 19 02:47:26 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200676 kb
Host smart-9449caaf-ae77-4ed3-a0c4-9966828888dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689064977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3689064977
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1438564168
Short name T586
Test name
Test status
Simulation time 129653540 ps
CPU time 1.43 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:31 PM PDT 24
Peak memory 207696 kb
Host smart-2e24d37d-d527-4d50-abf5-2cb0e3dd3db9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438564168 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1438564168
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3079576088
Short name T567
Test name
Test status
Simulation time 69659263 ps
CPU time 0.85 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:30 PM PDT 24
Peak memory 200264 kb
Host smart-ee733f92-12d4-4043-bfa0-d0d1a9918459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079576088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3079576088
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2951077876
Short name T581
Test name
Test status
Simulation time 119081429 ps
CPU time 1.1 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:30 PM PDT 24
Peak memory 200432 kb
Host smart-32abc5a7-470b-4d5c-b7cd-d2cbc7b8996c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951077876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2951077876
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.528464473
Short name T574
Test name
Test status
Simulation time 216486859 ps
CPU time 2.98 seconds
Started Mar 19 02:47:29 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 208776 kb
Host smart-8089b62f-86d9-4631-8875-deab17d00339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528464473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.528464473
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3949859387
Short name T615
Test name
Test status
Simulation time 402082467 ps
CPU time 1.88 seconds
Started Mar 19 02:47:30 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200628 kb
Host smart-85844bfd-7876-4ea8-8c1c-461942c2030a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949859387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3949859387
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2873820748
Short name T573
Test name
Test status
Simulation time 135207848 ps
CPU time 1.05 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 200472 kb
Host smart-8ff82bf7-14b1-46b7-9e6e-59ba2f57e1ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873820748 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2873820748
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1137545315
Short name T123
Test name
Test status
Simulation time 70072807 ps
CPU time 0.82 seconds
Started Mar 19 02:47:31 PM PDT 24
Finished Mar 19 02:47:32 PM PDT 24
Peak memory 200352 kb
Host smart-de46f155-d6d0-479a-aaca-b5638fa8d98a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137545315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1137545315
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1164974404
Short name T582
Test name
Test status
Simulation time 237689528 ps
CPU time 1.56 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:30 PM PDT 24
Peak memory 200640 kb
Host smart-1541728b-7735-4092-929c-620ee0db4b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164974404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1164974404
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2640119036
Short name T595
Test name
Test status
Simulation time 103494188 ps
CPU time 1.24 seconds
Started Mar 19 02:47:28 PM PDT 24
Finished Mar 19 02:47:29 PM PDT 24
Peak memory 208788 kb
Host smart-6c53e71f-5fe6-41a5-bb78-d0248a18d363
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640119036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2640119036
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1536498855
Short name T548
Test name
Test status
Simulation time 792710204 ps
CPU time 2.91 seconds
Started Mar 19 02:47:31 PM PDT 24
Finished Mar 19 02:47:34 PM PDT 24
Peak memory 200680 kb
Host smart-903331d9-2bce-4cda-bbe9-e2ea8571df45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536498855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1536498855
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3217183791
Short name T266
Test name
Test status
Simulation time 65980055 ps
CPU time 0.8 seconds
Started Mar 19 02:44:52 PM PDT 24
Finished Mar 19 02:44:53 PM PDT 24
Peak memory 200772 kb
Host smart-baca9b16-9699-4998-8f9f-077f35b99ddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217183791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3217183791
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2864140632
Short name T33
Test name
Test status
Simulation time 1224364564 ps
CPU time 5.82 seconds
Started Mar 19 02:44:50 PM PDT 24
Finished Mar 19 02:44:56 PM PDT 24
Peak memory 222544 kb
Host smart-21afe7f0-667c-4737-9c8a-0ec24ce0cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864140632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2864140632
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4241373101
Short name T250
Test name
Test status
Simulation time 244485581 ps
CPU time 1.09 seconds
Started Mar 19 02:44:56 PM PDT 24
Finished Mar 19 02:44:57 PM PDT 24
Peak memory 218164 kb
Host smart-a2d65621-faac-4398-8103-75e3ab93cc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241373101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4241373101
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3488899270
Short name T395
Test name
Test status
Simulation time 197365621 ps
CPU time 0.98 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:44:52 PM PDT 24
Peak memory 200724 kb
Host smart-6bec64fc-c03c-4498-b3bb-eb35679d8085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488899270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3488899270
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.4099553128
Short name T2
Test name
Test status
Simulation time 1309884479 ps
CPU time 5.47 seconds
Started Mar 19 02:44:52 PM PDT 24
Finished Mar 19 02:44:58 PM PDT 24
Peak memory 201080 kb
Host smart-6c608977-8166-4e77-bb96-9ab1952600cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099553128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.4099553128
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3080220050
Short name T79
Test name
Test status
Simulation time 16524361649 ps
CPU time 29.16 seconds
Started Mar 19 02:44:50 PM PDT 24
Finished Mar 19 02:45:19 PM PDT 24
Peak memory 218816 kb
Host smart-fc845141-ae5b-47e1-a780-2d3053039de1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080220050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3080220050
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1276143737
Short name T529
Test name
Test status
Simulation time 138195455 ps
CPU time 1.21 seconds
Started Mar 19 02:44:52 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 200864 kb
Host smart-e669fa7f-22e1-4db6-9d27-7c05ad31ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276143737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1276143737
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1453975843
Short name T403
Test name
Test status
Simulation time 184202200 ps
CPU time 1.32 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 201056 kb
Host smart-81adeb25-5432-4541-9876-839aab28b34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453975843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1453975843
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1404625722
Short name T328
Test name
Test status
Simulation time 1184780747 ps
CPU time 5.81 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:59 PM PDT 24
Peak memory 201088 kb
Host smart-82efa79d-4a18-4c32-b4a0-0bd2166e6b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404625722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1404625722
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.557313106
Short name T199
Test name
Test status
Simulation time 371501243 ps
CPU time 2.39 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 200856 kb
Host smart-b47f94dd-5c42-42af-8334-6f5f1f63137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557313106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.557313106
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3715924287
Short name T374
Test name
Test status
Simulation time 59707449 ps
CPU time 0.78 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:44:52 PM PDT 24
Peak memory 200728 kb
Host smart-d21613aa-2fa0-42ee-9744-55231d2871dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715924287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3715924287
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1054944992
Short name T288
Test name
Test status
Simulation time 1227538409 ps
CPU time 5.66 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:45:01 PM PDT 24
Peak memory 222600 kb
Host smart-a0a8853c-1a2c-46d1-9d96-6235954f3d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054944992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1054944992
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1033271454
Short name T255
Test name
Test status
Simulation time 244736829 ps
CPU time 1.12 seconds
Started Mar 19 02:44:56 PM PDT 24
Finished Mar 19 02:44:57 PM PDT 24
Peak memory 218216 kb
Host smart-a97c79bc-859b-44e0-8bed-f8da6aac02af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033271454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1033271454
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3979317047
Short name T202
Test name
Test status
Simulation time 156492431 ps
CPU time 0.83 seconds
Started Mar 19 02:44:50 PM PDT 24
Finished Mar 19 02:44:52 PM PDT 24
Peak memory 200688 kb
Host smart-a529d64e-0dd4-4bc5-82e8-0814cdd6ce16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979317047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3979317047
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2917978
Short name T130
Test name
Test status
Simulation time 1973426127 ps
CPU time 7.62 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:45:03 PM PDT 24
Peak memory 201044 kb
Host smart-b507a4e2-244a-4438-94dc-7d3dd6ec854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2917978
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2056718651
Short name T78
Test name
Test status
Simulation time 8358347229 ps
CPU time 13.32 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:45:07 PM PDT 24
Peak memory 217988 kb
Host smart-9d02106d-9627-4a1b-b373-fa52d395b65e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056718651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2056718651
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3991799751
Short name T268
Test name
Test status
Simulation time 141539714 ps
CPU time 1.12 seconds
Started Mar 19 02:44:50 PM PDT 24
Finished Mar 19 02:44:52 PM PDT 24
Peak memory 200880 kb
Host smart-3d4eca3a-4b76-4796-9771-0559facd8889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991799751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3991799751
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.522526481
Short name T24
Test name
Test status
Simulation time 207531648 ps
CPU time 1.43 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 201080 kb
Host smart-52a2c2dc-039a-4a88-a77b-64364b76816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522526481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.522526481
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3674894597
Short name T279
Test name
Test status
Simulation time 6155705647 ps
CPU time 28.44 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:45:23 PM PDT 24
Peak memory 201208 kb
Host smart-4ff2d22b-b90f-4087-bb1a-5c5c729ac377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674894597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3674894597
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.670952452
Short name T219
Test name
Test status
Simulation time 145153867 ps
CPU time 1.85 seconds
Started Mar 19 02:44:52 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 209052 kb
Host smart-fe7ffbaf-8902-41fa-a232-5c55e21d22a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670952452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.670952452
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3741907157
Short name T465
Test name
Test status
Simulation time 215192121 ps
CPU time 1.3 seconds
Started Mar 19 02:44:52 PM PDT 24
Finished Mar 19 02:44:53 PM PDT 24
Peak memory 200912 kb
Host smart-661c2991-904b-4b31-9cb2-0caed9d541e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741907157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3741907157
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.188708290
Short name T469
Test name
Test status
Simulation time 75440246 ps
CPU time 0.82 seconds
Started Mar 19 02:45:10 PM PDT 24
Finished Mar 19 02:45:11 PM PDT 24
Peak memory 200768 kb
Host smart-e7421e24-3598-4dd3-b58b-58defd9a26a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188708290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.188708290
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.989152826
Short name T31
Test name
Test status
Simulation time 1230298134 ps
CPU time 5.7 seconds
Started Mar 19 02:45:06 PM PDT 24
Finished Mar 19 02:45:12 PM PDT 24
Peak memory 218548 kb
Host smart-75e00da3-c498-41b5-934b-2e47762a4aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989152826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.989152826
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3981631749
Short name T285
Test name
Test status
Simulation time 244157699 ps
CPU time 1.1 seconds
Started Mar 19 02:45:09 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 218168 kb
Host smart-e8d58458-ca27-4edb-a9d9-0efc0319a8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981631749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3981631749
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.302597486
Short name T320
Test name
Test status
Simulation time 174448963 ps
CPU time 0.83 seconds
Started Mar 19 02:45:09 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 200764 kb
Host smart-a5f6b845-1d67-41df-bd21-27f09e018d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302597486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.302597486
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3371773213
Short name T209
Test name
Test status
Simulation time 1021865771 ps
CPU time 5.06 seconds
Started Mar 19 02:45:11 PM PDT 24
Finished Mar 19 02:45:17 PM PDT 24
Peak memory 201032 kb
Host smart-163fc19e-3b03-44af-a3e5-b0b55fd12124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371773213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3371773213
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3398396280
Short name T398
Test name
Test status
Simulation time 192365718 ps
CPU time 1.45 seconds
Started Mar 19 02:45:13 PM PDT 24
Finished Mar 19 02:45:15 PM PDT 24
Peak memory 201128 kb
Host smart-b93fd7a6-c882-45ac-ad87-fd1f73895418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398396280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3398396280
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3344664741
Short name T132
Test name
Test status
Simulation time 11433090049 ps
CPU time 41.88 seconds
Started Mar 19 02:45:10 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 201172 kb
Host smart-b8e58e66-80c2-4fbb-96b4-d7c63989aba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344664741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3344664741
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1202189083
Short name T206
Test name
Test status
Simulation time 319483940 ps
CPU time 2.29 seconds
Started Mar 19 02:45:11 PM PDT 24
Finished Mar 19 02:45:14 PM PDT 24
Peak memory 209144 kb
Host smart-32b8237d-7607-4fe5-92ed-daa9b88fbd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202189083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1202189083
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2211015837
Short name T179
Test name
Test status
Simulation time 82739655 ps
CPU time 0.91 seconds
Started Mar 19 02:45:12 PM PDT 24
Finished Mar 19 02:45:13 PM PDT 24
Peak memory 200864 kb
Host smart-4a7f3675-c7fc-4864-8c2f-1aea31546ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211015837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2211015837
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3189992696
Short name T257
Test name
Test status
Simulation time 63781408 ps
CPU time 0.73 seconds
Started Mar 19 02:45:21 PM PDT 24
Finished Mar 19 02:45:22 PM PDT 24
Peak memory 200784 kb
Host smart-8d1c7df7-be3e-4f17-9289-76bcba94f920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189992696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3189992696
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2159621650
Short name T45
Test name
Test status
Simulation time 1220543905 ps
CPU time 5.92 seconds
Started Mar 19 02:45:10 PM PDT 24
Finished Mar 19 02:45:16 PM PDT 24
Peak memory 222644 kb
Host smart-4e60186f-823f-46d9-a654-6863030f530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159621650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2159621650
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3898877252
Short name T195
Test name
Test status
Simulation time 144958226 ps
CPU time 0.85 seconds
Started Mar 19 02:45:09 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 200716 kb
Host smart-f915c795-35d5-4fc0-8bbf-dd3c4c40eb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898877252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3898877252
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2443277577
Short name T377
Test name
Test status
Simulation time 1871122202 ps
CPU time 7.43 seconds
Started Mar 19 02:45:12 PM PDT 24
Finished Mar 19 02:45:20 PM PDT 24
Peak memory 201056 kb
Host smart-69bda3ac-252f-405b-a6ee-963bd01de754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443277577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2443277577
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3635459369
Short name T148
Test name
Test status
Simulation time 103616819 ps
CPU time 1.08 seconds
Started Mar 19 02:45:11 PM PDT 24
Finished Mar 19 02:45:12 PM PDT 24
Peak memory 200856 kb
Host smart-6d30cb1a-fcfa-45cb-b9c4-f52c0b37c29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635459369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3635459369
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2177120616
Short name T479
Test name
Test status
Simulation time 109772922 ps
CPU time 1.17 seconds
Started Mar 19 02:45:10 PM PDT 24
Finished Mar 19 02:45:11 PM PDT 24
Peak memory 201144 kb
Host smart-5a146bf6-20cb-4f59-a49f-04e54c03a64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177120616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2177120616
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1709554466
Short name T61
Test name
Test status
Simulation time 1830422537 ps
CPU time 8.44 seconds
Started Mar 19 02:45:27 PM PDT 24
Finished Mar 19 02:45:35 PM PDT 24
Peak memory 201072 kb
Host smart-36e1dbe3-402b-4ab8-9208-71805d17842b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709554466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1709554466
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3383976073
Short name T510
Test name
Test status
Simulation time 554914336 ps
CPU time 3.19 seconds
Started Mar 19 02:45:13 PM PDT 24
Finished Mar 19 02:45:17 PM PDT 24
Peak memory 200956 kb
Host smart-85c10a56-bff9-4ad7-bd59-0daf39ccf269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383976073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3383976073
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1985459510
Short name T9
Test name
Test status
Simulation time 193483312 ps
CPU time 1.33 seconds
Started Mar 19 02:45:10 PM PDT 24
Finished Mar 19 02:45:12 PM PDT 24
Peak memory 200904 kb
Host smart-4d767dee-b23e-4d6e-aa69-0a052082e4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985459510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1985459510
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1433265018
Short name T252
Test name
Test status
Simulation time 73485856 ps
CPU time 0.78 seconds
Started Mar 19 02:45:18 PM PDT 24
Finished Mar 19 02:45:19 PM PDT 24
Peak memory 200780 kb
Host smart-cedd9e35-aafc-4f85-ba89-00f8a07ffd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433265018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1433265018
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3001471347
Short name T424
Test name
Test status
Simulation time 1228088171 ps
CPU time 5.66 seconds
Started Mar 19 02:45:17 PM PDT 24
Finished Mar 19 02:45:23 PM PDT 24
Peak memory 222652 kb
Host smart-e792d280-5890-4502-b0aa-4b3f4cee8c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001471347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3001471347
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3460556863
Short name T55
Test name
Test status
Simulation time 245776955 ps
CPU time 1.08 seconds
Started Mar 19 02:45:18 PM PDT 24
Finished Mar 19 02:45:19 PM PDT 24
Peak memory 218148 kb
Host smart-d0b1ccc9-7af1-429f-9470-cee4ffea2ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460556863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3460556863
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2699745433
Short name T369
Test name
Test status
Simulation time 109398793 ps
CPU time 0.77 seconds
Started Mar 19 02:45:22 PM PDT 24
Finished Mar 19 02:45:23 PM PDT 24
Peak memory 200756 kb
Host smart-fb2d56f1-6f83-411d-bec2-f61b34117997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699745433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2699745433
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1252108944
Short name T189
Test name
Test status
Simulation time 1100174338 ps
CPU time 5.34 seconds
Started Mar 19 02:45:17 PM PDT 24
Finished Mar 19 02:45:22 PM PDT 24
Peak memory 201068 kb
Host smart-9c35fa72-51cb-48d1-9781-dbf74d2d0ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252108944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1252108944
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2282827494
Short name T485
Test name
Test status
Simulation time 99191643 ps
CPU time 1.03 seconds
Started Mar 19 02:45:22 PM PDT 24
Finished Mar 19 02:45:23 PM PDT 24
Peak memory 200912 kb
Host smart-2a9c72f3-913d-4e4d-b4e2-d4c172f5108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282827494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2282827494
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1723945259
Short name T284
Test name
Test status
Simulation time 110702699 ps
CPU time 1.24 seconds
Started Mar 19 02:45:18 PM PDT 24
Finished Mar 19 02:45:19 PM PDT 24
Peak memory 201088 kb
Host smart-cb6d9698-f0d5-494b-a2ac-1cc425d6d61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723945259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1723945259
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1809883959
Short name T207
Test name
Test status
Simulation time 2271130032 ps
CPU time 9.94 seconds
Started Mar 19 02:45:15 PM PDT 24
Finished Mar 19 02:45:26 PM PDT 24
Peak memory 209428 kb
Host smart-1632c609-e977-4d71-9a64-0f8d920959ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809883959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1809883959
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2998086011
Short name T23
Test name
Test status
Simulation time 326778299 ps
CPU time 2.19 seconds
Started Mar 19 02:45:24 PM PDT 24
Finished Mar 19 02:45:27 PM PDT 24
Peak memory 200940 kb
Host smart-ac2cfd9e-b85d-477d-b272-aab6d6182f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998086011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2998086011
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1045077999
Short name T344
Test name
Test status
Simulation time 183897764 ps
CPU time 1.29 seconds
Started Mar 19 02:45:22 PM PDT 24
Finished Mar 19 02:45:23 PM PDT 24
Peak memory 200856 kb
Host smart-1122563d-da2a-4797-9843-91817eca1a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045077999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1045077999
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1137113498
Short name T260
Test name
Test status
Simulation time 98689585 ps
CPU time 0.9 seconds
Started Mar 19 02:45:22 PM PDT 24
Finished Mar 19 02:45:23 PM PDT 24
Peak memory 200744 kb
Host smart-0f5531b4-5ba6-477b-b049-41874f76eced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137113498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1137113498
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3360437627
Short name T30
Test name
Test status
Simulation time 1220999955 ps
CPU time 5.92 seconds
Started Mar 19 02:45:27 PM PDT 24
Finished Mar 19 02:45:33 PM PDT 24
Peak memory 218576 kb
Host smart-af10993d-e47d-4912-b8c0-368a731cc1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360437627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3360437627
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3876684365
Short name T170
Test name
Test status
Simulation time 244660710 ps
CPU time 1.05 seconds
Started Mar 19 02:45:22 PM PDT 24
Finished Mar 19 02:45:23 PM PDT 24
Peak memory 218184 kb
Host smart-0de8bbf7-6f3a-4e67-b61b-4c83f26cf9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876684365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3876684365
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2965177888
Short name T103
Test name
Test status
Simulation time 757580114 ps
CPU time 4.14 seconds
Started Mar 19 02:45:18 PM PDT 24
Finished Mar 19 02:45:22 PM PDT 24
Peak memory 201112 kb
Host smart-53f47988-e094-4280-8515-005d747ece50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965177888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2965177888
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.975490277
Short name T349
Test name
Test status
Simulation time 179831566 ps
CPU time 1.27 seconds
Started Mar 19 02:45:17 PM PDT 24
Finished Mar 19 02:45:19 PM PDT 24
Peak memory 200864 kb
Host smart-89647a33-98fe-42d1-9ede-4b562a0c9082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975490277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.975490277
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3887547406
Short name T399
Test name
Test status
Simulation time 195776204 ps
CPU time 1.5 seconds
Started Mar 19 02:45:25 PM PDT 24
Finished Mar 19 02:45:27 PM PDT 24
Peak memory 201080 kb
Host smart-60aba2d6-0c83-484c-ad12-b7dbf111ab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887547406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3887547406
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2616208560
Short name T10
Test name
Test status
Simulation time 5236609216 ps
CPU time 25.3 seconds
Started Mar 19 02:45:18 PM PDT 24
Finished Mar 19 02:45:44 PM PDT 24
Peak memory 209920 kb
Host smart-7276ff64-f9c6-4207-8ba7-73424ff18c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616208560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2616208560
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1985462592
Short name T227
Test name
Test status
Simulation time 446613140 ps
CPU time 2.51 seconds
Started Mar 19 02:45:23 PM PDT 24
Finished Mar 19 02:45:25 PM PDT 24
Peak memory 200896 kb
Host smart-e846315b-0854-4272-badf-67d3a418fa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985462592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1985462592
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2968974801
Short name T425
Test name
Test status
Simulation time 106775428 ps
CPU time 0.93 seconds
Started Mar 19 02:45:21 PM PDT 24
Finished Mar 19 02:45:22 PM PDT 24
Peak memory 200856 kb
Host smart-0d425cd4-4187-4981-a169-f3f06af014e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968974801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2968974801
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2017325885
Short name T240
Test name
Test status
Simulation time 82857973 ps
CPU time 0.79 seconds
Started Mar 19 02:45:29 PM PDT 24
Finished Mar 19 02:45:30 PM PDT 24
Peak memory 200736 kb
Host smart-f126abfa-ec24-4e4c-9eb9-909da872c862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017325885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2017325885
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.9322035
Short name T54
Test name
Test status
Simulation time 1225910462 ps
CPU time 5.68 seconds
Started Mar 19 02:45:30 PM PDT 24
Finished Mar 19 02:45:35 PM PDT 24
Peak memory 218392 kb
Host smart-16fd8018-384c-44be-8cb6-5405b973bd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9322035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.9322035
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.757563846
Short name T383
Test name
Test status
Simulation time 244122882 ps
CPU time 1.14 seconds
Started Mar 19 02:45:27 PM PDT 24
Finished Mar 19 02:45:28 PM PDT 24
Peak memory 218176 kb
Host smart-e0311267-8797-4819-87c6-8e112deda123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757563846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.757563846
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3564605751
Short name T362
Test name
Test status
Simulation time 121283340 ps
CPU time 0.78 seconds
Started Mar 19 02:45:24 PM PDT 24
Finished Mar 19 02:45:25 PM PDT 24
Peak memory 200756 kb
Host smart-af7da409-a79a-43be-a567-264779be0c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564605751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3564605751
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2636102203
Short name T110
Test name
Test status
Simulation time 911203319 ps
CPU time 4.95 seconds
Started Mar 19 02:45:26 PM PDT 24
Finished Mar 19 02:45:31 PM PDT 24
Peak memory 201072 kb
Host smart-59ba7631-8c80-4746-af11-fdf683579977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636102203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2636102203
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.60411479
Short name T188
Test name
Test status
Simulation time 148490522 ps
CPU time 1.19 seconds
Started Mar 19 02:45:26 PM PDT 24
Finished Mar 19 02:45:27 PM PDT 24
Peak memory 200868 kb
Host smart-c45e6465-27e1-4073-91a1-520988609805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60411479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.60411479
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3151703723
Short name T337
Test name
Test status
Simulation time 233661727 ps
CPU time 1.58 seconds
Started Mar 19 02:45:30 PM PDT 24
Finished Mar 19 02:45:31 PM PDT 24
Peak memory 201044 kb
Host smart-2397bf68-72ec-4f6d-a187-c5cb7c38cebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151703723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3151703723
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.783214860
Short name T446
Test name
Test status
Simulation time 190784128 ps
CPU time 1.34 seconds
Started Mar 19 02:45:25 PM PDT 24
Finished Mar 19 02:45:26 PM PDT 24
Peak memory 201044 kb
Host smart-95a994c5-ca71-4d9d-a9b8-3e45218fd7a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783214860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.783214860
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2571211828
Short name T358
Test name
Test status
Simulation time 318321621 ps
CPU time 2.27 seconds
Started Mar 19 02:45:24 PM PDT 24
Finished Mar 19 02:45:26 PM PDT 24
Peak memory 209152 kb
Host smart-f5ae9590-293c-4839-bd8f-b6afc85e2638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571211828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2571211828
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.915350296
Short name T483
Test name
Test status
Simulation time 138076407 ps
CPU time 1.14 seconds
Started Mar 19 02:45:27 PM PDT 24
Finished Mar 19 02:45:28 PM PDT 24
Peak memory 200872 kb
Host smart-7f25f145-868b-480d-b6db-06a98a9ec0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915350296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.915350296
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1519294161
Short name T165
Test name
Test status
Simulation time 65275987 ps
CPU time 0.79 seconds
Started Mar 19 02:45:27 PM PDT 24
Finished Mar 19 02:45:28 PM PDT 24
Peak memory 200748 kb
Host smart-8b27cf52-d2f8-4529-a298-097d8b9b7a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519294161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1519294161
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2671626721
Short name T417
Test name
Test status
Simulation time 1896833713 ps
CPU time 8.04 seconds
Started Mar 19 02:45:30 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 218616 kb
Host smart-c99e45ed-62c7-449e-8210-9f5affd5c6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671626721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2671626721
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2691113170
Short name T438
Test name
Test status
Simulation time 244541324 ps
CPU time 1.11 seconds
Started Mar 19 02:45:27 PM PDT 24
Finished Mar 19 02:45:28 PM PDT 24
Peak memory 218212 kb
Host smart-0b36f9de-2dca-4606-a0ef-04f8c1c2b2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691113170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2691113170
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2921488016
Short name T532
Test name
Test status
Simulation time 198359690 ps
CPU time 1.04 seconds
Started Mar 19 02:45:27 PM PDT 24
Finished Mar 19 02:45:29 PM PDT 24
Peak memory 200740 kb
Host smart-cefa92da-a0ae-4a8e-aa9b-6edcf7117d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921488016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2921488016
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1746980260
Short name T461
Test name
Test status
Simulation time 716370470 ps
CPU time 3.81 seconds
Started Mar 19 02:45:25 PM PDT 24
Finished Mar 19 02:45:29 PM PDT 24
Peak memory 201052 kb
Host smart-9a4df50f-375c-49db-82e8-ff448175cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746980260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1746980260
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4273836323
Short name T371
Test name
Test status
Simulation time 97029436 ps
CPU time 1.03 seconds
Started Mar 19 02:45:26 PM PDT 24
Finished Mar 19 02:45:27 PM PDT 24
Peak memory 200904 kb
Host smart-d9d88c68-c9df-4060-871c-700bcadecd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273836323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4273836323
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3243563639
Short name T281
Test name
Test status
Simulation time 117279710 ps
CPU time 1.19 seconds
Started Mar 19 02:45:24 PM PDT 24
Finished Mar 19 02:45:25 PM PDT 24
Peak memory 200992 kb
Host smart-a9af92cf-c89e-4a1e-a5c0-62c2768651c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243563639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3243563639
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.4263997249
Short name T380
Test name
Test status
Simulation time 11329875943 ps
CPU time 38.11 seconds
Started Mar 19 02:45:25 PM PDT 24
Finished Mar 19 02:46:03 PM PDT 24
Peak memory 211004 kb
Host smart-a0e31389-884a-4cce-81ac-37990bbac56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263997249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.4263997249
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.4234189086
Short name T226
Test name
Test status
Simulation time 124484790 ps
CPU time 1.75 seconds
Started Mar 19 02:45:25 PM PDT 24
Finished Mar 19 02:45:27 PM PDT 24
Peak memory 209148 kb
Host smart-55dc7fc6-06ed-4774-8b2b-0140af25172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234189086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.4234189086
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2411423292
Short name T39
Test name
Test status
Simulation time 68707985 ps
CPU time 0.76 seconds
Started Mar 19 02:45:25 PM PDT 24
Finished Mar 19 02:45:25 PM PDT 24
Peak memory 200892 kb
Host smart-ee09dff3-4328-46ee-bfba-378c9741c808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411423292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2411423292
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.689922449
Short name T484
Test name
Test status
Simulation time 133446758 ps
CPU time 0.92 seconds
Started Mar 19 02:45:40 PM PDT 24
Finished Mar 19 02:45:41 PM PDT 24
Peak memory 200728 kb
Host smart-2e6e897b-4e28-4a9f-a780-7765110e3848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689922449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.689922449
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1495665577
Short name T427
Test name
Test status
Simulation time 1229544684 ps
CPU time 5.67 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:45:43 PM PDT 24
Peak memory 218564 kb
Host smart-0b1ba989-31c3-427a-8ffe-5b3ded52f50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495665577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1495665577
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2472436660
Short name T184
Test name
Test status
Simulation time 245539937 ps
CPU time 1.06 seconds
Started Mar 19 02:45:39 PM PDT 24
Finished Mar 19 02:45:41 PM PDT 24
Peak memory 218148 kb
Host smart-7bd53549-c27c-497c-bfc4-f2fd6b54c64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472436660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2472436660
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2082251288
Short name T293
Test name
Test status
Simulation time 95234902 ps
CPU time 0.74 seconds
Started Mar 19 02:45:25 PM PDT 24
Finished Mar 19 02:45:26 PM PDT 24
Peak memory 200680 kb
Host smart-91070fcc-6e4e-49ac-850a-b7e1d53d8c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082251288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2082251288
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.642227758
Short name T365
Test name
Test status
Simulation time 1213744573 ps
CPU time 5.36 seconds
Started Mar 19 02:45:24 PM PDT 24
Finished Mar 19 02:45:30 PM PDT 24
Peak memory 201032 kb
Host smart-a62e4707-78d3-44e4-bada-b680149de5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642227758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.642227758
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.972769054
Short name T196
Test name
Test status
Simulation time 97703703 ps
CPU time 1.05 seconds
Started Mar 19 02:45:39 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 200864 kb
Host smart-ac34bdd1-ac71-4717-b146-5f83bc10311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972769054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.972769054
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1601565088
Short name T194
Test name
Test status
Simulation time 197571228 ps
CPU time 1.49 seconds
Started Mar 19 02:45:26 PM PDT 24
Finished Mar 19 02:45:28 PM PDT 24
Peak memory 201032 kb
Host smart-f7992099-e1f9-4b55-b5fc-f9542f89f2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601565088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1601565088
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2616625820
Short name T109
Test name
Test status
Simulation time 1043379581 ps
CPU time 4.99 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:43 PM PDT 24
Peak memory 201068 kb
Host smart-a31819a7-0467-4d37-a990-9d36cb3fd5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616625820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2616625820
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2541855105
Short name T476
Test name
Test status
Simulation time 371569337 ps
CPU time 2.56 seconds
Started Mar 19 02:45:36 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 200940 kb
Host smart-9dfb447d-d137-4cfb-9410-3fccb24a4366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541855105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2541855105
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3037704176
Short name T173
Test name
Test status
Simulation time 252898124 ps
CPU time 1.49 seconds
Started Mar 19 02:45:25 PM PDT 24
Finished Mar 19 02:45:27 PM PDT 24
Peak memory 200936 kb
Host smart-d75bd7d0-b5dc-4307-ad34-9122ab67275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037704176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3037704176
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3654582293
Short name T539
Test name
Test status
Simulation time 63286025 ps
CPU time 0.79 seconds
Started Mar 19 02:45:43 PM PDT 24
Finished Mar 19 02:45:44 PM PDT 24
Peak memory 200744 kb
Host smart-547c6368-c20a-41b3-9c19-310a4df65d0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654582293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3654582293
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3938959264
Short name T346
Test name
Test status
Simulation time 1235701472 ps
CPU time 5.62 seconds
Started Mar 19 02:45:40 PM PDT 24
Finished Mar 19 02:45:45 PM PDT 24
Peak memory 222576 kb
Host smart-5843a21d-6ab5-4a82-8b32-d38223b1a885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938959264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3938959264
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3857193119
Short name T294
Test name
Test status
Simulation time 244617544 ps
CPU time 1.01 seconds
Started Mar 19 02:45:40 PM PDT 24
Finished Mar 19 02:45:41 PM PDT 24
Peak memory 218188 kb
Host smart-21a3036e-b056-47ae-bafe-8e1421cc53c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857193119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3857193119
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2788437692
Short name T20
Test name
Test status
Simulation time 74989182 ps
CPU time 0.75 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 200740 kb
Host smart-b5fb8a8b-d1a0-4503-a378-02976d499ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788437692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2788437692
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1583253199
Short name T512
Test name
Test status
Simulation time 759961106 ps
CPU time 4.26 seconds
Started Mar 19 02:45:45 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 201096 kb
Host smart-988927ab-dd3b-46f2-93db-fc42a48c532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583253199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1583253199
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2177729753
Short name T423
Test name
Test status
Simulation time 168666611 ps
CPU time 1.15 seconds
Started Mar 19 02:45:40 PM PDT 24
Finished Mar 19 02:45:41 PM PDT 24
Peak memory 200872 kb
Host smart-83fef229-16af-4727-91a0-617a199fa840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177729753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2177729753
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.682018810
Short name T216
Test name
Test status
Simulation time 228746347 ps
CPU time 1.49 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 201100 kb
Host smart-8505b918-7761-4394-9206-4b77939cf9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682018810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.682018810
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3201024509
Short name T324
Test name
Test status
Simulation time 12855806952 ps
CPU time 43.49 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 209404 kb
Host smart-f417ea4d-16ed-4194-a98c-18fb4162605e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201024509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3201024509
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1700733133
Short name T212
Test name
Test status
Simulation time 118444547 ps
CPU time 1.51 seconds
Started Mar 19 02:45:36 PM PDT 24
Finished Mar 19 02:45:37 PM PDT 24
Peak memory 200912 kb
Host smart-e39c310d-a47b-41ca-bbab-e4c498208d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700733133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1700733133
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3199687372
Short name T355
Test name
Test status
Simulation time 233319983 ps
CPU time 1.36 seconds
Started Mar 19 02:45:36 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 201044 kb
Host smart-d5b5f6fd-a92b-4e95-96eb-bc7294828809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199687372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3199687372
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2442989116
Short name T332
Test name
Test status
Simulation time 71192751 ps
CPU time 0.77 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 200744 kb
Host smart-c20c3e9e-740e-446c-b2b6-e6a7d09795d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442989116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2442989116
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3417990465
Short name T466
Test name
Test status
Simulation time 1225705073 ps
CPU time 5.96 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:45:43 PM PDT 24
Peak memory 218004 kb
Host smart-c80a8de7-4d58-4ec5-a160-74ff6ed79259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417990465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3417990465
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1861516924
Short name T191
Test name
Test status
Simulation time 245616770 ps
CPU time 1.04 seconds
Started Mar 19 02:45:39 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 218324 kb
Host smart-3bac02ee-6610-4776-ac6b-2b67f11018e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861516924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1861516924
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1882179235
Short name T496
Test name
Test status
Simulation time 155023935 ps
CPU time 0.83 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 200664 kb
Host smart-216544ff-7c3f-4ad7-a875-e0e4d5fde4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882179235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1882179235
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1757882240
Short name T108
Test name
Test status
Simulation time 961623600 ps
CPU time 5.48 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:44 PM PDT 24
Peak memory 201044 kb
Host smart-3bb2dd31-05bd-4f9a-90b9-45563f942ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757882240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1757882240
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1001560563
Short name T146
Test name
Test status
Simulation time 159780599 ps
CPU time 1.16 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 200912 kb
Host smart-c4e6e001-bcb0-4430-8d68-30c0161f3a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001560563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1001560563
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2864659267
Short name T134
Test name
Test status
Simulation time 258994753 ps
CPU time 1.67 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 201088 kb
Host smart-526da227-f3bb-4b64-ba7c-61e7efba9a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864659267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2864659267
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2108065105
Short name T296
Test name
Test status
Simulation time 3068514683 ps
CPU time 15.41 seconds
Started Mar 19 02:45:36 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 209408 kb
Host smart-28085cf8-662a-43ef-856a-e50cf684ae80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108065105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2108065105
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1860238319
Short name T326
Test name
Test status
Simulation time 441278665 ps
CPU time 2.61 seconds
Started Mar 19 02:45:36 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 209144 kb
Host smart-d1892306-5745-440b-a11f-c88bc8f8ef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860238319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1860238319
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.4224776674
Short name T230
Test name
Test status
Simulation time 138531311 ps
CPU time 1.19 seconds
Started Mar 19 02:45:45 PM PDT 24
Finished Mar 19 02:45:47 PM PDT 24
Peak memory 200860 kb
Host smart-b29c2be0-6a7e-4819-8df4-22fad00b06cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224776674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4224776674
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3801637654
Short name T442
Test name
Test status
Simulation time 64610981 ps
CPU time 0.76 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 200740 kb
Host smart-2f2cf57a-4797-431a-ab69-a595f62502c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801637654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3801637654
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.192716231
Short name T422
Test name
Test status
Simulation time 2367966061 ps
CPU time 9.57 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:47 PM PDT 24
Peak memory 218624 kb
Host smart-d4a21353-fae9-4e69-9c23-a3c5ddc01452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192716231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.192716231
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.377537912
Short name T60
Test name
Test status
Simulation time 244284972 ps
CPU time 1.16 seconds
Started Mar 19 02:45:36 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 218328 kb
Host smart-b3bdf247-b35a-40d3-87d5-8c2dede6766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377537912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.377537912
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1302329431
Short name T254
Test name
Test status
Simulation time 134485281 ps
CPU time 0.81 seconds
Started Mar 19 02:45:39 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 200776 kb
Host smart-c8ec9db7-8324-40b0-b8b8-75b87b166d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302329431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1302329431
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3631586751
Short name T198
Test name
Test status
Simulation time 1279797219 ps
CPU time 5.04 seconds
Started Mar 19 02:45:35 PM PDT 24
Finished Mar 19 02:45:41 PM PDT 24
Peak memory 201096 kb
Host smart-29c103ab-da0b-4787-866d-dda6ede0d258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631586751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3631586751
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1662340302
Short name T419
Test name
Test status
Simulation time 111124432 ps
CPU time 0.97 seconds
Started Mar 19 02:45:43 PM PDT 24
Finished Mar 19 02:45:44 PM PDT 24
Peak memory 200908 kb
Host smart-20f90d35-8b84-456f-8a0f-9f3969a19cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662340302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1662340302
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.800639574
Short name T138
Test name
Test status
Simulation time 256033273 ps
CPU time 1.64 seconds
Started Mar 19 02:45:48 PM PDT 24
Finished Mar 19 02:45:49 PM PDT 24
Peak memory 201032 kb
Host smart-ec4c68f2-8f1a-4027-b05b-10be58ea5b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800639574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.800639574
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2930134953
Short name T205
Test name
Test status
Simulation time 1139947367 ps
CPU time 5.85 seconds
Started Mar 19 02:45:40 PM PDT 24
Finished Mar 19 02:45:46 PM PDT 24
Peak memory 209252 kb
Host smart-c870c53d-ab33-40c9-a354-e0390a2c9977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930134953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2930134953
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4061745903
Short name T171
Test name
Test status
Simulation time 365780404 ps
CPU time 2.53 seconds
Started Mar 19 02:45:36 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 200952 kb
Host smart-861a210d-48c7-4939-8e0a-08faffa9ac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061745903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4061745903
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.449571999
Short name T436
Test name
Test status
Simulation time 213496611 ps
CPU time 1.28 seconds
Started Mar 19 02:45:46 PM PDT 24
Finished Mar 19 02:45:47 PM PDT 24
Peak memory 200896 kb
Host smart-95885827-e68f-40c4-8191-3d6f892ba393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449571999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.449571999
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3968783978
Short name T185
Test name
Test status
Simulation time 245408801 ps
CPU time 1.12 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 218112 kb
Host smart-c9d80259-2a4f-452d-b3fd-f3f4808c8ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968783978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3968783978
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1833836870
Short name T241
Test name
Test status
Simulation time 201147862 ps
CPU time 0.94 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:44:53 PM PDT 24
Peak memory 200768 kb
Host smart-13435e93-4acb-48c1-bda1-6eced12d5fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833836870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1833836870
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2073740443
Short name T392
Test name
Test status
Simulation time 2054290094 ps
CPU time 7.17 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:45:02 PM PDT 24
Peak memory 201036 kb
Host smart-45767605-95b7-4fe7-873a-5e14d68a361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073740443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2073740443
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.322184711
Short name T74
Test name
Test status
Simulation time 17333258653 ps
CPU time 25.02 seconds
Started Mar 19 02:44:50 PM PDT 24
Finished Mar 19 02:45:16 PM PDT 24
Peak memory 218452 kb
Host smart-b8f303b1-f449-4bc1-a468-282547c26831
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322184711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.322184711
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.388366387
Short name T376
Test name
Test status
Simulation time 102954743 ps
CPU time 1.03 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 200804 kb
Host smart-aafeafe9-1420-432e-83e5-10a9e6f5f97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388366387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.388366387
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.923298792
Short name T301
Test name
Test status
Simulation time 219240721 ps
CPU time 1.43 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 201080 kb
Host smart-ee7112a8-3034-4a56-97b6-7f219b1b493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923298792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.923298792
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1435927865
Short name T378
Test name
Test status
Simulation time 9184945433 ps
CPU time 34.27 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:45:25 PM PDT 24
Peak memory 209400 kb
Host smart-6789abc0-8c50-4d16-8b67-8c8d485dc826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435927865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1435927865
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2536792822
Short name T181
Test name
Test status
Simulation time 149109111 ps
CPU time 1.21 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 200916 kb
Host smart-24b8c86a-4b6c-43da-a0fb-db70c78305ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536792822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2536792822
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3266388974
Short name T342
Test name
Test status
Simulation time 73611095 ps
CPU time 0.82 seconds
Started Mar 19 02:45:41 PM PDT 24
Finished Mar 19 02:45:42 PM PDT 24
Peak memory 200772 kb
Host smart-fa865421-647f-44c0-82a4-5b616c89dde5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266388974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3266388974
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2498700948
Short name T304
Test name
Test status
Simulation time 1221155781 ps
CPU time 5.48 seconds
Started Mar 19 02:45:41 PM PDT 24
Finished Mar 19 02:45:46 PM PDT 24
Peak memory 218560 kb
Host smart-91ddcaba-0816-43e5-982e-0cf3f063c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498700948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2498700948
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1109165997
Short name T314
Test name
Test status
Simulation time 245000076 ps
CPU time 1.07 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 218164 kb
Host smart-5d817e9f-d899-415f-9537-81f72acc1506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109165997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1109165997
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2886805761
Short name T493
Test name
Test status
Simulation time 194578120 ps
CPU time 0.99 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 200740 kb
Host smart-c9e0fb36-f838-49a2-8b78-efae5a53f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886805761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2886805761
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3879375966
Short name T397
Test name
Test status
Simulation time 1608709981 ps
CPU time 7 seconds
Started Mar 19 02:45:39 PM PDT 24
Finished Mar 19 02:45:46 PM PDT 24
Peak memory 201028 kb
Host smart-04657379-13e9-4ab0-a143-82289d6b0384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879375966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3879375966
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.967323610
Short name T229
Test name
Test status
Simulation time 102487766 ps
CPU time 1.03 seconds
Started Mar 19 02:45:40 PM PDT 24
Finished Mar 19 02:45:41 PM PDT 24
Peak memory 200908 kb
Host smart-6b6ae8bf-4783-4720-b048-91244fed7921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967323610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.967323610
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.61074593
Short name T172
Test name
Test status
Simulation time 122573026 ps
CPU time 1.27 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 201092 kb
Host smart-368501b6-238c-4a43-aeb5-715f6c6e7836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61074593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.61074593
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2163096057
Short name T467
Test name
Test status
Simulation time 1397626197 ps
CPU time 7.41 seconds
Started Mar 19 02:45:40 PM PDT 24
Finished Mar 19 02:45:47 PM PDT 24
Peak memory 209244 kb
Host smart-147c714b-a332-4e7d-957d-c443ef988223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163096057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2163096057
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2029677778
Short name T428
Test name
Test status
Simulation time 314158058 ps
CPU time 1.99 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 209136 kb
Host smart-9af42b38-1f50-4dfd-b444-c291b8e95021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029677778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2029677778
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2844117087
Short name T180
Test name
Test status
Simulation time 89949716 ps
CPU time 0.85 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 200904 kb
Host smart-3e293371-cdac-4626-8961-1a9c8afb5b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844117087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2844117087
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2982899995
Short name T340
Test name
Test status
Simulation time 71871847 ps
CPU time 0.79 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 200644 kb
Host smart-07a0e75d-1d34-4ded-bfa1-7088bbf3bd3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982899995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2982899995
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1230524457
Short name T278
Test name
Test status
Simulation time 1228743327 ps
CPU time 5.79 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:45:43 PM PDT 24
Peak memory 222628 kb
Host smart-e457c477-66c0-4ce1-96d1-271249dfe717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230524457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1230524457
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3590079909
Short name T411
Test name
Test status
Simulation time 244280781 ps
CPU time 1.11 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 218136 kb
Host smart-7f7c1668-6eac-412e-bb37-e5c99d88acad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590079909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3590079909
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1872961852
Short name T81
Test name
Test status
Simulation time 196897463 ps
CPU time 0.87 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:45:38 PM PDT 24
Peak memory 200756 kb
Host smart-b0c6fb24-5f2b-462d-8b9c-6dc166727326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872961852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1872961852
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.476597262
Short name T527
Test name
Test status
Simulation time 1105870216 ps
CPU time 5.25 seconds
Started Mar 19 02:45:39 PM PDT 24
Finished Mar 19 02:45:45 PM PDT 24
Peak memory 201100 kb
Host smart-bb97929c-dd68-46ed-8321-1168067c5fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476597262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.476597262
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1179144083
Short name T401
Test name
Test status
Simulation time 185450381 ps
CPU time 1.21 seconds
Started Mar 19 02:45:45 PM PDT 24
Finished Mar 19 02:45:47 PM PDT 24
Peak memory 200908 kb
Host smart-4a64eca8-df46-43da-81d2-073cdd99ed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179144083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1179144083
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2385605932
Short name T183
Test name
Test status
Simulation time 119704710 ps
CPU time 1.26 seconds
Started Mar 19 02:45:39 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 201012 kb
Host smart-6caa7c1b-7bc9-41e0-bd73-903e95f7e8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385605932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2385605932
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1933375442
Short name T468
Test name
Test status
Simulation time 10209158252 ps
CPU time 33.9 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 209436 kb
Host smart-450cb24e-cda6-434b-9cb3-34da9f2f664d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933375442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1933375442
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1353056077
Short name T406
Test name
Test status
Simulation time 458578690 ps
CPU time 2.79 seconds
Started Mar 19 02:45:37 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 200964 kb
Host smart-891abd0e-2f6d-493a-af0a-5cf52c8798b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353056077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1353056077
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1225646546
Short name T11
Test name
Test status
Simulation time 129323237 ps
CPU time 1.05 seconds
Started Mar 19 02:45:39 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 200908 kb
Host smart-d2e39254-2267-482a-83cb-6f578bd1cbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225646546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1225646546
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2345077141
Short name T421
Test name
Test status
Simulation time 67521527 ps
CPU time 0.8 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 200784 kb
Host smart-df6483f9-9de6-454f-88ad-1e32f70cf62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345077141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2345077141
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3644220865
Short name T280
Test name
Test status
Simulation time 2364961061 ps
CPU time 9.04 seconds
Started Mar 19 02:45:40 PM PDT 24
Finished Mar 19 02:45:49 PM PDT 24
Peak memory 217908 kb
Host smart-5ab505f0-c9b7-4e75-aa56-932148979a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644220865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3644220865
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1817675578
Short name T233
Test name
Test status
Simulation time 244280573 ps
CPU time 1.21 seconds
Started Mar 19 02:45:43 PM PDT 24
Finished Mar 19 02:45:44 PM PDT 24
Peak memory 218268 kb
Host smart-29325afa-62a5-4b02-bfa4-86f713cb2d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817675578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1817675578
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2019654149
Short name T5
Test name
Test status
Simulation time 209406257 ps
CPU time 1.07 seconds
Started Mar 19 02:45:39 PM PDT 24
Finished Mar 19 02:45:40 PM PDT 24
Peak memory 200772 kb
Host smart-09f27424-a6b8-40f6-b35c-f3f9f504577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019654149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2019654149
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.964986596
Short name T245
Test name
Test status
Simulation time 726235901 ps
CPU time 3.58 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:42 PM PDT 24
Peak memory 201036 kb
Host smart-94f803b1-9d2b-49f0-b6ae-2cd21b7d6c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964986596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.964986596
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.57530794
Short name T157
Test name
Test status
Simulation time 178118089 ps
CPU time 1.22 seconds
Started Mar 19 02:45:43 PM PDT 24
Finished Mar 19 02:45:45 PM PDT 24
Peak memory 200872 kb
Host smart-545a22d6-e684-43ce-a778-89b770b5d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57530794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.57530794
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2389199501
Short name T218
Test name
Test status
Simulation time 252575913 ps
CPU time 1.63 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 201116 kb
Host smart-6df43416-3bd5-4506-8563-231da41d59bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389199501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2389199501
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1678307421
Short name T35
Test name
Test status
Simulation time 4393314080 ps
CPU time 19.83 seconds
Started Mar 19 02:45:40 PM PDT 24
Finished Mar 19 02:46:00 PM PDT 24
Peak memory 201168 kb
Host smart-be1d55e1-66a6-4e1c-8d4e-fe1c4f2546e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678307421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1678307421
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2197947660
Short name T225
Test name
Test status
Simulation time 548282831 ps
CPU time 3.14 seconds
Started Mar 19 02:45:45 PM PDT 24
Finished Mar 19 02:45:49 PM PDT 24
Peak memory 200968 kb
Host smart-8f1f898f-3e40-4d0f-a6e7-116ddfa94603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197947660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2197947660
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2027935665
Short name T137
Test name
Test status
Simulation time 127815903 ps
CPU time 0.97 seconds
Started Mar 19 02:45:38 PM PDT 24
Finished Mar 19 02:45:39 PM PDT 24
Peak memory 200880 kb
Host smart-4f83e7db-ff32-4abd-8f83-3aee4913cb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027935665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2027935665
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.51380908
Short name T474
Test name
Test status
Simulation time 70073975 ps
CPU time 0.77 seconds
Started Mar 19 02:45:50 PM PDT 24
Finished Mar 19 02:45:51 PM PDT 24
Peak memory 200752 kb
Host smart-245da1ba-54c5-4498-be87-b429ce04aee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51380908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.51380908
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3249273594
Short name T431
Test name
Test status
Simulation time 244369922 ps
CPU time 1.09 seconds
Started Mar 19 02:45:46 PM PDT 24
Finished Mar 19 02:45:48 PM PDT 24
Peak memory 218168 kb
Host smart-f1781abc-b909-4031-bac7-bd26554f0877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249273594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3249273594
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.854687544
Short name T201
Test name
Test status
Simulation time 92780253 ps
CPU time 0.78 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 200780 kb
Host smart-cb4121a2-ec32-42ea-aab1-45defd4553f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854687544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.854687544
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1079554350
Short name T127
Test name
Test status
Simulation time 1454543504 ps
CPU time 5.69 seconds
Started Mar 19 02:45:48 PM PDT 24
Finished Mar 19 02:45:54 PM PDT 24
Peak memory 201072 kb
Host smart-59f221a7-34da-47cd-acbe-704a7000c295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079554350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1079554350
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.564101141
Short name T499
Test name
Test status
Simulation time 173785475 ps
CPU time 1.13 seconds
Started Mar 19 02:45:48 PM PDT 24
Finished Mar 19 02:45:49 PM PDT 24
Peak memory 200864 kb
Host smart-8acb08d6-3675-4189-8c2d-26e09e2e0273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564101141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.564101141
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2465159271
Short name T192
Test name
Test status
Simulation time 229522920 ps
CPU time 1.42 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 201028 kb
Host smart-0ff5d772-164e-4d2c-b2ca-35a607448a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465159271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2465159271
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.612515615
Short name T509
Test name
Test status
Simulation time 2559801851 ps
CPU time 9.68 seconds
Started Mar 19 02:45:48 PM PDT 24
Finished Mar 19 02:45:58 PM PDT 24
Peak memory 201212 kb
Host smart-c2695cb7-e1a3-41fe-8074-01c594768418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612515615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.612515615
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2658095356
Short name T274
Test name
Test status
Simulation time 140955478 ps
CPU time 1.87 seconds
Started Mar 19 02:45:50 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 200952 kb
Host smart-4be63b67-f508-4894-bd04-ef528e6e1496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658095356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2658095356
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4152288573
Short name T450
Test name
Test status
Simulation time 96945904 ps
CPU time 0.85 seconds
Started Mar 19 02:45:50 PM PDT 24
Finished Mar 19 02:45:51 PM PDT 24
Peak memory 200900 kb
Host smart-8ff20f21-6d79-442c-ac73-b9ed926c822b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152288573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4152288573
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2358060740
Short name T310
Test name
Test status
Simulation time 67696495 ps
CPU time 0.8 seconds
Started Mar 19 02:45:48 PM PDT 24
Finished Mar 19 02:45:49 PM PDT 24
Peak memory 200808 kb
Host smart-3c8eea6d-dc3c-4039-bb89-2013b8a2cd8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358060740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2358060740
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.385183250
Short name T381
Test name
Test status
Simulation time 2367723615 ps
CPU time 8.44 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:46:00 PM PDT 24
Peak memory 218756 kb
Host smart-d8a4075b-b629-4320-bdec-3b942ddf60ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385183250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.385183250
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2283541025
Short name T3
Test name
Test status
Simulation time 244315172 ps
CPU time 1.17 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 218124 kb
Host smart-6043ef10-8240-4dd7-827a-6c9a33c4a03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283541025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2283541025
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3588912817
Short name T312
Test name
Test status
Simulation time 201747658 ps
CPU time 0.89 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 200732 kb
Host smart-13249f85-a0e7-47c2-8a39-5e98274c1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588912817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3588912817
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3804944062
Short name T13
Test name
Test status
Simulation time 1679537792 ps
CPU time 6.78 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:58 PM PDT 24
Peak memory 201056 kb
Host smart-2b75f236-afde-4278-ac4a-1a11bc271936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804944062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3804944062
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.986303591
Short name T351
Test name
Test status
Simulation time 163484865 ps
CPU time 1.2 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 200872 kb
Host smart-ced6df50-15f2-4dc3-b4c9-0f10227c7c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986303591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.986303591
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4014479780
Short name T300
Test name
Test status
Simulation time 193077484 ps
CPU time 1.39 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:51 PM PDT 24
Peak memory 201036 kb
Host smart-9988d5f1-9947-419a-a9c1-487edb6a1a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014479780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4014479780
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.806362020
Short name T523
Test name
Test status
Simulation time 2220308306 ps
CPU time 10.24 seconds
Started Mar 19 02:45:48 PM PDT 24
Finished Mar 19 02:45:59 PM PDT 24
Peak memory 210548 kb
Host smart-77480a8e-d40d-4ee8-ae2f-9a4617f1dc55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806362020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.806362020
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4003334587
Short name T505
Test name
Test status
Simulation time 321791904 ps
CPU time 2.14 seconds
Started Mar 19 02:45:48 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 200820 kb
Host smart-835169ef-264b-4a3f-aac4-5ff92f97f89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003334587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4003334587
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.4036168244
Short name T151
Test name
Test status
Simulation time 75873789 ps
CPU time 0.84 seconds
Started Mar 19 02:45:50 PM PDT 24
Finished Mar 19 02:45:51 PM PDT 24
Peak memory 200896 kb
Host smart-62f232f4-9e62-47ed-8ea7-ee0dbbb04919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036168244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.4036168244
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.4017801728
Short name T490
Test name
Test status
Simulation time 78896607 ps
CPU time 0.83 seconds
Started Mar 19 02:45:56 PM PDT 24
Finished Mar 19 02:45:57 PM PDT 24
Peak memory 200740 kb
Host smart-c4374a35-d9ad-4787-80ae-90c999c10f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017801728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4017801728
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1570748418
Short name T43
Test name
Test status
Simulation time 1898793475 ps
CPU time 7.14 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:57 PM PDT 24
Peak memory 218544 kb
Host smart-3d0613d7-7e6b-41f9-b010-814cc93cac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570748418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1570748418
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1214187850
Short name T287
Test name
Test status
Simulation time 244375738 ps
CPU time 1.25 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 218264 kb
Host smart-b5dc59ea-5916-45da-882a-2a1b86ae2ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214187850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1214187850
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1847607187
Short name T220
Test name
Test status
Simulation time 232694887 ps
CPU time 0.9 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 200768 kb
Host smart-096232c4-2654-48d9-8ca2-a055e718c34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847607187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1847607187
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1137980422
Short name T290
Test name
Test status
Simulation time 1743250130 ps
CPU time 6.44 seconds
Started Mar 19 02:45:47 PM PDT 24
Finished Mar 19 02:45:53 PM PDT 24
Peak memory 201116 kb
Host smart-53eae4ad-2f18-4c47-9856-c8dd6a39392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137980422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1137980422
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2663409029
Short name T210
Test name
Test status
Simulation time 97242271 ps
CPU time 0.96 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 200864 kb
Host smart-719226c3-63d4-4077-bb2e-7bde36e09ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663409029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2663409029
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3439306513
Short name T520
Test name
Test status
Simulation time 192412999 ps
CPU time 1.54 seconds
Started Mar 19 02:45:54 PM PDT 24
Finished Mar 19 02:45:56 PM PDT 24
Peak memory 201052 kb
Host smart-40664d45-6a5c-4381-a353-25c2c13cee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439306513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3439306513
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.618070683
Short name T440
Test name
Test status
Simulation time 6244881274 ps
CPU time 28.34 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:46:17 PM PDT 24
Peak memory 201176 kb
Host smart-820aef2f-21f0-4f65-be67-8a709a328de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618070683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.618070683
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.4093473510
Short name T247
Test name
Test status
Simulation time 115155972 ps
CPU time 1.5 seconds
Started Mar 19 02:45:48 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 200820 kb
Host smart-5c7e9252-fbb8-4661-907e-54321ed53f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093473510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.4093473510
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3950731484
Short name T360
Test name
Test status
Simulation time 191611441 ps
CPU time 1.23 seconds
Started Mar 19 02:45:47 PM PDT 24
Finished Mar 19 02:45:49 PM PDT 24
Peak memory 200856 kb
Host smart-b6117bc3-5032-49b5-ba85-cfbd291a41ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950731484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3950731484
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1663100035
Short name T155
Test name
Test status
Simulation time 61530158 ps
CPU time 0.75 seconds
Started Mar 19 02:45:52 PM PDT 24
Finished Mar 19 02:45:53 PM PDT 24
Peak memory 200760 kb
Host smart-04ab28ee-997e-4d8c-b7ac-b8fe8061c1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663100035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1663100035
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.4021647970
Short name T42
Test name
Test status
Simulation time 2338626675 ps
CPU time 8.48 seconds
Started Mar 19 02:45:48 PM PDT 24
Finished Mar 19 02:45:57 PM PDT 24
Peak memory 230544 kb
Host smart-285f99a7-18ac-42df-b446-4d6796167ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021647970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.4021647970
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2569395808
Short name T393
Test name
Test status
Simulation time 245819479 ps
CPU time 1.06 seconds
Started Mar 19 02:45:52 PM PDT 24
Finished Mar 19 02:45:53 PM PDT 24
Peak memory 218140 kb
Host smart-b9b4525f-4e76-48f8-971b-d258dc0503f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569395808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2569395808
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.870220563
Short name T394
Test name
Test status
Simulation time 222373217 ps
CPU time 0.95 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:50 PM PDT 24
Peak memory 200736 kb
Host smart-4c47e097-6e47-45ca-80fa-b60e3c8c1256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870220563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.870220563
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2524150085
Short name T41
Test name
Test status
Simulation time 1587247389 ps
CPU time 6.45 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:58 PM PDT 24
Peak memory 201048 kb
Host smart-369bcc1f-94b5-4847-aa91-32d20dbce9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524150085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2524150085
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2967279986
Short name T321
Test name
Test status
Simulation time 177745605 ps
CPU time 1.22 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:53 PM PDT 24
Peak memory 200872 kb
Host smart-3ff3774f-f15d-4882-af3c-7b275b3835e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967279986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2967279986
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.258343573
Short name T501
Test name
Test status
Simulation time 237125030 ps
CPU time 1.56 seconds
Started Mar 19 02:45:50 PM PDT 24
Finished Mar 19 02:45:51 PM PDT 24
Peak memory 201048 kb
Host smart-d4710296-6b2a-4287-8c2a-5d26b1b2099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258343573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.258343573
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.92202707
Short name T234
Test name
Test status
Simulation time 113493486 ps
CPU time 0.97 seconds
Started Mar 19 02:45:52 PM PDT 24
Finished Mar 19 02:45:53 PM PDT 24
Peak memory 200764 kb
Host smart-91b75a1c-32a6-41d4-9054-997cb8cf95a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92202707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.92202707
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.4063699319
Short name T396
Test name
Test status
Simulation time 142992936 ps
CPU time 1.96 seconds
Started Mar 19 02:45:50 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 200912 kb
Host smart-800f7476-08c5-40b2-a438-b0d6ec152596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063699319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4063699319
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3362538065
Short name T56
Test name
Test status
Simulation time 188113689 ps
CPU time 1.29 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 200848 kb
Host smart-05706420-b741-475d-b9c5-0fb65fa6a2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362538065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3362538065
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2513195826
Short name T263
Test name
Test status
Simulation time 197957186 ps
CPU time 1.06 seconds
Started Mar 19 02:45:52 PM PDT 24
Finished Mar 19 02:45:53 PM PDT 24
Peak memory 200780 kb
Host smart-1945d36c-8d29-4f8c-8db6-bbd4b667be26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513195826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2513195826
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3921922060
Short name T457
Test name
Test status
Simulation time 2367225485 ps
CPU time 8.08 seconds
Started Mar 19 02:45:52 PM PDT 24
Finished Mar 19 02:46:00 PM PDT 24
Peak memory 218692 kb
Host smart-d1763dba-bb0c-4959-aa9d-72ab61d95245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921922060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3921922060
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2128626120
Short name T370
Test name
Test status
Simulation time 243483753 ps
CPU time 1.12 seconds
Started Mar 19 02:45:53 PM PDT 24
Finished Mar 19 02:45:54 PM PDT 24
Peak memory 218280 kb
Host smart-96286e5b-1c0b-4f02-9c4b-da2e03734e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128626120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2128626120
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1447966490
Short name T22
Test name
Test status
Simulation time 187289255 ps
CPU time 0.9 seconds
Started Mar 19 02:45:53 PM PDT 24
Finished Mar 19 02:45:54 PM PDT 24
Peak memory 200760 kb
Host smart-c1786782-e35a-4f4f-adb5-a98990034332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447966490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1447966490
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3466755810
Short name T158
Test name
Test status
Simulation time 961792049 ps
CPU time 4.74 seconds
Started Mar 19 02:45:44 PM PDT 24
Finished Mar 19 02:45:49 PM PDT 24
Peak memory 201040 kb
Host smart-a6af13df-a1f8-4faf-b248-2564a564ac99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466755810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3466755810
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3099454349
Short name T237
Test name
Test status
Simulation time 164581340 ps
CPU time 1.28 seconds
Started Mar 19 02:45:54 PM PDT 24
Finished Mar 19 02:45:56 PM PDT 24
Peak memory 200876 kb
Host smart-1cd86254-8d33-42f1-81aa-aa9afe05ccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099454349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3099454349
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3320169370
Short name T470
Test name
Test status
Simulation time 202527679 ps
CPU time 1.48 seconds
Started Mar 19 02:45:49 PM PDT 24
Finished Mar 19 02:45:51 PM PDT 24
Peak memory 201092 kb
Host smart-2180a73d-a85f-4eb5-abc9-ca5da34162fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320169370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3320169370
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3349104512
Short name T36
Test name
Test status
Simulation time 4245449111 ps
CPU time 19.98 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:46:11 PM PDT 24
Peak memory 209436 kb
Host smart-c4242326-2c36-409c-bf59-a82694bcb27f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349104512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3349104512
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3067921490
Short name T448
Test name
Test status
Simulation time 118197164 ps
CPU time 1.56 seconds
Started Mar 19 02:45:53 PM PDT 24
Finished Mar 19 02:45:54 PM PDT 24
Peak memory 200940 kb
Host smart-16d626b0-2584-44d1-af83-ada8e9f388f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067921490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3067921490
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2382992499
Short name T133
Test name
Test status
Simulation time 171491193 ps
CPU time 1.21 seconds
Started Mar 19 02:45:54 PM PDT 24
Finished Mar 19 02:45:55 PM PDT 24
Peak memory 200876 kb
Host smart-16de5f57-36cc-41bf-9f55-965cbcbab39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382992499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2382992499
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3911702598
Short name T77
Test name
Test status
Simulation time 78448897 ps
CPU time 0.88 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:05 PM PDT 24
Peak memory 200688 kb
Host smart-bd0ea55a-1fc2-4416-b864-a12600b7b7ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911702598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3911702598
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3652980167
Short name T44
Test name
Test status
Simulation time 1237922136 ps
CPU time 5.53 seconds
Started Mar 19 02:45:52 PM PDT 24
Finished Mar 19 02:45:58 PM PDT 24
Peak memory 217904 kb
Host smart-d2b05ba9-d456-484b-9cb8-dfab116c5829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652980167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3652980167
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2355174800
Short name T37
Test name
Test status
Simulation time 245290582 ps
CPU time 1.11 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 217700 kb
Host smart-15e30b05-0ab1-45bf-8819-541115f14fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355174800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2355174800
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.810974902
Short name T449
Test name
Test status
Simulation time 167568082 ps
CPU time 0.84 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 200764 kb
Host smart-ead880d7-aa2c-4b4f-a1ea-c67bd985d2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810974902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.810974902
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.875153818
Short name T261
Test name
Test status
Simulation time 981281272 ps
CPU time 5.2 seconds
Started Mar 19 02:45:53 PM PDT 24
Finished Mar 19 02:45:58 PM PDT 24
Peak memory 201056 kb
Host smart-30f200af-249a-4059-af72-d9507eed43e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875153818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.875153818
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.4011024638
Short name T203
Test name
Test status
Simulation time 101617028 ps
CPU time 1.02 seconds
Started Mar 19 02:45:51 PM PDT 24
Finished Mar 19 02:45:52 PM PDT 24
Peak memory 200336 kb
Host smart-c0376c84-4eaf-402f-a82f-b88167e4d06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011024638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.4011024638
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1297058759
Short name T238
Test name
Test status
Simulation time 121901479 ps
CPU time 1.22 seconds
Started Mar 19 02:45:53 PM PDT 24
Finished Mar 19 02:45:54 PM PDT 24
Peak memory 201040 kb
Host smart-d28aa1af-03c1-4f6e-bcbb-77e98ef652ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297058759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1297058759
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1897321092
Short name T412
Test name
Test status
Simulation time 4105020715 ps
CPU time 14.18 seconds
Started Mar 19 02:45:54 PM PDT 24
Finished Mar 19 02:46:08 PM PDT 24
Peak memory 201172 kb
Host smart-8bc58a19-69e4-4ff8-980d-278e374c28a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897321092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1897321092
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3260012450
Short name T494
Test name
Test status
Simulation time 385694699 ps
CPU time 2.17 seconds
Started Mar 19 02:45:52 PM PDT 24
Finished Mar 19 02:45:55 PM PDT 24
Peak memory 200908 kb
Host smart-4d29114f-2611-4228-95d3-0d7a9b46e823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260012450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3260012450
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2354975866
Short name T497
Test name
Test status
Simulation time 104860910 ps
CPU time 1 seconds
Started Mar 19 02:45:52 PM PDT 24
Finished Mar 19 02:45:53 PM PDT 24
Peak memory 200868 kb
Host smart-4905db27-3aa6-4d1c-a116-3215321f0eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354975866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2354975866
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1444565158
Short name T335
Test name
Test status
Simulation time 58623923 ps
CPU time 0.79 seconds
Started Mar 19 02:46:01 PM PDT 24
Finished Mar 19 02:46:02 PM PDT 24
Peak memory 200732 kb
Host smart-4d1f0ad1-b9d5-4992-9da1-d08e89f76b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444565158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1444565158
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1478961841
Short name T236
Test name
Test status
Simulation time 2366007499 ps
CPU time 8.83 seconds
Started Mar 19 02:45:58 PM PDT 24
Finished Mar 19 02:46:07 PM PDT 24
Peak memory 222736 kb
Host smart-23914826-a008-450c-8b35-8af2298cbefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478961841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1478961841
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.573360082
Short name T162
Test name
Test status
Simulation time 245077272 ps
CPU time 1.13 seconds
Started Mar 19 02:46:00 PM PDT 24
Finished Mar 19 02:46:01 PM PDT 24
Peak memory 218320 kb
Host smart-be5fbe7a-9e6e-47dd-a370-8764616e0593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573360082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.573360082
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1408487005
Short name T159
Test name
Test status
Simulation time 186444464 ps
CPU time 0.9 seconds
Started Mar 19 02:46:00 PM PDT 24
Finished Mar 19 02:46:01 PM PDT 24
Peak memory 200768 kb
Host smart-e5c8bb75-694d-4c53-b456-88f959f83ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408487005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1408487005
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2041875340
Short name T452
Test name
Test status
Simulation time 1455953394 ps
CPU time 7.26 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:10 PM PDT 24
Peak memory 200996 kb
Host smart-da080cd2-c68d-41ae-b083-8ac30e410980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041875340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2041875340
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4050362546
Short name T521
Test name
Test status
Simulation time 145027521 ps
CPU time 1.15 seconds
Started Mar 19 02:45:59 PM PDT 24
Finished Mar 19 02:46:01 PM PDT 24
Peak memory 200900 kb
Host smart-04fbc1af-a3db-487c-b693-e1a7ea64c2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050362546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4050362546
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.591699272
Short name T464
Test name
Test status
Simulation time 113582084 ps
CPU time 1.17 seconds
Started Mar 19 02:46:01 PM PDT 24
Finished Mar 19 02:46:02 PM PDT 24
Peak memory 201076 kb
Host smart-26473060-00c1-478e-8dbc-1e938245f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591699272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.591699272
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.870565736
Short name T200
Test name
Test status
Simulation time 7782462550 ps
CPU time 29.97 seconds
Started Mar 19 02:46:00 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 209980 kb
Host smart-1d42349e-4445-443c-ba84-4aee9bf590d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870565736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.870565736
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3462587402
Short name T472
Test name
Test status
Simulation time 115456618 ps
CPU time 1.65 seconds
Started Mar 19 02:46:01 PM PDT 24
Finished Mar 19 02:46:03 PM PDT 24
Peak memory 200820 kb
Host smart-20dc5b55-0c11-46a7-afcc-c8816e42b2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462587402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3462587402
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2885076768
Short name T154
Test name
Test status
Simulation time 86278005 ps
CPU time 0.9 seconds
Started Mar 19 02:45:57 PM PDT 24
Finished Mar 19 02:45:58 PM PDT 24
Peak memory 200908 kb
Host smart-17b97c24-682d-41a7-bfc9-f959d0b29df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885076768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2885076768
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.492853223
Short name T235
Test name
Test status
Simulation time 63287645 ps
CPU time 0.78 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 200748 kb
Host smart-f88823cb-37aa-4247-b2a6-56e3538c9bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492853223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.492853223
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1180220917
Short name T64
Test name
Test status
Simulation time 1221672774 ps
CPU time 5.75 seconds
Started Mar 19 02:44:52 PM PDT 24
Finished Mar 19 02:44:58 PM PDT 24
Peak memory 218088 kb
Host smart-07531289-c3e7-4b16-91db-734d398ae8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180220917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1180220917
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1042456891
Short name T405
Test name
Test status
Simulation time 246068396 ps
CPU time 1.06 seconds
Started Mar 19 02:44:55 PM PDT 24
Finished Mar 19 02:44:57 PM PDT 24
Peak memory 218100 kb
Host smart-73c1b770-a829-4b22-9471-2d38d8a0563a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042456891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1042456891
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3407045292
Short name T334
Test name
Test status
Simulation time 225576941 ps
CPU time 0.92 seconds
Started Mar 19 02:44:49 PM PDT 24
Finished Mar 19 02:44:50 PM PDT 24
Peak memory 200732 kb
Host smart-899ad9a4-2781-4f4f-bfbd-e6fad106ef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407045292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3407045292
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1034682679
Short name T114
Test name
Test status
Simulation time 804629464 ps
CPU time 3.99 seconds
Started Mar 19 02:44:52 PM PDT 24
Finished Mar 19 02:44:56 PM PDT 24
Peak memory 201084 kb
Host smart-ee2924cf-c8e6-4b1a-8cc8-3a0fea422734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034682679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1034682679
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2794529047
Short name T73
Test name
Test status
Simulation time 16571381113 ps
CPU time 25.85 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:45:19 PM PDT 24
Peak memory 217936 kb
Host smart-7a2c19fa-ecb8-4617-8efa-07596624d046
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794529047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2794529047
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4075812558
Short name T142
Test name
Test status
Simulation time 99814959 ps
CPU time 1 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:44:52 PM PDT 24
Peak memory 200868 kb
Host smart-def7326e-e251-4dcd-8e30-ef53c3639b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075812558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4075812558
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.494922023
Short name T347
Test name
Test status
Simulation time 225653404 ps
CPU time 1.44 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:44:56 PM PDT 24
Peak memory 201068 kb
Host smart-d3e846b3-b60e-4151-9f9f-13657d075e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494922023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.494922023
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1282607140
Short name T410
Test name
Test status
Simulation time 9284024324 ps
CPU time 35.59 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:45:29 PM PDT 24
Peak memory 209380 kb
Host smart-aee7b8b6-9ae2-4ead-bc58-0aaad373f57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282607140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1282607140
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2944302045
Short name T536
Test name
Test status
Simulation time 252579154 ps
CPU time 1.79 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 200948 kb
Host smart-ef01d71f-82c9-4a82-92d3-28e8e88d8bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944302045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2944302045
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2507004299
Short name T531
Test name
Test status
Simulation time 97862591 ps
CPU time 0.95 seconds
Started Mar 19 02:44:49 PM PDT 24
Finished Mar 19 02:44:50 PM PDT 24
Peak memory 200864 kb
Host smart-d705371a-1c25-4051-ade2-673b572b42a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507004299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2507004299
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1676833192
Short name T453
Test name
Test status
Simulation time 72905019 ps
CPU time 0.82 seconds
Started Mar 19 02:46:02 PM PDT 24
Finished Mar 19 02:46:03 PM PDT 24
Peak memory 200752 kb
Host smart-8fdc1ce0-3d59-4e8d-82ca-6436b559a7a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676833192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1676833192
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.4138470260
Short name T52
Test name
Test status
Simulation time 1881964256 ps
CPU time 6.99 seconds
Started Mar 19 02:45:56 PM PDT 24
Finished Mar 19 02:46:03 PM PDT 24
Peak memory 218096 kb
Host smart-dca88c9e-5f37-47ef-9f6a-3ddb88635243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138470260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4138470260
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2048301884
Short name T444
Test name
Test status
Simulation time 244410640 ps
CPU time 1.05 seconds
Started Mar 19 02:45:59 PM PDT 24
Finished Mar 19 02:46:01 PM PDT 24
Peak memory 218228 kb
Host smart-b75cd53a-5a45-449a-bcf8-cda7ff38c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048301884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2048301884
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1191078493
Short name T15
Test name
Test status
Simulation time 81409075 ps
CPU time 0.76 seconds
Started Mar 19 02:45:58 PM PDT 24
Finished Mar 19 02:45:59 PM PDT 24
Peak memory 200788 kb
Host smart-2cd62012-8ff8-41fe-9d08-011894ede706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191078493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1191078493
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.418242365
Short name T222
Test name
Test status
Simulation time 787244995 ps
CPU time 3.99 seconds
Started Mar 19 02:46:05 PM PDT 24
Finished Mar 19 02:46:10 PM PDT 24
Peak memory 201064 kb
Host smart-8424237f-3f29-49ac-9765-cca65c3cfc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418242365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.418242365
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3244390710
Short name T291
Test name
Test status
Simulation time 171690746 ps
CPU time 1.29 seconds
Started Mar 19 02:45:58 PM PDT 24
Finished Mar 19 02:46:00 PM PDT 24
Peak memory 200912 kb
Host smart-9d411877-473c-4367-8737-acf7e5fec7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244390710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3244390710
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3479293169
Short name T258
Test name
Test status
Simulation time 119536272 ps
CPU time 1.19 seconds
Started Mar 19 02:46:07 PM PDT 24
Finished Mar 19 02:46:09 PM PDT 24
Peak memory 201052 kb
Host smart-7a36f9f7-754e-4076-b059-fcc55df9ca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479293169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3479293169
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.732925349
Short name T384
Test name
Test status
Simulation time 207248647 ps
CPU time 1.5 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:04 PM PDT 24
Peak memory 200960 kb
Host smart-b17752e8-e466-44ea-b255-671ea2fb81dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732925349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.732925349
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.786935929
Short name T315
Test name
Test status
Simulation time 360068523 ps
CPU time 2.2 seconds
Started Mar 19 02:46:01 PM PDT 24
Finished Mar 19 02:46:03 PM PDT 24
Peak memory 200964 kb
Host smart-e723a64d-dade-4fd2-96c6-cada8a4f25f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786935929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.786935929
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1513071944
Short name T38
Test name
Test status
Simulation time 72039492 ps
CPU time 0.78 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:03 PM PDT 24
Peak memory 200888 kb
Host smart-f3179005-9214-402e-90bd-4676f7b77a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513071944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1513071944
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.816416641
Short name T244
Test name
Test status
Simulation time 77701525 ps
CPU time 0.86 seconds
Started Mar 19 02:45:59 PM PDT 24
Finished Mar 19 02:46:00 PM PDT 24
Peak memory 200760 kb
Host smart-25957e01-4f53-431c-b934-47cd882b9283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816416641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.816416641
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1777644120
Short name T302
Test name
Test status
Simulation time 1223072565 ps
CPU time 6.88 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:11 PM PDT 24
Peak memory 218544 kb
Host smart-856104df-1baf-4cfa-b4bf-735688b309c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777644120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1777644120
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1317909944
Short name T415
Test name
Test status
Simulation time 244872266 ps
CPU time 1.09 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:04 PM PDT 24
Peak memory 218316 kb
Host smart-076d385b-57f8-4f58-835d-42ba1f935c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317909944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1317909944
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1553572849
Short name T21
Test name
Test status
Simulation time 76707679 ps
CPU time 0.77 seconds
Started Mar 19 02:45:58 PM PDT 24
Finished Mar 19 02:46:00 PM PDT 24
Peak memory 200788 kb
Host smart-a0e3b66b-1475-4c12-9fe5-4db7d27cb16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553572849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1553572849
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.4074117195
Short name T84
Test name
Test status
Simulation time 716248559 ps
CPU time 3.88 seconds
Started Mar 19 02:46:02 PM PDT 24
Finished Mar 19 02:46:06 PM PDT 24
Peak memory 201096 kb
Host smart-2a6f9d9d-3e4a-449e-a960-2ddc32e84369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074117195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4074117195
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.463751349
Short name T277
Test name
Test status
Simulation time 101277674 ps
CPU time 1.02 seconds
Started Mar 19 02:46:08 PM PDT 24
Finished Mar 19 02:46:11 PM PDT 24
Peak memory 200872 kb
Host smart-2f50e656-6bc2-4171-8e81-01c0b9147c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463751349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.463751349
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2199635446
Short name T309
Test name
Test status
Simulation time 238161447 ps
CPU time 1.53 seconds
Started Mar 19 02:46:07 PM PDT 24
Finished Mar 19 02:46:11 PM PDT 24
Peak memory 200308 kb
Host smart-27f1e469-31b4-4bdc-9716-5440eb2cf059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199635446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2199635446
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1251697069
Short name T217
Test name
Test status
Simulation time 285736624 ps
CPU time 2.01 seconds
Started Mar 19 02:45:59 PM PDT 24
Finished Mar 19 02:46:02 PM PDT 24
Peak memory 200940 kb
Host smart-204396c2-4ad5-4b71-ad34-44a689734858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251697069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1251697069
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2038529772
Short name T391
Test name
Test status
Simulation time 299570832 ps
CPU time 1.74 seconds
Started Mar 19 02:46:02 PM PDT 24
Finished Mar 19 02:46:03 PM PDT 24
Peak memory 201084 kb
Host smart-050bfbb8-2c69-4f33-9c4d-fc94f9a43027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038529772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2038529772
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2912552532
Short name T480
Test name
Test status
Simulation time 62316046 ps
CPU time 0.79 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:04 PM PDT 24
Peak memory 200740 kb
Host smart-668e548a-fb98-4d69-98df-bad93b46b239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912552532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2912552532
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3803970194
Short name T528
Test name
Test status
Simulation time 1227703400 ps
CPU time 6.04 seconds
Started Mar 19 02:46:07 PM PDT 24
Finished Mar 19 02:46:15 PM PDT 24
Peak memory 217992 kb
Host smart-1e12dd5c-300e-49a9-adcb-983c17455733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803970194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3803970194
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3576963752
Short name T518
Test name
Test status
Simulation time 245110177 ps
CPU time 1.08 seconds
Started Mar 19 02:46:01 PM PDT 24
Finished Mar 19 02:46:02 PM PDT 24
Peak memory 218204 kb
Host smart-4af5b719-3b41-4fa3-88d9-fa9f9ba31a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576963752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3576963752
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3084674405
Short name T373
Test name
Test status
Simulation time 158615094 ps
CPU time 0.94 seconds
Started Mar 19 02:45:59 PM PDT 24
Finished Mar 19 02:46:01 PM PDT 24
Peak memory 200728 kb
Host smart-45359bc6-991e-47e8-8a52-931c7e216e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084674405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3084674405
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2098780388
Short name T272
Test name
Test status
Simulation time 995751838 ps
CPU time 5.43 seconds
Started Mar 19 02:46:02 PM PDT 24
Finished Mar 19 02:46:08 PM PDT 24
Peak memory 200996 kb
Host smart-a236c993-64f4-4a59-86f4-91c4bad261a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098780388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2098780388
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.226262143
Short name T375
Test name
Test status
Simulation time 109647595 ps
CPU time 1.13 seconds
Started Mar 19 02:45:59 PM PDT 24
Finished Mar 19 02:46:01 PM PDT 24
Peak memory 200860 kb
Host smart-d67b8b01-826e-4379-bfc1-dd48f0ad8229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226262143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.226262143
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3477209146
Short name T140
Test name
Test status
Simulation time 256573601 ps
CPU time 1.49 seconds
Started Mar 19 02:46:01 PM PDT 24
Finished Mar 19 02:46:02 PM PDT 24
Peak memory 201040 kb
Host smart-3faa3d31-68b1-4b51-b624-15f60d209a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477209146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3477209146
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2938805104
Short name T51
Test name
Test status
Simulation time 5543864227 ps
CPU time 23.36 seconds
Started Mar 19 02:46:05 PM PDT 24
Finished Mar 19 02:46:29 PM PDT 24
Peak memory 209376 kb
Host smart-aea1e192-922e-4e8d-a0a4-ed503f481921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938805104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2938805104
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.478731687
Short name T368
Test name
Test status
Simulation time 144407327 ps
CPU time 1.81 seconds
Started Mar 19 02:46:01 PM PDT 24
Finished Mar 19 02:46:03 PM PDT 24
Peak memory 200968 kb
Host smart-e651699b-6226-441d-9caa-0162c49d8b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478731687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.478731687
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3312203570
Short name T390
Test name
Test status
Simulation time 217076754 ps
CPU time 1.39 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:05 PM PDT 24
Peak memory 200900 kb
Host smart-9d138ecf-6ebe-4230-882f-f6dba9e04d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312203570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3312203570
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3254386292
Short name T462
Test name
Test status
Simulation time 77540700 ps
CPU time 0.77 seconds
Started Mar 19 02:46:04 PM PDT 24
Finished Mar 19 02:46:06 PM PDT 24
Peak memory 200752 kb
Host smart-37c0d393-f40e-4145-bb0b-db02e37078de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254386292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3254386292
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2427012229
Short name T32
Test name
Test status
Simulation time 2358291878 ps
CPU time 8.34 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:11 PM PDT 24
Peak memory 218456 kb
Host smart-ff9b4a79-6c17-44c3-a0b8-528574fda0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427012229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2427012229
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.918300901
Short name T145
Test name
Test status
Simulation time 244823722 ps
CPU time 1.22 seconds
Started Mar 19 02:46:01 PM PDT 24
Finished Mar 19 02:46:02 PM PDT 24
Peak memory 218084 kb
Host smart-974605d3-4042-451f-967a-53ebcb54c8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918300901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.918300901
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1388414193
Short name T18
Test name
Test status
Simulation time 240942316 ps
CPU time 0.96 seconds
Started Mar 19 02:46:00 PM PDT 24
Finished Mar 19 02:46:02 PM PDT 24
Peak memory 200768 kb
Host smart-d594ebaa-940e-43ee-9de8-e39c1287fbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388414193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1388414193
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.543570540
Short name T525
Test name
Test status
Simulation time 1526047456 ps
CPU time 6.34 seconds
Started Mar 19 02:46:00 PM PDT 24
Finished Mar 19 02:46:07 PM PDT 24
Peak memory 201096 kb
Host smart-d185a9fd-9790-4e0f-8e6e-6c083657dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543570540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.543570540
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1900743032
Short name T213
Test name
Test status
Simulation time 178790197 ps
CPU time 1.35 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:05 PM PDT 24
Peak memory 200864 kb
Host smart-9a96af2c-013d-4cbe-b32b-17539469f7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900743032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1900743032
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.424690900
Short name T336
Test name
Test status
Simulation time 191454609 ps
CPU time 1.33 seconds
Started Mar 19 02:46:07 PM PDT 24
Finished Mar 19 02:46:09 PM PDT 24
Peak memory 200264 kb
Host smart-e4e4dc30-cd27-43a5-ad65-05e6cd94d41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424690900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.424690900
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.969672084
Short name T388
Test name
Test status
Simulation time 4336488602 ps
CPU time 21.41 seconds
Started Mar 19 02:45:59 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 201192 kb
Host smart-bd0c5125-c1e1-4dab-b741-e80874645f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969672084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.969672084
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2141812858
Short name T343
Test name
Test status
Simulation time 135362678 ps
CPU time 1.93 seconds
Started Mar 19 02:46:03 PM PDT 24
Finished Mar 19 02:46:06 PM PDT 24
Peak memory 200836 kb
Host smart-de5fbd07-1e81-40fb-8c36-2867ab96db5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141812858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2141812858
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1342738369
Short name T407
Test name
Test status
Simulation time 143203372 ps
CPU time 1.25 seconds
Started Mar 19 02:45:59 PM PDT 24
Finished Mar 19 02:46:01 PM PDT 24
Peak memory 200888 kb
Host smart-c1d90379-c5cb-4af7-9dbb-7feaa20f5185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342738369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1342738369
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.262568362
Short name T259
Test name
Test status
Simulation time 61372215 ps
CPU time 0.78 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 200744 kb
Host smart-4985f4bc-f230-48bc-85df-618c97b40f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262568362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.262568362
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.640921960
Short name T46
Test name
Test status
Simulation time 1233827069 ps
CPU time 5.92 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:18 PM PDT 24
Peak memory 229908 kb
Host smart-c37d0b9b-aa5d-4cea-b8d6-6527b2ddffa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640921960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.640921960
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3874238924
Short name T169
Test name
Test status
Simulation time 244083595 ps
CPU time 1.07 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 218264 kb
Host smart-de39262b-8d95-49c7-9a82-ad4aed24bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874238924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3874238924
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2065517647
Short name T19
Test name
Test status
Simulation time 167244685 ps
CPU time 0.86 seconds
Started Mar 19 02:46:11 PM PDT 24
Finished Mar 19 02:46:13 PM PDT 24
Peak memory 200752 kb
Host smart-5dfd74f0-d4de-4991-a793-cbb90c315940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065517647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2065517647
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1213750519
Short name T445
Test name
Test status
Simulation time 728159444 ps
CPU time 3.99 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:15 PM PDT 24
Peak memory 201072 kb
Host smart-fbdd4544-60d5-4eed-b5c7-30e0777cd3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213750519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1213750519
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2835171207
Short name T366
Test name
Test status
Simulation time 172613467 ps
CPU time 1.24 seconds
Started Mar 19 02:46:06 PM PDT 24
Finished Mar 19 02:46:08 PM PDT 24
Peak memory 200908 kb
Host smart-86648001-b41b-422a-a69e-f8f1a2fb09c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835171207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2835171207
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2559559962
Short name T437
Test name
Test status
Simulation time 207289463 ps
CPU time 1.42 seconds
Started Mar 19 02:46:02 PM PDT 24
Finished Mar 19 02:46:04 PM PDT 24
Peak memory 201116 kb
Host smart-b808e911-ae62-4d74-8158-9b86150a3b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559559962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2559559962
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2273870711
Short name T275
Test name
Test status
Simulation time 6446574926 ps
CPU time 28.83 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:40 PM PDT 24
Peak memory 201200 kb
Host smart-ee25b46d-6b28-4cb4-ba53-146e1da1ca48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273870711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2273870711
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2176715517
Short name T135
Test name
Test status
Simulation time 558533463 ps
CPU time 3.04 seconds
Started Mar 19 02:46:14 PM PDT 24
Finished Mar 19 02:46:17 PM PDT 24
Peak memory 200900 kb
Host smart-301f968c-15cb-4fee-9db0-6a1d3290c120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176715517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2176715517
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3679579783
Short name T486
Test name
Test status
Simulation time 112316293 ps
CPU time 1.02 seconds
Started Mar 19 02:46:07 PM PDT 24
Finished Mar 19 02:46:09 PM PDT 24
Peak memory 200892 kb
Host smart-798f0307-5092-47d7-842d-b8a917190437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679579783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3679579783
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1771383121
Short name T76
Test name
Test status
Simulation time 60240156 ps
CPU time 0.75 seconds
Started Mar 19 02:46:08 PM PDT 24
Finished Mar 19 02:46:10 PM PDT 24
Peak memory 200756 kb
Host smart-fde7a77e-9fe2-4d47-afae-7cf68b9ec2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771383121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1771383121
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.21045632
Short name T48
Test name
Test status
Simulation time 1911422551 ps
CPU time 7.28 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:19 PM PDT 24
Peak memory 218516 kb
Host smart-2585de1c-29ad-4145-b25d-8b20fe774aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21045632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.21045632
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4195238982
Short name T176
Test name
Test status
Simulation time 244194222 ps
CPU time 1.13 seconds
Started Mar 19 02:46:08 PM PDT 24
Finished Mar 19 02:46:11 PM PDT 24
Peak memory 218284 kb
Host smart-06a18818-be05-42e1-9df0-67e265076400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195238982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4195238982
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1384768461
Short name T282
Test name
Test status
Simulation time 90322135 ps
CPU time 0.75 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 200732 kb
Host smart-bc9fa8a1-39a2-47e4-8780-2cc04a51baaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384768461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1384768461
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1524237966
Short name T152
Test name
Test status
Simulation time 794410522 ps
CPU time 4.43 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:16 PM PDT 24
Peak memory 201112 kb
Host smart-90549d76-4391-4461-9ce9-deab3e5dd112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524237966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1524237966
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.920380758
Short name T267
Test name
Test status
Simulation time 99704861 ps
CPU time 1.01 seconds
Started Mar 19 02:46:07 PM PDT 24
Finished Mar 19 02:46:11 PM PDT 24
Peak memory 200872 kb
Host smart-95c906dd-876f-4566-b857-fa7a4d6aba05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920380758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.920380758
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.283470066
Short name T141
Test name
Test status
Simulation time 223156242 ps
CPU time 1.44 seconds
Started Mar 19 02:46:07 PM PDT 24
Finished Mar 19 02:46:10 PM PDT 24
Peak memory 201064 kb
Host smart-c2642f26-7c10-4ed0-a089-6549c4c2d9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283470066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.283470066
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1167402440
Short name T115
Test name
Test status
Simulation time 4210729468 ps
CPU time 16.83 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:28 PM PDT 24
Peak memory 201180 kb
Host smart-47c8b3b6-6fe3-490b-bd55-5a183c24602a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167402440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1167402440
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3633115554
Short name T524
Test name
Test status
Simulation time 145240787 ps
CPU time 1.88 seconds
Started Mar 19 02:46:11 PM PDT 24
Finished Mar 19 02:46:13 PM PDT 24
Peak memory 200956 kb
Host smart-87addd7c-d35d-4836-b346-1bcb19af38e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633115554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3633115554
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.522952874
Short name T498
Test name
Test status
Simulation time 206647607 ps
CPU time 1.51 seconds
Started Mar 19 02:46:13 PM PDT 24
Finished Mar 19 02:46:15 PM PDT 24
Peak memory 200872 kb
Host smart-93cc3ee0-eb09-44a7-a730-d484dc42c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522952874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.522952874
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.649113231
Short name T492
Test name
Test status
Simulation time 76399420 ps
CPU time 0.77 seconds
Started Mar 19 02:46:15 PM PDT 24
Finished Mar 19 02:46:16 PM PDT 24
Peak memory 200720 kb
Host smart-6ad1a7d4-124f-4d5e-a574-e0e955a175e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649113231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.649113231
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.203644854
Short name T526
Test name
Test status
Simulation time 1224963975 ps
CPU time 5.57 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:16 PM PDT 24
Peak memory 222612 kb
Host smart-45bfc63e-6cd7-4174-b1d2-aa5ba1817f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203644854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.203644854
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.354832572
Short name T506
Test name
Test status
Simulation time 243788632 ps
CPU time 1.02 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 218188 kb
Host smart-cececf44-313d-4046-9345-2637255a350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354832572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.354832572
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1678130530
Short name T299
Test name
Test status
Simulation time 142857832 ps
CPU time 0.79 seconds
Started Mar 19 02:46:20 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 200760 kb
Host smart-84a587c2-4b9f-4fe9-a541-720ef44c24c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678130530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1678130530
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3944306330
Short name T221
Test name
Test status
Simulation time 888827261 ps
CPU time 4.5 seconds
Started Mar 19 02:46:22 PM PDT 24
Finished Mar 19 02:46:27 PM PDT 24
Peak memory 201068 kb
Host smart-8e0d05ef-8df4-4e41-96bc-3261f6669704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944306330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3944306330
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.88028119
Short name T385
Test name
Test status
Simulation time 161985521 ps
CPU time 1.16 seconds
Started Mar 19 02:46:07 PM PDT 24
Finished Mar 19 02:46:10 PM PDT 24
Peak memory 200864 kb
Host smart-43398514-3997-4350-914c-2599e1e6cc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88028119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.88028119
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2960174844
Short name T530
Test name
Test status
Simulation time 254417054 ps
CPU time 1.68 seconds
Started Mar 19 02:46:14 PM PDT 24
Finished Mar 19 02:46:16 PM PDT 24
Peak memory 201048 kb
Host smart-8f6347b8-ab44-4cf3-9039-24c89099d358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960174844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2960174844
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.183588613
Short name T463
Test name
Test status
Simulation time 2017174273 ps
CPU time 7.16 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:18 PM PDT 24
Peak memory 201044 kb
Host smart-d9f2ab58-6a00-41c2-8252-fd0a9da9a143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183588613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.183588613
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2791632339
Short name T182
Test name
Test status
Simulation time 330624068 ps
CPU time 1.97 seconds
Started Mar 19 02:46:08 PM PDT 24
Finished Mar 19 02:46:13 PM PDT 24
Peak memory 200916 kb
Host smart-02ce0ff1-08f5-4be5-a1f4-3e8d07479c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791632339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2791632339
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1953016471
Short name T223
Test name
Test status
Simulation time 181115802 ps
CPU time 1.19 seconds
Started Mar 19 02:46:20 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 200884 kb
Host smart-b0eff384-29e9-4e2d-8908-0adea58e51aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953016471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1953016471
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3464319743
Short name T367
Test name
Test status
Simulation time 83789084 ps
CPU time 0.77 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 200772 kb
Host smart-9a2529fb-90db-4042-89b3-d0f92d509f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464319743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3464319743
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3880304275
Short name T511
Test name
Test status
Simulation time 2364295659 ps
CPU time 8.57 seconds
Started Mar 19 02:46:08 PM PDT 24
Finished Mar 19 02:46:19 PM PDT 24
Peak memory 218272 kb
Host smart-d0be9372-ce4b-48ff-ab7d-b0317ed11f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880304275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3880304275
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2391181666
Short name T232
Test name
Test status
Simulation time 246199430 ps
CPU time 1.07 seconds
Started Mar 19 02:46:12 PM PDT 24
Finished Mar 19 02:46:13 PM PDT 24
Peak memory 218344 kb
Host smart-edf0220e-b368-450b-9609-1c20e5b3230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391181666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2391181666
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.436885903
Short name T204
Test name
Test status
Simulation time 149040807 ps
CPU time 0.84 seconds
Started Mar 19 02:46:14 PM PDT 24
Finished Mar 19 02:46:15 PM PDT 24
Peak memory 200724 kb
Host smart-592e600b-4c70-44c4-9d67-95ab2a81f0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436885903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.436885903
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2047568707
Short name T318
Test name
Test status
Simulation time 1110871840 ps
CPU time 4.87 seconds
Started Mar 19 02:46:16 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 201028 kb
Host smart-01725031-386f-415c-824b-8dab77c3c855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047568707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2047568707
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2031354905
Short name T297
Test name
Test status
Simulation time 109284586 ps
CPU time 1.07 seconds
Started Mar 19 02:46:12 PM PDT 24
Finished Mar 19 02:46:14 PM PDT 24
Peak memory 200892 kb
Host smart-411824ff-7143-4d02-affe-c7a3a36896e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031354905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2031354905
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1366474089
Short name T443
Test name
Test status
Simulation time 108368719 ps
CPU time 1.2 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:13 PM PDT 24
Peak memory 201052 kb
Host smart-e7ed39e8-bb74-475d-9fc1-633a04b50198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366474089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1366474089
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1189646054
Short name T249
Test name
Test status
Simulation time 6225987484 ps
CPU time 22.86 seconds
Started Mar 19 02:46:20 PM PDT 24
Finished Mar 19 02:46:43 PM PDT 24
Peak memory 201184 kb
Host smart-0c2b599a-4a0b-4e99-96ae-0488e7aee0f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189646054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1189646054
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2736476462
Short name T139
Test name
Test status
Simulation time 418036579 ps
CPU time 2.57 seconds
Started Mar 19 02:46:14 PM PDT 24
Finished Mar 19 02:46:17 PM PDT 24
Peak memory 209192 kb
Host smart-64d1a670-9528-4192-87d7-0467acbf3b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736476462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2736476462
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3688324097
Short name T307
Test name
Test status
Simulation time 90857593 ps
CPU time 0.87 seconds
Started Mar 19 02:46:12 PM PDT 24
Finished Mar 19 02:46:13 PM PDT 24
Peak memory 200892 kb
Host smart-4984a021-248e-4f65-b61a-40cea6448c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688324097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3688324097
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2367741893
Short name T327
Test name
Test status
Simulation time 82453350 ps
CPU time 0.81 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 200772 kb
Host smart-78e5a7bc-66a7-4934-b59a-36bd9a6fc629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367741893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2367741893
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3099616327
Short name T153
Test name
Test status
Simulation time 244158911 ps
CPU time 1.07 seconds
Started Mar 19 02:46:07 PM PDT 24
Finished Mar 19 02:46:11 PM PDT 24
Peak memory 218204 kb
Host smart-0122f3de-a156-4154-9589-23177b4e7753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099616327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3099616327
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3061915993
Short name T439
Test name
Test status
Simulation time 164481871 ps
CPU time 0.82 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 200784 kb
Host smart-c08ccf1c-0363-48e4-8166-8d486beafc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061915993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3061915993
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1960323042
Short name T131
Test name
Test status
Simulation time 1849714746 ps
CPU time 6.92 seconds
Started Mar 19 02:46:13 PM PDT 24
Finished Mar 19 02:46:20 PM PDT 24
Peak memory 201068 kb
Host smart-5aff1136-40b6-499c-8d4d-7d955638c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960323042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1960323042
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3947230976
Short name T319
Test name
Test status
Simulation time 109572013 ps
CPU time 1.01 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 200864 kb
Host smart-22a95322-59d5-425e-8577-1189251f5d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947230976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3947230976
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2292410842
Short name T317
Test name
Test status
Simulation time 118955359 ps
CPU time 1.31 seconds
Started Mar 19 02:46:11 PM PDT 24
Finished Mar 19 02:46:13 PM PDT 24
Peak memory 201092 kb
Host smart-0bdbcad2-482a-44b4-abea-4eaa0b13b1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292410842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2292410842
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3512954181
Short name T357
Test name
Test status
Simulation time 1601134412 ps
CPU time 6.24 seconds
Started Mar 19 02:46:11 PM PDT 24
Finished Mar 19 02:46:18 PM PDT 24
Peak memory 201036 kb
Host smart-a8edfea2-c71f-41cd-8b79-4b1bb8bdc967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512954181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3512954181
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3740379944
Short name T416
Test name
Test status
Simulation time 498741084 ps
CPU time 2.68 seconds
Started Mar 19 02:46:22 PM PDT 24
Finished Mar 19 02:46:25 PM PDT 24
Peak memory 200944 kb
Host smart-4e4d2af1-d0bb-4785-8e8d-982efc405989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740379944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3740379944
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.272159545
Short name T163
Test name
Test status
Simulation time 200998728 ps
CPU time 1.19 seconds
Started Mar 19 02:46:20 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 200892 kb
Host smart-570a35cb-9448-42fe-b77a-d2e29eda1b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272159545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.272159545
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.674078377
Short name T80
Test name
Test status
Simulation time 70735314 ps
CPU time 0.8 seconds
Started Mar 19 02:46:18 PM PDT 24
Finished Mar 19 02:46:19 PM PDT 24
Peak memory 200780 kb
Host smart-7a3d5e51-728d-45be-aaba-aea17d630d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674078377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.674078377
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2846179157
Short name T350
Test name
Test status
Simulation time 1223160649 ps
CPU time 5.62 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:16 PM PDT 24
Peak memory 222672 kb
Host smart-5f7714b2-0728-4fd9-9316-fe34f867431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846179157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2846179157
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.543738389
Short name T451
Test name
Test status
Simulation time 243986436 ps
CPU time 1.17 seconds
Started Mar 19 02:46:19 PM PDT 24
Finished Mar 19 02:46:20 PM PDT 24
Peak memory 218300 kb
Host smart-098450d4-2c32-4e66-b672-38c059cdd781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543738389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.543738389
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3429899675
Short name T276
Test name
Test status
Simulation time 111864845 ps
CPU time 0.77 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 200744 kb
Host smart-1e68318b-ebe7-48a0-91db-593b8fad9720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429899675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3429899675
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1509442073
Short name T49
Test name
Test status
Simulation time 1008534386 ps
CPU time 5.4 seconds
Started Mar 19 02:46:13 PM PDT 24
Finished Mar 19 02:46:18 PM PDT 24
Peak memory 201068 kb
Host smart-167d9889-8b1f-45f6-894f-2504e3bea0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509442073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1509442073
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.21181763
Short name T500
Test name
Test status
Simulation time 152199471 ps
CPU time 1.09 seconds
Started Mar 19 02:46:09 PM PDT 24
Finished Mar 19 02:46:12 PM PDT 24
Peak memory 200864 kb
Host smart-7164e9c6-2074-4484-94ec-d92e6991e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21181763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.21181763
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.644633835
Short name T323
Test name
Test status
Simulation time 190408886 ps
CPU time 1.42 seconds
Started Mar 19 02:46:16 PM PDT 24
Finished Mar 19 02:46:18 PM PDT 24
Peak memory 201024 kb
Host smart-e916edfa-c637-45e5-9989-c2783fcc373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644633835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.644633835
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3691792301
Short name T379
Test name
Test status
Simulation time 2493130364 ps
CPU time 11.58 seconds
Started Mar 19 02:46:25 PM PDT 24
Finished Mar 19 02:46:36 PM PDT 24
Peak memory 210760 kb
Host smart-1b3f1652-ba6b-45b5-b0e3-c63cec7e5dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691792301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3691792301
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4177249952
Short name T456
Test name
Test status
Simulation time 143774903 ps
CPU time 1.8 seconds
Started Mar 19 02:46:19 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 200972 kb
Host smart-571dc79d-0202-4289-aee5-cf267f03688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177249952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4177249952
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1954252549
Short name T447
Test name
Test status
Simulation time 135541564 ps
CPU time 1.16 seconds
Started Mar 19 02:46:10 PM PDT 24
Finished Mar 19 02:46:13 PM PDT 24
Peak memory 200860 kb
Host smart-f071cc96-e345-44d6-8989-4eaa5dc55408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954252549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1954252549
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2854835604
Short name T514
Test name
Test status
Simulation time 74607814 ps
CPU time 0.8 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 200720 kb
Host smart-b2fda3f8-7012-4671-92a8-64f726cf4a2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854835604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2854835604
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3715732496
Short name T478
Test name
Test status
Simulation time 1903871406 ps
CPU time 7.95 seconds
Started Mar 19 02:44:52 PM PDT 24
Finished Mar 19 02:45:00 PM PDT 24
Peak memory 222644 kb
Host smart-4b06e829-a6fc-4d63-a618-556a18deeb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715732496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3715732496
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.572173758
Short name T538
Test name
Test status
Simulation time 244665889 ps
CPU time 1.16 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 218224 kb
Host smart-a717f1b8-4b74-4f10-a792-676903536b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572173758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.572173758
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3042726747
Short name T313
Test name
Test status
Simulation time 136659905 ps
CPU time 0.8 seconds
Started Mar 19 02:44:54 PM PDT 24
Finished Mar 19 02:44:55 PM PDT 24
Peak memory 200716 kb
Host smart-34d92cd2-a2fa-41cb-bff3-225cf1ddd954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042726747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3042726747
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2049556165
Short name T515
Test name
Test status
Simulation time 1935298823 ps
CPU time 7.24 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:44:59 PM PDT 24
Peak memory 201056 kb
Host smart-97e40388-2fb3-4d31-8470-51be2c04df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049556165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2049556165
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2513230780
Short name T429
Test name
Test status
Simulation time 172574992 ps
CPU time 1.14 seconds
Started Mar 19 02:44:50 PM PDT 24
Finished Mar 19 02:44:51 PM PDT 24
Peak memory 200904 kb
Host smart-b354fc8c-f7c6-4453-a1e9-f83a92c6ebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513230780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2513230780
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.108747995
Short name T177
Test name
Test status
Simulation time 246542153 ps
CPU time 1.5 seconds
Started Mar 19 02:44:55 PM PDT 24
Finished Mar 19 02:44:57 PM PDT 24
Peak memory 201036 kb
Host smart-eef9f950-e7c3-483c-8dfc-1cf097de83ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108747995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.108747995
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1163313685
Short name T455
Test name
Test status
Simulation time 3503563374 ps
CPU time 16.87 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:45:08 PM PDT 24
Peak memory 201164 kb
Host smart-35a72854-e890-471b-bbdd-510729b70052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163313685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1163313685
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.385351083
Short name T190
Test name
Test status
Simulation time 301073152 ps
CPU time 1.99 seconds
Started Mar 19 02:44:51 PM PDT 24
Finished Mar 19 02:44:53 PM PDT 24
Peak memory 209108 kb
Host smart-b64af300-adec-48a2-a1b8-817fe89bd23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385351083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.385351083
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.133405513
Short name T435
Test name
Test status
Simulation time 105658689 ps
CPU time 0.91 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 200916 kb
Host smart-97a97bdd-a62e-41da-9b43-6ff2555f0fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133405513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.133405513
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2191206099
Short name T214
Test name
Test status
Simulation time 72398597 ps
CPU time 0.79 seconds
Started Mar 19 02:46:23 PM PDT 24
Finished Mar 19 02:46:24 PM PDT 24
Peak memory 200784 kb
Host smart-ab393d77-3681-4571-b164-8de86e83cbd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191206099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2191206099
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2127768849
Short name T404
Test name
Test status
Simulation time 1883790825 ps
CPU time 7.45 seconds
Started Mar 19 02:46:16 PM PDT 24
Finished Mar 19 02:46:24 PM PDT 24
Peak memory 218604 kb
Host smart-8ce642e1-688a-4e2b-9fb0-ec94cc7ab3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127768849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2127768849
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1697626462
Short name T329
Test name
Test status
Simulation time 245154506 ps
CPU time 1.11 seconds
Started Mar 19 02:46:17 PM PDT 24
Finished Mar 19 02:46:19 PM PDT 24
Peak memory 218172 kb
Host smart-3f328932-b883-4852-8b47-a85cac88b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697626462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1697626462
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.560583904
Short name T253
Test name
Test status
Simulation time 150249687 ps
CPU time 0.88 seconds
Started Mar 19 02:46:22 PM PDT 24
Finished Mar 19 02:46:24 PM PDT 24
Peak memory 200744 kb
Host smart-f922c47a-17ec-4dd5-84ac-269091d906f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560583904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.560583904
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3324682154
Short name T477
Test name
Test status
Simulation time 1716331299 ps
CPU time 7.01 seconds
Started Mar 19 02:46:17 PM PDT 24
Finished Mar 19 02:46:24 PM PDT 24
Peak memory 201048 kb
Host smart-3dec4d55-15b4-40ed-96c5-58c3e638a45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324682154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3324682154
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1269050311
Short name T540
Test name
Test status
Simulation time 102233451 ps
CPU time 0.97 seconds
Started Mar 19 02:46:17 PM PDT 24
Finished Mar 19 02:46:18 PM PDT 24
Peak memory 200908 kb
Host smart-be4cd83b-096a-4ab7-9311-9417a0003923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269050311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1269050311
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3896356283
Short name T418
Test name
Test status
Simulation time 115033303 ps
CPU time 1.16 seconds
Started Mar 19 02:46:17 PM PDT 24
Finished Mar 19 02:46:18 PM PDT 24
Peak memory 201084 kb
Host smart-17ee0bb6-919a-4925-8ef1-aef3de495ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896356283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3896356283
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1444357612
Short name T106
Test name
Test status
Simulation time 3068754589 ps
CPU time 15.76 seconds
Started Mar 19 02:46:24 PM PDT 24
Finished Mar 19 02:46:40 PM PDT 24
Peak memory 201148 kb
Host smart-c4fed853-c0fd-4598-98e4-26027b3dbdf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444357612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1444357612
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.4073438257
Short name T339
Test name
Test status
Simulation time 439282771 ps
CPU time 2.55 seconds
Started Mar 19 02:46:18 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 200920 kb
Host smart-8776262c-2d85-47b4-9adb-3add0b882802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073438257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4073438257
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2226846631
Short name T487
Test name
Test status
Simulation time 124194551 ps
CPU time 1.14 seconds
Started Mar 19 02:46:20 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 200896 kb
Host smart-56ccdf4d-b102-4d6a-aa09-266a26599ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226846631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2226846631
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.798194192
Short name T156
Test name
Test status
Simulation time 87984727 ps
CPU time 0.87 seconds
Started Mar 19 02:46:19 PM PDT 24
Finished Mar 19 02:46:20 PM PDT 24
Peak memory 200744 kb
Host smart-2e14710b-fdcf-4935-ac60-d4fb5f980e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798194192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.798194192
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1022013239
Short name T228
Test name
Test status
Simulation time 2383592760 ps
CPU time 8.12 seconds
Started Mar 19 02:46:25 PM PDT 24
Finished Mar 19 02:46:33 PM PDT 24
Peak memory 222756 kb
Host smart-90949ace-99b6-42e6-b6a9-0ba56af547b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022013239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1022013239
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1237915385
Short name T174
Test name
Test status
Simulation time 245078333 ps
CPU time 1.07 seconds
Started Mar 19 02:46:25 PM PDT 24
Finished Mar 19 02:46:26 PM PDT 24
Peak memory 218172 kb
Host smart-70e8e7ae-6461-41da-bea0-a2707d363646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237915385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1237915385
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4231162088
Short name T262
Test name
Test status
Simulation time 186189903 ps
CPU time 0.9 seconds
Started Mar 19 02:46:21 PM PDT 24
Finished Mar 19 02:46:23 PM PDT 24
Peak memory 200756 kb
Host smart-c52cb781-8258-4475-80f3-421527bc8d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231162088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4231162088
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3082368611
Short name T459
Test name
Test status
Simulation time 1391410075 ps
CPU time 5.87 seconds
Started Mar 19 02:46:23 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 201068 kb
Host smart-a528daa7-7f33-42b4-9a2c-201de9cd7f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082368611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3082368611
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2147587969
Short name T187
Test name
Test status
Simulation time 175157875 ps
CPU time 1.21 seconds
Started Mar 19 02:46:14 PM PDT 24
Finished Mar 19 02:46:15 PM PDT 24
Peak memory 200872 kb
Host smart-7ad45b4f-e958-42bf-943e-b007b58db3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147587969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2147587969
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2815325393
Short name T273
Test name
Test status
Simulation time 196908662 ps
CPU time 1.44 seconds
Started Mar 19 02:46:21 PM PDT 24
Finished Mar 19 02:46:22 PM PDT 24
Peak memory 201044 kb
Host smart-23738965-2102-4d79-9e24-1f46a0825bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815325393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2815325393
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2815978504
Short name T128
Test name
Test status
Simulation time 10929861124 ps
CPU time 35.48 seconds
Started Mar 19 02:46:16 PM PDT 24
Finished Mar 19 02:46:52 PM PDT 24
Peak memory 201208 kb
Host smart-028342de-4652-42bf-bd91-7bb65cebed71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815978504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2815978504
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3552135018
Short name T289
Test name
Test status
Simulation time 523081870 ps
CPU time 3.04 seconds
Started Mar 19 02:46:24 PM PDT 24
Finished Mar 19 02:46:28 PM PDT 24
Peak memory 200924 kb
Host smart-6019c74a-d0b5-4153-9a98-b10554bfcfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552135018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3552135018
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1195845714
Short name T271
Test name
Test status
Simulation time 132028627 ps
CPU time 1.13 seconds
Started Mar 19 02:46:20 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 200896 kb
Host smart-b8eed26d-6920-4049-8489-d29d26f5a60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195845714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1195845714
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2147592726
Short name T4
Test name
Test status
Simulation time 51826764 ps
CPU time 0.74 seconds
Started Mar 19 02:46:22 PM PDT 24
Finished Mar 19 02:46:23 PM PDT 24
Peak memory 200744 kb
Host smart-482672ea-e766-4381-84a8-580dfa6e7f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147592726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2147592726
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.4042511926
Short name T330
Test name
Test status
Simulation time 2355682999 ps
CPU time 8.62 seconds
Started Mar 19 02:46:23 PM PDT 24
Finished Mar 19 02:46:32 PM PDT 24
Peak memory 218432 kb
Host smart-df68e68f-c954-4095-a7cf-5dfafec4d33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042511926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4042511926
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2726932406
Short name T283
Test name
Test status
Simulation time 243665484 ps
CPU time 1.13 seconds
Started Mar 19 02:46:18 PM PDT 24
Finished Mar 19 02:46:19 PM PDT 24
Peak memory 218152 kb
Host smart-be7e6e69-d8bc-4ebd-a68e-68c5393c550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726932406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2726932406
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2549910886
Short name T517
Test name
Test status
Simulation time 88522729 ps
CPU time 0.8 seconds
Started Mar 19 02:46:25 PM PDT 24
Finished Mar 19 02:46:26 PM PDT 24
Peak memory 200768 kb
Host smart-24f7f289-14e5-47e8-85fc-5c17d81eabbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549910886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2549910886
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.572875443
Short name T522
Test name
Test status
Simulation time 1700877736 ps
CPU time 6.57 seconds
Started Mar 19 02:46:16 PM PDT 24
Finished Mar 19 02:46:23 PM PDT 24
Peak memory 201048 kb
Host smart-eb2f34f4-1ce6-439b-9d05-67579db3824f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572875443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.572875443
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3896730780
Short name T322
Test name
Test status
Simulation time 143246463 ps
CPU time 1.18 seconds
Started Mar 19 02:46:19 PM PDT 24
Finished Mar 19 02:46:21 PM PDT 24
Peak memory 200872 kb
Host smart-b1695c15-1bfa-47e5-af63-3bc39c4aa516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896730780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3896730780
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.738267329
Short name T136
Test name
Test status
Simulation time 262406741 ps
CPU time 1.57 seconds
Started Mar 19 02:46:23 PM PDT 24
Finished Mar 19 02:46:25 PM PDT 24
Peak memory 201036 kb
Host smart-6a781234-9075-4204-921d-2e71a285d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738267329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.738267329
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2043433426
Short name T503
Test name
Test status
Simulation time 6416614475 ps
CPU time 28.42 seconds
Started Mar 19 02:46:17 PM PDT 24
Finished Mar 19 02:46:46 PM PDT 24
Peak memory 201196 kb
Host smart-998d4a8f-edf2-454f-af5a-ebe3df2406b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043433426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2043433426
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1978348872
Short name T363
Test name
Test status
Simulation time 146653010 ps
CPU time 1.76 seconds
Started Mar 19 02:46:17 PM PDT 24
Finished Mar 19 02:46:19 PM PDT 24
Peak memory 200912 kb
Host smart-9e32a2c7-6f42-4cb5-9027-805ad619af25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978348872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1978348872
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1138813299
Short name T372
Test name
Test status
Simulation time 194942776 ps
CPU time 1.3 seconds
Started Mar 19 02:46:21 PM PDT 24
Finished Mar 19 02:46:23 PM PDT 24
Peak memory 200864 kb
Host smart-e345f0ba-0635-49dd-b264-ca2ed4065750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138813299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1138813299
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3721120178
Short name T197
Test name
Test status
Simulation time 70199066 ps
CPU time 0.78 seconds
Started Mar 19 02:46:32 PM PDT 24
Finished Mar 19 02:46:33 PM PDT 24
Peak memory 200756 kb
Host smart-8238a08b-41ee-4707-afed-099698158dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721120178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3721120178
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.955827760
Short name T345
Test name
Test status
Simulation time 1229422533 ps
CPU time 5.44 seconds
Started Mar 19 02:46:30 PM PDT 24
Finished Mar 19 02:46:35 PM PDT 24
Peak memory 217568 kb
Host smart-e2017650-d5b7-41dd-ba33-71c1dad8de3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955827760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.955827760
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2321172078
Short name T534
Test name
Test status
Simulation time 244989983 ps
CPU time 1.14 seconds
Started Mar 19 02:46:27 PM PDT 24
Finished Mar 19 02:46:28 PM PDT 24
Peak memory 218276 kb
Host smart-a59ad662-a156-4415-9464-2c4c232c480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321172078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2321172078
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.340541632
Short name T295
Test name
Test status
Simulation time 188746506 ps
CPU time 0.97 seconds
Started Mar 19 02:46:22 PM PDT 24
Finished Mar 19 02:46:24 PM PDT 24
Peak memory 200780 kb
Host smart-a884e7f5-2e94-4010-b9a3-062a8cdffb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340541632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.340541632
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.920473360
Short name T482
Test name
Test status
Simulation time 999031084 ps
CPU time 4.99 seconds
Started Mar 19 02:46:23 PM PDT 24
Finished Mar 19 02:46:28 PM PDT 24
Peak memory 201036 kb
Host smart-efd9becf-9ca2-44f6-aacd-1c3231219db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920473360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.920473360
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.4112780068
Short name T387
Test name
Test status
Simulation time 144115621 ps
CPU time 1.27 seconds
Started Mar 19 02:46:31 PM PDT 24
Finished Mar 19 02:46:33 PM PDT 24
Peak memory 200884 kb
Host smart-dc6cc84b-5135-4a2a-8dfb-06c07aa588e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112780068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.4112780068
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3222346744
Short name T231
Test name
Test status
Simulation time 119746759 ps
CPU time 1.32 seconds
Started Mar 19 02:46:19 PM PDT 24
Finished Mar 19 02:46:20 PM PDT 24
Peak memory 201048 kb
Host smart-4ef0d9a5-faa8-4639-a113-dfa5a333c0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222346744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3222346744
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3042082483
Short name T537
Test name
Test status
Simulation time 8466316841 ps
CPU time 29.54 seconds
Started Mar 19 02:46:32 PM PDT 24
Finished Mar 19 02:47:02 PM PDT 24
Peak memory 201224 kb
Host smart-86be918b-50c7-4eb5-b03e-52bac5d81436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042082483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3042082483
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1982898752
Short name T167
Test name
Test status
Simulation time 133483859 ps
CPU time 1.86 seconds
Started Mar 19 02:46:23 PM PDT 24
Finished Mar 19 02:46:25 PM PDT 24
Peak memory 200944 kb
Host smart-ceddc9ed-08b6-4118-adea-d5e456b77ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982898752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1982898752
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2127703732
Short name T104
Test name
Test status
Simulation time 157872653 ps
CPU time 1.34 seconds
Started Mar 19 02:46:18 PM PDT 24
Finished Mar 19 02:46:20 PM PDT 24
Peak memory 201088 kb
Host smart-8c72d7a3-2d08-456d-9a49-d0e50f27a859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127703732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2127703732
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3008073237
Short name T305
Test name
Test status
Simulation time 79234307 ps
CPU time 0.83 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:29 PM PDT 24
Peak memory 200724 kb
Host smart-9f90199e-562f-4e8e-b185-a786bfb3a280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008073237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3008073237
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.4083994061
Short name T29
Test name
Test status
Simulation time 1240748824 ps
CPU time 5.58 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:35 PM PDT 24
Peak memory 218580 kb
Host smart-24b896e3-cf6f-4ef1-8309-05a00d531f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083994061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.4083994061
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3164008305
Short name T248
Test name
Test status
Simulation time 244912605 ps
CPU time 1.13 seconds
Started Mar 19 02:46:30 PM PDT 24
Finished Mar 19 02:46:31 PM PDT 24
Peak memory 218032 kb
Host smart-816784e0-4e82-42a8-9d5d-aa002aba58a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164008305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3164008305
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2316680548
Short name T400
Test name
Test status
Simulation time 190862570 ps
CPU time 0.88 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 200776 kb
Host smart-d858d493-e3e6-4706-8924-3c5437f0d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316680548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2316680548
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1163319463
Short name T359
Test name
Test status
Simulation time 1188047618 ps
CPU time 4.77 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:33 PM PDT 24
Peak memory 201104 kb
Host smart-0fc5c9dd-e5b5-4f7b-a0e1-2f2151c6170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163319463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1163319463
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3456970366
Short name T6
Test name
Test status
Simulation time 145944423 ps
CPU time 1.13 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 200864 kb
Host smart-50ded680-45d7-4a54-be68-361faabed8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456970366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3456970366
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3089186822
Short name T186
Test name
Test status
Simulation time 123414377 ps
CPU time 1.23 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:29 PM PDT 24
Peak memory 201036 kb
Host smart-fdb60067-7f8b-41d9-8dd1-db525b178611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089186822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3089186822
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.713899538
Short name T471
Test name
Test status
Simulation time 115782798 ps
CPU time 1.38 seconds
Started Mar 19 02:46:26 PM PDT 24
Finished Mar 19 02:46:28 PM PDT 24
Peak memory 200908 kb
Host smart-aeb57f3b-b56b-449b-8c1d-ae8944650985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713899538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.713899538
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3752158459
Short name T269
Test name
Test status
Simulation time 108111911 ps
CPU time 0.94 seconds
Started Mar 19 02:46:27 PM PDT 24
Finished Mar 19 02:46:29 PM PDT 24
Peak memory 200864 kb
Host smart-076b7bae-5a2e-4501-a5f8-1a01ce1faa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752158459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3752158459
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2521925712
Short name T361
Test name
Test status
Simulation time 57452392 ps
CPU time 0.75 seconds
Started Mar 19 02:46:26 PM PDT 24
Finished Mar 19 02:46:27 PM PDT 24
Peak memory 200784 kb
Host smart-52e3f56c-048d-499c-865c-839174012431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521925712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2521925712
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.400100997
Short name T513
Test name
Test status
Simulation time 1888549127 ps
CPU time 7 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:35 PM PDT 24
Peak memory 217544 kb
Host smart-d5a4369c-aa7d-41ec-890e-7b4d6d496447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400100997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.400100997
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4075059659
Short name T535
Test name
Test status
Simulation time 246524577 ps
CPU time 1.03 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:29 PM PDT 24
Peak memory 218188 kb
Host smart-083bd295-3aea-4afa-a87b-bd0b81ddcc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075059659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4075059659
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3938891014
Short name T409
Test name
Test status
Simulation time 207277946 ps
CPU time 0.91 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 200728 kb
Host smart-d4e4c301-31ff-4f59-8397-25adc48d3f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938891014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3938891014
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2183354514
Short name T488
Test name
Test status
Simulation time 1724553491 ps
CPU time 6.92 seconds
Started Mar 19 02:46:27 PM PDT 24
Finished Mar 19 02:46:34 PM PDT 24
Peak memory 201080 kb
Host smart-cf23643d-89a9-42d8-b969-9637dbe25f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183354514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2183354514
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1344804349
Short name T441
Test name
Test status
Simulation time 106357407 ps
CPU time 1.09 seconds
Started Mar 19 02:46:26 PM PDT 24
Finished Mar 19 02:46:28 PM PDT 24
Peak memory 200944 kb
Host smart-b70b7fbb-1dbe-41ee-936e-4934dc08ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344804349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1344804349
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3375260839
Short name T160
Test name
Test status
Simulation time 195706113 ps
CPU time 1.38 seconds
Started Mar 19 02:46:30 PM PDT 24
Finished Mar 19 02:46:32 PM PDT 24
Peak memory 201040 kb
Host smart-846db074-b847-44e3-a306-b400b3471f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375260839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3375260839
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3053514248
Short name T504
Test name
Test status
Simulation time 11880243677 ps
CPU time 38.8 seconds
Started Mar 19 02:46:26 PM PDT 24
Finished Mar 19 02:47:05 PM PDT 24
Peak memory 210032 kb
Host smart-114e7792-cf2c-4f6f-be37-b431d0be856c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053514248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3053514248
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.213316526
Short name T354
Test name
Test status
Simulation time 283250695 ps
CPU time 1.93 seconds
Started Mar 19 02:46:30 PM PDT 24
Finished Mar 19 02:46:32 PM PDT 24
Peak memory 200928 kb
Host smart-b6ef64b7-0ce8-411a-9353-a3d4b3a93bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213316526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.213316526
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1327608038
Short name T408
Test name
Test status
Simulation time 57499407 ps
CPU time 0.73 seconds
Started Mar 19 02:46:27 PM PDT 24
Finished Mar 19 02:46:28 PM PDT 24
Peak memory 200864 kb
Host smart-8abdd422-8de5-4f01-a6d8-6b34d2f612ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327608038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1327608038
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.819529487
Short name T316
Test name
Test status
Simulation time 63236208 ps
CPU time 0.73 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:29 PM PDT 24
Peak memory 200772 kb
Host smart-ad3eb3db-a949-4bee-8a2b-7fc17344ebe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819529487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.819529487
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3646665364
Short name T27
Test name
Test status
Simulation time 2358972535 ps
CPU time 8.48 seconds
Started Mar 19 02:46:31 PM PDT 24
Finished Mar 19 02:46:40 PM PDT 24
Peak memory 222528 kb
Host smart-759b0b53-15c1-44d8-8665-2510627ddbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646665364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3646665364
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2398902403
Short name T353
Test name
Test status
Simulation time 245403071 ps
CPU time 1.07 seconds
Started Mar 19 02:46:24 PM PDT 24
Finished Mar 19 02:46:25 PM PDT 24
Peak memory 218212 kb
Host smart-92585249-03da-4566-80cb-be88170d88f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398902403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2398902403
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3151999047
Short name T473
Test name
Test status
Simulation time 135321663 ps
CPU time 0.82 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:29 PM PDT 24
Peak memory 200760 kb
Host smart-25a22fdd-c070-423b-b56d-97a87b0f6b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151999047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3151999047
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.824274861
Short name T129
Test name
Test status
Simulation time 1696458148 ps
CPU time 6.16 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:35 PM PDT 24
Peak memory 201048 kb
Host smart-74ecbc60-ff58-4858-b757-a3a27909d1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824274861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.824274861
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3620359705
Short name T149
Test name
Test status
Simulation time 101235341 ps
CPU time 0.97 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 200916 kb
Host smart-69263b15-796b-4c8b-9199-cb5df1b73b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620359705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3620359705
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3713692227
Short name T147
Test name
Test status
Simulation time 110272733 ps
CPU time 1.15 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 201080 kb
Host smart-4aec5aac-ab79-4d77-9ad8-e4c6777ae7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713692227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3713692227
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.704472143
Short name T516
Test name
Test status
Simulation time 140563798 ps
CPU time 1.08 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 200776 kb
Host smart-48e94ce4-8106-4387-9eb7-eca8df431deb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704472143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.704472143
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2916878623
Short name T414
Test name
Test status
Simulation time 302482638 ps
CPU time 2.05 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:31 PM PDT 24
Peak memory 209136 kb
Host smart-ab113af6-d673-4b5d-b6b2-04ed830eba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916878623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2916878623
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4172332371
Short name T251
Test name
Test status
Simulation time 149982829 ps
CPU time 1.29 seconds
Started Mar 19 02:46:26 PM PDT 24
Finished Mar 19 02:46:27 PM PDT 24
Peak memory 201064 kb
Host smart-00862f79-25bb-4d30-b8e7-534947bbed8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172332371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4172332371
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.121995720
Short name T62
Test name
Test status
Simulation time 66491735 ps
CPU time 0.77 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 200776 kb
Host smart-c4e9888a-66b2-4776-9ffe-d42d019c8fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121995720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.121995720
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3685249346
Short name T53
Test name
Test status
Simulation time 1909964034 ps
CPU time 7.98 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:37 PM PDT 24
Peak memory 218104 kb
Host smart-28849b2d-f6b9-4ac0-abcb-0875432327db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685249346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3685249346
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.477385823
Short name T161
Test name
Test status
Simulation time 245940631 ps
CPU time 1.07 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:29 PM PDT 24
Peak memory 218120 kb
Host smart-7db18c37-2bc5-4e4e-90ac-90fd5a2e1a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477385823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.477385823
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1393763183
Short name T432
Test name
Test status
Simulation time 111235710 ps
CPU time 0.78 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:29 PM PDT 24
Peak memory 200756 kb
Host smart-ed55f022-51ee-475b-8c48-4a9db030d2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393763183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1393763183
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1650595732
Short name T215
Test name
Test status
Simulation time 658282222 ps
CPU time 3.9 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:33 PM PDT 24
Peak memory 201056 kb
Host smart-3f0629c7-d82d-4777-a147-b0235031f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650595732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1650595732
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3551755818
Short name T256
Test name
Test status
Simulation time 162910870 ps
CPU time 1.21 seconds
Started Mar 19 02:46:31 PM PDT 24
Finished Mar 19 02:46:32 PM PDT 24
Peak memory 200884 kb
Host smart-0b4663aa-0ab6-42ea-a789-c6f253e8504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551755818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3551755818
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.918398439
Short name T507
Test name
Test status
Simulation time 188572875 ps
CPU time 1.36 seconds
Started Mar 19 02:46:30 PM PDT 24
Finished Mar 19 02:46:31 PM PDT 24
Peak memory 201076 kb
Host smart-03ddf50a-0fc3-4017-8366-46e58e280966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918398439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.918398439
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3139824232
Short name T426
Test name
Test status
Simulation time 1901717932 ps
CPU time 7.14 seconds
Started Mar 19 02:46:32 PM PDT 24
Finished Mar 19 02:46:39 PM PDT 24
Peak memory 201084 kb
Host smart-e221d195-dc62-4931-84d8-9be3a289d8a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139824232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3139824232
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.953883435
Short name T325
Test name
Test status
Simulation time 112116513 ps
CPU time 1.47 seconds
Started Mar 19 02:46:28 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 200904 kb
Host smart-bb1acb15-c174-4799-a3c1-4691a7a823b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953883435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.953883435
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2760000332
Short name T150
Test name
Test status
Simulation time 128531461 ps
CPU time 1.21 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:31 PM PDT 24
Peak memory 200848 kb
Host smart-3135ed4c-ee09-4fec-a61b-35f8f4a1229c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760000332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2760000332
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2925495452
Short name T168
Test name
Test status
Simulation time 57449793 ps
CPU time 0.79 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 200752 kb
Host smart-d1438b8d-56d7-48eb-b817-6c0e6f4bc86c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925495452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2925495452
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3788451172
Short name T34
Test name
Test status
Simulation time 1882123621 ps
CPU time 6.97 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:36 PM PDT 24
Peak memory 230364 kb
Host smart-bba725ad-8762-46e7-be05-562598387705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788451172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3788451172
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2807883020
Short name T286
Test name
Test status
Simulation time 244240951 ps
CPU time 1.1 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 218080 kb
Host smart-380b9aea-04be-4fd9-9c27-620848e6bb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807883020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2807883020
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1113278786
Short name T193
Test name
Test status
Simulation time 160567873 ps
CPU time 0.86 seconds
Started Mar 19 02:46:32 PM PDT 24
Finished Mar 19 02:46:33 PM PDT 24
Peak memory 200792 kb
Host smart-9b8ae670-adc7-47f1-a0c1-ac46da659aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113278786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1113278786
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4262661883
Short name T126
Test name
Test status
Simulation time 1553875416 ps
CPU time 6.04 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:35 PM PDT 24
Peak memory 201080 kb
Host smart-d760209f-a28a-4b4b-a2cd-8b47faffd66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262661883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4262661883
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4084609283
Short name T333
Test name
Test status
Simulation time 158208312 ps
CPU time 1.24 seconds
Started Mar 19 02:46:31 PM PDT 24
Finished Mar 19 02:46:33 PM PDT 24
Peak memory 200872 kb
Host smart-c3dc0d40-8183-47a6-999f-50904acb7337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084609283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4084609283
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2044645035
Short name T208
Test name
Test status
Simulation time 194449630 ps
CPU time 1.46 seconds
Started Mar 19 02:46:30 PM PDT 24
Finished Mar 19 02:46:31 PM PDT 24
Peak memory 201112 kb
Host smart-b8f507f3-12a5-415d-967a-9a61ae33965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044645035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2044645035
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2176012417
Short name T83
Test name
Test status
Simulation time 3195760565 ps
CPU time 14.79 seconds
Started Mar 19 02:46:37 PM PDT 24
Finished Mar 19 02:46:52 PM PDT 24
Peak memory 209412 kb
Host smart-65372ddf-8d51-4cfe-b295-f45c7cad557d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176012417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2176012417
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1469918802
Short name T1
Test name
Test status
Simulation time 118915940 ps
CPU time 1.51 seconds
Started Mar 19 02:46:31 PM PDT 24
Finished Mar 19 02:46:33 PM PDT 24
Peak memory 200960 kb
Host smart-010268fb-e9e2-4e1e-8247-4bde070e13bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469918802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1469918802
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.941573794
Short name T495
Test name
Test status
Simulation time 92066562 ps
CPU time 0.83 seconds
Started Mar 19 02:46:29 PM PDT 24
Finished Mar 19 02:46:30 PM PDT 24
Peak memory 200900 kb
Host smart-0983c826-6ee9-4143-b332-caf3f50071f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941573794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.941573794
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3993104143
Short name T481
Test name
Test status
Simulation time 65108510 ps
CPU time 0.86 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 200752 kb
Host smart-3b5ce157-c961-4da9-b9a4-c791bc95bca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993104143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3993104143
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1603642237
Short name T25
Test name
Test status
Simulation time 2354055840 ps
CPU time 8.19 seconds
Started Mar 19 02:46:42 PM PDT 24
Finished Mar 19 02:46:52 PM PDT 24
Peak memory 218408 kb
Host smart-97876132-3d65-48f6-8ff4-86c8a8a798bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603642237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1603642237
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3337708414
Short name T364
Test name
Test status
Simulation time 243952265 ps
CPU time 1.04 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:45 PM PDT 24
Peak memory 218212 kb
Host smart-0960591d-d246-4346-a91c-9c6e82c2afcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337708414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3337708414
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3060573556
Short name T519
Test name
Test status
Simulation time 113949579 ps
CPU time 0.83 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 200740 kb
Host smart-64270148-c09d-457e-be89-f9123c458020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060573556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3060573556
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2069644573
Short name T491
Test name
Test status
Simulation time 1710333296 ps
CPU time 7.23 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:48 PM PDT 24
Peak memory 201040 kb
Host smart-3affc439-8cca-49bd-a64a-4d718958c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069644573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2069644573
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.481214320
Short name T243
Test name
Test status
Simulation time 99148945 ps
CPU time 1.09 seconds
Started Mar 19 02:46:40 PM PDT 24
Finished Mar 19 02:46:44 PM PDT 24
Peak memory 200916 kb
Host smart-be028ed9-ccfa-4361-a3ea-25c494aa7528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481214320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.481214320
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3795699214
Short name T178
Test name
Test status
Simulation time 129289269 ps
CPU time 1.21 seconds
Started Mar 19 02:46:38 PM PDT 24
Finished Mar 19 02:46:42 PM PDT 24
Peak memory 201068 kb
Host smart-0c3df727-197f-4dd8-9b52-ed6b36e00487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795699214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3795699214
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3031418195
Short name T112
Test name
Test status
Simulation time 7467830861 ps
CPU time 36.63 seconds
Started Mar 19 02:46:39 PM PDT 24
Finished Mar 19 02:47:19 PM PDT 24
Peak memory 201188 kb
Host smart-37aa5830-8756-4464-a94f-c1472f5c68fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031418195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3031418195
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1124049859
Short name T420
Test name
Test status
Simulation time 547036784 ps
CPU time 2.85 seconds
Started Mar 19 02:46:41 PM PDT 24
Finished Mar 19 02:46:46 PM PDT 24
Peak memory 200904 kb
Host smart-9848ba53-7c80-402c-8ab0-2bd1555f1d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124049859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1124049859
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1430841354
Short name T386
Test name
Test status
Simulation time 81314628 ps
CPU time 0.87 seconds
Started Mar 19 02:46:37 PM PDT 24
Finished Mar 19 02:46:38 PM PDT 24
Peak memory 200868 kb
Host smart-e73916d0-3b12-4c11-9d00-5f663742bca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430841354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1430841354
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1490333572
Short name T306
Test name
Test status
Simulation time 60956867 ps
CPU time 0.75 seconds
Started Mar 19 02:45:02 PM PDT 24
Finished Mar 19 02:45:03 PM PDT 24
Peak memory 200700 kb
Host smart-49303dfb-ce1e-4ea4-8107-68579d4953b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490333572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1490333572
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.237146378
Short name T47
Test name
Test status
Simulation time 2352679909 ps
CPU time 8.28 seconds
Started Mar 19 02:45:01 PM PDT 24
Finished Mar 19 02:45:09 PM PDT 24
Peak memory 222792 kb
Host smart-4056ebdd-20e4-4914-af2c-2bc07c24dd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237146378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.237146378
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.136499290
Short name T502
Test name
Test status
Simulation time 243958897 ps
CPU time 1.18 seconds
Started Mar 19 02:45:00 PM PDT 24
Finished Mar 19 02:45:01 PM PDT 24
Peak memory 218304 kb
Host smart-c990d4f2-8082-484f-975f-962d7895e192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136499290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.136499290
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3229663246
Short name T434
Test name
Test status
Simulation time 147366337 ps
CPU time 0.87 seconds
Started Mar 19 02:44:53 PM PDT 24
Finished Mar 19 02:44:54 PM PDT 24
Peak memory 200672 kb
Host smart-b8c01e97-d695-43a4-a5ae-d5d505c23b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229663246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3229663246
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.548143873
Short name T352
Test name
Test status
Simulation time 1616119342 ps
CPU time 6.03 seconds
Started Mar 19 02:44:52 PM PDT 24
Finished Mar 19 02:44:58 PM PDT 24
Peak memory 201044 kb
Host smart-7ce411a2-8a19-4626-b7af-5303411041a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548143873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.548143873
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3256756506
Short name T246
Test name
Test status
Simulation time 185610410 ps
CPU time 1.23 seconds
Started Mar 19 02:45:02 PM PDT 24
Finished Mar 19 02:45:04 PM PDT 24
Peak memory 200772 kb
Host smart-84f3505c-d419-407e-8c23-7c589086e83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256756506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3256756506
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1523511643
Short name T508
Test name
Test status
Simulation time 234781392 ps
CPU time 1.49 seconds
Started Mar 19 02:44:56 PM PDT 24
Finished Mar 19 02:44:58 PM PDT 24
Peak memory 201088 kb
Host smart-ccebb114-13d3-49bc-a2cb-c49c88749ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523511643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1523511643
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1694103274
Short name T175
Test name
Test status
Simulation time 1087212480 ps
CPU time 5.88 seconds
Started Mar 19 02:45:00 PM PDT 24
Finished Mar 19 02:45:07 PM PDT 24
Peak memory 201040 kb
Host smart-cdb9bd4d-22cd-462a-964a-1d465d6c073b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694103274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1694103274
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1174883685
Short name T224
Test name
Test status
Simulation time 398024670 ps
CPU time 2.56 seconds
Started Mar 19 02:45:09 PM PDT 24
Finished Mar 19 02:45:12 PM PDT 24
Peak memory 200924 kb
Host smart-cb0332ff-dae4-417f-b84f-4acbf2156e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174883685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1174883685
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1455357335
Short name T264
Test name
Test status
Simulation time 126284085 ps
CPU time 0.98 seconds
Started Mar 19 02:45:00 PM PDT 24
Finished Mar 19 02:45:02 PM PDT 24
Peak memory 200884 kb
Host smart-4ee7d998-6be7-44fe-afe6-eab9e7a51db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455357335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1455357335
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1057454417
Short name T270
Test name
Test status
Simulation time 68818203 ps
CPU time 0.79 seconds
Started Mar 19 02:44:59 PM PDT 24
Finished Mar 19 02:45:01 PM PDT 24
Peak memory 200740 kb
Host smart-a317d7b7-5041-40d1-a4b9-2826f0d659ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057454417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1057454417
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.95115977
Short name T63
Test name
Test status
Simulation time 1901496277 ps
CPU time 7.48 seconds
Started Mar 19 02:45:02 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 217552 kb
Host smart-126b85b8-1cad-4be6-9993-c585d5860e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95115977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.95115977
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.643319475
Short name T40
Test name
Test status
Simulation time 244456822 ps
CPU time 1.13 seconds
Started Mar 19 02:45:06 PM PDT 24
Finished Mar 19 02:45:07 PM PDT 24
Peak memory 218308 kb
Host smart-763a8e36-17fd-445f-ab42-63f931e010a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643319475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.643319475
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.4183262636
Short name T17
Test name
Test status
Simulation time 86896996 ps
CPU time 0.79 seconds
Started Mar 19 02:44:59 PM PDT 24
Finished Mar 19 02:45:01 PM PDT 24
Peak memory 200708 kb
Host smart-09a36093-caee-44e9-a497-473d3ce5a454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183262636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.4183262636
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.484768174
Short name T298
Test name
Test status
Simulation time 1870262232 ps
CPU time 6.73 seconds
Started Mar 19 02:45:06 PM PDT 24
Finished Mar 19 02:45:13 PM PDT 24
Peak memory 201040 kb
Host smart-a3f81e6f-a08f-47b5-8530-d831bfae9e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484768174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.484768174
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3911324408
Short name T454
Test name
Test status
Simulation time 155946567 ps
CPU time 1.21 seconds
Started Mar 19 02:45:08 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 200864 kb
Host smart-f8bfe3a7-0110-4328-8b6c-dd7f67f0f487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911324408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3911324408
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1251878307
Short name T389
Test name
Test status
Simulation time 197607107 ps
CPU time 1.5 seconds
Started Mar 19 02:45:00 PM PDT 24
Finished Mar 19 02:45:02 PM PDT 24
Peak memory 201060 kb
Host smart-7710cc55-6e76-483f-8e5c-3dfa74cc337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251878307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1251878307
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.776233451
Short name T433
Test name
Test status
Simulation time 2834806788 ps
CPU time 14.22 seconds
Started Mar 19 02:45:02 PM PDT 24
Finished Mar 19 02:45:17 PM PDT 24
Peak memory 209696 kb
Host smart-e9dac821-3783-45f1-a369-29d0f8f6ec8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776233451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.776233451
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.431284944
Short name T58
Test name
Test status
Simulation time 131981109 ps
CPU time 1.61 seconds
Started Mar 19 02:45:02 PM PDT 24
Finished Mar 19 02:45:04 PM PDT 24
Peak memory 200952 kb
Host smart-5045672b-99c8-4b52-b29c-cbd0dab7cf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431284944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.431284944
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3830684975
Short name T413
Test name
Test status
Simulation time 81647846 ps
CPU time 0.84 seconds
Started Mar 19 02:45:09 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 200872 kb
Host smart-5c764248-256a-4fd8-a509-53b5894ace40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830684975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3830684975
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2298611037
Short name T85
Test name
Test status
Simulation time 88281594 ps
CPU time 0.84 seconds
Started Mar 19 02:45:00 PM PDT 24
Finished Mar 19 02:45:01 PM PDT 24
Peak memory 200760 kb
Host smart-ff19e2b3-4272-4774-8a46-65f4edc81b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298611037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2298611037
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1545128071
Short name T458
Test name
Test status
Simulation time 2362968684 ps
CPU time 7.92 seconds
Started Mar 19 02:45:01 PM PDT 24
Finished Mar 19 02:45:09 PM PDT 24
Peak memory 218676 kb
Host smart-5b5aaf12-65f4-45ab-8a65-53cdf0cc7861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545128071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1545128071
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2793122914
Short name T430
Test name
Test status
Simulation time 244743985 ps
CPU time 1.03 seconds
Started Mar 19 02:45:04 PM PDT 24
Finished Mar 19 02:45:05 PM PDT 24
Peak memory 218060 kb
Host smart-3c1d0c7e-e4f7-4366-a1a7-257633f8590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793122914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2793122914
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.679711193
Short name T211
Test name
Test status
Simulation time 181447842 ps
CPU time 0.86 seconds
Started Mar 19 02:44:59 PM PDT 24
Finished Mar 19 02:45:01 PM PDT 24
Peak memory 200716 kb
Host smart-822e8f05-7bd6-4ab7-8b92-b8fac850d537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679711193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.679711193
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3473340855
Short name T382
Test name
Test status
Simulation time 1626204631 ps
CPU time 6.48 seconds
Started Mar 19 02:45:01 PM PDT 24
Finished Mar 19 02:45:07 PM PDT 24
Peak memory 201036 kb
Host smart-9bf68a68-9561-46e2-93a2-e277c96b435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473340855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3473340855
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4282597896
Short name T57
Test name
Test status
Simulation time 176234756 ps
CPU time 1.19 seconds
Started Mar 19 02:45:08 PM PDT 24
Finished Mar 19 02:45:09 PM PDT 24
Peak memory 200864 kb
Host smart-415fe4e9-611b-491a-86ca-edde85f3399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282597896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4282597896
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3409840296
Short name T82
Test name
Test status
Simulation time 239118626 ps
CPU time 1.4 seconds
Started Mar 19 02:45:01 PM PDT 24
Finished Mar 19 02:45:03 PM PDT 24
Peak memory 201112 kb
Host smart-3e5cdbb6-4290-4f1d-9869-30030c18fb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409840296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3409840296
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1185845884
Short name T348
Test name
Test status
Simulation time 5017412107 ps
CPU time 18.45 seconds
Started Mar 19 02:45:07 PM PDT 24
Finished Mar 19 02:45:26 PM PDT 24
Peak memory 201188 kb
Host smart-e819c4e2-4ea1-4e9c-b8a3-fb399123c44d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185845884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1185845884
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1871151863
Short name T303
Test name
Test status
Simulation time 385992889 ps
CPU time 2.6 seconds
Started Mar 19 02:45:01 PM PDT 24
Finished Mar 19 02:45:03 PM PDT 24
Peak memory 200908 kb
Host smart-e86240f4-8012-4b5d-a982-ff647d8e8e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871151863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1871151863
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.387477525
Short name T475
Test name
Test status
Simulation time 171522360 ps
CPU time 1.15 seconds
Started Mar 19 02:45:00 PM PDT 24
Finished Mar 19 02:45:02 PM PDT 24
Peak memory 200888 kb
Host smart-e8e646b1-2e43-42aa-a934-f0d23e39c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387477525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.387477525
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2215090139
Short name T242
Test name
Test status
Simulation time 69078556 ps
CPU time 0.77 seconds
Started Mar 19 02:45:06 PM PDT 24
Finished Mar 19 02:45:07 PM PDT 24
Peak memory 200740 kb
Host smart-c4ea63cf-ffd8-4f5d-9798-c6a279401d68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215090139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2215090139
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3656048142
Short name T311
Test name
Test status
Simulation time 2365970769 ps
CPU time 8.36 seconds
Started Mar 19 02:45:13 PM PDT 24
Finished Mar 19 02:45:22 PM PDT 24
Peak memory 217996 kb
Host smart-e85a9523-82b3-4cd7-890a-e6e530c47824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656048142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3656048142
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2017033407
Short name T533
Test name
Test status
Simulation time 244539056 ps
CPU time 1.07 seconds
Started Mar 19 02:45:06 PM PDT 24
Finished Mar 19 02:45:08 PM PDT 24
Peak memory 218180 kb
Host smart-6ed0a6f2-666c-4ef7-9f3c-2600a7add820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017033407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2017033407
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3596858220
Short name T341
Test name
Test status
Simulation time 176957971 ps
CPU time 0.87 seconds
Started Mar 19 02:45:08 PM PDT 24
Finished Mar 19 02:45:09 PM PDT 24
Peak memory 200756 kb
Host smart-ef069fab-8586-402d-9ce3-d589094e224a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596858220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3596858220
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3831537666
Short name T113
Test name
Test status
Simulation time 2229497375 ps
CPU time 8.06 seconds
Started Mar 19 02:45:07 PM PDT 24
Finished Mar 19 02:45:15 PM PDT 24
Peak memory 201220 kb
Host smart-4609ccef-e7ea-4ab9-b1f7-2b082d6f7101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831537666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3831537666
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2511029956
Short name T356
Test name
Test status
Simulation time 109118615 ps
CPU time 1.04 seconds
Started Mar 19 02:45:03 PM PDT 24
Finished Mar 19 02:45:04 PM PDT 24
Peak memory 200808 kb
Host smart-2cd79f0c-0c1e-402c-9abd-ef0dba3dd32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511029956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2511029956
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2933700315
Short name T105
Test name
Test status
Simulation time 208371137 ps
CPU time 1.42 seconds
Started Mar 19 02:45:06 PM PDT 24
Finished Mar 19 02:45:07 PM PDT 24
Peak memory 201048 kb
Host smart-63e7d5d8-0e78-40f3-8187-e06ba204322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933700315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2933700315
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.499670169
Short name T308
Test name
Test status
Simulation time 6928846089 ps
CPU time 25.44 seconds
Started Mar 19 02:45:02 PM PDT 24
Finished Mar 19 02:45:28 PM PDT 24
Peak memory 209440 kb
Host smart-09d15362-ab57-4b14-a578-578b0d57406c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499670169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.499670169
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1593715897
Short name T460
Test name
Test status
Simulation time 110483049 ps
CPU time 1.42 seconds
Started Mar 19 02:45:08 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 200936 kb
Host smart-abff14c7-3cd9-46a6-8e8a-2c473a03afd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593715897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1593715897
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1552255839
Short name T338
Test name
Test status
Simulation time 190244594 ps
CPU time 1.33 seconds
Started Mar 19 02:45:07 PM PDT 24
Finished Mar 19 02:45:08 PM PDT 24
Peak memory 200884 kb
Host smart-e2824d9d-a7f2-4ebf-ab77-12c7d92a24fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552255839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1552255839
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3952690003
Short name T239
Test name
Test status
Simulation time 73983857 ps
CPU time 0.81 seconds
Started Mar 19 02:45:09 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 200732 kb
Host smart-b82069fd-273a-4d33-8f15-64ba6a4bfe95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952690003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3952690003
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3108860684
Short name T265
Test name
Test status
Simulation time 1237873212 ps
CPU time 5.54 seconds
Started Mar 19 02:45:06 PM PDT 24
Finished Mar 19 02:45:11 PM PDT 24
Peak memory 218548 kb
Host smart-9a3a2f8d-6923-488f-8095-965a3db857cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108860684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3108860684
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3800413989
Short name T489
Test name
Test status
Simulation time 244167159 ps
CPU time 1.13 seconds
Started Mar 19 02:45:09 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 218284 kb
Host smart-9cce173e-ad5c-4370-9312-b823558e704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800413989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3800413989
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.396037511
Short name T14
Test name
Test status
Simulation time 112745947 ps
CPU time 0.8 seconds
Started Mar 19 02:45:00 PM PDT 24
Finished Mar 19 02:45:02 PM PDT 24
Peak memory 200668 kb
Host smart-2dce9ee2-80fc-4607-9fa1-dfe3b7a6077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396037511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.396037511
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1081948275
Short name T402
Test name
Test status
Simulation time 820159748 ps
CPU time 4.33 seconds
Started Mar 19 02:45:01 PM PDT 24
Finished Mar 19 02:45:06 PM PDT 24
Peak memory 200996 kb
Host smart-d7d97e59-8977-4483-a9fb-2078d2cdf95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081948275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1081948275
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.245985930
Short name T144
Test name
Test status
Simulation time 96041515 ps
CPU time 0.97 seconds
Started Mar 19 02:45:07 PM PDT 24
Finished Mar 19 02:45:08 PM PDT 24
Peak memory 200884 kb
Host smart-4ff8a255-e1fa-4728-9ce9-0bd43d8f8307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245985930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.245985930
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3721105210
Short name T86
Test name
Test status
Simulation time 118859173 ps
CPU time 1.21 seconds
Started Mar 19 02:45:03 PM PDT 24
Finished Mar 19 02:45:04 PM PDT 24
Peak memory 201036 kb
Host smart-c8314b22-dc13-48a9-bf51-2c0e5a31ab5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721105210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3721105210
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2349943978
Short name T331
Test name
Test status
Simulation time 374571040 ps
CPU time 2.49 seconds
Started Mar 19 02:45:01 PM PDT 24
Finished Mar 19 02:45:05 PM PDT 24
Peak memory 200960 kb
Host smart-58bc2468-9c5f-47de-a0fe-83d417c97198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349943978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2349943978
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1746146151
Short name T292
Test name
Test status
Simulation time 70190538 ps
CPU time 0.79 seconds
Started Mar 19 02:45:08 PM PDT 24
Finished Mar 19 02:45:10 PM PDT 24
Peak memory 200892 kb
Host smart-8f4f73f5-9ec9-4478-a24e-af36b26f070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746146151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1746146151
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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