Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8113

1

T1

19

T6

25

T7

17

auto[1]

10992

1

T1

82

T3

4

T6

21

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5923	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6387	1			T1	27		T2	1		T3	2
reset_info_cp[2]	2976	1			T1	18		T3	1		T6	4
reset_info_cp[4]	3909	1			T1	14		T3	1		T6	14
reset_info_cp[8]	94	1			T6	1		T7	1		T9	2
reset_info_cp[16]	108	1			T1	1		T3	1		T7	1
reset_info_cp[32]	108	1			T7	1		T24	1		T78	1
reset_info_cp[64]	103	1			T24	2		T49	1		T26	1
reset_info_cp[128]	117	1			T1	1		T78	2		T26	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3078	1			T1	19		T6	5		T7	17
reset_info_cp[1]	auto[1]	2689	1			T1	7		T3	1		T6	8
reset_info_cp[2]	auto[0]	915	1			T6	4		T24	8		T35	6
reset_info_cp[2]	auto[1]	2061	1			T1	18		T3	1		T7	20
reset_info_cp[4]	auto[0]	1391	1			T6	5		T24	10		T35	3
reset_info_cp[4]	auto[1]	2518	1			T1	14		T3	1		T6	9
reset_info_cp[8]	auto[0]	40	1			T24	1		T138	1		T82	1
reset_info_cp[8]	auto[1]	54	1			T6	1		T7	1		T9	2
reset_info_cp[16]	auto[0]	45	1			T11	1		T95	1		T129	1
reset_info_cp[16]	auto[1]	63	1			T1	1		T3	1		T7	1
reset_info_cp[32]	auto[0]	51	1			T24	1		T78	1		T83	1
reset_info_cp[32]	auto[1]	57	1			T7	1		T26	1		T92	1
reset_info_cp[64]	auto[0]	37	1			T24	1		T83	1		T139	1
reset_info_cp[64]	auto[1]	66	1			T24	1		T49	1		T26	1
reset_info_cp[128]	auto[0]	43	1			T78	2		T91	1		T82	1
reset_info_cp[128]	auto[1]	74	1			T1	1		T26	1		T60	1