Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T534 /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.554512632 Mar 21 01:30:21 PM PDT 24 Mar 21 01:30:30 PM PDT 24 2188346664 ps
T535 /workspace/coverage/default/27.rstmgr_alert_test.2160376686 Mar 21 01:30:45 PM PDT 24 Mar 21 01:30:46 PM PDT 24 79985151 ps
T536 /workspace/coverage/default/19.rstmgr_por_stretcher.3604094802 Mar 21 01:30:18 PM PDT 24 Mar 21 01:30:19 PM PDT 24 226489622 ps
T537 /workspace/coverage/default/17.rstmgr_stress_all.2523406200 Mar 21 01:30:18 PM PDT 24 Mar 21 01:30:40 PM PDT 24 4691068270 ps
T538 /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3001920534 Mar 21 01:29:21 PM PDT 24 Mar 21 01:29:23 PM PDT 24 178814975 ps
T55 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2378055066 Mar 21 03:23:01 PM PDT 24 Mar 21 03:23:02 PM PDT 24 85279550 ps
T61 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2394202621 Mar 21 03:23:28 PM PDT 24 Mar 21 03:23:31 PM PDT 24 158778804 ps
T56 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.379809559 Mar 21 03:23:02 PM PDT 24 Mar 21 03:23:03 PM PDT 24 176648420 ps
T62 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2903513863 Mar 21 03:23:02 PM PDT 24 Mar 21 03:23:05 PM PDT 24 421991499 ps
T57 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1121594100 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:34 PM PDT 24 871294023 ps
T59 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.526635497 Mar 21 03:23:20 PM PDT 24 Mar 21 03:23:21 PM PDT 24 169818198 ps
T58 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1791467565 Mar 21 03:23:12 PM PDT 24 Mar 21 03:23:13 PM PDT 24 60703900 ps
T85 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1785303252 Mar 21 03:23:03 PM PDT 24 Mar 21 03:23:06 PM PDT 24 390168455 ps
T86 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1818229498 Mar 21 03:23:33 PM PDT 24 Mar 21 03:23:36 PM PDT 24 133416574 ps
T87 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.632331793 Mar 21 03:23:14 PM PDT 24 Mar 21 03:23:16 PM PDT 24 120540458 ps
T88 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4021260118 Mar 21 03:23:28 PM PDT 24 Mar 21 03:23:31 PM PDT 24 256989123 ps
T89 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.636876458 Mar 21 03:23:31 PM PDT 24 Mar 21 03:23:33 PM PDT 24 127985718 ps
T90 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2960579353 Mar 21 03:23:14 PM PDT 24 Mar 21 03:23:17 PM PDT 24 818291431 ps
T539 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1872537103 Mar 21 03:23:03 PM PDT 24 Mar 21 03:23:04 PM PDT 24 91573055 ps
T540 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3034738920 Mar 21 03:23:03 PM PDT 24 Mar 21 03:23:05 PM PDT 24 113742541 ps
T103 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3110043531 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:30 PM PDT 24 74077235 ps
T541 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1689964121 Mar 21 03:23:00 PM PDT 24 Mar 21 03:23:01 PM PDT 24 149869151 ps
T542 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2473299134 Mar 21 03:23:03 PM PDT 24 Mar 21 03:23:04 PM PDT 24 70073109 ps
T104 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1051922222 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:33 PM PDT 24 224690189 ps
T105 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.132883854 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:13 PM PDT 24 131897488 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4053761494 Mar 21 03:23:00 PM PDT 24 Mar 21 03:23:03 PM PDT 24 272653038 ps
T137 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3157945659 Mar 21 03:23:28 PM PDT 24 Mar 21 03:23:29 PM PDT 24 92873015 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1060255035 Mar 21 03:23:00 PM PDT 24 Mar 21 03:23:00 PM PDT 24 84646950 ps
T112 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2837118320 Mar 21 03:23:02 PM PDT 24 Mar 21 03:23:05 PM PDT 24 890498718 ps
T545 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2276942505 Mar 21 03:23:12 PM PDT 24 Mar 21 03:23:15 PM PDT 24 359234716 ps
T546 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.66284408 Mar 21 03:23:20 PM PDT 24 Mar 21 03:23:21 PM PDT 24 123490348 ps
T547 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2582328605 Mar 21 03:23:10 PM PDT 24 Mar 21 03:23:12 PM PDT 24 146777140 ps
T548 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2015132776 Mar 21 03:23:13 PM PDT 24 Mar 21 03:23:15 PM PDT 24 232364810 ps
T549 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3289029470 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:30 PM PDT 24 233070581 ps
T106 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3368364323 Mar 21 03:23:03 PM PDT 24 Mar 21 03:23:04 PM PDT 24 63116451 ps
T113 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1091932605 Mar 21 03:22:59 PM PDT 24 Mar 21 03:23:02 PM PDT 24 490418591 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2247286923 Mar 21 03:22:59 PM PDT 24 Mar 21 03:23:01 PM PDT 24 237533051 ps
T115 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.17214714 Mar 21 03:23:31 PM PDT 24 Mar 21 03:23:34 PM PDT 24 467829319 ps
T551 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2553695193 Mar 21 03:22:59 PM PDT 24 Mar 21 03:23:05 PM PDT 24 492664196 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3886398362 Mar 21 03:22:58 PM PDT 24 Mar 21 03:22:59 PM PDT 24 73331355 ps
T553 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2410361005 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:12 PM PDT 24 124120726 ps
T107 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.758846578 Mar 21 03:23:04 PM PDT 24 Mar 21 03:23:05 PM PDT 24 71280903 ps
T108 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4292015907 Mar 21 03:23:31 PM PDT 24 Mar 21 03:23:33 PM PDT 24 196408625 ps
T109 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.112485822 Mar 21 03:23:33 PM PDT 24 Mar 21 03:23:35 PM PDT 24 133661694 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1229285697 Mar 21 03:22:58 PM PDT 24 Mar 21 03:23:00 PM PDT 24 134481697 ps
T555 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3628485762 Mar 21 03:23:13 PM PDT 24 Mar 21 03:23:16 PM PDT 24 182027871 ps
T110 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3268939542 Mar 21 03:23:14 PM PDT 24 Mar 21 03:23:15 PM PDT 24 83696876 ps
T556 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1844770169 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:13 PM PDT 24 802038810 ps
T557 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.855897088 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:31 PM PDT 24 87163590 ps
T111 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1241724789 Mar 21 03:23:12 PM PDT 24 Mar 21 03:23:14 PM PDT 24 279374123 ps
T558 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3700353628 Mar 21 03:23:31 PM PDT 24 Mar 21 03:23:33 PM PDT 24 130314580 ps
T559 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4112885952 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:32 PM PDT 24 179904132 ps
T560 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.217904521 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:31 PM PDT 24 78911061 ps
T561 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1427696912 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:31 PM PDT 24 137205482 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1271676724 Mar 21 03:23:01 PM PDT 24 Mar 21 03:23:10 PM PDT 24 2025545054 ps
T563 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2872226757 Mar 21 03:23:12 PM PDT 24 Mar 21 03:23:13 PM PDT 24 86988879 ps
T564 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1702081929 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:30 PM PDT 24 75411714 ps
T565 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2325885355 Mar 21 03:23:13 PM PDT 24 Mar 21 03:23:14 PM PDT 24 71828059 ps
T119 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1339683046 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:13 PM PDT 24 429574183 ps
T566 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.164625734 Mar 21 03:23:14 PM PDT 24 Mar 21 03:23:15 PM PDT 24 131159984 ps
T567 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.413103482 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:15 PM PDT 24 662085206 ps
T568 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.586640585 Mar 21 03:22:59 PM PDT 24 Mar 21 03:23:00 PM PDT 24 85563516 ps
T569 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.844689751 Mar 21 03:23:28 PM PDT 24 Mar 21 03:23:30 PM PDT 24 181780132 ps
T114 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3745856927 Mar 21 03:23:31 PM PDT 24 Mar 21 03:23:38 PM PDT 24 2545017402 ps
T120 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4251994859 Mar 21 03:23:14 PM PDT 24 Mar 21 03:23:18 PM PDT 24 875124702 ps
T570 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4237961354 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:33 PM PDT 24 661211170 ps
T571 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1245549928 Mar 21 03:23:10 PM PDT 24 Mar 21 03:23:11 PM PDT 24 289000952 ps
T572 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3734392749 Mar 21 03:23:20 PM PDT 24 Mar 21 03:23:22 PM PDT 24 126081055 ps
T117 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1247755764 Mar 21 03:23:00 PM PDT 24 Mar 21 03:23:03 PM PDT 24 815247876 ps
T573 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.217349734 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:11 PM PDT 24 62104724 ps
T116 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4253364934 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:14 PM PDT 24 871086920 ps
T574 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2173093129 Mar 21 03:23:03 PM PDT 24 Mar 21 03:23:04 PM PDT 24 165571822 ps
T575 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3721450226 Mar 21 03:23:01 PM PDT 24 Mar 21 03:23:02 PM PDT 24 83704928 ps
T576 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2499736411 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:35 PM PDT 24 875571764 ps
T577 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.667694575 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:31 PM PDT 24 125988138 ps
T578 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.919605820 Mar 21 03:23:14 PM PDT 24 Mar 21 03:23:14 PM PDT 24 58856805 ps
T579 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3324434997 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:33 PM PDT 24 244692237 ps
T580 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2128988138 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:31 PM PDT 24 116073427 ps
T581 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3340672164 Mar 21 03:23:02 PM PDT 24 Mar 21 03:23:07 PM PDT 24 492125167 ps
T582 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1122243007 Mar 21 03:23:14 PM PDT 24 Mar 21 03:23:17 PM PDT 24 910381059 ps
T136 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3888912100 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:32 PM PDT 24 451948689 ps
T583 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3411428892 Mar 21 03:23:12 PM PDT 24 Mar 21 03:23:14 PM PDT 24 121538463 ps
T584 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1875535682 Mar 21 03:23:12 PM PDT 24 Mar 21 03:23:15 PM PDT 24 899821610 ps
T585 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3083096825 Mar 21 03:23:12 PM PDT 24 Mar 21 03:23:13 PM PDT 24 143567663 ps
T586 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2098833737 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:12 PM PDT 24 62521507 ps
T587 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3107345761 Mar 21 03:23:03 PM PDT 24 Mar 21 03:23:05 PM PDT 24 103896870 ps
T588 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.263304631 Mar 21 03:23:03 PM PDT 24 Mar 21 03:23:06 PM PDT 24 320986453 ps
T589 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3837717423 Mar 21 03:23:20 PM PDT 24 Mar 21 03:23:21 PM PDT 24 61400558 ps
T590 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3581280791 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:30 PM PDT 24 74705721 ps
T591 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1330680564 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:12 PM PDT 24 132189539 ps
T592 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3088665745 Mar 21 03:22:59 PM PDT 24 Mar 21 03:23:02 PM PDT 24 407991536 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2942465611 Mar 21 03:22:59 PM PDT 24 Mar 21 03:23:01 PM PDT 24 132105611 ps
T594 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.150173234 Mar 21 03:23:31 PM PDT 24 Mar 21 03:23:33 PM PDT 24 122161414 ps
T595 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3633754145 Mar 21 03:23:13 PM PDT 24 Mar 21 03:23:14 PM PDT 24 192621377 ps
T596 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.730373116 Mar 21 03:22:59 PM PDT 24 Mar 21 03:23:00 PM PDT 24 116948479 ps
T597 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.320208117 Mar 21 03:23:00 PM PDT 24 Mar 21 03:23:02 PM PDT 24 252033334 ps
T598 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.77453819 Mar 21 03:23:28 PM PDT 24 Mar 21 03:23:30 PM PDT 24 125742219 ps
T118 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2801313636 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:31 PM PDT 24 487163715 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3654140561 Mar 21 03:23:00 PM PDT 24 Mar 21 03:23:05 PM PDT 24 478400903 ps
T600 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3660476765 Mar 21 03:23:00 PM PDT 24 Mar 21 03:23:03 PM PDT 24 909421996 ps
T601 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4163450230 Mar 21 03:23:12 PM PDT 24 Mar 21 03:23:13 PM PDT 24 77441644 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.668160782 Mar 21 03:23:20 PM PDT 24 Mar 21 03:23:21 PM PDT 24 114903492 ps
T603 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2164218176 Mar 21 03:23:01 PM PDT 24 Mar 21 03:23:03 PM PDT 24 222033516 ps
T604 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1066295024 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:13 PM PDT 24 121776152 ps
T605 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2684318573 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:13 PM PDT 24 182446916 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1794784151 Mar 21 03:23:26 PM PDT 24 Mar 21 03:23:28 PM PDT 24 168613961 ps
T607 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.896578689 Mar 21 03:23:28 PM PDT 24 Mar 21 03:23:29 PM PDT 24 68075190 ps
T608 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1329172273 Mar 21 03:23:29 PM PDT 24 Mar 21 03:23:31 PM PDT 24 410991811 ps
T609 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2664612412 Mar 21 03:23:03 PM PDT 24 Mar 21 03:23:06 PM PDT 24 800444286 ps
T610 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1371285524 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:35 PM PDT 24 556196172 ps
T611 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4197247308 Mar 21 03:23:16 PM PDT 24 Mar 21 03:23:19 PM PDT 24 840738360 ps
T612 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2435097857 Mar 21 03:23:16 PM PDT 24 Mar 21 03:23:17 PM PDT 24 124492337 ps
T613 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4123351971 Mar 21 03:23:12 PM PDT 24 Mar 21 03:23:13 PM PDT 24 174075247 ps
T614 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3893562170 Mar 21 03:23:16 PM PDT 24 Mar 21 03:23:17 PM PDT 24 266708582 ps
T615 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1469719221 Mar 21 03:23:01 PM PDT 24 Mar 21 03:23:03 PM PDT 24 269125367 ps
T616 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3991407568 Mar 21 03:23:30 PM PDT 24 Mar 21 03:23:32 PM PDT 24 141915095 ps
T617 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1575594715 Mar 21 03:23:11 PM PDT 24 Mar 21 03:23:12 PM PDT 24 197493703 ps
T618 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1096196578 Mar 21 03:22:59 PM PDT 24 Mar 21 03:23:00 PM PDT 24 109785912 ps
T619 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2890720614 Mar 21 03:23:28 PM PDT 24 Mar 21 03:23:29 PM PDT 24 78605114 ps
T620 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2108407216 Mar 21 03:23:02 PM PDT 24 Mar 21 03:23:04 PM PDT 24 236707511 ps

Test location /workspace/coverage/default/14.rstmgr_smoke.2844780429
Short name T3
Test name
Test status
Simulation time 234403511 ps
CPU time 1.49 seconds
Started Mar 21 01:30:11 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 201072 kb
Host smart-fc2eb927-813f-4dbf-95a7-17dedfaf1268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844780429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2844780429
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2164997687
Short name T24
Test name
Test status
Simulation time 4008942856 ps
CPU time 16.01 seconds
Started Mar 21 01:29:55 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 210372 kb
Host smart-5defd299-b38c-477c-952a-d7599233236d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164997687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2164997687
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2903513863
Short name T62
Test name
Test status
Simulation time 421991499 ps
CPU time 2.94 seconds
Started Mar 21 03:23:02 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 208784 kb
Host smart-e22aed39-bb6a-4bd8-9019-469a35975c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903513863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2903513863
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3635158610
Short name T67
Test name
Test status
Simulation time 16783412807 ps
CPU time 25.69 seconds
Started Mar 21 01:29:10 PM PDT 24
Finished Mar 21 01:29:36 PM PDT 24
Peak memory 218820 kb
Host smart-c38312fa-51a3-48d8-b58b-d0d48a618414
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635158610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3635158610
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1729208446
Short name T26
Test name
Test status
Simulation time 1227411348 ps
CPU time 5.62 seconds
Started Mar 21 01:30:36 PM PDT 24
Finished Mar 21 01:30:43 PM PDT 24
Peak memory 217968 kb
Host smart-f4f9301e-cf89-4587-a1ce-05d4ee71953e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729208446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1729208446
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.417419364
Short name T2
Test name
Test status
Simulation time 337860908 ps
CPU time 1.98 seconds
Started Mar 21 01:29:36 PM PDT 24
Finished Mar 21 01:29:38 PM PDT 24
Peak memory 200792 kb
Host smart-047bb95d-270d-4c46-8aa7-9c8310c94b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417419364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.417419364
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2960579353
Short name T90
Test name
Test status
Simulation time 818291431 ps
CPU time 2.76 seconds
Started Mar 21 03:23:14 PM PDT 24
Finished Mar 21 03:23:17 PM PDT 24
Peak memory 200680 kb
Host smart-b69c57bb-583d-44b1-a45e-061ec5580c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960579353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2960579353
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4174891260
Short name T10
Test name
Test status
Simulation time 60687999 ps
CPU time 0.76 seconds
Started Mar 21 01:29:12 PM PDT 24
Finished Mar 21 01:29:13 PM PDT 24
Peak memory 200728 kb
Host smart-f1361741-618e-4b55-bd77-a47b842bd3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174891260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4174891260
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1306194841
Short name T139
Test name
Test status
Simulation time 279409746 ps
CPU time 1.58 seconds
Started Mar 21 01:30:13 PM PDT 24
Finished Mar 21 01:30:15 PM PDT 24
Peak memory 200992 kb
Host smart-8f1d5a01-f851-4157-a720-07cb1d49d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306194841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1306194841
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.42667662
Short name T14
Test name
Test status
Simulation time 151873910 ps
CPU time 1.24 seconds
Started Mar 21 01:30:20 PM PDT 24
Finished Mar 21 01:30:22 PM PDT 24
Peak memory 200768 kb
Host smart-3a076f32-f84a-4e64-8c4b-36a0737e1384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42667662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.42667662
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.672006898
Short name T7
Test name
Test status
Simulation time 1225421131 ps
CPU time 5.69 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:26 PM PDT 24
Peak memory 218536 kb
Host smart-41b5b565-a920-4d97-973b-c2393f88028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672006898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.672006898
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2664612412
Short name T609
Test name
Test status
Simulation time 800444286 ps
CPU time 2.81 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:06 PM PDT 24
Peak memory 200708 kb
Host smart-b353634f-f9ce-46e5-b817-3e75039b8f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664612412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2664612412
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3498524392
Short name T95
Test name
Test status
Simulation time 5453454242 ps
CPU time 20.48 seconds
Started Mar 21 01:30:12 PM PDT 24
Finished Mar 21 01:30:33 PM PDT 24
Peak memory 201208 kb
Host smart-0638099f-a460-4950-a3e4-396c39529f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498524392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3498524392
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2053582463
Short name T41
Test name
Test status
Simulation time 1217380088 ps
CPU time 6.13 seconds
Started Mar 21 01:30:02 PM PDT 24
Finished Mar 21 01:30:08 PM PDT 24
Peak memory 230772 kb
Host smart-f232c653-0417-4631-b3c0-28bfe59a5165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053582463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2053582463
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3368364323
Short name T106
Test name
Test status
Simulation time 63116451 ps
CPU time 0.83 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:04 PM PDT 24
Peak memory 200340 kb
Host smart-1c1b2c9f-2d79-4722-a5cf-5188f298d520
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368364323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3368364323
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3426511463
Short name T23
Test name
Test status
Simulation time 174862660 ps
CPU time 0.92 seconds
Started Mar 21 01:29:12 PM PDT 24
Finished Mar 21 01:29:14 PM PDT 24
Peak memory 200716 kb
Host smart-dc2e2fac-86fb-426c-8fd2-ec1bd2688fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426511463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3426511463
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1785303252
Short name T85
Test name
Test status
Simulation time 390168455 ps
CPU time 2.99 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:06 PM PDT 24
Peak memory 208844 kb
Host smart-1d83472a-d7a2-4f0c-84d9-443ba11ec549
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785303252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1785303252
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3013105313
Short name T169
Test name
Test status
Simulation time 124027920 ps
CPU time 1.31 seconds
Started Mar 21 01:30:03 PM PDT 24
Finished Mar 21 01:30:04 PM PDT 24
Peak memory 201060 kb
Host smart-84f16047-fd61-42e5-9d41-1a2900925a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013105313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3013105313
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3088665745
Short name T592
Test name
Test status
Simulation time 407991536 ps
CPU time 2.56 seconds
Started Mar 21 03:22:59 PM PDT 24
Finished Mar 21 03:23:02 PM PDT 24
Peak memory 200612 kb
Host smart-9764ebcb-78f8-4ae0-bbbe-4a98cf48b5d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088665745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
088665745
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2553695193
Short name T551
Test name
Test status
Simulation time 492664196 ps
CPU time 5.87 seconds
Started Mar 21 03:22:59 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 200612 kb
Host smart-04b52ee3-6f05-4238-9142-aaadd972ed0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553695193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
553695193
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1060255035
Short name T544
Test name
Test status
Simulation time 84646950 ps
CPU time 0.84 seconds
Started Mar 21 03:23:00 PM PDT 24
Finished Mar 21 03:23:00 PM PDT 24
Peak memory 200384 kb
Host smart-585ada6d-9fef-434d-8eec-83149d3e80a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060255035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
060255035
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1229285697
Short name T554
Test name
Test status
Simulation time 134481697 ps
CPU time 1.41 seconds
Started Mar 21 03:22:58 PM PDT 24
Finished Mar 21 03:23:00 PM PDT 24
Peak memory 208888 kb
Host smart-1ecf7a61-d671-4eb2-8105-a9555ce5cd2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229285697 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1229285697
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3721450226
Short name T575
Test name
Test status
Simulation time 83704928 ps
CPU time 0.88 seconds
Started Mar 21 03:23:01 PM PDT 24
Finished Mar 21 03:23:02 PM PDT 24
Peak memory 200384 kb
Host smart-76ada7f3-c139-411c-9672-c3d955f67cb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721450226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3721450226
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1469719221
Short name T615
Test name
Test status
Simulation time 269125367 ps
CPU time 1.66 seconds
Started Mar 21 03:23:01 PM PDT 24
Finished Mar 21 03:23:03 PM PDT 24
Peak memory 200584 kb
Host smart-f60e12a2-2685-4332-af34-03da5bb27f49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469719221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1469719221
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1247755764
Short name T117
Test name
Test status
Simulation time 815247876 ps
CPU time 2.8 seconds
Started Mar 21 03:23:00 PM PDT 24
Finished Mar 21 03:23:03 PM PDT 24
Peak memory 200688 kb
Host smart-dd97e065-35df-43eb-950a-26f46dfe30fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247755764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1247755764
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.320208117
Short name T597
Test name
Test status
Simulation time 252033334 ps
CPU time 1.62 seconds
Started Mar 21 03:23:00 PM PDT 24
Finished Mar 21 03:23:02 PM PDT 24
Peak memory 200564 kb
Host smart-7e834763-3a0e-4013-815c-fcd804f87a35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320208117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.320208117
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1271676724
Short name T562
Test name
Test status
Simulation time 2025545054 ps
CPU time 9.41 seconds
Started Mar 21 03:23:01 PM PDT 24
Finished Mar 21 03:23:10 PM PDT 24
Peak memory 200572 kb
Host smart-29dd86c5-09b6-40fe-a914-ec311e5e144a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271676724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
271676724
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.730373116
Short name T596
Test name
Test status
Simulation time 116948479 ps
CPU time 0.88 seconds
Started Mar 21 03:22:59 PM PDT 24
Finished Mar 21 03:23:00 PM PDT 24
Peak memory 200408 kb
Host smart-03708b11-7792-4ae6-b4d8-67b4a5ecb1fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730373116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.730373116
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3034738920
Short name T540
Test name
Test status
Simulation time 113742541 ps
CPU time 1.03 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 200476 kb
Host smart-4d8aa67e-c39b-4b00-bb29-631ee773cad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034738920 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3034738920
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.586640585
Short name T568
Test name
Test status
Simulation time 85563516 ps
CPU time 0.95 seconds
Started Mar 21 03:22:59 PM PDT 24
Finished Mar 21 03:23:00 PM PDT 24
Peak memory 200460 kb
Host smart-64f00d78-ccbd-46f5-a3d4-70bd6d35b9e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586640585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.586640585
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1091932605
Short name T113
Test name
Test status
Simulation time 490418591 ps
CPU time 2.01 seconds
Started Mar 21 03:22:59 PM PDT 24
Finished Mar 21 03:23:02 PM PDT 24
Peak memory 200644 kb
Host smart-3a9599d8-11f3-49ca-9d59-76731b56c1ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091932605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1091932605
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.526635497
Short name T59
Test name
Test status
Simulation time 169818198 ps
CPU time 1.12 seconds
Started Mar 21 03:23:20 PM PDT 24
Finished Mar 21 03:23:21 PM PDT 24
Peak memory 200512 kb
Host smart-d03276e8-4f07-463e-a459-65bb29a9f401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526635497 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.526635497
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2325885355
Short name T565
Test name
Test status
Simulation time 71828059 ps
CPU time 0.8 seconds
Started Mar 21 03:23:13 PM PDT 24
Finished Mar 21 03:23:14 PM PDT 24
Peak memory 200288 kb
Host smart-e83a7c81-635b-4f3e-b6ce-839d3b9016f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325885355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2325885355
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4163450230
Short name T601
Test name
Test status
Simulation time 77441644 ps
CPU time 0.93 seconds
Started Mar 21 03:23:12 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 200400 kb
Host smart-133be945-2827-43bd-a587-ec64780d074f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163450230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.4163450230
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3411428892
Short name T583
Test name
Test status
Simulation time 121538463 ps
CPU time 1.66 seconds
Started Mar 21 03:23:12 PM PDT 24
Finished Mar 21 03:23:14 PM PDT 24
Peak memory 208728 kb
Host smart-fecf5b4f-4e0a-4bf7-82a7-bacc4734feef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411428892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3411428892
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1122243007
Short name T582
Test name
Test status
Simulation time 910381059 ps
CPU time 3.59 seconds
Started Mar 21 03:23:14 PM PDT 24
Finished Mar 21 03:23:17 PM PDT 24
Peak memory 200636 kb
Host smart-4d7a14aa-53a5-4403-97c7-61efd6b61727
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122243007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1122243007
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2582328605
Short name T547
Test name
Test status
Simulation time 146777140 ps
CPU time 1.05 seconds
Started Mar 21 03:23:10 PM PDT 24
Finished Mar 21 03:23:12 PM PDT 24
Peak memory 200440 kb
Host smart-85786ddc-506a-4d3e-a21f-06919c936ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582328605 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2582328605
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.217349734
Short name T573
Test name
Test status
Simulation time 62104724 ps
CPU time 0.78 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:11 PM PDT 24
Peak memory 200380 kb
Host smart-c284b0dd-b174-4d8a-9fe4-debb34ef409e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217349734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.217349734
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.164625734
Short name T566
Test name
Test status
Simulation time 131159984 ps
CPU time 1.12 seconds
Started Mar 21 03:23:14 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 200448 kb
Host smart-932bdcaf-6727-4a3e-8c28-fa9c73b2350c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164625734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.164625734
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2276942505
Short name T545
Test name
Test status
Simulation time 359234716 ps
CPU time 2.57 seconds
Started Mar 21 03:23:12 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 216944 kb
Host smart-910c5cf4-ae40-458b-a76d-b8b3f5ab4e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276942505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2276942505
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4253364934
Short name T116
Test name
Test status
Simulation time 871086920 ps
CPU time 3.18 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:14 PM PDT 24
Peak memory 200692 kb
Host smart-30e844cb-03f4-4b89-947d-6ce98038f2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253364934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4253364934
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.4112885952
Short name T559
Test name
Test status
Simulation time 179904132 ps
CPU time 1.7 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:32 PM PDT 24
Peak memory 208908 kb
Host smart-115cb8d0-2bc8-4e06-9f60-c7e8ce059222
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112885952 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.4112885952
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.919605820
Short name T578
Test name
Test status
Simulation time 58856805 ps
CPU time 0.79 seconds
Started Mar 21 03:23:14 PM PDT 24
Finished Mar 21 03:23:14 PM PDT 24
Peak memory 200312 kb
Host smart-1116f9ea-27b2-4e22-8f6c-a7347ae56d1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919605820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.919605820
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1245549928
Short name T571
Test name
Test status
Simulation time 289000952 ps
CPU time 1.53 seconds
Started Mar 21 03:23:10 PM PDT 24
Finished Mar 21 03:23:11 PM PDT 24
Peak memory 200592 kb
Host smart-5a058b3e-70a7-4fc7-bcf8-822803589ff4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245549928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1245549928
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3628485762
Short name T555
Test name
Test status
Simulation time 182027871 ps
CPU time 2.64 seconds
Started Mar 21 03:23:13 PM PDT 24
Finished Mar 21 03:23:16 PM PDT 24
Peak memory 212252 kb
Host smart-923e4610-6394-4ed3-a04e-7e4f2afa25de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628485762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3628485762
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4251994859
Short name T120
Test name
Test status
Simulation time 875124702 ps
CPU time 3.47 seconds
Started Mar 21 03:23:14 PM PDT 24
Finished Mar 21 03:23:18 PM PDT 24
Peak memory 200680 kb
Host smart-2043a4b1-7711-4954-a39a-9d3512d34d91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251994859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.4251994859
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.77453819
Short name T598
Test name
Test status
Simulation time 125742219 ps
CPU time 1.39 seconds
Started Mar 21 03:23:28 PM PDT 24
Finished Mar 21 03:23:30 PM PDT 24
Peak memory 208936 kb
Host smart-a3485a2d-73ae-4730-8c10-5776784ea14b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77453819 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.77453819
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2890720614
Short name T619
Test name
Test status
Simulation time 78605114 ps
CPU time 0.89 seconds
Started Mar 21 03:23:28 PM PDT 24
Finished Mar 21 03:23:29 PM PDT 24
Peak memory 200404 kb
Host smart-b70c96ad-80ff-4b3f-a020-995856ea3fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890720614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2890720614
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.112485822
Short name T109
Test name
Test status
Simulation time 133661694 ps
CPU time 1.09 seconds
Started Mar 21 03:23:33 PM PDT 24
Finished Mar 21 03:23:35 PM PDT 24
Peak memory 200424 kb
Host smart-a29c0c02-adba-43fc-8dd8-a6ceee8fd320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112485822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.112485822
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1371285524
Short name T610
Test name
Test status
Simulation time 556196172 ps
CPU time 3.77 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:35 PM PDT 24
Peak memory 211624 kb
Host smart-10cc7984-5c71-476b-b700-c07619d8d351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371285524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1371285524
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1121594100
Short name T57
Test name
Test status
Simulation time 871294023 ps
CPU time 3.27 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:34 PM PDT 24
Peak memory 200608 kb
Host smart-741c11fc-0f83-4421-9fea-8d6478bb05fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121594100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1121594100
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3991407568
Short name T616
Test name
Test status
Simulation time 141915095 ps
CPU time 1.16 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:32 PM PDT 24
Peak memory 209736 kb
Host smart-b23ba56a-9857-420b-8328-b1de14d016e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991407568 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3991407568
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3157945659
Short name T137
Test name
Test status
Simulation time 92873015 ps
CPU time 0.91 seconds
Started Mar 21 03:23:28 PM PDT 24
Finished Mar 21 03:23:29 PM PDT 24
Peak memory 200384 kb
Host smart-62073054-ddf8-4a56-b748-b61bd010449e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157945659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3157945659
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1051922222
Short name T104
Test name
Test status
Simulation time 224690189 ps
CPU time 1.64 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:33 PM PDT 24
Peak memory 200608 kb
Host smart-b1ff116f-1c63-4fda-b9c6-54fcae82772c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051922222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1051922222
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2394202621
Short name T61
Test name
Test status
Simulation time 158778804 ps
CPU time 2.22 seconds
Started Mar 21 03:23:28 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 208832 kb
Host smart-84abe1cf-2521-4cf1-8aae-fe9e0e536979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394202621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2394202621
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2499736411
Short name T576
Test name
Test status
Simulation time 875571764 ps
CPU time 3.22 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:35 PM PDT 24
Peak memory 200760 kb
Host smart-17bd44b8-b6fc-4994-b6c0-ed1d5d82b48b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499736411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2499736411
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.844689751
Short name T569
Test name
Test status
Simulation time 181780132 ps
CPU time 1.36 seconds
Started Mar 21 03:23:28 PM PDT 24
Finished Mar 21 03:23:30 PM PDT 24
Peak memory 209864 kb
Host smart-a1830b40-a008-410e-aded-6f4044f4b614
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844689751 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.844689751
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3581280791
Short name T590
Test name
Test status
Simulation time 74705721 ps
CPU time 0.86 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:30 PM PDT 24
Peak memory 200404 kb
Host smart-d3c1ddb9-8ba3-46da-b819-6f06b60a92ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581280791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3581280791
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.667694575
Short name T577
Test name
Test status
Simulation time 125988138 ps
CPU time 1.03 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 200448 kb
Host smart-dbb2c9f6-0435-4a25-8f4d-2228f681e823
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667694575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.667694575
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4237961354
Short name T570
Test name
Test status
Simulation time 661211170 ps
CPU time 4.17 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:33 PM PDT 24
Peak memory 208824 kb
Host smart-88c1fbf4-17f3-47e1-9b48-af9dd7020204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237961354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4237961354
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1329172273
Short name T608
Test name
Test status
Simulation time 410991811 ps
CPU time 1.9 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 200648 kb
Host smart-24c82a32-578d-4aba-8eec-87ca648ae6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329172273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1329172273
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3700353628
Short name T558
Test name
Test status
Simulation time 130314580 ps
CPU time 1.46 seconds
Started Mar 21 03:23:31 PM PDT 24
Finished Mar 21 03:23:33 PM PDT 24
Peak memory 208956 kb
Host smart-2787e2a2-2034-4e9d-9529-97bd8d5d8b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700353628 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3700353628
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.217904521
Short name T560
Test name
Test status
Simulation time 78911061 ps
CPU time 0.88 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 200384 kb
Host smart-291108e6-e578-4a2e-bb1f-34c5169f5cd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217904521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.217904521
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4292015907
Short name T108
Test name
Test status
Simulation time 196408625 ps
CPU time 1.37 seconds
Started Mar 21 03:23:31 PM PDT 24
Finished Mar 21 03:23:33 PM PDT 24
Peak memory 200632 kb
Host smart-0e2720d6-3aac-496c-a073-93c3b70401fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292015907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.4292015907
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1818229498
Short name T86
Test name
Test status
Simulation time 133416574 ps
CPU time 1.89 seconds
Started Mar 21 03:23:33 PM PDT 24
Finished Mar 21 03:23:36 PM PDT 24
Peak memory 208856 kb
Host smart-5a83a618-2ce9-425c-8ab2-6b0c2d6128c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818229498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1818229498
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.17214714
Short name T115
Test name
Test status
Simulation time 467829319 ps
CPU time 2.08 seconds
Started Mar 21 03:23:31 PM PDT 24
Finished Mar 21 03:23:34 PM PDT 24
Peak memory 200684 kb
Host smart-9595664c-70ff-4862-a4a9-df0bdaeb5347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17214714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.17214714
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1427696912
Short name T561
Test name
Test status
Simulation time 137205482 ps
CPU time 1.17 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 200788 kb
Host smart-92727d47-e7b6-4ad9-9ce8-813c32bb7205
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427696912 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1427696912
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.896578689
Short name T607
Test name
Test status
Simulation time 68075190 ps
CPU time 0.81 seconds
Started Mar 21 03:23:28 PM PDT 24
Finished Mar 21 03:23:29 PM PDT 24
Peak memory 200380 kb
Host smart-c15f8bb1-5e4b-49a9-bca0-2b7fd22b3829
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896578689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.896578689
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3324434997
Short name T579
Test name
Test status
Simulation time 244692237 ps
CPU time 1.71 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:33 PM PDT 24
Peak memory 200620 kb
Host smart-177cdd71-7bb8-4ddf-a7c8-58c23c62f7ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324434997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3324434997
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4021260118
Short name T88
Test name
Test status
Simulation time 256989123 ps
CPU time 2.12 seconds
Started Mar 21 03:23:28 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 208828 kb
Host smart-e50be1f7-2fb9-4d9d-855f-bb14135a0b69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021260118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4021260118
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3745856927
Short name T114
Test name
Test status
Simulation time 2545017402 ps
CPU time 6.02 seconds
Started Mar 21 03:23:31 PM PDT 24
Finished Mar 21 03:23:38 PM PDT 24
Peak memory 200756 kb
Host smart-103e1a0d-4ee1-4244-9acc-1f2f15e806db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745856927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3745856927
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1794784151
Short name T606
Test name
Test status
Simulation time 168613961 ps
CPU time 1.6 seconds
Started Mar 21 03:23:26 PM PDT 24
Finished Mar 21 03:23:28 PM PDT 24
Peak memory 208912 kb
Host smart-f36ca480-01f9-4d9f-8296-e9b4c0db7ca1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794784151 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1794784151
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.855897088
Short name T557
Test name
Test status
Simulation time 87163590 ps
CPU time 0.91 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 200388 kb
Host smart-3b350e9b-e72e-42e6-a889-fce34c47807d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855897088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.855897088
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3110043531
Short name T103
Test name
Test status
Simulation time 74077235 ps
CPU time 0.95 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:30 PM PDT 24
Peak memory 200448 kb
Host smart-8c4f9124-c35b-4320-b87a-716717c01a7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110043531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3110043531
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3289029470
Short name T549
Test name
Test status
Simulation time 233070581 ps
CPU time 1.7 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:30 PM PDT 24
Peak memory 211012 kb
Host smart-3e3c1bba-b8a4-4bf3-a58f-761ab6f5b9d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289029470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3289029470
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2801313636
Short name T118
Test name
Test status
Simulation time 487163715 ps
CPU time 2.13 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 200540 kb
Host smart-7e078761-b642-4cb4-bfcf-120f87a2f334
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801313636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2801313636
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.636876458
Short name T89
Test name
Test status
Simulation time 127985718 ps
CPU time 1.04 seconds
Started Mar 21 03:23:31 PM PDT 24
Finished Mar 21 03:23:33 PM PDT 24
Peak memory 200504 kb
Host smart-3bb62719-9bcc-449d-9fcb-cb9e29410285
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636876458 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.636876458
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1702081929
Short name T564
Test name
Test status
Simulation time 75411714 ps
CPU time 0.83 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:30 PM PDT 24
Peak memory 200284 kb
Host smart-449172af-a3c6-4c97-b919-4de4e0d37929
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702081929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1702081929
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.150173234
Short name T594
Test name
Test status
Simulation time 122161414 ps
CPU time 1.12 seconds
Started Mar 21 03:23:31 PM PDT 24
Finished Mar 21 03:23:33 PM PDT 24
Peak memory 200444 kb
Host smart-f31dfbe4-545d-4fa1-8ff6-6337383d40e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150173234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.150173234
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2128988138
Short name T580
Test name
Test status
Simulation time 116073427 ps
CPU time 1.59 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 208884 kb
Host smart-66282fce-0399-45d4-af4a-1dec885b9bea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128988138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2128988138
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3888912100
Short name T136
Test name
Test status
Simulation time 451948689 ps
CPU time 1.81 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:32 PM PDT 24
Peak memory 200644 kb
Host smart-dd3a3315-c36f-4921-807d-6c20d4440c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888912100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3888912100
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2164218176
Short name T603
Test name
Test status
Simulation time 222033516 ps
CPU time 1.71 seconds
Started Mar 21 03:23:01 PM PDT 24
Finished Mar 21 03:23:03 PM PDT 24
Peak memory 200620 kb
Host smart-55765217-8278-4bb1-9f3f-c52b31d7e47f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164218176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
164218176
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3654140561
Short name T599
Test name
Test status
Simulation time 478400903 ps
CPU time 5.72 seconds
Started Mar 21 03:23:00 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 200580 kb
Host smart-3d4db8d2-db88-4d44-b94c-763adabcfd0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654140561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
654140561
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1872537103
Short name T539
Test name
Test status
Simulation time 91573055 ps
CPU time 0.81 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:04 PM PDT 24
Peak memory 200316 kb
Host smart-4a03ccd4-f49d-40a4-a715-08fe7051e04c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872537103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
872537103
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.379809559
Short name T56
Test name
Test status
Simulation time 176648420 ps
CPU time 1.21 seconds
Started Mar 21 03:23:02 PM PDT 24
Finished Mar 21 03:23:03 PM PDT 24
Peak memory 210004 kb
Host smart-6f6d4cfa-b734-4577-a03b-081ff51121a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379809559 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.379809559
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3886398362
Short name T552
Test name
Test status
Simulation time 73331355 ps
CPU time 0.85 seconds
Started Mar 21 03:22:58 PM PDT 24
Finished Mar 21 03:22:59 PM PDT 24
Peak memory 200360 kb
Host smart-973eb005-1262-4377-9151-f23319cabb3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886398362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3886398362
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2942465611
Short name T593
Test name
Test status
Simulation time 132105611 ps
CPU time 1.29 seconds
Started Mar 21 03:22:59 PM PDT 24
Finished Mar 21 03:23:01 PM PDT 24
Peak memory 200652 kb
Host smart-dfff2b7e-42d0-4f44-b354-f6635298d5fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942465611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2942465611
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3107345761
Short name T587
Test name
Test status
Simulation time 103896870 ps
CPU time 1.66 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 208828 kb
Host smart-83eb9381-0e7e-4fb1-b7e5-8d93f939b45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107345761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3107345761
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2837118320
Short name T112
Test name
Test status
Simulation time 890498718 ps
CPU time 3.07 seconds
Started Mar 21 03:23:02 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 200636 kb
Host smart-331a1796-9c94-4cee-a713-bda319dec194
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837118320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2837118320
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1096196578
Short name T618
Test name
Test status
Simulation time 109785912 ps
CPU time 1.32 seconds
Started Mar 21 03:22:59 PM PDT 24
Finished Mar 21 03:23:00 PM PDT 24
Peak memory 200532 kb
Host smart-465cd878-d4d0-46df-be9c-ab2fd6118ee6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096196578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
096196578
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3340672164
Short name T581
Test name
Test status
Simulation time 492125167 ps
CPU time 5.77 seconds
Started Mar 21 03:23:02 PM PDT 24
Finished Mar 21 03:23:07 PM PDT 24
Peak memory 200592 kb
Host smart-db68285e-f587-44b0-86ae-eccc0033888d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340672164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
340672164
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2378055066
Short name T55
Test name
Test status
Simulation time 85279550 ps
CPU time 0.82 seconds
Started Mar 21 03:23:01 PM PDT 24
Finished Mar 21 03:23:02 PM PDT 24
Peak memory 200360 kb
Host smart-0da4e4db-a8be-4b17-b2a2-21d6a3b1ce95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378055066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
378055066
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2173093129
Short name T574
Test name
Test status
Simulation time 165571822 ps
CPU time 1.13 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:04 PM PDT 24
Peak memory 200536 kb
Host smart-1cc7fae6-619a-4632-927e-caa66dc95158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173093129 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2173093129
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2473299134
Short name T542
Test name
Test status
Simulation time 70073109 ps
CPU time 0.73 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:04 PM PDT 24
Peak memory 200300 kb
Host smart-43726a65-0be6-4617-ade8-38df21e50276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473299134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2473299134
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2108407216
Short name T620
Test name
Test status
Simulation time 236707511 ps
CPU time 1.59 seconds
Started Mar 21 03:23:02 PM PDT 24
Finished Mar 21 03:23:04 PM PDT 24
Peak memory 200612 kb
Host smart-c39a57ac-4346-4c67-9c44-1cb75390c1e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108407216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2108407216
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.263304631
Short name T588
Test name
Test status
Simulation time 320986453 ps
CPU time 2.39 seconds
Started Mar 21 03:23:03 PM PDT 24
Finished Mar 21 03:23:06 PM PDT 24
Peak memory 200684 kb
Host smart-0033c3b5-69b8-482e-a733-67e3bea0b9db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263304631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.263304631
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3660476765
Short name T600
Test name
Test status
Simulation time 909421996 ps
CPU time 3.1 seconds
Started Mar 21 03:23:00 PM PDT 24
Finished Mar 21 03:23:03 PM PDT 24
Peak memory 200708 kb
Host smart-a400d64c-6f70-4b07-ae6f-87623a3c876e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660476765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3660476765
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.668160782
Short name T602
Test name
Test status
Simulation time 114903492 ps
CPU time 1.41 seconds
Started Mar 21 03:23:20 PM PDT 24
Finished Mar 21 03:23:21 PM PDT 24
Peak memory 208672 kb
Host smart-408276cb-2238-4395-9e10-063b09db3d7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668160782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.668160782
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4053761494
Short name T543
Test name
Test status
Simulation time 272653038 ps
CPU time 3.38 seconds
Started Mar 21 03:23:00 PM PDT 24
Finished Mar 21 03:23:03 PM PDT 24
Peak memory 200572 kb
Host smart-b9b72809-dca7-41f2-a8c2-dc6dbcdbe253
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053761494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
053761494
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1689964121
Short name T541
Test name
Test status
Simulation time 149869151 ps
CPU time 0.97 seconds
Started Mar 21 03:23:00 PM PDT 24
Finished Mar 21 03:23:01 PM PDT 24
Peak memory 200400 kb
Host smart-7f4ea0b3-76cd-45d9-8e91-339826581661
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689964121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
689964121
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2410361005
Short name T553
Test name
Test status
Simulation time 124120726 ps
CPU time 1 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:12 PM PDT 24
Peak memory 200520 kb
Host smart-2c03a51c-fdba-42a9-bb10-90df3c6f1fd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410361005 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2410361005
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.758846578
Short name T107
Test name
Test status
Simulation time 71280903 ps
CPU time 0.88 seconds
Started Mar 21 03:23:04 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 200356 kb
Host smart-b2618c8d-40ba-43a9-8b0b-3a824ced6285
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758846578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.758846578
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.132883854
Short name T105
Test name
Test status
Simulation time 131897488 ps
CPU time 1.04 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 200460 kb
Host smart-28eb36eb-3ae0-499a-b20a-f32832f64e51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132883854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.132883854
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2247286923
Short name T550
Test name
Test status
Simulation time 237533051 ps
CPU time 1.87 seconds
Started Mar 21 03:22:59 PM PDT 24
Finished Mar 21 03:23:01 PM PDT 24
Peak memory 208920 kb
Host smart-2844d142-7cb6-41d4-b4e8-0bf81a771d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247286923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2247286923
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1575594715
Short name T617
Test name
Test status
Simulation time 197493703 ps
CPU time 1.43 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:12 PM PDT 24
Peak memory 208760 kb
Host smart-577c1f92-ff44-499b-8260-020e9bcaddd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575594715 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1575594715
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1791467565
Short name T58
Test name
Test status
Simulation time 60703900 ps
CPU time 0.79 seconds
Started Mar 21 03:23:12 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 200328 kb
Host smart-b474f588-1942-41ab-90a9-afd535d1d249
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791467565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1791467565
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3083096825
Short name T585
Test name
Test status
Simulation time 143567663 ps
CPU time 1.11 seconds
Started Mar 21 03:23:12 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 200444 kb
Host smart-fa6115d9-b597-448b-9e61-e2fc02db937e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083096825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3083096825
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3734392749
Short name T572
Test name
Test status
Simulation time 126081055 ps
CPU time 1.72 seconds
Started Mar 21 03:23:20 PM PDT 24
Finished Mar 21 03:23:22 PM PDT 24
Peak memory 208796 kb
Host smart-66682bf6-2169-4b64-977a-eee68101fea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734392749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3734392749
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1844770169
Short name T556
Test name
Test status
Simulation time 802038810 ps
CPU time 2.52 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 200696 kb
Host smart-33a2831f-51b0-49a6-ba66-417d79271c78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844770169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1844770169
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.66284408
Short name T546
Test name
Test status
Simulation time 123490348 ps
CPU time 1.4 seconds
Started Mar 21 03:23:20 PM PDT 24
Finished Mar 21 03:23:21 PM PDT 24
Peak memory 208592 kb
Host smart-47675fee-aea3-42e3-b97d-b88ab667d02e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66284408 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.66284408
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3837717423
Short name T589
Test name
Test status
Simulation time 61400558 ps
CPU time 0.76 seconds
Started Mar 21 03:23:20 PM PDT 24
Finished Mar 21 03:23:21 PM PDT 24
Peak memory 200380 kb
Host smart-5c1da40a-4141-45fd-bb2e-fa658490be07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837717423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3837717423
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2435097857
Short name T612
Test name
Test status
Simulation time 124492337 ps
CPU time 1.26 seconds
Started Mar 21 03:23:16 PM PDT 24
Finished Mar 21 03:23:17 PM PDT 24
Peak memory 200636 kb
Host smart-9bae14e7-12ab-4405-b740-bd45083f8324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435097857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2435097857
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2015132776
Short name T548
Test name
Test status
Simulation time 232364810 ps
CPU time 1.88 seconds
Started Mar 21 03:23:13 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 208888 kb
Host smart-0d8529ad-f744-4f4b-9c52-eb0bc9265d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015132776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2015132776
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1875535682
Short name T584
Test name
Test status
Simulation time 899821610 ps
CPU time 3.31 seconds
Started Mar 21 03:23:12 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 200660 kb
Host smart-32a898c3-169f-414a-a9eb-f6e3b66e2652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875535682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1875535682
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2684318573
Short name T605
Test name
Test status
Simulation time 182446916 ps
CPU time 1.74 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 208968 kb
Host smart-38993d1d-5c5b-4b71-a9ea-406e0ccdd288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684318573 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2684318573
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3268939542
Short name T110
Test name
Test status
Simulation time 83696876 ps
CPU time 0.9 seconds
Started Mar 21 03:23:14 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 200384 kb
Host smart-1599d7ee-c4c4-4b42-a9fe-501841617f92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268939542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3268939542
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1241724789
Short name T111
Test name
Test status
Simulation time 279374123 ps
CPU time 1.63 seconds
Started Mar 21 03:23:12 PM PDT 24
Finished Mar 21 03:23:14 PM PDT 24
Peak memory 200644 kb
Host smart-f791dd81-0389-45c8-9299-b0ebf0ca2b0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241724789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1241724789
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.413103482
Short name T567
Test name
Test status
Simulation time 662085206 ps
CPU time 4.55 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 208744 kb
Host smart-b9279c48-1d0e-44e7-bbdb-0c165aceafd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413103482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.413103482
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3633754145
Short name T595
Test name
Test status
Simulation time 192621377 ps
CPU time 1.23 seconds
Started Mar 21 03:23:13 PM PDT 24
Finished Mar 21 03:23:14 PM PDT 24
Peak memory 208540 kb
Host smart-edd8ae3b-77e2-4f88-b35f-8221ef1dc794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633754145 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3633754145
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2872226757
Short name T563
Test name
Test status
Simulation time 86988879 ps
CPU time 0.86 seconds
Started Mar 21 03:23:12 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 200404 kb
Host smart-6fdc0ff2-fcd2-406c-873f-c31a8d1e48cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872226757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2872226757
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3893562170
Short name T614
Test name
Test status
Simulation time 266708582 ps
CPU time 1.67 seconds
Started Mar 21 03:23:16 PM PDT 24
Finished Mar 21 03:23:17 PM PDT 24
Peak memory 200680 kb
Host smart-b989e88b-8c97-487f-bc91-64f825485a4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893562170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3893562170
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.632331793
Short name T87
Test name
Test status
Simulation time 120540458 ps
CPU time 1.6 seconds
Started Mar 21 03:23:14 PM PDT 24
Finished Mar 21 03:23:16 PM PDT 24
Peak memory 211988 kb
Host smart-de1b959d-86bb-493e-8b24-842d56980941
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632331793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.632331793
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1339683046
Short name T119
Test name
Test status
Simulation time 429574183 ps
CPU time 1.81 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 200640 kb
Host smart-2dd47721-b3e3-43f3-88ee-b2eadfae4f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339683046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1339683046
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1330680564
Short name T591
Test name
Test status
Simulation time 132189539 ps
CPU time 1.08 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:12 PM PDT 24
Peak memory 200512 kb
Host smart-f33fdcde-e186-461c-b2dc-da205d352527
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330680564 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1330680564
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2098833737
Short name T586
Test name
Test status
Simulation time 62521507 ps
CPU time 0.83 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:12 PM PDT 24
Peak memory 200360 kb
Host smart-0e7190bc-d589-4ddc-96db-b347c978e9fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098833737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2098833737
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1066295024
Short name T604
Test name
Test status
Simulation time 121776152 ps
CPU time 1.05 seconds
Started Mar 21 03:23:11 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 200460 kb
Host smart-e800a4a1-7aa7-4765-96f0-92765c8834b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066295024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1066295024
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4123351971
Short name T613
Test name
Test status
Simulation time 174075247 ps
CPU time 1.42 seconds
Started Mar 21 03:23:12 PM PDT 24
Finished Mar 21 03:23:13 PM PDT 24
Peak memory 208640 kb
Host smart-f8872864-dfd7-4646-8f2e-b43e9a84f693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123351971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4123351971
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4197247308
Short name T611
Test name
Test status
Simulation time 840738360 ps
CPU time 2.55 seconds
Started Mar 21 03:23:16 PM PDT 24
Finished Mar 21 03:23:19 PM PDT 24
Peak memory 200616 kb
Host smart-f0bcc673-78e4-42fa-a929-da2d6961b6e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197247308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.4197247308
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3912499594
Short name T285
Test name
Test status
Simulation time 1212914509 ps
CPU time 6.31 seconds
Started Mar 21 01:29:12 PM PDT 24
Finished Mar 21 01:29:19 PM PDT 24
Peak memory 218100 kb
Host smart-5ca3d1c3-4b34-4a8d-9f7a-d3427b72db2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912499594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3912499594
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.505189262
Short name T449
Test name
Test status
Simulation time 245124387 ps
CPU time 1.15 seconds
Started Mar 21 01:29:13 PM PDT 24
Finished Mar 21 01:29:15 PM PDT 24
Peak memory 218044 kb
Host smart-d531c1d9-b6b4-4239-9e7a-be6f90169ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505189262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.505189262
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1423194891
Short name T216
Test name
Test status
Simulation time 131322660 ps
CPU time 0.84 seconds
Started Mar 21 01:29:05 PM PDT 24
Finished Mar 21 01:29:06 PM PDT 24
Peak memory 200656 kb
Host smart-689827f6-876e-48fd-9b05-93d6c1885a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423194891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1423194891
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3522722923
Short name T397
Test name
Test status
Simulation time 1442329979 ps
CPU time 5.48 seconds
Started Mar 21 01:29:02 PM PDT 24
Finished Mar 21 01:29:08 PM PDT 24
Peak memory 201020 kb
Host smart-65195c14-be70-40d9-a170-e7b375fd1094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522722923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3522722923
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.209434664
Short name T164
Test name
Test status
Simulation time 101949147 ps
CPU time 1 seconds
Started Mar 21 01:29:12 PM PDT 24
Finished Mar 21 01:29:14 PM PDT 24
Peak memory 200824 kb
Host smart-e4292e5a-8093-4e61-aa97-bf948e9edc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209434664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.209434664
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3675003689
Short name T311
Test name
Test status
Simulation time 226276086 ps
CPU time 1.45 seconds
Started Mar 21 01:29:03 PM PDT 24
Finished Mar 21 01:29:05 PM PDT 24
Peak memory 200928 kb
Host smart-988e5df9-98cc-4aa9-aa67-d14899b0a80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675003689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3675003689
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2273818719
Short name T254
Test name
Test status
Simulation time 2838141622 ps
CPU time 10.75 seconds
Started Mar 21 01:29:12 PM PDT 24
Finished Mar 21 01:29:23 PM PDT 24
Peak memory 210616 kb
Host smart-1fbe877e-b6f2-4a39-9eaa-4de25631a3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273818719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2273818719
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1247327602
Short name T531
Test name
Test status
Simulation time 321909088 ps
CPU time 2.12 seconds
Started Mar 21 01:29:04 PM PDT 24
Finished Mar 21 01:29:07 PM PDT 24
Peak memory 200904 kb
Host smart-5727e00f-aa96-4b14-a3ac-fe64bff9b2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247327602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1247327602
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.4220087565
Short name T78
Test name
Test status
Simulation time 165747698 ps
CPU time 1.2 seconds
Started Mar 21 01:29:03 PM PDT 24
Finished Mar 21 01:29:04 PM PDT 24
Peak memory 201064 kb
Host smart-5ea01dd1-d98f-4c56-9791-cc5c85d46555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220087565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.4220087565
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4045659071
Short name T317
Test name
Test status
Simulation time 76075521 ps
CPU time 0.78 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:21 PM PDT 24
Peak memory 200720 kb
Host smart-f8e324a4-bbb5-4f0f-b4b1-e6f8b73a8b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045659071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4045659071
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.749656295
Short name T44
Test name
Test status
Simulation time 1888123903 ps
CPU time 7.71 seconds
Started Mar 21 01:29:11 PM PDT 24
Finished Mar 21 01:29:19 PM PDT 24
Peak memory 218004 kb
Host smart-85fe883f-cbbd-4c4f-a122-372cb01b27a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749656295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.749656295
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1222302031
Short name T336
Test name
Test status
Simulation time 244529091 ps
CPU time 1.09 seconds
Started Mar 21 01:29:11 PM PDT 24
Finished Mar 21 01:29:13 PM PDT 24
Peak memory 218100 kb
Host smart-62c7104f-2ff6-4b91-b9bc-1ab5dab5b850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222302031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1222302031
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1262919895
Short name T432
Test name
Test status
Simulation time 1620713249 ps
CPU time 6.33 seconds
Started Mar 21 01:29:11 PM PDT 24
Finished Mar 21 01:29:18 PM PDT 24
Peak memory 200972 kb
Host smart-da874f52-8207-4c69-acbb-ce75474e4600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262919895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1262919895
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1319821006
Short name T65
Test name
Test status
Simulation time 8413424263 ps
CPU time 13.53 seconds
Started Mar 21 01:29:19 PM PDT 24
Finished Mar 21 01:29:33 PM PDT 24
Peak memory 217592 kb
Host smart-b7b19f9c-9f79-4369-94fa-48e57b57bd4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319821006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1319821006
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3291429285
Short name T151
Test name
Test status
Simulation time 102111682 ps
CPU time 0.99 seconds
Started Mar 21 01:29:12 PM PDT 24
Finished Mar 21 01:29:13 PM PDT 24
Peak memory 200776 kb
Host smart-e1678b20-1fe9-4e8e-8f80-08d2a03ec737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291429285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3291429285
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2052106603
Short name T205
Test name
Test status
Simulation time 111032147 ps
CPU time 1.14 seconds
Started Mar 21 01:29:11 PM PDT 24
Finished Mar 21 01:29:12 PM PDT 24
Peak memory 201044 kb
Host smart-f79c3fcb-9d1e-4c78-bf46-533b3513bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052106603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2052106603
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.933859069
Short name T326
Test name
Test status
Simulation time 5496611519 ps
CPU time 27.48 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:48 PM PDT 24
Peak memory 201156 kb
Host smart-cf21850a-6d37-438a-89ba-93957431ca9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933859069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.933859069
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3749644707
Short name T207
Test name
Test status
Simulation time 130445586 ps
CPU time 1.74 seconds
Started Mar 21 01:29:11 PM PDT 24
Finished Mar 21 01:29:13 PM PDT 24
Peak memory 209132 kb
Host smart-d5ea4974-3038-4357-bd59-20127d356d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749644707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3749644707
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1301570221
Short name T301
Test name
Test status
Simulation time 125659145 ps
CPU time 0.92 seconds
Started Mar 21 01:29:11 PM PDT 24
Finished Mar 21 01:29:12 PM PDT 24
Peak memory 200864 kb
Host smart-7436b9e5-c1d3-4f7e-87c1-a34fd3fe6814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301570221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1301570221
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3695648078
Short name T484
Test name
Test status
Simulation time 55787541 ps
CPU time 0.84 seconds
Started Mar 21 01:29:57 PM PDT 24
Finished Mar 21 01:29:58 PM PDT 24
Peak memory 200740 kb
Host smart-9148b4ab-eadd-487a-9ee3-6fcd5f50f98f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695648078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3695648078
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1966473913
Short name T34
Test name
Test status
Simulation time 2176930172 ps
CPU time 8.4 seconds
Started Mar 21 01:29:56 PM PDT 24
Finished Mar 21 01:30:04 PM PDT 24
Peak memory 218664 kb
Host smart-6e043299-8520-44be-b9bb-db68596d8bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966473913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1966473913
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3305971436
Short name T197
Test name
Test status
Simulation time 244791042 ps
CPU time 1.2 seconds
Started Mar 21 01:29:55 PM PDT 24
Finished Mar 21 01:29:56 PM PDT 24
Peak memory 218136 kb
Host smart-2e0c4541-06be-413e-8e7a-676317060035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305971436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3305971436
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.846911338
Short name T367
Test name
Test status
Simulation time 150537398 ps
CPU time 0.84 seconds
Started Mar 21 01:29:54 PM PDT 24
Finished Mar 21 01:29:55 PM PDT 24
Peak memory 200652 kb
Host smart-2c1abc64-d3ad-4dc9-b14d-c866508ac27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846911338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.846911338
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.313810166
Short name T430
Test name
Test status
Simulation time 1248990258 ps
CPU time 5.18 seconds
Started Mar 21 01:29:55 PM PDT 24
Finished Mar 21 01:30:00 PM PDT 24
Peak memory 201016 kb
Host smart-d8e58b82-406f-484b-8423-71582de71325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313810166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.313810166
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.103353345
Short name T479
Test name
Test status
Simulation time 110904864 ps
CPU time 0.97 seconds
Started Mar 21 01:29:54 PM PDT 24
Finished Mar 21 01:29:55 PM PDT 24
Peak memory 200816 kb
Host smart-92dfbb27-81fe-4fce-b438-227700019a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103353345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.103353345
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.545827821
Short name T161
Test name
Test status
Simulation time 203862602 ps
CPU time 1.53 seconds
Started Mar 21 01:29:54 PM PDT 24
Finished Mar 21 01:29:56 PM PDT 24
Peak memory 200968 kb
Host smart-46549d5f-5719-4e5b-bc66-821fa78c8a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545827821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.545827821
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2529383837
Short name T68
Test name
Test status
Simulation time 4436981623 ps
CPU time 18.97 seconds
Started Mar 21 01:29:55 PM PDT 24
Finished Mar 21 01:30:14 PM PDT 24
Peak memory 201148 kb
Host smart-c53476a8-e7f7-452d-bcdd-f9255a88dfd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529383837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2529383837
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3035677237
Short name T221
Test name
Test status
Simulation time 358574619 ps
CPU time 2.43 seconds
Started Mar 21 01:29:57 PM PDT 24
Finished Mar 21 01:30:00 PM PDT 24
Peak memory 200872 kb
Host smart-4fda263c-092f-435f-b2de-57219371f262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035677237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3035677237
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4196189335
Short name T233
Test name
Test status
Simulation time 174483458 ps
CPU time 1.23 seconds
Started Mar 21 01:29:56 PM PDT 24
Finished Mar 21 01:29:57 PM PDT 24
Peak memory 200780 kb
Host smart-75da0857-5c82-4dd7-9462-638bbd5295be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196189335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4196189335
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1512464257
Short name T522
Test name
Test status
Simulation time 67999284 ps
CPU time 0.75 seconds
Started Mar 21 01:30:04 PM PDT 24
Finished Mar 21 01:30:05 PM PDT 24
Peak memory 200704 kb
Host smart-0cd412ea-bb98-41f4-aa32-9d1f84ca1920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512464257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1512464257
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2696145271
Short name T36
Test name
Test status
Simulation time 2370960175 ps
CPU time 7.96 seconds
Started Mar 21 01:30:03 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 217792 kb
Host smart-ceb12cf3-e7ff-404f-9431-123fecf76688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696145271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2696145271
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1600501300
Short name T196
Test name
Test status
Simulation time 244365611 ps
CPU time 1.08 seconds
Started Mar 21 01:30:05 PM PDT 24
Finished Mar 21 01:30:06 PM PDT 24
Peak memory 218080 kb
Host smart-d9f71f44-0efe-47ef-a7cd-61fd0b4956fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600501300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1600501300
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2647267455
Short name T229
Test name
Test status
Simulation time 141623626 ps
CPU time 0.84 seconds
Started Mar 21 01:30:18 PM PDT 24
Finished Mar 21 01:30:18 PM PDT 24
Peak memory 200704 kb
Host smart-3090385a-c537-41c2-953b-99e7ffaffa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647267455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2647267455
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.862482688
Short name T461
Test name
Test status
Simulation time 881702720 ps
CPU time 4.18 seconds
Started Mar 21 01:30:05 PM PDT 24
Finished Mar 21 01:30:09 PM PDT 24
Peak memory 201064 kb
Host smart-c202ab73-a3a3-4e4f-803a-550d0816cbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862482688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.862482688
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.788846493
Short name T424
Test name
Test status
Simulation time 181706543 ps
CPU time 1.39 seconds
Started Mar 21 01:30:03 PM PDT 24
Finished Mar 21 01:30:05 PM PDT 24
Peak memory 200824 kb
Host smart-e0ca5de1-98c7-409a-b4dc-4b9708d594cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788846493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.788846493
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1625880360
Short name T316
Test name
Test status
Simulation time 255328293 ps
CPU time 1.64 seconds
Started Mar 21 01:29:56 PM PDT 24
Finished Mar 21 01:29:58 PM PDT 24
Peak memory 201048 kb
Host smart-283219d9-edfa-411c-8d64-8e47c74b1a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625880360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1625880360
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2546187186
Short name T218
Test name
Test status
Simulation time 2002376039 ps
CPU time 10.35 seconds
Started Mar 21 01:30:05 PM PDT 24
Finished Mar 21 01:30:15 PM PDT 24
Peak memory 209260 kb
Host smart-5055ec51-0ec3-45e7-b06e-b3c03d83367b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546187186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2546187186
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1312786609
Short name T206
Test name
Test status
Simulation time 359824336 ps
CPU time 2.09 seconds
Started Mar 21 01:30:06 PM PDT 24
Finished Mar 21 01:30:08 PM PDT 24
Peak memory 209120 kb
Host smart-ebe0a82d-28cb-42ff-be5e-53c4d1f5d6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312786609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1312786609
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2150383053
Short name T138
Test name
Test status
Simulation time 182078302 ps
CPU time 1.21 seconds
Started Mar 21 01:30:05 PM PDT 24
Finished Mar 21 01:30:06 PM PDT 24
Peak memory 200780 kb
Host smart-942b5f2c-243a-4fbd-aa12-b5194c13b1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150383053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2150383053
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2452348321
Short name T292
Test name
Test status
Simulation time 88990192 ps
CPU time 0.94 seconds
Started Mar 21 01:30:03 PM PDT 24
Finished Mar 21 01:30:04 PM PDT 24
Peak memory 200672 kb
Host smart-4f39e65a-2e28-4bdf-a3a3-9c44e384fd84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452348321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2452348321
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3855891754
Short name T345
Test name
Test status
Simulation time 244583866 ps
CPU time 1.06 seconds
Started Mar 21 01:30:04 PM PDT 24
Finished Mar 21 01:30:05 PM PDT 24
Peak memory 218156 kb
Host smart-ca6b2c3b-cbd3-4315-8a95-99d4a93e8d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855891754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3855891754
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2397768147
Short name T17
Test name
Test status
Simulation time 165899108 ps
CPU time 0.93 seconds
Started Mar 21 01:30:09 PM PDT 24
Finished Mar 21 01:30:10 PM PDT 24
Peak memory 200728 kb
Host smart-fa5c4d18-7ffb-4a4a-b99e-c375edc2a415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397768147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2397768147
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1866696193
Short name T76
Test name
Test status
Simulation time 1641799121 ps
CPU time 6.69 seconds
Started Mar 21 01:30:09 PM PDT 24
Finished Mar 21 01:30:15 PM PDT 24
Peak memory 201044 kb
Host smart-ddae044d-2e5a-44b9-882d-e19ea2b48d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866696193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1866696193
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.4192000519
Short name T134
Test name
Test status
Simulation time 143832965 ps
CPU time 1.17 seconds
Started Mar 21 01:30:09 PM PDT 24
Finished Mar 21 01:30:10 PM PDT 24
Peak memory 200856 kb
Host smart-c596d75e-0bfb-4a49-92a8-4f33b56e22c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192000519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.4192000519
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2708714229
Short name T469
Test name
Test status
Simulation time 192450017 ps
CPU time 1.49 seconds
Started Mar 21 01:30:07 PM PDT 24
Finished Mar 21 01:30:08 PM PDT 24
Peak memory 201016 kb
Host smart-2d6249df-2399-41c7-8dbd-7537a1bf1c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708714229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2708714229
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1218366138
Short name T463
Test name
Test status
Simulation time 19213270701 ps
CPU time 64.76 seconds
Started Mar 21 01:30:06 PM PDT 24
Finished Mar 21 01:31:11 PM PDT 24
Peak memory 209328 kb
Host smart-8a34c217-9b5f-4fbe-9a6d-41a4445a1395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218366138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1218366138
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3359448376
Short name T315
Test name
Test status
Simulation time 121201948 ps
CPU time 1.45 seconds
Started Mar 21 01:30:09 PM PDT 24
Finished Mar 21 01:30:11 PM PDT 24
Peak memory 200944 kb
Host smart-d5f1de99-8f5c-4d84-83bf-dd9de7125222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359448376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3359448376
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3063382393
Short name T444
Test name
Test status
Simulation time 89113956 ps
CPU time 0.92 seconds
Started Mar 21 01:30:02 PM PDT 24
Finished Mar 21 01:30:03 PM PDT 24
Peak memory 200756 kb
Host smart-b957bfde-e78e-474c-8089-51572337f260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063382393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3063382393
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3482586129
Short name T341
Test name
Test status
Simulation time 63526529 ps
CPU time 0.79 seconds
Started Mar 21 01:30:11 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 200740 kb
Host smart-e6448cd8-31d0-48e5-bddb-a7e7187080ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482586129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3482586129
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.573433128
Short name T314
Test name
Test status
Simulation time 1219364272 ps
CPU time 6.14 seconds
Started Mar 21 01:30:03 PM PDT 24
Finished Mar 21 01:30:09 PM PDT 24
Peak memory 218548 kb
Host smart-0fc17bb6-b258-4b73-8390-e5bc8d8db1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573433128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.573433128
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2835479614
Short name T279
Test name
Test status
Simulation time 244275121 ps
CPU time 1.08 seconds
Started Mar 21 01:30:04 PM PDT 24
Finished Mar 21 01:30:05 PM PDT 24
Peak memory 218012 kb
Host smart-8008095b-a824-424f-85ab-509c9c633568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835479614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2835479614
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3565880586
Short name T249
Test name
Test status
Simulation time 101448646 ps
CPU time 0.81 seconds
Started Mar 21 01:30:02 PM PDT 24
Finished Mar 21 01:30:03 PM PDT 24
Peak memory 200604 kb
Host smart-d1215e68-947d-4cbc-a7b9-df3975a85140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565880586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3565880586
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.598230497
Short name T357
Test name
Test status
Simulation time 852707618 ps
CPU time 4.39 seconds
Started Mar 21 01:30:03 PM PDT 24
Finished Mar 21 01:30:08 PM PDT 24
Peak memory 201084 kb
Host smart-48ddaadc-6924-40ff-b4f9-466eca4fc20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598230497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.598230497
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2760775809
Short name T346
Test name
Test status
Simulation time 104830547 ps
CPU time 1.06 seconds
Started Mar 21 01:30:02 PM PDT 24
Finished Mar 21 01:30:03 PM PDT 24
Peak memory 200856 kb
Host smart-192a2ac1-9085-4f7a-bb55-2683cde6b493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760775809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2760775809
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2775200147
Short name T135
Test name
Test status
Simulation time 12346790872 ps
CPU time 46.24 seconds
Started Mar 21 01:30:05 PM PDT 24
Finished Mar 21 01:30:51 PM PDT 24
Peak memory 201180 kb
Host smart-5311e9eb-5c49-4665-8de9-b26c22f7d98d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775200147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2775200147
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1525260410
Short name T200
Test name
Test status
Simulation time 124618081 ps
CPU time 1.53 seconds
Started Mar 21 01:30:06 PM PDT 24
Finished Mar 21 01:30:08 PM PDT 24
Peak memory 200904 kb
Host smart-d8fcfb8d-733e-482e-b2cd-e213e43082a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525260410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1525260410
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3877457807
Short name T246
Test name
Test status
Simulation time 88957140 ps
CPU time 0.92 seconds
Started Mar 21 01:30:01 PM PDT 24
Finished Mar 21 01:30:02 PM PDT 24
Peak memory 200760 kb
Host smart-56745ebd-06bf-4e90-8c40-1ab03d4b9766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877457807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3877457807
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2257427309
Short name T46
Test name
Test status
Simulation time 81650827 ps
CPU time 0.83 seconds
Started Mar 21 01:30:10 PM PDT 24
Finished Mar 21 01:30:11 PM PDT 24
Peak memory 200740 kb
Host smart-ec9f6fc1-ec7b-4ce4-9293-72d9304130f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257427309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2257427309
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1646261323
Short name T372
Test name
Test status
Simulation time 1223798935 ps
CPU time 5.92 seconds
Started Mar 21 01:30:11 PM PDT 24
Finished Mar 21 01:30:17 PM PDT 24
Peak memory 218568 kb
Host smart-01854286-7635-440f-b014-19273a94c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646261323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1646261323
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.74686549
Short name T15
Test name
Test status
Simulation time 243908029 ps
CPU time 1.06 seconds
Started Mar 21 01:30:13 PM PDT 24
Finished Mar 21 01:30:14 PM PDT 24
Peak memory 218156 kb
Host smart-f755b0ad-6051-4317-9d88-af53960650c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74686549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.74686549
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2740421920
Short name T412
Test name
Test status
Simulation time 192068299 ps
CPU time 0.87 seconds
Started Mar 21 01:30:10 PM PDT 24
Finished Mar 21 01:30:11 PM PDT 24
Peak memory 200736 kb
Host smart-2c182baa-8656-4175-9a3d-af65a529a58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740421920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2740421920
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1802530832
Short name T398
Test name
Test status
Simulation time 1069500203 ps
CPU time 6.03 seconds
Started Mar 21 01:30:11 PM PDT 24
Finished Mar 21 01:30:17 PM PDT 24
Peak memory 200952 kb
Host smart-68ef3883-6305-42db-bece-9f44034515a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802530832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1802530832
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3284182458
Short name T456
Test name
Test status
Simulation time 157324171 ps
CPU time 1.13 seconds
Started Mar 21 01:30:10 PM PDT 24
Finished Mar 21 01:30:11 PM PDT 24
Peak memory 200860 kb
Host smart-323bed57-2f17-4c00-a9e1-505722622507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284182458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3284182458
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.55632950
Short name T225
Test name
Test status
Simulation time 3098470943 ps
CPU time 13.41 seconds
Started Mar 21 01:30:13 PM PDT 24
Finished Mar 21 01:30:26 PM PDT 24
Peak memory 209364 kb
Host smart-afa97c23-1a2b-4dff-b528-efb7f48bf598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55632950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.55632950
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1012224925
Short name T234
Test name
Test status
Simulation time 133905121 ps
CPU time 1.82 seconds
Started Mar 21 01:30:12 PM PDT 24
Finished Mar 21 01:30:14 PM PDT 24
Peak memory 209148 kb
Host smart-25408073-82d6-481e-a541-21d25c99c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012224925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1012224925
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3845535257
Short name T356
Test name
Test status
Simulation time 78070227 ps
CPU time 0.79 seconds
Started Mar 21 01:30:11 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 200756 kb
Host smart-2f7e7f7f-3ab5-432a-81c6-0db3a52cb322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845535257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3845535257
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2555547378
Short name T39
Test name
Test status
Simulation time 1882038529 ps
CPU time 7.06 seconds
Started Mar 21 01:30:12 PM PDT 24
Finished Mar 21 01:30:19 PM PDT 24
Peak memory 222496 kb
Host smart-73eac11c-5fbf-471e-86d2-dec0a631bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555547378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2555547378
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3905717387
Short name T408
Test name
Test status
Simulation time 244584313 ps
CPU time 1.09 seconds
Started Mar 21 01:30:10 PM PDT 24
Finished Mar 21 01:30:11 PM PDT 24
Peak memory 218060 kb
Host smart-9094edeb-02eb-486e-95b0-5ea867d15f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905717387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3905717387
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.4252292677
Short name T209
Test name
Test status
Simulation time 204484873 ps
CPU time 0.86 seconds
Started Mar 21 01:30:10 PM PDT 24
Finished Mar 21 01:30:11 PM PDT 24
Peak memory 200672 kb
Host smart-b7aef519-2858-4faa-a396-ce4c0c76cc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252292677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.4252292677
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.34942035
Short name T149
Test name
Test status
Simulation time 1567961772 ps
CPU time 6.35 seconds
Started Mar 21 01:30:11 PM PDT 24
Finished Mar 21 01:30:18 PM PDT 24
Peak memory 200936 kb
Host smart-41189250-979c-44ba-8d3a-8848a979dcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34942035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.34942035
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2468635911
Short name T437
Test name
Test status
Simulation time 113231518 ps
CPU time 1.02 seconds
Started Mar 21 01:30:12 PM PDT 24
Finished Mar 21 01:30:13 PM PDT 24
Peak memory 200780 kb
Host smart-a316a5c2-b0c7-4ed0-bc2e-b4d6a0a9456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468635911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2468635911
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3637039938
Short name T300
Test name
Test status
Simulation time 199696594 ps
CPU time 1.46 seconds
Started Mar 21 01:30:11 PM PDT 24
Finished Mar 21 01:30:13 PM PDT 24
Peak memory 201052 kb
Host smart-30271202-88ed-4ad2-bde7-8f7c1b301591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637039938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3637039938
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1796928333
Short name T81
Test name
Test status
Simulation time 150865233 ps
CPU time 1.81 seconds
Started Mar 21 01:30:10 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 200944 kb
Host smart-5ace8636-e95b-4318-909d-9b060b019573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796928333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1796928333
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2358973511
Short name T364
Test name
Test status
Simulation time 127705985 ps
CPU time 1.14 seconds
Started Mar 21 01:30:11 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 200780 kb
Host smart-88d79176-6944-4317-90b3-10a77ceede7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358973511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2358973511
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3794951600
Short name T204
Test name
Test status
Simulation time 67825868 ps
CPU time 0.83 seconds
Started Mar 21 01:30:22 PM PDT 24
Finished Mar 21 01:30:24 PM PDT 24
Peak memory 200664 kb
Host smart-c600ec29-00bf-4b6e-867c-3a6bedb99037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794951600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3794951600
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2024366503
Short name T529
Test name
Test status
Simulation time 1225618966 ps
CPU time 6.16 seconds
Started Mar 21 01:30:12 PM PDT 24
Finished Mar 21 01:30:18 PM PDT 24
Peak memory 218556 kb
Host smart-c5e8bb2a-4b5a-46d9-84ac-d04ab583a465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024366503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2024366503
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2252511999
Short name T295
Test name
Test status
Simulation time 244783383 ps
CPU time 1.16 seconds
Started Mar 21 01:30:11 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 218316 kb
Host smart-8b8a6ab3-cf7f-4f43-b491-870cb8affec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252511999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2252511999
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2227130394
Short name T74
Test name
Test status
Simulation time 196609090 ps
CPU time 0.92 seconds
Started Mar 21 01:30:10 PM PDT 24
Finished Mar 21 01:30:11 PM PDT 24
Peak memory 200648 kb
Host smart-4e03fd4d-fed7-45c9-9501-a2dd5740c99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227130394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2227130394
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2931133751
Short name T93
Test name
Test status
Simulation time 813120256 ps
CPU time 4.2 seconds
Started Mar 21 01:30:12 PM PDT 24
Finished Mar 21 01:30:16 PM PDT 24
Peak memory 201028 kb
Host smart-66435071-b3f1-4fc7-a8bf-8b668aa9237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931133751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2931133751
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2791111391
Short name T144
Test name
Test status
Simulation time 110822617 ps
CPU time 1.03 seconds
Started Mar 21 01:30:12 PM PDT 24
Finished Mar 21 01:30:13 PM PDT 24
Peak memory 200868 kb
Host smart-4a6e2955-45a3-4cf2-95ab-bca933ed911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791111391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2791111391
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3307515052
Short name T516
Test name
Test status
Simulation time 242238857 ps
CPU time 1.5 seconds
Started Mar 21 01:30:10 PM PDT 24
Finished Mar 21 01:30:12 PM PDT 24
Peak memory 201032 kb
Host smart-3e1bac09-736c-4506-9276-57e0aae0846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307515052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3307515052
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3853456269
Short name T75
Test name
Test status
Simulation time 198119236 ps
CPU time 1.26 seconds
Started Mar 21 01:30:23 PM PDT 24
Finished Mar 21 01:30:25 PM PDT 24
Peak memory 200844 kb
Host smart-5456b76b-23be-441a-a8b6-a6934d75f414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853456269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3853456269
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2857594511
Short name T217
Test name
Test status
Simulation time 370027047 ps
CPU time 2.46 seconds
Started Mar 21 01:30:09 PM PDT 24
Finished Mar 21 01:30:11 PM PDT 24
Peak memory 200896 kb
Host smart-8e8c02ab-5bef-462e-b355-fc1c7b15e6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857594511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2857594511
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1883995123
Short name T150
Test name
Test status
Simulation time 212823566 ps
CPU time 1.38 seconds
Started Mar 21 01:30:12 PM PDT 24
Finished Mar 21 01:30:13 PM PDT 24
Peak memory 200932 kb
Host smart-fde46150-1cf0-4826-94ea-5b3ad22f7d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883995123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1883995123
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.690328213
Short name T514
Test name
Test status
Simulation time 66356510 ps
CPU time 0.77 seconds
Started Mar 21 01:30:19 PM PDT 24
Finished Mar 21 01:30:21 PM PDT 24
Peak memory 200636 kb
Host smart-15a64ff7-17e5-46bc-a8ec-8d7ef26fd07d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690328213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.690328213
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.554512632
Short name T534
Test name
Test status
Simulation time 2188346664 ps
CPU time 9 seconds
Started Mar 21 01:30:21 PM PDT 24
Finished Mar 21 01:30:30 PM PDT 24
Peak memory 222680 kb
Host smart-98ef7b38-3343-4eb8-9c17-e7bd4ca3a4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554512632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.554512632
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.845582126
Short name T465
Test name
Test status
Simulation time 246821798 ps
CPU time 1.07 seconds
Started Mar 21 01:30:19 PM PDT 24
Finished Mar 21 01:30:21 PM PDT 24
Peak memory 218140 kb
Host smart-52902d1d-1fc9-433a-b299-8b67f6523fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845582126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.845582126
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1224911215
Short name T354
Test name
Test status
Simulation time 176238357 ps
CPU time 0.88 seconds
Started Mar 21 01:30:26 PM PDT 24
Finished Mar 21 01:30:27 PM PDT 24
Peak memory 200636 kb
Host smart-f38ab391-f1e5-419f-9efe-8f47fb483043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224911215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1224911215
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3688408822
Short name T6
Test name
Test status
Simulation time 1470038115 ps
CPU time 5.65 seconds
Started Mar 21 01:30:19 PM PDT 24
Finished Mar 21 01:30:26 PM PDT 24
Peak memory 200988 kb
Host smart-4081c5b2-3fb9-4f15-a409-d076c8e13717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688408822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3688408822
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1246975672
Short name T171
Test name
Test status
Simulation time 127658555 ps
CPU time 1.18 seconds
Started Mar 21 01:30:19 PM PDT 24
Finished Mar 21 01:30:20 PM PDT 24
Peak memory 201036 kb
Host smart-e8a0ab23-f71d-464e-ab9b-0a3db1072188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246975672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1246975672
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2523406200
Short name T537
Test name
Test status
Simulation time 4691068270 ps
CPU time 21.18 seconds
Started Mar 21 01:30:18 PM PDT 24
Finished Mar 21 01:30:40 PM PDT 24
Peak memory 201104 kb
Host smart-0ea0d57a-5f26-4fd3-80e5-59442f2f68e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523406200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2523406200
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3898849669
Short name T527
Test name
Test status
Simulation time 421276040 ps
CPU time 2.25 seconds
Started Mar 21 01:30:20 PM PDT 24
Finished Mar 21 01:30:22 PM PDT 24
Peak memory 209240 kb
Host smart-e4afaa64-9881-4b19-8a50-9e068330b10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898849669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3898849669
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2742539340
Short name T190
Test name
Test status
Simulation time 185406032 ps
CPU time 1.24 seconds
Started Mar 21 01:30:18 PM PDT 24
Finished Mar 21 01:30:20 PM PDT 24
Peak memory 200816 kb
Host smart-f2fe8c9d-87c6-4010-9f07-8fe5f69f51e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742539340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2742539340
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2539230435
Short name T187
Test name
Test status
Simulation time 68031087 ps
CPU time 0.73 seconds
Started Mar 21 01:30:19 PM PDT 24
Finished Mar 21 01:30:20 PM PDT 24
Peak memory 200672 kb
Host smart-ec60a676-ba03-4415-9913-709caa8adceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539230435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2539230435
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1184557370
Short name T27
Test name
Test status
Simulation time 2365386428 ps
CPU time 8.38 seconds
Started Mar 21 01:30:22 PM PDT 24
Finished Mar 21 01:30:31 PM PDT 24
Peak memory 218400 kb
Host smart-006ef2d3-24b6-41aa-9d70-7a0313315548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184557370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1184557370
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.694231082
Short name T498
Test name
Test status
Simulation time 243988664 ps
CPU time 1.16 seconds
Started Mar 21 01:30:20 PM PDT 24
Finished Mar 21 01:30:22 PM PDT 24
Peak memory 218272 kb
Host smart-aa4c1ad6-d7a4-40af-904c-fd752146cae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694231082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.694231082
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3155595392
Short name T304
Test name
Test status
Simulation time 196410677 ps
CPU time 0.91 seconds
Started Mar 21 01:30:20 PM PDT 24
Finished Mar 21 01:30:21 PM PDT 24
Peak memory 200748 kb
Host smart-9a9e71d6-aacb-476a-b73a-ab774f7babd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155595392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3155595392
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3985174787
Short name T383
Test name
Test status
Simulation time 1621632600 ps
CPU time 6.45 seconds
Started Mar 21 01:30:20 PM PDT 24
Finished Mar 21 01:30:26 PM PDT 24
Peak memory 201032 kb
Host smart-9dc1fbeb-c354-460d-89a2-2a9ce225608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985174787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3985174787
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.4193285415
Short name T338
Test name
Test status
Simulation time 181153944 ps
CPU time 1.16 seconds
Started Mar 21 01:30:22 PM PDT 24
Finished Mar 21 01:30:24 PM PDT 24
Peak memory 200856 kb
Host smart-22eb6365-7c7c-4861-aaa4-7e7b7b2f2f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193285415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.4193285415
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.4056025608
Short name T474
Test name
Test status
Simulation time 119246505 ps
CPU time 1.2 seconds
Started Mar 21 01:30:21 PM PDT 24
Finished Mar 21 01:30:23 PM PDT 24
Peak memory 201036 kb
Host smart-11379ef4-1615-4ece-b594-82c174f16f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056025608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.4056025608
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2257814732
Short name T261
Test name
Test status
Simulation time 14747779006 ps
CPU time 54.99 seconds
Started Mar 21 01:30:23 PM PDT 24
Finished Mar 21 01:31:18 PM PDT 24
Peak memory 201100 kb
Host smart-c31e1361-d891-411c-93a3-35a7108ac472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257814732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2257814732
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.387402393
Short name T509
Test name
Test status
Simulation time 126280441 ps
CPU time 1.73 seconds
Started Mar 21 01:30:21 PM PDT 24
Finished Mar 21 01:30:23 PM PDT 24
Peak memory 209152 kb
Host smart-d1db6fa2-df74-4df2-b2a5-7e20f79203b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387402393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.387402393
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2316985446
Short name T277
Test name
Test status
Simulation time 214371943 ps
CPU time 1.4 seconds
Started Mar 21 01:30:22 PM PDT 24
Finished Mar 21 01:30:24 PM PDT 24
Peak memory 200848 kb
Host smart-e6e69448-1d32-4598-9f1d-d0feb4121ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316985446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2316985446
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3223130884
Short name T494
Test name
Test status
Simulation time 67364193 ps
CPU time 0.78 seconds
Started Mar 21 01:30:29 PM PDT 24
Finished Mar 21 01:30:30 PM PDT 24
Peak memory 200724 kb
Host smart-3d3c7f09-4abf-4949-8160-523a2bd36ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223130884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3223130884
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2777015658
Short name T1
Test name
Test status
Simulation time 2346293605 ps
CPU time 8.48 seconds
Started Mar 21 01:30:30 PM PDT 24
Finished Mar 21 01:30:39 PM PDT 24
Peak memory 222736 kb
Host smart-7de22499-023d-429c-be3f-3e307763ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777015658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2777015658
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1475316922
Short name T369
Test name
Test status
Simulation time 244741918 ps
CPU time 1.15 seconds
Started Mar 21 01:30:30 PM PDT 24
Finished Mar 21 01:30:31 PM PDT 24
Peak memory 218052 kb
Host smart-af667dca-5c2d-4a88-ba81-7f05a3a1b7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475316922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1475316922
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3604094802
Short name T536
Test name
Test status
Simulation time 226489622 ps
CPU time 0.91 seconds
Started Mar 21 01:30:18 PM PDT 24
Finished Mar 21 01:30:19 PM PDT 24
Peak memory 200756 kb
Host smart-9268db14-0a93-47b8-af78-0ab9414e4bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604094802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3604094802
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3996530754
Short name T263
Test name
Test status
Simulation time 1460124753 ps
CPU time 5.44 seconds
Started Mar 21 01:30:23 PM PDT 24
Finished Mar 21 01:30:29 PM PDT 24
Peak memory 201032 kb
Host smart-33ddc208-1b82-4e69-99f8-15d26608284e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996530754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3996530754
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.4027181301
Short name T142
Test name
Test status
Simulation time 100908486 ps
CPU time 1.03 seconds
Started Mar 21 01:30:28 PM PDT 24
Finished Mar 21 01:30:29 PM PDT 24
Peak memory 200856 kb
Host smart-bfe98859-0211-4b3b-8ab3-95bad884746c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027181301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4027181301
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2268290840
Short name T384
Test name
Test status
Simulation time 116901595 ps
CPU time 1.21 seconds
Started Mar 21 01:30:20 PM PDT 24
Finished Mar 21 01:30:22 PM PDT 24
Peak memory 201064 kb
Host smart-757819f4-ce20-4f38-8262-6eba104c6a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268290840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2268290840
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3779254344
Short name T69
Test name
Test status
Simulation time 7209917761 ps
CPU time 28.27 seconds
Started Mar 21 01:30:30 PM PDT 24
Finished Mar 21 01:30:59 PM PDT 24
Peak memory 201044 kb
Host smart-e50e9155-bd78-40ee-8ce9-59e6db0f6752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779254344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3779254344
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1215653295
Short name T132
Test name
Test status
Simulation time 352400922 ps
CPU time 2.15 seconds
Started Mar 21 01:30:28 PM PDT 24
Finished Mar 21 01:30:30 PM PDT 24
Peak memory 200844 kb
Host smart-bf5541d4-67d9-451e-b31c-64dc554262dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215653295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1215653295
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.973760023
Short name T303
Test name
Test status
Simulation time 147992097 ps
CPU time 1.08 seconds
Started Mar 21 01:30:28 PM PDT 24
Finished Mar 21 01:30:30 PM PDT 24
Peak memory 200784 kb
Host smart-b56271f0-8d40-474e-b909-7b9197523bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973760023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.973760023
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.536129792
Short name T431
Test name
Test status
Simulation time 118827907 ps
CPU time 0.88 seconds
Started Mar 21 01:29:19 PM PDT 24
Finished Mar 21 01:29:21 PM PDT 24
Peak memory 200736 kb
Host smart-31ef988a-e57c-42f7-81f9-48675d751609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536129792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.536129792
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.493222837
Short name T377
Test name
Test status
Simulation time 1899999418 ps
CPU time 7.69 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:28 PM PDT 24
Peak memory 218444 kb
Host smart-1d93ffcd-99d4-4f7d-b293-a988a72cce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493222837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.493222837
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3916601607
Short name T168
Test name
Test status
Simulation time 244125431 ps
CPU time 1.12 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:21 PM PDT 24
Peak memory 218136 kb
Host smart-3c03fd7d-cb26-4260-b212-811be448d3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916601607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3916601607
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1326474627
Short name T312
Test name
Test status
Simulation time 111624616 ps
CPU time 0.83 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:21 PM PDT 24
Peak memory 200716 kb
Host smart-ffae54de-7071-41a3-9068-9a29d6241e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326474627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1326474627
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3845952776
Short name T387
Test name
Test status
Simulation time 840128053 ps
CPU time 4.57 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:25 PM PDT 24
Peak memory 200956 kb
Host smart-1aab90ce-4a34-49fa-a1be-4e888cc151d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845952776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3845952776
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2413086868
Short name T63
Test name
Test status
Simulation time 8274174815 ps
CPU time 16.01 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:36 PM PDT 24
Peak memory 217788 kb
Host smart-3472fe7c-d472-469b-8af6-8ed914c40676
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413086868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2413086868
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4191960704
Short name T486
Test name
Test status
Simulation time 104494767 ps
CPU time 0.96 seconds
Started Mar 21 01:29:21 PM PDT 24
Finished Mar 21 01:29:22 PM PDT 24
Peak memory 200736 kb
Host smart-6fba378e-e89d-4e70-83ef-cf4227a67e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191960704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4191960704
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.4183108104
Short name T524
Test name
Test status
Simulation time 120323398 ps
CPU time 1.17 seconds
Started Mar 21 01:29:19 PM PDT 24
Finished Mar 21 01:29:21 PM PDT 24
Peak memory 200940 kb
Host smart-16f44667-ca35-4eef-b67b-492b971f02d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183108104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.4183108104
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1097895322
Short name T101
Test name
Test status
Simulation time 5289778850 ps
CPU time 24.64 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:45 PM PDT 24
Peak memory 209260 kb
Host smart-e2f6cead-20cb-45d2-ac54-092ecc34a3b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097895322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1097895322
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1464936195
Short name T450
Test name
Test status
Simulation time 330209153 ps
CPU time 2.27 seconds
Started Mar 21 01:29:17 PM PDT 24
Finished Mar 21 01:29:19 PM PDT 24
Peak memory 209176 kb
Host smart-2cd064a1-ce00-4fc0-a4f5-6a0a57786b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464936195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1464936195
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3200044044
Short name T442
Test name
Test status
Simulation time 136165021 ps
CPU time 1.15 seconds
Started Mar 21 01:29:19 PM PDT 24
Finished Mar 21 01:29:20 PM PDT 24
Peak memory 200780 kb
Host smart-4a1fce66-5810-44ba-847e-15c4b29faff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200044044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3200044044
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3291456461
Short name T143
Test name
Test status
Simulation time 79948724 ps
CPU time 0.82 seconds
Started Mar 21 01:30:29 PM PDT 24
Finished Mar 21 01:30:30 PM PDT 24
Peak memory 200720 kb
Host smart-5eb44c8f-30df-4322-a44b-2a9b2f1ca89f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291456461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3291456461
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1633584468
Short name T32
Test name
Test status
Simulation time 1887328051 ps
CPU time 7.07 seconds
Started Mar 21 01:30:27 PM PDT 24
Finished Mar 21 01:30:34 PM PDT 24
Peak memory 217752 kb
Host smart-614bd34f-f1a9-49ec-b5a0-28494163058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633584468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1633584468
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.842020958
Short name T459
Test name
Test status
Simulation time 243834263 ps
CPU time 1.12 seconds
Started Mar 21 01:30:26 PM PDT 24
Finished Mar 21 01:30:28 PM PDT 24
Peak memory 218128 kb
Host smart-33611ade-b99d-4d0c-9544-f1dc362ec572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842020958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.842020958
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1267130673
Short name T330
Test name
Test status
Simulation time 117275906 ps
CPU time 0.78 seconds
Started Mar 21 01:30:28 PM PDT 24
Finished Mar 21 01:30:29 PM PDT 24
Peak memory 200744 kb
Host smart-ee9a7124-3659-4ef1-81f1-8fe16ddeae83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267130673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1267130673
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3505102911
Short name T525
Test name
Test status
Simulation time 825877622 ps
CPU time 4.21 seconds
Started Mar 21 01:30:28 PM PDT 24
Finished Mar 21 01:30:33 PM PDT 24
Peak memory 201072 kb
Host smart-bda53f3d-1151-446a-b488-3be3b08b4cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505102911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3505102911
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.831149806
Short name T141
Test name
Test status
Simulation time 167165386 ps
CPU time 1.15 seconds
Started Mar 21 01:30:27 PM PDT 24
Finished Mar 21 01:30:29 PM PDT 24
Peak memory 200780 kb
Host smart-45f3956a-bf3e-48b8-b98c-9130033063ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831149806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.831149806
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1677476225
Short name T127
Test name
Test status
Simulation time 263786909 ps
CPU time 1.49 seconds
Started Mar 21 01:30:26 PM PDT 24
Finished Mar 21 01:30:28 PM PDT 24
Peak memory 201060 kb
Host smart-ddded335-f583-4414-8de4-5397b92d13c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677476225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1677476225
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.653293246
Short name T240
Test name
Test status
Simulation time 4810894667 ps
CPU time 21.37 seconds
Started Mar 21 01:30:29 PM PDT 24
Finished Mar 21 01:30:50 PM PDT 24
Peak memory 201212 kb
Host smart-18e37935-41b8-419e-9336-b17af9cbe49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653293246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.653293246
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1157242272
Short name T385
Test name
Test status
Simulation time 130541327 ps
CPU time 1.58 seconds
Started Mar 21 01:30:27 PM PDT 24
Finished Mar 21 01:30:29 PM PDT 24
Peak memory 200844 kb
Host smart-4ffb482e-1fbd-44df-996c-2e8cd8545e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157242272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1157242272
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2769076893
Short name T128
Test name
Test status
Simulation time 208455665 ps
CPU time 1.26 seconds
Started Mar 21 01:30:29 PM PDT 24
Finished Mar 21 01:30:30 PM PDT 24
Peak memory 200864 kb
Host smart-be9938d2-92be-4dc1-8a6b-98fb181963ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769076893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2769076893
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3577640409
Short name T488
Test name
Test status
Simulation time 89077111 ps
CPU time 0.92 seconds
Started Mar 21 01:30:38 PM PDT 24
Finished Mar 21 01:30:39 PM PDT 24
Peak memory 200776 kb
Host smart-332f97e7-025e-4d2c-a1a1-7b1174757445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577640409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3577640409
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1877182760
Short name T9
Test name
Test status
Simulation time 2351716830 ps
CPU time 7.84 seconds
Started Mar 21 01:30:28 PM PDT 24
Finished Mar 21 01:30:36 PM PDT 24
Peak memory 221832 kb
Host smart-5901b7a3-f0ab-4ab3-90fe-93b654398d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877182760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1877182760
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3099246307
Short name T70
Test name
Test status
Simulation time 244457210 ps
CPU time 1.2 seconds
Started Mar 21 01:30:28 PM PDT 24
Finished Mar 21 01:30:29 PM PDT 24
Peak memory 218108 kb
Host smart-fba826f2-7945-453e-bcaa-65a75c01f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099246307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3099246307
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1149058671
Short name T400
Test name
Test status
Simulation time 137857127 ps
CPU time 0.82 seconds
Started Mar 21 01:30:29 PM PDT 24
Finished Mar 21 01:30:30 PM PDT 24
Peak memory 200632 kb
Host smart-2141a549-d469-4cab-9bbe-5a056d59aa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149058671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1149058671
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1226452423
Short name T125
Test name
Test status
Simulation time 2017750754 ps
CPU time 6.88 seconds
Started Mar 21 01:30:38 PM PDT 24
Finished Mar 21 01:30:46 PM PDT 24
Peak memory 200988 kb
Host smart-93d35b1b-d2c2-40b2-90da-813c2d69e68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226452423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1226452423
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3650151548
Short name T426
Test name
Test status
Simulation time 101279160 ps
CPU time 0.96 seconds
Started Mar 21 01:30:26 PM PDT 24
Finished Mar 21 01:30:27 PM PDT 24
Peak memory 200836 kb
Host smart-478568fa-75ab-47e7-a6d8-7f60f14ec8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650151548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3650151548
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2345717215
Short name T49
Test name
Test status
Simulation time 113990299 ps
CPU time 1.11 seconds
Started Mar 21 01:30:28 PM PDT 24
Finished Mar 21 01:30:29 PM PDT 24
Peak memory 200860 kb
Host smart-d83b3b54-1617-4483-b95d-9adba12bf14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345717215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2345717215
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1393952591
Short name T236
Test name
Test status
Simulation time 7059670024 ps
CPU time 27.53 seconds
Started Mar 21 01:30:36 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 209360 kb
Host smart-4ecb67ba-73ae-45a3-892e-5a22a4e9ec62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393952591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1393952591
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1165832243
Short name T223
Test name
Test status
Simulation time 146204312 ps
CPU time 1.74 seconds
Started Mar 21 01:30:28 PM PDT 24
Finished Mar 21 01:30:30 PM PDT 24
Peak memory 200956 kb
Host smart-e2bfe81a-e5ca-407b-9fa2-af8f0502b68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165832243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1165832243
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1721423001
Short name T158
Test name
Test status
Simulation time 243661102 ps
CPU time 1.42 seconds
Started Mar 21 01:30:27 PM PDT 24
Finished Mar 21 01:30:29 PM PDT 24
Peak memory 200844 kb
Host smart-e0ab3ba1-5772-4192-921d-f6bd3aabeda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721423001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1721423001
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.4228020557
Short name T52
Test name
Test status
Simulation time 68370076 ps
CPU time 0.77 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:38 PM PDT 24
Peak memory 200732 kb
Host smart-eaeb3bca-bdf5-420c-8263-5c29550b6c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228020557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.4228020557
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.613758944
Short name T227
Test name
Test status
Simulation time 245208905 ps
CPU time 1.04 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:38 PM PDT 24
Peak memory 218180 kb
Host smart-2a2593b4-77f1-43ae-919a-9cc6ee6cb167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613758944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.613758944
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3915710415
Short name T284
Test name
Test status
Simulation time 135364777 ps
CPU time 0.84 seconds
Started Mar 21 01:30:38 PM PDT 24
Finished Mar 21 01:30:40 PM PDT 24
Peak memory 200752 kb
Host smart-070881db-64da-4bfc-a3c6-bee51dcca723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915710415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3915710415
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3280448405
Short name T399
Test name
Test status
Simulation time 1645256406 ps
CPU time 7.25 seconds
Started Mar 21 01:30:35 PM PDT 24
Finished Mar 21 01:30:43 PM PDT 24
Peak memory 201000 kb
Host smart-836760b7-70e0-4fd3-bbd4-5eb0bb5fcf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280448405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3280448405
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.868728106
Short name T257
Test name
Test status
Simulation time 151742665 ps
CPU time 1.15 seconds
Started Mar 21 01:30:36 PM PDT 24
Finished Mar 21 01:30:38 PM PDT 24
Peak memory 200848 kb
Host smart-6f4a2211-6a9c-42b4-9ef7-88f0323f757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868728106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.868728106
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1806214270
Short name T242
Test name
Test status
Simulation time 200654729 ps
CPU time 1.42 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:39 PM PDT 24
Peak memory 201056 kb
Host smart-2e7474b9-9d3a-4be4-ba0a-fd0c2807a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806214270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1806214270
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.445429341
Short name T98
Test name
Test status
Simulation time 1344450145 ps
CPU time 6.46 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:44 PM PDT 24
Peak memory 200952 kb
Host smart-fb8e43f8-03b7-4bfd-a83d-8cf9e35688ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445429341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.445429341
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3352001511
Short name T476
Test name
Test status
Simulation time 137665389 ps
CPU time 1.8 seconds
Started Mar 21 01:30:38 PM PDT 24
Finished Mar 21 01:30:39 PM PDT 24
Peak memory 200828 kb
Host smart-b5384980-fe08-49d3-8973-b83b604b20be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352001511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3352001511
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3647997535
Short name T503
Test name
Test status
Simulation time 248361338 ps
CPU time 1.46 seconds
Started Mar 21 01:30:36 PM PDT 24
Finished Mar 21 01:30:37 PM PDT 24
Peak memory 200944 kb
Host smart-88cbb16b-98df-4883-bba9-1a9afc49819d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647997535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3647997535
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3768783011
Short name T402
Test name
Test status
Simulation time 69066591 ps
CPU time 0.79 seconds
Started Mar 21 01:30:35 PM PDT 24
Finished Mar 21 01:30:36 PM PDT 24
Peak memory 200740 kb
Host smart-31c9aa34-9964-4238-9c7b-c1181cdb7555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768783011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3768783011
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3804897100
Short name T40
Test name
Test status
Simulation time 1880250381 ps
CPU time 7.99 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:45 PM PDT 24
Peak memory 222568 kb
Host smart-b7d2b64a-dca6-48a5-8fd7-f239a114e732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804897100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3804897100
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2031954074
Short name T358
Test name
Test status
Simulation time 246524599 ps
CPU time 1.05 seconds
Started Mar 21 01:30:36 PM PDT 24
Finished Mar 21 01:30:38 PM PDT 24
Peak memory 218108 kb
Host smart-7b4c8ae8-e4b4-49ef-aa0f-9950f1b4803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031954074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2031954074
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1682122664
Short name T428
Test name
Test status
Simulation time 195492488 ps
CPU time 0.92 seconds
Started Mar 21 01:30:39 PM PDT 24
Finished Mar 21 01:30:40 PM PDT 24
Peak memory 200684 kb
Host smart-b7f40e9b-47d0-4fa6-a65e-b85267d10070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682122664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1682122664
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.816613252
Short name T173
Test name
Test status
Simulation time 971286444 ps
CPU time 4.85 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:42 PM PDT 24
Peak memory 201052 kb
Host smart-2e1da981-89bb-4b4e-bd0a-54fe58292d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816613252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.816613252
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.555678503
Short name T351
Test name
Test status
Simulation time 105953766 ps
CPU time 1.07 seconds
Started Mar 21 01:30:36 PM PDT 24
Finished Mar 21 01:30:38 PM PDT 24
Peak memory 200780 kb
Host smart-74871e9d-ce6f-4fe6-93cc-06ae69b6dda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555678503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.555678503
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.424559097
Short name T342
Test name
Test status
Simulation time 121153308 ps
CPU time 1.25 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:38 PM PDT 24
Peak memory 201016 kb
Host smart-61a44bcc-6d6c-48e4-9f64-a36b881bfa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424559097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.424559097
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.483301131
Short name T288
Test name
Test status
Simulation time 4821869443 ps
CPU time 23.47 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:31:01 PM PDT 24
Peak memory 201180 kb
Host smart-7da9f015-3548-4fcb-b645-87f6fef00741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483301131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.483301131
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1885287971
Short name T401
Test name
Test status
Simulation time 281499909 ps
CPU time 1.98 seconds
Started Mar 21 01:30:40 PM PDT 24
Finished Mar 21 01:30:42 PM PDT 24
Peak memory 200928 kb
Host smart-a3bc3de9-8acf-45ba-b5b4-2ea499a4656c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885287971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1885287971
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3463666273
Short name T517
Test name
Test status
Simulation time 112775730 ps
CPU time 1.04 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:38 PM PDT 24
Peak memory 200876 kb
Host smart-7ac38218-0844-4dc7-a417-c17e18ac9024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463666273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3463666273
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3268404120
Short name T382
Test name
Test status
Simulation time 71075197 ps
CPU time 0.79 seconds
Started Mar 21 01:30:44 PM PDT 24
Finished Mar 21 01:30:45 PM PDT 24
Peak memory 200672 kb
Host smart-562081ed-3d9c-4fc5-9e87-eb0df3cfc85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268404120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3268404120
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2374517825
Short name T386
Test name
Test status
Simulation time 1212591533 ps
CPU time 5.67 seconds
Started Mar 21 01:30:46 PM PDT 24
Finished Mar 21 01:30:52 PM PDT 24
Peak memory 222560 kb
Host smart-ae7384c9-9d5d-4c75-85a0-3661bde655fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374517825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2374517825
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3004757288
Short name T439
Test name
Test status
Simulation time 244077811 ps
CPU time 1.07 seconds
Started Mar 21 01:30:43 PM PDT 24
Finished Mar 21 01:30:45 PM PDT 24
Peak memory 218060 kb
Host smart-8ce30efb-e3f6-4cc6-95c9-661c1a885905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004757288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3004757288
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3269823559
Short name T212
Test name
Test status
Simulation time 127064338 ps
CPU time 0.81 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:38 PM PDT 24
Peak memory 200648 kb
Host smart-2a81f1c5-81d4-49d1-9586-ee4e5e6a8871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269823559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3269823559
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3721299983
Short name T373
Test name
Test status
Simulation time 984913188 ps
CPU time 4.76 seconds
Started Mar 21 01:30:36 PM PDT 24
Finished Mar 21 01:30:41 PM PDT 24
Peak memory 201044 kb
Host smart-130704a3-d282-4fd6-92e7-68d3d44e4fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721299983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3721299983
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3003074759
Short name T297
Test name
Test status
Simulation time 108733076 ps
CPU time 1.03 seconds
Started Mar 21 01:30:43 PM PDT 24
Finished Mar 21 01:30:44 PM PDT 24
Peak memory 200776 kb
Host smart-966f92d7-0acc-438b-be0e-fdf7179dbc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003074759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3003074759
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2274609677
Short name T521
Test name
Test status
Simulation time 203859087 ps
CPU time 1.33 seconds
Started Mar 21 01:30:37 PM PDT 24
Finished Mar 21 01:30:38 PM PDT 24
Peak memory 201036 kb
Host smart-8c43c8ff-55f8-4167-91b2-22fb39dc6894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274609677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2274609677
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1663789637
Short name T305
Test name
Test status
Simulation time 4857776094 ps
CPU time 22.87 seconds
Started Mar 21 01:30:48 PM PDT 24
Finished Mar 21 01:31:11 PM PDT 24
Peak memory 201172 kb
Host smart-6c5004d4-fe42-4f79-ad09-a267bbaf0249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663789637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1663789637
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2855032233
Short name T79
Test name
Test status
Simulation time 329364401 ps
CPU time 2.29 seconds
Started Mar 21 01:30:43 PM PDT 24
Finished Mar 21 01:30:45 PM PDT 24
Peak memory 209108 kb
Host smart-1e81a7da-7b44-421d-a719-a57b084576bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855032233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2855032233
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3321756159
Short name T466
Test name
Test status
Simulation time 87026201 ps
CPU time 0.87 seconds
Started Mar 21 01:30:39 PM PDT 24
Finished Mar 21 01:30:40 PM PDT 24
Peak memory 200864 kb
Host smart-381c0364-e800-47b7-bbef-fea169c2226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321756159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3321756159
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.405633334
Short name T337
Test name
Test status
Simulation time 68990244 ps
CPU time 0.75 seconds
Started Mar 21 01:30:45 PM PDT 24
Finished Mar 21 01:30:46 PM PDT 24
Peak memory 200652 kb
Host smart-8208b8be-248e-4749-b0ce-94e9876a06e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405633334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.405633334
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3728908728
Short name T30
Test name
Test status
Simulation time 2367844754 ps
CPU time 9.01 seconds
Started Mar 21 01:30:45 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 218144 kb
Host smart-484ce198-f891-49f1-ba67-9f4024b5d89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728908728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3728908728
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1207168064
Short name T153
Test name
Test status
Simulation time 244821225 ps
CPU time 1.11 seconds
Started Mar 21 01:30:46 PM PDT 24
Finished Mar 21 01:30:47 PM PDT 24
Peak memory 218132 kb
Host smart-669360b2-f45b-48b1-b8fd-b2b3f916256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207168064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1207168064
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.230683993
Short name T460
Test name
Test status
Simulation time 180023137 ps
CPU time 0.85 seconds
Started Mar 21 01:30:44 PM PDT 24
Finished Mar 21 01:30:45 PM PDT 24
Peak memory 200736 kb
Host smart-dd562925-cb88-4f40-b2c2-ba60dae87cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230683993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.230683993
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3920742949
Short name T231
Test name
Test status
Simulation time 877861323 ps
CPU time 4.44 seconds
Started Mar 21 01:30:42 PM PDT 24
Finished Mar 21 01:30:47 PM PDT 24
Peak memory 201040 kb
Host smart-d7c66d46-8ca2-46e4-8f6f-d53a4842f3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920742949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3920742949
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2000624403
Short name T487
Test name
Test status
Simulation time 115358453 ps
CPU time 1.04 seconds
Started Mar 21 01:30:46 PM PDT 24
Finished Mar 21 01:30:47 PM PDT 24
Peak memory 200880 kb
Host smart-73327d07-0f7c-48b3-8a1f-5026151064b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000624403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2000624403
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.624310094
Short name T453
Test name
Test status
Simulation time 111539163 ps
CPU time 1.18 seconds
Started Mar 21 01:30:43 PM PDT 24
Finished Mar 21 01:30:44 PM PDT 24
Peak memory 201032 kb
Host smart-3ac95071-5491-461b-a9df-d21c047cff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624310094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.624310094
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1122717890
Short name T378
Test name
Test status
Simulation time 10286284047 ps
CPU time 34.09 seconds
Started Mar 21 01:30:43 PM PDT 24
Finished Mar 21 01:31:17 PM PDT 24
Peak memory 201160 kb
Host smart-d2b542f4-37b4-47ff-9abe-f80b6c1896a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122717890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1122717890
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2273769518
Short name T162
Test name
Test status
Simulation time 148817426 ps
CPU time 1.85 seconds
Started Mar 21 01:30:44 PM PDT 24
Finished Mar 21 01:30:46 PM PDT 24
Peak memory 200940 kb
Host smart-2115909e-0d9b-493e-994a-641c5b6d6105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273769518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2273769518
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2458890842
Short name T405
Test name
Test status
Simulation time 73856714 ps
CPU time 0.82 seconds
Started Mar 21 01:30:45 PM PDT 24
Finished Mar 21 01:30:46 PM PDT 24
Peak memory 200808 kb
Host smart-c362b0b1-d4a5-443b-b06d-cdf1b5b3c739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458890842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2458890842
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.777659003
Short name T433
Test name
Test status
Simulation time 73279587 ps
CPU time 0.8 seconds
Started Mar 21 01:30:43 PM PDT 24
Finished Mar 21 01:30:44 PM PDT 24
Peak memory 200720 kb
Host smart-9419937a-44d0-49d4-a0d6-a79dac7776a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777659003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.777659003
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3237044249
Short name T262
Test name
Test status
Simulation time 1906137120 ps
CPU time 7.04 seconds
Started Mar 21 01:30:45 PM PDT 24
Finished Mar 21 01:30:52 PM PDT 24
Peak memory 217440 kb
Host smart-b721fe30-91d7-4d9d-b927-0d329b29224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237044249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3237044249
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1745418335
Short name T174
Test name
Test status
Simulation time 244784792 ps
CPU time 1.1 seconds
Started Mar 21 01:30:42 PM PDT 24
Finished Mar 21 01:30:43 PM PDT 24
Peak memory 218192 kb
Host smart-fe53bc3f-ea42-4a3e-a329-6417e8b1961e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745418335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1745418335
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1464003050
Short name T13
Test name
Test status
Simulation time 165939949 ps
CPU time 0.86 seconds
Started Mar 21 01:30:52 PM PDT 24
Finished Mar 21 01:30:53 PM PDT 24
Peak memory 200736 kb
Host smart-0568e40c-73d3-4972-8dae-a1f007277c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464003050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1464003050
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3583047333
Short name T208
Test name
Test status
Simulation time 1661000397 ps
CPU time 6.51 seconds
Started Mar 21 01:30:47 PM PDT 24
Finished Mar 21 01:30:54 PM PDT 24
Peak memory 200912 kb
Host smart-d44f8c65-136f-4e3a-8a02-43754004a545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583047333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3583047333
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3267691183
Short name T291
Test name
Test status
Simulation time 109485347 ps
CPU time 1.05 seconds
Started Mar 21 01:30:47 PM PDT 24
Finished Mar 21 01:30:48 PM PDT 24
Peak memory 200864 kb
Host smart-24ab5319-b5df-42f4-bd89-3751421e7b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267691183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3267691183
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2622397968
Short name T296
Test name
Test status
Simulation time 245914277 ps
CPU time 1.45 seconds
Started Mar 21 01:30:43 PM PDT 24
Finished Mar 21 01:30:44 PM PDT 24
Peak memory 200956 kb
Host smart-b36ba418-7455-4031-9cae-d55103288a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622397968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2622397968
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2345986849
Short name T213
Test name
Test status
Simulation time 2548180829 ps
CPU time 9.71 seconds
Started Mar 21 01:30:42 PM PDT 24
Finished Mar 21 01:30:52 PM PDT 24
Peak memory 201136 kb
Host smart-fd4b31fa-c29a-44bb-80d3-7e950a29243a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345986849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2345986849
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.577714034
Short name T407
Test name
Test status
Simulation time 357117148 ps
CPU time 2.09 seconds
Started Mar 21 01:30:42 PM PDT 24
Finished Mar 21 01:30:44 PM PDT 24
Peak memory 200820 kb
Host smart-018c63a1-f115-432a-a3bd-2f0311a9a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577714034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.577714034
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.760625986
Short name T332
Test name
Test status
Simulation time 96688674 ps
CPU time 0.89 seconds
Started Mar 21 01:30:42 PM PDT 24
Finished Mar 21 01:30:43 PM PDT 24
Peak memory 200892 kb
Host smart-7e04d919-dff1-48ac-af46-17afebb7960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760625986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.760625986
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2160376686
Short name T535
Test name
Test status
Simulation time 79985151 ps
CPU time 0.85 seconds
Started Mar 21 01:30:45 PM PDT 24
Finished Mar 21 01:30:46 PM PDT 24
Peak memory 200716 kb
Host smart-aad8b3c3-fc86-4775-931a-14ea2e8afe2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160376686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2160376686
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3867204839
Short name T133
Test name
Test status
Simulation time 1884635852 ps
CPU time 6.97 seconds
Started Mar 21 01:30:48 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 218440 kb
Host smart-8686c23d-dd27-49d3-a339-58f058a7dcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867204839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3867204839
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1579404632
Short name T51
Test name
Test status
Simulation time 244204740 ps
CPU time 1.06 seconds
Started Mar 21 01:30:45 PM PDT 24
Finished Mar 21 01:30:47 PM PDT 24
Peak memory 217984 kb
Host smart-c657310c-ea8e-4ac3-8f76-92be287e3715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579404632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1579404632
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3830806895
Short name T194
Test name
Test status
Simulation time 142953166 ps
CPU time 0.85 seconds
Started Mar 21 01:30:45 PM PDT 24
Finished Mar 21 01:30:46 PM PDT 24
Peak memory 200724 kb
Host smart-cc624e89-d855-4ab7-94e4-b234d02314de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830806895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3830806895
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1333651833
Short name T267
Test name
Test status
Simulation time 884416281 ps
CPU time 4.17 seconds
Started Mar 21 01:30:46 PM PDT 24
Finished Mar 21 01:30:51 PM PDT 24
Peak memory 201008 kb
Host smart-021be527-6c57-4802-b526-48d42e0c366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333651833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1333651833
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.406283091
Short name T507
Test name
Test status
Simulation time 146235452 ps
CPU time 1.12 seconds
Started Mar 21 01:30:48 PM PDT 24
Finished Mar 21 01:30:49 PM PDT 24
Peak memory 200872 kb
Host smart-ba296f7e-dcf9-4c23-b1f3-425beb214570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406283091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.406283091
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1828061768
Short name T355
Test name
Test status
Simulation time 192995680 ps
CPU time 1.47 seconds
Started Mar 21 01:30:47 PM PDT 24
Finished Mar 21 01:30:48 PM PDT 24
Peak memory 201056 kb
Host smart-b70364cd-3572-4b67-b2d4-dc38a145a842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828061768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1828061768
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3506890721
Short name T359
Test name
Test status
Simulation time 4492860830 ps
CPU time 16.75 seconds
Started Mar 21 01:30:44 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 209384 kb
Host smart-0bf1eccb-ec6b-4201-ac0b-7ee4ad33efb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506890721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3506890721
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.4150631142
Short name T323
Test name
Test status
Simulation time 106199394 ps
CPU time 1.49 seconds
Started Mar 21 01:30:43 PM PDT 24
Finished Mar 21 01:30:45 PM PDT 24
Peak memory 200956 kb
Host smart-9ad32186-92c6-4136-b291-e8848cae4b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150631142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4150631142
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1499815461
Short name T186
Test name
Test status
Simulation time 136647828 ps
CPU time 1.2 seconds
Started Mar 21 01:30:45 PM PDT 24
Finished Mar 21 01:30:47 PM PDT 24
Peak memory 200932 kb
Host smart-9052454f-b807-4bdd-a814-9cb534218e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499815461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1499815461
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3521431057
Short name T147
Test name
Test status
Simulation time 81244550 ps
CPU time 0.82 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 200720 kb
Host smart-eed37059-6776-4976-ac7d-d8354cc897ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521431057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3521431057
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2288468724
Short name T38
Test name
Test status
Simulation time 1218586711 ps
CPU time 5.65 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 222064 kb
Host smart-62a34148-5fac-4420-ab2e-de7919aacd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288468724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2288468724
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3109141824
Short name T478
Test name
Test status
Simulation time 243611935 ps
CPU time 1.17 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:54 PM PDT 24
Peak memory 218140 kb
Host smart-45b4c823-9a15-4b11-95bb-e6c3ab5cb10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109141824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3109141824
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2579878094
Short name T518
Test name
Test status
Simulation time 146999257 ps
CPU time 0.83 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:54 PM PDT 24
Peak memory 200732 kb
Host smart-0cd8870a-a666-4abc-9dca-8ac1a1bca9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579878094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2579878094
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1235233728
Short name T97
Test name
Test status
Simulation time 750253345 ps
CPU time 3.9 seconds
Started Mar 21 01:30:52 PM PDT 24
Finished Mar 21 01:30:57 PM PDT 24
Peak memory 201024 kb
Host smart-2f67281b-718b-41cf-93ee-0d72f83ce759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235233728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1235233728
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.528488261
Short name T443
Test name
Test status
Simulation time 182234168 ps
CPU time 1.22 seconds
Started Mar 21 01:30:52 PM PDT 24
Finished Mar 21 01:30:54 PM PDT 24
Peak memory 200780 kb
Host smart-c4ac6150-484a-497c-9b7e-5e685c812bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528488261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.528488261
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.4072584702
Short name T270
Test name
Test status
Simulation time 108915312 ps
CPU time 1.19 seconds
Started Mar 21 01:30:47 PM PDT 24
Finished Mar 21 01:30:49 PM PDT 24
Peak memory 200908 kb
Host smart-d96ca73e-bed9-42c2-8c6f-c217080304bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072584702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.4072584702
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1984770762
Short name T126
Test name
Test status
Simulation time 13646718006 ps
CPU time 47.88 seconds
Started Mar 21 01:30:52 PM PDT 24
Finished Mar 21 01:31:40 PM PDT 24
Peak memory 201116 kb
Host smart-247852b4-3656-4865-b14c-60a9c832c17d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984770762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1984770762
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3685218580
Short name T452
Test name
Test status
Simulation time 387459549 ps
CPU time 2.43 seconds
Started Mar 21 01:30:57 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 200896 kb
Host smart-cf00aea4-d05f-4480-83d9-46b789c479ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685218580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3685218580
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3863962546
Short name T182
Test name
Test status
Simulation time 101953740 ps
CPU time 0.99 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 200856 kb
Host smart-1f44d887-d4fe-4ff1-a3e6-c4ca284d34c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863962546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3863962546
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.721256375
Short name T350
Test name
Test status
Simulation time 68157806 ps
CPU time 0.79 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 200224 kb
Host smart-0f688e6e-752b-4eb1-8a74-144e5ae1cd4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721256375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.721256375
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3093982120
Short name T28
Test name
Test status
Simulation time 2170091783 ps
CPU time 7.59 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:31:02 PM PDT 24
Peak memory 218204 kb
Host smart-7477eea4-c7dd-408f-928f-045ba3b3fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093982120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3093982120
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3223391656
Short name T390
Test name
Test status
Simulation time 243606652 ps
CPU time 1.13 seconds
Started Mar 21 01:30:55 PM PDT 24
Finished Mar 21 01:30:57 PM PDT 24
Peak memory 218240 kb
Host smart-27c91e91-ab7b-4d15-852a-63c5c989c032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223391656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3223391656
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2107048292
Short name T278
Test name
Test status
Simulation time 152990957 ps
CPU time 0.88 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 200736 kb
Host smart-cbe244b4-6de5-42e6-a194-22fa12448623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107048292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2107048292
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3561877105
Short name T256
Test name
Test status
Simulation time 837032399 ps
CPU time 4.48 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:31:02 PM PDT 24
Peak memory 201068 kb
Host smart-c178de6c-79b3-4c9f-a0f7-c9d71d9e6390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561877105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3561877105
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2535110970
Short name T188
Test name
Test status
Simulation time 183740304 ps
CPU time 1.25 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:54 PM PDT 24
Peak memory 200888 kb
Host smart-db699509-d080-4180-a03b-29942c842deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535110970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2535110970
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.930096997
Short name T361
Test name
Test status
Simulation time 129535898 ps
CPU time 1.25 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 200616 kb
Host smart-524284ce-a151-4803-828c-6db0fdefa1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930096997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.930096997
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2997778661
Short name T121
Test name
Test status
Simulation time 3042718939 ps
CPU time 14 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:31:07 PM PDT 24
Peak memory 209352 kb
Host smart-1e258a70-9d96-4055-a62b-982615df172f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997778661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2997778661
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3602740035
Short name T272
Test name
Test status
Simulation time 115036449 ps
CPU time 1.58 seconds
Started Mar 21 01:30:55 PM PDT 24
Finished Mar 21 01:30:58 PM PDT 24
Peak memory 200964 kb
Host smart-e79512a7-1b4f-456c-b0a4-93431ac7d963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602740035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3602740035
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3950579638
Short name T299
Test name
Test status
Simulation time 126910861 ps
CPU time 1.04 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:57 PM PDT 24
Peak memory 200876 kb
Host smart-503968d2-c74f-45b5-bbd1-596731ee054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950579638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3950579638
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2739818628
Short name T414
Test name
Test status
Simulation time 87607351 ps
CPU time 0.85 seconds
Started Mar 21 01:29:28 PM PDT 24
Finished Mar 21 01:29:29 PM PDT 24
Peak memory 200740 kb
Host smart-47d99f40-d26d-474e-8290-df505f6520db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739818628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2739818628
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2405767637
Short name T152
Test name
Test status
Simulation time 245157287 ps
CPU time 1.08 seconds
Started Mar 21 01:29:21 PM PDT 24
Finished Mar 21 01:29:22 PM PDT 24
Peak memory 218112 kb
Host smart-b8f675ad-fc2a-4bcd-92fd-ddae1fea9dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405767637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2405767637
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3224005284
Short name T22
Test name
Test status
Simulation time 140647782 ps
CPU time 0.78 seconds
Started Mar 21 01:29:18 PM PDT 24
Finished Mar 21 01:29:20 PM PDT 24
Peak memory 200616 kb
Host smart-f6a3bc57-e4f1-4ba0-b9e6-773272642583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224005284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3224005284
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2223419987
Short name T394
Test name
Test status
Simulation time 1686635167 ps
CPU time 6.17 seconds
Started Mar 21 01:29:19 PM PDT 24
Finished Mar 21 01:29:25 PM PDT 24
Peak memory 201000 kb
Host smart-577d012c-52b3-418b-97f7-4753fa180594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223419987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2223419987
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.339501217
Short name T64
Test name
Test status
Simulation time 8378548126 ps
CPU time 13.16 seconds
Started Mar 21 01:29:28 PM PDT 24
Finished Mar 21 01:29:42 PM PDT 24
Peak memory 217684 kb
Host smart-bfcc909c-2f47-48e1-925d-77ae5619b701
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339501217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.339501217
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3001920534
Short name T538
Test name
Test status
Simulation time 178814975 ps
CPU time 1.25 seconds
Started Mar 21 01:29:21 PM PDT 24
Finished Mar 21 01:29:23 PM PDT 24
Peak memory 200840 kb
Host smart-512aa343-9002-4669-9fa1-2eb98e081136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001920534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3001920534
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2367355812
Short name T177
Test name
Test status
Simulation time 263865960 ps
CPU time 1.5 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:22 PM PDT 24
Peak memory 201084 kb
Host smart-475fcb17-b383-4945-850c-9c22d68ae588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367355812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2367355812
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2733177713
Short name T446
Test name
Test status
Simulation time 13777842599 ps
CPU time 46.57 seconds
Started Mar 21 01:29:21 PM PDT 24
Finished Mar 21 01:30:08 PM PDT 24
Peak memory 209352 kb
Host smart-39e932fd-7508-411c-8923-26c94e9d9fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733177713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2733177713
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3425501049
Short name T172
Test name
Test status
Simulation time 315238035 ps
CPU time 2.31 seconds
Started Mar 21 01:29:20 PM PDT 24
Finished Mar 21 01:29:23 PM PDT 24
Peak memory 200828 kb
Host smart-b34c8b51-e630-4d0a-bf82-bddf7ef19b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425501049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3425501049
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3990373294
Short name T290
Test name
Test status
Simulation time 150940151 ps
CPU time 1.12 seconds
Started Mar 21 01:29:19 PM PDT 24
Finished Mar 21 01:29:20 PM PDT 24
Peak memory 200772 kb
Host smart-8b4d16a6-44b2-45dd-b2a1-5e82f934da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990373294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3990373294
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3641476541
Short name T335
Test name
Test status
Simulation time 80449784 ps
CPU time 0.8 seconds
Started Mar 21 01:30:59 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 200708 kb
Host smart-cc87f957-8886-4df0-ad6a-f6930ac05fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641476541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3641476541
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1191781060
Short name T31
Test name
Test status
Simulation time 1217082355 ps
CPU time 5.7 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:59 PM PDT 24
Peak memory 222500 kb
Host smart-ee8ebd8d-ffc7-4b41-aa8e-268c42d514db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191781060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1191781060
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.677952073
Short name T175
Test name
Test status
Simulation time 247866466 ps
CPU time 1.12 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:57 PM PDT 24
Peak memory 218192 kb
Host smart-5b294e23-4f92-4a16-82ad-97b7b51c3de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677952073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.677952073
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.118763499
Short name T427
Test name
Test status
Simulation time 86897673 ps
CPU time 0.83 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:56 PM PDT 24
Peak memory 200736 kb
Host smart-2ea0ad01-6b75-4c8f-b838-564c07598fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118763499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.118763499
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3596077523
Short name T499
Test name
Test status
Simulation time 1700837471 ps
CPU time 6.57 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:31:01 PM PDT 24
Peak memory 201032 kb
Host smart-b97495b7-ad4a-4606-ba1e-9c09b1415efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596077523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3596077523
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2428873182
Short name T25
Test name
Test status
Simulation time 166440144 ps
CPU time 1.2 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:30:58 PM PDT 24
Peak memory 200788 kb
Host smart-f1291005-28fc-49f2-931a-775520e975bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428873182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2428873182
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.574813496
Short name T60
Test name
Test status
Simulation time 123666504 ps
CPU time 1.25 seconds
Started Mar 21 01:30:52 PM PDT 24
Finished Mar 21 01:30:54 PM PDT 24
Peak memory 201032 kb
Host smart-25bf0445-0fb1-445f-ba4a-d33a6d444c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574813496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.574813496
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2472105465
Short name T376
Test name
Test status
Simulation time 12956548124 ps
CPU time 52.47 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:31:46 PM PDT 24
Peak memory 209392 kb
Host smart-2eb235e0-7f2a-4d84-bfb1-d97e0217c68a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472105465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2472105465
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.889246286
Short name T403
Test name
Test status
Simulation time 136790578 ps
CPU time 1.76 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 209020 kb
Host smart-5a9c7d8d-3ddd-4724-a897-59cdcdcb90f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889246286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.889246286
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.301378742
Short name T237
Test name
Test status
Simulation time 131987948 ps
CPU time 1.17 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:57 PM PDT 24
Peak memory 200892 kb
Host smart-d26da312-f834-4c03-9cfa-bd68fdd4cd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301378742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.301378742
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.659012866
Short name T157
Test name
Test status
Simulation time 65571215 ps
CPU time 0.78 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:30:58 PM PDT 24
Peak memory 200636 kb
Host smart-987ebd20-ec4a-4652-8c23-666617f2c3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659012866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.659012866
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3597769347
Short name T505
Test name
Test status
Simulation time 1234004779 ps
CPU time 5.67 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:31:03 PM PDT 24
Peak memory 222540 kb
Host smart-c7aab1f8-f921-4837-9f09-51d654b925a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597769347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3597769347
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.226355946
Short name T519
Test name
Test status
Simulation time 246455261 ps
CPU time 1.06 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:30:58 PM PDT 24
Peak memory 218156 kb
Host smart-fd0db5fc-2efc-4d82-ac16-26913dc77d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226355946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.226355946
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.4012360789
Short name T309
Test name
Test status
Simulation time 75745893 ps
CPU time 0.75 seconds
Started Mar 21 01:30:55 PM PDT 24
Finished Mar 21 01:30:56 PM PDT 24
Peak memory 200732 kb
Host smart-202e4908-227f-49c2-9023-760055d548bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012360789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.4012360789
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3855090920
Short name T480
Test name
Test status
Simulation time 794743046 ps
CPU time 4.16 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:31:01 PM PDT 24
Peak memory 201068 kb
Host smart-899de4a9-8f16-4cb9-a927-c87d2ca6366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855090920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3855090920
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.737679053
Short name T163
Test name
Test status
Simulation time 148195479 ps
CPU time 1.1 seconds
Started Mar 21 01:30:52 PM PDT 24
Finished Mar 21 01:30:54 PM PDT 24
Peak memory 200860 kb
Host smart-6ab388a3-67a1-4bc0-ae91-4c03bf7e171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737679053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.737679053
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1912144749
Short name T252
Test name
Test status
Simulation time 120448895 ps
CPU time 1.22 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:56 PM PDT 24
Peak memory 200960 kb
Host smart-c4a16648-09a1-4177-83e3-86e2ead0e065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912144749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1912144749
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3028938624
Short name T333
Test name
Test status
Simulation time 202038173 ps
CPU time 1.34 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:30:58 PM PDT 24
Peak memory 200792 kb
Host smart-952e8e54-e82e-41fb-8b4f-bc457f1b1d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028938624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3028938624
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1933184646
Short name T219
Test name
Test status
Simulation time 137493696 ps
CPU time 1.69 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 201044 kb
Host smart-dc898672-6c5a-4020-8bea-54c4f7851598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933184646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1933184646
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3023685378
Short name T434
Test name
Test status
Simulation time 246444880 ps
CPU time 1.49 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 200864 kb
Host smart-d4ce7c97-27de-42fe-8cc3-0905760ed4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023685378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3023685378
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.439079286
Short name T259
Test name
Test status
Simulation time 95690320 ps
CPU time 0.92 seconds
Started Mar 21 01:30:55 PM PDT 24
Finished Mar 21 01:30:57 PM PDT 24
Peak memory 200752 kb
Host smart-a9fb01a9-66c0-45d2-a18d-59e3145080fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439079286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.439079286
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.497257099
Short name T33
Test name
Test status
Simulation time 2406374073 ps
CPU time 8.07 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:31:05 PM PDT 24
Peak memory 222700 kb
Host smart-d213482c-022b-4a6a-bf53-e20852cbf8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497257099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.497257099
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3303802357
Short name T506
Test name
Test status
Simulation time 244532977 ps
CPU time 1.15 seconds
Started Mar 21 01:30:52 PM PDT 24
Finished Mar 21 01:30:54 PM PDT 24
Peak memory 218260 kb
Host smart-e89b175b-17cb-4bd6-a73b-a5a63f3cd5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303802357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3303802357
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3886583209
Short name T16
Test name
Test status
Simulation time 151328477 ps
CPU time 0.8 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:56 PM PDT 24
Peak memory 200748 kb
Host smart-2c951304-d05d-41ec-9099-e5cc0ecef38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886583209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3886583209
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1816236493
Short name T124
Test name
Test status
Simulation time 1352842641 ps
CPU time 4.86 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 201064 kb
Host smart-adf04019-fadd-495b-8842-74f1158fb43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816236493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1816236493
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2487907838
Short name T193
Test name
Test status
Simulation time 161022659 ps
CPU time 1.25 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:30:58 PM PDT 24
Peak memory 200752 kb
Host smart-095903ba-a527-403a-bc0d-8ac2dedd5886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487907838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2487907838
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.760727405
Short name T526
Test name
Test status
Simulation time 118149550 ps
CPU time 1.21 seconds
Started Mar 21 01:30:53 PM PDT 24
Finished Mar 21 01:30:54 PM PDT 24
Peak memory 201048 kb
Host smart-fee94c57-2093-462e-b7ac-3679ba87077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760727405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.760727405
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2567340799
Short name T53
Test name
Test status
Simulation time 328983055 ps
CPU time 2.17 seconds
Started Mar 21 01:30:52 PM PDT 24
Finished Mar 21 01:30:55 PM PDT 24
Peak memory 201048 kb
Host smart-bdd290c8-b70e-4a87-ad8c-c639c314e292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567340799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2567340799
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.918034421
Short name T467
Test name
Test status
Simulation time 481193823 ps
CPU time 2.63 seconds
Started Mar 21 01:30:56 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 200888 kb
Host smart-11d33493-e328-410a-a848-12b8846e78fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918034421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.918034421
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2241116541
Short name T176
Test name
Test status
Simulation time 195400610 ps
CPU time 1.28 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:57 PM PDT 24
Peak memory 200780 kb
Host smart-4d6c4ae9-b7d1-4d7f-be08-805d154159fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241116541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2241116541
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1539608387
Short name T192
Test name
Test status
Simulation time 64665307 ps
CPU time 0.76 seconds
Started Mar 21 01:31:04 PM PDT 24
Finished Mar 21 01:31:05 PM PDT 24
Peak memory 200844 kb
Host smart-53985df1-658a-4057-863a-81770d33bb94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539608387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1539608387
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1164575756
Short name T416
Test name
Test status
Simulation time 1884495862 ps
CPU time 7.68 seconds
Started Mar 21 01:31:02 PM PDT 24
Finished Mar 21 01:31:10 PM PDT 24
Peak memory 218532 kb
Host smart-4b9755aa-d3de-4da1-85cf-a6f5c23192ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164575756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1164575756
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2481398208
Short name T325
Test name
Test status
Simulation time 243947695 ps
CPU time 1.1 seconds
Started Mar 21 01:31:04 PM PDT 24
Finished Mar 21 01:31:05 PM PDT 24
Peak memory 218192 kb
Host smart-36304f20-fabd-421c-9613-3622c926f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481398208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2481398208
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2876602100
Short name T411
Test name
Test status
Simulation time 142329395 ps
CPU time 0.95 seconds
Started Mar 21 01:30:55 PM PDT 24
Finished Mar 21 01:30:57 PM PDT 24
Peak memory 200756 kb
Host smart-32b9dfc2-fccb-44f1-8daf-3b924b9e7f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876602100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2876602100
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3033177304
Short name T371
Test name
Test status
Simulation time 978701171 ps
CPU time 4.77 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:31:00 PM PDT 24
Peak memory 201080 kb
Host smart-23e8c69a-f19d-4afd-8077-89a08eb94e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033177304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3033177304
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3704387619
Short name T167
Test name
Test status
Simulation time 190291835 ps
CPU time 1.19 seconds
Started Mar 21 01:31:05 PM PDT 24
Finished Mar 21 01:31:06 PM PDT 24
Peak memory 200948 kb
Host smart-0582d909-e769-4c4d-96f6-b9c87b626ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704387619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3704387619
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3968022661
Short name T392
Test name
Test status
Simulation time 192497168 ps
CPU time 1.33 seconds
Started Mar 21 01:30:54 PM PDT 24
Finished Mar 21 01:30:56 PM PDT 24
Peak memory 201044 kb
Host smart-9082a15e-639d-44ad-baec-38ae9cb3fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968022661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3968022661
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2765296795
Short name T100
Test name
Test status
Simulation time 1155080286 ps
CPU time 6.12 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:09 PM PDT 24
Peak memory 201044 kb
Host smart-72a2ac35-824e-4a16-a0ab-9e653c5284ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765296795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2765296795
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2060024827
Short name T482
Test name
Test status
Simulation time 328707279 ps
CPU time 2.24 seconds
Started Mar 21 01:31:01 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 209088 kb
Host smart-d63b0d9b-1d2e-4926-af3c-9c0c3b7e43e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060024827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2060024827
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3659126290
Short name T82
Test name
Test status
Simulation time 246617077 ps
CPU time 1.59 seconds
Started Mar 21 01:31:01 PM PDT 24
Finished Mar 21 01:31:03 PM PDT 24
Peak memory 200856 kb
Host smart-a5777665-5f54-4188-92f3-30ac2089fe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659126290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3659126290
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1464497534
Short name T155
Test name
Test status
Simulation time 75566311 ps
CPU time 0.78 seconds
Started Mar 21 01:31:04 PM PDT 24
Finished Mar 21 01:31:05 PM PDT 24
Peak memory 200760 kb
Host smart-aa39236e-8b44-4f84-98bd-8752458085ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464497534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1464497534
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1221493614
Short name T438
Test name
Test status
Simulation time 2167764454 ps
CPU time 8.08 seconds
Started Mar 21 01:31:05 PM PDT 24
Finished Mar 21 01:31:14 PM PDT 24
Peak memory 218672 kb
Host smart-5e7f69f4-acf2-48b8-9c5f-1614b1585311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221493614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1221493614
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3524106559
Short name T8
Test name
Test status
Simulation time 244699589 ps
CPU time 1.21 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 218168 kb
Host smart-ad50d168-08a1-433d-b095-5d0022eeae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524106559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3524106559
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.27012003
Short name T199
Test name
Test status
Simulation time 109289426 ps
CPU time 0.8 seconds
Started Mar 21 01:31:01 PM PDT 24
Finished Mar 21 01:31:02 PM PDT 24
Peak memory 200696 kb
Host smart-bc84de68-18a0-4271-921a-67873e1068b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27012003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.27012003
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1475675149
Short name T179
Test name
Test status
Simulation time 1501123452 ps
CPU time 5.81 seconds
Started Mar 21 01:31:04 PM PDT 24
Finished Mar 21 01:31:11 PM PDT 24
Peak memory 201112 kb
Host smart-27a8364c-313d-441f-abe5-22a87cab285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475675149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1475675149
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3557549237
Short name T201
Test name
Test status
Simulation time 144615626 ps
CPU time 1.08 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:05 PM PDT 24
Peak memory 200780 kb
Host smart-1caae810-a8aa-44c4-9ecf-8faa33dc5879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557549237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3557549237
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.501442841
Short name T228
Test name
Test status
Simulation time 118863493 ps
CPU time 1.2 seconds
Started Mar 21 01:31:02 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 201064 kb
Host smart-48c23061-0f4a-4780-b1b9-98bb3d04face
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501442841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.501442841
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2089060409
Short name T198
Test name
Test status
Simulation time 2178966299 ps
CPU time 10.5 seconds
Started Mar 21 01:31:02 PM PDT 24
Finished Mar 21 01:31:13 PM PDT 24
Peak memory 201080 kb
Host smart-85808dbc-9c40-422e-9989-eb4d6a8ecbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089060409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2089060409
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3853043972
Short name T268
Test name
Test status
Simulation time 348778216 ps
CPU time 2.4 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:06 PM PDT 24
Peak memory 200912 kb
Host smart-b04d31e0-b00f-4e7b-a5d5-6d2aa5eb547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853043972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3853043972
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3544330986
Short name T475
Test name
Test status
Simulation time 120608929 ps
CPU time 0.99 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 200864 kb
Host smart-c2c7e67d-0bc2-4f01-baeb-b4d8b4743cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544330986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3544330986
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2586724266
Short name T348
Test name
Test status
Simulation time 84407997 ps
CPU time 0.82 seconds
Started Mar 21 01:31:02 PM PDT 24
Finished Mar 21 01:31:03 PM PDT 24
Peak memory 200716 kb
Host smart-5c8b47ac-9218-4cec-a0de-f6e441c6fe1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586724266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2586724266
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.968509798
Short name T389
Test name
Test status
Simulation time 1225539019 ps
CPU time 5.6 seconds
Started Mar 21 01:31:02 PM PDT 24
Finished Mar 21 01:31:09 PM PDT 24
Peak memory 222624 kb
Host smart-39b3d438-f656-4617-8137-393264148a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968509798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.968509798
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3586807292
Short name T352
Test name
Test status
Simulation time 244276577 ps
CPU time 1.11 seconds
Started Mar 21 01:31:05 PM PDT 24
Finished Mar 21 01:31:06 PM PDT 24
Peak memory 218204 kb
Host smart-2d089882-fa40-40e5-a9fa-4b0a1cc37222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586807292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3586807292
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.497470343
Short name T18
Test name
Test status
Simulation time 211820812 ps
CPU time 0.96 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 200748 kb
Host smart-962d09c9-6b1b-4371-9198-37bd22e80185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497470343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.497470343
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1076402262
Short name T48
Test name
Test status
Simulation time 1437877543 ps
CPU time 6.09 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:09 PM PDT 24
Peak memory 201032 kb
Host smart-1a2beeaa-239c-4338-93e8-8c6c3034c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076402262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1076402262
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.635918721
Short name T214
Test name
Test status
Simulation time 102069570 ps
CPU time 1.03 seconds
Started Mar 21 01:31:02 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 200868 kb
Host smart-96737926-536c-451c-95d5-70939d1652ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635918721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.635918721
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2652826406
Short name T327
Test name
Test status
Simulation time 227237035 ps
CPU time 1.46 seconds
Started Mar 21 01:31:02 PM PDT 24
Finished Mar 21 01:31:03 PM PDT 24
Peak memory 201048 kb
Host smart-d77062ea-cf7a-4ba8-89d8-583f188ff8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652826406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2652826406
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2126271513
Short name T380
Test name
Test status
Simulation time 4625684558 ps
CPU time 17.05 seconds
Started Mar 21 01:31:02 PM PDT 24
Finished Mar 21 01:31:19 PM PDT 24
Peak memory 209348 kb
Host smart-5e16d8d3-a70c-4b16-b10b-ad224d561238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126271513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2126271513
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3998504037
Short name T269
Test name
Test status
Simulation time 432946011 ps
CPU time 2.36 seconds
Started Mar 21 01:31:13 PM PDT 24
Finished Mar 21 01:31:15 PM PDT 24
Peak memory 209208 kb
Host smart-669c935d-cb60-49b0-8c73-11d8d1860890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998504037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3998504037
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.463388816
Short name T195
Test name
Test status
Simulation time 262040243 ps
CPU time 1.47 seconds
Started Mar 21 01:31:04 PM PDT 24
Finished Mar 21 01:31:06 PM PDT 24
Peak memory 200988 kb
Host smart-3064deba-d64a-4f03-b927-d498b6bcd1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463388816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.463388816
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3722376523
Short name T381
Test name
Test status
Simulation time 64120251 ps
CPU time 0.75 seconds
Started Mar 21 01:31:10 PM PDT 24
Finished Mar 21 01:31:11 PM PDT 24
Peak memory 200736 kb
Host smart-7b220180-231a-41d4-afaa-5956513182b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722376523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3722376523
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4010449542
Short name T448
Test name
Test status
Simulation time 2361915881 ps
CPU time 8.44 seconds
Started Mar 21 01:31:04 PM PDT 24
Finished Mar 21 01:31:12 PM PDT 24
Peak memory 222644 kb
Host smart-241f6087-bb01-464a-b727-aaf6bf96ed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010449542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4010449542
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2438023100
Short name T146
Test name
Test status
Simulation time 243731527 ps
CPU time 1.08 seconds
Started Mar 21 01:31:13 PM PDT 24
Finished Mar 21 01:31:14 PM PDT 24
Peak memory 218148 kb
Host smart-cfc3ee75-9af0-4b6a-9b11-5828c896f6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438023100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2438023100
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3774631538
Short name T294
Test name
Test status
Simulation time 115943029 ps
CPU time 0.79 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 200636 kb
Host smart-220b9ab1-03e3-47d0-84cd-d9f5289d0a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774631538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3774631538
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3232654709
Short name T418
Test name
Test status
Simulation time 855323204 ps
CPU time 4.53 seconds
Started Mar 21 01:31:04 PM PDT 24
Finished Mar 21 01:31:09 PM PDT 24
Peak memory 201032 kb
Host smart-d8481adc-c83f-4310-ba4d-593224620f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232654709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3232654709
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1567518999
Short name T286
Test name
Test status
Simulation time 155620742 ps
CPU time 1.13 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:04 PM PDT 24
Peak memory 200768 kb
Host smart-737f0f14-2d99-46f6-8db0-c6103833a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567518999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1567518999
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3738073283
Short name T245
Test name
Test status
Simulation time 248954371 ps
CPU time 1.59 seconds
Started Mar 21 01:31:03 PM PDT 24
Finished Mar 21 01:31:05 PM PDT 24
Peak memory 200964 kb
Host smart-8c9a24f8-01c6-4e46-807b-1b633df390c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738073283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3738073283
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3288259964
Short name T222
Test name
Test status
Simulation time 2038835412 ps
CPU time 7.96 seconds
Started Mar 21 01:31:09 PM PDT 24
Finished Mar 21 01:31:17 PM PDT 24
Peak memory 200960 kb
Host smart-24618ad0-fd77-448e-a7a3-0eb0d17b2852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288259964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3288259964
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.951455471
Short name T343
Test name
Test status
Simulation time 376659838 ps
CPU time 2.37 seconds
Started Mar 21 01:31:14 PM PDT 24
Finished Mar 21 01:31:17 PM PDT 24
Peak memory 201004 kb
Host smart-142a52b0-337a-4e52-8cfe-2ccae07b3d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951455471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.951455471
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3617941620
Short name T375
Test name
Test status
Simulation time 115747605 ps
CPU time 0.97 seconds
Started Mar 21 01:31:02 PM PDT 24
Finished Mar 21 01:31:03 PM PDT 24
Peak memory 200864 kb
Host smart-c850113d-0476-4d37-a041-3f5b50e41305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617941620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3617941620
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.4228413296
Short name T502
Test name
Test status
Simulation time 71372448 ps
CPU time 0.75 seconds
Started Mar 21 01:31:09 PM PDT 24
Finished Mar 21 01:31:09 PM PDT 24
Peak memory 200716 kb
Host smart-6dd739ad-ea8c-4064-9358-474dba8313e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228413296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4228413296
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3083888397
Short name T42
Test name
Test status
Simulation time 1894631265 ps
CPU time 7.41 seconds
Started Mar 21 01:31:14 PM PDT 24
Finished Mar 21 01:31:21 PM PDT 24
Peak memory 218604 kb
Host smart-56d48b5e-4a5e-40a5-9556-852b8b1a486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083888397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3083888397
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2639782191
Short name T495
Test name
Test status
Simulation time 244166459 ps
CPU time 1.17 seconds
Started Mar 21 01:31:09 PM PDT 24
Finished Mar 21 01:31:10 PM PDT 24
Peak memory 218260 kb
Host smart-e77f3123-68a6-4885-b6d3-b75a16e8dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639782191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2639782191
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1377149648
Short name T185
Test name
Test status
Simulation time 87071235 ps
CPU time 0.76 seconds
Started Mar 21 01:31:11 PM PDT 24
Finished Mar 21 01:31:12 PM PDT 24
Peak memory 200648 kb
Host smart-69cceb8d-3333-41a3-880c-8813ae7e3f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377149648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1377149648
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1445589755
Short name T91
Test name
Test status
Simulation time 997293015 ps
CPU time 5.24 seconds
Started Mar 21 01:31:08 PM PDT 24
Finished Mar 21 01:31:13 PM PDT 24
Peak memory 201084 kb
Host smart-12210bf4-1acc-47a1-a611-1eab18e30c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445589755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1445589755
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.754869674
Short name T156
Test name
Test status
Simulation time 107064876 ps
CPU time 1.01 seconds
Started Mar 21 01:31:10 PM PDT 24
Finished Mar 21 01:31:11 PM PDT 24
Peak memory 200864 kb
Host smart-fc8be9de-d88a-434f-b311-d8fa46c70910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754869674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.754869674
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.4228324566
Short name T344
Test name
Test status
Simulation time 194733728 ps
CPU time 1.33 seconds
Started Mar 21 01:31:12 PM PDT 24
Finished Mar 21 01:31:13 PM PDT 24
Peak memory 200940 kb
Host smart-c2735aed-7540-44aa-878e-5ac716ec4c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228324566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4228324566
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2045795264
Short name T409
Test name
Test status
Simulation time 1544504519 ps
CPU time 7.58 seconds
Started Mar 21 01:31:10 PM PDT 24
Finished Mar 21 01:31:18 PM PDT 24
Peak memory 209232 kb
Host smart-caefa3b7-fa56-4987-b6a4-d9c66be4f210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045795264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2045795264
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1865608072
Short name T131
Test name
Test status
Simulation time 568290383 ps
CPU time 2.85 seconds
Started Mar 21 01:31:11 PM PDT 24
Finished Mar 21 01:31:14 PM PDT 24
Peak memory 200940 kb
Host smart-eb2898ce-a3e6-4d3e-99ed-eec28de38169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865608072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1865608072
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3937581360
Short name T264
Test name
Test status
Simulation time 131288643 ps
CPU time 1.18 seconds
Started Mar 21 01:31:09 PM PDT 24
Finished Mar 21 01:31:10 PM PDT 24
Peak memory 200864 kb
Host smart-91682748-401e-4be6-9eed-d7be503f4c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937581360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3937581360
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3447361419
Short name T391
Test name
Test status
Simulation time 60037102 ps
CPU time 0.72 seconds
Started Mar 21 01:31:13 PM PDT 24
Finished Mar 21 01:31:14 PM PDT 24
Peak memory 200724 kb
Host smart-15e00989-7d20-43c9-a63b-875ef04dbcb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447361419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3447361419
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1295033213
Short name T410
Test name
Test status
Simulation time 2362724122 ps
CPU time 8.3 seconds
Started Mar 21 01:31:08 PM PDT 24
Finished Mar 21 01:31:16 PM PDT 24
Peak memory 218364 kb
Host smart-fb78f1a5-836d-401a-a37d-cfbd0f3af4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295033213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1295033213
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.105602803
Short name T230
Test name
Test status
Simulation time 243917604 ps
CPU time 1.1 seconds
Started Mar 21 01:31:14 PM PDT 24
Finished Mar 21 01:31:15 PM PDT 24
Peak memory 218320 kb
Host smart-ebe322b5-a65f-4d63-aa3d-0eac09c0f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105602803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.105602803
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3272845193
Short name T20
Test name
Test status
Simulation time 176243783 ps
CPU time 0.96 seconds
Started Mar 21 01:31:12 PM PDT 24
Finished Mar 21 01:31:13 PM PDT 24
Peak memory 200712 kb
Host smart-9e881a4d-ddf5-4162-94a6-d389a56dc190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272845193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3272845193
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3689056261
Short name T425
Test name
Test status
Simulation time 1446173169 ps
CPU time 5.69 seconds
Started Mar 21 01:31:13 PM PDT 24
Finished Mar 21 01:31:19 PM PDT 24
Peak memory 201020 kb
Host smart-595eb314-4599-41c8-ae90-42dca5b2be2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689056261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3689056261
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.794361473
Short name T489
Test name
Test status
Simulation time 145115451 ps
CPU time 1.12 seconds
Started Mar 21 01:31:10 PM PDT 24
Finished Mar 21 01:31:12 PM PDT 24
Peak memory 200780 kb
Host smart-fecad295-9057-4107-942d-1ab0bec62c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794361473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.794361473
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1492847237
Short name T492
Test name
Test status
Simulation time 190024722 ps
CPU time 1.38 seconds
Started Mar 21 01:31:12 PM PDT 24
Finished Mar 21 01:31:14 PM PDT 24
Peak memory 201032 kb
Host smart-2bfc003d-1406-4edd-89d8-90fcdd48ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492847237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1492847237
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.4054222064
Short name T363
Test name
Test status
Simulation time 7209088977 ps
CPU time 28.44 seconds
Started Mar 21 01:31:13 PM PDT 24
Finished Mar 21 01:31:41 PM PDT 24
Peak memory 201084 kb
Host smart-4890ad94-ca2b-4dba-8b61-88f3e2f95ef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054222064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.4054222064
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.1951027157
Short name T329
Test name
Test status
Simulation time 393194126 ps
CPU time 2.38 seconds
Started Mar 21 01:31:09 PM PDT 24
Finished Mar 21 01:31:12 PM PDT 24
Peak memory 200844 kb
Host smart-6d92f596-b719-4394-9ea4-fa4e40c7b570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951027157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1951027157
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2270493340
Short name T483
Test name
Test status
Simulation time 200277575 ps
CPU time 1.24 seconds
Started Mar 21 01:31:09 PM PDT 24
Finished Mar 21 01:31:11 PM PDT 24
Peak memory 200864 kb
Host smart-b8dec985-811d-4c54-aa51-cefae2c7ab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270493340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2270493340
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1748683488
Short name T379
Test name
Test status
Simulation time 133784320 ps
CPU time 0.94 seconds
Started Mar 21 01:31:11 PM PDT 24
Finished Mar 21 01:31:12 PM PDT 24
Peak memory 200728 kb
Host smart-96e88bb2-cf09-4a2f-a35e-b80dc545cbac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748683488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1748683488
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2983624071
Short name T324
Test name
Test status
Simulation time 1224623977 ps
CPU time 5.74 seconds
Started Mar 21 01:31:12 PM PDT 24
Finished Mar 21 01:31:18 PM PDT 24
Peak memory 217764 kb
Host smart-9ac679f2-2739-4fa2-b8df-0524d84918dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983624071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2983624071
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1548572214
Short name T310
Test name
Test status
Simulation time 244523239 ps
CPU time 1.08 seconds
Started Mar 21 01:31:12 PM PDT 24
Finished Mar 21 01:31:13 PM PDT 24
Peak memory 218320 kb
Host smart-bfa55745-4518-4e44-bec5-e5bdd1e94fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548572214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1548572214
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2502492228
Short name T322
Test name
Test status
Simulation time 199819141 ps
CPU time 0.9 seconds
Started Mar 21 01:31:10 PM PDT 24
Finished Mar 21 01:31:11 PM PDT 24
Peak memory 200736 kb
Host smart-17e581a7-c13c-43b4-b1a3-e21692def846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502492228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2502492228
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2208305806
Short name T451
Test name
Test status
Simulation time 1631618378 ps
CPU time 6.2 seconds
Started Mar 21 01:31:11 PM PDT 24
Finished Mar 21 01:31:17 PM PDT 24
Peak memory 201032 kb
Host smart-a9b3f226-6d96-441c-958c-ba38fb01ff66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208305806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2208305806
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2371626996
Short name T530
Test name
Test status
Simulation time 106900232 ps
CPU time 0.99 seconds
Started Mar 21 01:31:12 PM PDT 24
Finished Mar 21 01:31:13 PM PDT 24
Peak memory 200844 kb
Host smart-93861e6f-714b-4922-9187-5147517e9285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371626996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2371626996
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3161887959
Short name T248
Test name
Test status
Simulation time 206956659 ps
CPU time 1.38 seconds
Started Mar 21 01:31:10 PM PDT 24
Finished Mar 21 01:31:12 PM PDT 24
Peak memory 201028 kb
Host smart-cd2fb6b1-4a33-4af1-a360-990999c9cffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161887959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3161887959
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1061282146
Short name T232
Test name
Test status
Simulation time 3256180309 ps
CPU time 13.23 seconds
Started Mar 21 01:31:11 PM PDT 24
Finished Mar 21 01:31:24 PM PDT 24
Peak memory 209416 kb
Host smart-92cad54b-32a8-4034-9b02-b0dcb275e592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061282146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1061282146
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2372910072
Short name T84
Test name
Test status
Simulation time 126528834 ps
CPU time 1.64 seconds
Started Mar 21 01:31:11 PM PDT 24
Finished Mar 21 01:31:12 PM PDT 24
Peak memory 209160 kb
Host smart-9d49c357-446f-475e-bda3-eef343d93c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372910072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2372910072
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.461851228
Short name T166
Test name
Test status
Simulation time 147529585 ps
CPU time 1.24 seconds
Started Mar 21 01:31:12 PM PDT 24
Finished Mar 21 01:31:13 PM PDT 24
Peak memory 200876 kb
Host smart-98564f8f-fd63-4ce7-b3c9-fcdf88f57606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461851228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.461851228
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3042432437
Short name T366
Test name
Test status
Simulation time 70743851 ps
CPU time 0.78 seconds
Started Mar 21 01:29:26 PM PDT 24
Finished Mar 21 01:29:27 PM PDT 24
Peak memory 200696 kb
Host smart-1aea05d6-10b5-4dba-9ea9-2ab56945188e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042432437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3042432437
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2466657280
Short name T510
Test name
Test status
Simulation time 1232174005 ps
CPU time 5.81 seconds
Started Mar 21 01:29:27 PM PDT 24
Finished Mar 21 01:29:33 PM PDT 24
Peak memory 218544 kb
Host smart-3c14c0ed-7d99-4075-8464-9183389bbce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466657280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2466657280
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3481477691
Short name T321
Test name
Test status
Simulation time 244167239 ps
CPU time 1.08 seconds
Started Mar 21 01:29:29 PM PDT 24
Finished Mar 21 01:29:31 PM PDT 24
Peak memory 218012 kb
Host smart-c1d206ab-6a56-4a0b-938f-c4b1b98dc5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481477691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3481477691
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.217753920
Short name T422
Test name
Test status
Simulation time 101150505 ps
CPU time 0.76 seconds
Started Mar 21 01:29:30 PM PDT 24
Finished Mar 21 01:29:31 PM PDT 24
Peak memory 200732 kb
Host smart-2dd1f20e-e043-43a8-a8fa-b9c7c3538890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217753920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.217753920
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.639184069
Short name T122
Test name
Test status
Simulation time 1905544956 ps
CPU time 8.6 seconds
Started Mar 21 01:29:26 PM PDT 24
Finished Mar 21 01:29:35 PM PDT 24
Peak memory 201000 kb
Host smart-3c5205f4-c308-43fc-8fcc-9b8bd16eeefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639184069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.639184069
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3567871299
Short name T66
Test name
Test status
Simulation time 16515337386 ps
CPU time 27.86 seconds
Started Mar 21 01:29:27 PM PDT 24
Finished Mar 21 01:29:55 PM PDT 24
Peak memory 217748 kb
Host smart-baee0bfa-ec4a-4c7f-b7a0-f0b55dbda81d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567871299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3567871299
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.801054024
Short name T404
Test name
Test status
Simulation time 141166524 ps
CPU time 1.14 seconds
Started Mar 21 01:29:30 PM PDT 24
Finished Mar 21 01:29:31 PM PDT 24
Peak memory 200792 kb
Host smart-f8550123-a839-4299-911e-b2d5c5bbf714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801054024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.801054024
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3191211379
Short name T441
Test name
Test status
Simulation time 194833428 ps
CPU time 1.43 seconds
Started Mar 21 01:29:26 PM PDT 24
Finished Mar 21 01:29:28 PM PDT 24
Peak memory 200936 kb
Host smart-32b49414-7036-43ca-bb66-d9f6b1af6e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191211379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3191211379
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1145786467
Short name T83
Test name
Test status
Simulation time 11542491096 ps
CPU time 43.33 seconds
Started Mar 21 01:29:30 PM PDT 24
Finished Mar 21 01:30:13 PM PDT 24
Peak memory 201124 kb
Host smart-3ab96acd-3211-472c-84f6-079f094b3c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145786467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1145786467
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1602103295
Short name T54
Test name
Test status
Simulation time 248450889 ps
CPU time 1.93 seconds
Started Mar 21 01:29:27 PM PDT 24
Finished Mar 21 01:29:29 PM PDT 24
Peak memory 200824 kb
Host smart-bf83cf96-cc37-4439-a041-003e85c87cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602103295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1602103295
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3219986661
Short name T129
Test name
Test status
Simulation time 173792064 ps
CPU time 1.08 seconds
Started Mar 21 01:29:28 PM PDT 24
Finished Mar 21 01:29:29 PM PDT 24
Peak memory 200988 kb
Host smart-2d1090c6-68ea-45c2-96a9-9e4cb39c8395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219986661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3219986661
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3240210607
Short name T244
Test name
Test status
Simulation time 65693187 ps
CPU time 0.74 seconds
Started Mar 21 01:31:18 PM PDT 24
Finished Mar 21 01:31:18 PM PDT 24
Peak memory 200740 kb
Host smart-f9a9c01e-9ca1-4f83-97cb-67e2a80e5c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240210607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3240210607
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1900336280
Short name T347
Test name
Test status
Simulation time 2359625157 ps
CPU time 9.22 seconds
Started Mar 21 01:31:18 PM PDT 24
Finished Mar 21 01:31:28 PM PDT 24
Peak memory 218676 kb
Host smart-9c7ee03a-ce71-4957-9e38-867e8d5a581f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900336280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1900336280
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3555976164
Short name T318
Test name
Test status
Simulation time 243981218 ps
CPU time 1.11 seconds
Started Mar 21 01:31:20 PM PDT 24
Finished Mar 21 01:31:21 PM PDT 24
Peak memory 218268 kb
Host smart-1cb866b8-5e64-46e6-8fdc-cb115f631329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555976164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3555976164
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.4171372739
Short name T241
Test name
Test status
Simulation time 195456871 ps
CPU time 0.9 seconds
Started Mar 21 01:31:09 PM PDT 24
Finished Mar 21 01:31:10 PM PDT 24
Peak memory 200656 kb
Host smart-2b585790-f73e-4c61-b7bd-2f50ea6cdb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171372739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.4171372739
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3522025912
Short name T94
Test name
Test status
Simulation time 1008904039 ps
CPU time 5.13 seconds
Started Mar 21 01:31:12 PM PDT 24
Finished Mar 21 01:31:17 PM PDT 24
Peak memory 201032 kb
Host smart-bb1939d1-8a66-4c9a-ae4f-58767a8f5428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522025912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3522025912
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4153433874
Short name T47
Test name
Test status
Simulation time 155033640 ps
CPU time 1.15 seconds
Started Mar 21 01:31:19 PM PDT 24
Finished Mar 21 01:31:21 PM PDT 24
Peak memory 200784 kb
Host smart-2a2bb5cf-7818-4fcd-b6f9-f75e8ae2d554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153433874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4153433874
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2555367396
Short name T308
Test name
Test status
Simulation time 108110178 ps
CPU time 1.16 seconds
Started Mar 21 01:31:08 PM PDT 24
Finished Mar 21 01:31:10 PM PDT 24
Peak memory 201052 kb
Host smart-4af148b7-7a91-4f5b-9299-69de935336d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555367396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2555367396
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3425723269
Short name T445
Test name
Test status
Simulation time 3237803054 ps
CPU time 12.33 seconds
Started Mar 21 01:31:18 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 201136 kb
Host smart-9fbbe19c-efbe-42ca-b309-353773832e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425723269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3425723269
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3803291795
Short name T224
Test name
Test status
Simulation time 130608830 ps
CPU time 1.63 seconds
Started Mar 21 01:31:20 PM PDT 24
Finished Mar 21 01:31:22 PM PDT 24
Peak memory 200924 kb
Host smart-f2af7e2d-7da1-4dfd-abd0-f9761daa9828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803291795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3803291795
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2753684904
Short name T275
Test name
Test status
Simulation time 153403854 ps
CPU time 1.13 seconds
Started Mar 21 01:31:11 PM PDT 24
Finished Mar 21 01:31:12 PM PDT 24
Peak memory 200856 kb
Host smart-27831890-d60a-4d4a-93bb-63e8b92bbfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753684904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2753684904
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.4266494663
Short name T395
Test name
Test status
Simulation time 66448646 ps
CPU time 0.76 seconds
Started Mar 21 01:31:24 PM PDT 24
Finished Mar 21 01:31:25 PM PDT 24
Peak memory 200704 kb
Host smart-72ebd4ec-2c8a-4d2d-a269-0cd976aad7b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266494663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.4266494663
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1863564624
Short name T429
Test name
Test status
Simulation time 1224122709 ps
CPU time 5.64 seconds
Started Mar 21 01:31:21 PM PDT 24
Finished Mar 21 01:31:26 PM PDT 24
Peak memory 217496 kb
Host smart-a320aa35-4610-4472-b266-dbab74a8d0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863564624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1863564624
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4179307360
Short name T215
Test name
Test status
Simulation time 244358380 ps
CPU time 1.19 seconds
Started Mar 21 01:31:19 PM PDT 24
Finished Mar 21 01:31:20 PM PDT 24
Peak memory 218152 kb
Host smart-3a007c71-4591-4af3-bf72-cf4bbad875e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179307360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4179307360
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2942634939
Short name T472
Test name
Test status
Simulation time 99034948 ps
CPU time 0.76 seconds
Started Mar 21 01:31:19 PM PDT 24
Finished Mar 21 01:31:20 PM PDT 24
Peak memory 200756 kb
Host smart-dd53ec1e-2249-4fea-b8f8-995427249061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942634939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2942634939
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1345730713
Short name T368
Test name
Test status
Simulation time 762372245 ps
CPU time 4.09 seconds
Started Mar 21 01:31:19 PM PDT 24
Finished Mar 21 01:31:23 PM PDT 24
Peak memory 201052 kb
Host smart-604390d2-d572-4ad8-959e-7bc3e6d85782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345730713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1345730713
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1000622682
Short name T362
Test name
Test status
Simulation time 154526151 ps
CPU time 1.16 seconds
Started Mar 21 01:31:21 PM PDT 24
Finished Mar 21 01:31:22 PM PDT 24
Peak memory 200868 kb
Host smart-baf6a005-e1bb-4cb0-ad68-f5e3602200db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000622682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1000622682
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.4178675106
Short name T349
Test name
Test status
Simulation time 244786389 ps
CPU time 1.5 seconds
Started Mar 21 01:31:20 PM PDT 24
Finished Mar 21 01:31:21 PM PDT 24
Peak memory 201028 kb
Host smart-11d4c6ca-4bc9-44bf-b15a-e0c6fc781c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178675106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4178675106
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.694714056
Short name T508
Test name
Test status
Simulation time 1883829336 ps
CPU time 9.2 seconds
Started Mar 21 01:31:20 PM PDT 24
Finished Mar 21 01:31:29 PM PDT 24
Peak memory 201000 kb
Host smart-f7347390-2ae7-41a9-8114-5f69d0c5494b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694714056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.694714056
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.234726200
Short name T4
Test name
Test status
Simulation time 432619309 ps
CPU time 2.34 seconds
Started Mar 21 01:31:20 PM PDT 24
Finished Mar 21 01:31:22 PM PDT 24
Peak memory 209056 kb
Host smart-63700cb3-24c3-4efb-9a3b-4c123f828b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234726200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.234726200
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2953368268
Short name T513
Test name
Test status
Simulation time 202402146 ps
CPU time 1.3 seconds
Started Mar 21 01:31:20 PM PDT 24
Finished Mar 21 01:31:21 PM PDT 24
Peak memory 200864 kb
Host smart-f753901f-d203-4a36-ace9-5523d5095f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953368268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2953368268
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.253796289
Short name T273
Test name
Test status
Simulation time 87246791 ps
CPU time 0.83 seconds
Started Mar 21 01:31:19 PM PDT 24
Finished Mar 21 01:31:20 PM PDT 24
Peak memory 200704 kb
Host smart-d46299f3-0113-4be0-84fc-f0cf5ecd8220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253796289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.253796289
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3936702649
Short name T37
Test name
Test status
Simulation time 2345970882 ps
CPU time 8.14 seconds
Started Mar 21 01:31:20 PM PDT 24
Finished Mar 21 01:31:28 PM PDT 24
Peak memory 218224 kb
Host smart-8541fa71-09df-4688-a1fd-140d3520b9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936702649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3936702649
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.541973917
Short name T170
Test name
Test status
Simulation time 245318945 ps
CPU time 1.13 seconds
Started Mar 21 01:31:22 PM PDT 24
Finished Mar 21 01:31:23 PM PDT 24
Peak memory 218112 kb
Host smart-654f0b4c-92e4-4f75-ace9-bc1e3011057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541973917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.541973917
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3210338280
Short name T5
Test name
Test status
Simulation time 113150647 ps
CPU time 0.77 seconds
Started Mar 21 01:31:17 PM PDT 24
Finished Mar 21 01:31:18 PM PDT 24
Peak memory 200732 kb
Host smart-180e1a23-e499-4cf2-b527-8e557c65414c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210338280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3210338280
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2956016465
Short name T202
Test name
Test status
Simulation time 1496129219 ps
CPU time 5.99 seconds
Started Mar 21 01:31:18 PM PDT 24
Finished Mar 21 01:31:24 PM PDT 24
Peak memory 201000 kb
Host smart-f9fe3688-5b51-48b4-8348-f0f6d84ba7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956016465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2956016465
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2344100780
Short name T77
Test name
Test status
Simulation time 104956651 ps
CPU time 0.98 seconds
Started Mar 21 01:31:20 PM PDT 24
Finished Mar 21 01:31:21 PM PDT 24
Peak memory 200844 kb
Host smart-e1d4c3b4-f5fe-4bde-a734-bf8e4607db9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344100780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2344100780
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.4088571738
Short name T512
Test name
Test status
Simulation time 195362518 ps
CPU time 1.38 seconds
Started Mar 21 01:31:18 PM PDT 24
Finished Mar 21 01:31:19 PM PDT 24
Peak memory 201060 kb
Host smart-281c9d0a-f7f8-4e8d-96e4-7fa5efb53fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088571738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4088571738
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.127726301
Short name T238
Test name
Test status
Simulation time 98606289 ps
CPU time 0.92 seconds
Started Mar 21 01:31:18 PM PDT 24
Finished Mar 21 01:31:19 PM PDT 24
Peak memory 200736 kb
Host smart-c80ab99b-cce0-4390-ad09-4599ee0920fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127726301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.127726301
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3421560145
Short name T226
Test name
Test status
Simulation time 119109580 ps
CPU time 1.61 seconds
Started Mar 21 01:31:23 PM PDT 24
Finished Mar 21 01:31:24 PM PDT 24
Peak memory 200896 kb
Host smart-bba3b760-5c31-48d0-9c0c-a13ded664831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421560145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3421560145
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2904308056
Short name T504
Test name
Test status
Simulation time 72582286 ps
CPU time 0.8 seconds
Started Mar 21 01:31:20 PM PDT 24
Finished Mar 21 01:31:21 PM PDT 24
Peak memory 200780 kb
Host smart-5700ea78-f702-4d6c-82ce-58b40917ccb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904308056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2904308056
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.502507306
Short name T374
Test name
Test status
Simulation time 72615701 ps
CPU time 0.79 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:30 PM PDT 24
Peak memory 200720 kb
Host smart-69d20f83-cc84-4fcd-9bc2-1846f686b76f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502507306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.502507306
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3231014142
Short name T501
Test name
Test status
Simulation time 1227375409 ps
CPU time 5.79 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:35 PM PDT 24
Peak memory 217980 kb
Host smart-e5d60343-fde4-49e3-a1cc-9644962862c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231014142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3231014142
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2295437256
Short name T281
Test name
Test status
Simulation time 244193929 ps
CPU time 1.07 seconds
Started Mar 21 01:31:28 PM PDT 24
Finished Mar 21 01:31:30 PM PDT 24
Peak memory 218264 kb
Host smart-77043ae9-d611-4255-9356-f41e16a388ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295437256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2295437256
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.165036887
Short name T250
Test name
Test status
Simulation time 85233959 ps
CPU time 0.78 seconds
Started Mar 21 01:31:19 PM PDT 24
Finished Mar 21 01:31:20 PM PDT 24
Peak memory 200736 kb
Host smart-89bb59c8-1bdb-4626-9f1f-0370be7a0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165036887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.165036887
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3428370269
Short name T35
Test name
Test status
Simulation time 768122330 ps
CPU time 3.74 seconds
Started Mar 21 01:31:24 PM PDT 24
Finished Mar 21 01:31:28 PM PDT 24
Peak memory 201056 kb
Host smart-aabba1ff-0395-42ba-bb7a-30d7dc30d661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428370269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3428370269
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1046591732
Short name T148
Test name
Test status
Simulation time 180401938 ps
CPU time 1.19 seconds
Started Mar 21 01:31:27 PM PDT 24
Finished Mar 21 01:31:28 PM PDT 24
Peak memory 200780 kb
Host smart-8b3e7c8a-8a11-4954-a3ce-99ee2ac0a796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046591732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1046591732
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3036639877
Short name T220
Test name
Test status
Simulation time 190148656 ps
CPU time 1.37 seconds
Started Mar 21 01:31:24 PM PDT 24
Finished Mar 21 01:31:26 PM PDT 24
Peak memory 201144 kb
Host smart-70304768-73e3-481b-a939-8c34fe4fb70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036639877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3036639877
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3687466908
Short name T406
Test name
Test status
Simulation time 2405422170 ps
CPU time 12.1 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:42 PM PDT 24
Peak memory 209296 kb
Host smart-a89e7860-2c30-4798-b5ba-a488b74f335d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687466908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3687466908
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3311475409
Short name T320
Test name
Test status
Simulation time 261362232 ps
CPU time 1.76 seconds
Started Mar 21 01:31:19 PM PDT 24
Finished Mar 21 01:31:21 PM PDT 24
Peak memory 200916 kb
Host smart-644d20f4-7c9d-4790-819f-06300573893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311475409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3311475409
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.339732357
Short name T210
Test name
Test status
Simulation time 157898263 ps
CPU time 1.04 seconds
Started Mar 21 01:31:25 PM PDT 24
Finished Mar 21 01:31:26 PM PDT 24
Peak memory 200924 kb
Host smart-0eecb6b0-a2a2-492c-9dc4-dfaa92368d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339732357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.339732357
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1786269215
Short name T360
Test name
Test status
Simulation time 73481215 ps
CPU time 0.82 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 200776 kb
Host smart-5d942f1a-6b8b-41ac-b250-782f73e972d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786269215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1786269215
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3457822124
Short name T464
Test name
Test status
Simulation time 1226792464 ps
CPU time 5.68 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:35 PM PDT 24
Peak memory 217912 kb
Host smart-472dad68-6486-473f-b7d3-157033695c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457822124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3457822124
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2143455426
Short name T283
Test name
Test status
Simulation time 244983340 ps
CPU time 1.07 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:30 PM PDT 24
Peak memory 218228 kb
Host smart-607a123d-c2a5-44fd-9c8a-321928292bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143455426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2143455426
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2213382582
Short name T293
Test name
Test status
Simulation time 108272858 ps
CPU time 0.77 seconds
Started Mar 21 01:31:28 PM PDT 24
Finished Mar 21 01:31:29 PM PDT 24
Peak memory 200648 kb
Host smart-5ea6eecb-51c6-4723-b5d5-efa0fdc1a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213382582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2213382582
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.4096669815
Short name T421
Test name
Test status
Simulation time 1534121430 ps
CPU time 5.96 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:36 PM PDT 24
Peak memory 201004 kb
Host smart-8518f7d2-3415-4175-b94b-39a3bdb7a579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096669815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4096669815
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4082011976
Short name T306
Test name
Test status
Simulation time 178784844 ps
CPU time 1.23 seconds
Started Mar 21 01:31:28 PM PDT 24
Finished Mar 21 01:31:30 PM PDT 24
Peak memory 200856 kb
Host smart-e0be48e7-cde0-4ec1-add6-3a1d39ce1b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082011976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.4082011976
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.4242106371
Short name T211
Test name
Test status
Simulation time 201698560 ps
CPU time 1.49 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 201036 kb
Host smart-1e575e80-23ff-4a2c-be6a-ad6b8a0df9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242106371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.4242106371
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3270110981
Short name T313
Test name
Test status
Simulation time 4831820369 ps
CPU time 18.15 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:47 PM PDT 24
Peak memory 209276 kb
Host smart-d6956c4d-716a-4267-824e-1dc258b9dde7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270110981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3270110981
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2835755055
Short name T253
Test name
Test status
Simulation time 433451590 ps
CPU time 2.42 seconds
Started Mar 21 01:31:28 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 209140 kb
Host smart-93ec1b2e-a771-4dfe-8c3d-47ac32c29fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835755055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2835755055
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2119613532
Short name T388
Test name
Test status
Simulation time 77783233 ps
CPU time 0.83 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:30 PM PDT 24
Peak memory 200852 kb
Host smart-d41208a0-44f3-4f8e-af65-4b70b49c667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119613532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2119613532
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.260735836
Short name T154
Test name
Test status
Simulation time 61944760 ps
CPU time 0.75 seconds
Started Mar 21 01:31:28 PM PDT 24
Finished Mar 21 01:31:29 PM PDT 24
Peak memory 200688 kb
Host smart-d8402508-2eae-48f1-9e28-8254329455cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260735836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.260735836
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.4119698641
Short name T45
Test name
Test status
Simulation time 1224621098 ps
CPU time 5.59 seconds
Started Mar 21 01:31:28 PM PDT 24
Finished Mar 21 01:31:34 PM PDT 24
Peak memory 217480 kb
Host smart-d40ecd0f-6fa8-4f2f-8ba4-bfd8557d5079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119698641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.4119698641
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3548688740
Short name T140
Test name
Test status
Simulation time 244692999 ps
CPU time 1.13 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:30 PM PDT 24
Peak memory 218164 kb
Host smart-0addfbd8-1bd9-41e5-bf16-2dda7edfc4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548688740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3548688740
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2169476209
Short name T73
Test name
Test status
Simulation time 168202017 ps
CPU time 0.84 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 200676 kb
Host smart-6f7064ac-a08b-4f88-8292-7d96580fcbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169476209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2169476209
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1570066533
Short name T419
Test name
Test status
Simulation time 1531705325 ps
CPU time 5.96 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:35 PM PDT 24
Peak memory 201052 kb
Host smart-eef631f8-5e0b-441d-ac48-bf2db5c6a3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570066533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1570066533
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3171970554
Short name T334
Test name
Test status
Simulation time 101538693 ps
CPU time 1.02 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 200880 kb
Host smart-ecd55b07-1950-48d2-b4ac-126306ca6d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171970554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3171970554
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4100841422
Short name T307
Test name
Test status
Simulation time 193284628 ps
CPU time 1.41 seconds
Started Mar 21 01:31:35 PM PDT 24
Finished Mar 21 01:31:36 PM PDT 24
Peak memory 201056 kb
Host smart-15d344eb-0100-49a8-aaf5-8883275bbab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100841422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4100841422
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.955978365
Short name T481
Test name
Test status
Simulation time 1341250115 ps
CPU time 6.8 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:37 PM PDT 24
Peak memory 209280 kb
Host smart-09835a92-2ae6-461e-a9d2-a3caaf3cceb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955978365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.955978365
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1329111517
Short name T191
Test name
Test status
Simulation time 514321349 ps
CPU time 2.77 seconds
Started Mar 21 01:31:27 PM PDT 24
Finished Mar 21 01:31:30 PM PDT 24
Peak memory 200908 kb
Host smart-df854969-cf34-4f53-a510-c97ec29f682e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329111517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1329111517
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1131017581
Short name T11
Test name
Test status
Simulation time 126830215 ps
CPU time 1.04 seconds
Started Mar 21 01:31:28 PM PDT 24
Finished Mar 21 01:31:29 PM PDT 24
Peak memory 200864 kb
Host smart-62fe8a63-1f65-4190-b292-d1ee68abaf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131017581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1131017581
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2616429681
Short name T490
Test name
Test status
Simulation time 65483843 ps
CPU time 0.8 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 200752 kb
Host smart-01ec00f3-f0d8-4ab7-9cf0-19971d84bf41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616429681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2616429681
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2178395386
Short name T454
Test name
Test status
Simulation time 1222049713 ps
CPU time 5.95 seconds
Started Mar 21 01:31:34 PM PDT 24
Finished Mar 21 01:31:40 PM PDT 24
Peak memory 218036 kb
Host smart-7da14daf-c3a0-4d6e-b709-62694e9ba9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178395386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2178395386
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.818091077
Short name T396
Test name
Test status
Simulation time 244702717 ps
CPU time 1.06 seconds
Started Mar 21 01:31:33 PM PDT 24
Finished Mar 21 01:31:34 PM PDT 24
Peak memory 218356 kb
Host smart-897d7972-3953-4e5e-a6af-5656d7de4988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818091077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.818091077
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.448277652
Short name T470
Test name
Test status
Simulation time 199989024 ps
CPU time 0.9 seconds
Started Mar 21 01:31:31 PM PDT 24
Finished Mar 21 01:31:32 PM PDT 24
Peak memory 200728 kb
Host smart-ab7a5023-b812-4cf4-a8bc-bb41c35da4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448277652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.448277652
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3979057601
Short name T71
Test name
Test status
Simulation time 1911789051 ps
CPU time 7.32 seconds
Started Mar 21 01:31:28 PM PDT 24
Finished Mar 21 01:31:36 PM PDT 24
Peak memory 201032 kb
Host smart-c141468a-7d27-4220-b242-6f0dcb7139ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979057601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3979057601
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.318504628
Short name T485
Test name
Test status
Simulation time 144023808 ps
CPU time 1.21 seconds
Started Mar 21 01:31:31 PM PDT 24
Finished Mar 21 01:31:32 PM PDT 24
Peak memory 200852 kb
Host smart-c41473f4-36e7-4482-a350-0f9d29139fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318504628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.318504628
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.909746713
Short name T473
Test name
Test status
Simulation time 242082665 ps
CPU time 1.57 seconds
Started Mar 21 01:31:32 PM PDT 24
Finished Mar 21 01:31:34 PM PDT 24
Peak memory 201064 kb
Host smart-e9c7bda7-c6a0-460d-96f1-e15076428942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909746713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.909746713
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.20726492
Short name T243
Test name
Test status
Simulation time 2973851696 ps
CPU time 12.3 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:41 PM PDT 24
Peak memory 201148 kb
Host smart-6fe2845f-45d3-422d-9b25-cb563d79e5e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20726492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.20726492
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3946880835
Short name T180
Test name
Test status
Simulation time 353112950 ps
CPU time 2.49 seconds
Started Mar 21 01:31:33 PM PDT 24
Finished Mar 21 01:31:35 PM PDT 24
Peak memory 200940 kb
Host smart-6a79e9d0-2d51-431e-933a-566b4f881a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946880835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3946880835
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1818892691
Short name T423
Test name
Test status
Simulation time 165026136 ps
CPU time 1.43 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 201020 kb
Host smart-013cea4d-df49-455f-9c4d-f8b2cb50ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818892691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1818892691
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.344633529
Short name T496
Test name
Test status
Simulation time 73450384 ps
CPU time 0.78 seconds
Started Mar 21 01:31:38 PM PDT 24
Finished Mar 21 01:31:39 PM PDT 24
Peak memory 200728 kb
Host smart-eb3c979c-d148-4a92-9f70-b3df662f7949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344633529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.344633529
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1454745758
Short name T462
Test name
Test status
Simulation time 2363006388 ps
CPU time 8.48 seconds
Started Mar 21 01:31:40 PM PDT 24
Finished Mar 21 01:31:48 PM PDT 24
Peak memory 218704 kb
Host smart-b8e683d4-44cf-4849-8925-59a0ca29044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454745758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1454745758
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1146965451
Short name T189
Test name
Test status
Simulation time 245360051 ps
CPU time 1.06 seconds
Started Mar 21 01:31:38 PM PDT 24
Finished Mar 21 01:31:39 PM PDT 24
Peak memory 217996 kb
Host smart-92148e23-8fff-4d6e-958b-61377dbe92e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146965451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1146965451
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.134956495
Short name T255
Test name
Test status
Simulation time 120234708 ps
CPU time 0.81 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 200796 kb
Host smart-2684183c-5ca1-47fc-97de-6e1ea4667e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134956495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.134956495
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.216314619
Short name T271
Test name
Test status
Simulation time 1150754489 ps
CPU time 5.01 seconds
Started Mar 21 01:31:31 PM PDT 24
Finished Mar 21 01:31:36 PM PDT 24
Peak memory 201060 kb
Host smart-d18df24a-a9e7-4405-9d36-e3ae6714fdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216314619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.216314619
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4185355107
Short name T417
Test name
Test status
Simulation time 114318705 ps
CPU time 1.02 seconds
Started Mar 21 01:31:37 PM PDT 24
Finished Mar 21 01:31:38 PM PDT 24
Peak memory 200864 kb
Host smart-b3722842-62f3-47de-afb1-8d7f943facbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185355107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4185355107
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4185518308
Short name T266
Test name
Test status
Simulation time 128374911 ps
CPU time 1.22 seconds
Started Mar 21 01:31:30 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 201048 kb
Host smart-4024ab72-7392-4f1b-b42b-a3be90b8acae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185518308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4185518308
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.864159295
Short name T96
Test name
Test status
Simulation time 5019649072 ps
CPU time 24.61 seconds
Started Mar 21 01:31:37 PM PDT 24
Finished Mar 21 01:32:01 PM PDT 24
Peak memory 201196 kb
Host smart-d206c607-57cf-473e-8229-4fea404319d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864159295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.864159295
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3257956363
Short name T298
Test name
Test status
Simulation time 134194168 ps
CPU time 1.62 seconds
Started Mar 21 01:31:29 PM PDT 24
Finished Mar 21 01:31:31 PM PDT 24
Peak memory 209088 kb
Host smart-1748c774-3d3e-433a-acfc-9a2e5235ccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257956363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3257956363
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1465615082
Short name T276
Test name
Test status
Simulation time 128872828 ps
CPU time 1.02 seconds
Started Mar 21 01:31:33 PM PDT 24
Finished Mar 21 01:31:34 PM PDT 24
Peak memory 200852 kb
Host smart-395dcdfe-c53c-4d57-987d-01530d8a4d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465615082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1465615082
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4289416363
Short name T528
Test name
Test status
Simulation time 79447910 ps
CPU time 0.81 seconds
Started Mar 21 01:31:40 PM PDT 24
Finished Mar 21 01:31:41 PM PDT 24
Peak memory 200720 kb
Host smart-8dffc7f0-d6b0-4d9d-9d52-c9d75c00bd51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289416363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4289416363
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2381742091
Short name T370
Test name
Test status
Simulation time 1892954698 ps
CPU time 7.84 seconds
Started Mar 21 01:31:38 PM PDT 24
Finished Mar 21 01:31:46 PM PDT 24
Peak memory 218528 kb
Host smart-da1cf0d8-e9c8-41bd-92ad-057a1edcfcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381742091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2381742091
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.829157564
Short name T50
Test name
Test status
Simulation time 243942603 ps
CPU time 1.09 seconds
Started Mar 21 01:31:35 PM PDT 24
Finished Mar 21 01:31:37 PM PDT 24
Peak memory 218156 kb
Host smart-85ba95dd-2160-4211-9dde-ff2d19403e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829157564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.829157564
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3989984378
Short name T19
Test name
Test status
Simulation time 192190394 ps
CPU time 0.85 seconds
Started Mar 21 01:31:35 PM PDT 24
Finished Mar 21 01:31:36 PM PDT 24
Peak memory 200648 kb
Host smart-e555898e-aba9-4c88-b9d0-bf9f54eb4bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989984378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3989984378
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4224230504
Short name T92
Test name
Test status
Simulation time 1200750116 ps
CPU time 5.21 seconds
Started Mar 21 01:31:37 PM PDT 24
Finished Mar 21 01:31:42 PM PDT 24
Peak memory 201032 kb
Host smart-8b8774a6-ae4a-494d-ade1-fbb7f74a62af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224230504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4224230504
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2474640450
Short name T455
Test name
Test status
Simulation time 164915624 ps
CPU time 1.22 seconds
Started Mar 21 01:31:39 PM PDT 24
Finished Mar 21 01:31:41 PM PDT 24
Peak memory 200856 kb
Host smart-e1a74fb0-8e43-4aa3-b10e-5b94c20ada3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474640450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2474640450
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1904328903
Short name T165
Test name
Test status
Simulation time 253065133 ps
CPU time 1.47 seconds
Started Mar 21 01:31:36 PM PDT 24
Finished Mar 21 01:31:38 PM PDT 24
Peak memory 200948 kb
Host smart-4f994952-7d55-4ab1-bbbc-e62f0f73f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904328903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1904328903
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4132830325
Short name T533
Test name
Test status
Simulation time 14785864543 ps
CPU time 46.94 seconds
Started Mar 21 01:31:38 PM PDT 24
Finished Mar 21 01:32:25 PM PDT 24
Peak memory 209344 kb
Host smart-15a1e6e1-db81-4b2d-987c-464f294660a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132830325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4132830325
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2462986482
Short name T178
Test name
Test status
Simulation time 327833116 ps
CPU time 2.1 seconds
Started Mar 21 01:31:35 PM PDT 24
Finished Mar 21 01:31:37 PM PDT 24
Peak memory 200908 kb
Host smart-ba4aa57a-f81d-45e4-bf0e-e2b6edbeb2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462986482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2462986482
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.4185291116
Short name T365
Test name
Test status
Simulation time 179439614 ps
CPU time 1.35 seconds
Started Mar 21 01:31:37 PM PDT 24
Finished Mar 21 01:31:38 PM PDT 24
Peak memory 201008 kb
Host smart-412c9824-dc05-4936-896f-3179a0a99785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185291116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4185291116
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3275737096
Short name T457
Test name
Test status
Simulation time 64204541 ps
CPU time 0.77 seconds
Started Mar 21 01:31:42 PM PDT 24
Finished Mar 21 01:31:43 PM PDT 24
Peak memory 200744 kb
Host smart-85d430c7-8059-441a-8339-45841da7bc2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275737096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3275737096
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2585622574
Short name T491
Test name
Test status
Simulation time 2182599922 ps
CPU time 7.59 seconds
Started Mar 21 01:31:35 PM PDT 24
Finished Mar 21 01:31:43 PM PDT 24
Peak memory 218676 kb
Host smart-23c89a63-a465-4d27-9206-193ae9561cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585622574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2585622574
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2145039387
Short name T436
Test name
Test status
Simulation time 244911691 ps
CPU time 1.08 seconds
Started Mar 21 01:31:36 PM PDT 24
Finished Mar 21 01:31:37 PM PDT 24
Peak memory 218252 kb
Host smart-84465e46-8590-438f-85d4-fca65e8ae92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145039387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2145039387
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.787513450
Short name T235
Test name
Test status
Simulation time 109246999 ps
CPU time 0.83 seconds
Started Mar 21 01:31:39 PM PDT 24
Finished Mar 21 01:31:40 PM PDT 24
Peak memory 200704 kb
Host smart-5bde81f4-bbd8-4ba4-af23-8803d7d42ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787513450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.787513450
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1015883131
Short name T123
Test name
Test status
Simulation time 1294453315 ps
CPU time 5.04 seconds
Started Mar 21 01:31:40 PM PDT 24
Finished Mar 21 01:31:45 PM PDT 24
Peak memory 201052 kb
Host smart-a4c2e2e5-dc71-44f2-b59a-fc4378141298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015883131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1015883131
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.222606586
Short name T160
Test name
Test status
Simulation time 103734373 ps
CPU time 1.02 seconds
Started Mar 21 01:31:40 PM PDT 24
Finished Mar 21 01:31:41 PM PDT 24
Peak memory 200876 kb
Host smart-d3c9fc30-58b0-4d4b-b204-24e9b1aa1639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222606586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.222606586
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3658439217
Short name T184
Test name
Test status
Simulation time 230940845 ps
CPU time 1.45 seconds
Started Mar 21 01:31:38 PM PDT 24
Finished Mar 21 01:31:40 PM PDT 24
Peak memory 201020 kb
Host smart-e7151113-388a-41b8-9d12-53bf21e6ab8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658439217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3658439217
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2162578179
Short name T102
Test name
Test status
Simulation time 1807327406 ps
CPU time 6.99 seconds
Started Mar 21 01:31:38 PM PDT 24
Finished Mar 21 01:31:45 PM PDT 24
Peak memory 201044 kb
Host smart-a374908e-bdd4-4063-96c0-b259454d5dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162578179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2162578179
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1531478586
Short name T130
Test name
Test status
Simulation time 448705581 ps
CPU time 2.42 seconds
Started Mar 21 01:31:36 PM PDT 24
Finished Mar 21 01:31:39 PM PDT 24
Peak memory 200928 kb
Host smart-1b03825f-826b-4752-a473-d473c245e76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531478586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1531478586
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2368744635
Short name T435
Test name
Test status
Simulation time 230082645 ps
CPU time 1.29 seconds
Started Mar 21 01:31:36 PM PDT 24
Finished Mar 21 01:31:37 PM PDT 24
Peak memory 200864 kb
Host smart-a4e8423c-fb6f-4b14-b1e2-134b5b695f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368744635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2368744635
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.4052863180
Short name T339
Test name
Test status
Simulation time 64608898 ps
CPU time 0.78 seconds
Started Mar 21 01:29:36 PM PDT 24
Finished Mar 21 01:29:38 PM PDT 24
Peak memory 200648 kb
Host smart-efac18a4-9aa3-47b8-bd32-c164cb5a7116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052863180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4052863180
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1608649841
Short name T440
Test name
Test status
Simulation time 1881847192 ps
CPU time 7.52 seconds
Started Mar 21 01:29:26 PM PDT 24
Finished Mar 21 01:29:34 PM PDT 24
Peak memory 222068 kb
Host smart-6dcbcf8a-b302-4ad5-9f47-fbd59bf2c62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608649841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1608649841
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.956915917
Short name T523
Test name
Test status
Simulation time 245027725 ps
CPU time 1.06 seconds
Started Mar 21 01:29:27 PM PDT 24
Finished Mar 21 01:29:28 PM PDT 24
Peak memory 218000 kb
Host smart-ec738030-ff77-4c80-829e-cd1639a46af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956915917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.956915917
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3187135844
Short name T289
Test name
Test status
Simulation time 88573872 ps
CPU time 0.75 seconds
Started Mar 21 01:29:27 PM PDT 24
Finished Mar 21 01:29:28 PM PDT 24
Peak memory 200724 kb
Host smart-ba270991-1751-4cc9-8424-518f6ac9ee19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187135844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3187135844
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.653506606
Short name T258
Test name
Test status
Simulation time 870920700 ps
CPU time 4.6 seconds
Started Mar 21 01:29:26 PM PDT 24
Finished Mar 21 01:29:31 PM PDT 24
Peak memory 200960 kb
Host smart-f09e0445-0a92-4cfd-9713-a5148bf145fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653506606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.653506606
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.89575520
Short name T420
Test name
Test status
Simulation time 106195050 ps
CPU time 1.05 seconds
Started Mar 21 01:29:27 PM PDT 24
Finished Mar 21 01:29:29 PM PDT 24
Peak memory 200868 kb
Host smart-65b19a91-013c-4135-bcc9-7db977052b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89575520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.89575520
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.165737037
Short name T415
Test name
Test status
Simulation time 125825409 ps
CPU time 1.35 seconds
Started Mar 21 01:29:28 PM PDT 24
Finished Mar 21 01:29:30 PM PDT 24
Peak memory 201060 kb
Host smart-fee1cc7a-2bdc-442d-98f4-d7c2dbdb5fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165737037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.165737037
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2034380626
Short name T340
Test name
Test status
Simulation time 999946826 ps
CPU time 4.21 seconds
Started Mar 21 01:29:35 PM PDT 24
Finished Mar 21 01:29:40 PM PDT 24
Peak memory 201088 kb
Host smart-f427d4cd-734e-49cc-ae12-d6a2923987aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034380626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2034380626
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.231101127
Short name T287
Test name
Test status
Simulation time 131406049 ps
CPU time 1.68 seconds
Started Mar 21 01:29:29 PM PDT 24
Finished Mar 21 01:29:30 PM PDT 24
Peak memory 200892 kb
Host smart-928fbf00-af74-4c0b-86c2-388a2f58560b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231101127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.231101127
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3443327459
Short name T282
Test name
Test status
Simulation time 69370328 ps
CPU time 0.8 seconds
Started Mar 21 01:29:27 PM PDT 24
Finished Mar 21 01:29:28 PM PDT 24
Peak memory 200856 kb
Host smart-5d38eb8e-fbc3-4f83-a3fb-475743a4685a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443327459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3443327459
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3660285715
Short name T203
Test name
Test status
Simulation time 78068447 ps
CPU time 0.82 seconds
Started Mar 21 01:29:34 PM PDT 24
Finished Mar 21 01:29:35 PM PDT 24
Peak memory 200652 kb
Host smart-aa6aaa06-1acc-42fe-956f-a47b9dfd5b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660285715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3660285715
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.13785419
Short name T319
Test name
Test status
Simulation time 1214961519 ps
CPU time 6.01 seconds
Started Mar 21 01:29:37 PM PDT 24
Finished Mar 21 01:29:43 PM PDT 24
Peak memory 217956 kb
Host smart-d8c82ce9-70a4-46cf-b912-e9ea0e217bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13785419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.13785419
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2251238121
Short name T280
Test name
Test status
Simulation time 244330607 ps
CPU time 1.05 seconds
Started Mar 21 01:29:35 PM PDT 24
Finished Mar 21 01:29:36 PM PDT 24
Peak memory 217932 kb
Host smart-a5b2e9ba-2892-452f-8228-4f0267281407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251238121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2251238121
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2960848044
Short name T468
Test name
Test status
Simulation time 170192152 ps
CPU time 0.85 seconds
Started Mar 21 01:29:35 PM PDT 24
Finished Mar 21 01:29:36 PM PDT 24
Peak memory 200720 kb
Host smart-b634db3e-dbe9-443c-94d0-45f2b81c1393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960848044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2960848044
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.728736100
Short name T458
Test name
Test status
Simulation time 1059699247 ps
CPU time 4.86 seconds
Started Mar 21 01:29:37 PM PDT 24
Finished Mar 21 01:29:42 PM PDT 24
Peak memory 200960 kb
Host smart-3ca1fe7b-c598-48cf-9c72-153c60b43259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728736100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.728736100
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2529373971
Short name T511
Test name
Test status
Simulation time 167816716 ps
CPU time 1.16 seconds
Started Mar 21 01:29:33 PM PDT 24
Finished Mar 21 01:29:34 PM PDT 24
Peak memory 200876 kb
Host smart-00b0b65f-4b1a-49af-99ae-7cedf984f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529373971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2529373971
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1748884667
Short name T274
Test name
Test status
Simulation time 207122739 ps
CPU time 1.38 seconds
Started Mar 21 01:29:33 PM PDT 24
Finished Mar 21 01:29:35 PM PDT 24
Peak memory 201052 kb
Host smart-c8f9a37b-dfb7-4fec-b71f-28c116d0e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748884667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1748884667
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2430456180
Short name T413
Test name
Test status
Simulation time 1128375841 ps
CPU time 5.4 seconds
Started Mar 21 01:29:35 PM PDT 24
Finished Mar 21 01:29:40 PM PDT 24
Peak memory 209080 kb
Host smart-d3c965c6-b555-45cc-b5e5-f0b95209a640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430456180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2430456180
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1222650885
Short name T181
Test name
Test status
Simulation time 79245912 ps
CPU time 0.83 seconds
Started Mar 21 01:29:35 PM PDT 24
Finished Mar 21 01:29:36 PM PDT 24
Peak memory 200772 kb
Host smart-68f48317-76d1-4950-9365-e9bebfad32e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222650885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1222650885
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2756272440
Short name T247
Test name
Test status
Simulation time 79408124 ps
CPU time 0.86 seconds
Started Mar 21 01:29:47 PM PDT 24
Finished Mar 21 01:29:48 PM PDT 24
Peak memory 200636 kb
Host smart-44ed0740-d845-4135-b05a-f42cb97a6e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756272440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2756272440
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2093288757
Short name T43
Test name
Test status
Simulation time 1228994268 ps
CPU time 6.3 seconds
Started Mar 21 01:29:47 PM PDT 24
Finished Mar 21 01:29:53 PM PDT 24
Peak memory 218480 kb
Host smart-661ee118-2f29-43dd-b126-3817ef75f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093288757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2093288757
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3435701382
Short name T477
Test name
Test status
Simulation time 245028549 ps
CPU time 1.15 seconds
Started Mar 21 01:29:49 PM PDT 24
Finished Mar 21 01:29:50 PM PDT 24
Peak memory 218144 kb
Host smart-366bf127-ae6c-4e7e-82d6-65bbf12fd489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435701382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3435701382
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.4169591068
Short name T21
Test name
Test status
Simulation time 182986343 ps
CPU time 0.95 seconds
Started Mar 21 01:29:35 PM PDT 24
Finished Mar 21 01:29:36 PM PDT 24
Peak memory 200652 kb
Host smart-914e44e3-74ad-486d-a446-c0ee964043b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169591068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.4169591068
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1848171391
Short name T72
Test name
Test status
Simulation time 928779340 ps
CPU time 4.58 seconds
Started Mar 21 01:29:46 PM PDT 24
Finished Mar 21 01:29:50 PM PDT 24
Peak memory 200956 kb
Host smart-2647a317-5fe3-4d7d-a40b-baeeddd509e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848171391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1848171391
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4032034320
Short name T12
Test name
Test status
Simulation time 106279015 ps
CPU time 1.05 seconds
Started Mar 21 01:29:47 PM PDT 24
Finished Mar 21 01:29:49 PM PDT 24
Peak memory 200796 kb
Host smart-2580ae77-3aa2-4c24-a040-db2919906c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032034320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4032034320
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3333237606
Short name T145
Test name
Test status
Simulation time 194484056 ps
CPU time 1.27 seconds
Started Mar 21 01:29:33 PM PDT 24
Finished Mar 21 01:29:34 PM PDT 24
Peak memory 201040 kb
Host smart-4e8566ed-bdf9-44d0-9f96-ae4e54c7459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333237606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3333237606
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3879843048
Short name T265
Test name
Test status
Simulation time 5211746870 ps
CPU time 23.79 seconds
Started Mar 21 01:29:46 PM PDT 24
Finished Mar 21 01:30:10 PM PDT 24
Peak memory 201204 kb
Host smart-8c98e43a-9f24-417a-9a30-c9c27f98c225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879843048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3879843048
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3052621499
Short name T80
Test name
Test status
Simulation time 283789049 ps
CPU time 1.98 seconds
Started Mar 21 01:29:47 PM PDT 24
Finished Mar 21 01:29:49 PM PDT 24
Peak memory 209164 kb
Host smart-936e136b-16af-46be-98aa-ccd7e7cdf237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052621499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3052621499
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1330510652
Short name T471
Test name
Test status
Simulation time 93613183 ps
CPU time 0.94 seconds
Started Mar 21 01:29:48 PM PDT 24
Finished Mar 21 01:29:49 PM PDT 24
Peak memory 200828 kb
Host smart-fe0f6f17-83eb-48d9-9e3e-3fe3207a9bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330510652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1330510652
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1953320245
Short name T353
Test name
Test status
Simulation time 71070580 ps
CPU time 0.78 seconds
Started Mar 21 01:29:55 PM PDT 24
Finished Mar 21 01:29:56 PM PDT 24
Peak memory 200728 kb
Host smart-1e5a227d-7245-46f5-93d9-b92bffa03989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953320245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1953320245
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.479652602
Short name T29
Test name
Test status
Simulation time 1224007282 ps
CPU time 6.15 seconds
Started Mar 21 01:29:48 PM PDT 24
Finished Mar 21 01:29:54 PM PDT 24
Peak memory 218556 kb
Host smart-11e069fc-5c62-4a7c-a033-e1c4cc7e573a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479652602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.479652602
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2383244164
Short name T239
Test name
Test status
Simulation time 246107483 ps
CPU time 1.04 seconds
Started Mar 21 01:29:54 PM PDT 24
Finished Mar 21 01:29:55 PM PDT 24
Peak memory 218128 kb
Host smart-f4960ead-ec90-4529-bc4c-41d9aec88157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383244164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2383244164
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3538771719
Short name T302
Test name
Test status
Simulation time 197988032 ps
CPU time 0.86 seconds
Started Mar 21 01:29:46 PM PDT 24
Finished Mar 21 01:29:48 PM PDT 24
Peak memory 200680 kb
Host smart-1727d91b-f2af-4a8a-96a6-23209939c834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538771719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3538771719
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2269611090
Short name T99
Test name
Test status
Simulation time 887362211 ps
CPU time 4.08 seconds
Started Mar 21 01:29:48 PM PDT 24
Finished Mar 21 01:29:52 PM PDT 24
Peak memory 201076 kb
Host smart-95b5ae16-7c12-4ea9-b364-99aa40b1f4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269611090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2269611090
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1648542201
Short name T260
Test name
Test status
Simulation time 98494887 ps
CPU time 1.03 seconds
Started Mar 21 01:29:46 PM PDT 24
Finished Mar 21 01:29:47 PM PDT 24
Peak memory 200780 kb
Host smart-a35657c0-1f61-464a-adec-75611ef2593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648542201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1648542201
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2660403050
Short name T515
Test name
Test status
Simulation time 118867288 ps
CPU time 1.21 seconds
Started Mar 21 01:29:47 PM PDT 24
Finished Mar 21 01:29:48 PM PDT 24
Peak memory 200924 kb
Host smart-160eafca-3eba-4bab-98b4-8b9d6f7f3a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660403050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2660403050
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.824148763
Short name T328
Test name
Test status
Simulation time 382191610 ps
CPU time 2.64 seconds
Started Mar 21 01:29:48 PM PDT 24
Finished Mar 21 01:29:50 PM PDT 24
Peak memory 200896 kb
Host smart-3b4cd3da-c2dc-475d-9f28-c471fb4e356f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824148763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.824148763
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3237433373
Short name T493
Test name
Test status
Simulation time 101328922 ps
CPU time 0.89 seconds
Started Mar 21 01:29:46 PM PDT 24
Finished Mar 21 01:29:47 PM PDT 24
Peak memory 200872 kb
Host smart-e61e74fa-b8fd-4f8d-bc76-c774c17acb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237433373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3237433373
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.698654098
Short name T520
Test name
Test status
Simulation time 82197079 ps
CPU time 0.82 seconds
Started Mar 21 01:29:56 PM PDT 24
Finished Mar 21 01:29:57 PM PDT 24
Peak memory 200648 kb
Host smart-4590de56-1b7a-4d96-a376-d1ff5b8f2fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698654098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.698654098
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1205760053
Short name T393
Test name
Test status
Simulation time 1892470498 ps
CPU time 7.39 seconds
Started Mar 21 01:29:57 PM PDT 24
Finished Mar 21 01:30:04 PM PDT 24
Peak memory 217936 kb
Host smart-a6eb2912-aeda-4b50-94a8-255685ec527c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205760053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1205760053
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2373097717
Short name T183
Test name
Test status
Simulation time 244704349 ps
CPU time 1.17 seconds
Started Mar 21 01:29:57 PM PDT 24
Finished Mar 21 01:29:58 PM PDT 24
Peak memory 218164 kb
Host smart-88e02a08-4d5f-4dca-808e-8f4daabf157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373097717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2373097717
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.1954331952
Short name T500
Test name
Test status
Simulation time 107541350 ps
CPU time 0.83 seconds
Started Mar 21 01:29:55 PM PDT 24
Finished Mar 21 01:29:56 PM PDT 24
Peak memory 200716 kb
Host smart-073d27db-3b13-48b4-953a-7dceda19cdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954331952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1954331952
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2651583110
Short name T447
Test name
Test status
Simulation time 753904902 ps
CPU time 3.83 seconds
Started Mar 21 01:29:55 PM PDT 24
Finished Mar 21 01:29:59 PM PDT 24
Peak memory 201052 kb
Host smart-e72cc35c-aea2-4212-9ced-20fb73eb674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651583110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2651583110
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3025042677
Short name T331
Test name
Test status
Simulation time 169241189 ps
CPU time 1.3 seconds
Started Mar 21 01:29:56 PM PDT 24
Finished Mar 21 01:29:57 PM PDT 24
Peak memory 200780 kb
Host smart-c15710b3-4a19-4095-aff5-de668cf7c698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025042677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3025042677
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2938035774
Short name T159
Test name
Test status
Simulation time 190482800 ps
CPU time 1.35 seconds
Started Mar 21 01:29:56 PM PDT 24
Finished Mar 21 01:29:57 PM PDT 24
Peak memory 200988 kb
Host smart-1462314e-b57f-4b14-8cd0-513f84e66ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938035774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2938035774
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.623243174
Short name T497
Test name
Test status
Simulation time 9906144149 ps
CPU time 34.23 seconds
Started Mar 21 01:29:54 PM PDT 24
Finished Mar 21 01:30:29 PM PDT 24
Peak memory 201156 kb
Host smart-0a3423be-d3ce-43c6-9353-3f738afb2c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623243174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.623243174
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3257407973
Short name T251
Test name
Test status
Simulation time 367615962 ps
CPU time 2.16 seconds
Started Mar 21 01:29:54 PM PDT 24
Finished Mar 21 01:29:56 PM PDT 24
Peak memory 200912 kb
Host smart-f6afc9ce-58f7-4a6a-849e-6a29d3a75338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257407973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3257407973
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1728581103
Short name T532
Test name
Test status
Simulation time 79415312 ps
CPU time 0.82 seconds
Started Mar 21 01:29:55 PM PDT 24
Finished Mar 21 01:29:56 PM PDT 24
Peak memory 200820 kb
Host smart-a5507421-7fc2-4e98-a46c-5e5e63cf61f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728581103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1728581103
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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