Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8789

1

T2

22

T6

18

T14

35

auto[1]

11769

1

T2

22

T5

4

T6

83

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6263	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6959	1			T1	1		T2	16		T3	1
reset_info_cp[2]	3178	1			T2	8		T5	1		T6	17
reset_info_cp[4]	4219	1			T2	9		T5	1		T6	16
reset_info_cp[8]	109	1			T48	2		T98	2		T89	3
reset_info_cp[16]	114	1			T14	1		T23	1		T24	1
reset_info_cp[32]	115	1			T6	1		T41	1		T43	1
reset_info_cp[64]	106	1			T6	1		T24	2		T45	1
reset_info_cp[128]	115	1			T14	1		T41	1		T48	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3319	1			T2	8		T6	18		T14	8
reset_info_cp[1]	auto[1]	3020	1			T2	7		T5	1		T6	8
reset_info_cp[2]	auto[0]	1019	1			T2	3		T14	3		T41	12
reset_info_cp[2]	auto[1]	2159	1			T2	5		T5	1		T6	17
reset_info_cp[4]	auto[0]	1533	1			T2	4		T14	12		T41	23
reset_info_cp[4]	auto[1]	2686	1			T2	5		T5	1		T6	16
reset_info_cp[8]	auto[0]	45	1			T48	1		T98	2		T89	3
reset_info_cp[8]	auto[1]	64	1			T48	1		T26	1		T90	2
reset_info_cp[16]	auto[0]	44	1			T14	1		T45	1		T48	1
reset_info_cp[16]	auto[1]	70	1			T23	1		T24	1		T45	1
reset_info_cp[32]	auto[0]	42	1			T86	1		T131	1		T128	2
reset_info_cp[32]	auto[1]	73	1			T6	1		T41	1		T43	1
reset_info_cp[64]	auto[0]	49	1			T45	1		T48	1		T86	2
reset_info_cp[64]	auto[1]	57	1			T6	1		T24	2		T26	2
reset_info_cp[128]	auto[0]	39	1			T14	1		T41	1		T48	1
reset_info_cp[128]	auto[1]	76	1			T48	1		T86	1		T98	1