Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/36.rstmgr_reset.3672457849 Mar 24 12:44:05 PM PDT 24 Mar 24 12:44:10 PM PDT 24 871463954 ps
T537 /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.778127648 Mar 24 12:44:16 PM PDT 24 Mar 24 12:44:17 PM PDT 24 140035868 ps
T538 /workspace/coverage/default/27.rstmgr_alert_test.3129216986 Mar 24 12:44:03 PM PDT 24 Mar 24 12:44:04 PM PDT 24 61452317 ps
T539 /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.21218768 Mar 24 12:44:11 PM PDT 24 Mar 24 12:44:12 PM PDT 24 131731549 ps
T540 /workspace/coverage/default/0.rstmgr_alert_test.452235947 Mar 24 12:43:18 PM PDT 24 Mar 24 12:43:18 PM PDT 24 90242699 ps
T62 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1507508034 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:01 PM PDT 24 105115688 ps
T65 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1176048337 Mar 24 12:34:32 PM PDT 24 Mar 24 12:34:35 PM PDT 24 533743902 ps
T63 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.21514396 Mar 24 12:34:39 PM PDT 24 Mar 24 12:34:41 PM PDT 24 194897700 ps
T64 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.960915669 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:59 PM PDT 24 253692571 ps
T105 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1404251550 Mar 24 12:34:46 PM PDT 24 Mar 24 12:34:47 PM PDT 24 76824005 ps
T106 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2883140189 Mar 24 12:34:33 PM PDT 24 Mar 24 12:34:35 PM PDT 24 279200617 ps
T107 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2064162087 Mar 24 12:34:22 PM PDT 24 Mar 24 12:34:23 PM PDT 24 136274052 ps
T66 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.629965026 Mar 24 12:34:38 PM PDT 24 Mar 24 12:34:39 PM PDT 24 97541189 ps
T108 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2816806709 Mar 24 12:34:30 PM PDT 24 Mar 24 12:34:32 PM PDT 24 223787804 ps
T109 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4234626162 Mar 24 12:34:43 PM PDT 24 Mar 24 12:34:44 PM PDT 24 67156237 ps
T67 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.393682449 Mar 24 12:34:35 PM PDT 24 Mar 24 12:34:36 PM PDT 24 194911497 ps
T70 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2161483701 Mar 24 12:34:29 PM PDT 24 Mar 24 12:34:30 PM PDT 24 140859285 ps
T110 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4091889662 Mar 24 12:34:28 PM PDT 24 Mar 24 12:34:29 PM PDT 24 80696909 ps
T68 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2675026624 Mar 24 12:34:36 PM PDT 24 Mar 24 12:34:37 PM PDT 24 117366390 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3643927055 Mar 24 12:35:57 PM PDT 24 Mar 24 12:35:58 PM PDT 24 133236947 ps
T111 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1119730039 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:51 PM PDT 24 234903233 ps
T542 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1413248067 Mar 24 12:34:45 PM PDT 24 Mar 24 12:34:48 PM PDT 24 221666171 ps
T69 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1988677244 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:55 PM PDT 24 274359300 ps
T543 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3868285906 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:04 PM PDT 24 114331712 ps
T544 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.65630605 Mar 24 12:34:46 PM PDT 24 Mar 24 12:34:47 PM PDT 24 129155151 ps
T92 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1985545151 Mar 24 12:34:36 PM PDT 24 Mar 24 12:34:38 PM PDT 24 163484120 ps
T96 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4189822598 Mar 24 12:34:35 PM PDT 24 Mar 24 12:34:38 PM PDT 24 943797472 ps
T93 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.557233881 Mar 24 12:34:45 PM PDT 24 Mar 24 12:34:47 PM PDT 24 283191759 ps
T545 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.118488244 Mar 24 12:34:41 PM PDT 24 Mar 24 12:34:42 PM PDT 24 129149703 ps
T546 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.174265588 Mar 24 12:34:39 PM PDT 24 Mar 24 12:34:40 PM PDT 24 57370491 ps
T97 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1904853625 Mar 24 12:34:27 PM PDT 24 Mar 24 12:34:31 PM PDT 24 781743402 ps
T94 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3701993544 Mar 24 12:34:55 PM PDT 24 Mar 24 12:34:57 PM PDT 24 122949101 ps
T95 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2285799522 Mar 24 12:34:31 PM PDT 24 Mar 24 12:34:34 PM PDT 24 242865062 ps
T112 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1218318734 Mar 24 12:34:36 PM PDT 24 Mar 24 12:34:40 PM PDT 24 499737571 ps
T547 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.309957425 Mar 24 12:34:25 PM PDT 24 Mar 24 12:34:28 PM PDT 24 141524032 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3914506761 Mar 24 12:34:50 PM PDT 24 Mar 24 12:34:54 PM PDT 24 796670645 ps
T120 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2320461346 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:51 PM PDT 24 466362765 ps
T549 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.426091521 Mar 24 12:35:57 PM PDT 24 Mar 24 12:35:59 PM PDT 24 129991057 ps
T550 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1903200363 Mar 24 12:34:40 PM PDT 24 Mar 24 12:34:41 PM PDT 24 76280675 ps
T551 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.990434547 Mar 24 12:34:38 PM PDT 24 Mar 24 12:34:40 PM PDT 24 228278374 ps
T113 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1185759952 Mar 24 12:34:40 PM PDT 24 Mar 24 12:34:43 PM PDT 24 894706123 ps
T552 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3308613225 Mar 24 12:36:01 PM PDT 24 Mar 24 12:36:03 PM PDT 24 174458755 ps
T132 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.900904339 Mar 24 12:34:36 PM PDT 24 Mar 24 12:34:39 PM PDT 24 913630552 ps
T553 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3434822663 Mar 24 12:34:55 PM PDT 24 Mar 24 12:34:58 PM PDT 24 188827939 ps
T554 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3743094929 Mar 24 12:34:33 PM PDT 24 Mar 24 12:34:35 PM PDT 24 185866001 ps
T555 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1178664601 Mar 24 12:34:39 PM PDT 24 Mar 24 12:34:40 PM PDT 24 237334104 ps
T556 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2450911772 Mar 24 12:34:34 PM PDT 24 Mar 24 12:34:37 PM PDT 24 266900779 ps
T557 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1831239137 Mar 24 12:34:14 PM PDT 24 Mar 24 12:34:17 PM PDT 24 465917669 ps
T558 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1934723 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:03 PM PDT 24 296954054 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1618345182 Mar 24 12:34:21 PM PDT 24 Mar 24 12:34:23 PM PDT 24 119941459 ps
T560 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2000836750 Mar 24 12:34:39 PM PDT 24 Mar 24 12:34:42 PM PDT 24 188236392 ps
T561 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1215219134 Mar 24 12:34:46 PM PDT 24 Mar 24 12:34:48 PM PDT 24 220691035 ps
T562 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3667286104 Mar 24 12:35:56 PM PDT 24 Mar 24 12:35:57 PM PDT 24 63531745 ps
T563 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1774602606 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:07 PM PDT 24 129692371 ps
T564 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4011078879 Mar 24 12:34:28 PM PDT 24 Mar 24 12:34:30 PM PDT 24 249989585 ps
T565 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2672887907 Mar 24 12:34:28 PM PDT 24 Mar 24 12:34:34 PM PDT 24 478488711 ps
T566 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4163507634 Mar 24 12:36:05 PM PDT 24 Mar 24 12:36:06 PM PDT 24 85865995 ps
T134 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4128156033 Mar 24 12:34:28 PM PDT 24 Mar 24 12:34:32 PM PDT 24 911913961 ps
T567 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2811245367 Mar 24 12:34:43 PM PDT 24 Mar 24 12:34:46 PM PDT 24 405278129 ps
T568 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.985258649 Mar 24 12:34:30 PM PDT 24 Mar 24 12:34:36 PM PDT 24 482116186 ps
T569 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1890251058 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:45 PM PDT 24 67397932 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1270012167 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:54 PM PDT 24 73531956 ps
T571 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2145359581 Mar 24 12:35:27 PM PDT 24 Mar 24 12:35:41 PM PDT 24 1537330324 ps
T572 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3102104414 Mar 24 12:34:30 PM PDT 24 Mar 24 12:34:32 PM PDT 24 280373620 ps
T573 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1837796567 Mar 24 12:34:36 PM PDT 24 Mar 24 12:34:37 PM PDT 24 130160911 ps
T574 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3910521551 Mar 24 12:34:52 PM PDT 24 Mar 24 12:34:54 PM PDT 24 300983075 ps
T575 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1543012230 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:09 PM PDT 24 432793066 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3601343416 Mar 24 12:34:30 PM PDT 24 Mar 24 12:34:33 PM PDT 24 356159594 ps
T577 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.26002455 Mar 24 12:34:22 PM PDT 24 Mar 24 12:34:23 PM PDT 24 151070161 ps
T578 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2279606924 Mar 24 12:35:57 PM PDT 24 Mar 24 12:36:00 PM PDT 24 531041221 ps
T579 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1654237129 Mar 24 12:34:37 PM PDT 24 Mar 24 12:34:39 PM PDT 24 112234432 ps
T133 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.825156091 Mar 24 12:34:40 PM PDT 24 Mar 24 12:34:42 PM PDT 24 555332834 ps
T135 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3783195573 Mar 24 12:35:08 PM PDT 24 Mar 24 12:35:12 PM PDT 24 781206464 ps
T580 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.242733675 Mar 24 12:35:56 PM PDT 24 Mar 24 12:35:57 PM PDT 24 126651076 ps
T581 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1117913281 Mar 24 12:36:01 PM PDT 24 Mar 24 12:36:02 PM PDT 24 64581332 ps
T118 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3556096187 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:16 PM PDT 24 1993384681 ps
T117 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1662234142 Mar 24 12:34:37 PM PDT 24 Mar 24 12:34:41 PM PDT 24 781329854 ps
T582 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2755168029 Mar 24 12:34:39 PM PDT 24 Mar 24 12:34:40 PM PDT 24 54151657 ps
T583 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2896414976 Mar 24 12:34:59 PM PDT 24 Mar 24 12:35:02 PM PDT 24 155773611 ps
T584 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2770725424 Mar 24 12:34:37 PM PDT 24 Mar 24 12:34:40 PM PDT 24 113231242 ps
T585 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2986352604 Mar 24 12:34:44 PM PDT 24 Mar 24 12:34:45 PM PDT 24 60068534 ps
T586 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1415434391 Mar 24 12:34:25 PM PDT 24 Mar 24 12:34:28 PM PDT 24 127109813 ps
T587 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3401530479 Mar 24 12:34:37 PM PDT 24 Mar 24 12:34:40 PM PDT 24 424989563 ps
T588 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3345420368 Mar 24 12:34:40 PM PDT 24 Mar 24 12:34:42 PM PDT 24 237276112 ps
T589 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2292573485 Mar 24 12:34:49 PM PDT 24 Mar 24 12:34:50 PM PDT 24 128153803 ps
T590 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2143511897 Mar 24 12:34:36 PM PDT 24 Mar 24 12:34:38 PM PDT 24 120741831 ps
T591 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2188544912 Mar 24 12:34:36 PM PDT 24 Mar 24 12:34:39 PM PDT 24 81244044 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1347844683 Mar 24 12:34:24 PM PDT 24 Mar 24 12:34:26 PM PDT 24 501577897 ps
T593 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3686778864 Mar 24 12:34:39 PM PDT 24 Mar 24 12:34:40 PM PDT 24 138445720 ps
T594 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2564226067 Mar 24 12:34:23 PM PDT 24 Mar 24 12:34:25 PM PDT 24 117738701 ps
T595 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3123885799 Mar 24 12:34:14 PM PDT 24 Mar 24 12:34:15 PM PDT 24 62236341 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4158910302 Mar 24 12:34:35 PM PDT 24 Mar 24 12:34:37 PM PDT 24 213781428 ps
T597 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.739036475 Mar 24 12:34:55 PM PDT 24 Mar 24 12:34:58 PM PDT 24 274568536 ps
T598 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1318366615 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:54 PM PDT 24 191149475 ps
T599 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3034448973 Mar 24 12:34:42 PM PDT 24 Mar 24 12:34:43 PM PDT 24 130233442 ps
T600 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1060566456 Mar 24 12:34:45 PM PDT 24 Mar 24 12:34:47 PM PDT 24 84540545 ps
T601 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3626491121 Mar 24 12:34:35 PM PDT 24 Mar 24 12:34:38 PM PDT 24 413366645 ps
T602 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1957921693 Mar 24 12:34:58 PM PDT 24 Mar 24 12:35:01 PM PDT 24 264035699 ps
T115 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2731170383 Mar 24 12:34:42 PM PDT 24 Mar 24 12:34:51 PM PDT 24 894998889 ps
T603 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2696884636 Mar 24 12:35:56 PM PDT 24 Mar 24 12:35:58 PM PDT 24 97244798 ps
T604 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1137820823 Mar 24 12:34:26 PM PDT 24 Mar 24 12:34:29 PM PDT 24 230281273 ps
T605 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3663068113 Mar 24 12:34:42 PM PDT 24 Mar 24 12:34:44 PM PDT 24 561115560 ps
T606 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1759611154 Mar 24 12:34:27 PM PDT 24 Mar 24 12:34:36 PM PDT 24 1530295453 ps
T114 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2480401044 Mar 24 12:34:33 PM PDT 24 Mar 24 12:34:37 PM PDT 24 944455484 ps
T119 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2556032711 Mar 24 12:34:39 PM PDT 24 Mar 24 12:34:41 PM PDT 24 414409539 ps
T607 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.426246936 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:06 PM PDT 24 75916181 ps
T608 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2473313612 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:11 PM PDT 24 178904101 ps
T609 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3974546944 Mar 24 12:34:42 PM PDT 24 Mar 24 12:34:44 PM PDT 24 223161410 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2494583890 Mar 24 12:34:47 PM PDT 24 Mar 24 12:34:49 PM PDT 24 134112829 ps
T611 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3398689029 Mar 24 12:34:45 PM PDT 24 Mar 24 12:34:46 PM PDT 24 176651968 ps
T612 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3615061193 Mar 24 12:34:28 PM PDT 24 Mar 24 12:34:30 PM PDT 24 511495233 ps
T613 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1770166194 Mar 24 12:34:45 PM PDT 24 Mar 24 12:34:45 PM PDT 24 58618979 ps
T116 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1723625517 Mar 24 12:34:35 PM PDT 24 Mar 24 12:34:39 PM PDT 24 997504864 ps
T614 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3638412125 Mar 24 12:34:37 PM PDT 24 Mar 24 12:34:39 PM PDT 24 136409706 ps
T615 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3484969011 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:05 PM PDT 24 842462346 ps
T616 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3172044435 Mar 24 12:34:56 PM PDT 24 Mar 24 12:35:01 PM PDT 24 601832340 ps
T617 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2456164401 Mar 24 12:34:34 PM PDT 24 Mar 24 12:34:41 PM PDT 24 139690843 ps
T618 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3609909608 Mar 24 12:34:29 PM PDT 24 Mar 24 12:34:30 PM PDT 24 85524166 ps
T619 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3533045429 Mar 24 12:36:05 PM PDT 24 Mar 24 12:36:07 PM PDT 24 94665283 ps
T620 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3903074196 Mar 24 12:34:35 PM PDT 24 Mar 24 12:34:37 PM PDT 24 66397020 ps

Test location /workspace/coverage/default/4.rstmgr_smoke.603767092
Short name T5
Test name
Test status
Simulation time 121868060 ps
CPU time 1.18 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 201004 kb
Host smart-0fa846a3-1907-4600-be69-c69cfc23c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603767092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.603767092
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3815841731
Short name T48
Test name
Test status
Simulation time 4487104605 ps
CPU time 19.61 seconds
Started Mar 24 12:43:44 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 201132 kb
Host smart-9a8d736c-7cb0-4c21-939f-45f44b606c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815841731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3815841731
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1985545151
Short name T92
Test name
Test status
Simulation time 163484120 ps
CPU time 1.45 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:38 PM PDT 24
Peak memory 212760 kb
Host smart-001d363d-407c-43f5-8493-d43c2ea55068
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985545151 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1985545151
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.423389401
Short name T126
Test name
Test status
Simulation time 436705933 ps
CPU time 2.32 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 209400 kb
Host smart-237b6a26-f457-43bb-a26c-a7de12226a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423389401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.423389401
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.727783616
Short name T24
Test name
Test status
Simulation time 1234119773 ps
CPU time 5.66 seconds
Started Mar 24 12:44:01 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 218556 kb
Host smart-aed13fa5-fbf0-4951-b23d-ea291dd893cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727783616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.727783616
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.135869834
Short name T74
Test name
Test status
Simulation time 8353590304 ps
CPU time 13.06 seconds
Started Mar 24 12:43:23 PM PDT 24
Finished Mar 24 12:43:37 PM PDT 24
Peak memory 218288 kb
Host smart-cdae63c4-9210-47db-aeb1-9254d0ce9f97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135869834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.135869834
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2445309819
Short name T44
Test name
Test status
Simulation time 85398897 ps
CPU time 0.84 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:51 PM PDT 24
Peak memory 200788 kb
Host smart-506ab9f5-d744-4358-8e00-f46d21171b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445309819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2445309819
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1904853625
Short name T97
Test name
Test status
Simulation time 781743402 ps
CPU time 2.91 seconds
Started Mar 24 12:34:27 PM PDT 24
Finished Mar 24 12:34:31 PM PDT 24
Peak memory 200496 kb
Host smart-caa5d7e0-ea09-4da4-a0a7-a5de2bd5a0a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904853625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1904853625
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1507508034
Short name T62
Test name
Test status
Simulation time 105115688 ps
CPU time 1.37 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 200500 kb
Host smart-7810c693-bf48-4ac5-88f4-b41ae256e076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507508034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1507508034
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2292289773
Short name T7
Test name
Test status
Simulation time 175624960 ps
CPU time 1.17 seconds
Started Mar 24 12:43:42 PM PDT 24
Finished Mar 24 12:43:43 PM PDT 24
Peak memory 200828 kb
Host smart-904190be-57d4-4603-b020-4a9e7982203e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292289773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2292289773
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3325461397
Short name T121
Test name
Test status
Simulation time 13836891833 ps
CPU time 45.33 seconds
Started Mar 24 12:43:36 PM PDT 24
Finished Mar 24 12:44:21 PM PDT 24
Peak memory 209340 kb
Host smart-1661f120-e098-48f9-bc65-839251287fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325461397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3325461397
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3739584894
Short name T27
Test name
Test status
Simulation time 2170141437 ps
CPU time 7.94 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 218228 kb
Host smart-7d3bd426-96e4-4c06-bd3a-8af4a2aef3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739584894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3739584894
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2450911772
Short name T556
Test name
Test status
Simulation time 266900779 ps
CPU time 1.97 seconds
Started Mar 24 12:34:34 PM PDT 24
Finished Mar 24 12:34:37 PM PDT 24
Peak memory 208628 kb
Host smart-3cfe4c14-e766-4ecc-8707-012da7b8b866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450911772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2450911772
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1185759952
Short name T113
Test name
Test status
Simulation time 894706123 ps
CPU time 3.04 seconds
Started Mar 24 12:34:40 PM PDT 24
Finished Mar 24 12:34:43 PM PDT 24
Peak memory 200508 kb
Host smart-4da9a733-9a15-4c42-bcbd-4af9f369154b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185759952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1185759952
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2598309599
Short name T128
Test name
Test status
Simulation time 254107732 ps
CPU time 1.51 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:35 PM PDT 24
Peak memory 200824 kb
Host smart-73cd53fb-e550-4352-a3d4-28e3d15c991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598309599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2598309599
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.783139352
Short name T37
Test name
Test status
Simulation time 1225573106 ps
CPU time 5.32 seconds
Started Mar 24 12:44:04 PM PDT 24
Finished Mar 24 12:44:09 PM PDT 24
Peak memory 218592 kb
Host smart-77084e82-396b-429b-8e0c-595d724c8c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783139352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.783139352
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2948729831
Short name T19
Test name
Test status
Simulation time 178576013 ps
CPU time 0.87 seconds
Started Mar 24 12:43:36 PM PDT 24
Finished Mar 24 12:43:37 PM PDT 24
Peak memory 200684 kb
Host smart-c00049bb-67f5-44c9-9311-e8bb48bcf06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948729831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2948729831
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.4244268569
Short name T10
Test name
Test status
Simulation time 244443485 ps
CPU time 1.13 seconds
Started Mar 24 12:44:08 PM PDT 24
Finished Mar 24 12:44:09 PM PDT 24
Peak memory 218176 kb
Host smart-3b7fcff5-c1b5-446f-82c5-d51b0198cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244268569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.4244268569
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3556096187
Short name T118
Test name
Test status
Simulation time 1993384681 ps
CPU time 4.97 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 200576 kb
Host smart-baa3aee6-536a-4133-8573-21c1d034081a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556096187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3556096187
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2731170383
Short name T115
Test name
Test status
Simulation time 894998889 ps
CPU time 3.1 seconds
Started Mar 24 12:34:42 PM PDT 24
Finished Mar 24 12:34:51 PM PDT 24
Peak memory 200528 kb
Host smart-60ad6af8-cf10-4400-85ba-260e3ba8bf66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731170383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2731170383
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2811245367
Short name T567
Test name
Test status
Simulation time 405278129 ps
CPU time 2.69 seconds
Started Mar 24 12:34:43 PM PDT 24
Finished Mar 24 12:34:46 PM PDT 24
Peak memory 200416 kb
Host smart-93f6fba7-9454-487e-8256-59ec37789636
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811245367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
811245367
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2145359581
Short name T571
Test name
Test status
Simulation time 1537330324 ps
CPU time 7.58 seconds
Started Mar 24 12:35:27 PM PDT 24
Finished Mar 24 12:35:41 PM PDT 24
Peak memory 199556 kb
Host smart-6f8c0843-2748-425a-9441-dc2285894b21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145359581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
145359581
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3643927055
Short name T541
Test name
Test status
Simulation time 133236947 ps
CPU time 0.94 seconds
Started Mar 24 12:35:57 PM PDT 24
Finished Mar 24 12:35:58 PM PDT 24
Peak memory 200248 kb
Host smart-05d1dbee-1bce-45b9-afbf-85d6ba6cd62b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643927055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
643927055
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.242733675
Short name T580
Test name
Test status
Simulation time 126651076 ps
CPU time 0.94 seconds
Started Mar 24 12:35:56 PM PDT 24
Finished Mar 24 12:35:57 PM PDT 24
Peak memory 200188 kb
Host smart-740b1cee-f217-4770-85c9-b6c185d7baca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242733675 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.242733675
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.4163507634
Short name T566
Test name
Test status
Simulation time 85865995 ps
CPU time 0.88 seconds
Started Mar 24 12:36:05 PM PDT 24
Finished Mar 24 12:36:06 PM PDT 24
Peak memory 200200 kb
Host smart-5a1add10-d437-4564-af05-7d8ec35d6bfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163507634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.4163507634
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1618345182
Short name T559
Test name
Test status
Simulation time 119941459 ps
CPU time 1.63 seconds
Started Mar 24 12:34:21 PM PDT 24
Finished Mar 24 12:34:23 PM PDT 24
Peak memory 208740 kb
Host smart-bf430649-a9c1-4fd6-a047-6774e9b30661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618345182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1618345182
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3626491121
Short name T601
Test name
Test status
Simulation time 413366645 ps
CPU time 1.77 seconds
Started Mar 24 12:34:35 PM PDT 24
Finished Mar 24 12:34:38 PM PDT 24
Peak memory 200516 kb
Host smart-d1a42064-7741-45b0-89ca-c6208fe41317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626491121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3626491121
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3601343416
Short name T576
Test name
Test status
Simulation time 356159594 ps
CPU time 2.52 seconds
Started Mar 24 12:34:30 PM PDT 24
Finished Mar 24 12:34:33 PM PDT 24
Peak memory 200440 kb
Host smart-49fed49d-0e62-429b-b7e0-8a3ef330017c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601343416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
601343416
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1759611154
Short name T606
Test name
Test status
Simulation time 1530295453 ps
CPU time 8.31 seconds
Started Mar 24 12:34:27 PM PDT 24
Finished Mar 24 12:34:36 PM PDT 24
Peak memory 200440 kb
Host smart-3e6562c8-a0eb-4579-9007-edf2ab97b1d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759611154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
759611154
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.65630605
Short name T544
Test name
Test status
Simulation time 129155151 ps
CPU time 0.88 seconds
Started Mar 24 12:34:46 PM PDT 24
Finished Mar 24 12:34:47 PM PDT 24
Peak memory 200244 kb
Host smart-160842a6-635e-4979-b4e8-877fcc554fb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65630605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.65630605
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3308613225
Short name T552
Test name
Test status
Simulation time 174458755 ps
CPU time 1.11 seconds
Started Mar 24 12:36:01 PM PDT 24
Finished Mar 24 12:36:03 PM PDT 24
Peak memory 200376 kb
Host smart-d64b5667-3a91-4083-b60d-c3463e3ffc64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308613225 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3308613225
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1117913281
Short name T581
Test name
Test status
Simulation time 64581332 ps
CPU time 0.75 seconds
Started Mar 24 12:36:01 PM PDT 24
Finished Mar 24 12:36:02 PM PDT 24
Peak memory 200264 kb
Host smart-88a850e1-0512-4383-9584-6d60098b778a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117913281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1117913281
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2064162087
Short name T107
Test name
Test status
Simulation time 136274052 ps
CPU time 1.06 seconds
Started Mar 24 12:34:22 PM PDT 24
Finished Mar 24 12:34:23 PM PDT 24
Peak memory 200312 kb
Host smart-2971fde9-ebd1-4d42-8823-a8580bcc197b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064162087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2064162087
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4011078879
Short name T564
Test name
Test status
Simulation time 249989585 ps
CPU time 1.83 seconds
Started Mar 24 12:34:28 PM PDT 24
Finished Mar 24 12:34:30 PM PDT 24
Peak memory 208616 kb
Host smart-2085f21a-961a-465e-8924-8af86490a3ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011078879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.4011078879
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.825156091
Short name T133
Test name
Test status
Simulation time 555332834 ps
CPU time 2 seconds
Started Mar 24 12:34:40 PM PDT 24
Finished Mar 24 12:34:42 PM PDT 24
Peak memory 200556 kb
Host smart-e8549b55-94b1-4fc9-a795-998daf012d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825156091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
825156091
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2473313612
Short name T608
Test name
Test status
Simulation time 178904101 ps
CPU time 1.77 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:11 PM PDT 24
Peak memory 208740 kb
Host smart-0b42401e-334f-4feb-9a30-34ff8bac45ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473313612 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2473313612
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1903200363
Short name T550
Test name
Test status
Simulation time 76280675 ps
CPU time 0.8 seconds
Started Mar 24 12:34:40 PM PDT 24
Finished Mar 24 12:34:41 PM PDT 24
Peak memory 200268 kb
Host smart-0781221e-53d6-42f7-8245-965349fd569c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903200363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1903200363
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3434822663
Short name T553
Test name
Test status
Simulation time 188827939 ps
CPU time 1.42 seconds
Started Mar 24 12:34:55 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 200480 kb
Host smart-7a665f4e-0fcd-4932-a435-2d03a7198599
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434822663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3434822663
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2000836750
Short name T560
Test name
Test status
Simulation time 188236392 ps
CPU time 2.72 seconds
Started Mar 24 12:34:39 PM PDT 24
Finished Mar 24 12:34:42 PM PDT 24
Peak memory 212184 kb
Host smart-a0445319-dcd1-470a-a8c6-508f103d0f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000836750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2000836750
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2292573485
Short name T589
Test name
Test status
Simulation time 128153803 ps
CPU time 1 seconds
Started Mar 24 12:34:49 PM PDT 24
Finished Mar 24 12:34:50 PM PDT 24
Peak memory 200364 kb
Host smart-fb3015b1-7efb-4b8a-b0fb-24911ee49be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292573485 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2292573485
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.4091889662
Short name T110
Test name
Test status
Simulation time 80696909 ps
CPU time 0.8 seconds
Started Mar 24 12:34:28 PM PDT 24
Finished Mar 24 12:34:29 PM PDT 24
Peak memory 200244 kb
Host smart-e67faee3-f623-4c45-abfc-fd35c2ea7e65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091889662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4091889662
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1119730039
Short name T111
Test name
Test status
Simulation time 234903233 ps
CPU time 1.57 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:51 PM PDT 24
Peak memory 200484 kb
Host smart-d7c69489-9e27-4591-bcc5-d47584417827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119730039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1119730039
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1957921693
Short name T602
Test name
Test status
Simulation time 264035699 ps
CPU time 2.05 seconds
Started Mar 24 12:34:58 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 208704 kb
Host smart-7bda2266-605f-42f6-a1a6-379d65c91b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957921693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1957921693
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1215219134
Short name T561
Test name
Test status
Simulation time 220691035 ps
CPU time 1.32 seconds
Started Mar 24 12:34:46 PM PDT 24
Finished Mar 24 12:34:48 PM PDT 24
Peak memory 208580 kb
Host smart-82c816aa-3bec-4606-a6c5-3dc34a780577
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215219134 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1215219134
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1890251058
Short name T569
Test name
Test status
Simulation time 67397932 ps
CPU time 0.81 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:45 PM PDT 24
Peak memory 200260 kb
Host smart-68f1cd4f-9d72-467c-9789-34ee4f8351d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890251058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1890251058
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2816806709
Short name T108
Test name
Test status
Simulation time 223787804 ps
CPU time 1.42 seconds
Started Mar 24 12:34:30 PM PDT 24
Finished Mar 24 12:34:32 PM PDT 24
Peak memory 200500 kb
Host smart-792d1943-d7c0-4234-a683-2f8a6650de1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816806709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2816806709
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.557233881
Short name T93
Test name
Test status
Simulation time 283191759 ps
CPU time 2.07 seconds
Started Mar 24 12:34:45 PM PDT 24
Finished Mar 24 12:34:47 PM PDT 24
Peak memory 216824 kb
Host smart-fc852eb7-e857-4333-8546-adf609be2bab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557233881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.557233881
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3686778864
Short name T593
Test name
Test status
Simulation time 138445720 ps
CPU time 1.06 seconds
Started Mar 24 12:34:39 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 208592 kb
Host smart-2e19a475-25cf-43af-a37c-6cd56fb45c53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686778864 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3686778864
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3903074196
Short name T620
Test name
Test status
Simulation time 66397020 ps
CPU time 0.83 seconds
Started Mar 24 12:34:35 PM PDT 24
Finished Mar 24 12:34:37 PM PDT 24
Peak memory 200268 kb
Host smart-7ade426d-824f-40f7-8c62-dae093f0f9c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903074196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3903074196
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2896414976
Short name T583
Test name
Test status
Simulation time 155773611 ps
CPU time 1.18 seconds
Started Mar 24 12:34:59 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 200328 kb
Host smart-bfcc16f8-fe82-4f42-9542-33f39bb4fa22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896414976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2896414976
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.990434547
Short name T551
Test name
Test status
Simulation time 228278374 ps
CPU time 1.81 seconds
Started Mar 24 12:34:38 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 211120 kb
Host smart-9e150f8a-b16b-4311-97d1-c8f3922646d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990434547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.990434547
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4189822598
Short name T96
Test name
Test status
Simulation time 943797472 ps
CPU time 3.04 seconds
Started Mar 24 12:34:35 PM PDT 24
Finished Mar 24 12:34:38 PM PDT 24
Peak memory 200568 kb
Host smart-22d67c0b-0b15-41a1-a137-2d8cfaf6c636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189822598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.4189822598
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1837796567
Short name T573
Test name
Test status
Simulation time 130160911 ps
CPU time 1.03 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:37 PM PDT 24
Peak memory 208524 kb
Host smart-dc4e5f8e-4655-4e8f-b3bf-e35652b5683b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837796567 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1837796567
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2986352604
Short name T585
Test name
Test status
Simulation time 60068534 ps
CPU time 0.77 seconds
Started Mar 24 12:34:44 PM PDT 24
Finished Mar 24 12:34:45 PM PDT 24
Peak memory 200228 kb
Host smart-e5990149-165a-4032-9840-73ff2fe09bc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986352604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2986352604
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2883140189
Short name T106
Test name
Test status
Simulation time 279200617 ps
CPU time 1.57 seconds
Started Mar 24 12:34:33 PM PDT 24
Finished Mar 24 12:34:35 PM PDT 24
Peak memory 200516 kb
Host smart-9cf8b93a-6eda-47ec-97d2-4088eaa69f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883140189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2883140189
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3172044435
Short name T616
Test name
Test status
Simulation time 601832340 ps
CPU time 4 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 208672 kb
Host smart-dd5a1c69-da01-4eb3-8d23-facd3567e475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172044435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3172044435
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3783195573
Short name T135
Test name
Test status
Simulation time 781206464 ps
CPU time 2.71 seconds
Started Mar 24 12:35:08 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 200556 kb
Host smart-8ae22cfd-9d07-41a9-87b6-fb6da7ec63dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783195573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3783195573
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.393682449
Short name T67
Test name
Test status
Simulation time 194911497 ps
CPU time 1.31 seconds
Started Mar 24 12:34:35 PM PDT 24
Finished Mar 24 12:34:36 PM PDT 24
Peak memory 200472 kb
Host smart-97c65aad-04fd-49cd-bac1-7e581ea4892d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393682449 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.393682449
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1060566456
Short name T600
Test name
Test status
Simulation time 84540545 ps
CPU time 0.85 seconds
Started Mar 24 12:34:45 PM PDT 24
Finished Mar 24 12:34:47 PM PDT 24
Peak memory 200252 kb
Host smart-663f076f-7bb9-41e3-aede-6f59642d31f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060566456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1060566456
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1774602606
Short name T563
Test name
Test status
Simulation time 129692371 ps
CPU time 1.19 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:07 PM PDT 24
Peak memory 200308 kb
Host smart-cf088122-827e-497e-9820-51783f640450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774602606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1774602606
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.4128156033
Short name T134
Test name
Test status
Simulation time 911913961 ps
CPU time 3.32 seconds
Started Mar 24 12:34:28 PM PDT 24
Finished Mar 24 12:34:32 PM PDT 24
Peak memory 200532 kb
Host smart-86419246-c0e7-460f-bb94-f41739a496a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128156033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.4128156033
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2143511897
Short name T590
Test name
Test status
Simulation time 120741831 ps
CPU time 1.23 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:38 PM PDT 24
Peak memory 208476 kb
Host smart-fa6a72cb-21ff-46bf-bbbc-3bc727e6da01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143511897 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2143511897
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3609909608
Short name T618
Test name
Test status
Simulation time 85524166 ps
CPU time 0.87 seconds
Started Mar 24 12:34:29 PM PDT 24
Finished Mar 24 12:34:30 PM PDT 24
Peak memory 200264 kb
Host smart-c3cc8f25-ae88-4d00-b581-2152ba1ed037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609909608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3609909608
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3868285906
Short name T543
Test name
Test status
Simulation time 114331712 ps
CPU time 1.37 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 200488 kb
Host smart-09322cc8-e8ec-44e2-abd2-ce2e4936a229
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868285906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3868285906
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2320461346
Short name T120
Test name
Test status
Simulation time 466362765 ps
CPU time 3.4 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:51 PM PDT 24
Peak memory 200424 kb
Host smart-a9fdc13d-97c6-41ee-9f33-8fb20ecdf622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320461346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2320461346
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3663068113
Short name T605
Test name
Test status
Simulation time 561115560 ps
CPU time 2 seconds
Started Mar 24 12:34:42 PM PDT 24
Finished Mar 24 12:34:44 PM PDT 24
Peak memory 200508 kb
Host smart-13f9c39d-afe0-4fc8-9ac9-8977c48a026f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663068113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3663068113
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3701993544
Short name T94
Test name
Test status
Simulation time 122949101 ps
CPU time 0.94 seconds
Started Mar 24 12:34:55 PM PDT 24
Finished Mar 24 12:34:57 PM PDT 24
Peak memory 200340 kb
Host smart-231249d2-5b1f-4b60-95ca-31abb37f09f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701993544 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3701993544
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.4234626162
Short name T109
Test name
Test status
Simulation time 67156237 ps
CPU time 0.76 seconds
Started Mar 24 12:34:43 PM PDT 24
Finished Mar 24 12:34:44 PM PDT 24
Peak memory 200212 kb
Host smart-77e33f0a-6fc9-446a-83cb-cd47950e68e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234626162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.4234626162
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1178664601
Short name T555
Test name
Test status
Simulation time 237334104 ps
CPU time 1.56 seconds
Started Mar 24 12:34:39 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 208776 kb
Host smart-5b9925ba-0a79-4f47-ab79-f928cfbdeaed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178664601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1178664601
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1934723
Short name T558
Test name
Test status
Simulation time 296954054 ps
CPU time 1.93 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 208692 kb
Host smart-572a5356-c5d7-49bf-b68b-7b6bb4c2c0f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1934723
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2556032711
Short name T119
Test name
Test status
Simulation time 414409539 ps
CPU time 1.79 seconds
Started Mar 24 12:34:39 PM PDT 24
Finished Mar 24 12:34:41 PM PDT 24
Peak memory 200508 kb
Host smart-4c2b6d39-2c7b-4737-9479-4ac79fad6cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556032711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2556032711
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2564226067
Short name T594
Test name
Test status
Simulation time 117738701 ps
CPU time 1.18 seconds
Started Mar 24 12:34:23 PM PDT 24
Finished Mar 24 12:34:25 PM PDT 24
Peak memory 208508 kb
Host smart-d6b5c75c-4d38-47f9-8662-1d5497f430b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564226067 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2564226067
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2755168029
Short name T582
Test name
Test status
Simulation time 54151657 ps
CPU time 0.73 seconds
Started Mar 24 12:34:39 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 200192 kb
Host smart-2db37e55-ead1-4340-8fd2-fd38507eb02d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755168029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2755168029
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.739036475
Short name T597
Test name
Test status
Simulation time 274568536 ps
CPU time 1.52 seconds
Started Mar 24 12:34:55 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 200500 kb
Host smart-803cc9f7-e258-42dc-b4c6-0030b1933dfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739036475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.739036475
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1988677244
Short name T69
Test name
Test status
Simulation time 274359300 ps
CPU time 1.72 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:55 PM PDT 24
Peak memory 200568 kb
Host smart-cf186272-aa05-4773-89ec-9c6aaf8b265e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988677244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1988677244
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3398689029
Short name T611
Test name
Test status
Simulation time 176651968 ps
CPU time 1.13 seconds
Started Mar 24 12:34:45 PM PDT 24
Finished Mar 24 12:34:46 PM PDT 24
Peak memory 208568 kb
Host smart-e3d305e5-d029-4857-a84b-00c640e3b29f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398689029 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3398689029
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2188544912
Short name T591
Test name
Test status
Simulation time 81244044 ps
CPU time 0.85 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:39 PM PDT 24
Peak memory 200224 kb
Host smart-5425eb68-8465-40cb-a252-64e90b4019c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188544912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2188544912
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1413248067
Short name T542
Test name
Test status
Simulation time 221666171 ps
CPU time 1.49 seconds
Started Mar 24 12:34:45 PM PDT 24
Finished Mar 24 12:34:48 PM PDT 24
Peak memory 200484 kb
Host smart-92a1d692-32e7-44a9-9595-680e330c31c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413248067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1413248067
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1543012230
Short name T575
Test name
Test status
Simulation time 432793066 ps
CPU time 2.84 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:09 PM PDT 24
Peak memory 212036 kb
Host smart-45e6be2c-251d-4e5e-ab75-4ba5b91c0e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543012230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1543012230
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3401530479
Short name T587
Test name
Test status
Simulation time 424989563 ps
CPU time 1.87 seconds
Started Mar 24 12:34:37 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 200536 kb
Host smart-087fda7b-dbdb-4305-a930-ded324f1917a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401530479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3401530479
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1137820823
Short name T604
Test name
Test status
Simulation time 230281273 ps
CPU time 1.6 seconds
Started Mar 24 12:34:26 PM PDT 24
Finished Mar 24 12:34:29 PM PDT 24
Peak memory 200436 kb
Host smart-2cb9a429-ae08-486c-af11-74fc8297e7f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137820823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
137820823
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3914506761
Short name T548
Test name
Test status
Simulation time 796670645 ps
CPU time 4.21 seconds
Started Mar 24 12:34:50 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 200464 kb
Host smart-8fbf76b2-db8f-401f-bd5c-e1b97287c16d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914506761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
914506761
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.118488244
Short name T545
Test name
Test status
Simulation time 129149703 ps
CPU time 0.91 seconds
Started Mar 24 12:34:41 PM PDT 24
Finished Mar 24 12:34:42 PM PDT 24
Peak memory 200260 kb
Host smart-733de4ac-863a-47d1-90be-9e39bc324ad2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118488244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.118488244
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2675026624
Short name T68
Test name
Test status
Simulation time 117366390 ps
CPU time 1.25 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:37 PM PDT 24
Peak memory 208596 kb
Host smart-d0892f0d-9221-4351-a43b-1c42ebad7361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675026624 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2675026624
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1770166194
Short name T613
Test name
Test status
Simulation time 58618979 ps
CPU time 0.74 seconds
Started Mar 24 12:34:45 PM PDT 24
Finished Mar 24 12:34:45 PM PDT 24
Peak memory 200128 kb
Host smart-46ac2ea6-8e5b-4a0d-96d9-6130a80be13b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770166194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1770166194
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3638412125
Short name T614
Test name
Test status
Simulation time 136409706 ps
CPU time 1.34 seconds
Started Mar 24 12:34:37 PM PDT 24
Finished Mar 24 12:34:39 PM PDT 24
Peak memory 200440 kb
Host smart-d3d0ff4f-bab0-49e4-9f90-7fe7ce9d8da5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638412125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3638412125
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3102104414
Short name T572
Test name
Test status
Simulation time 280373620 ps
CPU time 1.95 seconds
Started Mar 24 12:34:30 PM PDT 24
Finished Mar 24 12:34:32 PM PDT 24
Peak memory 216844 kb
Host smart-1b1caaa4-3a9a-4b3d-a616-46c97f494856
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102104414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3102104414
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3615061193
Short name T612
Test name
Test status
Simulation time 511495233 ps
CPU time 2.05 seconds
Started Mar 24 12:34:28 PM PDT 24
Finished Mar 24 12:34:30 PM PDT 24
Peak memory 200548 kb
Host smart-2b5dc971-ccdb-4db7-af5f-295f5eb29b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615061193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3615061193
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4158910302
Short name T596
Test name
Test status
Simulation time 213781428 ps
CPU time 1.65 seconds
Started Mar 24 12:34:35 PM PDT 24
Finished Mar 24 12:34:37 PM PDT 24
Peak memory 200468 kb
Host smart-cd163ca3-e247-4785-8ecf-c9e959aba772
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158910302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
158910302
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.985258649
Short name T568
Test name
Test status
Simulation time 482116186 ps
CPU time 5.51 seconds
Started Mar 24 12:34:30 PM PDT 24
Finished Mar 24 12:34:36 PM PDT 24
Peak memory 200460 kb
Host smart-ba3d1f62-9956-44fe-9d0a-8d8a43f53fa0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985258649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.985258649
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2494583890
Short name T610
Test name
Test status
Simulation time 134112829 ps
CPU time 0.91 seconds
Started Mar 24 12:34:47 PM PDT 24
Finished Mar 24 12:34:49 PM PDT 24
Peak memory 200268 kb
Host smart-0d0fae49-7293-44a1-a612-fee775b38e81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494583890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
494583890
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2161483701
Short name T70
Test name
Test status
Simulation time 140859285 ps
CPU time 1.15 seconds
Started Mar 24 12:34:29 PM PDT 24
Finished Mar 24 12:34:30 PM PDT 24
Peak memory 210860 kb
Host smart-84b956a2-bf5d-41d9-bb26-c5120dec79eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161483701 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2161483701
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1270012167
Short name T570
Test name
Test status
Simulation time 73531956 ps
CPU time 0.78 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 200268 kb
Host smart-d3dca11b-320c-40fd-bac4-b298fc97fbb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270012167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1270012167
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3743094929
Short name T554
Test name
Test status
Simulation time 185866001 ps
CPU time 1.31 seconds
Started Mar 24 12:34:33 PM PDT 24
Finished Mar 24 12:34:35 PM PDT 24
Peak memory 200500 kb
Host smart-4270ad29-b2bd-4084-9b57-e49db6ad790b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743094929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3743094929
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3910521551
Short name T574
Test name
Test status
Simulation time 300983075 ps
CPU time 2.4 seconds
Started Mar 24 12:34:52 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 208696 kb
Host smart-e6d21a3d-2e99-446b-a79b-4b60d33117f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910521551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3910521551
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1347844683
Short name T592
Test name
Test status
Simulation time 501577897 ps
CPU time 2 seconds
Started Mar 24 12:34:24 PM PDT 24
Finished Mar 24 12:34:26 PM PDT 24
Peak memory 200592 kb
Host smart-63147048-3b1e-43b1-8591-c122d312021c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347844683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1347844683
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3345420368
Short name T588
Test name
Test status
Simulation time 237276112 ps
CPU time 1.57 seconds
Started Mar 24 12:34:40 PM PDT 24
Finished Mar 24 12:34:42 PM PDT 24
Peak memory 200416 kb
Host smart-b26395d8-f011-400b-b258-966d50611b7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345420368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
345420368
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2672887907
Short name T565
Test name
Test status
Simulation time 478488711 ps
CPU time 5.97 seconds
Started Mar 24 12:34:28 PM PDT 24
Finished Mar 24 12:34:34 PM PDT 24
Peak memory 200412 kb
Host smart-d55ae8a5-885b-442f-b7a7-fef43e51e6dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672887907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
672887907
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3034448973
Short name T599
Test name
Test status
Simulation time 130233442 ps
CPU time 0.91 seconds
Started Mar 24 12:34:42 PM PDT 24
Finished Mar 24 12:34:43 PM PDT 24
Peak memory 200252 kb
Host smart-66a9a8f3-cd37-4937-91d6-7f52e73f4603
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034448973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
034448973
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.629965026
Short name T66
Test name
Test status
Simulation time 97541189 ps
CPU time 1.02 seconds
Started Mar 24 12:34:38 PM PDT 24
Finished Mar 24 12:34:39 PM PDT 24
Peak memory 208552 kb
Host smart-4c4a9f46-a60f-489d-bbd6-c1b20a74666b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629965026 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.629965026
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3123885799
Short name T595
Test name
Test status
Simulation time 62236341 ps
CPU time 0.77 seconds
Started Mar 24 12:34:14 PM PDT 24
Finished Mar 24 12:34:15 PM PDT 24
Peak memory 200268 kb
Host smart-edcf87ee-024e-40e4-9f7d-84211777c91b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123885799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3123885799
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.960915669
Short name T64
Test name
Test status
Simulation time 253692571 ps
CPU time 1.65 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:59 PM PDT 24
Peak memory 200456 kb
Host smart-2ba9222c-e01e-4ccf-9ac8-0397991291d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960915669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.960915669
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2285799522
Short name T95
Test name
Test status
Simulation time 242865062 ps
CPU time 1.9 seconds
Started Mar 24 12:34:31 PM PDT 24
Finished Mar 24 12:34:34 PM PDT 24
Peak memory 200484 kb
Host smart-95bb49be-c67b-4bef-8380-800cf50a58ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285799522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2285799522
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1723625517
Short name T116
Test name
Test status
Simulation time 997504864 ps
CPU time 3.35 seconds
Started Mar 24 12:34:35 PM PDT 24
Finished Mar 24 12:34:39 PM PDT 24
Peak memory 200492 kb
Host smart-516879ab-35ec-4fd4-915d-788543eea95b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723625517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1723625517
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.309957425
Short name T547
Test name
Test status
Simulation time 141524032 ps
CPU time 1.16 seconds
Started Mar 24 12:34:25 PM PDT 24
Finished Mar 24 12:34:28 PM PDT 24
Peak memory 209608 kb
Host smart-d235b633-5b30-4e24-9f4e-4cb3dfc3c1fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309957425 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.309957425
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.426246936
Short name T607
Test name
Test status
Simulation time 75916181 ps
CPU time 0.8 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:06 PM PDT 24
Peak memory 200156 kb
Host smart-bbb372a8-1223-4764-ad49-c40657b3bbeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426246936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.426246936
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1415434391
Short name T586
Test name
Test status
Simulation time 127109813 ps
CPU time 1.2 seconds
Started Mar 24 12:34:25 PM PDT 24
Finished Mar 24 12:34:28 PM PDT 24
Peak memory 200484 kb
Host smart-d46761a3-a33a-401c-a1a5-ad8c28c88af0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415434391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1415434391
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2279606924
Short name T578
Test name
Test status
Simulation time 531041221 ps
CPU time 3.22 seconds
Started Mar 24 12:35:57 PM PDT 24
Finished Mar 24 12:36:00 PM PDT 24
Peak memory 216816 kb
Host smart-80eaa2f4-a609-43a5-a1c5-20ebc6f9a72d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279606924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2279606924
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2480401044
Short name T114
Test name
Test status
Simulation time 944455484 ps
CPU time 3.41 seconds
Started Mar 24 12:34:33 PM PDT 24
Finished Mar 24 12:34:37 PM PDT 24
Peak memory 200484 kb
Host smart-4814e364-6c8e-4c07-a161-06983a9bc2fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480401044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2480401044
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1654237129
Short name T579
Test name
Test status
Simulation time 112234432 ps
CPU time 1.06 seconds
Started Mar 24 12:34:37 PM PDT 24
Finished Mar 24 12:34:39 PM PDT 24
Peak memory 208508 kb
Host smart-34665d8c-4572-48b2-b71c-b19de45520c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654237129 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1654237129
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.174265588
Short name T546
Test name
Test status
Simulation time 57370491 ps
CPU time 0.77 seconds
Started Mar 24 12:34:39 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 200260 kb
Host smart-872618b0-de8e-48fa-898f-46d4f4c52442
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174265588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.174265588
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2456164401
Short name T617
Test name
Test status
Simulation time 139690843 ps
CPU time 1.11 seconds
Started Mar 24 12:34:34 PM PDT 24
Finished Mar 24 12:34:41 PM PDT 24
Peak memory 200328 kb
Host smart-11787424-7895-4dc8-8661-9a4981a81168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456164401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2456164401
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1176048337
Short name T65
Test name
Test status
Simulation time 533743902 ps
CPU time 3.37 seconds
Started Mar 24 12:34:32 PM PDT 24
Finished Mar 24 12:34:35 PM PDT 24
Peak memory 208668 kb
Host smart-0f3389b1-0083-46c3-ad71-b169bda406fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176048337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1176048337
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1662234142
Short name T117
Test name
Test status
Simulation time 781329854 ps
CPU time 2.8 seconds
Started Mar 24 12:34:37 PM PDT 24
Finished Mar 24 12:34:41 PM PDT 24
Peak memory 200532 kb
Host smart-4d12643e-080e-4604-a89f-7fb73c7913ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662234142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1662234142
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2696884636
Short name T603
Test name
Test status
Simulation time 97244798 ps
CPU time 0.91 seconds
Started Mar 24 12:35:56 PM PDT 24
Finished Mar 24 12:35:58 PM PDT 24
Peak memory 200372 kb
Host smart-0c5382dd-ce18-4681-8c76-8f0cbb7ca66b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696884636 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2696884636
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1404251550
Short name T105
Test name
Test status
Simulation time 76824005 ps
CPU time 0.79 seconds
Started Mar 24 12:34:46 PM PDT 24
Finished Mar 24 12:34:47 PM PDT 24
Peak memory 200268 kb
Host smart-c0458cba-7afe-43ef-86f7-1f58a589bad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404251550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1404251550
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.21514396
Short name T63
Test name
Test status
Simulation time 194897700 ps
CPU time 1.42 seconds
Started Mar 24 12:34:39 PM PDT 24
Finished Mar 24 12:34:41 PM PDT 24
Peak memory 200512 kb
Host smart-4a590aca-c473-4c3f-8ad0-4bf013430543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21514396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same
_csr_outstanding.21514396
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1831239137
Short name T557
Test name
Test status
Simulation time 465917669 ps
CPU time 3.56 seconds
Started Mar 24 12:34:14 PM PDT 24
Finished Mar 24 12:34:17 PM PDT 24
Peak memory 209100 kb
Host smart-f4cb6fda-003a-4819-9c60-84b1fe36f397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831239137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1831239137
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3484969011
Short name T615
Test name
Test status
Simulation time 842462346 ps
CPU time 2.97 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 200512 kb
Host smart-b518d103-d41f-481a-af97-c114b1a56bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484969011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3484969011
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3667286104
Short name T562
Test name
Test status
Simulation time 63531745 ps
CPU time 0.77 seconds
Started Mar 24 12:35:56 PM PDT 24
Finished Mar 24 12:35:57 PM PDT 24
Peak memory 200120 kb
Host smart-cdcec2e3-e02f-4c95-9336-e7cd847fa141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667286104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3667286104
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.26002455
Short name T577
Test name
Test status
Simulation time 151070161 ps
CPU time 1.19 seconds
Started Mar 24 12:34:22 PM PDT 24
Finished Mar 24 12:34:23 PM PDT 24
Peak memory 200324 kb
Host smart-4ae8583b-3ffe-423b-977c-d7f604ad550d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26002455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same
_csr_outstanding.26002455
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.426091521
Short name T549
Test name
Test status
Simulation time 129991057 ps
CPU time 1.86 seconds
Started Mar 24 12:35:57 PM PDT 24
Finished Mar 24 12:35:59 PM PDT 24
Peak memory 208688 kb
Host smart-47e7f89c-39d7-4947-970b-cd3e95690c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426091521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.426091521
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.900904339
Short name T132
Test name
Test status
Simulation time 913630552 ps
CPU time 3.28 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:39 PM PDT 24
Peak memory 200560 kb
Host smart-2f208843-baed-420f-81f4-a78002269157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900904339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
900904339
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1318366615
Short name T598
Test name
Test status
Simulation time 191149475 ps
CPU time 1.26 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:54 PM PDT 24
Peak memory 208588 kb
Host smart-285396be-b38f-4c74-996f-2c1d89b4480c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318366615 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1318366615
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3533045429
Short name T619
Test name
Test status
Simulation time 94665283 ps
CPU time 0.85 seconds
Started Mar 24 12:36:05 PM PDT 24
Finished Mar 24 12:36:07 PM PDT 24
Peak memory 200264 kb
Host smart-ba04975b-d813-42ea-99ad-4e521b9818cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533045429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3533045429
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3974546944
Short name T609
Test name
Test status
Simulation time 223161410 ps
CPU time 1.48 seconds
Started Mar 24 12:34:42 PM PDT 24
Finished Mar 24 12:34:44 PM PDT 24
Peak memory 200480 kb
Host smart-b7b1f8ed-8f8f-486e-8396-ca5736246d2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974546944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3974546944
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2770725424
Short name T584
Test name
Test status
Simulation time 113231242 ps
CPU time 1.6 seconds
Started Mar 24 12:34:37 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 208660 kb
Host smart-80900991-d783-417e-8f75-804e359f3336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770725424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2770725424
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1218318734
Short name T112
Test name
Test status
Simulation time 499737571 ps
CPU time 2.12 seconds
Started Mar 24 12:34:36 PM PDT 24
Finished Mar 24 12:34:40 PM PDT 24
Peak memory 200496 kb
Host smart-d71c8006-5a5f-45aa-979b-afcbeb86db3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218318734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1218318734
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.452235947
Short name T540
Test name
Test status
Simulation time 90242699 ps
CPU time 0.85 seconds
Started Mar 24 12:43:18 PM PDT 24
Finished Mar 24 12:43:18 PM PDT 24
Peak memory 200692 kb
Host smart-db55b632-2db5-4b30-a165-1bff94a28e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452235947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.452235947
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3543865063
Short name T353
Test name
Test status
Simulation time 1229825253 ps
CPU time 5.53 seconds
Started Mar 24 12:43:17 PM PDT 24
Finished Mar 24 12:43:23 PM PDT 24
Peak memory 222580 kb
Host smart-14f4206e-ddda-4468-b175-57a70ed92042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543865063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3543865063
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.55092064
Short name T495
Test name
Test status
Simulation time 244450052 ps
CPU time 1.08 seconds
Started Mar 24 12:43:27 PM PDT 24
Finished Mar 24 12:43:29 PM PDT 24
Peak memory 218072 kb
Host smart-fcafbd21-3775-4696-b676-8a9a303ce4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55092064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.55092064
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.756592397
Short name T361
Test name
Test status
Simulation time 99286425 ps
CPU time 0.8 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 200632 kb
Host smart-5dc7ebae-3975-4ca3-8f62-b119b8df9d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756592397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.756592397
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.4285190672
Short name T198
Test name
Test status
Simulation time 832827941 ps
CPU time 3.86 seconds
Started Mar 24 12:43:13 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 201008 kb
Host smart-6e4c97ee-275b-4382-979a-5c5a0051d645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285190672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.4285190672
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3288092698
Short name T338
Test name
Test status
Simulation time 107457744 ps
CPU time 0.99 seconds
Started Mar 24 12:43:17 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 200852 kb
Host smart-be8e6881-efab-459f-9497-d9fc1ab4027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288092698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3288092698
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1961651949
Short name T291
Test name
Test status
Simulation time 245290165 ps
CPU time 1.45 seconds
Started Mar 24 12:43:23 PM PDT 24
Finished Mar 24 12:43:26 PM PDT 24
Peak memory 200956 kb
Host smart-1719714d-fefe-4e11-ae63-65ee54bcf305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961651949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1961651949
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1705070271
Short name T429
Test name
Test status
Simulation time 3932693412 ps
CPU time 18 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:26 PM PDT 24
Peak memory 201092 kb
Host smart-9294b6d4-b2a5-41a4-8af5-190f968d5d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705070271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1705070271
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.790487099
Short name T480
Test name
Test status
Simulation time 290148609 ps
CPU time 1.85 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:14 PM PDT 24
Peak memory 200872 kb
Host smart-e4c80b34-d30f-4302-b75b-b7ece961d412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790487099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.790487099
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1511092947
Short name T521
Test name
Test status
Simulation time 67692790 ps
CPU time 0.75 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 200848 kb
Host smart-6847eb30-47bf-4802-88b0-6d37a8476d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511092947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1511092947
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1303504011
Short name T152
Test name
Test status
Simulation time 65247308 ps
CPU time 0.77 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 200700 kb
Host smart-2c66e1c2-250c-4220-b1f1-e1bec9a8551d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303504011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1303504011
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.293767657
Short name T330
Test name
Test status
Simulation time 2175666038 ps
CPU time 8.3 seconds
Started Mar 24 12:43:34 PM PDT 24
Finished Mar 24 12:43:43 PM PDT 24
Peak memory 218960 kb
Host smart-4f75c639-df59-4a20-a117-ce78dcd506bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293767657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.293767657
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2021921208
Short name T409
Test name
Test status
Simulation time 244367707 ps
CPU time 1.2 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 218032 kb
Host smart-7f3a181f-511f-47f2-b84e-dfb82b11288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021921208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2021921208
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2352030089
Short name T249
Test name
Test status
Simulation time 153776205 ps
CPU time 0.87 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 200676 kb
Host smart-e0c5698e-44e4-49bb-9d35-fc83a10eda69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352030089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2352030089
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2310988521
Short name T190
Test name
Test status
Simulation time 837584032 ps
CPU time 4.2 seconds
Started Mar 24 12:43:13 PM PDT 24
Finished Mar 24 12:43:18 PM PDT 24
Peak memory 200968 kb
Host smart-8dca257d-fc66-4f70-8984-e0cd61952dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310988521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2310988521
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3888558896
Short name T72
Test name
Test status
Simulation time 8858599419 ps
CPU time 13.25 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:28 PM PDT 24
Peak memory 217684 kb
Host smart-900c1f16-4d5b-4e32-94b9-d9c35b169ff5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888558896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3888558896
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.487638500
Short name T294
Test name
Test status
Simulation time 182775715 ps
CPU time 1.19 seconds
Started Mar 24 12:43:20 PM PDT 24
Finished Mar 24 12:43:22 PM PDT 24
Peak memory 200816 kb
Host smart-2f8a3f85-0602-4ec1-bc66-d8210a5e03d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487638500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.487638500
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3594132691
Short name T180
Test name
Test status
Simulation time 110567166 ps
CPU time 1.22 seconds
Started Mar 24 12:43:11 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 201008 kb
Host smart-ed67bc96-680a-4790-bd97-6a5988fa23d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594132691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3594132691
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2699007455
Short name T471
Test name
Test status
Simulation time 5175989690 ps
CPU time 17.38 seconds
Started Mar 24 12:43:20 PM PDT 24
Finished Mar 24 12:43:38 PM PDT 24
Peak memory 217400 kb
Host smart-3a81a228-046d-46d8-99c0-742b2045c44e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699007455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2699007455
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.871094299
Short name T235
Test name
Test status
Simulation time 268741388 ps
CPU time 1.88 seconds
Started Mar 24 12:43:21 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 200860 kb
Host smart-c47bb5c7-5c36-4e68-8850-1425bafbe8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871094299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.871094299
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1830517326
Short name T149
Test name
Test status
Simulation time 60729813 ps
CPU time 0.75 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 200816 kb
Host smart-b9068a8c-d2db-4891-8107-66efeeec8401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830517326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1830517326
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3185928761
Short name T368
Test name
Test status
Simulation time 68534163 ps
CPU time 0.76 seconds
Started Mar 24 12:43:53 PM PDT 24
Finished Mar 24 12:43:56 PM PDT 24
Peak memory 200696 kb
Host smart-23f956bb-81c6-4b20-aabf-4b89d2d369d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185928761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3185928761
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.511112702
Short name T250
Test name
Test status
Simulation time 1224742455 ps
CPU time 5.72 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:39 PM PDT 24
Peak memory 218596 kb
Host smart-5cdceaf5-3b48-480b-962f-c6ad85a2315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511112702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.511112702
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2243419442
Short name T501
Test name
Test status
Simulation time 244193769 ps
CPU time 1.02 seconds
Started Mar 24 12:43:34 PM PDT 24
Finished Mar 24 12:43:35 PM PDT 24
Peak memory 218172 kb
Host smart-54566aab-370e-40bf-b699-780a769b47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243419442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2243419442
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.8240750
Short name T370
Test name
Test status
Simulation time 158440993 ps
CPU time 0.84 seconds
Started Mar 24 12:43:23 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 200664 kb
Host smart-7f75757e-091b-4936-b2f5-59eb194b5d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8240750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.8240750
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2251965149
Short name T188
Test name
Test status
Simulation time 1510670585 ps
CPU time 6.16 seconds
Started Mar 24 12:43:31 PM PDT 24
Finished Mar 24 12:43:38 PM PDT 24
Peak memory 201332 kb
Host smart-b462f21f-b5c8-4e53-b072-1df3014b3b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251965149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2251965149
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.770122308
Short name T243
Test name
Test status
Simulation time 156776086 ps
CPU time 1.13 seconds
Started Mar 24 12:43:38 PM PDT 24
Finished Mar 24 12:43:40 PM PDT 24
Peak memory 200896 kb
Host smart-f2b30792-df0e-4516-9875-b95c6ffeb94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770122308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.770122308
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1074050391
Short name T329
Test name
Test status
Simulation time 192454960 ps
CPU time 1.32 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:35 PM PDT 24
Peak memory 201100 kb
Host smart-29116df2-0f90-4073-85e3-3b56b373ad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074050391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1074050391
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3820691599
Short name T83
Test name
Test status
Simulation time 121402423 ps
CPU time 1.48 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:43:47 PM PDT 24
Peak memory 200928 kb
Host smart-e113331d-dd76-485c-8bc3-9d0819e142e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820691599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3820691599
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.413261550
Short name T479
Test name
Test status
Simulation time 81910179 ps
CPU time 0.86 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:50 PM PDT 24
Peak memory 200824 kb
Host smart-3088961d-e641-46ff-b2e9-24d49a0fe728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413261550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.413261550
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.249143381
Short name T147
Test name
Test status
Simulation time 54831098 ps
CPU time 0.75 seconds
Started Mar 24 12:43:28 PM PDT 24
Finished Mar 24 12:43:29 PM PDT 24
Peak memory 200660 kb
Host smart-cbfe2bb1-725d-440e-a3d5-11e8a7dfc0ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249143381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.249143381
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3337905517
Short name T415
Test name
Test status
Simulation time 1233452634 ps
CPU time 5.7 seconds
Started Mar 24 12:43:32 PM PDT 24
Finished Mar 24 12:43:38 PM PDT 24
Peak memory 222540 kb
Host smart-97d7bb12-5c88-4268-b6ad-b3fcae9895f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337905517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3337905517
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3433400325
Short name T392
Test name
Test status
Simulation time 244155170 ps
CPU time 1.07 seconds
Started Mar 24 12:43:27 PM PDT 24
Finished Mar 24 12:43:28 PM PDT 24
Peak memory 218180 kb
Host smart-654234fa-2b90-4e89-908c-0917a6780e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433400325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3433400325
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.4066650174
Short name T529
Test name
Test status
Simulation time 98780056 ps
CPU time 0.78 seconds
Started Mar 24 12:43:20 PM PDT 24
Finished Mar 24 12:43:22 PM PDT 24
Peak memory 200708 kb
Host smart-d2649d77-1a55-4835-9d37-61990f170264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066650174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.4066650174
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2732839745
Short name T80
Test name
Test status
Simulation time 905709761 ps
CPU time 4.58 seconds
Started Mar 24 12:43:50 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 200940 kb
Host smart-96e20865-ad24-435d-a2c2-ad73324e73b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732839745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2732839745
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1106000100
Short name T508
Test name
Test status
Simulation time 110079971 ps
CPU time 1.01 seconds
Started Mar 24 12:43:34 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 200820 kb
Host smart-02342bc6-2c5b-4f3f-a08e-a9cb59efeea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106000100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1106000100
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.953560128
Short name T513
Test name
Test status
Simulation time 118454773 ps
CPU time 1.2 seconds
Started Mar 24 12:43:47 PM PDT 24
Finished Mar 24 12:43:48 PM PDT 24
Peak memory 201052 kb
Host smart-2a550f09-6709-4a36-ae67-2a897b38e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953560128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.953560128
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1197003021
Short name T467
Test name
Test status
Simulation time 12385757441 ps
CPU time 46.8 seconds
Started Mar 24 12:43:34 PM PDT 24
Finished Mar 24 12:44:21 PM PDT 24
Peak memory 209284 kb
Host smart-2552947d-8af5-4197-8eba-3d7e378f5726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197003021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1197003021
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.786385778
Short name T466
Test name
Test status
Simulation time 352995631 ps
CPU time 2.3 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 200872 kb
Host smart-a5ee6d31-edbf-4a31-a57d-7c4efced4d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786385778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.786385778
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3351476362
Short name T389
Test name
Test status
Simulation time 70027579 ps
CPU time 0.82 seconds
Started Mar 24 12:43:36 PM PDT 24
Finished Mar 24 12:43:37 PM PDT 24
Peak memory 200648 kb
Host smart-bb0cc0b9-153b-4ee7-a549-17a553f5db45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351476362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3351476362
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2482168318
Short name T263
Test name
Test status
Simulation time 2362586314 ps
CPU time 8 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:41 PM PDT 24
Peak memory 222460 kb
Host smart-e9d0a15c-3464-4319-8707-2dc118705257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482168318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2482168318
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.898396392
Short name T349
Test name
Test status
Simulation time 244780432 ps
CPU time 1.11 seconds
Started Mar 24 12:43:41 PM PDT 24
Finished Mar 24 12:43:43 PM PDT 24
Peak memory 218316 kb
Host smart-97c507b7-db73-4d19-91a2-71489d5b0e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898396392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.898396392
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.491884000
Short name T525
Test name
Test status
Simulation time 202618210 ps
CPU time 0.87 seconds
Started Mar 24 12:43:38 PM PDT 24
Finished Mar 24 12:43:40 PM PDT 24
Peak memory 200760 kb
Host smart-23ee7e55-c70f-4c79-998b-14ad79ef3492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491884000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.491884000
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3883326912
Short name T104
Test name
Test status
Simulation time 2052371329 ps
CPU time 8.39 seconds
Started Mar 24 12:43:38 PM PDT 24
Finished Mar 24 12:43:47 PM PDT 24
Peak memory 201000 kb
Host smart-e908cc08-8bd1-4210-8672-6e5a74cb3d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883326912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3883326912
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3683103873
Short name T317
Test name
Test status
Simulation time 172947269 ps
CPU time 1.18 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 200828 kb
Host smart-da6f502b-7e1e-4406-a98e-7a4d1605aa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683103873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3683103873
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.4058198642
Short name T535
Test name
Test status
Simulation time 253115768 ps
CPU time 1.51 seconds
Started Mar 24 12:43:36 PM PDT 24
Finished Mar 24 12:43:38 PM PDT 24
Peak memory 200956 kb
Host smart-51612dfb-52f6-425b-a065-075b02b3cc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058198642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.4058198642
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.763640973
Short name T419
Test name
Test status
Simulation time 6999754681 ps
CPU time 30.23 seconds
Started Mar 24 12:43:37 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 201068 kb
Host smart-f3f2bd99-38a7-4cd4-a538-e6360c36ced6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763640973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.763640973
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2539719085
Short name T491
Test name
Test status
Simulation time 259574850 ps
CPU time 1.7 seconds
Started Mar 24 12:43:29 PM PDT 24
Finished Mar 24 12:43:31 PM PDT 24
Peak memory 200884 kb
Host smart-f272d176-29ae-4a57-942e-982608e7bbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539719085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2539719085
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2337812506
Short name T225
Test name
Test status
Simulation time 73366111 ps
CPU time 0.82 seconds
Started Mar 24 12:43:40 PM PDT 24
Finished Mar 24 12:43:41 PM PDT 24
Peak memory 200816 kb
Host smart-c048397a-29ca-4ede-aece-d61289523bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337812506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2337812506
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3793451899
Short name T451
Test name
Test status
Simulation time 70082785 ps
CPU time 0.79 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:43:47 PM PDT 24
Peak memory 200660 kb
Host smart-a5b1d7bf-16bf-4259-bc40-653447e7052d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793451899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3793451899
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3560683071
Short name T402
Test name
Test status
Simulation time 2168760955 ps
CPU time 8.29 seconds
Started Mar 24 12:43:32 PM PDT 24
Finished Mar 24 12:43:41 PM PDT 24
Peak memory 222656 kb
Host smart-88f7c723-cca6-40f5-9ed9-7b572c0b2dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560683071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3560683071
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3180628967
Short name T434
Test name
Test status
Simulation time 135440363 ps
CPU time 0.81 seconds
Started Mar 24 12:43:36 PM PDT 24
Finished Mar 24 12:43:37 PM PDT 24
Peak memory 200672 kb
Host smart-8a4f547b-9c05-4713-9798-47b78d8506f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180628967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3180628967
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2505965235
Short name T458
Test name
Test status
Simulation time 1657414891 ps
CPU time 6.26 seconds
Started Mar 24 12:43:29 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 200928 kb
Host smart-40e10241-c88c-45c2-90a8-f893ba18d172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505965235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2505965235
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3743708747
Short name T60
Test name
Test status
Simulation time 149567540 ps
CPU time 1.1 seconds
Started Mar 24 12:43:42 PM PDT 24
Finished Mar 24 12:43:44 PM PDT 24
Peak memory 200916 kb
Host smart-6c1a941d-6742-4216-b2ee-f80628c44fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743708747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3743708747
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3060804251
Short name T178
Test name
Test status
Simulation time 121822814 ps
CPU time 1.23 seconds
Started Mar 24 12:43:24 PM PDT 24
Finished Mar 24 12:43:26 PM PDT 24
Peak memory 201060 kb
Host smart-f0843e0f-fc4b-4203-93cc-8ddffa6d3618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060804251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3060804251
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2661310571
Short name T268
Test name
Test status
Simulation time 11090903360 ps
CPU time 37.07 seconds
Started Mar 24 12:43:37 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 201076 kb
Host smart-67e3db44-b3d9-413d-976d-24468bfc24b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661310571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2661310571
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.325950418
Short name T499
Test name
Test status
Simulation time 120733416 ps
CPU time 1.46 seconds
Started Mar 24 12:43:28 PM PDT 24
Finished Mar 24 12:43:30 PM PDT 24
Peak memory 200872 kb
Host smart-ae73b202-9cc7-402f-9427-818ae59a43b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325950418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.325950418
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1118106823
Short name T262
Test name
Test status
Simulation time 87148893 ps
CPU time 0.91 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:34 PM PDT 24
Peak memory 200820 kb
Host smart-dddbee4a-ee6c-4938-a453-59b7f8336f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118106823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1118106823
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.23738349
Short name T274
Test name
Test status
Simulation time 72733593 ps
CPU time 0.79 seconds
Started Mar 24 12:43:34 PM PDT 24
Finished Mar 24 12:43:35 PM PDT 24
Peak memory 200704 kb
Host smart-08f78f0c-d7d2-4ced-8b40-b095419c8791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23738349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.23738349
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1572874423
Short name T49
Test name
Test status
Simulation time 1222626699 ps
CPU time 5.71 seconds
Started Mar 24 12:43:23 PM PDT 24
Finished Mar 24 12:43:29 PM PDT 24
Peak memory 218472 kb
Host smart-a8924dcf-c43f-4682-ad17-9a31fe0ff370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572874423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1572874423
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3634272367
Short name T55
Test name
Test status
Simulation time 243983788 ps
CPU time 1.05 seconds
Started Mar 24 12:43:45 PM PDT 24
Finished Mar 24 12:43:46 PM PDT 24
Peak memory 218192 kb
Host smart-417ee379-a5c5-476f-85b1-a84ba9c467a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634272367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3634272367
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1388362948
Short name T206
Test name
Test status
Simulation time 858458254 ps
CPU time 4.23 seconds
Started Mar 24 12:43:40 PM PDT 24
Finished Mar 24 12:43:44 PM PDT 24
Peak memory 201120 kb
Host smart-035056b9-3acb-4e84-b784-84724cb1de3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388362948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1388362948
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3606240288
Short name T497
Test name
Test status
Simulation time 109105312 ps
CPU time 1.05 seconds
Started Mar 24 12:43:34 PM PDT 24
Finished Mar 24 12:43:35 PM PDT 24
Peak memory 200836 kb
Host smart-8e089ac6-4433-4c3e-a41a-336142ebd68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606240288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3606240288
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1606466626
Short name T129
Test name
Test status
Simulation time 246871672 ps
CPU time 1.52 seconds
Started Mar 24 12:43:54 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 201076 kb
Host smart-32967dd7-a240-4974-a521-fba44bc6c6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606466626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1606466626
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1213922533
Short name T503
Test name
Test status
Simulation time 12391460287 ps
CPU time 44.53 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:44:30 PM PDT 24
Peak memory 209324 kb
Host smart-aeea5792-6e96-4a34-913a-3f35f3eb0840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213922533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1213922533
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1922511691
Short name T173
Test name
Test status
Simulation time 360608184 ps
CPU time 1.96 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:54 PM PDT 24
Peak memory 200948 kb
Host smart-02073097-1c8f-48b8-bfe0-eca8bb9db4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922511691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1922511691
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2574562701
Short name T183
Test name
Test status
Simulation time 95451992 ps
CPU time 0.88 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:41 PM PDT 24
Peak memory 200756 kb
Host smart-871262ad-0494-4689-b4cb-9e2a924e6e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574562701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2574562701
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2108989104
Short name T143
Test name
Test status
Simulation time 76913557 ps
CPU time 0.85 seconds
Started Mar 24 12:43:40 PM PDT 24
Finished Mar 24 12:43:43 PM PDT 24
Peak memory 201004 kb
Host smart-5a48d7bc-ede7-4aee-9370-21e170d94194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108989104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2108989104
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.194933401
Short name T320
Test name
Test status
Simulation time 1893498026 ps
CPU time 7.83 seconds
Started Mar 24 12:43:54 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 218476 kb
Host smart-f774f22e-c9cd-4c9e-b6ea-426ee9f22268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194933401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.194933401
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1835678008
Short name T61
Test name
Test status
Simulation time 244746776 ps
CPU time 1.17 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:52 PM PDT 24
Peak memory 218172 kb
Host smart-046872ba-dd44-4fb3-b201-b8b82b797ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835678008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1835678008
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1827717290
Short name T222
Test name
Test status
Simulation time 93072242 ps
CPU time 0.77 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:54 PM PDT 24
Peak memory 200648 kb
Host smart-b6ed7d74-c679-4789-a6e3-edbed3bceb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827717290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1827717290
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3731336020
Short name T270
Test name
Test status
Simulation time 1316453742 ps
CPU time 5.34 seconds
Started Mar 24 12:43:43 PM PDT 24
Finished Mar 24 12:43:49 PM PDT 24
Peak memory 200940 kb
Host smart-e3439751-45d6-434b-871d-530560d13029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731336020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3731336020
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1934026328
Short name T136
Test name
Test status
Simulation time 118414454 ps
CPU time 1.06 seconds
Started Mar 24 12:43:37 PM PDT 24
Finished Mar 24 12:43:38 PM PDT 24
Peak memory 200756 kb
Host smart-f25e3ea5-81dd-4d6c-89e7-8d08a2684d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934026328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1934026328
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1040746462
Short name T407
Test name
Test status
Simulation time 249703985 ps
CPU time 1.47 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:41 PM PDT 24
Peak memory 201004 kb
Host smart-8cf8aefa-f44c-42cd-903d-d1502291991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040746462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1040746462
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.4060909821
Short name T530
Test name
Test status
Simulation time 6054332083 ps
CPU time 26.24 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 201224 kb
Host smart-38670e77-ba7f-4643-9a3a-2e4a61b6fbbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060909821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.4060909821
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.503499222
Short name T462
Test name
Test status
Simulation time 375750315 ps
CPU time 1.99 seconds
Started Mar 24 12:43:34 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 200932 kb
Host smart-bab2e682-857b-48ec-afd8-dd8cb52e4bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503499222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.503499222
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2346612721
Short name T176
Test name
Test status
Simulation time 85666390 ps
CPU time 0.89 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 200888 kb
Host smart-08af54a6-8a8e-4849-9da6-9ff9657b2650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346612721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2346612721
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2451542982
Short name T518
Test name
Test status
Simulation time 127736343 ps
CPU time 0.9 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:34 PM PDT 24
Peak memory 200692 kb
Host smart-24cfc307-606a-422d-b959-a62b45657e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451542982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2451542982
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1584948883
Short name T296
Test name
Test status
Simulation time 1231866242 ps
CPU time 5.86 seconds
Started Mar 24 12:43:40 PM PDT 24
Finished Mar 24 12:43:46 PM PDT 24
Peak memory 222548 kb
Host smart-af497849-67ac-4b39-a058-1b4891eae766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584948883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1584948883
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2687238525
Short name T284
Test name
Test status
Simulation time 245870275 ps
CPU time 1.05 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 218200 kb
Host smart-2d6fc44b-4af2-47af-9d00-058d61f90f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687238525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2687238525
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1742816259
Short name T229
Test name
Test status
Simulation time 130737800 ps
CPU time 0.78 seconds
Started Mar 24 12:43:53 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 200764 kb
Host smart-8832b57e-e592-48e5-b08b-b9bf2535ea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742816259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1742816259
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2719297445
Short name T306
Test name
Test status
Simulation time 1530008640 ps
CPU time 6.11 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:42 PM PDT 24
Peak memory 200960 kb
Host smart-527604e7-2960-44cd-9853-d780ef5cbb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719297445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2719297445
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2530827525
Short name T395
Test name
Test status
Simulation time 111823443 ps
CPU time 1.18 seconds
Started Mar 24 12:43:48 PM PDT 24
Finished Mar 24 12:43:50 PM PDT 24
Peak memory 201076 kb
Host smart-5c6ea89b-e2dc-4fa6-ab07-97e5953c8c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530827525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2530827525
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2215080292
Short name T309
Test name
Test status
Simulation time 8102962750 ps
CPU time 28.93 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 209316 kb
Host smart-1c15a268-ed52-4341-91e6-912e33fa3109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215080292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2215080292
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.185997359
Short name T170
Test name
Test status
Simulation time 543609443 ps
CPU time 2.75 seconds
Started Mar 24 12:43:30 PM PDT 24
Finished Mar 24 12:43:43 PM PDT 24
Peak memory 200880 kb
Host smart-61e87307-b566-4cd5-9d27-dc4401661d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185997359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.185997359
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2993827421
Short name T159
Test name
Test status
Simulation time 141951227 ps
CPU time 1.29 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:43:48 PM PDT 24
Peak memory 200784 kb
Host smart-1d96cce6-b3b6-446f-9010-968982178987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993827421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2993827421
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1703937859
Short name T359
Test name
Test status
Simulation time 64451209 ps
CPU time 0.74 seconds
Started Mar 24 12:43:53 PM PDT 24
Finished Mar 24 12:43:56 PM PDT 24
Peak memory 200784 kb
Host smart-8d066271-9052-4f60-9fa3-bcb2589259b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703937859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1703937859
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2113401543
Short name T38
Test name
Test status
Simulation time 1220128790 ps
CPU time 5.59 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:43:52 PM PDT 24
Peak memory 222692 kb
Host smart-22f3a697-afdf-4ae5-ab2d-e5187a96a435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113401543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2113401543
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2740243711
Short name T265
Test name
Test status
Simulation time 243409981 ps
CPU time 1.16 seconds
Started Mar 24 12:43:54 PM PDT 24
Finished Mar 24 12:43:56 PM PDT 24
Peak memory 218160 kb
Host smart-7ebd1fb6-7c2d-4fc2-b829-3062fd14d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740243711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2740243711
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2499251504
Short name T420
Test name
Test status
Simulation time 98661671 ps
CPU time 0.78 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:43:47 PM PDT 24
Peak memory 200688 kb
Host smart-fc95f5ca-b10c-4a55-9067-77333321815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499251504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2499251504
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1684314415
Short name T335
Test name
Test status
Simulation time 877071675 ps
CPU time 4.5 seconds
Started Mar 24 12:43:53 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 201008 kb
Host smart-0443d2e1-a111-4b49-8e79-e0d430582560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684314415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1684314415
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1614521069
Short name T192
Test name
Test status
Simulation time 142829240 ps
CPU time 1.06 seconds
Started Mar 24 12:43:45 PM PDT 24
Finished Mar 24 12:43:46 PM PDT 24
Peak memory 200820 kb
Host smart-09cffcfc-d839-48d4-a6f1-23e7e4e4e846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614521069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1614521069
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.76405149
Short name T277
Test name
Test status
Simulation time 121985159 ps
CPU time 1.17 seconds
Started Mar 24 12:43:53 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 201088 kb
Host smart-ca02772a-709e-4826-aa11-30570088f530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76405149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.76405149
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.4098900145
Short name T351
Test name
Test status
Simulation time 2341261730 ps
CPU time 10.34 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:45 PM PDT 24
Peak memory 209316 kb
Host smart-ea3a3055-259c-446d-8b7e-dc465194471d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098900145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.4098900145
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.194928629
Short name T203
Test name
Test status
Simulation time 139189782 ps
CPU time 1.85 seconds
Started Mar 24 12:43:38 PM PDT 24
Finished Mar 24 12:43:44 PM PDT 24
Peak memory 201220 kb
Host smart-f61005f9-cd56-414a-bd8d-5fbdc9754777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194928629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.194928629
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.822883688
Short name T488
Test name
Test status
Simulation time 79831140 ps
CPU time 0.86 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 200856 kb
Host smart-9c597c54-e3d0-446b-b3e9-8f92b35dd50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822883688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.822883688
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.663126896
Short name T287
Test name
Test status
Simulation time 71073452 ps
CPU time 0.78 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:54 PM PDT 24
Peak memory 200668 kb
Host smart-7eebc3d6-94f8-4955-82a6-46be84600261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663126896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.663126896
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3150466069
Short name T31
Test name
Test status
Simulation time 1226798142 ps
CPU time 5.54 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 218004 kb
Host smart-0f264cb9-1898-4a67-9c3e-b6306fa49a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150466069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3150466069
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2376472996
Short name T352
Test name
Test status
Simulation time 244914747 ps
CPU time 1.06 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:53 PM PDT 24
Peak memory 218236 kb
Host smart-5fc68c07-91cc-4053-b58c-eac83b506c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376472996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2376472996
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2336280916
Short name T22
Test name
Test status
Simulation time 95995417 ps
CPU time 0.8 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:40 PM PDT 24
Peak memory 200628 kb
Host smart-636e17ac-026d-49d6-ae6a-33d7ba244036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336280916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2336280916
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3107089136
Short name T131
Test name
Test status
Simulation time 1559468089 ps
CPU time 6.25 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:49 PM PDT 24
Peak memory 201120 kb
Host smart-74c24d66-12e3-4161-83d3-c7ecb12780a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107089136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3107089136
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.603015721
Short name T490
Test name
Test status
Simulation time 175241899 ps
CPU time 1.16 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 200756 kb
Host smart-efb09a92-6c6f-47c3-a02a-a2ee7021dec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603015721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.603015721
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.676022951
Short name T484
Test name
Test status
Simulation time 121325789 ps
CPU time 1.34 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:43:58 PM PDT 24
Peak memory 201008 kb
Host smart-5cb1b6df-d1da-4926-b0ca-ea7d61217b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676022951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.676022951
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2250078407
Short name T507
Test name
Test status
Simulation time 230114155 ps
CPU time 1.34 seconds
Started Mar 24 12:43:36 PM PDT 24
Finished Mar 24 12:43:37 PM PDT 24
Peak memory 200760 kb
Host smart-f7b7a7bc-2926-43e5-b701-52433b6b1d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250078407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2250078407
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2409597674
Short name T145
Test name
Test status
Simulation time 332914285 ps
CPU time 2.05 seconds
Started Mar 24 12:43:24 PM PDT 24
Finished Mar 24 12:43:31 PM PDT 24
Peak memory 200932 kb
Host smart-815ac5ed-c146-4480-8b0c-5e36f74af558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409597674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2409597674
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1144156952
Short name T204
Test name
Test status
Simulation time 163947407 ps
CPU time 1.29 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 201044 kb
Host smart-8d8e3df9-0954-440f-8e33-529a978e724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144156952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1144156952
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3689937357
Short name T473
Test name
Test status
Simulation time 76190538 ps
CPU time 0.79 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:43:59 PM PDT 24
Peak memory 200728 kb
Host smart-1b19e611-310c-4d78-b4b7-f6c8b3fc42f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689937357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3689937357
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1906898977
Short name T39
Test name
Test status
Simulation time 1877915770 ps
CPU time 6.8 seconds
Started Mar 24 12:43:45 PM PDT 24
Finished Mar 24 12:43:52 PM PDT 24
Peak memory 218524 kb
Host smart-6334526e-2f5e-464e-9300-31b9f654c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906898977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1906898977
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2995596664
Short name T141
Test name
Test status
Simulation time 243577129 ps
CPU time 1.17 seconds
Started Mar 24 12:43:32 PM PDT 24
Finished Mar 24 12:43:34 PM PDT 24
Peak memory 218164 kb
Host smart-e3f81baa-194c-44a2-be6c-81ddbdbf148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995596664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2995596664
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2386468893
Short name T398
Test name
Test status
Simulation time 105981259 ps
CPU time 0.79 seconds
Started Mar 24 12:43:43 PM PDT 24
Finished Mar 24 12:43:44 PM PDT 24
Peak memory 200756 kb
Host smart-d8ba5633-5e99-4b24-a50a-97c4a05a0db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386468893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2386468893
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1807402166
Short name T193
Test name
Test status
Simulation time 776781327 ps
CPU time 3.94 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 201012 kb
Host smart-63b7be63-29d7-4f86-b1b7-fb3b3a7126c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807402166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1807402166
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3403857530
Short name T416
Test name
Test status
Simulation time 155955520 ps
CPU time 1.13 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:53 PM PDT 24
Peak memory 200924 kb
Host smart-a69d26a4-50b7-43a1-bc98-46da4c3e3bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403857530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3403857530
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2234435661
Short name T215
Test name
Test status
Simulation time 204023039 ps
CPU time 1.35 seconds
Started Mar 24 12:43:37 PM PDT 24
Finished Mar 24 12:43:38 PM PDT 24
Peak memory 200956 kb
Host smart-9e893a05-5746-4164-93c4-97a5b73d93fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234435661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2234435661
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.285868472
Short name T363
Test name
Test status
Simulation time 264409734 ps
CPU time 1.65 seconds
Started Mar 24 12:43:37 PM PDT 24
Finished Mar 24 12:43:39 PM PDT 24
Peak memory 201008 kb
Host smart-b7b95efd-88cf-4cc2-a56d-4d0ed5202a08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285868472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.285868472
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.643766135
Short name T155
Test name
Test status
Simulation time 120902660 ps
CPU time 1.54 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:40 PM PDT 24
Peak memory 209176 kb
Host smart-0d0628dd-de18-4d1d-ab27-d6aad5b7518c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643766135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.643766135
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1655526748
Short name T360
Test name
Test status
Simulation time 110855619 ps
CPU time 0.99 seconds
Started Mar 24 12:43:48 PM PDT 24
Finished Mar 24 12:43:49 PM PDT 24
Peak memory 200784 kb
Host smart-769e3d9d-7656-449c-8f93-0b66125cc5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655526748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1655526748
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1477442807
Short name T350
Test name
Test status
Simulation time 106523285 ps
CPU time 0.88 seconds
Started Mar 24 12:43:26 PM PDT 24
Finished Mar 24 12:43:27 PM PDT 24
Peak memory 201004 kb
Host smart-20638b32-c190-4435-a9b7-1a703420ed8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477442807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1477442807
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2395153680
Short name T446
Test name
Test status
Simulation time 1221702680 ps
CPU time 5.26 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:19 PM PDT 24
Peak memory 218476 kb
Host smart-d9637cad-eb7f-489d-b7a2-7e58dddf0648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395153680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2395153680
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.638782583
Short name T169
Test name
Test status
Simulation time 243193623 ps
CPU time 1.18 seconds
Started Mar 24 12:43:28 PM PDT 24
Finished Mar 24 12:43:31 PM PDT 24
Peak memory 218148 kb
Host smart-13008c73-b3c0-43bf-ac84-0d57205f3479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638782583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.638782583
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1137474880
Short name T4
Test name
Test status
Simulation time 147905674 ps
CPU time 0.84 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 200680 kb
Host smart-5087bb3d-fe1e-46da-bcae-a5742896164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137474880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1137474880
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2510182162
Short name T248
Test name
Test status
Simulation time 893997431 ps
CPU time 4.16 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:21 PM PDT 24
Peak memory 200932 kb
Host smart-c00b4e1a-c369-47b5-8e0f-2468c7999ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510182162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2510182162
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2699600846
Short name T75
Test name
Test status
Simulation time 16608866941 ps
CPU time 24.78 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:37 PM PDT 24
Peak memory 217812 kb
Host smart-c5fd46a7-f113-4971-9c7c-c8eb721bfed7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699600846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2699600846
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3233992869
Short name T79
Test name
Test status
Simulation time 108199083 ps
CPU time 0.99 seconds
Started Mar 24 12:43:09 PM PDT 24
Finished Mar 24 12:43:10 PM PDT 24
Peak memory 200820 kb
Host smart-889c2d6d-8fe9-46e8-92d0-a71da441b7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233992869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3233992869
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2208855872
Short name T238
Test name
Test status
Simulation time 246280926 ps
CPU time 1.45 seconds
Started Mar 24 12:43:21 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 201064 kb
Host smart-08c54d4c-063e-461c-96a6-2845afedcc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208855872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2208855872
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2284732543
Short name T90
Test name
Test status
Simulation time 7000549564 ps
CPU time 29.34 seconds
Started Mar 24 12:43:17 PM PDT 24
Finished Mar 24 12:43:47 PM PDT 24
Peak memory 209356 kb
Host smart-0e99ca8b-75ac-4b2d-b191-60021cc79018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284732543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2284732543
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2187800788
Short name T11
Test name
Test status
Simulation time 124831662 ps
CPU time 1.63 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 200872 kb
Host smart-c17d78f0-4018-44d5-8c14-732b16d9a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187800788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2187800788
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1737127352
Short name T89
Test name
Test status
Simulation time 136650252 ps
CPU time 1.16 seconds
Started Mar 24 12:43:22 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 200796 kb
Host smart-6b20fc15-d784-4caf-aaa3-b619b6a448bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737127352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1737127352
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1465884106
Short name T527
Test name
Test status
Simulation time 78166160 ps
CPU time 0.81 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:51 PM PDT 24
Peak memory 200768 kb
Host smart-8d935da5-1f3f-4276-9e87-3179f52ae383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465884106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1465884106
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2308691522
Short name T35
Test name
Test status
Simulation time 2362337410 ps
CPU time 8.32 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:43 PM PDT 24
Peak memory 218380 kb
Host smart-500bf514-5565-4724-af29-e6108899a2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308691522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2308691522
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.281803662
Short name T443
Test name
Test status
Simulation time 244446496 ps
CPU time 1.09 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 218144 kb
Host smart-ac430a54-954d-47d5-b6e2-16b2d5ffd1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281803662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.281803662
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.4035841036
Short name T315
Test name
Test status
Simulation time 84240378 ps
CPU time 0.8 seconds
Started Mar 24 12:43:40 PM PDT 24
Finished Mar 24 12:43:40 PM PDT 24
Peak memory 200684 kb
Host smart-7aa81b34-914c-47fc-9112-2a1b4c01c03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035841036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4035841036
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2655527309
Short name T323
Test name
Test status
Simulation time 875153125 ps
CPU time 4.38 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 201068 kb
Host smart-fffb8efc-1b5c-462d-939e-8cbb09bdb3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655527309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2655527309
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1289306014
Short name T280
Test name
Test status
Simulation time 108915482 ps
CPU time 1.05 seconds
Started Mar 24 12:43:56 PM PDT 24
Finished Mar 24 12:43:58 PM PDT 24
Peak memory 200912 kb
Host smart-055dbb64-be9a-47bb-929c-9a787bf09b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289306014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1289306014
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.390188309
Short name T532
Test name
Test status
Simulation time 201701662 ps
CPU time 1.39 seconds
Started Mar 24 12:43:59 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 201008 kb
Host smart-ac588da4-1faa-4312-aa06-174841943c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390188309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.390188309
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3501361270
Short name T405
Test name
Test status
Simulation time 338707184 ps
CPU time 2.27 seconds
Started Mar 24 12:43:34 PM PDT 24
Finished Mar 24 12:43:37 PM PDT 24
Peak memory 200960 kb
Host smart-36375fc8-68ab-45a8-9c7e-c60950973271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501361270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3501361270
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.213817943
Short name T421
Test name
Test status
Simulation time 123155606 ps
CPU time 0.99 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:51 PM PDT 24
Peak memory 200872 kb
Host smart-85e04cf2-229f-41a7-a392-148713097758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213817943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.213817943
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1701120328
Short name T171
Test name
Test status
Simulation time 67575523 ps
CPU time 0.75 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:53 PM PDT 24
Peak memory 200660 kb
Host smart-f6c75bf8-35cf-4b98-a48f-380b6d73fef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701120328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1701120328
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3994849926
Short name T340
Test name
Test status
Simulation time 2363763816 ps
CPU time 8.38 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 218704 kb
Host smart-00870319-2431-4bbb-a757-1ad24d708e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994849926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3994849926
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4248042021
Short name T522
Test name
Test status
Simulation time 246831097 ps
CPU time 1.08 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:43:52 PM PDT 24
Peak memory 218080 kb
Host smart-aeb88a13-a1fd-4a88-90ae-dc945fa8fe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248042021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4248042021
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1424641302
Short name T261
Test name
Test status
Simulation time 102867217 ps
CPU time 0.76 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:50 PM PDT 24
Peak memory 200680 kb
Host smart-be2195b0-769c-403d-bc47-5d10d8800a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424641302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1424641302
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1226277025
Short name T411
Test name
Test status
Simulation time 1899704382 ps
CPU time 6.84 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 200964 kb
Host smart-b260190f-69e2-45a6-a5e5-95750a7b6d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226277025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1226277025
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3133964801
Short name T271
Test name
Test status
Simulation time 184150463 ps
CPU time 1.27 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:53 PM PDT 24
Peak memory 200848 kb
Host smart-fb070be7-1170-44cb-8ace-aa8b19770ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133964801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3133964801
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2087210613
Short name T179
Test name
Test status
Simulation time 203237465 ps
CPU time 1.36 seconds
Started Mar 24 12:44:01 PM PDT 24
Finished Mar 24 12:44:02 PM PDT 24
Peak memory 201120 kb
Host smart-edef642c-700c-4514-a51b-a9dd42b3d0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087210613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2087210613
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3231867611
Short name T101
Test name
Test status
Simulation time 3864985991 ps
CPU time 13.32 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:48 PM PDT 24
Peak memory 201056 kb
Host smart-59fad2d5-e80d-4ccc-9601-b8b8473e923b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231867611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3231867611
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1353015270
Short name T510
Test name
Test status
Simulation time 303791007 ps
CPU time 1.95 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:01 PM PDT 24
Peak memory 209028 kb
Host smart-42a6b271-6df8-4dc6-8ffa-40b514cc2500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353015270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1353015270
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1148114275
Short name T367
Test name
Test status
Simulation time 182116993 ps
CPU time 1.23 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:51 PM PDT 24
Peak memory 200828 kb
Host smart-05c4b10e-09a3-4e91-8399-4468c7681b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148114275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1148114275
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.4075399134
Short name T40
Test name
Test status
Simulation time 1888596302 ps
CPU time 6.71 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:59 PM PDT 24
Peak memory 217460 kb
Host smart-d33ed758-9af7-449d-b6c9-b77998c443ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075399134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4075399134
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1567220821
Short name T457
Test name
Test status
Simulation time 244151595 ps
CPU time 1.04 seconds
Started Mar 24 12:43:36 PM PDT 24
Finished Mar 24 12:43:37 PM PDT 24
Peak memory 218140 kb
Host smart-1279f320-37de-4f81-b80b-abc86326b640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567220821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1567220821
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3177640323
Short name T401
Test name
Test status
Simulation time 150370007 ps
CPU time 0.81 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:39 PM PDT 24
Peak memory 200980 kb
Host smart-96b1ec86-d560-4110-8ad8-9e5320f3eb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177640323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3177640323
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.4047155881
Short name T233
Test name
Test status
Simulation time 2241585501 ps
CPU time 8.18 seconds
Started Mar 24 12:43:40 PM PDT 24
Finished Mar 24 12:43:48 PM PDT 24
Peak memory 201232 kb
Host smart-cb6c0d2d-1420-4c57-89a7-f43a2b6b08f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047155881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.4047155881
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3195966237
Short name T260
Test name
Test status
Simulation time 107486521 ps
CPU time 1.03 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:53 PM PDT 24
Peak memory 200904 kb
Host smart-caf3b638-199d-4d66-9f82-5f359803dfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195966237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3195966237
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.867229289
Short name T299
Test name
Test status
Simulation time 202690777 ps
CPU time 1.38 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:35 PM PDT 24
Peak memory 201048 kb
Host smart-76bd73ed-7b63-4743-98f2-66791dea8304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867229289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.867229289
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.632184940
Short name T456
Test name
Test status
Simulation time 8523013446 ps
CPU time 30.04 seconds
Started Mar 24 12:43:44 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 209400 kb
Host smart-c833ab34-cace-4e48-80e7-bc6cbb50caab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632184940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.632184940
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2506863172
Short name T267
Test name
Test status
Simulation time 130582350 ps
CPU time 1.57 seconds
Started Mar 24 12:43:50 PM PDT 24
Finished Mar 24 12:43:51 PM PDT 24
Peak memory 209392 kb
Host smart-417fd599-f823-4e96-af90-191859b0ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506863172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2506863172
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3626247317
Short name T463
Test name
Test status
Simulation time 144231370 ps
CPU time 1.3 seconds
Started Mar 24 12:43:48 PM PDT 24
Finished Mar 24 12:43:50 PM PDT 24
Peak memory 200872 kb
Host smart-34a1f8b9-fcff-493c-8f77-21d505553c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626247317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3626247317
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2733937397
Short name T34
Test name
Test status
Simulation time 60748707 ps
CPU time 0.71 seconds
Started Mar 24 12:43:56 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 200764 kb
Host smart-a565b75a-f22c-4a1a-895a-51e10fa55e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733937397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2733937397
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1144559653
Short name T440
Test name
Test status
Simulation time 1878715226 ps
CPU time 7.14 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 217632 kb
Host smart-9c3b828a-77f7-4b40-8784-6533a53486c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144559653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1144559653
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3031348031
Short name T252
Test name
Test status
Simulation time 244191081 ps
CPU time 1.11 seconds
Started Mar 24 12:43:45 PM PDT 24
Finished Mar 24 12:43:46 PM PDT 24
Peak memory 218080 kb
Host smart-2518e780-1c70-44cd-9bfa-8a71c141f27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031348031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3031348031
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3449751301
Short name T533
Test name
Test status
Simulation time 205650036 ps
CPU time 0.94 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 200700 kb
Host smart-1a1bf915-933d-42ae-830f-ca9a5a0c9f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449751301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3449751301
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2675933227
Short name T102
Test name
Test status
Simulation time 1490496038 ps
CPU time 5.97 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:18 PM PDT 24
Peak memory 201000 kb
Host smart-8efcd6b2-64ee-4fa4-b7e4-52731fffa787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675933227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2675933227
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.204001683
Short name T224
Test name
Test status
Simulation time 156696715 ps
CPU time 1.15 seconds
Started Mar 24 12:43:53 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 200868 kb
Host smart-3c6486d7-92cf-4025-81f1-57ead6d0374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204001683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.204001683
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1583418344
Short name T433
Test name
Test status
Simulation time 117901937 ps
CPU time 1.25 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:41 PM PDT 24
Peak memory 200956 kb
Host smart-b03d7b4c-4df8-4382-b4d4-b6ca027ad787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583418344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1583418344
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.300372601
Short name T400
Test name
Test status
Simulation time 4385946924 ps
CPU time 16.95 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 209404 kb
Host smart-e2dc0803-811f-4602-9f21-8ed3c83a1ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300372601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.300372601
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1948438667
Short name T194
Test name
Test status
Simulation time 486543321 ps
CPU time 2.55 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:52 PM PDT 24
Peak memory 200880 kb
Host smart-aece54aa-d2e1-40e9-bc97-862c4823f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948438667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1948438667
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1182009569
Short name T427
Test name
Test status
Simulation time 92355086 ps
CPU time 0.87 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 200896 kb
Host smart-04942236-322b-4015-940c-10ba87fd9f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182009569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1182009569
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2872201255
Short name T470
Test name
Test status
Simulation time 64531571 ps
CPU time 0.77 seconds
Started Mar 24 12:44:06 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 200796 kb
Host smart-8b488062-a3d1-4498-a8bd-dba19c821464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872201255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2872201255
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2359205280
Short name T437
Test name
Test status
Simulation time 1881294591 ps
CPU time 7.55 seconds
Started Mar 24 12:43:50 PM PDT 24
Finished Mar 24 12:43:59 PM PDT 24
Peak memory 217756 kb
Host smart-4b6aa597-6d23-4bf3-bfdf-87bdf27f24ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359205280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2359205280
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.794578969
Short name T344
Test name
Test status
Simulation time 244356705 ps
CPU time 1.08 seconds
Started Mar 24 12:43:50 PM PDT 24
Finished Mar 24 12:43:51 PM PDT 24
Peak memory 218228 kb
Host smart-25a572d0-aadb-4f4b-9416-054bb14dc585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794578969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.794578969
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2710967253
Short name T3
Test name
Test status
Simulation time 211068495 ps
CPU time 0.9 seconds
Started Mar 24 12:43:54 PM PDT 24
Finished Mar 24 12:43:56 PM PDT 24
Peak memory 200732 kb
Host smart-71b8278a-b2ce-41db-952d-241f3b202c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710967253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2710967253
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1056863842
Short name T316
Test name
Test status
Simulation time 967199724 ps
CPU time 4.75 seconds
Started Mar 24 12:43:56 PM PDT 24
Finished Mar 24 12:44:01 PM PDT 24
Peak memory 201076 kb
Host smart-ca107fa6-cc26-4d6f-b2d2-964006c9dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056863842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1056863842
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1664137082
Short name T461
Test name
Test status
Simulation time 139873504 ps
CPU time 1.15 seconds
Started Mar 24 12:44:03 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 200924 kb
Host smart-d8bc5bb4-1b9c-4860-a71d-38f0a4a62f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664137082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1664137082
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1649727660
Short name T172
Test name
Test status
Simulation time 128197003 ps
CPU time 1.16 seconds
Started Mar 24 12:43:59 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 200956 kb
Host smart-83eb1b12-c147-4dcb-862f-94fea1782660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649727660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1649727660
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2323277236
Short name T486
Test name
Test status
Simulation time 9671610185 ps
CPU time 34.65 seconds
Started Mar 24 12:43:48 PM PDT 24
Finished Mar 24 12:44:23 PM PDT 24
Peak memory 209300 kb
Host smart-e3525aee-5d0f-46a6-b8da-5e633c736caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323277236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2323277236
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3610748110
Short name T374
Test name
Test status
Simulation time 257203410 ps
CPU time 1.75 seconds
Started Mar 24 12:43:46 PM PDT 24
Finished Mar 24 12:43:48 PM PDT 24
Peak memory 200856 kb
Host smart-1acbac33-48e0-4489-9fc6-fa9a67175c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610748110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3610748110
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1463377677
Short name T46
Test name
Test status
Simulation time 79405988 ps
CPU time 0.8 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:52 PM PDT 24
Peak memory 200904 kb
Host smart-01e5a38d-d8f0-4b63-875c-3079075be5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463377677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1463377677
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.174933109
Short name T410
Test name
Test status
Simulation time 63896819 ps
CPU time 0.74 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:43:56 PM PDT 24
Peak memory 200764 kb
Host smart-b2f535e1-9d31-4cab-9296-1246773721d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174933109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.174933109
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3091122408
Short name T448
Test name
Test status
Simulation time 1899091283 ps
CPU time 8.02 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 222564 kb
Host smart-c8e7e098-5576-4203-8370-0d57af645e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091122408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3091122408
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2781607081
Short name T498
Test name
Test status
Simulation time 244788950 ps
CPU time 1.16 seconds
Started Mar 24 12:43:59 PM PDT 24
Finished Mar 24 12:44:06 PM PDT 24
Peak memory 218308 kb
Host smart-9d0ab95a-4fe4-4cab-9667-ed6275fb7daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781607081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2781607081
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.4255931706
Short name T478
Test name
Test status
Simulation time 111370898 ps
CPU time 0.81 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 200764 kb
Host smart-cef40bcd-deb8-4e23-835b-733fc28ec5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255931706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.4255931706
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.930977056
Short name T157
Test name
Test status
Simulation time 672788894 ps
CPU time 3.89 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 201008 kb
Host smart-b9da3bfc-d826-462f-9a17-97234c28aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930977056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.930977056
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3110820926
Short name T154
Test name
Test status
Simulation time 188897439 ps
CPU time 1.21 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:54 PM PDT 24
Peak memory 200824 kb
Host smart-b9e8077f-fc41-4f4f-b26f-415f1535f517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110820926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3110820926
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1996215234
Short name T430
Test name
Test status
Simulation time 121956884 ps
CPU time 1.16 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 201064 kb
Host smart-13bad94b-adb3-4e0b-bb8a-9fa1cd0f64c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996215234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1996215234
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3587445668
Short name T86
Test name
Test status
Simulation time 4929444727 ps
CPU time 20.27 seconds
Started Mar 24 12:43:47 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 209396 kb
Host smart-f8322160-661a-48ee-b9c2-795a71f1f0e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587445668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3587445668
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1343364708
Short name T160
Test name
Test status
Simulation time 136980930 ps
CPU time 1.75 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:51 PM PDT 24
Peak memory 209060 kb
Host smart-9af816fb-9a32-4507-9a06-07638c028586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343364708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1343364708
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2688303050
Short name T259
Test name
Test status
Simulation time 63663568 ps
CPU time 0.79 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:50 PM PDT 24
Peak memory 200784 kb
Host smart-532ccc85-ae2f-4f65-954f-e3541960d50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688303050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2688303050
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2060905552
Short name T333
Test name
Test status
Simulation time 70614916 ps
CPU time 0.79 seconds
Started Mar 24 12:44:04 PM PDT 24
Finished Mar 24 12:44:05 PM PDT 24
Peak memory 200764 kb
Host smart-ef8a42c3-f306-4261-9efd-c39a263b9467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060905552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2060905552
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1888960450
Short name T348
Test name
Test status
Simulation time 1223620727 ps
CPU time 6.16 seconds
Started Mar 24 12:43:48 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 222572 kb
Host smart-efb08d82-1e6d-47c5-a39c-3822988d859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888960450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1888960450
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2012546813
Short name T288
Test name
Test status
Simulation time 244287085 ps
CPU time 1.13 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:54 PM PDT 24
Peak memory 218164 kb
Host smart-4790e871-7b76-4e3a-ad24-be7505a4033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012546813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2012546813
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3938422263
Short name T214
Test name
Test status
Simulation time 134148958 ps
CPU time 0.81 seconds
Started Mar 24 12:43:50 PM PDT 24
Finished Mar 24 12:43:52 PM PDT 24
Peak memory 200696 kb
Host smart-355f8b5c-ef44-46ca-8eaf-ab8364f08e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938422263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3938422263
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3714184402
Short name T182
Test name
Test status
Simulation time 999710996 ps
CPU time 4.88 seconds
Started Mar 24 12:43:50 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 201124 kb
Host smart-a1fe850a-27ad-4e22-a5f2-b5e434a2d4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714184402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3714184402
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.774121666
Short name T447
Test name
Test status
Simulation time 143694294 ps
CPU time 1.09 seconds
Started Mar 24 12:44:01 PM PDT 24
Finished Mar 24 12:44:02 PM PDT 24
Peak memory 200888 kb
Host smart-d3ea15c3-c0a6-4bcf-8771-444f833c9a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774121666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.774121666
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.893601136
Short name T286
Test name
Test status
Simulation time 253119096 ps
CPU time 1.45 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:54 PM PDT 24
Peak memory 201072 kb
Host smart-75541d68-0609-4d12-b56a-2f735b6524be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893601136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.893601136
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.761283613
Short name T454
Test name
Test status
Simulation time 4335148496 ps
CPU time 21.3 seconds
Started Mar 24 12:43:50 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 209284 kb
Host smart-bf44b45b-43ff-4ed9-bfe5-1e736a02a2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761283613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.761283613
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2993119068
Short name T283
Test name
Test status
Simulation time 167034228 ps
CPU time 1.28 seconds
Started Mar 24 12:43:47 PM PDT 24
Finished Mar 24 12:43:49 PM PDT 24
Peak memory 201068 kb
Host smart-d37d0ec0-2243-47f5-8325-e03d43f1c0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993119068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2993119068
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3129216986
Short name T538
Test name
Test status
Simulation time 61452317 ps
CPU time 0.78 seconds
Started Mar 24 12:44:03 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 200728 kb
Host smart-30c7ac91-bf96-4fd1-985f-a95a5b5e6a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129216986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3129216986
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3146045456
Short name T269
Test name
Test status
Simulation time 243944846 ps
CPU time 1.05 seconds
Started Mar 24 12:44:01 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 218156 kb
Host smart-d6f5b3fb-6bee-4143-9568-ee0218af49b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146045456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3146045456
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2901759432
Short name T384
Test name
Test status
Simulation time 209738054 ps
CPU time 1.01 seconds
Started Mar 24 12:43:59 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 200764 kb
Host smart-fb8cdc39-43b6-44b5-8901-a0eec540747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901759432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2901759432
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2152279851
Short name T464
Test name
Test status
Simulation time 1498965904 ps
CPU time 6.43 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:46 PM PDT 24
Peak memory 201008 kb
Host smart-8af8325f-fe0d-4308-8856-eb7d7efce476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152279851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2152279851
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3809345069
Short name T301
Test name
Test status
Simulation time 107068670 ps
CPU time 1 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 200860 kb
Host smart-1f08de8a-8e9a-4e50-a180-626f6ab5bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809345069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3809345069
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3161419297
Short name T196
Test name
Test status
Simulation time 236620099 ps
CPU time 1.4 seconds
Started Mar 24 12:43:56 PM PDT 24
Finished Mar 24 12:43:58 PM PDT 24
Peak memory 201068 kb
Host smart-7fb627ab-37ca-4c2a-9204-b9597121c990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161419297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3161419297
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2285012881
Short name T423
Test name
Test status
Simulation time 2266223027 ps
CPU time 8.38 seconds
Started Mar 24 12:44:03 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 201196 kb
Host smart-b1977ec8-b664-4501-bcd9-cfff24fae9c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285012881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2285012881
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3546051274
Short name T88
Test name
Test status
Simulation time 254495576 ps
CPU time 1.9 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 200896 kb
Host smart-ea5a14d7-56a3-4516-92f7-7c98caee868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546051274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3546051274
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.195076580
Short name T449
Test name
Test status
Simulation time 124831264 ps
CPU time 1.02 seconds
Started Mar 24 12:43:50 PM PDT 24
Finished Mar 24 12:43:52 PM PDT 24
Peak memory 200880 kb
Host smart-0605a0b5-1b57-461f-b2b4-e20b957b43e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195076580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.195076580
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1711113457
Short name T336
Test name
Test status
Simulation time 78249609 ps
CPU time 0.78 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:10 PM PDT 24
Peak memory 200632 kb
Host smart-27989f06-2cd4-498c-9796-7969f7faca71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711113457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1711113457
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2405625426
Short name T52
Test name
Test status
Simulation time 2352309433 ps
CPU time 7.9 seconds
Started Mar 24 12:44:08 PM PDT 24
Finished Mar 24 12:44:16 PM PDT 24
Peak memory 222588 kb
Host smart-65071a4d-76a6-4c54-8049-a85fcc199ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405625426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2405625426
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3613852804
Short name T292
Test name
Test status
Simulation time 243874706 ps
CPU time 1.11 seconds
Started Mar 24 12:43:57 PM PDT 24
Finished Mar 24 12:43:58 PM PDT 24
Peak memory 218112 kb
Host smart-a1d7ed88-9e35-4916-a0d7-6315b5559309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613852804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3613852804
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4104988397
Short name T21
Test name
Test status
Simulation time 119540136 ps
CPU time 0.83 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 200788 kb
Host smart-b7cd208a-d920-44a9-972c-fcbfc7c4be39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104988397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4104988397
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1850933219
Short name T313
Test name
Test status
Simulation time 1692719111 ps
CPU time 5.77 seconds
Started Mar 24 12:44:01 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 201380 kb
Host smart-9f6b1c85-396f-42ad-9a8f-d54b86206dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850933219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1850933219
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3733197619
Short name T256
Test name
Test status
Simulation time 99442090 ps
CPU time 1.06 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 200880 kb
Host smart-0fdd352d-fe96-4d25-a2a2-c48c797df915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733197619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3733197619
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2043021027
Short name T23
Test name
Test status
Simulation time 112579674 ps
CPU time 1.17 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:51 PM PDT 24
Peak memory 201096 kb
Host smart-a9d51ee6-6ea9-4610-b871-254b418d713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043021027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2043021027
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3840268009
Short name T138
Test name
Test status
Simulation time 14495108382 ps
CPU time 54.08 seconds
Started Mar 24 12:44:03 PM PDT 24
Finished Mar 24 12:44:57 PM PDT 24
Peak memory 210136 kb
Host smart-0b111098-8620-4bf8-9622-50979cd7e5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840268009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3840268009
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2897157733
Short name T364
Test name
Test status
Simulation time 374899978 ps
CPU time 2.4 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:10 PM PDT 24
Peak memory 200840 kb
Host smart-9d79d4d9-ec5f-4b55-bcaa-2ce14b531781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897157733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2897157733
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2584350487
Short name T184
Test name
Test status
Simulation time 209875070 ps
CPU time 1.25 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 200804 kb
Host smart-bb6df746-9650-468e-8297-beec1703744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584350487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2584350487
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2279236820
Short name T258
Test name
Test status
Simulation time 68371439 ps
CPU time 0.83 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 200676 kb
Host smart-7db28f3b-a568-4871-a49f-d89b08bbf391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279236820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2279236820
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1298621628
Short name T253
Test name
Test status
Simulation time 1231249354 ps
CPU time 5.41 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 222624 kb
Host smart-d4c286b6-56da-4da3-8b77-580883d9eb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298621628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1298621628
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2038710648
Short name T408
Test name
Test status
Simulation time 245943913 ps
CPU time 1.03 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 218160 kb
Host smart-7fbbb8ee-d0a5-4302-ae45-c69e6bd47627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038710648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2038710648
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1106154335
Short name T390
Test name
Test status
Simulation time 151985210 ps
CPU time 0.8 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 200772 kb
Host smart-9ad231b3-e86c-4ca3-821e-8a811e57a67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106154335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1106154335
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.355387587
Short name T100
Test name
Test status
Simulation time 1429634581 ps
CPU time 5.1 seconds
Started Mar 24 12:44:05 PM PDT 24
Finished Mar 24 12:44:10 PM PDT 24
Peak memory 201100 kb
Host smart-a7fb2518-7ebf-4649-bf28-f45cf0e90b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355387587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.355387587
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.536438688
Short name T187
Test name
Test status
Simulation time 109110978 ps
CPU time 0.96 seconds
Started Mar 24 12:44:04 PM PDT 24
Finished Mar 24 12:44:05 PM PDT 24
Peak memory 200776 kb
Host smart-935d255b-79e3-47e4-ab9a-f46adb6685c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536438688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.536438688
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1225187701
Short name T282
Test name
Test status
Simulation time 231856183 ps
CPU time 1.38 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:56 PM PDT 24
Peak memory 200968 kb
Host smart-9d80f617-b58c-4334-b5e2-fd835d708208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225187701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1225187701
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1429269285
Short name T475
Test name
Test status
Simulation time 4183859203 ps
CPU time 20.74 seconds
Started Mar 24 12:44:22 PM PDT 24
Finished Mar 24 12:44:43 PM PDT 24
Peak memory 201176 kb
Host smart-8c513496-8c43-4d83-9c30-cf0d938f14b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429269285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1429269285
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1558013492
Short name T295
Test name
Test status
Simulation time 110332121 ps
CPU time 1.48 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:56 PM PDT 24
Peak memory 200916 kb
Host smart-f02e8ac0-0836-4c3e-8427-9e69785e5e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558013492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1558013492
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3227355964
Short name T481
Test name
Test status
Simulation time 149074691 ps
CPU time 1.19 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:53 PM PDT 24
Peak memory 200804 kb
Host smart-e849493b-f923-41b9-be5a-f435a7ff89c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227355964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3227355964
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3781287722
Short name T76
Test name
Test status
Simulation time 89031674 ps
CPU time 0.86 seconds
Started Mar 24 12:43:22 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 200708 kb
Host smart-be27e11d-7078-4231-b281-d6cc49016126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781287722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3781287722
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3206910677
Short name T322
Test name
Test status
Simulation time 1226703767 ps
CPU time 5.44 seconds
Started Mar 24 12:43:18 PM PDT 24
Finished Mar 24 12:43:23 PM PDT 24
Peak memory 218512 kb
Host smart-7acf5abb-ae33-451f-997c-792ba9fb2ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206910677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3206910677
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2109186441
Short name T177
Test name
Test status
Simulation time 244415907 ps
CPU time 1.15 seconds
Started Mar 24 12:43:31 PM PDT 24
Finished Mar 24 12:43:32 PM PDT 24
Peak memory 218200 kb
Host smart-8fffd40a-810d-4d30-a03a-fab8d949383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109186441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2109186441
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.238148326
Short name T212
Test name
Test status
Simulation time 227834127 ps
CPU time 0.97 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 200680 kb
Host smart-bd8ae610-5cb3-4476-8600-be1610765e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238148326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.238148326
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.289131389
Short name T511
Test name
Test status
Simulation time 1320573585 ps
CPU time 5.39 seconds
Started Mar 24 12:43:18 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 200992 kb
Host smart-8d3cacff-663f-4025-8d00-2ef468dbf8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289131389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.289131389
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3129820945
Short name T73
Test name
Test status
Simulation time 16709116479 ps
CPU time 25.94 seconds
Started Mar 24 12:43:25 PM PDT 24
Finished Mar 24 12:43:52 PM PDT 24
Peak memory 217992 kb
Host smart-526ec764-afc8-4f6b-bd00-228b9599ff62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129820945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3129820945
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.121009557
Short name T524
Test name
Test status
Simulation time 105199487 ps
CPU time 0.99 seconds
Started Mar 24 12:43:30 PM PDT 24
Finished Mar 24 12:43:31 PM PDT 24
Peak memory 200812 kb
Host smart-cf9e3ff7-716f-4d5b-b0e9-a706c42845ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121009557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.121009557
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1877447162
Short name T9
Test name
Test status
Simulation time 110999880 ps
CPU time 1.18 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 200984 kb
Host smart-11221246-4e7e-4e47-812d-66058ca78ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877447162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1877447162
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3716198407
Short name T216
Test name
Test status
Simulation time 3246061884 ps
CPU time 13.3 seconds
Started Mar 24 12:43:28 PM PDT 24
Finished Mar 24 12:43:42 PM PDT 24
Peak memory 201096 kb
Host smart-b28610b4-1420-4ec7-93b1-4e58dbdd1f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716198407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3716198407
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1442825965
Short name T289
Test name
Test status
Simulation time 460290368 ps
CPU time 2.45 seconds
Started Mar 24 12:43:17 PM PDT 24
Finished Mar 24 12:43:19 PM PDT 24
Peak memory 209240 kb
Host smart-8d9a14d9-585c-4a39-8297-d2b08e666ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442825965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1442825965
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2967588109
Short name T375
Test name
Test status
Simulation time 134899105 ps
CPU time 0.98 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:22 PM PDT 24
Peak memory 200748 kb
Host smart-a3874a77-ec2a-4266-9163-516f9609169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967588109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2967588109
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3248892131
Short name T332
Test name
Test status
Simulation time 59275558 ps
CPU time 0.71 seconds
Started Mar 24 12:44:08 PM PDT 24
Finished Mar 24 12:44:08 PM PDT 24
Peak memory 200796 kb
Host smart-295828db-6480-45d5-b44a-90d0104d5115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248892131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3248892131
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1802244189
Short name T381
Test name
Test status
Simulation time 1225120003 ps
CPU time 5.7 seconds
Started Mar 24 12:43:54 PM PDT 24
Finished Mar 24 12:44:01 PM PDT 24
Peak memory 218556 kb
Host smart-33646749-6aaa-4a3e-b25d-870a19f11de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802244189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1802244189
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.409609182
Short name T373
Test name
Test status
Simulation time 243954349 ps
CPU time 1.04 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:43:58 PM PDT 24
Peak memory 218268 kb
Host smart-170d41b9-456d-4767-8577-598070bf5f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409609182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.409609182
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2569539653
Short name T326
Test name
Test status
Simulation time 113863987 ps
CPU time 0.81 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 200648 kb
Host smart-bed8b5f6-908d-457e-9674-ba68eafff725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569539653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2569539653
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.478641508
Short name T123
Test name
Test status
Simulation time 1404509025 ps
CPU time 5.35 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:08 PM PDT 24
Peak memory 201044 kb
Host smart-2a396d32-8428-4c7f-87df-471ceec30f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478641508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.478641508
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2606939287
Short name T245
Test name
Test status
Simulation time 155489797 ps
CPU time 1.1 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 200776 kb
Host smart-67a30e45-01e9-48fa-a4a7-78e3a2122960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606939287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2606939287
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.389018226
Short name T441
Test name
Test status
Simulation time 201790936 ps
CPU time 1.32 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 201020 kb
Host smart-27d0604c-24c5-47fc-9ae3-bed9870500e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389018226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.389018226
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2288407799
Short name T58
Test name
Test status
Simulation time 7249303702 ps
CPU time 26.22 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:33 PM PDT 24
Peak memory 209324 kb
Host smart-51e5c5dc-ef0f-4602-9b93-2abe7e12e085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288407799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2288407799
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2685157541
Short name T355
Test name
Test status
Simulation time 345620604 ps
CPU time 1.87 seconds
Started Mar 24 12:43:57 PM PDT 24
Finished Mar 24 12:44:00 PM PDT 24
Peak memory 200944 kb
Host smart-4e94f4cc-d404-4a5a-b8b8-45430eb655f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685157541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2685157541
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1421228964
Short name T45
Test name
Test status
Simulation time 262741467 ps
CPU time 1.48 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 200932 kb
Host smart-b72c56da-c3ad-463d-8186-c3fc36992ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421228964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1421228964
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.81559746
Short name T339
Test name
Test status
Simulation time 72067933 ps
CPU time 0.82 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 200692 kb
Host smart-b61ba7d0-80d1-4826-82cd-699f2b87d896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81559746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.81559746
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.4073655743
Short name T6
Test name
Test status
Simulation time 1223869238 ps
CPU time 5.73 seconds
Started Mar 24 12:44:32 PM PDT 24
Finished Mar 24 12:44:38 PM PDT 24
Peak memory 218076 kb
Host smart-0d7b646c-8165-4152-a6ed-429f3d81a9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073655743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.4073655743
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1308986812
Short name T310
Test name
Test status
Simulation time 244661613 ps
CPU time 1.12 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:43:57 PM PDT 24
Peak memory 218196 kb
Host smart-df6ab47f-0ebe-4c55-a315-ac6f0d786e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308986812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1308986812
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2350082295
Short name T496
Test name
Test status
Simulation time 144738253 ps
CPU time 0.87 seconds
Started Mar 24 12:44:27 PM PDT 24
Finished Mar 24 12:44:28 PM PDT 24
Peak memory 200696 kb
Host smart-01192202-cd4c-4a0b-9a2d-794eae4402ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350082295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2350082295
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.302108302
Short name T312
Test name
Test status
Simulation time 1300378473 ps
CPU time 5.08 seconds
Started Mar 24 12:44:03 PM PDT 24
Finished Mar 24 12:44:09 PM PDT 24
Peak memory 201108 kb
Host smart-078f87b3-4ae2-4818-8444-88266d654fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302108302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.302108302
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.4237379250
Short name T386
Test name
Test status
Simulation time 164112617 ps
CPU time 1.16 seconds
Started Mar 24 12:43:56 PM PDT 24
Finished Mar 24 12:43:58 PM PDT 24
Peak memory 200780 kb
Host smart-09b07651-9109-4bdd-af96-17dc0104fa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237379250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.4237379250
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2841703057
Short name T403
Test name
Test status
Simulation time 119456812 ps
CPU time 1.12 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:43:58 PM PDT 24
Peak memory 201016 kb
Host smart-42293e4a-632c-41a6-98db-4bd045190276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841703057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2841703057
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.566676038
Short name T219
Test name
Test status
Simulation time 1178871811 ps
CPU time 5.2 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 201044 kb
Host smart-88dafbb7-932f-4f79-b88c-0c0c833154db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566676038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.566676038
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.4238607691
Short name T228
Test name
Test status
Simulation time 124864823 ps
CPU time 1.54 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:09 PM PDT 24
Peak memory 209068 kb
Host smart-9898e9aa-7027-4575-871b-8c2b6e15b9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238607691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.4238607691
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2765048220
Short name T417
Test name
Test status
Simulation time 95624672 ps
CPU time 0.92 seconds
Started Mar 24 12:43:54 PM PDT 24
Finished Mar 24 12:43:56 PM PDT 24
Peak memory 200872 kb
Host smart-51bfb854-3e86-49ff-870c-6a289bc209f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765048220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2765048220
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1562753947
Short name T254
Test name
Test status
Simulation time 58996604 ps
CPU time 0.76 seconds
Started Mar 24 12:43:51 PM PDT 24
Finished Mar 24 12:43:53 PM PDT 24
Peak memory 200768 kb
Host smart-7db5da47-4001-4c62-87eb-d6b4fd20671a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562753947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1562753947
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1276164006
Short name T376
Test name
Test status
Simulation time 243817668 ps
CPU time 1.08 seconds
Started Mar 24 12:44:17 PM PDT 24
Finished Mar 24 12:44:18 PM PDT 24
Peak memory 218176 kb
Host smart-1aeee0ce-221f-4e5b-969c-01cb38a754c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276164006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1276164006
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.215953041
Short name T231
Test name
Test status
Simulation time 75955707 ps
CPU time 0.72 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:08 PM PDT 24
Peak memory 200776 kb
Host smart-e27e0b64-cd22-4fa8-9ee0-897d808f5149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215953041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.215953041
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1497854619
Short name T197
Test name
Test status
Simulation time 1512616454 ps
CPU time 5.67 seconds
Started Mar 24 12:43:56 PM PDT 24
Finished Mar 24 12:44:02 PM PDT 24
Peak memory 200968 kb
Host smart-8cfcb45f-8b3e-4a4e-9fb5-3cc52307dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497854619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1497854619
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2679096468
Short name T175
Test name
Test status
Simulation time 169623269 ps
CPU time 1.12 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:08 PM PDT 24
Peak memory 200900 kb
Host smart-3b61a89e-cedb-4d45-83ba-f28d1a874efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679096468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2679096468
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.26373732
Short name T444
Test name
Test status
Simulation time 204525096 ps
CPU time 1.34 seconds
Started Mar 24 12:44:05 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 201000 kb
Host smart-c0ec2355-e907-4b17-a5fa-5e452e40285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26373732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.26373732
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3540292091
Short name T438
Test name
Test status
Simulation time 5714862909 ps
CPU time 18.92 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:21 PM PDT 24
Peak memory 201148 kb
Host smart-d0442096-f7f3-447a-b684-fa2f9662805d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540292091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3540292091
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3006024128
Short name T500
Test name
Test status
Simulation time 388073895 ps
CPU time 2.12 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:01 PM PDT 24
Peak memory 200952 kb
Host smart-397f1e0a-875d-47b2-91ad-06b96cb56272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006024128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3006024128
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1298204003
Short name T230
Test name
Test status
Simulation time 120780667 ps
CPU time 1.02 seconds
Started Mar 24 12:44:04 PM PDT 24
Finished Mar 24 12:44:05 PM PDT 24
Peak memory 200860 kb
Host smart-fb7c44e6-142f-4ac3-8dd3-cafb2e809d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298204003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1298204003
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3636897846
Short name T502
Test name
Test status
Simulation time 64692363 ps
CPU time 0.77 seconds
Started Mar 24 12:44:19 PM PDT 24
Finished Mar 24 12:44:20 PM PDT 24
Peak memory 200776 kb
Host smart-585bc5a1-2b2f-4e71-b944-d15b6df715c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636897846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3636897846
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1147153676
Short name T318
Test name
Test status
Simulation time 1904963886 ps
CPU time 7.61 seconds
Started Mar 24 12:44:04 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 218580 kb
Host smart-da02319f-bcbc-4135-9c19-a2642b0a245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147153676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1147153676
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3608367232
Short name T514
Test name
Test status
Simulation time 245204276 ps
CPU time 1.17 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 218188 kb
Host smart-1bea30f9-04d3-479f-9009-f6c4c1a6459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608367232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3608367232
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1345727708
Short name T234
Test name
Test status
Simulation time 148485209 ps
CPU time 0.92 seconds
Started Mar 24 12:44:00 PM PDT 24
Finished Mar 24 12:44:02 PM PDT 24
Peak memory 200780 kb
Host smart-7042c54f-16f9-4918-a17b-faa018f8a130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345727708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1345727708
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2930547894
Short name T236
Test name
Test status
Simulation time 866752437 ps
CPU time 4.69 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 201012 kb
Host smart-f4307f2f-8fcd-4a56-add4-bb3b99ddd830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930547894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2930547894
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1646618804
Short name T200
Test name
Test status
Simulation time 160120215 ps
CPU time 1.08 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:08 PM PDT 24
Peak memory 200788 kb
Host smart-77c9ba7c-d11f-4b14-8c37-f6cf3d6b65ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646618804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1646618804
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.4054375122
Short name T337
Test name
Test status
Simulation time 197774898 ps
CPU time 1.38 seconds
Started Mar 24 12:43:55 PM PDT 24
Finished Mar 24 12:44:01 PM PDT 24
Peak memory 201068 kb
Host smart-654758fd-dba0-44be-a06c-46955541dda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054375122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.4054375122
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3733752335
Short name T281
Test name
Test status
Simulation time 7826629753 ps
CPU time 26.66 seconds
Started Mar 24 12:44:03 PM PDT 24
Finished Mar 24 12:44:30 PM PDT 24
Peak memory 209296 kb
Host smart-5d1874d4-c9e6-410c-a39e-22f157154a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733752335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3733752335
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.927990908
Short name T531
Test name
Test status
Simulation time 140649710 ps
CPU time 1.81 seconds
Started Mar 24 12:44:28 PM PDT 24
Finished Mar 24 12:44:30 PM PDT 24
Peak memory 209252 kb
Host smart-53ec1547-f9ae-4879-b3ec-8d57a3ca3070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927990908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.927990908
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3566392732
Short name T515
Test name
Test status
Simulation time 87704282 ps
CPU time 0.8 seconds
Started Mar 24 12:44:17 PM PDT 24
Finished Mar 24 12:44:18 PM PDT 24
Peak memory 200896 kb
Host smart-e36196ee-294c-4d05-9b41-02a284486541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566392732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3566392732
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2714601396
Short name T199
Test name
Test status
Simulation time 80615890 ps
CPU time 0.83 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 200744 kb
Host smart-b27e3d98-4f25-4351-bb78-f2a0a593b865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714601396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2714601396
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.860204897
Short name T32
Test name
Test status
Simulation time 1897333234 ps
CPU time 7.39 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:20 PM PDT 24
Peak memory 218636 kb
Host smart-774c5aea-ed8e-4d1a-8831-b3d587ed85ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860204897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.860204897
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.73907289
Short name T523
Test name
Test status
Simulation time 244152443 ps
CPU time 1.11 seconds
Started Mar 24 12:44:00 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 218232 kb
Host smart-4e5b705d-0c13-4ba1-aa81-75ff6676d281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73907289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.73907289
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.997953209
Short name T303
Test name
Test status
Simulation time 88233729 ps
CPU time 0.77 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 200684 kb
Host smart-cb5b249e-7948-4b45-8fb7-758110087e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997953209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.997953209
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1906478521
Short name T43
Test name
Test status
Simulation time 1035411303 ps
CPU time 5.18 seconds
Started Mar 24 12:44:06 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 201012 kb
Host smart-89aff1f2-96ab-45c4-a396-a4b258769867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906478521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1906478521
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1304512250
Short name T195
Test name
Test status
Simulation time 103815265 ps
CPU time 1.05 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 200904 kb
Host smart-a705e00d-63e5-4e11-91d5-a602d4727635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304512250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1304512250
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3728113819
Short name T387
Test name
Test status
Simulation time 121533654 ps
CPU time 1.27 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 201084 kb
Host smart-d6667ec7-e09a-4898-8774-55b34d2aeef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728113819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3728113819
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2723175675
Short name T505
Test name
Test status
Simulation time 6644246792 ps
CPU time 27.94 seconds
Started Mar 24 12:44:17 PM PDT 24
Finished Mar 24 12:44:45 PM PDT 24
Peak memory 201220 kb
Host smart-0da21fe4-2d81-4be8-9fac-96b0d1a91287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723175675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2723175675
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3467745711
Short name T472
Test name
Test status
Simulation time 306458732 ps
CPU time 2.25 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 209164 kb
Host smart-867087c4-de88-4c73-bec4-3ceff43fed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467745711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3467745711
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.4173933031
Short name T391
Test name
Test status
Simulation time 120946814 ps
CPU time 1.12 seconds
Started Mar 24 12:44:06 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 200908 kb
Host smart-5889a451-3040-4739-8177-f71476c0b6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173933031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4173933031
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.159829770
Short name T142
Test name
Test status
Simulation time 70856419 ps
CPU time 0.74 seconds
Started Mar 24 12:44:08 PM PDT 24
Finished Mar 24 12:44:09 PM PDT 24
Peak memory 200772 kb
Host smart-9df7e523-7f01-40c3-aeca-29bbc7de5449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159829770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.159829770
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1793884896
Short name T26
Test name
Test status
Simulation time 1233286829 ps
CPU time 6.03 seconds
Started Mar 24 12:44:05 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 218424 kb
Host smart-f5e00987-b2c3-4486-bf6b-f92be58d1677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793884896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1793884896
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3768807959
Short name T369
Test name
Test status
Simulation time 243742299 ps
CPU time 1.18 seconds
Started Mar 24 12:44:04 PM PDT 24
Finished Mar 24 12:44:06 PM PDT 24
Peak memory 218016 kb
Host smart-4ac032f9-19b9-498c-9642-e57f5cd25361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768807959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3768807959
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1416685908
Short name T78
Test name
Test status
Simulation time 204535659 ps
CPU time 0.98 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 200976 kb
Host smart-6346b8be-1b2b-417c-a7d7-5ed3d64a5f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416685908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1416685908
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1824152781
Short name T487
Test name
Test status
Simulation time 1704418918 ps
CPU time 6.86 seconds
Started Mar 24 12:43:59 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 201124 kb
Host smart-084fbbf5-cea5-4b7a-9d4e-01588f7787d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824152781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1824152781
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3527663457
Short name T146
Test name
Test status
Simulation time 179486455 ps
CPU time 1.19 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 200820 kb
Host smart-f4325aa4-2c5b-4f6d-a43d-66a7bfb53a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527663457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3527663457
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2871383978
Short name T380
Test name
Test status
Simulation time 190031297 ps
CPU time 1.4 seconds
Started Mar 24 12:44:21 PM PDT 24
Finished Mar 24 12:44:23 PM PDT 24
Peak memory 201104 kb
Host smart-d7021f9a-82ff-41e2-a1f4-913941368cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871383978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2871383978
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2611906827
Short name T276
Test name
Test status
Simulation time 1871631755 ps
CPU time 7.3 seconds
Started Mar 24 12:44:04 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 200980 kb
Host smart-7246abd2-63ef-4122-8d46-a132ffddf673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611906827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2611906827
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1335103229
Short name T181
Test name
Test status
Simulation time 391701483 ps
CPU time 2.46 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:10 PM PDT 24
Peak memory 200936 kb
Host smart-076f0abf-5ca5-46ac-ac54-a945566df743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335103229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1335103229
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3672004914
Short name T127
Test name
Test status
Simulation time 218942301 ps
CPU time 1.29 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 201132 kb
Host smart-e3ba3fae-1127-4edc-8a56-514fc2b40253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672004914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3672004914
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3125066584
Short name T307
Test name
Test status
Simulation time 93037910 ps
CPU time 0.87 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 200764 kb
Host smart-32c5892e-d987-4292-b707-2423d9a81b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125066584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3125066584
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1945395562
Short name T82
Test name
Test status
Simulation time 2339085307 ps
CPU time 8.13 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:10 PM PDT 24
Peak memory 218608 kb
Host smart-0fbb8a80-c8d2-4a7b-a5a0-67a543ef7608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945395562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1945395562
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.4230999375
Short name T166
Test name
Test status
Simulation time 244708858 ps
CPU time 1.18 seconds
Started Mar 24 12:44:06 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 218196 kb
Host smart-33508cc9-111a-40d5-9209-f9e486300ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230999375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.4230999375
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3513461224
Short name T412
Test name
Test status
Simulation time 121666156 ps
CPU time 0.81 seconds
Started Mar 24 12:44:03 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 200764 kb
Host smart-c1304f37-ad2f-4080-9fc9-c508922a9c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513461224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3513461224
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3672457849
Short name T536
Test name
Test status
Simulation time 871463954 ps
CPU time 4.78 seconds
Started Mar 24 12:44:05 PM PDT 24
Finished Mar 24 12:44:10 PM PDT 24
Peak memory 201044 kb
Host smart-b7dee0c0-3e15-4516-b40b-058ab7e1b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672457849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3672457849
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3636745367
Short name T240
Test name
Test status
Simulation time 180284113 ps
CPU time 1.2 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 200880 kb
Host smart-bebe4df6-1372-41ab-a09d-3af2b9cab3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636745367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3636745367
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1687495720
Short name T413
Test name
Test status
Simulation time 125955916 ps
CPU time 1.18 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 201084 kb
Host smart-16440d84-bc61-4a40-aedd-2b8691ed5069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687495720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1687495720
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2313721898
Short name T257
Test name
Test status
Simulation time 8037603865 ps
CPU time 35.19 seconds
Started Mar 24 12:44:06 PM PDT 24
Finished Mar 24 12:44:42 PM PDT 24
Peak memory 201088 kb
Host smart-6246264e-3555-4bae-bca3-686795909a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313721898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2313721898
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2081313893
Short name T304
Test name
Test status
Simulation time 122032379 ps
CPU time 1.59 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 200884 kb
Host smart-cf84f7a6-7e06-4a79-a7c9-2e0e998710d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081313893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2081313893
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.4246349793
Short name T362
Test name
Test status
Simulation time 224609611 ps
CPU time 1.34 seconds
Started Mar 24 12:43:56 PM PDT 24
Finished Mar 24 12:43:58 PM PDT 24
Peak memory 200752 kb
Host smart-8ff38d9a-e3b6-4994-a460-bcdfef83e279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246349793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.4246349793
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3255673398
Short name T47
Test name
Test status
Simulation time 71996475 ps
CPU time 0.79 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 200796 kb
Host smart-1415972f-df17-47b5-99dc-961459707593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255673398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3255673398
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2063078411
Short name T379
Test name
Test status
Simulation time 1882461449 ps
CPU time 7.77 seconds
Started Mar 24 12:44:03 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 218492 kb
Host smart-0b24db65-8cd8-4e53-beaf-fbaf47f5972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063078411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2063078411
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.515903553
Short name T185
Test name
Test status
Simulation time 244616764 ps
CPU time 1.12 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 218108 kb
Host smart-bd2ea2ae-fe63-4116-8f40-23d622e5db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515903553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.515903553
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.637694323
Short name T221
Test name
Test status
Simulation time 229952591 ps
CPU time 0.93 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 200752 kb
Host smart-5cc8bcb7-0080-41af-ba18-d7ef761959fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637694323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.637694323
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1011735433
Short name T98
Test name
Test status
Simulation time 1733551613 ps
CPU time 6.53 seconds
Started Mar 24 12:44:01 PM PDT 24
Finished Mar 24 12:44:08 PM PDT 24
Peak memory 201004 kb
Host smart-59885638-035d-4a96-aa11-c3b89025d08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011735433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1011735433
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.491643498
Short name T512
Test name
Test status
Simulation time 112063944 ps
CPU time 1.01 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 200888 kb
Host smart-ee2c1809-c42d-4356-88a6-a6bcdfe134f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491643498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.491643498
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.878255434
Short name T485
Test name
Test status
Simulation time 127317533 ps
CPU time 1.24 seconds
Started Mar 24 12:44:05 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 201024 kb
Host smart-d2a88817-41fc-49a7-b7eb-8a1fa1208f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878255434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.878255434
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.557100449
Short name T482
Test name
Test status
Simulation time 932213794 ps
CPU time 3.77 seconds
Started Mar 24 12:43:53 PM PDT 24
Finished Mar 24 12:43:59 PM PDT 24
Peak memory 201104 kb
Host smart-480f8117-3b4a-4367-a7e9-6afcf552dcbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557100449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.557100449
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2680620034
Short name T167
Test name
Test status
Simulation time 514251655 ps
CPU time 2.78 seconds
Started Mar 24 12:43:59 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 200876 kb
Host smart-27f03d61-5881-4910-88c8-a05db62b3bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680620034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2680620034
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1677971284
Short name T202
Test name
Test status
Simulation time 151611002 ps
CPU time 1.05 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 200896 kb
Host smart-29ddff1e-c600-453e-80c0-cff44dadadb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677971284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1677971284
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.149868479
Short name T246
Test name
Test status
Simulation time 80615227 ps
CPU time 0.82 seconds
Started Mar 24 12:44:02 PM PDT 24
Finished Mar 24 12:44:03 PM PDT 24
Peak memory 200748 kb
Host smart-80fa2729-682a-4161-a2d0-6110fa0f4f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149868479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.149868479
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3584688673
Short name T130
Test name
Test status
Simulation time 1891330880 ps
CPU time 7.38 seconds
Started Mar 24 12:43:58 PM PDT 24
Finished Mar 24 12:44:06 PM PDT 24
Peak memory 218264 kb
Host smart-6a13993c-46e2-444f-afc5-71eab6b9353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584688673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3584688673
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2462006499
Short name T278
Test name
Test status
Simulation time 244233677 ps
CPU time 1.12 seconds
Started Mar 24 12:44:20 PM PDT 24
Finished Mar 24 12:44:21 PM PDT 24
Peak memory 218184 kb
Host smart-63e6751c-68d1-4e7d-9bef-bdb9649a74bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462006499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2462006499
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3470594734
Short name T20
Test name
Test status
Simulation time 148701088 ps
CPU time 0.84 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 200752 kb
Host smart-9ccda7c9-4f5f-42c8-89f8-5647dcfa57a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470594734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3470594734
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2446388014
Short name T382
Test name
Test status
Simulation time 1027127576 ps
CPU time 5.54 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 201060 kb
Host smart-2a181402-cad5-44a2-a989-b05d86426ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446388014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2446388014
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3353321880
Short name T210
Test name
Test status
Simulation time 183705091 ps
CPU time 1.22 seconds
Started Mar 24 12:44:05 PM PDT 24
Finished Mar 24 12:44:06 PM PDT 24
Peak memory 200720 kb
Host smart-e332fae7-e7ac-4aba-a8e1-3e8c8852bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353321880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3353321880
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3457300184
Short name T208
Test name
Test status
Simulation time 262198357 ps
CPU time 1.48 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 201100 kb
Host smart-15a1d1bf-38d9-449b-a837-463a0b2549c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457300184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3457300184
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1104621280
Short name T122
Test name
Test status
Simulation time 6369377695 ps
CPU time 21.49 seconds
Started Mar 24 12:43:52 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 201200 kb
Host smart-03f9f9a6-4c6f-4b37-a234-ccc11f3dc8e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104621280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1104621280
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3331827652
Short name T8
Test name
Test status
Simulation time 149531961 ps
CPU time 1.86 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 201196 kb
Host smart-b4504132-dfc1-43bd-97fd-f75275065fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331827652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3331827652
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.817090247
Short name T331
Test name
Test status
Simulation time 60939447 ps
CPU time 0.73 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 200884 kb
Host smart-b5b6e1b2-5ee7-4f33-9774-48e83f804664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817090247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.817090247
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.328270552
Short name T328
Test name
Test status
Simulation time 66821813 ps
CPU time 0.78 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 200720 kb
Host smart-9ef97d5e-7310-47ea-abf9-4680d67da5c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328270552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.328270552
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.645188518
Short name T33
Test name
Test status
Simulation time 1224074215 ps
CPU time 5.74 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 218624 kb
Host smart-4c597679-05f2-4066-8b81-360be707bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645188518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.645188518
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.6490860
Short name T25
Test name
Test status
Simulation time 243824636 ps
CPU time 1.06 seconds
Started Mar 24 12:44:08 PM PDT 24
Finished Mar 24 12:44:09 PM PDT 24
Peak memory 218184 kb
Host smart-72775078-9017-4c9a-9cf2-e2f9baf65c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6490860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.6490860
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2113316795
Short name T279
Test name
Test status
Simulation time 183577611 ps
CPU time 0.84 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 200748 kb
Host smart-f4ec014a-796b-412e-8db7-8eca4baca697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113316795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2113316795
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.111768717
Short name T205
Test name
Test status
Simulation time 902700986 ps
CPU time 4.56 seconds
Started Mar 24 12:44:16 PM PDT 24
Finished Mar 24 12:44:21 PM PDT 24
Peak memory 201056 kb
Host smart-79fd12e3-7691-4fca-b910-c6b3cec7211e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111768717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.111768717
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1858017335
Short name T477
Test name
Test status
Simulation time 165732316 ps
CPU time 1.17 seconds
Started Mar 24 12:44:04 PM PDT 24
Finished Mar 24 12:44:05 PM PDT 24
Peak memory 200776 kb
Host smart-fad85082-a471-44b9-8255-9fe5827593ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858017335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1858017335
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2219038349
Short name T42
Test name
Test status
Simulation time 112830863 ps
CPU time 1.3 seconds
Started Mar 24 12:43:59 PM PDT 24
Finished Mar 24 12:44:01 PM PDT 24
Peak memory 201100 kb
Host smart-abfc8697-6f75-4caa-800b-e8a58765beaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219038349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2219038349
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2957401169
Short name T125
Test name
Test status
Simulation time 9708479090 ps
CPU time 32.63 seconds
Started Mar 24 12:44:21 PM PDT 24
Finished Mar 24 12:44:54 PM PDT 24
Peak memory 209328 kb
Host smart-8be3e566-b4bd-4351-86d1-68e22dd46b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957401169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2957401169
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3861830321
Short name T1
Test name
Test status
Simulation time 120067172 ps
CPU time 1.51 seconds
Started Mar 24 12:44:17 PM PDT 24
Finished Mar 24 12:44:18 PM PDT 24
Peak memory 200940 kb
Host smart-de4fbef5-6905-4216-b6c7-389b3aad4312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861830321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3861830321
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2814710985
Short name T465
Test name
Test status
Simulation time 132076841 ps
CPU time 0.98 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 200908 kb
Host smart-894f5199-5eb0-4d7d-9f73-c6e54708925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814710985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2814710985
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2557359996
Short name T140
Test name
Test status
Simulation time 74788497 ps
CPU time 0.78 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 200708 kb
Host smart-a4de85ac-fd2c-4bd9-bdff-a5f105ed8ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557359996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2557359996
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1891767771
Short name T51
Test name
Test status
Simulation time 1230448194 ps
CPU time 5.67 seconds
Started Mar 24 12:43:22 PM PDT 24
Finished Mar 24 12:43:28 PM PDT 24
Peak memory 222564 kb
Host smart-9212c112-8078-41b5-91b6-c58cfdc7669e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891767771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1891767771
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2271168461
Short name T153
Test name
Test status
Simulation time 244500952 ps
CPU time 1.12 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 218072 kb
Host smart-19fc5bbb-6b84-4ff4-a890-6b936479aa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271168461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2271168461
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1372965913
Short name T273
Test name
Test status
Simulation time 218689212 ps
CPU time 0.91 seconds
Started Mar 24 12:43:13 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 200608 kb
Host smart-3e490dc4-1c45-4db7-93b5-25b9f675f2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372965913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1372965913
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3234476805
Short name T137
Test name
Test status
Simulation time 1112908598 ps
CPU time 5.32 seconds
Started Mar 24 12:43:30 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 201084 kb
Host smart-04b25fcd-3782-4a81-8573-881d61f5a027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234476805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3234476805
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3899929407
Short name T71
Test name
Test status
Simulation time 8331051128 ps
CPU time 13.28 seconds
Started Mar 24 12:43:19 PM PDT 24
Finished Mar 24 12:43:33 PM PDT 24
Peak memory 217640 kb
Host smart-bbb00092-ed14-4076-ad27-5a8b064abfc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899929407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3899929407
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.849156965
Short name T12
Test name
Test status
Simulation time 105489506 ps
CPU time 0.99 seconds
Started Mar 24 12:43:17 PM PDT 24
Finished Mar 24 12:43:18 PM PDT 24
Peak memory 200808 kb
Host smart-2f80b851-e09a-4c96-bf0a-5203d93898c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849156965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.849156965
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1561956604
Short name T450
Test name
Test status
Simulation time 8475103404 ps
CPU time 28.09 seconds
Started Mar 24 12:43:13 PM PDT 24
Finished Mar 24 12:43:42 PM PDT 24
Peak memory 209320 kb
Host smart-ed8ad242-861d-45e0-a184-5363d35eb7f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561956604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1561956604
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2846724350
Short name T343
Test name
Test status
Simulation time 319774059 ps
CPU time 2.18 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:18 PM PDT 24
Peak memory 200932 kb
Host smart-63003743-2f6b-4dd0-9a88-7a2583efc326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846724350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2846724350
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.869617066
Short name T517
Test name
Test status
Simulation time 105945045 ps
CPU time 0.95 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 200828 kb
Host smart-419914af-c11f-47b3-919b-9f5ca8eede93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869617066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.869617066
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2305963258
Short name T474
Test name
Test status
Simulation time 63530873 ps
CPU time 0.74 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 200776 kb
Host smart-5b17ead0-c191-48e4-a8b6-4bc71f514e09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305963258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2305963258
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1879291626
Short name T388
Test name
Test status
Simulation time 1891627465 ps
CPU time 7.23 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:20 PM PDT 24
Peak memory 218600 kb
Host smart-621ba1a6-6cb0-421f-8a7d-d8186f4f65b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879291626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1879291626
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.880006981
Short name T293
Test name
Test status
Simulation time 244951358 ps
CPU time 1.1 seconds
Started Mar 24 12:44:26 PM PDT 24
Finished Mar 24 12:44:28 PM PDT 24
Peak memory 218168 kb
Host smart-f089f339-8f42-450e-b3da-805c27b3d0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880006981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.880006981
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3990764660
Short name T424
Test name
Test status
Simulation time 129991624 ps
CPU time 0.81 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:11 PM PDT 24
Peak memory 200788 kb
Host smart-5e220c9d-a415-4f0b-b2ac-1b026c5e9381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990764660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3990764660
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4159687600
Short name T439
Test name
Test status
Simulation time 1306331643 ps
CPU time 5.82 seconds
Started Mar 24 12:44:33 PM PDT 24
Finished Mar 24 12:44:39 PM PDT 24
Peak memory 200992 kb
Host smart-c5be8634-9e6e-4bd5-9fe6-c812307422ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159687600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4159687600
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.404588273
Short name T156
Test name
Test status
Simulation time 144773121 ps
CPU time 1.18 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 200880 kb
Host smart-729ed93f-7c29-4588-8cd0-b988a7a0f818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404588273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.404588273
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1466147897
Short name T84
Test name
Test status
Simulation time 112704695 ps
CPU time 1.19 seconds
Started Mar 24 12:44:16 PM PDT 24
Finished Mar 24 12:44:17 PM PDT 24
Peak memory 200968 kb
Host smart-653e70c4-21b8-47be-be6c-32a2afc5a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466147897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1466147897
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.597021513
Short name T308
Test name
Test status
Simulation time 4589568942 ps
CPU time 17.26 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:28 PM PDT 24
Peak memory 210956 kb
Host smart-2fa86a4d-06a8-42d8-bb38-d259aa0c8dd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597021513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.597021513
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2414053512
Short name T168
Test name
Test status
Simulation time 377358459 ps
CPU time 2.45 seconds
Started Mar 24 12:44:05 PM PDT 24
Finished Mar 24 12:44:08 PM PDT 24
Peak memory 200816 kb
Host smart-8d81a98e-9f02-4822-a224-eceb3decf2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414053512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2414053512
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.261915408
Short name T489
Test name
Test status
Simulation time 86733302 ps
CPU time 0.9 seconds
Started Mar 24 12:44:18 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 200884 kb
Host smart-f4b1aa5e-1e0b-46fe-a9ee-30a89e47c9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261915408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.261915408
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3382359625
Short name T311
Test name
Test status
Simulation time 64192386 ps
CPU time 0.8 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 200768 kb
Host smart-e0d8c452-e40f-4615-a854-2c185d4091b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382359625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3382359625
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1467440555
Short name T30
Test name
Test status
Simulation time 2356211136 ps
CPU time 8.37 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 222784 kb
Host smart-b2fb5570-7ea6-43c4-ab5f-bb91890f17a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467440555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1467440555
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.779521436
Short name T255
Test name
Test status
Simulation time 243416217 ps
CPU time 1.04 seconds
Started Mar 24 12:44:28 PM PDT 24
Finished Mar 24 12:44:29 PM PDT 24
Peak memory 218312 kb
Host smart-7d100733-476d-41a1-be2e-3d0bfe039ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779521436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.779521436
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3873373078
Short name T341
Test name
Test status
Simulation time 139154843 ps
CPU time 0.81 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:21 PM PDT 24
Peak memory 200776 kb
Host smart-a0215977-0215-4e0f-b676-9f7994f307fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873373078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3873373078
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3727721659
Short name T14
Test name
Test status
Simulation time 911450476 ps
CPU time 4.78 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 12:44:29 PM PDT 24
Peak memory 201092 kb
Host smart-dc4a8e0e-c52a-4bad-b290-bf8c8e9cc161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727721659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3727721659
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.778127648
Short name T537
Test name
Test status
Simulation time 140035868 ps
CPU time 1.13 seconds
Started Mar 24 12:44:16 PM PDT 24
Finished Mar 24 12:44:17 PM PDT 24
Peak memory 200908 kb
Host smart-905b5f7c-a11a-420c-b586-81fe855d4897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778127648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.778127648
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.4104492537
Short name T239
Test name
Test status
Simulation time 126235056 ps
CPU time 1.2 seconds
Started Mar 24 12:44:18 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 201092 kb
Host smart-e1115ade-4911-4168-a38b-e6de05babdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104492537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4104492537
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3523880716
Short name T103
Test name
Test status
Simulation time 3324689184 ps
CPU time 16.01 seconds
Started Mar 24 12:44:39 PM PDT 24
Finished Mar 24 12:44:55 PM PDT 24
Peak memory 209400 kb
Host smart-a5687c5a-8a7d-42d0-bcdd-d6e9407e46d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523880716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3523880716
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1654942129
Short name T334
Test name
Test status
Simulation time 152333336 ps
CPU time 1.82 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 200840 kb
Host smart-1421810a-310a-45fb-ac16-9189c96a4d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654942129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1654942129
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3459903498
Short name T290
Test name
Test status
Simulation time 138238903 ps
CPU time 1.13 seconds
Started Mar 24 12:44:17 PM PDT 24
Finished Mar 24 12:44:18 PM PDT 24
Peak memory 200872 kb
Host smart-169359a9-ead7-4f87-8672-6a71123c0c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459903498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3459903498
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.744035280
Short name T468
Test name
Test status
Simulation time 60815719 ps
CPU time 0.75 seconds
Started Mar 24 12:44:04 PM PDT 24
Finished Mar 24 12:44:05 PM PDT 24
Peak memory 200624 kb
Host smart-9c9788cd-b160-400e-b5fe-7dc893e98026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744035280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.744035280
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.470129696
Short name T422
Test name
Test status
Simulation time 2362633923 ps
CPU time 8.53 seconds
Started Mar 24 12:44:25 PM PDT 24
Finished Mar 24 12:44:33 PM PDT 24
Peak memory 218412 kb
Host smart-f0843271-1b04-4bac-8bcf-f93b66391ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470129696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.470129696
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1767174718
Short name T305
Test name
Test status
Simulation time 244613773 ps
CPU time 1.1 seconds
Started Mar 24 12:44:08 PM PDT 24
Finished Mar 24 12:44:09 PM PDT 24
Peak memory 218092 kb
Host smart-8776b767-09f8-4d13-b09e-6b06860bc2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767174718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1767174718
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.892782890
Short name T528
Test name
Test status
Simulation time 243821187 ps
CPU time 0.95 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:13 PM PDT 24
Peak memory 200744 kb
Host smart-965462d6-a457-4b8c-8244-8856e98995d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892782890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.892782890
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.556707640
Short name T297
Test name
Test status
Simulation time 1440881596 ps
CPU time 5.62 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:21 PM PDT 24
Peak memory 201068 kb
Host smart-4fbee7eb-8d7b-4867-9eb1-29beb5d675a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556707640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.556707640
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2856103855
Short name T526
Test name
Test status
Simulation time 174572787 ps
CPU time 1.15 seconds
Started Mar 24 12:44:25 PM PDT 24
Finished Mar 24 12:44:26 PM PDT 24
Peak memory 200888 kb
Host smart-35036301-902c-498c-a285-790fbae7cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856103855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2856103855
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1759033424
Short name T399
Test name
Test status
Simulation time 248449696 ps
CPU time 1.44 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:17 PM PDT 24
Peak memory 200988 kb
Host smart-05544098-9ba0-476d-b33f-c282abdb3fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759033424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1759033424
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.51691985
Short name T144
Test name
Test status
Simulation time 475066923 ps
CPU time 2.46 seconds
Started Mar 24 12:44:32 PM PDT 24
Finished Mar 24 12:44:35 PM PDT 24
Peak memory 201084 kb
Host smart-1a7a5838-296a-427a-9b17-f5e64a1223b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51691985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.51691985
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3222610493
Short name T459
Test name
Test status
Simulation time 320737952 ps
CPU time 2.12 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 200916 kb
Host smart-8f05b710-510d-4bbf-a52e-bfbea0fb4e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222610493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3222610493
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.786300958
Short name T383
Test name
Test status
Simulation time 120074782 ps
CPU time 1.02 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 200748 kb
Host smart-6298a761-5e16-40be-9df3-a20596865d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786300958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.786300958
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1415343480
Short name T455
Test name
Test status
Simulation time 80316739 ps
CPU time 0.86 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 200776 kb
Host smart-a22ce4f0-c700-4844-bb9d-476414067ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415343480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1415343480
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1690922923
Short name T298
Test name
Test status
Simulation time 2158931714 ps
CPU time 8.28 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 12:44:33 PM PDT 24
Peak memory 222796 kb
Host smart-7a80e31a-6d7d-4c3d-9a0c-6bc2a639530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690922923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1690922923
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1090539903
Short name T148
Test name
Test status
Simulation time 244942120 ps
CPU time 1.08 seconds
Started Mar 24 12:44:18 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 218136 kb
Host smart-737752f2-410e-404f-8c4e-24d7fcd78481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090539903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1090539903
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.901481744
Short name T519
Test name
Test status
Simulation time 75456412 ps
CPU time 0.69 seconds
Started Mar 24 12:44:07 PM PDT 24
Finished Mar 24 12:44:07 PM PDT 24
Peak memory 200676 kb
Host smart-43301ea9-59ba-4b6a-a860-8fa1b66efc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901481744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.901481744
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.437603499
Short name T442
Test name
Test status
Simulation time 1624329425 ps
CPU time 6.79 seconds
Started Mar 24 12:44:10 PM PDT 24
Finished Mar 24 12:44:22 PM PDT 24
Peak memory 201076 kb
Host smart-b946dabc-6e33-4925-9378-55e2a985eef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437603499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.437603499
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2786927338
Short name T493
Test name
Test status
Simulation time 110152897 ps
CPU time 1.03 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:16 PM PDT 24
Peak memory 200904 kb
Host smart-8189443e-6b2f-4ff2-833c-844f91397dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786927338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2786927338
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1312600180
Short name T476
Test name
Test status
Simulation time 196815208 ps
CPU time 1.46 seconds
Started Mar 24 12:44:25 PM PDT 24
Finished Mar 24 12:44:27 PM PDT 24
Peak memory 201316 kb
Host smart-6d2ffa5e-a0d6-4637-81d6-7bb8d82cd35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312600180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1312600180
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1497639418
Short name T346
Test name
Test status
Simulation time 3779105737 ps
CPU time 17.42 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:30 PM PDT 24
Peak memory 209308 kb
Host smart-a59ba30e-ac91-4d9c-99c1-12b7296242e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497639418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1497639418
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3618860014
Short name T483
Test name
Test status
Simulation time 127653090 ps
CPU time 1.81 seconds
Started Mar 24 12:44:32 PM PDT 24
Finished Mar 24 12:44:34 PM PDT 24
Peak memory 200944 kb
Host smart-5cb421d3-b9e2-4268-9a1a-a766318edb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618860014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3618860014
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3755701291
Short name T377
Test name
Test status
Simulation time 145567661 ps
CPU time 1.31 seconds
Started Mar 24 12:44:03 PM PDT 24
Finished Mar 24 12:44:05 PM PDT 24
Peak memory 201016 kb
Host smart-1d170d9c-7291-4f35-9534-8c4a14db7f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755701291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3755701291
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3143051109
Short name T163
Test name
Test status
Simulation time 91397078 ps
CPU time 0.83 seconds
Started Mar 24 12:44:27 PM PDT 24
Finished Mar 24 12:44:28 PM PDT 24
Peak memory 200736 kb
Host smart-873ba1ab-e05e-4e1e-a29d-f1b9d0e12fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143051109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3143051109
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2216477439
Short name T469
Test name
Test status
Simulation time 244455513 ps
CPU time 1.14 seconds
Started Mar 24 12:44:18 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 218232 kb
Host smart-96fe01ba-c11d-4ccd-a8c8-d56c583871f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216477439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2216477439
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1104696154
Short name T342
Test name
Test status
Simulation time 145616175 ps
CPU time 0.86 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 200768 kb
Host smart-66473719-2a24-4ec0-8385-6e329a2d9e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104696154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1104696154
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.568911538
Short name T432
Test name
Test status
Simulation time 1009368869 ps
CPU time 4.95 seconds
Started Mar 24 12:44:09 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 201100 kb
Host smart-a7967764-dedd-4693-8b49-faa4ea9559ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568911538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.568911538
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.512210195
Short name T372
Test name
Test status
Simulation time 157991285 ps
CPU time 1.16 seconds
Started Mar 24 12:44:05 PM PDT 24
Finished Mar 24 12:44:06 PM PDT 24
Peak memory 200816 kb
Host smart-0d5e9fbd-1efd-472c-83f4-baf0be60dae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512210195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.512210195
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3268065382
Short name T445
Test name
Test status
Simulation time 114605195 ps
CPU time 1.15 seconds
Started Mar 24 12:44:21 PM PDT 24
Finished Mar 24 12:44:22 PM PDT 24
Peak memory 201096 kb
Host smart-6ca94d3b-c0af-40d8-93c4-628592032f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268065382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3268065382
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3345822880
Short name T425
Test name
Test status
Simulation time 900490286 ps
CPU time 4.74 seconds
Started Mar 24 12:44:27 PM PDT 24
Finished Mar 24 12:44:32 PM PDT 24
Peak memory 201076 kb
Host smart-7605cb21-e9e5-471d-a2d0-e13d2d316c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345822880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3345822880
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3758941357
Short name T226
Test name
Test status
Simulation time 342872095 ps
CPU time 2.3 seconds
Started Mar 24 12:44:28 PM PDT 24
Finished Mar 24 12:44:30 PM PDT 24
Peak memory 200964 kb
Host smart-ce26019b-ec85-414a-a374-748a25f7722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758941357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3758941357
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.394131054
Short name T186
Test name
Test status
Simulation time 227482677 ps
CPU time 1.36 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:17 PM PDT 24
Peak memory 200896 kb
Host smart-fd490423-b665-4311-8436-747486a39986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394131054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.394131054
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.891484473
Short name T431
Test name
Test status
Simulation time 65743701 ps
CPU time 0.79 seconds
Started Mar 24 12:44:08 PM PDT 24
Finished Mar 24 12:44:09 PM PDT 24
Peak memory 200768 kb
Host smart-648ab6bd-8e2c-42e4-acc1-4066a89d45ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891484473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.891484473
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2567533322
Short name T36
Test name
Test status
Simulation time 2346129419 ps
CPU time 9.07 seconds
Started Mar 24 12:44:17 PM PDT 24
Finished Mar 24 12:44:26 PM PDT 24
Peak memory 222808 kb
Host smart-ff09ec52-2e21-49e8-b2d8-24ba36aedf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567533322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2567533322
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3369411027
Short name T394
Test name
Test status
Simulation time 243859270 ps
CPU time 1.13 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 218216 kb
Host smart-515d74a9-edad-44bc-ab75-cf915898f4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369411027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3369411027
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2363127375
Short name T428
Test name
Test status
Simulation time 199530902 ps
CPU time 0.86 seconds
Started Mar 24 12:44:14 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 200648 kb
Host smart-b87ee694-e51f-4f79-882a-4f97946921ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363127375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2363127375
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2963817220
Short name T124
Test name
Test status
Simulation time 2067040584 ps
CPU time 7.31 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:21 PM PDT 24
Peak memory 201080 kb
Host smart-b45c348c-5ba2-4e7b-aa96-52afc8047b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963817220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2963817220
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1092533732
Short name T358
Test name
Test status
Simulation time 190284636 ps
CPU time 1.16 seconds
Started Mar 24 12:44:26 PM PDT 24
Finished Mar 24 12:44:28 PM PDT 24
Peak memory 200904 kb
Host smart-455fc59a-138a-43a0-9a12-07f2cece54d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092533732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1092533732
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3926761604
Short name T378
Test name
Test status
Simulation time 111328064 ps
CPU time 1.18 seconds
Started Mar 24 12:44:24 PM PDT 24
Finished Mar 24 12:44:25 PM PDT 24
Peak memory 201080 kb
Host smart-5cea98fa-73d7-4f64-b69b-417851f0d28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926761604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3926761604
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2706875163
Short name T327
Test name
Test status
Simulation time 10670290966 ps
CPU time 41.52 seconds
Started Mar 24 12:44:29 PM PDT 24
Finished Mar 24 12:45:11 PM PDT 24
Peak memory 209272 kb
Host smart-6fee6567-bbf5-459f-9ec7-8a1cdf5d3064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706875163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2706875163
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3169383950
Short name T452
Test name
Test status
Simulation time 387205222 ps
CPU time 2.49 seconds
Started Mar 24 12:44:21 PM PDT 24
Finished Mar 24 12:44:24 PM PDT 24
Peak memory 200928 kb
Host smart-23629cd3-fed7-4068-93a3-6356568e8192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169383950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3169383950
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2864509840
Short name T247
Test name
Test status
Simulation time 143785605 ps
CPU time 1.08 seconds
Started Mar 24 12:44:21 PM PDT 24
Finished Mar 24 12:44:22 PM PDT 24
Peak memory 200836 kb
Host smart-2355034e-42ec-4a99-92b5-fe8db3f235c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864509840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2864509840
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2734513695
Short name T534
Test name
Test status
Simulation time 68368145 ps
CPU time 0.8 seconds
Started Mar 24 12:44:25 PM PDT 24
Finished Mar 24 12:44:26 PM PDT 24
Peak memory 200780 kb
Host smart-5204f8f6-f953-4b9c-bcd1-bde2e5c5b465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734513695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2734513695
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3956236308
Short name T29
Test name
Test status
Simulation time 2375595599 ps
CPU time 8.45 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:20 PM PDT 24
Peak memory 218204 kb
Host smart-f839a16d-445e-400e-adc5-1a7ce7f3bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956236308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3956236308
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2833806307
Short name T426
Test name
Test status
Simulation time 243874350 ps
CPU time 1.05 seconds
Started Mar 24 12:44:16 PM PDT 24
Finished Mar 24 12:44:17 PM PDT 24
Peak memory 218156 kb
Host smart-c20ba3eb-374c-4afc-a440-8a30a64a4727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833806307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2833806307
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3523346872
Short name T435
Test name
Test status
Simulation time 138357817 ps
CPU time 0.83 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:16 PM PDT 24
Peak memory 200764 kb
Host smart-def0fc9b-d1b3-4ea8-ab1a-5f38e2165335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523346872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3523346872
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.4267053336
Short name T321
Test name
Test status
Simulation time 852128096 ps
CPU time 4.05 seconds
Started Mar 24 12:44:16 PM PDT 24
Finished Mar 24 12:44:20 PM PDT 24
Peak memory 200972 kb
Host smart-df15ba7b-62bc-4378-9da7-a02411f8bc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267053336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.4267053336
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.908084061
Short name T406
Test name
Test status
Simulation time 171033113 ps
CPU time 1.24 seconds
Started Mar 24 12:44:27 PM PDT 24
Finished Mar 24 12:44:29 PM PDT 24
Peak memory 200788 kb
Host smart-553d409d-4b89-4cd0-ba94-1aa605d10bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908084061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.908084061
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.576732920
Short name T404
Test name
Test status
Simulation time 205699949 ps
CPU time 1.43 seconds
Started Mar 24 12:44:18 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 200972 kb
Host smart-23d100ce-6116-4c03-be51-ea76f9c07004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576732920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.576732920
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1353230140
Short name T272
Test name
Test status
Simulation time 4900732345 ps
CPU time 24.1 seconds
Started Mar 24 12:44:18 PM PDT 24
Finished Mar 24 12:44:42 PM PDT 24
Peak memory 209392 kb
Host smart-5d6e534e-8c13-43ce-a8c0-3eb7577cf91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353230140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1353230140
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2812768410
Short name T54
Test name
Test status
Simulation time 501693303 ps
CPU time 2.54 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 200956 kb
Host smart-3d29188e-3904-49de-ae3c-048e9eb08cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812768410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2812768410
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3095564831
Short name T356
Test name
Test status
Simulation time 57984892 ps
CPU time 0.82 seconds
Started Mar 24 12:44:08 PM PDT 24
Finished Mar 24 12:44:09 PM PDT 24
Peak memory 200900 kb
Host smart-dc0e6074-7021-4a00-8740-dfcd8b615e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095564831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3095564831
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1255449792
Short name T174
Test name
Test status
Simulation time 61698477 ps
CPU time 0.74 seconds
Started Mar 24 12:44:13 PM PDT 24
Finished Mar 24 12:44:14 PM PDT 24
Peak memory 200788 kb
Host smart-879a488d-561e-4f7d-a3c3-a070f7097051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255449792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1255449792
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1229014469
Short name T492
Test name
Test status
Simulation time 2380640710 ps
CPU time 7.65 seconds
Started Mar 24 12:44:33 PM PDT 24
Finished Mar 24 12:44:40 PM PDT 24
Peak memory 217972 kb
Host smart-9d1f3be5-f5be-4285-9ed2-969b3d6c54cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229014469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1229014469
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2723647694
Short name T56
Test name
Test status
Simulation time 244860360 ps
CPU time 1 seconds
Started Mar 24 12:44:18 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 218040 kb
Host smart-25573d2b-ac5f-415b-bc2f-366004a6ab97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723647694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2723647694
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2736683664
Short name T242
Test name
Test status
Simulation time 135410933 ps
CPU time 0.89 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:16 PM PDT 24
Peak memory 200784 kb
Host smart-71b3478a-49ea-4a32-9a1b-6acb5c2515e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736683664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2736683664
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.981311999
Short name T506
Test name
Test status
Simulation time 767237892 ps
CPU time 4.19 seconds
Started Mar 24 12:44:30 PM PDT 24
Finished Mar 24 12:44:34 PM PDT 24
Peak memory 201300 kb
Host smart-7e1ea95a-91c8-4600-98b9-576339af6974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981311999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.981311999
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2538274483
Short name T162
Test name
Test status
Simulation time 112330741 ps
CPU time 0.98 seconds
Started Mar 24 12:44:20 PM PDT 24
Finished Mar 24 12:44:26 PM PDT 24
Peak memory 200872 kb
Host smart-0d5bb1a8-e09b-41d6-88cc-261f2d12f5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538274483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2538274483
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1902955575
Short name T227
Test name
Test status
Simulation time 252906120 ps
CPU time 1.46 seconds
Started Mar 24 12:44:21 PM PDT 24
Finished Mar 24 12:44:23 PM PDT 24
Peak memory 200928 kb
Host smart-ec1c84a1-3908-452e-bc3d-ab1e4fa983f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902955575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1902955575
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2294876535
Short name T41
Test name
Test status
Simulation time 2130969635 ps
CPU time 10.25 seconds
Started Mar 24 12:44:26 PM PDT 24
Finished Mar 24 12:44:36 PM PDT 24
Peak memory 201108 kb
Host smart-522df755-6a54-4762-b23f-51360b92bc33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294876535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2294876535
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2487470260
Short name T87
Test name
Test status
Simulation time 277702705 ps
CPU time 1.96 seconds
Started Mar 24 12:44:32 PM PDT 24
Finished Mar 24 12:44:34 PM PDT 24
Peak memory 200948 kb
Host smart-746f0b0e-06a1-4643-b14d-67568098ecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487470260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2487470260
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.21218768
Short name T539
Test name
Test status
Simulation time 131731549 ps
CPU time 1.04 seconds
Started Mar 24 12:44:11 PM PDT 24
Finished Mar 24 12:44:12 PM PDT 24
Peak memory 200896 kb
Host smart-657ffa1d-96ea-4851-a7ba-fabc1827297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21218768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.21218768
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2882912821
Short name T161
Test name
Test status
Simulation time 67904828 ps
CPU time 0.75 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 200632 kb
Host smart-ccc47dd5-1a5c-4851-b80c-4bd7a1af76af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882912821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2882912821
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1447440679
Short name T504
Test name
Test status
Simulation time 1876998106 ps
CPU time 7.22 seconds
Started Mar 24 12:44:17 PM PDT 24
Finished Mar 24 12:44:24 PM PDT 24
Peak memory 218596 kb
Host smart-94706031-d9c5-49c1-bcf2-b1ecdc3c1437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447440679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1447440679
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.353839877
Short name T85
Test name
Test status
Simulation time 244871821 ps
CPU time 1.03 seconds
Started Mar 24 12:44:14 PM PDT 24
Finished Mar 24 12:44:16 PM PDT 24
Peak memory 218168 kb
Host smart-98672741-feb8-4491-a11a-95fdc25f3c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353839877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.353839877
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1584524306
Short name T158
Test name
Test status
Simulation time 128405345 ps
CPU time 0.81 seconds
Started Mar 24 12:44:27 PM PDT 24
Finished Mar 24 12:44:28 PM PDT 24
Peak memory 200768 kb
Host smart-17f0091b-7859-4854-925c-637a7bb559e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584524306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1584524306
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3686150509
Short name T302
Test name
Test status
Simulation time 656697872 ps
CPU time 3.71 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:19 PM PDT 24
Peak memory 201072 kb
Host smart-bd10f613-74ad-4c8e-9ddd-100acd31b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686150509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3686150509
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2530233956
Short name T191
Test name
Test status
Simulation time 147323407 ps
CPU time 1.12 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:16 PM PDT 24
Peak memory 200888 kb
Host smart-e6df9591-02ea-4ef1-bdf7-1b6cb6fb258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530233956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2530233956
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2539868884
Short name T59
Test name
Test status
Simulation time 251117223 ps
CPU time 1.43 seconds
Started Mar 24 12:44:19 PM PDT 24
Finished Mar 24 12:44:21 PM PDT 24
Peak memory 201064 kb
Host smart-7cb51212-adc6-4c56-bb1d-730f933f0596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539868884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2539868884
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3865829384
Short name T207
Test name
Test status
Simulation time 1408917119 ps
CPU time 5.87 seconds
Started Mar 24 12:44:12 PM PDT 24
Finished Mar 24 12:44:18 PM PDT 24
Peak memory 201100 kb
Host smart-10195a05-c001-4879-8bb3-cd380456a70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865829384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3865829384
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1829118127
Short name T91
Test name
Test status
Simulation time 133359078 ps
CPU time 1.56 seconds
Started Mar 24 12:44:15 PM PDT 24
Finished Mar 24 12:44:17 PM PDT 24
Peak memory 209176 kb
Host smart-ba2f7cab-512f-4344-a405-a55c918c2662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829118127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1829118127
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.458278535
Short name T150
Test name
Test status
Simulation time 245370517 ps
CPU time 1.49 seconds
Started Mar 24 12:44:19 PM PDT 24
Finished Mar 24 12:44:20 PM PDT 24
Peak memory 201084 kb
Host smart-3118cdaa-f586-404f-a120-fe8dd2305e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458278535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.458278535
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.995382509
Short name T396
Test name
Test status
Simulation time 71869786 ps
CPU time 0.75 seconds
Started Mar 24 12:44:34 PM PDT 24
Finished Mar 24 12:44:35 PM PDT 24
Peak memory 200788 kb
Host smart-bba2e934-0d77-4e12-bf8e-19641734a3ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995382509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.995382509
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1826056325
Short name T81
Test name
Test status
Simulation time 1219030693 ps
CPU time 5.37 seconds
Started Mar 24 12:44:28 PM PDT 24
Finished Mar 24 12:44:33 PM PDT 24
Peak memory 222676 kb
Host smart-c1512120-bab0-4a09-8eff-d6bb93c0e558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826056325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1826056325
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3119807358
Short name T57
Test name
Test status
Simulation time 244023851 ps
CPU time 1.12 seconds
Started Mar 24 12:44:26 PM PDT 24
Finished Mar 24 12:44:28 PM PDT 24
Peak memory 218108 kb
Host smart-7d0b950e-c3d4-4d27-8695-acd29e6e9f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119807358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3119807358
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1539067643
Short name T319
Test name
Test status
Simulation time 87039874 ps
CPU time 0.76 seconds
Started Mar 24 12:44:30 PM PDT 24
Finished Mar 24 12:44:30 PM PDT 24
Peak memory 200764 kb
Host smart-9d573711-d24a-44ec-a8a8-546445eb790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539067643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1539067643
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.679060442
Short name T2
Test name
Test status
Simulation time 1486377093 ps
CPU time 6.27 seconds
Started Mar 24 12:44:33 PM PDT 24
Finished Mar 24 12:44:39 PM PDT 24
Peak memory 201056 kb
Host smart-fda404d6-06c4-40ea-b046-0c3322dcc803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679060442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.679060442
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1382516326
Short name T151
Test name
Test status
Simulation time 100235579 ps
CPU time 1.06 seconds
Started Mar 24 12:44:14 PM PDT 24
Finished Mar 24 12:44:15 PM PDT 24
Peak memory 200896 kb
Host smart-dd7eaacf-a3f9-4938-941c-6ae255c224f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382516326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1382516326
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1068269485
Short name T232
Test name
Test status
Simulation time 114113688 ps
CPU time 1.19 seconds
Started Mar 24 12:44:09 PM PDT 24
Finished Mar 24 12:44:10 PM PDT 24
Peak memory 200952 kb
Host smart-21cf3e8b-cd24-4cd1-bec1-66a628b7072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068269485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1068269485
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3420331885
Short name T266
Test name
Test status
Simulation time 1382831091 ps
CPU time 6.22 seconds
Started Mar 24 12:44:21 PM PDT 24
Finished Mar 24 12:44:27 PM PDT 24
Peak memory 209164 kb
Host smart-39a76b39-426b-42e0-ab08-8997a5105b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420331885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3420331885
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1298173020
Short name T414
Test name
Test status
Simulation time 379245391 ps
CPU time 2.38 seconds
Started Mar 24 12:44:20 PM PDT 24
Finished Mar 24 12:44:23 PM PDT 24
Peak memory 200944 kb
Host smart-2c750da2-0e70-4c08-a536-e883f09e8654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298173020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1298173020
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.646852959
Short name T189
Test name
Test status
Simulation time 236203389 ps
CPU time 1.43 seconds
Started Mar 24 12:44:16 PM PDT 24
Finished Mar 24 12:44:17 PM PDT 24
Peak memory 201012 kb
Host smart-209f08e1-6420-4f46-9dae-dd8578e63196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646852959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.646852959
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3933935184
Short name T354
Test name
Test status
Simulation time 72081306 ps
CPU time 0.78 seconds
Started Mar 24 12:43:49 PM PDT 24
Finished Mar 24 12:43:51 PM PDT 24
Peak memory 200692 kb
Host smart-38bfc0f7-47be-4875-9584-a2fcf98989ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933935184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3933935184
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1549292374
Short name T460
Test name
Test status
Simulation time 1864455063 ps
CPU time 7.07 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:23 PM PDT 24
Peak memory 217976 kb
Host smart-03983bfa-1ff8-4529-993b-e971827a9a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549292374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1549292374
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4194544615
Short name T453
Test name
Test status
Simulation time 244583776 ps
CPU time 1.16 seconds
Started Mar 24 12:43:38 PM PDT 24
Finished Mar 24 12:43:44 PM PDT 24
Peak memory 218172 kb
Host smart-2fe16020-546c-4d6e-80a6-e19cb4aee31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194544615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4194544615
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1144959000
Short name T516
Test name
Test status
Simulation time 162368660 ps
CPU time 0.83 seconds
Started Mar 24 12:43:19 PM PDT 24
Finished Mar 24 12:43:20 PM PDT 24
Peak memory 200648 kb
Host smart-701b8387-3bc1-466c-8b99-f2adab50fcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144959000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1144959000
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4171109730
Short name T347
Test name
Test status
Simulation time 1773705414 ps
CPU time 6.81 seconds
Started Mar 24 12:43:20 PM PDT 24
Finished Mar 24 12:43:27 PM PDT 24
Peak memory 200960 kb
Host smart-3777a604-79c4-4d46-8913-56090094942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171109730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4171109730
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2711775141
Short name T223
Test name
Test status
Simulation time 152446261 ps
CPU time 1.19 seconds
Started Mar 24 12:43:31 PM PDT 24
Finished Mar 24 12:43:32 PM PDT 24
Peak memory 200896 kb
Host smart-8350f2c3-583a-47f4-97e7-541a25249435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711775141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2711775141
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.7363962
Short name T241
Test name
Test status
Simulation time 246787700 ps
CPU time 1.55 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:14 PM PDT 24
Peak memory 200944 kb
Host smart-2af8c045-3d78-4fe9-98ad-479624dba8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7363962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.7363962
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.184260552
Short name T251
Test name
Test status
Simulation time 8372759057 ps
CPU time 28.65 seconds
Started Mar 24 12:43:20 PM PDT 24
Finished Mar 24 12:43:49 PM PDT 24
Peak memory 209308 kb
Host smart-1e904770-0616-4780-bc7d-baf9c1effd9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184260552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.184260552
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3757191332
Short name T218
Test name
Test status
Simulation time 300491715 ps
CPU time 1.99 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:18 PM PDT 24
Peak memory 209016 kb
Host smart-d7c44df1-68b0-44ba-afe0-f347d2f56a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757191332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3757191332
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1417270234
Short name T264
Test name
Test status
Simulation time 261624125 ps
CPU time 1.49 seconds
Started Mar 24 12:43:18 PM PDT 24
Finished Mar 24 12:43:19 PM PDT 24
Peak memory 200840 kb
Host smart-70937b36-d57e-4592-9889-901bda0764d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417270234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1417270234
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.4081716907
Short name T436
Test name
Test status
Simulation time 61563234 ps
CPU time 0.73 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:33 PM PDT 24
Peak memory 200768 kb
Host smart-7a1bd15e-b292-4439-ad3d-a2291a90090e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081716907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4081716907
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3186206470
Short name T397
Test name
Test status
Simulation time 1220076679 ps
CPU time 5.68 seconds
Started Mar 24 12:43:25 PM PDT 24
Finished Mar 24 12:43:30 PM PDT 24
Peak memory 222580 kb
Host smart-9723d932-0a28-4d45-9760-47cc1cf5390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186206470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3186206470
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2641807272
Short name T164
Test name
Test status
Simulation time 243649394 ps
CPU time 1.11 seconds
Started Mar 24 12:43:21 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 218056 kb
Host smart-0b890d83-d143-4295-b335-2372aa4ebec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641807272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2641807272
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.216219428
Short name T18
Test name
Test status
Simulation time 185482866 ps
CPU time 0.94 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:40 PM PDT 24
Peak memory 200772 kb
Host smart-1bc18cb7-25d4-4934-ac93-0b47d4cae16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216219428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.216219428
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1372107253
Short name T99
Test name
Test status
Simulation time 878627024 ps
CPU time 4.61 seconds
Started Mar 24 12:43:38 PM PDT 24
Finished Mar 24 12:43:43 PM PDT 24
Peak memory 201088 kb
Host smart-21a0dfe0-96fc-484e-8c9c-268a21f6b286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372107253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1372107253
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.361641464
Short name T494
Test name
Test status
Simulation time 152164256 ps
CPU time 1.11 seconds
Started Mar 24 12:43:23 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 200900 kb
Host smart-8ac54318-99c6-43ee-9fb3-6b7361a29b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361641464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.361641464
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3546149740
Short name T314
Test name
Test status
Simulation time 123444164 ps
CPU time 1.21 seconds
Started Mar 24 12:43:30 PM PDT 24
Finished Mar 24 12:43:31 PM PDT 24
Peak memory 200984 kb
Host smart-6e668ed1-aa6b-4871-859d-5ed4c41f41de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546149740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3546149740
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1742200763
Short name T300
Test name
Test status
Simulation time 9576476041 ps
CPU time 35.41 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:44:10 PM PDT 24
Peak memory 211372 kb
Host smart-2dd97a2e-7f18-4d69-8fed-57a437fc6bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742200763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1742200763
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.879353780
Short name T509
Test name
Test status
Simulation time 155856453 ps
CPU time 1.91 seconds
Started Mar 24 12:43:32 PM PDT 24
Finished Mar 24 12:43:34 PM PDT 24
Peak memory 200872 kb
Host smart-7142b00a-2d59-41ad-994a-a537669e8e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879353780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.879353780
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3555884459
Short name T213
Test name
Test status
Simulation time 179747029 ps
CPU time 1.3 seconds
Started Mar 24 12:43:23 PM PDT 24
Finished Mar 24 12:43:25 PM PDT 24
Peak memory 200984 kb
Host smart-776aad1d-9128-4c28-8afb-54c04597559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555884459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3555884459
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.960695690
Short name T371
Test name
Test status
Simulation time 81988328 ps
CPU time 0.78 seconds
Started Mar 24 12:43:31 PM PDT 24
Finished Mar 24 12:43:32 PM PDT 24
Peak memory 200724 kb
Host smart-d755416c-0089-4dd9-81e6-a7c7bf9e863a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960695690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.960695690
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2269718244
Short name T28
Test name
Test status
Simulation time 2357052204 ps
CPU time 8.25 seconds
Started Mar 24 12:43:28 PM PDT 24
Finished Mar 24 12:43:38 PM PDT 24
Peak memory 218632 kb
Host smart-216a1226-1908-45ca-8497-373f59ce66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269718244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2269718244
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1097283442
Short name T365
Test name
Test status
Simulation time 244665746 ps
CPU time 1.12 seconds
Started Mar 24 12:43:18 PM PDT 24
Finished Mar 24 12:43:19 PM PDT 24
Peak memory 218084 kb
Host smart-e839cab1-df39-41fa-a3aa-014639bc63f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097283442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1097283442
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2967980601
Short name T17
Test name
Test status
Simulation time 80989533 ps
CPU time 0.75 seconds
Started Mar 24 12:43:25 PM PDT 24
Finished Mar 24 12:43:26 PM PDT 24
Peak memory 200668 kb
Host smart-330886a0-589a-4f94-a661-b26c32f99de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967980601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2967980601
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1862878541
Short name T77
Test name
Test status
Simulation time 1401590239 ps
CPU time 5.15 seconds
Started Mar 24 12:43:23 PM PDT 24
Finished Mar 24 12:43:29 PM PDT 24
Peak memory 201040 kb
Host smart-181a76ad-70c2-435b-8b3f-e05f8a5c6f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862878541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1862878541
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2550398599
Short name T165
Test name
Test status
Simulation time 100981947 ps
CPU time 0.99 seconds
Started Mar 24 12:43:32 PM PDT 24
Finished Mar 24 12:43:34 PM PDT 24
Peak memory 200772 kb
Host smart-5b7c64cc-b87e-41fb-9164-1ac822570283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550398599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2550398599
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2729809345
Short name T211
Test name
Test status
Simulation time 111783118 ps
CPU time 1.11 seconds
Started Mar 24 12:43:22 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 200924 kb
Host smart-fac6cbd0-207d-4808-9ce5-2712797eba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729809345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2729809345
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1995834777
Short name T325
Test name
Test status
Simulation time 13863049142 ps
CPU time 47.08 seconds
Started Mar 24 12:43:31 PM PDT 24
Finished Mar 24 12:44:18 PM PDT 24
Peak memory 217040 kb
Host smart-d81e7169-c03e-40f6-aeaf-7978065ce390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995834777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1995834777
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2711387122
Short name T217
Test name
Test status
Simulation time 352155801 ps
CPU time 2.07 seconds
Started Mar 24 12:43:27 PM PDT 24
Finished Mar 24 12:43:29 PM PDT 24
Peak memory 200936 kb
Host smart-d620eef3-6e46-479c-a414-e8c96cbccad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711387122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2711387122
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3484462472
Short name T357
Test name
Test status
Simulation time 194000428 ps
CPU time 1.21 seconds
Started Mar 24 12:43:20 PM PDT 24
Finished Mar 24 12:43:22 PM PDT 24
Peak memory 200816 kb
Host smart-71979692-58cc-479c-9ca1-29492c50aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484462472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3484462472
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2315509472
Short name T285
Test name
Test status
Simulation time 59360639 ps
CPU time 0.7 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 200692 kb
Host smart-1b40646d-1373-4fbd-92ec-358c78168490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315509472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2315509472
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1890684922
Short name T50
Test name
Test status
Simulation time 2352303327 ps
CPU time 7.9 seconds
Started Mar 24 12:43:32 PM PDT 24
Finished Mar 24 12:43:41 PM PDT 24
Peak memory 222640 kb
Host smart-82baa241-6898-433a-be87-4ded56fbd04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890684922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1890684922
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2838195520
Short name T139
Test name
Test status
Simulation time 244487882 ps
CPU time 1.07 seconds
Started Mar 24 12:43:26 PM PDT 24
Finished Mar 24 12:43:27 PM PDT 24
Peak memory 218220 kb
Host smart-e7d97e69-9e0b-4595-9e66-38d0056fc449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838195520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2838195520
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.648131722
Short name T16
Test name
Test status
Simulation time 109865934 ps
CPU time 0.79 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:40 PM PDT 24
Peak memory 200736 kb
Host smart-14ae42a9-43e7-43bf-900e-dd61244a97b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648131722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.648131722
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3453373218
Short name T418
Test name
Test status
Simulation time 947005587 ps
CPU time 4.74 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:44 PM PDT 24
Peak memory 201048 kb
Host smart-024b1e70-e351-461e-8794-7473d7fd85fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453373218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3453373218
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1129003070
Short name T393
Test name
Test status
Simulation time 183147914 ps
CPU time 1.18 seconds
Started Mar 24 12:43:39 PM PDT 24
Finished Mar 24 12:43:41 PM PDT 24
Peak memory 200816 kb
Host smart-267dbda1-7558-436c-9544-ea40acb84c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129003070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1129003070
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.786953934
Short name T13
Test name
Test status
Simulation time 249416963 ps
CPU time 1.47 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:35 PM PDT 24
Peak memory 201072 kb
Host smart-ed3c53fe-1fa9-4da4-80ff-0aa0d92bf285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786953934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.786953934
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.909924399
Short name T237
Test name
Test status
Simulation time 6184129719 ps
CPU time 27.35 seconds
Started Mar 24 12:43:37 PM PDT 24
Finished Mar 24 12:44:04 PM PDT 24
Peak memory 209320 kb
Host smart-9a65ec69-95a4-4416-83cb-65e631308f03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909924399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.909924399
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3610403631
Short name T275
Test name
Test status
Simulation time 284498049 ps
CPU time 2.02 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:35 PM PDT 24
Peak memory 200884 kb
Host smart-43e4491f-3beb-40dc-b18f-bcdb47989065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610403631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3610403631
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.4069329371
Short name T366
Test name
Test status
Simulation time 102077916 ps
CPU time 0.96 seconds
Started Mar 24 12:43:28 PM PDT 24
Finished Mar 24 12:43:29 PM PDT 24
Peak memory 200776 kb
Host smart-af9e9b1c-a66b-4d36-957c-c7fc6149e7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069329371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.4069329371
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3189149279
Short name T345
Test name
Test status
Simulation time 89491557 ps
CPU time 0.81 seconds
Started Mar 24 12:43:35 PM PDT 24
Finished Mar 24 12:43:36 PM PDT 24
Peak memory 200788 kb
Host smart-20e779d1-658b-40cd-94f3-a166bbed9a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189149279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3189149279
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2950744701
Short name T53
Test name
Test status
Simulation time 2359548313 ps
CPU time 8.91 seconds
Started Mar 24 12:43:45 PM PDT 24
Finished Mar 24 12:43:54 PM PDT 24
Peak memory 218412 kb
Host smart-8d0e4279-9539-4922-85aa-495be164d738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950744701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2950744701
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1594130941
Short name T385
Test name
Test status
Simulation time 243958175 ps
CPU time 1.09 seconds
Started Mar 24 12:43:26 PM PDT 24
Finished Mar 24 12:43:27 PM PDT 24
Peak memory 218112 kb
Host smart-2c49810f-6a23-4270-90a2-7e862ad06215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594130941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1594130941
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.4005329011
Short name T15
Test name
Test status
Simulation time 102164731 ps
CPU time 0.84 seconds
Started Mar 24 12:43:37 PM PDT 24
Finished Mar 24 12:43:38 PM PDT 24
Peak memory 200676 kb
Host smart-c1136a9c-ac6d-4d87-9906-d64444109ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005329011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4005329011
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2582581892
Short name T201
Test name
Test status
Simulation time 827752336 ps
CPU time 4.11 seconds
Started Mar 24 12:43:33 PM PDT 24
Finished Mar 24 12:43:37 PM PDT 24
Peak memory 201076 kb
Host smart-6250c88c-028d-4f6f-83f5-9ad9f8db162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582581892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2582581892
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3314977416
Short name T209
Test name
Test status
Simulation time 174814377 ps
CPU time 1.2 seconds
Started Mar 24 12:43:30 PM PDT 24
Finished Mar 24 12:43:32 PM PDT 24
Peak memory 200896 kb
Host smart-a0cc29a4-5837-4a6e-9510-f16b9c0973e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314977416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3314977416
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1745864917
Short name T220
Test name
Test status
Simulation time 204111270 ps
CPU time 1.35 seconds
Started Mar 24 12:43:45 PM PDT 24
Finished Mar 24 12:43:46 PM PDT 24
Peak memory 201044 kb
Host smart-aa745ac6-5cfb-4580-a2f3-0084871a39b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745864917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1745864917
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.220735585
Short name T520
Test name
Test status
Simulation time 7038464290 ps
CPU time 23.02 seconds
Started Mar 24 12:43:32 PM PDT 24
Finished Mar 24 12:43:55 PM PDT 24
Peak memory 201172 kb
Host smart-c700c059-6fb8-4e3e-8d42-215497ba5a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220735585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.220735585
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1089145503
Short name T244
Test name
Test status
Simulation time 142774986 ps
CPU time 1.84 seconds
Started Mar 24 12:43:40 PM PDT 24
Finished Mar 24 12:43:42 PM PDT 24
Peak memory 200948 kb
Host smart-eca4dd1b-e1dd-440b-97bd-fe20726d40e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089145503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1089145503
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2284426932
Short name T324
Test name
Test status
Simulation time 147953875 ps
CPU time 1.19 seconds
Started Mar 24 12:43:45 PM PDT 24
Finished Mar 24 12:43:47 PM PDT 24
Peak memory 200816 kb
Host smart-83bbb76b-e3f6-44f4-9f38-54d7bea29849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284426932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2284426932
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%