Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7686

1

T3

27

T4

96

T5

19

auto[1]

10647

1

T3

28

T4

87

T5

82

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5762	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6119	1			T1	1		T2	1		T3	13
reset_info_cp[2]	2835	1			T3	12		T4	30		T5	14
reset_info_cp[4]	3689	1			T3	11		T4	38		T5	18
reset_info_cp[8]	107	1			T26	1		T57	1		T51	1
reset_info_cp[16]	106	1			T4	1		T15	1		T17	1
reset_info_cp[32]	116	1			T3	1		T5	1		T15	2
reset_info_cp[64]	106	1			T4	2		T12	1		T17	1
reset_info_cp[128]	113	1			T3	1		T15	1		T17	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2922	1			T3	5		T4	27		T5	19
reset_info_cp[1]	auto[1]	2577	1			T3	7		T4	30		T5	7
reset_info_cp[2]	auto[0]	899	1			T3	7		T4	14		T69	4
reset_info_cp[2]	auto[1]	1936	1			T3	5		T4	16		T5	14
reset_info_cp[4]	auto[0]	1267	1			T3	6		T4	18		T69	6
reset_info_cp[4]	auto[1]	2422	1			T3	5		T4	20		T5	18
reset_info_cp[8]	auto[0]	49	1			T92	2		T142	1		T94	1
reset_info_cp[8]	auto[1]	58	1			T26	1		T57	1		T51	1
reset_info_cp[16]	auto[0]	44	1			T111	1		T143	1		T138	1
reset_info_cp[16]	auto[1]	62	1			T4	1		T15	1		T17	1
reset_info_cp[32]	auto[0]	43	1			T26	1		T95	2		T144	1
reset_info_cp[32]	auto[1]	73	1			T3	1		T5	1		T15	2
reset_info_cp[64]	auto[0]	50	1			T4	1		T12	1		T55	2
reset_info_cp[64]	auto[1]	56	1			T4	1		T17	1		T50	1
reset_info_cp[128]	auto[0]	48	1			T92	2		T142	1		T107	1
reset_info_cp[128]	auto[1]	65	1			T3	1		T15	1		T17	1