Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T542 /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2619555808 Mar 26 03:22:16 PM PDT 24 Mar 26 03:22:17 PM PDT 24 243613055 ps
T543 /workspace/coverage/default/26.rstmgr_por_stretcher.2705896026 Mar 26 03:22:54 PM PDT 24 Mar 26 03:22:55 PM PDT 24 173485823 ps
T544 /workspace/coverage/default/26.rstmgr_sw_rst.1745952796 Mar 26 03:23:01 PM PDT 24 Mar 26 03:23:03 PM PDT 24 274246226 ps
T545 /workspace/coverage/default/36.rstmgr_stress_all.735832248 Mar 26 03:22:57 PM PDT 24 Mar 26 03:23:07 PM PDT 24 3007141232 ps
T546 /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2123632975 Mar 26 03:22:08 PM PDT 24 Mar 26 03:22:09 PM PDT 24 161413617 ps
T70 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4273757398 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:52 PM PDT 24 146495959 ps
T71 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2738302596 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:52 PM PDT 24 73287921 ps
T72 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1236579939 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:42 PM PDT 24 201496178 ps
T73 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.392768613 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:42 PM PDT 24 769902749 ps
T74 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3548833530 Mar 26 02:39:43 PM PDT 24 Mar 26 02:39:44 PM PDT 24 100906032 ps
T75 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2618020347 Mar 26 02:39:41 PM PDT 24 Mar 26 02:39:42 PM PDT 24 99316285 ps
T97 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1711402510 Mar 26 02:39:38 PM PDT 24 Mar 26 02:39:40 PM PDT 24 103776448 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2696590709 Mar 26 02:39:38 PM PDT 24 Mar 26 02:39:40 PM PDT 24 223666702 ps
T126 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.497048754 Mar 26 02:39:28 PM PDT 24 Mar 26 02:39:29 PM PDT 24 139401183 ps
T98 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.857289907 Mar 26 02:39:55 PM PDT 24 Mar 26 02:39:57 PM PDT 24 114899253 ps
T103 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1933029517 Mar 26 02:39:41 PM PDT 24 Mar 26 02:39:43 PM PDT 24 505247620 ps
T125 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3379987460 Mar 26 02:39:41 PM PDT 24 Mar 26 02:39:47 PM PDT 24 485992677 ps
T117 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2601007500 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:54 PM PDT 24 80323588 ps
T99 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1757465395 Mar 26 02:39:54 PM PDT 24 Mar 26 02:39:56 PM PDT 24 505743646 ps
T100 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1582894205 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:41 PM PDT 24 215982340 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2768026514 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:41 PM PDT 24 130613438 ps
T141 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.600336248 Mar 26 02:39:25 PM PDT 24 Mar 26 02:39:33 PM PDT 24 1547825148 ps
T118 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1262742768 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:41 PM PDT 24 149695054 ps
T104 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1871439702 Mar 26 02:39:37 PM PDT 24 Mar 26 02:39:41 PM PDT 24 895784731 ps
T119 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.39387945 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:41 PM PDT 24 227536139 ps
T120 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.290390546 Mar 26 02:39:43 PM PDT 24 Mar 26 02:39:44 PM PDT 24 124411192 ps
T101 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.203802322 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:54 PM PDT 24 115364361 ps
T102 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2462338874 Mar 26 02:39:41 PM PDT 24 Mar 26 02:39:43 PM PDT 24 131231963 ps
T121 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1850468517 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:52 PM PDT 24 277953836 ps
T108 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2212503184 Mar 26 02:39:42 PM PDT 24 Mar 26 02:39:43 PM PDT 24 68823202 ps
T105 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3674601232 Mar 26 02:39:55 PM PDT 24 Mar 26 02:39:57 PM PDT 24 122235029 ps
T122 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1138648627 Mar 26 02:39:42 PM PDT 24 Mar 26 02:39:43 PM PDT 24 70855585 ps
T128 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2824689640 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:54 PM PDT 24 958297204 ps
T106 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2022594097 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:41 PM PDT 24 147074728 ps
T549 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3957987778 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:53 PM PDT 24 86081212 ps
T123 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1880970566 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:53 PM PDT 24 79871966 ps
T127 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.79502114 Mar 26 02:39:38 PM PDT 24 Mar 26 02:39:40 PM PDT 24 425868772 ps
T134 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.29478342 Mar 26 02:39:40 PM PDT 24 Mar 26 02:39:44 PM PDT 24 524942990 ps
T135 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1384503743 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:55 PM PDT 24 202868748 ps
T550 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3140411266 Mar 26 02:39:53 PM PDT 24 Mar 26 02:39:55 PM PDT 24 185450258 ps
T551 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3544586393 Mar 26 02:39:26 PM PDT 24 Mar 26 02:39:27 PM PDT 24 185739295 ps
T124 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2505958584 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:52 PM PDT 24 261790766 ps
T552 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3600237678 Mar 26 02:39:55 PM PDT 24 Mar 26 02:39:58 PM PDT 24 489568327 ps
T132 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1221675748 Mar 26 02:39:41 PM PDT 24 Mar 26 02:39:43 PM PDT 24 419532522 ps
T553 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2281301088 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:55 PM PDT 24 475860789 ps
T554 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4070784828 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:52 PM PDT 24 154533746 ps
T555 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4235163480 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:52 PM PDT 24 126914599 ps
T556 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3607691109 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:42 PM PDT 24 136189825 ps
T130 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1101195742 Mar 26 02:39:43 PM PDT 24 Mar 26 02:39:45 PM PDT 24 851713095 ps
T557 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3715229716 Mar 26 02:39:37 PM PDT 24 Mar 26 02:39:39 PM PDT 24 144024364 ps
T558 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2594880229 Mar 26 02:39:43 PM PDT 24 Mar 26 02:39:45 PM PDT 24 203233265 ps
T559 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3220924189 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:54 PM PDT 24 123700202 ps
T560 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2647967424 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:54 PM PDT 24 75327924 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.88391201 Mar 26 02:39:26 PM PDT 24 Mar 26 02:39:27 PM PDT 24 93865128 ps
T562 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3963036445 Mar 26 02:39:43 PM PDT 24 Mar 26 02:39:44 PM PDT 24 72582159 ps
T563 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3522923465 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:53 PM PDT 24 252490526 ps
T564 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1917321750 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:54 PM PDT 24 59659440 ps
T565 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2107438668 Mar 26 02:39:48 PM PDT 24 Mar 26 02:39:50 PM PDT 24 223582994 ps
T566 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3081899090 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:40 PM PDT 24 61277581 ps
T567 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1189580935 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:41 PM PDT 24 110236011 ps
T568 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2614674872 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:52 PM PDT 24 79066708 ps
T569 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1223189126 Mar 26 02:39:38 PM PDT 24 Mar 26 02:39:49 PM PDT 24 2289298969 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1861203294 Mar 26 02:39:42 PM PDT 24 Mar 26 02:39:51 PM PDT 24 2290222842 ps
T571 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2455806157 Mar 26 02:39:25 PM PDT 24 Mar 26 02:39:28 PM PDT 24 402691094 ps
T572 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1878160874 Mar 26 02:39:49 PM PDT 24 Mar 26 02:39:51 PM PDT 24 141985796 ps
T573 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.255498162 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:47 PM PDT 24 1533161304 ps
T574 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3225843169 Mar 26 02:39:42 PM PDT 24 Mar 26 02:39:44 PM PDT 24 112912473 ps
T575 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3882598263 Mar 26 02:39:41 PM PDT 24 Mar 26 02:39:42 PM PDT 24 244830983 ps
T576 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.749115647 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:57 PM PDT 24 484209159 ps
T577 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.550996641 Mar 26 02:39:43 PM PDT 24 Mar 26 02:39:44 PM PDT 24 65402667 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2590970184 Mar 26 02:39:42 PM PDT 24 Mar 26 02:39:44 PM PDT 24 262992815 ps
T139 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.511170426 Mar 26 02:39:42 PM PDT 24 Mar 26 02:39:45 PM PDT 24 895323531 ps
T133 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.115197765 Mar 26 02:39:58 PM PDT 24 Mar 26 02:40:02 PM PDT 24 785242002 ps
T109 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1079292679 Mar 26 02:39:43 PM PDT 24 Mar 26 02:39:45 PM PDT 24 159747596 ps
T579 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2084425130 Mar 26 02:39:42 PM PDT 24 Mar 26 02:39:44 PM PDT 24 475036021 ps
T580 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.387250824 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:53 PM PDT 24 492418135 ps
T129 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1095306994 Mar 26 02:39:26 PM PDT 24 Mar 26 02:39:29 PM PDT 24 925333010 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1714212999 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:40 PM PDT 24 151246856 ps
T582 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3115559915 Mar 26 02:39:44 PM PDT 24 Mar 26 02:39:46 PM PDT 24 480827502 ps
T583 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2813122979 Mar 26 02:39:41 PM PDT 24 Mar 26 02:39:41 PM PDT 24 63415903 ps
T584 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2179370400 Mar 26 02:39:45 PM PDT 24 Mar 26 02:39:47 PM PDT 24 81022839 ps
T585 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2114243496 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:53 PM PDT 24 129234386 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.974816844 Mar 26 02:39:40 PM PDT 24 Mar 26 02:39:41 PM PDT 24 174577622 ps
T587 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1819574393 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:55 PM PDT 24 203357429 ps
T588 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2214265865 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:54 PM PDT 24 142166667 ps
T131 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3721808566 Mar 26 02:39:55 PM PDT 24 Mar 26 02:39:57 PM PDT 24 476983405 ps
T589 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2862716108 Mar 26 02:39:46 PM PDT 24 Mar 26 02:39:48 PM PDT 24 226857570 ps
T590 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4242945356 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:57 PM PDT 24 470109517 ps
T591 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1181030677 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:53 PM PDT 24 323916906 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4131376971 Mar 26 02:39:41 PM PDT 24 Mar 26 02:39:42 PM PDT 24 100159272 ps
T140 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1114416454 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:56 PM PDT 24 781335237 ps
T593 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2967570642 Mar 26 02:39:40 PM PDT 24 Mar 26 02:39:41 PM PDT 24 96151956 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3653968198 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:41 PM PDT 24 237481364 ps
T595 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2200160125 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:52 PM PDT 24 76902256 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.765198497 Mar 26 02:39:54 PM PDT 24 Mar 26 02:39:57 PM PDT 24 124622430 ps
T597 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2405585929 Mar 26 02:39:43 PM PDT 24 Mar 26 02:39:46 PM PDT 24 400041273 ps
T598 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4230075556 Mar 26 02:39:42 PM PDT 24 Mar 26 02:39:45 PM PDT 24 469113933 ps
T599 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1107649546 Mar 26 02:39:38 PM PDT 24 Mar 26 02:39:39 PM PDT 24 87829258 ps
T600 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1743924472 Mar 26 02:39:58 PM PDT 24 Mar 26 02:40:01 PM PDT 24 880584616 ps
T601 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2512179618 Mar 26 02:39:29 PM PDT 24 Mar 26 02:39:32 PM PDT 24 126819795 ps
T602 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1056141499 Mar 26 02:39:56 PM PDT 24 Mar 26 02:39:57 PM PDT 24 131706260 ps
T603 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2252446088 Mar 26 02:39:39 PM PDT 24 Mar 26 02:39:40 PM PDT 24 64998585 ps
T604 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2004274954 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:54 PM PDT 24 72069120 ps
T605 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3523006723 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:54 PM PDT 24 79605279 ps
T110 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1284317071 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:51 PM PDT 24 62320073 ps
T606 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1528559582 Mar 26 02:39:40 PM PDT 24 Mar 26 02:39:43 PM PDT 24 324900499 ps
T607 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.792688372 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:54 PM PDT 24 150368799 ps
T608 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.842675660 Mar 26 02:39:40 PM PDT 24 Mar 26 02:39:41 PM PDT 24 73650663 ps
T609 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.286403790 Mar 26 02:39:40 PM PDT 24 Mar 26 02:39:41 PM PDT 24 90736313 ps
T610 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3065792794 Mar 26 02:40:07 PM PDT 24 Mar 26 02:40:10 PM PDT 24 116038730 ps
T611 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3401925218 Mar 26 02:39:50 PM PDT 24 Mar 26 02:39:52 PM PDT 24 429363159 ps
T612 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4226279773 Mar 26 02:39:41 PM PDT 24 Mar 26 02:39:42 PM PDT 24 157075366 ps
T613 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4271483217 Mar 26 02:39:49 PM PDT 24 Mar 26 02:39:51 PM PDT 24 194274871 ps
T614 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1658610252 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:54 PM PDT 24 74365282 ps
T615 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1016545581 Mar 26 02:39:42 PM PDT 24 Mar 26 02:39:44 PM PDT 24 81738812 ps
T616 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3935315691 Mar 26 02:39:28 PM PDT 24 Mar 26 02:39:30 PM PDT 24 246987139 ps
T617 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2833642755 Mar 26 02:39:51 PM PDT 24 Mar 26 02:39:55 PM PDT 24 938585743 ps
T618 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1464825275 Mar 26 02:39:52 PM PDT 24 Mar 26 02:39:54 PM PDT 24 121868055 ps
T619 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3719240782 Mar 26 02:39:54 PM PDT 24 Mar 26 02:39:58 PM PDT 24 166369756 ps
T620 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.993102503 Mar 26 02:39:40 PM PDT 24 Mar 26 02:39:42 PM PDT 24 130497176 ps

Test location /workspace/coverage/default/41.rstmgr_stress_all.2773989391
Short name T4
Test name
Test status
Simulation time 5697574113 ps
CPU time 20.49 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:31 PM PDT 24
Peak memory 201124 kb
Host smart-3e4533ca-e169-44ea-9e8a-18e73db691d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773989391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2773989391
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3367508791
Short name T89
Test name
Test status
Simulation time 357777394 ps
CPU time 2.2 seconds
Started Mar 26 03:22:26 PM PDT 24
Finished Mar 26 03:22:29 PM PDT 24
Peak memory 209120 kb
Host smart-62c7f2de-8422-41a5-94aa-3b277f58703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367508791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3367508791
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1236579939
Short name T72
Test name
Test status
Simulation time 201496178 ps
CPU time 2.07 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:42 PM PDT 24
Peak memory 208992 kb
Host smart-a287cebc-447a-4f35-b1a7-b92ba1abc222
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236579939 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1236579939
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2542320213
Short name T77
Test name
Test status
Simulation time 16836954902 ps
CPU time 25.71 seconds
Started Mar 26 03:21:59 PM PDT 24
Finished Mar 26 03:22:26 PM PDT 24
Peak memory 217784 kb
Host smart-73c0bc2b-08ab-4252-98b1-81c9015f1787
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542320213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2542320213
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.995597103
Short name T17
Test name
Test status
Simulation time 1221451264 ps
CPU time 5.61 seconds
Started Mar 26 03:21:56 PM PDT 24
Finished Mar 26 03:22:02 PM PDT 24
Peak memory 218060 kb
Host smart-7349009c-351f-4bd8-9e71-3be004b2c84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995597103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.995597103
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.392768613
Short name T73
Test name
Test status
Simulation time 769902749 ps
CPU time 2.79 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:42 PM PDT 24
Peak memory 200684 kb
Host smart-ea59e887-7f78-4d4b-8944-47aeed44fe63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392768613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
392768613
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1077598061
Short name T56
Test name
Test status
Simulation time 79400973 ps
CPU time 0.81 seconds
Started Mar 26 03:21:54 PM PDT 24
Finished Mar 26 03:21:56 PM PDT 24
Peak memory 200672 kb
Host smart-dc76f211-fb8f-4ca3-af80-5f55cdec88ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077598061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1077598061
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1841384726
Short name T95
Test name
Test status
Simulation time 4590701956 ps
CPU time 23.77 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 201076 kb
Host smart-d429a3ff-4a66-412c-bfe4-5255d2be7966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841384726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1841384726
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1160143768
Short name T213
Test name
Test status
Simulation time 109649893 ps
CPU time 1.02 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 200816 kb
Host smart-0dcb81b8-4981-4394-90c7-bfebb762e72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160143768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1160143768
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3928095879
Short name T143
Test name
Test status
Simulation time 146525516 ps
CPU time 1.16 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200800 kb
Host smart-4fdeb55d-bf67-4500-b85d-e821d071ac7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928095879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3928095879
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1471562878
Short name T28
Test name
Test status
Simulation time 2373346280 ps
CPU time 8.25 seconds
Started Mar 26 03:23:22 PM PDT 24
Finished Mar 26 03:23:30 PM PDT 24
Peak memory 222712 kb
Host smart-0cd038c5-d1f5-4079-b6b0-1321b59567a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471562878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1471562878
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.79502114
Short name T127
Test name
Test status
Simulation time 425868772 ps
CPU time 1.86 seconds
Started Mar 26 02:39:38 PM PDT 24
Finished Mar 26 02:39:40 PM PDT 24
Peak memory 200536 kb
Host smart-1252dfa8-ad6e-41c2-a322-6e8891e540e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79502114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.79502114
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4003790965
Short name T37
Test name
Test status
Simulation time 1906003844 ps
CPU time 7.02 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:47 PM PDT 24
Peak memory 222572 kb
Host smart-c6afaeee-ca2a-4c50-b174-cdad0402262c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003790965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4003790965
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2282083366
Short name T60
Test name
Test status
Simulation time 2174546537 ps
CPU time 8.57 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 218100 kb
Host smart-3f985264-53a1-4f86-9078-45a842b6134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282083366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2282083366
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2618020347
Short name T75
Test name
Test status
Simulation time 99316285 ps
CPU time 1.61 seconds
Started Mar 26 02:39:41 PM PDT 24
Finished Mar 26 02:39:42 PM PDT 24
Peak memory 211052 kb
Host smart-ec191c29-edee-4c87-846b-c92e7eeb6db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618020347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2618020347
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.39387945
Short name T119
Test name
Test status
Simulation time 227536139 ps
CPU time 1.52 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200676 kb
Host smart-fbd5eec8-47b9-42e7-96e7-7e4990e3373e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same
_csr_outstanding.39387945
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.439451412
Short name T20
Test name
Test status
Simulation time 146408003 ps
CPU time 0.86 seconds
Started Mar 26 03:21:57 PM PDT 24
Finished Mar 26 03:21:58 PM PDT 24
Peak memory 200656 kb
Host smart-44bac9ee-302a-45b5-b79c-d7e9aa6a72a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439451412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.439451412
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1287415359
Short name T190
Test name
Test status
Simulation time 244027122 ps
CPU time 1.02 seconds
Started Mar 26 03:22:08 PM PDT 24
Finished Mar 26 03:22:10 PM PDT 24
Peak memory 218096 kb
Host smart-a7509d29-07fa-461f-baa6-55b279aac1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287415359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1287415359
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1095306994
Short name T129
Test name
Test status
Simulation time 925333010 ps
CPU time 3.27 seconds
Started Mar 26 02:39:26 PM PDT 24
Finished Mar 26 02:39:29 PM PDT 24
Peak memory 200628 kb
Host smart-3693bce5-2c33-4606-9de5-b83a9c8167a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095306994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1095306994
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2455806157
Short name T571
Test name
Test status
Simulation time 402691094 ps
CPU time 2.63 seconds
Started Mar 26 02:39:25 PM PDT 24
Finished Mar 26 02:39:28 PM PDT 24
Peak memory 200552 kb
Host smart-ea96b4e0-7ce4-4669-a083-e7e7409a3684
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455806157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
455806157
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.600336248
Short name T141
Test name
Test status
Simulation time 1547825148 ps
CPU time 8.01 seconds
Started Mar 26 02:39:25 PM PDT 24
Finished Mar 26 02:39:33 PM PDT 24
Peak memory 200572 kb
Host smart-402bf6ad-df1e-41f4-885c-d77da84c53bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600336248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.600336248
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.497048754
Short name T126
Test name
Test status
Simulation time 139401183 ps
CPU time 0.99 seconds
Started Mar 26 02:39:28 PM PDT 24
Finished Mar 26 02:39:29 PM PDT 24
Peak memory 200372 kb
Host smart-d00b2345-2ec9-41ad-925c-49332a431c3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497048754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.497048754
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3544586393
Short name T551
Test name
Test status
Simulation time 185739295 ps
CPU time 1.29 seconds
Started Mar 26 02:39:26 PM PDT 24
Finished Mar 26 02:39:27 PM PDT 24
Peak memory 208676 kb
Host smart-ddb4a278-aae3-4a77-b0d3-14396bee6a31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544586393 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3544586393
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.88391201
Short name T561
Test name
Test status
Simulation time 93865128 ps
CPU time 0.92 seconds
Started Mar 26 02:39:26 PM PDT 24
Finished Mar 26 02:39:27 PM PDT 24
Peak memory 200372 kb
Host smart-cec097e0-18d7-45ed-ab2a-5eca919d9001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88391201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.88391201
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3935315691
Short name T616
Test name
Test status
Simulation time 246987139 ps
CPU time 1.72 seconds
Started Mar 26 02:39:28 PM PDT 24
Finished Mar 26 02:39:30 PM PDT 24
Peak memory 200572 kb
Host smart-d3cef69a-1d61-437d-8aa0-d020ab5777a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935315691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3935315691
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2512179618
Short name T601
Test name
Test status
Simulation time 126819795 ps
CPU time 1.82 seconds
Started Mar 26 02:39:29 PM PDT 24
Finished Mar 26 02:39:32 PM PDT 24
Peak memory 211344 kb
Host smart-1b54e1af-b0b7-4e7b-b28b-821b717d2e21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512179618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2512179618
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1189580935
Short name T567
Test name
Test status
Simulation time 110236011 ps
CPU time 1.36 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200444 kb
Host smart-457fb139-bf7f-4954-8d8f-73e4f3cd464f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189580935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
189580935
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1223189126
Short name T569
Test name
Test status
Simulation time 2289298969 ps
CPU time 10.25 seconds
Started Mar 26 02:39:38 PM PDT 24
Finished Mar 26 02:39:49 PM PDT 24
Peak memory 200744 kb
Host smart-70f38586-c04c-47ed-9261-32b972fed5c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223189126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
223189126
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2967570642
Short name T593
Test name
Test status
Simulation time 96151956 ps
CPU time 0.85 seconds
Started Mar 26 02:39:40 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200336 kb
Host smart-363b099f-e881-43b1-801c-783e465545da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967570642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
967570642
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.842675660
Short name T608
Test name
Test status
Simulation time 73650663 ps
CPU time 0.81 seconds
Started Mar 26 02:39:40 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200320 kb
Host smart-bb3b502e-3202-47de-af6e-e84d607a886c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842675660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.842675660
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1871439702
Short name T104
Test name
Test status
Simulation time 895784731 ps
CPU time 3.35 seconds
Started Mar 26 02:39:37 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200628 kb
Host smart-28dba283-6435-4223-8128-ea0e812f1a18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871439702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.1871439702
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1878160874
Short name T572
Test name
Test status
Simulation time 141985796 ps
CPU time 1.13 seconds
Started Mar 26 02:39:49 PM PDT 24
Finished Mar 26 02:39:51 PM PDT 24
Peak memory 208640 kb
Host smart-1b17b0e8-a10b-44ae-a6e4-7c1e27a72697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878160874 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1878160874
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1917321750
Short name T564
Test name
Test status
Simulation time 59659440 ps
CPU time 0.78 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 200368 kb
Host smart-a8a03f90-9302-450b-982b-371a246be533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917321750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1917321750
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2200160125
Short name T595
Test name
Test status
Simulation time 76902256 ps
CPU time 1.01 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:52 PM PDT 24
Peak memory 200452 kb
Host smart-87170115-600c-45ea-9ffb-523b7422f387
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200160125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2200160125
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2862716108
Short name T589
Test name
Test status
Simulation time 226857570 ps
CPU time 2.04 seconds
Started Mar 26 02:39:46 PM PDT 24
Finished Mar 26 02:39:48 PM PDT 24
Peak memory 211928 kb
Host smart-715fbe63-fb4a-4a84-a0f6-1448b08b5c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862716108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2862716108
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3401925218
Short name T611
Test name
Test status
Simulation time 429363159 ps
CPU time 2.01 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:52 PM PDT 24
Peak memory 200612 kb
Host smart-b773596e-8917-497f-b4f4-8bc30cd174dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401925218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3401925218
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1464825275
Short name T618
Test name
Test status
Simulation time 121868055 ps
CPU time 1 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 200416 kb
Host smart-177a7aec-bf79-403b-8f74-16c078eae776
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464825275 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1464825275
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3523006723
Short name T605
Test name
Test status
Simulation time 79605279 ps
CPU time 0.92 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 200348 kb
Host smart-ab7c8328-6ffb-48f0-95d4-bc97034982e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523006723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3523006723
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2505958584
Short name T124
Test name
Test status
Simulation time 261790766 ps
CPU time 1.54 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:52 PM PDT 24
Peak memory 200588 kb
Host smart-ef0639ed-de94-471b-ad33-7fe08e923d5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505958584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2505958584
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.857289907
Short name T98
Test name
Test status
Simulation time 114899253 ps
CPU time 1.55 seconds
Started Mar 26 02:39:55 PM PDT 24
Finished Mar 26 02:39:57 PM PDT 24
Peak memory 211508 kb
Host smart-83295831-f6af-49f2-a1c1-f97b3976eccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857289907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.857289907
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.115197765
Short name T133
Test name
Test status
Simulation time 785242002 ps
CPU time 3.01 seconds
Started Mar 26 02:39:58 PM PDT 24
Finished Mar 26 02:40:02 PM PDT 24
Peak memory 200588 kb
Host smart-83eb3d6b-6311-4524-b650-68a01c69c664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115197765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.115197765
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3065792794
Short name T610
Test name
Test status
Simulation time 116038730 ps
CPU time 1.03 seconds
Started Mar 26 02:40:07 PM PDT 24
Finished Mar 26 02:40:10 PM PDT 24
Peak memory 200500 kb
Host smart-2cb9a68f-48b6-465d-8cf8-0863c77f3d4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065792794 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3065792794
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2614674872
Short name T568
Test name
Test status
Simulation time 79066708 ps
CPU time 0.83 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:52 PM PDT 24
Peak memory 200352 kb
Host smart-93930d3c-5623-4304-b220-8a9459458eaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614674872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2614674872
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.4273757398
Short name T70
Test name
Test status
Simulation time 146495959 ps
CPU time 1.1 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:52 PM PDT 24
Peak memory 200444 kb
Host smart-c9f2b4cc-f76c-4609-969c-ce4b0dda62ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273757398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.4273757398
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3522923465
Short name T563
Test name
Test status
Simulation time 252490526 ps
CPU time 1.96 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:53 PM PDT 24
Peak memory 208820 kb
Host smart-44142a30-8834-4b95-8ea5-09cb85d1b99c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522923465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3522923465
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2833642755
Short name T617
Test name
Test status
Simulation time 938585743 ps
CPU time 3.02 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:55 PM PDT 24
Peak memory 200624 kb
Host smart-c9d4def3-9b6c-4ea9-a7b2-246420c577a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833642755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2833642755
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4070784828
Short name T554
Test name
Test status
Simulation time 154533746 ps
CPU time 1.41 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:52 PM PDT 24
Peak memory 208640 kb
Host smart-4fe23414-39a6-4276-9732-adf965fee934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070784828 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4070784828
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2738302596
Short name T71
Test name
Test status
Simulation time 73287921 ps
CPU time 0.84 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:52 PM PDT 24
Peak memory 200328 kb
Host smart-365f0a50-3dcc-4aa1-8a36-160ffd289b73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738302596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2738302596
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2601007500
Short name T117
Test name
Test status
Simulation time 80323588 ps
CPU time 0.94 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 200324 kb
Host smart-13aa36f8-75d9-4b7c-9b1e-2a5e6c5361ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601007500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2601007500
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.749115647
Short name T576
Test name
Test status
Simulation time 484209159 ps
CPU time 4.01 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:57 PM PDT 24
Peak memory 208708 kb
Host smart-013b27f3-e256-439c-869a-bfc29bbc571d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749115647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.749115647
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1757465395
Short name T99
Test name
Test status
Simulation time 505743646 ps
CPU time 2.33 seconds
Started Mar 26 02:39:54 PM PDT 24
Finished Mar 26 02:39:56 PM PDT 24
Peak memory 200636 kb
Host smart-e5139fd5-e771-4215-a447-817bcfba0e15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757465395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1757465395
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.4235163480
Short name T555
Test name
Test status
Simulation time 126914599 ps
CPU time 1 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:52 PM PDT 24
Peak memory 200428 kb
Host smart-d821a28c-3c00-40dd-a944-ba6c796a9177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235163480 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.4235163480
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1284317071
Short name T110
Test name
Test status
Simulation time 62320073 ps
CPU time 0.81 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:51 PM PDT 24
Peak memory 200260 kb
Host smart-0cd6734e-b3d7-447b-ba72-e43eb6d7136f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284317071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1284317071
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1056141499
Short name T602
Test name
Test status
Simulation time 131706260 ps
CPU time 1.22 seconds
Started Mar 26 02:39:56 PM PDT 24
Finished Mar 26 02:39:57 PM PDT 24
Peak memory 200632 kb
Host smart-79617f15-0042-4c83-b9c3-b9a9700c126a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056141499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1056141499
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2281301088
Short name T553
Test name
Test status
Simulation time 475860789 ps
CPU time 2.9 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:55 PM PDT 24
Peak memory 208860 kb
Host smart-c771fb9a-8454-46e3-b792-b7faa0d17078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281301088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2281301088
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2824689640
Short name T128
Test name
Test status
Simulation time 958297204 ps
CPU time 3.24 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 208708 kb
Host smart-0a888be4-7495-4343-8f04-115ef125f624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824689640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2824689640
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.203802322
Short name T101
Test name
Test status
Simulation time 115364361 ps
CPU time 1.26 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 208644 kb
Host smart-13d7519b-9bd1-4029-a978-bf8d44c19105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203802322 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.203802322
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2004274954
Short name T604
Test name
Test status
Simulation time 72069120 ps
CPU time 0.82 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 200376 kb
Host smart-58767205-0223-4617-b405-57f072a9c679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004274954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2004274954
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1850468517
Short name T121
Test name
Test status
Simulation time 277953836 ps
CPU time 1.68 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:52 PM PDT 24
Peak memory 200628 kb
Host smart-769d93bf-865b-4076-aa7e-f94519960ee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850468517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1850468517
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.765198497
Short name T596
Test name
Test status
Simulation time 124622430 ps
CPU time 1.74 seconds
Started Mar 26 02:39:54 PM PDT 24
Finished Mar 26 02:39:57 PM PDT 24
Peak memory 208884 kb
Host smart-2e7e12ef-6d46-489f-98b6-19e05df49107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765198497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.765198497
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3721808566
Short name T131
Test name
Test status
Simulation time 476983405 ps
CPU time 2.02 seconds
Started Mar 26 02:39:55 PM PDT 24
Finished Mar 26 02:39:57 PM PDT 24
Peak memory 200584 kb
Host smart-7940cb5b-e503-4518-a06a-b48eceecccea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721808566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3721808566
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3674601232
Short name T105
Test name
Test status
Simulation time 122235029 ps
CPU time 0.98 seconds
Started Mar 26 02:39:55 PM PDT 24
Finished Mar 26 02:39:57 PM PDT 24
Peak memory 200412 kb
Host smart-8d273490-6a9e-4160-959b-62e50b9bc52f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674601232 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3674601232
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2647967424
Short name T560
Test name
Test status
Simulation time 75327924 ps
CPU time 0.78 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 200336 kb
Host smart-9e261c1c-7599-49b8-a3e3-878e17240652
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647967424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2647967424
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2107438668
Short name T565
Test name
Test status
Simulation time 223582994 ps
CPU time 1.58 seconds
Started Mar 26 02:39:48 PM PDT 24
Finished Mar 26 02:39:50 PM PDT 24
Peak memory 200576 kb
Host smart-fb6244ee-eed9-43c5-a0fa-7ddd0a74992f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107438668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2107438668
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1384503743
Short name T135
Test name
Test status
Simulation time 202868748 ps
CPU time 1.55 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:55 PM PDT 24
Peak memory 208700 kb
Host smart-667404d4-cb77-4a84-9ebb-17f9b1617eea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384503743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1384503743
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1114416454
Short name T140
Test name
Test status
Simulation time 781335237 ps
CPU time 2.72 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:56 PM PDT 24
Peak memory 200604 kb
Host smart-dbf73289-9f47-484e-87ce-1d497df244be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114416454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1114416454
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.792688372
Short name T607
Test name
Test status
Simulation time 150368799 ps
CPU time 1.42 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 212212 kb
Host smart-c1303ad1-7589-4762-bd86-73b45f4dbc49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792688372 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.792688372
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1658610252
Short name T614
Test name
Test status
Simulation time 74365282 ps
CPU time 0.8 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 200372 kb
Host smart-74d19367-6a67-40b9-b60e-eb0c7d98a5f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658610252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1658610252
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1819574393
Short name T587
Test name
Test status
Simulation time 203357429 ps
CPU time 1.56 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:55 PM PDT 24
Peak memory 200600 kb
Host smart-34b138cb-59fe-4729-ada6-bd64ef4f11e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819574393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1819574393
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4242945356
Short name T590
Test name
Test status
Simulation time 470109517 ps
CPU time 3.6 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:57 PM PDT 24
Peak memory 208860 kb
Host smart-c910d1b6-6b7a-4d3d-bd39-4b0bc438133d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242945356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4242945356
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1743924472
Short name T600
Test name
Test status
Simulation time 880584616 ps
CPU time 3.16 seconds
Started Mar 26 02:39:58 PM PDT 24
Finished Mar 26 02:40:01 PM PDT 24
Peak memory 200536 kb
Host smart-ae1f5885-7984-4368-beff-f857f59f1a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743924472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1743924472
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3140411266
Short name T550
Test name
Test status
Simulation time 185450258 ps
CPU time 1.22 seconds
Started Mar 26 02:39:53 PM PDT 24
Finished Mar 26 02:39:55 PM PDT 24
Peak memory 200452 kb
Host smart-617f16b2-506d-42dc-8c63-d38ce82a452a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140411266 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3140411266
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1880970566
Short name T123
Test name
Test status
Simulation time 79871966 ps
CPU time 0.86 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:53 PM PDT 24
Peak memory 200368 kb
Host smart-c92543d0-7a44-4d82-a6a5-53bd853d673b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880970566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1880970566
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2214265865
Short name T588
Test name
Test status
Simulation time 142166667 ps
CPU time 1.19 seconds
Started Mar 26 02:39:52 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 200460 kb
Host smart-18b62316-e305-4216-870b-b8d1e459233c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214265865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2214265865
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1181030677
Short name T591
Test name
Test status
Simulation time 323916906 ps
CPU time 2.28 seconds
Started Mar 26 02:39:50 PM PDT 24
Finished Mar 26 02:39:53 PM PDT 24
Peak memory 208784 kb
Host smart-e9737cc1-6b9e-4a6c-a95a-d7e3656f4d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181030677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1181030677
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.387250824
Short name T580
Test name
Test status
Simulation time 492418135 ps
CPU time 1.92 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:53 PM PDT 24
Peak memory 200672 kb
Host smart-a0c2ce52-5522-44fd-9014-ee39991bb30c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387250824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.387250824
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2114243496
Short name T585
Test name
Test status
Simulation time 129234386 ps
CPU time 1.06 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:53 PM PDT 24
Peak memory 200500 kb
Host smart-889c5a01-846d-4575-8d3c-25308806fa6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114243496 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2114243496
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3957987778
Short name T549
Test name
Test status
Simulation time 86081212 ps
CPU time 0.83 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:53 PM PDT 24
Peak memory 200232 kb
Host smart-748b2ce6-17d6-4a0d-ad9b-872b7e71fe1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957987778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3957987778
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3220924189
Short name T559
Test name
Test status
Simulation time 123700202 ps
CPU time 1.28 seconds
Started Mar 26 02:39:51 PM PDT 24
Finished Mar 26 02:39:54 PM PDT 24
Peak memory 200528 kb
Host smart-b5bc5db0-d885-4da7-8f29-6aa8025b7c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220924189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3220924189
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3719240782
Short name T619
Test name
Test status
Simulation time 166369756 ps
CPU time 2.24 seconds
Started Mar 26 02:39:54 PM PDT 24
Finished Mar 26 02:39:58 PM PDT 24
Peak memory 208780 kb
Host smart-876e9982-485d-4cc8-b580-c17f204d4c0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719240782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3719240782
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3600237678
Short name T552
Test name
Test status
Simulation time 489568327 ps
CPU time 1.83 seconds
Started Mar 26 02:39:55 PM PDT 24
Finished Mar 26 02:39:58 PM PDT 24
Peak memory 200656 kb
Host smart-f86d63b3-d4ff-42df-86a0-fa28e6cf97ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600237678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3600237678
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3653968198
Short name T594
Test name
Test status
Simulation time 237481364 ps
CPU time 1.64 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200480 kb
Host smart-d98a75ca-c33c-4fff-8446-c6dcae9ddc17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653968198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
653968198
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.255498162
Short name T573
Test name
Test status
Simulation time 1533161304 ps
CPU time 7.89 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:47 PM PDT 24
Peak memory 200588 kb
Host smart-1c01962d-b02c-4e61-9092-b90272e1d8e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255498162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.255498162
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2768026514
Short name T548
Test name
Test status
Simulation time 130613438 ps
CPU time 0.92 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200356 kb
Host smart-2b616d1b-d655-4732-af6f-4cb518893a13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768026514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
768026514
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.286403790
Short name T609
Test name
Test status
Simulation time 90736313 ps
CPU time 0.93 seconds
Started Mar 26 02:39:40 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200444 kb
Host smart-16861dcf-ec94-4a43-bcc0-49fac969c853
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286403790 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.286403790
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2252446088
Short name T603
Test name
Test status
Simulation time 64998585 ps
CPU time 0.79 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:40 PM PDT 24
Peak memory 200388 kb
Host smart-63a530fb-2e65-41f4-b17d-ac17d180157a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252446088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2252446088
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1714212999
Short name T581
Test name
Test status
Simulation time 151246856 ps
CPU time 1.25 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:40 PM PDT 24
Peak memory 200424 kb
Host smart-8b18c431-12b4-4678-b93b-af7a3945de8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714212999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1714212999
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1528559582
Short name T606
Test name
Test status
Simulation time 324900499 ps
CPU time 2.59 seconds
Started Mar 26 02:39:40 PM PDT 24
Finished Mar 26 02:39:43 PM PDT 24
Peak memory 212012 kb
Host smart-6eb79f88-f36f-44f2-9050-c76486f01e65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528559582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1528559582
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1933029517
Short name T103
Test name
Test status
Simulation time 505247620 ps
CPU time 1.85 seconds
Started Mar 26 02:39:41 PM PDT 24
Finished Mar 26 02:39:43 PM PDT 24
Peak memory 200672 kb
Host smart-51acb7af-a2b9-4b3c-bcdd-6ca3f3112af3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933029517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1933029517
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1079292679
Short name T109
Test name
Test status
Simulation time 159747596 ps
CPU time 2.12 seconds
Started Mar 26 02:39:43 PM PDT 24
Finished Mar 26 02:39:45 PM PDT 24
Peak memory 200532 kb
Host smart-8609a8eb-4f2a-4493-8163-97ba478bd4a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079292679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
079292679
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1861203294
Short name T570
Test name
Test status
Simulation time 2290222842 ps
CPU time 9.6 seconds
Started Mar 26 02:39:42 PM PDT 24
Finished Mar 26 02:39:51 PM PDT 24
Peak memory 200572 kb
Host smart-b8c91a25-c3d6-477e-89c2-580574155e4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861203294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
861203294
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4131376971
Short name T592
Test name
Test status
Simulation time 100159272 ps
CPU time 0.88 seconds
Started Mar 26 02:39:41 PM PDT 24
Finished Mar 26 02:39:42 PM PDT 24
Peak memory 200392 kb
Host smart-45ffeab1-ead6-43c9-8955-7824c43ea158
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131376971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
131376971
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.974816844
Short name T586
Test name
Test status
Simulation time 174577622 ps
CPU time 1.54 seconds
Started Mar 26 02:39:40 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 208800 kb
Host smart-a2cbb7c8-2950-4af8-a3ec-11e7442473c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974816844 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.974816844
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1107649546
Short name T599
Test name
Test status
Simulation time 87829258 ps
CPU time 0.89 seconds
Started Mar 26 02:39:38 PM PDT 24
Finished Mar 26 02:39:39 PM PDT 24
Peak memory 200352 kb
Host smart-4c9f5e98-722b-4ec6-9e72-8c4b19432f80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107649546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1107649546
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2590970184
Short name T578
Test name
Test status
Simulation time 262992815 ps
CPU time 1.6 seconds
Started Mar 26 02:39:42 PM PDT 24
Finished Mar 26 02:39:44 PM PDT 24
Peak memory 200556 kb
Host smart-ec5caeeb-92af-4ed1-b5e9-1dc7ebfcfe5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590970184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2590970184
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3607691109
Short name T556
Test name
Test status
Simulation time 136189825 ps
CPU time 2.05 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:42 PM PDT 24
Peak memory 216924 kb
Host smart-f9f9b1af-c95d-4b79-8710-dbb5b4763584
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607691109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3607691109
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2696590709
Short name T547
Test name
Test status
Simulation time 223666702 ps
CPU time 1.64 seconds
Started Mar 26 02:39:38 PM PDT 24
Finished Mar 26 02:39:40 PM PDT 24
Peak memory 208660 kb
Host smart-21355682-d20c-4235-a593-0049a7e88088
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696590709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
696590709
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3379987460
Short name T125
Test name
Test status
Simulation time 485992677 ps
CPU time 6.06 seconds
Started Mar 26 02:39:41 PM PDT 24
Finished Mar 26 02:39:47 PM PDT 24
Peak memory 200564 kb
Host smart-43875c2a-d03b-4ec0-8954-98d624acbd4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379987460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
379987460
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3715229716
Short name T557
Test name
Test status
Simulation time 144024364 ps
CPU time 1.09 seconds
Started Mar 26 02:39:37 PM PDT 24
Finished Mar 26 02:39:39 PM PDT 24
Peak memory 200364 kb
Host smart-afe48a5a-acea-4d2d-b54e-631173abc238
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715229716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
715229716
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2022594097
Short name T106
Test name
Test status
Simulation time 147074728 ps
CPU time 1.2 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 208648 kb
Host smart-ce973e8f-704e-478d-be86-649bf14f20fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022594097 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2022594097
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3081899090
Short name T566
Test name
Test status
Simulation time 61277581 ps
CPU time 0.76 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:40 PM PDT 24
Peak memory 200324 kb
Host smart-3d594184-6885-4e80-8c5e-cda521f02311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081899090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3081899090
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4226279773
Short name T612
Test name
Test status
Simulation time 157075366 ps
CPU time 1.19 seconds
Started Mar 26 02:39:41 PM PDT 24
Finished Mar 26 02:39:42 PM PDT 24
Peak memory 200424 kb
Host smart-8201e547-dcbc-4f51-a742-0095aa81b745
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226279773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4226279773
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1582894205
Short name T100
Test name
Test status
Simulation time 215982340 ps
CPU time 1.6 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200608 kb
Host smart-8194390b-df1d-4921-bc59-be8387d34c9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582894205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1582894205
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.993102503
Short name T620
Test name
Test status
Simulation time 130497176 ps
CPU time 1.05 seconds
Started Mar 26 02:39:40 PM PDT 24
Finished Mar 26 02:39:42 PM PDT 24
Peak memory 200404 kb
Host smart-29835f6e-822d-49be-a9fc-3ce5963a162a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993102503 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.993102503
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2813122979
Short name T583
Test name
Test status
Simulation time 63415903 ps
CPU time 0.77 seconds
Started Mar 26 02:39:41 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200360 kb
Host smart-c6fc1be5-4b9c-48c1-a825-03654220c23c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813122979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2813122979
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3882598263
Short name T575
Test name
Test status
Simulation time 244830983 ps
CPU time 1.63 seconds
Started Mar 26 02:39:41 PM PDT 24
Finished Mar 26 02:39:42 PM PDT 24
Peak memory 200624 kb
Host smart-02fb2f16-9d51-45d9-a3ef-3f9fd7cc4aa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882598263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3882598263
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1711402510
Short name T97
Test name
Test status
Simulation time 103776448 ps
CPU time 1.47 seconds
Started Mar 26 02:39:38 PM PDT 24
Finished Mar 26 02:39:40 PM PDT 24
Peak memory 216872 kb
Host smart-c396a939-782e-48b7-9280-3ee60cd32ff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711402510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1711402510
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1221675748
Short name T132
Test name
Test status
Simulation time 419532522 ps
CPU time 1.88 seconds
Started Mar 26 02:39:41 PM PDT 24
Finished Mar 26 02:39:43 PM PDT 24
Peak memory 200512 kb
Host smart-43613898-b00a-4a32-9156-8b0f88d9218c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221675748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1221675748
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2462338874
Short name T102
Test name
Test status
Simulation time 131231963 ps
CPU time 1.4 seconds
Started Mar 26 02:39:41 PM PDT 24
Finished Mar 26 02:39:43 PM PDT 24
Peak memory 208648 kb
Host smart-2632c958-34d5-49c8-93df-89adf2e0ee8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462338874 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2462338874
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2212503184
Short name T108
Test name
Test status
Simulation time 68823202 ps
CPU time 0.85 seconds
Started Mar 26 02:39:42 PM PDT 24
Finished Mar 26 02:39:43 PM PDT 24
Peak memory 200332 kb
Host smart-0de22e75-a230-4f43-b1b7-4685968369d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212503184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2212503184
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1262742768
Short name T118
Test name
Test status
Simulation time 149695054 ps
CPU time 1.22 seconds
Started Mar 26 02:39:39 PM PDT 24
Finished Mar 26 02:39:41 PM PDT 24
Peak memory 200444 kb
Host smart-ec3e5664-04f3-4aed-bc85-21206dfc85d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262742768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1262742768
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3225843169
Short name T574
Test name
Test status
Simulation time 112912473 ps
CPU time 1.66 seconds
Started Mar 26 02:39:42 PM PDT 24
Finished Mar 26 02:39:44 PM PDT 24
Peak memory 208724 kb
Host smart-241bdfc4-70a3-48d9-85f7-04873cfca18b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225843169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3225843169
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2084425130
Short name T579
Test name
Test status
Simulation time 475036021 ps
CPU time 1.85 seconds
Started Mar 26 02:39:42 PM PDT 24
Finished Mar 26 02:39:44 PM PDT 24
Peak memory 200660 kb
Host smart-6b30c5e0-12f5-4c9e-b013-297ba51d5483
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084425130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2084425130
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4271483217
Short name T613
Test name
Test status
Simulation time 194274871 ps
CPU time 1.36 seconds
Started Mar 26 02:39:49 PM PDT 24
Finished Mar 26 02:39:51 PM PDT 24
Peak memory 208724 kb
Host smart-3af31307-0b33-4feb-9a51-9f449360cfd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271483217 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4271483217
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1138648627
Short name T122
Test name
Test status
Simulation time 70855585 ps
CPU time 0.85 seconds
Started Mar 26 02:39:42 PM PDT 24
Finished Mar 26 02:39:43 PM PDT 24
Peak memory 200380 kb
Host smart-cf71d8df-ba7d-48da-b0c0-477ab51f5289
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138648627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1138648627
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.290390546
Short name T120
Test name
Test status
Simulation time 124411192 ps
CPU time 1.15 seconds
Started Mar 26 02:39:43 PM PDT 24
Finished Mar 26 02:39:44 PM PDT 24
Peak memory 200376 kb
Host smart-f67a0a47-7a68-4b4e-9bcd-73ec4c0f2d58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290390546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.290390546
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.29478342
Short name T134
Test name
Test status
Simulation time 524942990 ps
CPU time 3.53 seconds
Started Mar 26 02:39:40 PM PDT 24
Finished Mar 26 02:39:44 PM PDT 24
Peak memory 208828 kb
Host smart-bbf00ac3-2294-4e64-ae78-a898949b2215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29478342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.29478342
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1101195742
Short name T130
Test name
Test status
Simulation time 851713095 ps
CPU time 2.79 seconds
Started Mar 26 02:39:43 PM PDT 24
Finished Mar 26 02:39:45 PM PDT 24
Peak memory 200660 kb
Host smart-78f20fb5-00a0-4ef1-9c0a-7af65236f519
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101195742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1101195742
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3548833530
Short name T74
Test name
Test status
Simulation time 100906032 ps
CPU time 0.93 seconds
Started Mar 26 02:39:43 PM PDT 24
Finished Mar 26 02:39:44 PM PDT 24
Peak memory 200444 kb
Host smart-b775c5b2-252a-47c5-bcb1-01c667fde9e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548833530 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3548833530
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3963036445
Short name T562
Test name
Test status
Simulation time 72582159 ps
CPU time 0.86 seconds
Started Mar 26 02:39:43 PM PDT 24
Finished Mar 26 02:39:44 PM PDT 24
Peak memory 200308 kb
Host smart-901674b1-36fb-4002-ad27-681b327064f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963036445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3963036445
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1016545581
Short name T615
Test name
Test status
Simulation time 81738812 ps
CPU time 1.03 seconds
Started Mar 26 02:39:42 PM PDT 24
Finished Mar 26 02:39:44 PM PDT 24
Peak memory 200372 kb
Host smart-b2cb1a71-361c-4006-b7a2-e7559036bea3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016545581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1016545581
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2405585929
Short name T597
Test name
Test status
Simulation time 400041273 ps
CPU time 2.7 seconds
Started Mar 26 02:39:43 PM PDT 24
Finished Mar 26 02:39:46 PM PDT 24
Peak memory 208796 kb
Host smart-f551a3e0-13b2-4881-b780-93eebd18dc0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405585929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2405585929
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3115559915
Short name T582
Test name
Test status
Simulation time 480827502 ps
CPU time 2 seconds
Started Mar 26 02:39:44 PM PDT 24
Finished Mar 26 02:39:46 PM PDT 24
Peak memory 200632 kb
Host smart-87f36501-e75e-48d7-a7cf-3f2712ce4976
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115559915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3115559915
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2594880229
Short name T558
Test name
Test status
Simulation time 203233265 ps
CPU time 2.1 seconds
Started Mar 26 02:39:43 PM PDT 24
Finished Mar 26 02:39:45 PM PDT 24
Peak memory 208908 kb
Host smart-3f497cbd-a1a2-4cd7-913a-63645a1e47d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594880229 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2594880229
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.550996641
Short name T577
Test name
Test status
Simulation time 65402667 ps
CPU time 0.8 seconds
Started Mar 26 02:39:43 PM PDT 24
Finished Mar 26 02:39:44 PM PDT 24
Peak memory 200368 kb
Host smart-d7263237-ebe8-47e7-b5f8-32af11554812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550996641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.550996641
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2179370400
Short name T584
Test name
Test status
Simulation time 81022839 ps
CPU time 0.97 seconds
Started Mar 26 02:39:45 PM PDT 24
Finished Mar 26 02:39:47 PM PDT 24
Peak memory 200456 kb
Host smart-50b096b2-2b5e-4582-829c-a92968cc56fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179370400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2179370400
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4230075556
Short name T598
Test name
Test status
Simulation time 469113933 ps
CPU time 3.62 seconds
Started Mar 26 02:39:42 PM PDT 24
Finished Mar 26 02:39:45 PM PDT 24
Peak memory 208800 kb
Host smart-e61faaf0-166e-413b-b2b5-6fc0f0da7d56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230075556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4230075556
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.511170426
Short name T139
Test name
Test status
Simulation time 895323531 ps
CPU time 3.26 seconds
Started Mar 26 02:39:42 PM PDT 24
Finished Mar 26 02:39:45 PM PDT 24
Peak memory 200584 kb
Host smart-38fe3be4-ba80-4ad1-89cc-fb755bae377e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511170426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
511170426
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3153754081
Short name T354
Test name
Test status
Simulation time 244082114 ps
CPU time 1.12 seconds
Started Mar 26 03:21:53 PM PDT 24
Finished Mar 26 03:21:54 PM PDT 24
Peak memory 218176 kb
Host smart-471534b3-a726-4ffe-8e1c-16350c7e47b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153754081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3153754081
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1745737368
Short name T455
Test name
Test status
Simulation time 92487277 ps
CPU time 0.78 seconds
Started Mar 26 03:22:02 PM PDT 24
Finished Mar 26 03:22:03 PM PDT 24
Peak memory 200704 kb
Host smart-18779006-cf81-409f-96a4-e5103731e9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745737368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1745737368
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.282588300
Short name T87
Test name
Test status
Simulation time 2078137259 ps
CPU time 7.03 seconds
Started Mar 26 03:21:58 PM PDT 24
Finished Mar 26 03:22:06 PM PDT 24
Peak memory 200996 kb
Host smart-0bb01b00-d42c-4062-89d4-c50ce53f985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282588300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.282588300
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4039909911
Short name T286
Test name
Test status
Simulation time 97150873 ps
CPU time 1.09 seconds
Started Mar 26 03:22:03 PM PDT 24
Finished Mar 26 03:22:05 PM PDT 24
Peak memory 200776 kb
Host smart-a28a0cda-a18d-4043-8271-a077faa85137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039909911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4039909911
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1886699348
Short name T401
Test name
Test status
Simulation time 193238830 ps
CPU time 1.41 seconds
Started Mar 26 03:22:04 PM PDT 24
Finished Mar 26 03:22:06 PM PDT 24
Peak memory 201020 kb
Host smart-93c0e19d-28e2-4004-a877-75fa77e390f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886699348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1886699348
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3396886571
Short name T447
Test name
Test status
Simulation time 2421215188 ps
CPU time 11.21 seconds
Started Mar 26 03:21:49 PM PDT 24
Finished Mar 26 03:22:01 PM PDT 24
Peak memory 209784 kb
Host smart-9479c48c-4685-4fef-ad0b-4ebae6d2a7d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396886571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3396886571
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2012040938
Short name T372
Test name
Test status
Simulation time 470332528 ps
CPU time 2.49 seconds
Started Mar 26 03:21:55 PM PDT 24
Finished Mar 26 03:21:58 PM PDT 24
Peak memory 209048 kb
Host smart-cbdbbb61-f628-4b98-b6db-2e999e2b8009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012040938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2012040938
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3224656193
Short name T84
Test name
Test status
Simulation time 290987577 ps
CPU time 1.56 seconds
Started Mar 26 03:22:02 PM PDT 24
Finished Mar 26 03:22:04 PM PDT 24
Peak memory 201172 kb
Host smart-9913f82f-8c7d-4d04-b019-8217245ef5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224656193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3224656193
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1434369214
Short name T9
Test name
Test status
Simulation time 62025619 ps
CPU time 0.74 seconds
Started Mar 26 03:22:00 PM PDT 24
Finished Mar 26 03:22:01 PM PDT 24
Peak memory 200600 kb
Host smart-6940bcb4-440c-435a-88b3-7f658fa45ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434369214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1434369214
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3807352106
Short name T394
Test name
Test status
Simulation time 1894043029 ps
CPU time 7.51 seconds
Started Mar 26 03:22:02 PM PDT 24
Finished Mar 26 03:22:10 PM PDT 24
Peak memory 222612 kb
Host smart-c8b8d4a9-d8f3-4305-92de-192c6c86e3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807352106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3807352106
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3931251110
Short name T292
Test name
Test status
Simulation time 929538157 ps
CPU time 5.13 seconds
Started Mar 26 03:22:03 PM PDT 24
Finished Mar 26 03:22:09 PM PDT 24
Peak memory 200964 kb
Host smart-30d2c8e2-791c-41d4-90f7-a57908ae4932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931251110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3931251110
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2288074079
Short name T81
Test name
Test status
Simulation time 16512781735 ps
CPU time 28.05 seconds
Started Mar 26 03:22:01 PM PDT 24
Finished Mar 26 03:22:30 PM PDT 24
Peak memory 218740 kb
Host smart-1092ff19-6992-4bf4-ad4c-af96829cecf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288074079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2288074079
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.837520905
Short name T469
Test name
Test status
Simulation time 183206770 ps
CPU time 1.24 seconds
Started Mar 26 03:22:10 PM PDT 24
Finished Mar 26 03:22:11 PM PDT 24
Peak memory 200804 kb
Host smart-7236d53e-c84e-4996-9c2d-96d52c4b24a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837520905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.837520905
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1183899122
Short name T147
Test name
Test status
Simulation time 201575296 ps
CPU time 1.49 seconds
Started Mar 26 03:21:55 PM PDT 24
Finished Mar 26 03:21:57 PM PDT 24
Peak memory 200952 kb
Host smart-80dfe4c3-3b0a-4f4c-b76c-b64f3a35c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183899122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1183899122
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.546178
Short name T396
Test name
Test status
Simulation time 2127667381 ps
CPU time 10.01 seconds
Started Mar 26 03:21:59 PM PDT 24
Finished Mar 26 03:22:09 PM PDT 24
Peak memory 209208 kb
Host smart-413cd141-59b9-4c12-b339-3cd54379d546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.546178
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2792838895
Short name T446
Test name
Test status
Simulation time 512826021 ps
CPU time 3.11 seconds
Started Mar 26 03:22:03 PM PDT 24
Finished Mar 26 03:22:06 PM PDT 24
Peak memory 200888 kb
Host smart-e4b5931d-573d-41b3-a05b-9f839a0a8aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792838895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2792838895
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2220351487
Short name T268
Test name
Test status
Simulation time 112322713 ps
CPU time 0.99 seconds
Started Mar 26 03:22:05 PM PDT 24
Finished Mar 26 03:22:06 PM PDT 24
Peak memory 200804 kb
Host smart-8e08804c-6839-42cd-ac8e-718ca1893bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220351487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2220351487
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1824098949
Short name T433
Test name
Test status
Simulation time 59940019 ps
CPU time 0.72 seconds
Started Mar 26 03:22:16 PM PDT 24
Finished Mar 26 03:22:18 PM PDT 24
Peak memory 200708 kb
Host smart-e1089a6b-9dc5-4743-a951-632962601577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824098949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1824098949
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1597026406
Short name T524
Test name
Test status
Simulation time 1885910995 ps
CPU time 7.25 seconds
Started Mar 26 03:22:16 PM PDT 24
Finished Mar 26 03:22:24 PM PDT 24
Peak memory 217692 kb
Host smart-b7849054-d79b-4658-8e7a-81ef8bd87262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597026406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1597026406
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2990003033
Short name T160
Test name
Test status
Simulation time 245911913 ps
CPU time 1.06 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 218152 kb
Host smart-ebe8b692-09d9-4b37-b832-273126f11085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990003033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2990003033
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4265016333
Short name T448
Test name
Test status
Simulation time 105772982 ps
CPU time 0.8 seconds
Started Mar 26 03:22:17 PM PDT 24
Finished Mar 26 03:22:18 PM PDT 24
Peak memory 200744 kb
Host smart-aba29801-63d7-403f-ab47-da5d086a57c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265016333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4265016333
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3399226105
Short name T235
Test name
Test status
Simulation time 1960009772 ps
CPU time 7.34 seconds
Started Mar 26 03:22:17 PM PDT 24
Finished Mar 26 03:22:24 PM PDT 24
Peak memory 201028 kb
Host smart-86c56909-0263-43bb-b41f-d45211a4ab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399226105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3399226105
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2291744639
Short name T319
Test name
Test status
Simulation time 193875070 ps
CPU time 1.48 seconds
Started Mar 26 03:22:16 PM PDT 24
Finished Mar 26 03:22:17 PM PDT 24
Peak memory 200992 kb
Host smart-0b1a4d0b-a17b-47a3-9749-8ee5d92a451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291744639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2291744639
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1797869436
Short name T263
Test name
Test status
Simulation time 3150805347 ps
CPU time 13.83 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:32 PM PDT 24
Peak memory 209384 kb
Host smart-3fd331ec-27af-4eaa-ae46-9afde9e7597d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797869436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1797869436
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3839949675
Short name T312
Test name
Test status
Simulation time 137863452 ps
CPU time 1.77 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 209112 kb
Host smart-bab3dd74-0017-4c3a-92a0-7bd74b27e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839949675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3839949675
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3021981050
Short name T171
Test name
Test status
Simulation time 169321119 ps
CPU time 1.21 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 200824 kb
Host smart-842f284e-a5da-41f2-8f86-a9e2f93fa7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021981050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3021981050
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.654418982
Short name T296
Test name
Test status
Simulation time 68150246 ps
CPU time 0.75 seconds
Started Mar 26 03:22:19 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 200688 kb
Host smart-f97f92e5-bc85-4a1a-9c69-1e929e1700cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654418982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.654418982
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1424217272
Short name T329
Test name
Test status
Simulation time 1220966256 ps
CPU time 6.05 seconds
Started Mar 26 03:22:24 PM PDT 24
Finished Mar 26 03:22:31 PM PDT 24
Peak memory 222536 kb
Host smart-a6a265a6-e2ac-4340-8dad-a5c31a7c7f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424217272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1424217272
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2619555808
Short name T542
Test name
Test status
Simulation time 243613055 ps
CPU time 1.05 seconds
Started Mar 26 03:22:16 PM PDT 24
Finished Mar 26 03:22:17 PM PDT 24
Peak memory 218100 kb
Host smart-1d345a3f-8c2d-41dc-919d-8a0a129056c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619555808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2619555808
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2975190102
Short name T422
Test name
Test status
Simulation time 220322889 ps
CPU time 0.92 seconds
Started Mar 26 03:22:16 PM PDT 24
Finished Mar 26 03:22:17 PM PDT 24
Peak memory 200676 kb
Host smart-81b987c1-e11f-4d2f-ae2f-d31d41c53b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975190102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2975190102
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2372146786
Short name T518
Test name
Test status
Simulation time 825865261 ps
CPU time 4.17 seconds
Started Mar 26 03:22:14 PM PDT 24
Finished Mar 26 03:22:19 PM PDT 24
Peak memory 200860 kb
Host smart-b52e8ec9-c0ee-49dd-b16e-13e0e70c7668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372146786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2372146786
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.357804493
Short name T473
Test name
Test status
Simulation time 96453257 ps
CPU time 0.98 seconds
Started Mar 26 03:22:21 PM PDT 24
Finished Mar 26 03:22:22 PM PDT 24
Peak memory 200832 kb
Host smart-295b70fd-9d47-417d-84ea-31c21fdbc31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357804493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.357804493
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2002154538
Short name T173
Test name
Test status
Simulation time 248111693 ps
CPU time 1.45 seconds
Started Mar 26 03:22:20 PM PDT 24
Finished Mar 26 03:22:22 PM PDT 24
Peak memory 201020 kb
Host smart-e2f2618f-5d02-4474-a516-ad8aaeaad769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002154538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2002154538
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2175394352
Short name T387
Test name
Test status
Simulation time 1796632020 ps
CPU time 8.26 seconds
Started Mar 26 03:22:19 PM PDT 24
Finished Mar 26 03:22:27 PM PDT 24
Peak memory 200960 kb
Host smart-5b177728-a74b-4ef3-aad9-4ed42cbee7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175394352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2175394352
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.113249119
Short name T521
Test name
Test status
Simulation time 123580399 ps
CPU time 1.67 seconds
Started Mar 26 03:22:17 PM PDT 24
Finished Mar 26 03:22:19 PM PDT 24
Peak memory 209120 kb
Host smart-d109f939-4cf5-48bb-b402-976a257b9760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113249119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.113249119
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.464920647
Short name T144
Test name
Test status
Simulation time 224536645 ps
CPU time 1.31 seconds
Started Mar 26 03:22:24 PM PDT 24
Finished Mar 26 03:22:26 PM PDT 24
Peak memory 200724 kb
Host smart-8990a8d6-78e7-4c57-a852-d1d0712effab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464920647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.464920647
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3880359532
Short name T458
Test name
Test status
Simulation time 76951106 ps
CPU time 0.78 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:29 PM PDT 24
Peak memory 200732 kb
Host smart-2ea4b979-cefe-4aff-8c13-e146cbda4bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880359532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3880359532
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3621564723
Short name T30
Test name
Test status
Simulation time 1907260887 ps
CPU time 8.06 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:36 PM PDT 24
Peak memory 218140 kb
Host smart-f502aefb-1d89-473f-9094-23e986c8ccef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621564723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3621564723
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1520547433
Short name T508
Test name
Test status
Simulation time 244656427 ps
CPU time 1.16 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:31 PM PDT 24
Peak memory 218096 kb
Host smart-b59f12e1-04f3-40f5-887d-c80496063a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520547433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1520547433
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.96966904
Short name T218
Test name
Test status
Simulation time 115200108 ps
CPU time 0.83 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:30 PM PDT 24
Peak memory 200696 kb
Host smart-c65ffd4a-e3fc-4922-9e03-fbfeff182165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96966904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.96966904
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3234762296
Short name T416
Test name
Test status
Simulation time 741671435 ps
CPU time 3.78 seconds
Started Mar 26 03:22:31 PM PDT 24
Finished Mar 26 03:22:35 PM PDT 24
Peak memory 201028 kb
Host smart-5f180d44-ddd3-481f-8da2-dfec097ca9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234762296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3234762296
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.48075904
Short name T271
Test name
Test status
Simulation time 109865491 ps
CPU time 1.07 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:31 PM PDT 24
Peak memory 200824 kb
Host smart-a5ee93b8-e355-49a6-938c-e63d50068b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48075904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.48075904
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3580001486
Short name T156
Test name
Test status
Simulation time 109986259 ps
CPU time 1.13 seconds
Started Mar 26 03:22:19 PM PDT 24
Finished Mar 26 03:22:21 PM PDT 24
Peak memory 201008 kb
Host smart-3a016490-520f-4feb-bf75-825b78dcd444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580001486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3580001486
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3148304131
Short name T291
Test name
Test status
Simulation time 1024364208 ps
CPU time 5.33 seconds
Started Mar 26 03:22:31 PM PDT 24
Finished Mar 26 03:22:37 PM PDT 24
Peak memory 200988 kb
Host smart-95afe074-d4d3-43bf-9b3e-bbd0cb61c1cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148304131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3148304131
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.4022699493
Short name T472
Test name
Test status
Simulation time 341914578 ps
CPU time 2.34 seconds
Started Mar 26 03:22:26 PM PDT 24
Finished Mar 26 03:22:28 PM PDT 24
Peak memory 209060 kb
Host smart-2dccd470-6828-44ac-8310-ad711cef14ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022699493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.4022699493
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2419444824
Short name T258
Test name
Test status
Simulation time 92080139 ps
CPU time 0.91 seconds
Started Mar 26 03:22:27 PM PDT 24
Finished Mar 26 03:22:28 PM PDT 24
Peak memory 200828 kb
Host smart-603b8f30-c890-41a1-ac37-16538f54a9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419444824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2419444824
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3481758602
Short name T400
Test name
Test status
Simulation time 73022821 ps
CPU time 0.75 seconds
Started Mar 26 03:22:26 PM PDT 24
Finished Mar 26 03:22:27 PM PDT 24
Peak memory 200728 kb
Host smart-40676626-f26f-49f2-9cce-bbb2a7bc9082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481758602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3481758602
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.419707668
Short name T38
Test name
Test status
Simulation time 1880293306 ps
CPU time 8.22 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:38 PM PDT 24
Peak memory 217636 kb
Host smart-4a78fd7e-62ed-46d7-a2d8-555195e4fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419707668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.419707668
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.4157450241
Short name T256
Test name
Test status
Simulation time 243989790 ps
CPU time 1.13 seconds
Started Mar 26 03:22:27 PM PDT 24
Finished Mar 26 03:22:28 PM PDT 24
Peak memory 218100 kb
Host smart-4c8c14bf-26ef-42d4-8168-ac9c739f637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157450241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.4157450241
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2755148561
Short name T505
Test name
Test status
Simulation time 108774158 ps
CPU time 0.81 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:29 PM PDT 24
Peak memory 200700 kb
Host smart-09d29ea8-8934-4b95-b50f-bc693632b023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755148561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2755148561
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2107127929
Short name T206
Test name
Test status
Simulation time 790709093 ps
CPU time 3.83 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:32 PM PDT 24
Peak memory 200984 kb
Host smart-ce30e69d-3661-4573-8d93-f2a6d7945ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107127929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2107127929
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3722408629
Short name T274
Test name
Test status
Simulation time 100874761 ps
CPU time 1 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:31 PM PDT 24
Peak memory 200844 kb
Host smart-9073eb3b-1f94-4ccf-b3a5-dfc851415b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722408629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3722408629
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.951176772
Short name T507
Test name
Test status
Simulation time 249748386 ps
CPU time 1.62 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:31 PM PDT 24
Peak memory 201004 kb
Host smart-d3735761-2b67-40e5-bf99-3b6666e7a98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951176772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.951176772
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3280257249
Short name T138
Test name
Test status
Simulation time 3120972179 ps
CPU time 15.38 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 201128 kb
Host smart-30729df1-909b-41b2-9ff2-1095d8d6d78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280257249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3280257249
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2906841270
Short name T201
Test name
Test status
Simulation time 136656488 ps
CPU time 1.65 seconds
Started Mar 26 03:22:26 PM PDT 24
Finished Mar 26 03:22:28 PM PDT 24
Peak memory 209116 kb
Host smart-de30951b-d377-40bc-b074-ca04275505c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906841270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2906841270
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3338304623
Short name T159
Test name
Test status
Simulation time 99291240 ps
CPU time 1 seconds
Started Mar 26 03:22:26 PM PDT 24
Finished Mar 26 03:22:27 PM PDT 24
Peak memory 200796 kb
Host smart-7525ce22-f9d3-4c11-b96b-accc9dbb317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338304623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3338304623
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.925236351
Short name T215
Test name
Test status
Simulation time 65741365 ps
CPU time 0.77 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:30 PM PDT 24
Peak memory 200676 kb
Host smart-e493fbec-78b7-4ac4-b6cb-64a1beda86b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925236351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.925236351
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2225876426
Short name T40
Test name
Test status
Simulation time 1882962906 ps
CPU time 7.26 seconds
Started Mar 26 03:22:27 PM PDT 24
Finished Mar 26 03:22:34 PM PDT 24
Peak memory 222808 kb
Host smart-1d1207bc-4f02-4829-99c5-dc0e89d02083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225876426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2225876426
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3490759316
Short name T519
Test name
Test status
Simulation time 244945704 ps
CPU time 1.07 seconds
Started Mar 26 03:22:26 PM PDT 24
Finished Mar 26 03:22:27 PM PDT 24
Peak memory 218224 kb
Host smart-36a6542b-9db4-4e4d-a6b1-d0b92357ac5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490759316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3490759316
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4182753495
Short name T409
Test name
Test status
Simulation time 161327433 ps
CPU time 0.88 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:28 PM PDT 24
Peak memory 200744 kb
Host smart-0ad23bc6-4cba-44f3-863b-10b4ce047e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182753495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4182753495
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2345586444
Short name T487
Test name
Test status
Simulation time 978335852 ps
CPU time 5.55 seconds
Started Mar 26 03:22:27 PM PDT 24
Finished Mar 26 03:22:33 PM PDT 24
Peak memory 201076 kb
Host smart-1c3f5b30-dae5-4c65-99ec-5f13eb2b3926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345586444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2345586444
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3432156357
Short name T456
Test name
Test status
Simulation time 152276971 ps
CPU time 1.12 seconds
Started Mar 26 03:22:32 PM PDT 24
Finished Mar 26 03:22:33 PM PDT 24
Peak memory 200832 kb
Host smart-82d082fc-10cf-45ab-97a2-80e005d03d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432156357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3432156357
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2141895899
Short name T434
Test name
Test status
Simulation time 242734213 ps
CPU time 1.55 seconds
Started Mar 26 03:22:26 PM PDT 24
Finished Mar 26 03:22:28 PM PDT 24
Peak memory 201020 kb
Host smart-8c271658-623f-4343-8dea-c3bbee5f8136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141895899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2141895899
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1322567159
Short name T440
Test name
Test status
Simulation time 1482841310 ps
CPU time 5.86 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:34 PM PDT 24
Peak memory 201004 kb
Host smart-ea1133a2-db0b-4517-a467-dba389a4678e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322567159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1322567159
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1028760895
Short name T299
Test name
Test status
Simulation time 240535348 ps
CPU time 1.4 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:30 PM PDT 24
Peak memory 200804 kb
Host smart-3e9ab6a3-3954-438a-822b-dc9622dae177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028760895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1028760895
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3957124890
Short name T495
Test name
Test status
Simulation time 73861950 ps
CPU time 0.75 seconds
Started Mar 26 03:22:26 PM PDT 24
Finished Mar 26 03:22:27 PM PDT 24
Peak memory 200668 kb
Host smart-8ce7d668-213c-4cd4-8948-be2b25f1bad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957124890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3957124890
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.570579642
Short name T499
Test name
Test status
Simulation time 1225954702 ps
CPU time 5.96 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:35 PM PDT 24
Peak memory 217948 kb
Host smart-09259ec2-2390-4172-9e54-c6dcf58fa0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570579642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.570579642
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.4027542467
Short name T170
Test name
Test status
Simulation time 244865208 ps
CPU time 1.09 seconds
Started Mar 26 03:22:28 PM PDT 24
Finished Mar 26 03:22:29 PM PDT 24
Peak memory 218120 kb
Host smart-0a0c57cc-17b6-4076-a8df-8b9cbf90c9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027542467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.4027542467
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3866308206
Short name T8
Test name
Test status
Simulation time 205284106 ps
CPU time 1.04 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:31 PM PDT 24
Peak memory 200704 kb
Host smart-f4b2ec8c-9234-42ff-b7b7-96134cc31a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866308206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3866308206
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.332668327
Short name T113
Test name
Test status
Simulation time 1523206393 ps
CPU time 5.54 seconds
Started Mar 26 03:22:26 PM PDT 24
Finished Mar 26 03:22:31 PM PDT 24
Peak memory 201004 kb
Host smart-6dc93f54-5bbc-4850-8139-fef42d9b9303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332668327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.332668327
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2601717116
Short name T497
Test name
Test status
Simulation time 110860433 ps
CPU time 1.04 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:31 PM PDT 24
Peak memory 200848 kb
Host smart-923da102-d4b8-4b2a-a18e-7131c9c8eabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601717116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2601717116
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.280756543
Short name T531
Test name
Test status
Simulation time 250821750 ps
CPU time 1.49 seconds
Started Mar 26 03:22:27 PM PDT 24
Finished Mar 26 03:22:28 PM PDT 24
Peak memory 201004 kb
Host smart-c08b4a69-0cfc-4df9-9705-5898ce0ee868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280756543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.280756543
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3241363212
Short name T406
Test name
Test status
Simulation time 3305799529 ps
CPU time 12 seconds
Started Mar 26 03:22:31 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 209272 kb
Host smart-eabd8f82-23dc-4cbb-b274-fc59f2c0228e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241363212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3241363212
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3712355993
Short name T240
Test name
Test status
Simulation time 115858345 ps
CPU time 1.5 seconds
Started Mar 26 03:22:29 PM PDT 24
Finished Mar 26 03:22:31 PM PDT 24
Peak memory 200856 kb
Host smart-eb57b978-d27e-45ad-8a8d-300fb4ace4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712355993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3712355993
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2780910804
Short name T194
Test name
Test status
Simulation time 85950109 ps
CPU time 0.87 seconds
Started Mar 26 03:22:27 PM PDT 24
Finished Mar 26 03:22:28 PM PDT 24
Peak memory 200824 kb
Host smart-5b4be949-dce8-42b8-b25c-f607f07ff971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780910804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2780910804
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2629483805
Short name T389
Test name
Test status
Simulation time 68980703 ps
CPU time 0.84 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:41 PM PDT 24
Peak memory 200716 kb
Host smart-77495063-a2a8-433a-b5bb-70a9afadc15a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629483805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2629483805
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1578108458
Short name T207
Test name
Test status
Simulation time 244660335 ps
CPU time 1.15 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 218232 kb
Host smart-67c41fc0-3de1-494a-99e5-60e994deff7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578108458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1578108458
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1078721509
Short name T25
Test name
Test status
Simulation time 202832813 ps
CPU time 0.96 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:40 PM PDT 24
Peak memory 200664 kb
Host smart-4b397292-e3cd-4985-aeb9-289a4c26e842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078721509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1078721509
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4271020329
Short name T211
Test name
Test status
Simulation time 865454110 ps
CPU time 4.21 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:45 PM PDT 24
Peak memory 200996 kb
Host smart-97bd55f3-31ae-42fe-a8e0-1d5f221f5e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271020329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4271020329
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1003265313
Short name T484
Test name
Test status
Simulation time 148780935 ps
CPU time 1.15 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200872 kb
Host smart-b49491bd-b68d-4797-b32a-32fca37bc420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003265313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1003265313
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.856770777
Short name T289
Test name
Test status
Simulation time 124832989 ps
CPU time 1.3 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200992 kb
Host smart-ba6881f9-3f87-40ea-86b1-ebfdef29a00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856770777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.856770777
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3484087903
Short name T221
Test name
Test status
Simulation time 8690892205 ps
CPU time 30.5 seconds
Started Mar 26 03:22:35 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 201128 kb
Host smart-ced83ec9-63a4-4775-8685-7d194ac65482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484087903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3484087903
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1971224461
Short name T395
Test name
Test status
Simulation time 537070788 ps
CPU time 2.81 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 200892 kb
Host smart-14a0b6cc-2612-41f7-8618-73ad90b275b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971224461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1971224461
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2569311805
Short name T180
Test name
Test status
Simulation time 141361520 ps
CPU time 1 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200804 kb
Host smart-d1d8288a-6642-4585-8d8c-4ce5c14bb1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569311805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2569311805
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3916528404
Short name T509
Test name
Test status
Simulation time 77906085 ps
CPU time 0.81 seconds
Started Mar 26 03:22:38 PM PDT 24
Finished Mar 26 03:22:39 PM PDT 24
Peak memory 200676 kb
Host smart-d47edb7c-84ae-46cc-8a09-62b73a7de929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916528404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3916528404
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.4110295214
Short name T44
Test name
Test status
Simulation time 1900787257 ps
CPU time 7.06 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:48 PM PDT 24
Peak memory 217964 kb
Host smart-f09db4aa-8690-4b6c-bfcb-b664f333be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110295214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.4110295214
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2329485836
Short name T172
Test name
Test status
Simulation time 244819374 ps
CPU time 1.07 seconds
Started Mar 26 03:22:38 PM PDT 24
Finished Mar 26 03:22:40 PM PDT 24
Peak memory 218116 kb
Host smart-a5f4ff0d-2a43-46b0-aead-18bb57f05ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329485836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2329485836
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.404558654
Short name T467
Test name
Test status
Simulation time 128414269 ps
CPU time 0.85 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:40 PM PDT 24
Peak memory 200700 kb
Host smart-73302ba2-2d35-4f5d-8bb0-603a61931464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404558654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.404558654
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1305876045
Short name T322
Test name
Test status
Simulation time 1328989795 ps
CPU time 4.89 seconds
Started Mar 26 03:22:38 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 200980 kb
Host smart-bfec5ca8-cbbb-4f95-9c73-6d6cf840b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305876045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1305876045
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1555216449
Short name T335
Test name
Test status
Simulation time 142790389 ps
CPU time 1.15 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200836 kb
Host smart-83031719-d610-4513-9ef3-4dbcc5664aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555216449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1555216449
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2984550465
Short name T288
Test name
Test status
Simulation time 126981509 ps
CPU time 1.27 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200964 kb
Host smart-5342a175-237b-4f90-8418-20f6af8311be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984550465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2984550465
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.24467488
Short name T343
Test name
Test status
Simulation time 4431034312 ps
CPU time 18.89 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:59 PM PDT 24
Peak memory 209312 kb
Host smart-b8e9b342-4a84-4b7c-9e1b-87ed2f29a871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24467488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.24467488
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1893746984
Short name T64
Test name
Test status
Simulation time 453111541 ps
CPU time 2.57 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 200884 kb
Host smart-d4dd9522-e2c1-48e2-a936-c413357e12c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893746984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1893746984
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3232336066
Short name T475
Test name
Test status
Simulation time 163415872 ps
CPU time 1.1 seconds
Started Mar 26 03:22:38 PM PDT 24
Finished Mar 26 03:22:39 PM PDT 24
Peak memory 200828 kb
Host smart-6acf9961-013e-40be-a9f2-3a55aed6f05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232336066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3232336066
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1035136683
Short name T330
Test name
Test status
Simulation time 81314326 ps
CPU time 0.87 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200684 kb
Host smart-5c5f7c60-9db7-46d9-9169-2904e1ef47ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035136683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1035136683
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.465570422
Short name T413
Test name
Test status
Simulation time 1894673196 ps
CPU time 7.06 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:48 PM PDT 24
Peak memory 218504 kb
Host smart-7b2e2f28-9570-45d1-ba1d-efd49fff4efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465570422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.465570422
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2449070795
Short name T533
Test name
Test status
Simulation time 244356337 ps
CPU time 1.14 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 218144 kb
Host smart-9f3b604f-ea47-4e40-930d-df3509ee2d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449070795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2449070795
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.111113814
Short name T212
Test name
Test status
Simulation time 106106172 ps
CPU time 0.82 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:40 PM PDT 24
Peak memory 200700 kb
Host smart-2942950b-64d4-4e68-9281-daa8fb3c52bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111113814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.111113814
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1449300151
Short name T209
Test name
Test status
Simulation time 2163838693 ps
CPU time 9.41 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:49 PM PDT 24
Peak memory 201128 kb
Host smart-e45718ac-81e9-4e84-bfff-400a7960b75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449300151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1449300151
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.203626466
Short name T449
Test name
Test status
Simulation time 143536174 ps
CPU time 1.18 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200732 kb
Host smart-83aab81c-ecf2-4548-9267-1d1d2fd409af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203626466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.203626466
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.450477737
Short name T460
Test name
Test status
Simulation time 119747040 ps
CPU time 1.16 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:41 PM PDT 24
Peak memory 201008 kb
Host smart-0c804d4a-c326-4daf-b666-2c29893faf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450477737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.450477737
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.319718983
Short name T522
Test name
Test status
Simulation time 7872011895 ps
CPU time 28.15 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 201140 kb
Host smart-e322e763-ed01-44b8-a458-305310c43a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319718983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.319718983
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.554954239
Short name T501
Test name
Test status
Simulation time 308455014 ps
CPU time 2.12 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 209064 kb
Host smart-b520c53d-5827-413e-9674-d4d73a4ed161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554954239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.554954239
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2163578930
Short name T146
Test name
Test status
Simulation time 66024045 ps
CPU time 0.8 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200832 kb
Host smart-21c8d0df-ebed-48aa-adfd-4bd24e6c7b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163578930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2163578930
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.57749989
Short name T315
Test name
Test status
Simulation time 100992640 ps
CPU time 0.89 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200696 kb
Host smart-e5e374cd-efee-47a4-9e2e-eb378cb929c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57749989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.57749989
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.252027687
Short name T514
Test name
Test status
Simulation time 1227662112 ps
CPU time 5.72 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:45 PM PDT 24
Peak memory 222476 kb
Host smart-110b759f-e164-4e19-b921-e40fb7673474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252027687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.252027687
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3802706377
Short name T7
Test name
Test status
Simulation time 244284696 ps
CPU time 1.08 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 218108 kb
Host smart-8359310c-5367-4397-9f67-f56ef5ec681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802706377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3802706377
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.382851259
Short name T294
Test name
Test status
Simulation time 166412291 ps
CPU time 0.84 seconds
Started Mar 26 03:22:36 PM PDT 24
Finished Mar 26 03:22:37 PM PDT 24
Peak memory 200668 kb
Host smart-0f15a03b-bbe8-4a66-a2e9-e0a106fc2c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382851259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.382851259
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.73434603
Short name T69
Test name
Test status
Simulation time 863662010 ps
CPU time 4.29 seconds
Started Mar 26 03:22:38 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 201004 kb
Host smart-39ddf4eb-2e4f-4443-8671-000b1f179973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73434603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.73434603
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1143955835
Short name T217
Test name
Test status
Simulation time 167915285 ps
CPU time 1.19 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200860 kb
Host smart-2b2b5ae2-6b00-45de-8dee-d71320e054b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143955835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1143955835
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1045032446
Short name T465
Test name
Test status
Simulation time 113735086 ps
CPU time 1.19 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 201024 kb
Host smart-39e6e1bc-9561-469f-babf-46aeab836e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045032446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1045032446
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1818826607
Short name T57
Test name
Test status
Simulation time 1852037650 ps
CPU time 7.91 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:48 PM PDT 24
Peak memory 201004 kb
Host smart-98c1962a-60d7-4fbc-a232-9b1247b35bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818826607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1818826607
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1763241342
Short name T244
Test name
Test status
Simulation time 401039111 ps
CPU time 2.29 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200840 kb
Host smart-5043cabe-1e77-4e68-aba3-db87a3581ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763241342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1763241342
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1580831989
Short name T237
Test name
Test status
Simulation time 150448039 ps
CPU time 1.26 seconds
Started Mar 26 03:22:37 PM PDT 24
Finished Mar 26 03:22:40 PM PDT 24
Peak memory 200856 kb
Host smart-b30385be-705d-4a3a-8afd-2c8db83891e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580831989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1580831989
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1196970848
Short name T264
Test name
Test status
Simulation time 101072461 ps
CPU time 0.84 seconds
Started Mar 26 03:22:03 PM PDT 24
Finished Mar 26 03:22:04 PM PDT 24
Peak memory 200680 kb
Host smart-5d499ff4-7636-41fd-97c8-1ed644f98cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196970848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1196970848
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2734805981
Short name T58
Test name
Test status
Simulation time 2343414938 ps
CPU time 7.77 seconds
Started Mar 26 03:22:01 PM PDT 24
Finished Mar 26 03:22:10 PM PDT 24
Peak memory 218632 kb
Host smart-ca04a4e7-23cf-4971-82ca-009ae464e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734805981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2734805981
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.4293517055
Short name T478
Test name
Test status
Simulation time 244831858 ps
CPU time 1.09 seconds
Started Mar 26 03:22:06 PM PDT 24
Finished Mar 26 03:22:07 PM PDT 24
Peak memory 218096 kb
Host smart-cbf877c5-b6bc-499a-82de-39a9841e9de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293517055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.4293517055
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2788014761
Short name T231
Test name
Test status
Simulation time 164165195 ps
CPU time 0.86 seconds
Started Mar 26 03:22:02 PM PDT 24
Finished Mar 26 03:22:04 PM PDT 24
Peak memory 200672 kb
Host smart-c7053023-680d-44bf-8894-68aa18f5f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788014761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2788014761
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3689778493
Short name T137
Test name
Test status
Simulation time 1210417182 ps
CPU time 5.37 seconds
Started Mar 26 03:22:02 PM PDT 24
Finished Mar 26 03:22:08 PM PDT 24
Peak memory 201004 kb
Host smart-4a96a7e5-30ea-49be-b627-52fd910217f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689778493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3689778493
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1332497145
Short name T78
Test name
Test status
Simulation time 16749617564 ps
CPU time 24.89 seconds
Started Mar 26 03:22:05 PM PDT 24
Finished Mar 26 03:22:30 PM PDT 24
Peak memory 217760 kb
Host smart-e9804828-d22e-4fd0-856b-8922d13df896
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332497145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1332497145
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3670955676
Short name T88
Test name
Test status
Simulation time 153035678 ps
CPU time 1.2 seconds
Started Mar 26 03:22:05 PM PDT 24
Finished Mar 26 03:22:07 PM PDT 24
Peak memory 200820 kb
Host smart-809980ef-61fc-441f-81d4-dec7b9f380f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670955676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3670955676
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2337682684
Short name T157
Test name
Test status
Simulation time 264983699 ps
CPU time 1.55 seconds
Started Mar 26 03:22:04 PM PDT 24
Finished Mar 26 03:22:07 PM PDT 24
Peak memory 200968 kb
Host smart-714b4955-ae8f-4b80-bb2e-ad077b583668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337682684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2337682684
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1752028662
Short name T502
Test name
Test status
Simulation time 4845862131 ps
CPU time 17.63 seconds
Started Mar 26 03:21:59 PM PDT 24
Finished Mar 26 03:22:18 PM PDT 24
Peak memory 201108 kb
Host smart-0350ec41-3f18-4657-91f2-1d0e3861591c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752028662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1752028662
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.4003180021
Short name T198
Test name
Test status
Simulation time 137366942 ps
CPU time 1.6 seconds
Started Mar 26 03:22:03 PM PDT 24
Finished Mar 26 03:22:05 PM PDT 24
Peak memory 209100 kb
Host smart-79e6978f-9f6b-4739-af7c-209c0510bc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003180021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.4003180021
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1914762928
Short name T52
Test name
Test status
Simulation time 162700494 ps
CPU time 1.28 seconds
Started Mar 26 03:22:02 PM PDT 24
Finished Mar 26 03:22:04 PM PDT 24
Peak memory 200788 kb
Host smart-d35257a5-962a-4665-8f88-f2db8f161040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914762928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1914762928
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.258302923
Short name T525
Test name
Test status
Simulation time 62659234 ps
CPU time 0.71 seconds
Started Mar 26 03:22:35 PM PDT 24
Finished Mar 26 03:22:36 PM PDT 24
Peak memory 200700 kb
Host smart-dcbfebee-7a48-48dd-ad7c-5a70d0e9f70b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258302923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.258302923
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2732350678
Short name T34
Test name
Test status
Simulation time 2342627409 ps
CPU time 8.42 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:49 PM PDT 24
Peak memory 222656 kb
Host smart-3e8e0b7f-1f60-4ede-81e7-900b525e5bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732350678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2732350678
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1786095813
Short name T515
Test name
Test status
Simulation time 244452310 ps
CPU time 1.05 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 218096 kb
Host smart-6c2fa553-1f55-4a67-a32f-c0d8dfea3589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786095813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1786095813
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1325167242
Short name T21
Test name
Test status
Simulation time 212904534 ps
CPU time 0.92 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:41 PM PDT 24
Peak memory 200676 kb
Host smart-489b8bb4-e4b7-463b-a6b4-7c2b4aad68b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325167242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1325167242
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.322612973
Short name T345
Test name
Test status
Simulation time 1829290000 ps
CPU time 6.91 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:46 PM PDT 24
Peak memory 201024 kb
Host smart-368b0056-b0e4-47c6-80a7-4af91707bd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322612973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.322612973
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3656328633
Short name T504
Test name
Test status
Simulation time 184077962 ps
CPU time 1.25 seconds
Started Mar 26 03:22:42 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 200804 kb
Host smart-1f92253e-9c1f-4273-9049-f7059d511a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656328633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3656328633
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3887835667
Short name T418
Test name
Test status
Simulation time 250451523 ps
CPU time 1.65 seconds
Started Mar 26 03:22:44 PM PDT 24
Finished Mar 26 03:22:46 PM PDT 24
Peak memory 201008 kb
Host smart-8276ab03-fe36-4a15-81a3-a2414a5307c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887835667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3887835667
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3438091125
Short name T255
Test name
Test status
Simulation time 2880141577 ps
CPU time 14.74 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 201144 kb
Host smart-88ad7cee-5ee4-4129-bd0c-edf74257145f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438091125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3438091125
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.529202220
Short name T317
Test name
Test status
Simulation time 137611397 ps
CPU time 1.93 seconds
Started Mar 26 03:22:42 PM PDT 24
Finished Mar 26 03:22:44 PM PDT 24
Peak memory 209048 kb
Host smart-330130a2-ca3d-4e7e-8f77-cbe9706dc094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529202220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.529202220
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3010264114
Short name T257
Test name
Test status
Simulation time 140982342 ps
CPU time 1.28 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200988 kb
Host smart-d8bd7ca4-284b-4737-bb0f-9e3ed58b46a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010264114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3010264114
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.612196383
Short name T538
Test name
Test status
Simulation time 64397480 ps
CPU time 0.77 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 200680 kb
Host smart-0408beec-4e3a-4959-91a2-b7e2ed068764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612196383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.612196383
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1519582156
Short name T45
Test name
Test status
Simulation time 1883833972 ps
CPU time 7.66 seconds
Started Mar 26 03:22:43 PM PDT 24
Finished Mar 26 03:22:50 PM PDT 24
Peak memory 217584 kb
Host smart-172c5268-3eb6-4f56-8d5c-1daa5a2aa773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519582156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1519582156
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3147241287
Short name T148
Test name
Test status
Simulation time 243775859 ps
CPU time 1.14 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 218252 kb
Host smart-3986ec97-30b7-4334-8c43-83a3670ea9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147241287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3147241287
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3208339978
Short name T200
Test name
Test status
Simulation time 169202950 ps
CPU time 0.82 seconds
Started Mar 26 03:22:37 PM PDT 24
Finished Mar 26 03:22:38 PM PDT 24
Peak memory 200664 kb
Host smart-398eb65f-564b-4925-9aeb-150ed84ae0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208339978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3208339978
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2086400093
Short name T310
Test name
Test status
Simulation time 1606830025 ps
CPU time 7.06 seconds
Started Mar 26 03:22:40 PM PDT 24
Finished Mar 26 03:22:47 PM PDT 24
Peak memory 201056 kb
Host smart-dbe4264d-c582-4b02-8aeb-e5ca1238da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086400093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2086400093
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2451246948
Short name T436
Test name
Test status
Simulation time 160744558 ps
CPU time 1.16 seconds
Started Mar 26 03:22:48 PM PDT 24
Finished Mar 26 03:22:50 PM PDT 24
Peak memory 200764 kb
Host smart-9107f711-a760-4d63-a2b5-b1f1f670d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451246948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2451246948
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.198425289
Short name T353
Test name
Test status
Simulation time 119498211 ps
CPU time 1.21 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:42 PM PDT 24
Peak memory 201004 kb
Host smart-8e01b50f-e067-41dd-a517-851146a47eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198425289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.198425289
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3003155965
Short name T537
Test name
Test status
Simulation time 1614075942 ps
CPU time 7.78 seconds
Started Mar 26 03:22:42 PM PDT 24
Finished Mar 26 03:22:50 PM PDT 24
Peak memory 201036 kb
Host smart-80513a91-7a7f-4c1d-8c62-92f5032b2ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003155965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3003155965
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2337594453
Short name T438
Test name
Test status
Simulation time 158107542 ps
CPU time 1.97 seconds
Started Mar 26 03:22:42 PM PDT 24
Finished Mar 26 03:22:44 PM PDT 24
Peak memory 200904 kb
Host smart-705da9af-ec92-4872-a757-7a872ea8930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337594453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2337594453
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1040660792
Short name T414
Test name
Test status
Simulation time 157825608 ps
CPU time 1.24 seconds
Started Mar 26 03:22:38 PM PDT 24
Finished Mar 26 03:22:40 PM PDT 24
Peak memory 200980 kb
Host smart-2b2be123-3bc7-4acb-9d7d-168286e46c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040660792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1040660792
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.955979959
Short name T333
Test name
Test status
Simulation time 63915483 ps
CPU time 0.84 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:22:54 PM PDT 24
Peak memory 200684 kb
Host smart-861a8915-f053-497c-b525-507f6bf3999c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955979959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.955979959
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2101445977
Short name T61
Test name
Test status
Simulation time 2347850993 ps
CPU time 9.02 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:23:03 PM PDT 24
Peak memory 218080 kb
Host smart-6b135806-02a1-44cc-814e-15c5065c0160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101445977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2101445977
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1970967213
Short name T494
Test name
Test status
Simulation time 244484757 ps
CPU time 1.17 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 218112 kb
Host smart-076e07d0-9f91-44c6-85c7-78257f8ced13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970967213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1970967213
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3324531672
Short name T506
Test name
Test status
Simulation time 86495663 ps
CPU time 0.79 seconds
Started Mar 26 03:22:48 PM PDT 24
Finished Mar 26 03:22:49 PM PDT 24
Peak memory 200636 kb
Host smart-21dba225-2b49-47af-92ed-ffc138ac6c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324531672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3324531672
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2806540685
Short name T393
Test name
Test status
Simulation time 1400245836 ps
CPU time 5.55 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:47 PM PDT 24
Peak memory 201028 kb
Host smart-8587cd94-e40c-4dd4-9fb9-39d661671944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806540685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2806540685
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4042058575
Short name T53
Test name
Test status
Simulation time 107112860 ps
CPU time 0.99 seconds
Started Mar 26 03:22:38 PM PDT 24
Finished Mar 26 03:22:40 PM PDT 24
Peak memory 200804 kb
Host smart-057c3c3c-bda5-4dd6-97be-4ff94ca5995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042058575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4042058575
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.714356946
Short name T86
Test name
Test status
Simulation time 259943255 ps
CPU time 1.5 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 200988 kb
Host smart-d4270eb3-b9aa-4faf-a096-99807397b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714356946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.714356946
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1518134759
Short name T272
Test name
Test status
Simulation time 3426801186 ps
CPU time 16.53 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 209340 kb
Host smart-f3132e57-d6b2-4743-bef7-24464e73b44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518134759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1518134759
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.4252758715
Short name T178
Test name
Test status
Simulation time 115163759 ps
CPU time 1.45 seconds
Started Mar 26 03:22:41 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 200776 kb
Host smart-cd32e7d9-fc4e-441b-a42a-7d55103a99d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252758715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.4252758715
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1901286867
Short name T202
Test name
Test status
Simulation time 143246448 ps
CPU time 1.14 seconds
Started Mar 26 03:22:39 PM PDT 24
Finished Mar 26 03:22:40 PM PDT 24
Peak memory 200804 kb
Host smart-237d7062-620c-4c99-9843-c5b697ee62af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901286867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1901286867
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2603917967
Short name T177
Test name
Test status
Simulation time 64451022 ps
CPU time 0.83 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200720 kb
Host smart-9717c915-f61c-4dac-ba6d-9c13efd8cae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603917967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2603917967
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3723226150
Short name T199
Test name
Test status
Simulation time 245276993 ps
CPU time 1.14 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 218084 kb
Host smart-75ac5237-b0f3-44b2-a00b-5175e387738f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723226150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3723226150
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3134369337
Short name T486
Test name
Test status
Simulation time 167442689 ps
CPU time 0.86 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200708 kb
Host smart-72ca1aec-6758-4313-a2e8-c2cd9ca2047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134369337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3134369337
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.758059045
Short name T358
Test name
Test status
Simulation time 1794162950 ps
CPU time 7.53 seconds
Started Mar 26 03:22:58 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 201016 kb
Host smart-81d7cd5a-3518-4e7e-9a39-28fd051d4177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758059045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.758059045
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3499326950
Short name T340
Test name
Test status
Simulation time 150159426 ps
CPU time 1.21 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200872 kb
Host smart-f1f83390-2240-4320-8c0f-f7b3f60a127c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499326950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3499326950
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1830339120
Short name T239
Test name
Test status
Simulation time 196957995 ps
CPU time 1.44 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:03 PM PDT 24
Peak memory 201012 kb
Host smart-3cd4ff82-e97d-45d3-a5bf-0c8f603d9fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830339120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1830339120
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3313013431
Short name T111
Test name
Test status
Simulation time 4371222535 ps
CPU time 18.8 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:23:11 PM PDT 24
Peak memory 210944 kb
Host smart-4c9b6a39-73d9-4f28-acb4-22f33ba9c34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313013431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3313013431
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1696739789
Short name T169
Test name
Test status
Simulation time 371609481 ps
CPU time 2.31 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200856 kb
Host smart-a339257f-2a82-4ea9-9c12-277f0b83fd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696739789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1696739789
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3586004594
Short name T63
Test name
Test status
Simulation time 99064670 ps
CPU time 0.93 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:22:54 PM PDT 24
Peak memory 200824 kb
Host smart-16b1bd78-c749-4a2e-9830-9e973466a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586004594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3586004594
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.783219828
Short name T331
Test name
Test status
Simulation time 77273894 ps
CPU time 0.79 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200676 kb
Host smart-2079574f-9956-4b14-bfe2-5feec8dd59b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783219828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.783219828
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2488305364
Short name T43
Test name
Test status
Simulation time 2198637390 ps
CPU time 8.26 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 221748 kb
Host smart-3ec3880c-38da-427a-92f5-4eb8b7338d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488305364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2488305364
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3390590714
Short name T347
Test name
Test status
Simulation time 244829397 ps
CPU time 1.1 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 218244 kb
Host smart-3ecdf1e4-8ad1-4512-a47c-b38a372ba022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390590714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3390590714
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.706655520
Short name T287
Test name
Test status
Simulation time 223987137 ps
CPU time 0.92 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200696 kb
Host smart-8f5218f1-3e2c-4eff-b185-fe1c8cb32270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706655520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.706655520
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3322572251
Short name T392
Test name
Test status
Simulation time 1348340931 ps
CPU time 5.78 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:23:00 PM PDT 24
Peak memory 200996 kb
Host smart-5bb8a6be-be56-4563-991b-ff82a48fd07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322572251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3322572251
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.4173270420
Short name T369
Test name
Test status
Simulation time 143244586 ps
CPU time 1.12 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200836 kb
Host smart-baeda8cb-0ce0-46d8-af48-a551c60b481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173270420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.4173270420
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1628003347
Short name T184
Test name
Test status
Simulation time 122118523 ps
CPU time 1.18 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200588 kb
Host smart-23714532-11ae-4aa4-b3e2-0c5e0c7cf1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628003347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1628003347
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3945142632
Short name T181
Test name
Test status
Simulation time 7333421722 ps
CPU time 29.36 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:23:24 PM PDT 24
Peak memory 209336 kb
Host smart-66cd64c9-e4b0-447e-879a-bd65330cd745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945142632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3945142632
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.977416229
Short name T14
Test name
Test status
Simulation time 141578107 ps
CPU time 1.89 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 200864 kb
Host smart-cfa5bb1e-492d-48d0-a217-ca8f964819ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977416229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.977416229
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3163859192
Short name T196
Test name
Test status
Simulation time 133748731 ps
CPU time 1.12 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200796 kb
Host smart-0402a4ac-7c24-4353-844a-a1c2bd863a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163859192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3163859192
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1823675174
Short name T489
Test name
Test status
Simulation time 78857983 ps
CPU time 0.83 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 200160 kb
Host smart-35f5556a-5460-4ca5-b9d9-8678e1c7562b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823675174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1823675174
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2217502135
Short name T459
Test name
Test status
Simulation time 1214867261 ps
CPU time 5.89 seconds
Started Mar 26 03:22:51 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 218540 kb
Host smart-5f63fbfa-ce60-4f6a-8a2f-6e9da408e4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217502135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2217502135
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3203143204
Short name T528
Test name
Test status
Simulation time 244161908 ps
CPU time 1.17 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:00 PM PDT 24
Peak memory 218128 kb
Host smart-081d3a83-c829-4d51-8704-d2062a46d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203143204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3203143204
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2864210424
Short name T18
Test name
Test status
Simulation time 158486197 ps
CPU time 0.85 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200708 kb
Host smart-34f8ed0a-d76a-4220-a2be-5ffc547a11f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864210424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2864210424
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1070473542
Short name T462
Test name
Test status
Simulation time 1655872077 ps
CPU time 6.76 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 201048 kb
Host smart-3fa5bef8-ae2e-4e02-8513-b5de2cb041af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070473542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1070473542
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2388364187
Short name T364
Test name
Test status
Simulation time 188993117 ps
CPU time 1.22 seconds
Started Mar 26 03:22:52 PM PDT 24
Finished Mar 26 03:22:54 PM PDT 24
Peak memory 200792 kb
Host smart-c6026546-435c-495d-b334-f7bcbc1c5aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388364187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2388364187
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.757084009
Short name T411
Test name
Test status
Simulation time 118035715 ps
CPU time 1.24 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 201012 kb
Host smart-9d009551-f83a-4b4c-aabf-28b66617be21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757084009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.757084009
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.4192916749
Short name T386
Test name
Test status
Simulation time 242694216 ps
CPU time 1.41 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 201024 kb
Host smart-01fc0858-c65f-49c2-84c0-eb7d4adf3f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192916749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.4192916749
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3714445245
Short name T363
Test name
Test status
Simulation time 410083877 ps
CPU time 2.36 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 209144 kb
Host smart-f6fb11e5-6cd7-4d1a-80dc-79010bd3c00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714445245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3714445245
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1822629660
Short name T441
Test name
Test status
Simulation time 88784655 ps
CPU time 0.84 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200832 kb
Host smart-6f2b1566-33b2-43f3-8026-567ca60ac0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822629660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1822629660
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.524296936
Short name T424
Test name
Test status
Simulation time 72779184 ps
CPU time 0.82 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200704 kb
Host smart-b0a1eb79-8d4d-4c20-8d92-80690a6c6271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524296936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.524296936
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2261649573
Short name T36
Test name
Test status
Simulation time 1886622860 ps
CPU time 7.44 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:23:08 PM PDT 24
Peak memory 221552 kb
Host smart-6bffc3df-8540-4880-9f1e-1317accdad5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261649573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2261649573
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.16271179
Short name T222
Test name
Test status
Simulation time 244360056 ps
CPU time 1.06 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:22:54 PM PDT 24
Peak memory 218048 kb
Host smart-852001bf-b019-4d0c-957e-30bb40fb7997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16271179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.16271179
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2705896026
Short name T543
Test name
Test status
Simulation time 173485823 ps
CPU time 0.9 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200308 kb
Host smart-bb64be1e-fb69-4617-8bb1-b64ca898181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705896026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2705896026
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.742691772
Short name T324
Test name
Test status
Simulation time 1849760609 ps
CPU time 6.81 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:23:02 PM PDT 24
Peak memory 200936 kb
Host smart-51a762b9-686a-434f-9527-66887c3a9f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742691772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.742691772
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1221777672
Short name T253
Test name
Test status
Simulation time 105872291 ps
CPU time 1.01 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200836 kb
Host smart-33345e95-49c0-41d2-9879-b950232becad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221777672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1221777672
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2085132651
Short name T179
Test name
Test status
Simulation time 228286197 ps
CPU time 1.54 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 200508 kb
Host smart-4cb4f727-97cf-406a-b2ac-6d21adee36b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085132651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2085132651
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1733221122
Short name T492
Test name
Test status
Simulation time 3234472074 ps
CPU time 16.37 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:23:12 PM PDT 24
Peak memory 201128 kb
Host smart-62782aa9-7279-43b0-a1ce-002983633999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733221122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1733221122
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1745952796
Short name T544
Test name
Test status
Simulation time 274246226 ps
CPU time 1.85 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:03 PM PDT 24
Peak memory 200884 kb
Host smart-e0138f2e-8506-404b-bc99-1718f1f68113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745952796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1745952796
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.577010771
Short name T342
Test name
Test status
Simulation time 84900965 ps
CPU time 0.84 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200860 kb
Host smart-31c213be-634c-4528-8bfb-e750112673e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577010771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.577010771
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1552009407
Short name T150
Test name
Test status
Simulation time 81650927 ps
CPU time 0.89 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200744 kb
Host smart-880ff1a5-41fc-476b-908c-c1564f1a70db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552009407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1552009407
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3626855645
Short name T67
Test name
Test status
Simulation time 2375180584 ps
CPU time 8.08 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:23:02 PM PDT 24
Peak memory 218660 kb
Host smart-2ebdc1bb-c5de-4915-aa93-429f789fde1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626855645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3626855645
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.375498377
Short name T481
Test name
Test status
Simulation time 243736373 ps
CPU time 1.02 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 218136 kb
Host smart-c68a1298-061c-4ec5-b5d9-c39ee5982fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375498377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.375498377
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2236371983
Short name T336
Test name
Test status
Simulation time 163368209 ps
CPU time 0.85 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200724 kb
Host smart-c8a8fe8e-147f-4227-a303-090ce506be02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236371983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2236371983
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.191612923
Short name T188
Test name
Test status
Simulation time 998958083 ps
CPU time 4.86 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:59 PM PDT 24
Peak memory 200992 kb
Host smart-10cc4ab2-5228-4380-abc2-0b431303aec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191612923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.191612923
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.173010307
Short name T373
Test name
Test status
Simulation time 188781335 ps
CPU time 1.18 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200848 kb
Host smart-0ced4530-ff11-434c-af26-47e45f91be45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173010307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.173010307
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.4011356201
Short name T16
Test name
Test status
Simulation time 118856109 ps
CPU time 1.27 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 201016 kb
Host smart-eb8937b4-8607-4001-84b4-11edb0862804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011356201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.4011356201
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2745127300
Short name T295
Test name
Test status
Simulation time 3415094422 ps
CPU time 16.69 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:23:10 PM PDT 24
Peak memory 201308 kb
Host smart-14df4917-93c0-4cad-ab9b-2de5adc0b189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745127300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2745127300
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2449027756
Short name T534
Test name
Test status
Simulation time 383455600 ps
CPU time 2.43 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200888 kb
Host smart-a92a0800-2fd2-448a-bf17-e879fb1738a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449027756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2449027756
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2992659078
Short name T337
Test name
Test status
Simulation time 153734570 ps
CPU time 1.27 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 201008 kb
Host smart-1b3e381b-8145-4442-93a6-5632e437beb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992659078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2992659078
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3762161857
Short name T161
Test name
Test status
Simulation time 83532225 ps
CPU time 0.82 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:22:54 PM PDT 24
Peak memory 200680 kb
Host smart-19c65b11-8c1f-4f85-879c-3e6fa19582b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762161857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3762161857
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3779689177
Short name T59
Test name
Test status
Simulation time 1237541799 ps
CPU time 5.75 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:23:01 PM PDT 24
Peak memory 218012 kb
Host smart-491ee827-ff73-415e-a1d3-51e034f42ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779689177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3779689177
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1341021678
Short name T205
Test name
Test status
Simulation time 244165800 ps
CPU time 1.2 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 218096 kb
Host smart-fe3a14ec-2b35-4e00-9d52-f74f05019533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341021678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1341021678
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.847954774
Short name T474
Test name
Test status
Simulation time 172576442 ps
CPU time 0.88 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:54 PM PDT 24
Peak memory 200688 kb
Host smart-a6b87ea7-7f16-4adf-bfe5-6706f0316123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847954774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.847954774
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1663572077
Short name T405
Test name
Test status
Simulation time 1831162985 ps
CPU time 8.04 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 201016 kb
Host smart-fccaf1e5-4061-48c4-b9c3-6bd346a049ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663572077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1663572077
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3397306570
Short name T151
Test name
Test status
Simulation time 102650301 ps
CPU time 1.07 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 200784 kb
Host smart-6d42a43d-452e-4392-b632-069cd700665a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397306570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3397306570
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1796006342
Short name T13
Test name
Test status
Simulation time 187822698 ps
CPU time 1.42 seconds
Started Mar 26 03:22:52 PM PDT 24
Finished Mar 26 03:22:53 PM PDT 24
Peak memory 200980 kb
Host smart-702b109b-1eb2-4a91-a1af-096823e8c749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796006342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1796006342
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.225625169
Short name T116
Test name
Test status
Simulation time 3933319442 ps
CPU time 15.98 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:23:11 PM PDT 24
Peak memory 209320 kb
Host smart-f3f56d39-43e8-4ddf-b6d4-2b95f8733d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225625169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.225625169
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2589947131
Short name T320
Test name
Test status
Simulation time 446613015 ps
CPU time 2.48 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200868 kb
Host smart-fba211a9-754c-466e-abac-bc9c4baef7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589947131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2589947131
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2476000548
Short name T249
Test name
Test status
Simulation time 147318001 ps
CPU time 1.01 seconds
Started Mar 26 03:22:52 PM PDT 24
Finished Mar 26 03:22:54 PM PDT 24
Peak memory 200828 kb
Host smart-a21d521c-740c-45ab-b68f-6bee9c10dafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476000548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2476000548
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2363161673
Short name T470
Test name
Test status
Simulation time 64653703 ps
CPU time 0.77 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200684 kb
Host smart-b84047d0-f75a-475f-9740-3c252a8e5fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363161673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2363161673
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3972174194
Short name T33
Test name
Test status
Simulation time 1223867337 ps
CPU time 6.08 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:23:02 PM PDT 24
Peak memory 222552 kb
Host smart-1e412b01-ab36-4fda-a28b-21449a45b106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972174194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3972174194
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1427964382
Short name T432
Test name
Test status
Simulation time 244455433 ps
CPU time 1.12 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 218080 kb
Host smart-ed3a2722-c693-4a61-a836-69dfa6367183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427964382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1427964382
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1096548848
Short name T248
Test name
Test status
Simulation time 228285361 ps
CPU time 0.96 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 200676 kb
Host smart-d8a773fc-f225-4930-867b-97d0af6beae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096548848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1096548848
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.4019538325
Short name T536
Test name
Test status
Simulation time 977756167 ps
CPU time 5 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:59 PM PDT 24
Peak memory 201012 kb
Host smart-a6e1cef6-31b2-406b-b4c7-6c185545ecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019538325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4019538325
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3776415765
Short name T278
Test name
Test status
Simulation time 106287764 ps
CPU time 0.97 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 200812 kb
Host smart-b0b03d5b-6a72-41c8-8cc5-09e805d4ece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776415765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3776415765
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2598065398
Short name T435
Test name
Test status
Simulation time 111416177 ps
CPU time 1.19 seconds
Started Mar 26 03:22:54 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200992 kb
Host smart-8f672546-140e-4638-8704-c098d22892f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598065398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2598065398
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3485600004
Short name T301
Test name
Test status
Simulation time 5400912273 ps
CPU time 19.52 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:23:15 PM PDT 24
Peak memory 209308 kb
Host smart-f1b7c527-77a9-41ea-b2a4-ca7c261fcb44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485600004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3485600004
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2440084344
Short name T488
Test name
Test status
Simulation time 297617200 ps
CPU time 2.03 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 209056 kb
Host smart-7c4d849c-6d80-448c-b094-2721caa36691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440084344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2440084344
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.388914324
Short name T176
Test name
Test status
Simulation time 293875166 ps
CPU time 1.76 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200984 kb
Host smart-4655008d-e549-451e-8994-cb8851e54c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388914324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.388914324
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2133962406
Short name T417
Test name
Test status
Simulation time 63983229 ps
CPU time 0.76 seconds
Started Mar 26 03:22:13 PM PDT 24
Finished Mar 26 03:22:14 PM PDT 24
Peak memory 200708 kb
Host smart-4bad8ff5-fdf2-4aa6-afae-c0065a1a00a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133962406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2133962406
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.407916269
Short name T32
Test name
Test status
Simulation time 2360055486 ps
CPU time 9.61 seconds
Started Mar 26 03:22:09 PM PDT 24
Finished Mar 26 03:22:19 PM PDT 24
Peak memory 222716 kb
Host smart-8847d2e5-fc15-4d39-b5af-ef14a1260a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407916269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.407916269
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1502968676
Short name T368
Test name
Test status
Simulation time 244038848 ps
CPU time 1.05 seconds
Started Mar 26 03:22:08 PM PDT 24
Finished Mar 26 03:22:09 PM PDT 24
Peak memory 218068 kb
Host smart-dd8f7200-1864-4b77-bbc5-eb0c3689cf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502968676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1502968676
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.4124620417
Short name T327
Test name
Test status
Simulation time 199731580 ps
CPU time 0.89 seconds
Started Mar 26 03:22:07 PM PDT 24
Finished Mar 26 03:22:08 PM PDT 24
Peak memory 200668 kb
Host smart-3a1cf867-4423-46d6-a08f-0790f3828411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124620417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.4124620417
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.4136860136
Short name T402
Test name
Test status
Simulation time 828212889 ps
CPU time 4.1 seconds
Started Mar 26 03:22:07 PM PDT 24
Finished Mar 26 03:22:12 PM PDT 24
Peak memory 201044 kb
Host smart-36ebe969-b7ce-4dba-bc8b-db3171afbca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136860136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4136860136
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3100010264
Short name T76
Test name
Test status
Simulation time 16515618408 ps
CPU time 27.88 seconds
Started Mar 26 03:22:09 PM PDT 24
Finished Mar 26 03:22:37 PM PDT 24
Peak memory 217800 kb
Host smart-ec23a7db-415b-4112-8bc8-99ea9b02acf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100010264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3100010264
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3624548503
Short name T529
Test name
Test status
Simulation time 101155726 ps
CPU time 1 seconds
Started Mar 26 03:22:11 PM PDT 24
Finished Mar 26 03:22:12 PM PDT 24
Peak memory 200828 kb
Host smart-986705d5-5d4c-4bfd-b958-e9a5455797ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624548503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3624548503
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3191924253
Short name T283
Test name
Test status
Simulation time 131235704 ps
CPU time 1.22 seconds
Started Mar 26 03:22:07 PM PDT 24
Finished Mar 26 03:22:08 PM PDT 24
Peak memory 201004 kb
Host smart-ca91d9a5-0e55-4011-98f0-0c8eda7b38d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191924253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3191924253
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.424255818
Short name T357
Test name
Test status
Simulation time 2828636684 ps
CPU time 13.36 seconds
Started Mar 26 03:22:08 PM PDT 24
Finished Mar 26 03:22:22 PM PDT 24
Peak memory 200996 kb
Host smart-4ae1548d-61e3-431f-b5a3-f059453c99be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424255818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.424255818
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2274263781
Short name T284
Test name
Test status
Simulation time 120151339 ps
CPU time 1.5 seconds
Started Mar 26 03:22:09 PM PDT 24
Finished Mar 26 03:22:10 PM PDT 24
Peak memory 200836 kb
Host smart-c5b42203-a578-468c-ab86-501e30787aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274263781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2274263781
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2111257263
Short name T304
Test name
Test status
Simulation time 225527257 ps
CPU time 1.53 seconds
Started Mar 26 03:22:02 PM PDT 24
Finished Mar 26 03:22:04 PM PDT 24
Peak memory 200788 kb
Host smart-3ab15bfa-cb47-41c6-b9b9-f374dbedacbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111257263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2111257263
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3824778386
Short name T297
Test name
Test status
Simulation time 72938435 ps
CPU time 0.77 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:00 PM PDT 24
Peak memory 200608 kb
Host smart-a84faf25-df33-4e9c-805b-f4754a5d6650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824778386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3824778386
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3273164489
Short name T285
Test name
Test status
Simulation time 2364512837 ps
CPU time 9.13 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 218632 kb
Host smart-48b3a550-1f86-4020-adba-0edbc5dac41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273164489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3273164489
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.100288187
Short name T498
Test name
Test status
Simulation time 244946246 ps
CPU time 1.21 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 218136 kb
Host smart-6c4e757b-b9c3-4b8c-aefd-b46a5c7763e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100288187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.100288187
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3084097353
Short name T412
Test name
Test status
Simulation time 169416099 ps
CPU time 0.86 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 200660 kb
Host smart-e3ae58cc-235c-4cab-9778-5067079eb7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084097353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3084097353
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2061354644
Short name T280
Test name
Test status
Simulation time 1906873092 ps
CPU time 7.02 seconds
Started Mar 26 03:22:58 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 201016 kb
Host smart-bc0e566c-a6e5-4bb1-b383-396a44f39cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061354644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2061354644
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.644086679
Short name T439
Test name
Test status
Simulation time 109815072 ps
CPU time 1.09 seconds
Started Mar 26 03:22:53 PM PDT 24
Finished Mar 26 03:22:55 PM PDT 24
Peak memory 200844 kb
Host smart-45983c71-ddee-4944-b979-199a5053ae98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644086679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.644086679
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2533600693
Short name T302
Test name
Test status
Simulation time 193243173 ps
CPU time 1.37 seconds
Started Mar 26 03:22:55 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 200992 kb
Host smart-b6a001d7-ce9a-4255-b49a-8b483465eab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533600693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2533600693
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3030020661
Short name T437
Test name
Test status
Simulation time 3214262631 ps
CPU time 11.92 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:23:08 PM PDT 24
Peak memory 209348 kb
Host smart-7fe66248-6c1e-4372-b586-21d28e2ca0f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030020661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3030020661
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4129553221
Short name T2
Test name
Test status
Simulation time 351611464 ps
CPU time 2.34 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:01 PM PDT 24
Peak memory 200852 kb
Host smart-05caa449-caf0-41ef-9420-1998ad6d4049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129553221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4129553221
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2911067895
Short name T376
Test name
Test status
Simulation time 103365708 ps
CPU time 0.92 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:01 PM PDT 24
Peak memory 200804 kb
Host smart-51d54b65-b3d1-483a-b89e-c747fce92605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911067895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2911067895
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2816688826
Short name T242
Test name
Test status
Simulation time 61830069 ps
CPU time 0.76 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200712 kb
Host smart-b8a2dc11-8f68-4192-b6c5-33d1b0893721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816688826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2816688826
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2582953761
Short name T480
Test name
Test status
Simulation time 1223086643 ps
CPU time 6.28 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:07 PM PDT 24
Peak memory 222440 kb
Host smart-52715f86-aec9-4b22-879f-3930764f46d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582953761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2582953761
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1801378570
Short name T251
Test name
Test status
Simulation time 245414288 ps
CPU time 1.04 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:01 PM PDT 24
Peak memory 218072 kb
Host smart-a83745ea-dad4-4d8d-bbf6-71c246303fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801378570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1801378570
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2778855505
Short name T19
Test name
Test status
Simulation time 206609205 ps
CPU time 0.9 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200752 kb
Host smart-671e80a0-65a5-4d0d-9f56-73cc0385ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778855505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2778855505
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1309938592
Short name T107
Test name
Test status
Simulation time 1783965635 ps
CPU time 6.97 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 200880 kb
Host smart-20ff3186-e7ba-42c6-a7e4-800e29229086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309938592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1309938592
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2730252974
Short name T384
Test name
Test status
Simulation time 136948377 ps
CPU time 1.07 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:01 PM PDT 24
Peak memory 200796 kb
Host smart-316f84c9-aff3-4a1e-b9cf-8ff2da51bb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730252974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2730252974
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2481009394
Short name T27
Test name
Test status
Simulation time 128938570 ps
CPU time 1.19 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 201064 kb
Host smart-4f7cfaf7-acab-40a2-95c1-435b66fd2266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481009394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2481009394
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1484073646
Short name T365
Test name
Test status
Simulation time 8492390762 ps
CPU time 29.4 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:29 PM PDT 24
Peak memory 209372 kb
Host smart-024ac44a-3a74-43e8-8409-561922e9bf15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484073646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1484073646
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.261418838
Short name T187
Test name
Test status
Simulation time 279242315 ps
CPU time 2.05 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 200848 kb
Host smart-d24333bd-3773-4d99-8d49-e72464674dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261418838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.261418838
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3816059723
Short name T482
Test name
Test status
Simulation time 220527601 ps
CPU time 1.44 seconds
Started Mar 26 03:22:58 PM PDT 24
Finished Mar 26 03:22:59 PM PDT 24
Peak memory 200844 kb
Host smart-6037550b-d9d9-4df8-9d0f-2c44ee6fed33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816059723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3816059723
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3956167286
Short name T468
Test name
Test status
Simulation time 86453812 ps
CPU time 0.83 seconds
Started Mar 26 03:22:58 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200704 kb
Host smart-7c968ff2-8df5-482e-9ede-ae9d6440cc96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956167286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3956167286
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3772713469
Short name T29
Test name
Test status
Simulation time 2359218534 ps
CPU time 8.81 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:11 PM PDT 24
Peak memory 222692 kb
Host smart-7164effe-7483-4677-b8a4-e9ffc382dc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772713469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3772713469
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.70455017
Short name T408
Test name
Test status
Simulation time 244197814 ps
CPU time 1.15 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:57 PM PDT 24
Peak memory 218088 kb
Host smart-7e375b79-eb69-4d51-bb3e-e9213f0c9aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70455017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.70455017
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.959342311
Short name T493
Test name
Test status
Simulation time 111202606 ps
CPU time 0.77 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 200748 kb
Host smart-28aeca83-7931-46c1-b3f3-af11ed4077ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959342311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.959342311
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1173375005
Short name T48
Test name
Test status
Simulation time 737946274 ps
CPU time 3.67 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 201020 kb
Host smart-70b778d0-b506-4453-ab35-872529133c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173375005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1173375005
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3932006507
Short name T483
Test name
Test status
Simulation time 93205466 ps
CPU time 0.96 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 200852 kb
Host smart-b055374d-d998-424c-94b3-ea4b545d745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932006507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3932006507
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.446225530
Short name T316
Test name
Test status
Simulation time 244417323 ps
CPU time 1.62 seconds
Started Mar 26 03:23:14 PM PDT 24
Finished Mar 26 03:23:16 PM PDT 24
Peak memory 201032 kb
Host smart-16bc78c0-c586-4823-b8be-ccde5a619029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446225530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.446225530
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2534023873
Short name T485
Test name
Test status
Simulation time 4786241826 ps
CPU time 21.22 seconds
Started Mar 26 03:22:58 PM PDT 24
Finished Mar 26 03:23:19 PM PDT 24
Peak memory 201084 kb
Host smart-2bf4b5a6-a552-4786-9b9a-d3120f28caa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534023873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2534023873
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3514062853
Short name T341
Test name
Test status
Simulation time 368740841 ps
CPU time 2.03 seconds
Started Mar 26 03:22:58 PM PDT 24
Finished Mar 26 03:23:00 PM PDT 24
Peak memory 200888 kb
Host smart-1a045c1a-4103-43c7-8ae9-d4a69d5bf002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514062853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3514062853
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3890198694
Short name T12
Test name
Test status
Simulation time 127907977 ps
CPU time 1.08 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:02 PM PDT 24
Peak memory 200832 kb
Host smart-27961e38-7c8a-4918-bf74-49cf6b3651f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890198694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3890198694
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.867927970
Short name T46
Test name
Test status
Simulation time 63606075 ps
CPU time 0.75 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:02 PM PDT 24
Peak memory 200648 kb
Host smart-c6e99969-a58d-4de5-b844-7ac96d020366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867927970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.867927970
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.4222651954
Short name T370
Test name
Test status
Simulation time 2155293036 ps
CPU time 8.08 seconds
Started Mar 26 03:23:20 PM PDT 24
Finished Mar 26 03:23:29 PM PDT 24
Peak memory 218660 kb
Host smart-fb934f10-371d-43c4-bb0e-91490fa66a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222651954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.4222651954
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3618094078
Short name T10
Test name
Test status
Simulation time 245163423 ps
CPU time 1.03 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:58 PM PDT 24
Peak memory 218124 kb
Host smart-3faf4ca6-b5a4-448d-8692-51636446f060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618094078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3618094078
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.131125110
Short name T348
Test name
Test status
Simulation time 190291688 ps
CPU time 0.89 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:01 PM PDT 24
Peak memory 200712 kb
Host smart-5912a080-371a-435f-9581-716b3adf5435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131125110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.131125110
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2082214991
Short name T238
Test name
Test status
Simulation time 1481300915 ps
CPU time 6.01 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 201016 kb
Host smart-6243af5a-0697-4e84-bcfb-b083f15d57ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082214991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2082214991
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2254411417
Short name T350
Test name
Test status
Simulation time 175987064 ps
CPU time 1.22 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:22:59 PM PDT 24
Peak memory 200828 kb
Host smart-a1500bc3-9316-40eb-a3c3-08795edaf43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254411417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2254411417
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.328466116
Short name T303
Test name
Test status
Simulation time 195107659 ps
CPU time 1.31 seconds
Started Mar 26 03:23:06 PM PDT 24
Finished Mar 26 03:23:07 PM PDT 24
Peak memory 201032 kb
Host smart-8b3047a5-b95a-4838-a2ad-5ad325e85617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328466116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.328466116
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.646385789
Short name T136
Test name
Test status
Simulation time 18596142243 ps
CPU time 61.08 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:24:04 PM PDT 24
Peak memory 201124 kb
Host smart-fa87f742-f762-4211-aea0-fcb166090af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646385789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.646385789
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3132977716
Short name T530
Test name
Test status
Simulation time 284202968 ps
CPU time 2.11 seconds
Started Mar 26 03:23:06 PM PDT 24
Finished Mar 26 03:23:08 PM PDT 24
Peak memory 209132 kb
Host smart-53214957-87d6-496d-9c2c-aa0c8ae44f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132977716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3132977716
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.983076829
Short name T243
Test name
Test status
Simulation time 75480519 ps
CPU time 0.86 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 200708 kb
Host smart-c43f20f4-5378-4c3d-b8c5-e5de07574b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983076829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.983076829
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1933108343
Short name T323
Test name
Test status
Simulation time 1887587275 ps
CPU time 7.41 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 218508 kb
Host smart-99a39b6a-2fb8-4d50-8141-d05367021bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933108343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1933108343
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1922842391
Short name T210
Test name
Test status
Simulation time 244784258 ps
CPU time 1.04 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:03 PM PDT 24
Peak memory 218192 kb
Host smart-b758a99a-bf4c-48d7-bcd1-b2ca6a79d211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922842391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1922842391
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2005351619
Short name T425
Test name
Test status
Simulation time 88814782 ps
CPU time 0.8 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200696 kb
Host smart-5ffeae2f-f1d9-4f9c-859f-375262c5f35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005351619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2005351619
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1472436976
Short name T155
Test name
Test status
Simulation time 1266047195 ps
CPU time 4.92 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:08 PM PDT 24
Peak memory 201024 kb
Host smart-6302d350-dd6f-48df-986d-45b2b53dccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472436976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1472436976
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2816909384
Short name T355
Test name
Test status
Simulation time 96323474 ps
CPU time 1 seconds
Started Mar 26 03:23:07 PM PDT 24
Finished Mar 26 03:23:08 PM PDT 24
Peak memory 200816 kb
Host smart-160b8d5d-725f-4c92-9e74-29e9e6dd23b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816909384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2816909384
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3858171139
Short name T252
Test name
Test status
Simulation time 113654538 ps
CPU time 1.18 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:01 PM PDT 24
Peak memory 201016 kb
Host smart-4ab126b1-8721-4fc6-8d59-e7d3b09f0408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858171139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3858171139
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3940551767
Short name T452
Test name
Test status
Simulation time 6002168901 ps
CPU time 25.74 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:26 PM PDT 24
Peak memory 201032 kb
Host smart-f916db46-62f9-47ef-b862-4fc67155353f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940551767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3940551767
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.802537415
Short name T398
Test name
Test status
Simulation time 373249427 ps
CPU time 2.62 seconds
Started Mar 26 03:22:56 PM PDT 24
Finished Mar 26 03:22:59 PM PDT 24
Peak memory 200900 kb
Host smart-ef86b554-8cf9-4196-ac71-051b26e67713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802537415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.802537415
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1505924514
Short name T314
Test name
Test status
Simulation time 111826204 ps
CPU time 0.92 seconds
Started Mar 26 03:23:09 PM PDT 24
Finished Mar 26 03:23:10 PM PDT 24
Peak memory 200828 kb
Host smart-99f46a79-bb20-457d-801c-02c9ab6b9b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505924514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1505924514
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3239039647
Short name T523
Test name
Test status
Simulation time 75581181 ps
CPU time 0.81 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:03 PM PDT 24
Peak memory 200716 kb
Host smart-45785cf6-16ad-4da6-8136-a741b4d565bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239039647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3239039647
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1248853769
Short name T308
Test name
Test status
Simulation time 2356581791 ps
CPU time 8.08 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:08 PM PDT 24
Peak memory 222680 kb
Host smart-adedbba5-f1dc-4abd-889f-0eb47ed7de05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248853769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1248853769
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3707868898
Short name T496
Test name
Test status
Simulation time 244326428 ps
CPU time 1.07 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:01 PM PDT 24
Peak memory 218040 kb
Host smart-99324029-84b9-49f3-9054-1bb818b3f41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707868898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3707868898
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.4099907147
Short name T471
Test name
Test status
Simulation time 190577924 ps
CPU time 0.91 seconds
Started Mar 26 03:22:58 PM PDT 24
Finished Mar 26 03:22:59 PM PDT 24
Peak memory 200680 kb
Host smart-3abd4eaf-e45e-4f53-a748-3a50485da4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099907147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.4099907147
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3382173648
Short name T114
Test name
Test status
Simulation time 1775259460 ps
CPU time 7.03 seconds
Started Mar 26 03:23:09 PM PDT 24
Finished Mar 26 03:23:17 PM PDT 24
Peak memory 201004 kb
Host smart-616ff794-945c-4f9f-b0b9-d160101f4a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382173648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3382173648
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1389675710
Short name T421
Test name
Test status
Simulation time 102486557 ps
CPU time 0.95 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 200852 kb
Host smart-970e5cdf-4d2e-4221-a8b5-e4a26eab4984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389675710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1389675710
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1991732208
Short name T359
Test name
Test status
Simulation time 127328340 ps
CPU time 1.22 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 201020 kb
Host smart-9339cdc3-b0d7-4a10-9b86-ca7cf6355cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991732208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1991732208
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.887476387
Short name T511
Test name
Test status
Simulation time 1294008348 ps
CPU time 6.64 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 201028 kb
Host smart-00ede1ad-497e-45dc-bcf5-e54eadb767da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887476387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.887476387
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3587760265
Short name T66
Test name
Test status
Simulation time 501408828 ps
CPU time 2.5 seconds
Started Mar 26 03:22:58 PM PDT 24
Finished Mar 26 03:23:01 PM PDT 24
Peak memory 200892 kb
Host smart-016a990e-c009-4118-887d-d71186286eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587760265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3587760265
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1274967651
Short name T226
Test name
Test status
Simulation time 72827821 ps
CPU time 0.78 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:03 PM PDT 24
Peak memory 200796 kb
Host smart-6fcc4f5c-8007-46af-97aa-9ed5f3de2f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274967651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1274967651
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2348524836
Short name T175
Test name
Test status
Simulation time 76033242 ps
CPU time 0.82 seconds
Started Mar 26 03:23:06 PM PDT 24
Finished Mar 26 03:23:07 PM PDT 24
Peak memory 200700 kb
Host smart-eeef7fb3-4476-40fc-9ad4-465af8c0b4db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348524836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2348524836
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1899735041
Short name T15
Test name
Test status
Simulation time 1220632234 ps
CPU time 5.82 seconds
Started Mar 26 03:23:12 PM PDT 24
Finished Mar 26 03:23:17 PM PDT 24
Peak memory 217404 kb
Host smart-c10f0554-5223-4b2a-a637-295539f5f3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899735041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1899735041
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1381540653
Short name T311
Test name
Test status
Simulation time 243330779 ps
CPU time 1.07 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:03 PM PDT 24
Peak memory 218076 kb
Host smart-ff9e2c25-aa35-4385-8889-3bc8b9808ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381540653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1381540653
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3827052641
Short name T298
Test name
Test status
Simulation time 96907076 ps
CPU time 0.77 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:00 PM PDT 24
Peak memory 200680 kb
Host smart-f1d442a1-dd56-45c4-9d6b-0dbf993767e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827052641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3827052641
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3011665185
Short name T262
Test name
Test status
Simulation time 906364973 ps
CPU time 4.42 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200912 kb
Host smart-ef248cdd-de54-4c68-b3f0-655f8580c9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011665185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3011665185
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1723747828
Short name T191
Test name
Test status
Simulation time 104774702 ps
CPU time 1.02 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 200852 kb
Host smart-1b6db314-ae8f-4448-9610-1e92361a105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723747828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1723747828
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2454198478
Short name T165
Test name
Test status
Simulation time 117534237 ps
CPU time 1.17 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:03 PM PDT 24
Peak memory 200988 kb
Host smart-86a1fbea-356b-482f-a28f-ed997cc06f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454198478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2454198478
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.735832248
Short name T545
Test name
Test status
Simulation time 3007141232 ps
CPU time 10.34 seconds
Started Mar 26 03:22:57 PM PDT 24
Finished Mar 26 03:23:07 PM PDT 24
Peak memory 201092 kb
Host smart-5db8f700-47af-4faa-8a5e-6d004fe84332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735832248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.735832248
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3051733640
Short name T466
Test name
Test status
Simulation time 124523250 ps
CPU time 1.47 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:02 PM PDT 24
Peak memory 200888 kb
Host smart-bc86e259-2921-4277-b226-91a008674b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051733640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3051733640
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1752120041
Short name T186
Test name
Test status
Simulation time 235998972 ps
CPU time 1.57 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:03 PM PDT 24
Peak memory 200832 kb
Host smart-9f9ee832-4ab0-4713-828f-a9e1e64dad45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752120041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1752120041
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.312463120
Short name T500
Test name
Test status
Simulation time 88656523 ps
CPU time 0.8 seconds
Started Mar 26 03:23:05 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200676 kb
Host smart-49ce44ae-6d40-4423-97df-6c2084673b32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312463120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.312463120
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2740312575
Short name T443
Test name
Test status
Simulation time 1226912366 ps
CPU time 5.61 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 218512 kb
Host smart-fa74401f-3703-4a4e-b656-da1054920454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740312575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2740312575
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3340972004
Short name T154
Test name
Test status
Simulation time 244106481 ps
CPU time 1.07 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 218140 kb
Host smart-0d979060-8d44-405d-8700-b298f2ebd59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340972004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3340972004
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.4228194647
Short name T23
Test name
Test status
Simulation time 194537180 ps
CPU time 0.87 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 200696 kb
Host smart-4f14940e-f711-4f91-9b7c-c681ef90aaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228194647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.4228194647
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2621664125
Short name T339
Test name
Test status
Simulation time 1365794084 ps
CPU time 5.28 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 201008 kb
Host smart-4b90ad2c-5b7e-4edb-8621-8afb07e0ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621664125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2621664125
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2242944492
Short name T326
Test name
Test status
Simulation time 155283896 ps
CPU time 1.09 seconds
Started Mar 26 03:23:02 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 200836 kb
Host smart-f0882fe6-5221-4a4b-b0d6-286b840d7c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242944492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2242944492
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2848199578
Short name T230
Test name
Test status
Simulation time 121661122 ps
CPU time 1.18 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:00 PM PDT 24
Peak memory 200984 kb
Host smart-25d5c189-ca7e-458a-b03f-865d38e54b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848199578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2848199578
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2941852365
Short name T115
Test name
Test status
Simulation time 4314347786 ps
CPU time 19.16 seconds
Started Mar 26 03:22:59 PM PDT 24
Finished Mar 26 03:23:18 PM PDT 24
Peak memory 201132 kb
Host smart-51c8474f-91a8-4266-8248-51550f013fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941852365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2941852365
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2696501198
Short name T158
Test name
Test status
Simulation time 155856831 ps
CPU time 1.81 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:02 PM PDT 24
Peak memory 200892 kb
Host smart-2897b907-2631-493e-a43a-2b727fb0739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696501198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2696501198
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1995372047
Short name T541
Test name
Test status
Simulation time 138439633 ps
CPU time 1.07 seconds
Started Mar 26 03:23:05 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200840 kb
Host smart-b23ee19b-4692-4aa9-b865-48264e873be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995372047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1995372047
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3459898172
Short name T426
Test name
Test status
Simulation time 58689900 ps
CPU time 0.76 seconds
Started Mar 26 03:23:05 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200684 kb
Host smart-4a7c54b4-169f-4bcc-b599-3d0a4aef29ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459898172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3459898172
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3237961288
Short name T380
Test name
Test status
Simulation time 1223835549 ps
CPU time 5.36 seconds
Started Mar 26 03:23:05 PM PDT 24
Finished Mar 26 03:23:11 PM PDT 24
Peak memory 222092 kb
Host smart-26dc262a-1515-452f-bd68-b397d260f8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237961288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3237961288
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1743982440
Short name T445
Test name
Test status
Simulation time 244278358 ps
CPU time 1.09 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 218108 kb
Host smart-7e57a62e-b681-4b24-b51e-ebf62807dcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743982440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1743982440
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.296626128
Short name T404
Test name
Test status
Simulation time 114071032 ps
CPU time 0.76 seconds
Started Mar 26 03:23:05 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200680 kb
Host smart-04e474d7-c4df-4576-801c-e6e105dd8de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296626128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.296626128
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3378852030
Short name T381
Test name
Test status
Simulation time 1264876787 ps
CPU time 5.21 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 201056 kb
Host smart-4c5fcc31-4c39-4a7e-99c6-25d65521679c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378852030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3378852030
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1356191281
Short name T513
Test name
Test status
Simulation time 112108840 ps
CPU time 1.04 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200840 kb
Host smart-2fab2f20-fa2b-4905-bb0a-b2b1736864ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356191281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1356191281
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3051278793
Short name T247
Test name
Test status
Simulation time 113321547 ps
CPU time 1.21 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 200964 kb
Host smart-5c462798-9e33-4106-8f4c-ed02a7e1a201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051278793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3051278793
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2507525228
Short name T403
Test name
Test status
Simulation time 8739936756 ps
CPU time 27.67 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:31 PM PDT 24
Peak memory 209304 kb
Host smart-80196c96-7ba6-46e3-af62-c4b7314045c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507525228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2507525228
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2665659652
Short name T93
Test name
Test status
Simulation time 383250695 ps
CPU time 2.1 seconds
Started Mar 26 03:22:58 PM PDT 24
Finished Mar 26 03:23:00 PM PDT 24
Peak memory 200856 kb
Host smart-0d886783-21b5-47c3-808f-5a62e68f4ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665659652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2665659652
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2401191750
Short name T420
Test name
Test status
Simulation time 128614453 ps
CPU time 1.11 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 200836 kb
Host smart-ad01bd13-09cf-4c7e-b786-992d2335d3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401191750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2401191750
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.950071103
Short name T183
Test name
Test status
Simulation time 72193959 ps
CPU time 0.79 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 200696 kb
Host smart-23e394c5-870b-48d6-9caf-69f708833efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950071103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.950071103
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.547676769
Short name T517
Test name
Test status
Simulation time 1896586765 ps
CPU time 7.9 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:12 PM PDT 24
Peak memory 222560 kb
Host smart-e35faea8-89ac-4bed-9ef3-eb0e1be7b33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547676769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.547676769
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1848458796
Short name T332
Test name
Test status
Simulation time 244067928 ps
CPU time 1.14 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 218228 kb
Host smart-8dd95c1e-c74b-4221-b32c-f656869327ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848458796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1848458796
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.993111468
Short name T306
Test name
Test status
Simulation time 135707683 ps
CPU time 0.82 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 200672 kb
Host smart-50e437a4-a68c-4eee-9c07-beef65a84e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993111468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.993111468
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3456064698
Short name T250
Test name
Test status
Simulation time 923570326 ps
CPU time 4.54 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:07 PM PDT 24
Peak memory 201012 kb
Host smart-bffcb466-0b20-497c-8014-95fd3cc95772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456064698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3456064698
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1293538650
Short name T62
Test name
Test status
Simulation time 149580529 ps
CPU time 1.13 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:02 PM PDT 24
Peak memory 200792 kb
Host smart-ecc55ddc-59d3-40cf-a639-b682c3dbe5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293538650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1293538650
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1223488182
Short name T328
Test name
Test status
Simulation time 228457236 ps
CPU time 1.51 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 201024 kb
Host smart-69282698-7e80-4893-9efc-05b0bb53f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223488182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1223488182
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3996331786
Short name T338
Test name
Test status
Simulation time 234247575 ps
CPU time 1.39 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:04 PM PDT 24
Peak memory 201044 kb
Host smart-8944631a-2e10-4b25-b359-ee57880530fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996331786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3996331786
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1547979863
Short name T163
Test name
Test status
Simulation time 440287389 ps
CPU time 2.5 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200864 kb
Host smart-007411b0-d7e7-4146-b288-6899386367c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547979863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1547979863
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.85317000
Short name T220
Test name
Test status
Simulation time 137082652 ps
CPU time 1.18 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 200812 kb
Host smart-61b9fa10-f6b6-4886-a0e4-a9af64f4d382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85317000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.85317000
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.333758102
Short name T361
Test name
Test status
Simulation time 73738049 ps
CPU time 0.83 seconds
Started Mar 26 03:22:14 PM PDT 24
Finished Mar 26 03:22:15 PM PDT 24
Peak memory 200700 kb
Host smart-1280f92a-8bb0-462a-8c8d-9fd5f01494d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333758102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.333758102
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4237617671
Short name T50
Test name
Test status
Simulation time 2359259799 ps
CPU time 9.46 seconds
Started Mar 26 03:22:09 PM PDT 24
Finished Mar 26 03:22:18 PM PDT 24
Peak memory 222632 kb
Host smart-2af95962-7871-4d38-8e5f-a88ac28f3801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237617671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4237617671
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1136671342
Short name T267
Test name
Test status
Simulation time 244318527 ps
CPU time 1.06 seconds
Started Mar 26 03:22:08 PM PDT 24
Finished Mar 26 03:22:10 PM PDT 24
Peak memory 218144 kb
Host smart-11859a73-aca7-43cd-8fd0-0a898f2e7af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136671342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1136671342
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.536641728
Short name T232
Test name
Test status
Simulation time 124234844 ps
CPU time 0.79 seconds
Started Mar 26 03:22:07 PM PDT 24
Finished Mar 26 03:22:08 PM PDT 24
Peak memory 200656 kb
Host smart-1db058b8-e410-4505-a497-d4f7c2c168e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536641728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.536641728
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.120698524
Short name T277
Test name
Test status
Simulation time 1356415181 ps
CPU time 5.61 seconds
Started Mar 26 03:22:09 PM PDT 24
Finished Mar 26 03:22:15 PM PDT 24
Peak memory 201012 kb
Host smart-431e9a97-b8f1-48b2-aedc-b559a40d270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120698524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.120698524
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3757211706
Short name T80
Test name
Test status
Simulation time 16601832566 ps
CPU time 25.75 seconds
Started Mar 26 03:22:12 PM PDT 24
Finished Mar 26 03:22:38 PM PDT 24
Peak memory 217692 kb
Host smart-576011ba-1ac5-43af-96db-06b885ce0525
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757211706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3757211706
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2184037668
Short name T429
Test name
Test status
Simulation time 151608537 ps
CPU time 1.12 seconds
Started Mar 26 03:22:14 PM PDT 24
Finished Mar 26 03:22:16 PM PDT 24
Peak memory 200796 kb
Host smart-a471c6ac-37ee-4c37-8acf-0357fd2ed2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184037668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2184037668
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3809294238
Short name T442
Test name
Test status
Simulation time 128498116 ps
CPU time 1.15 seconds
Started Mar 26 03:22:08 PM PDT 24
Finished Mar 26 03:22:09 PM PDT 24
Peak memory 201012 kb
Host smart-19f54d04-3548-4522-b8b0-cc02fe8443dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809294238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3809294238
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3503434233
Short name T450
Test name
Test status
Simulation time 12438290609 ps
CPU time 47.26 seconds
Started Mar 26 03:22:09 PM PDT 24
Finished Mar 26 03:22:56 PM PDT 24
Peak memory 201080 kb
Host smart-a4f868bb-cd81-416a-8830-372e97b78d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503434233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3503434233
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.997954659
Short name T162
Test name
Test status
Simulation time 296908530 ps
CPU time 1.95 seconds
Started Mar 26 03:22:07 PM PDT 24
Finished Mar 26 03:22:09 PM PDT 24
Peak memory 209256 kb
Host smart-14762e21-7f63-474c-9c4b-c8588f2f4ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997954659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.997954659
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2123632975
Short name T546
Test name
Test status
Simulation time 161413617 ps
CPU time 1.1 seconds
Started Mar 26 03:22:08 PM PDT 24
Finished Mar 26 03:22:09 PM PDT 24
Peak memory 200724 kb
Host smart-00d4c1fa-68a1-4c2f-b830-d5c0afb994a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123632975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2123632975
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3224572048
Short name T49
Test name
Test status
Simulation time 63413237 ps
CPU time 0.76 seconds
Started Mar 26 03:23:09 PM PDT 24
Finished Mar 26 03:23:10 PM PDT 24
Peak memory 200716 kb
Host smart-c9d5de8e-0bdc-4934-b72b-4859bbf59014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224572048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3224572048
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1582448599
Short name T276
Test name
Test status
Simulation time 2186298419 ps
CPU time 8.62 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:12 PM PDT 24
Peak memory 222624 kb
Host smart-aa7b40ae-55a7-4107-9975-68110d4364b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582448599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1582448599
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.978062949
Short name T153
Test name
Test status
Simulation time 244575723 ps
CPU time 1.04 seconds
Started Mar 26 03:23:05 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 218268 kb
Host smart-cdf57888-7aff-46cd-99ec-d0dd0f51329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978062949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.978062949
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2397809880
Short name T22
Test name
Test status
Simulation time 197485744 ps
CPU time 0.95 seconds
Started Mar 26 03:23:04 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 200696 kb
Host smart-60796150-0dfe-416e-b3c3-d334d6fdba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397809880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2397809880
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3257729702
Short name T208
Test name
Test status
Simulation time 1466629323 ps
CPU time 5.75 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:15 PM PDT 24
Peak memory 201008 kb
Host smart-b33c5940-a284-4c95-a57b-cc539f1bf3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257729702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3257729702
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.416907149
Short name T382
Test name
Test status
Simulation time 109325207 ps
CPU time 1 seconds
Started Mar 26 03:23:05 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200824 kb
Host smart-1273c41d-ff46-4f26-8f37-2e2a40eb53a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416907149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.416907149
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2891044565
Short name T270
Test name
Test status
Simulation time 196245668 ps
CPU time 1.66 seconds
Started Mar 26 03:23:03 PM PDT 24
Finished Mar 26 03:23:05 PM PDT 24
Peak memory 201028 kb
Host smart-96fbb8c9-7958-45dc-8edf-2f4710861b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891044565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2891044565
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.4162411002
Short name T321
Test name
Test status
Simulation time 2653091963 ps
CPU time 9.71 seconds
Started Mar 26 03:23:00 PM PDT 24
Finished Mar 26 03:23:10 PM PDT 24
Peak memory 201176 kb
Host smart-9b50375f-2752-442c-89ac-f99092f0639b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162411002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4162411002
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.4172612374
Short name T457
Test name
Test status
Simulation time 137481575 ps
CPU time 1.68 seconds
Started Mar 26 03:23:05 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 209108 kb
Host smart-bba07ac5-2023-4712-a882-298bac275b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172612374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4172612374
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3828578117
Short name T229
Test name
Test status
Simulation time 149118524 ps
CPU time 1.02 seconds
Started Mar 26 03:23:01 PM PDT 24
Finished Mar 26 03:23:02 PM PDT 24
Peak memory 200848 kb
Host smart-55b1feb4-e833-45e2-9eda-79666a6dbf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828578117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3828578117
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3657161274
Short name T444
Test name
Test status
Simulation time 77648050 ps
CPU time 0.77 seconds
Started Mar 26 03:23:18 PM PDT 24
Finished Mar 26 03:23:19 PM PDT 24
Peak memory 200704 kb
Host smart-cf169960-5850-4475-834d-4a4675a06442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657161274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3657161274
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2271808750
Short name T388
Test name
Test status
Simulation time 2371416160 ps
CPU time 8.24 seconds
Started Mar 26 03:23:26 PM PDT 24
Finished Mar 26 03:23:34 PM PDT 24
Peak memory 222708 kb
Host smart-cce01080-24fb-4c7e-9671-4d51550ec472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271808750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2271808750
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3849996489
Short name T1
Test name
Test status
Simulation time 245443221 ps
CPU time 1.04 seconds
Started Mar 26 03:23:23 PM PDT 24
Finished Mar 26 03:23:29 PM PDT 24
Peak memory 218144 kb
Host smart-d4d3e7fc-7729-46fe-855b-a654d28d1f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849996489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3849996489
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2731570414
Short name T85
Test name
Test status
Simulation time 172705899 ps
CPU time 0.93 seconds
Started Mar 26 03:23:08 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 200684 kb
Host smart-9c1ebf0c-9ad6-42f8-99fb-534894338671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731570414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2731570414
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2762821324
Short name T47
Test name
Test status
Simulation time 1231964766 ps
CPU time 4.66 seconds
Started Mar 26 03:23:08 PM PDT 24
Finished Mar 26 03:23:13 PM PDT 24
Peak memory 200996 kb
Host smart-0669e1f0-8121-4d3e-9b59-94e98dc44674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762821324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2762821324
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.256113434
Short name T334
Test name
Test status
Simulation time 142661921 ps
CPU time 1.05 seconds
Started Mar 26 03:23:22 PM PDT 24
Finished Mar 26 03:23:23 PM PDT 24
Peak memory 200736 kb
Host smart-cef0a09b-ce8d-435b-902d-7efb53782790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256113434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.256113434
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3369455475
Short name T351
Test name
Test status
Simulation time 196950939 ps
CPU time 1.33 seconds
Started Mar 26 03:23:12 PM PDT 24
Finished Mar 26 03:23:13 PM PDT 24
Peak memory 201040 kb
Host smart-9967505c-8ac4-4513-882e-b23f8f8ed42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369455475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3369455475
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2884577709
Short name T246
Test name
Test status
Simulation time 358417313 ps
CPU time 2.1 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:12 PM PDT 24
Peak memory 200884 kb
Host smart-5ff739ad-1608-41bd-82b4-5a0d9672a9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884577709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2884577709
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3843350804
Short name T516
Test name
Test status
Simulation time 150610569 ps
CPU time 1.07 seconds
Started Mar 26 03:23:22 PM PDT 24
Finished Mar 26 03:23:23 PM PDT 24
Peak memory 200808 kb
Host smart-d149daa1-5b19-4355-b150-112b8adb19b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843350804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3843350804
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3767691235
Short name T164
Test name
Test status
Simulation time 52616833 ps
CPU time 0.73 seconds
Started Mar 26 03:23:27 PM PDT 24
Finished Mar 26 03:23:28 PM PDT 24
Peak memory 200728 kb
Host smart-2693ab8a-71a6-436d-88d2-4966306ee291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767691235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3767691235
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2096232451
Short name T375
Test name
Test status
Simulation time 1909384753 ps
CPU time 7.14 seconds
Started Mar 26 03:23:24 PM PDT 24
Finished Mar 26 03:23:31 PM PDT 24
Peak memory 217936 kb
Host smart-6d2576ee-81d2-445f-969e-31cc29cea4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096232451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2096232451
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1197145352
Short name T279
Test name
Test status
Simulation time 244700127 ps
CPU time 1.12 seconds
Started Mar 26 03:23:29 PM PDT 24
Finished Mar 26 03:23:30 PM PDT 24
Peak memory 218244 kb
Host smart-18fff834-5e60-4432-b3d0-9d67babe9d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197145352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1197145352
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3035094555
Short name T510
Test name
Test status
Simulation time 92318814 ps
CPU time 0.73 seconds
Started Mar 26 03:23:15 PM PDT 24
Finished Mar 26 03:23:16 PM PDT 24
Peak memory 200712 kb
Host smart-4fe3db8f-ea6e-43f6-83e8-1d008c671760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035094555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3035094555
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.682333335
Short name T367
Test name
Test status
Simulation time 1923166172 ps
CPU time 6.46 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:17 PM PDT 24
Peak memory 201008 kb
Host smart-35da5cc2-2cc2-49c5-b9cd-f9c8f898161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682333335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.682333335
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3314150585
Short name T307
Test name
Test status
Simulation time 106733797 ps
CPU time 1.06 seconds
Started Mar 26 03:23:11 PM PDT 24
Finished Mar 26 03:23:12 PM PDT 24
Peak memory 200812 kb
Host smart-e746895c-8246-49bc-b06c-fd0b2caa0643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314150585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3314150585
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2607248560
Short name T360
Test name
Test status
Simulation time 214581565 ps
CPU time 1.53 seconds
Started Mar 26 03:23:29 PM PDT 24
Finished Mar 26 03:23:31 PM PDT 24
Peak memory 200988 kb
Host smart-84953e90-2bb2-4aca-bd6c-a4d78543a9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607248560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2607248560
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.414728319
Short name T374
Test name
Test status
Simulation time 2267750003 ps
CPU time 10.07 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:20 PM PDT 24
Peak memory 201112 kb
Host smart-3493e2d6-5604-436f-9714-47d03c020742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414728319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.414728319
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3813214785
Short name T454
Test name
Test status
Simulation time 159397392 ps
CPU time 2.1 seconds
Started Mar 26 03:23:12 PM PDT 24
Finished Mar 26 03:23:14 PM PDT 24
Peak memory 200884 kb
Host smart-4e19168a-c382-40c2-98f5-63d31405b005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813214785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3813214785
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1758758278
Short name T92
Test name
Test status
Simulation time 161416107 ps
CPU time 1.34 seconds
Started Mar 26 03:23:29 PM PDT 24
Finished Mar 26 03:23:31 PM PDT 24
Peak memory 201028 kb
Host smart-190f4e23-80c1-404f-a318-d61b13ab1fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758758278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1758758278
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2727641862
Short name T371
Test name
Test status
Simulation time 66954285 ps
CPU time 0.76 seconds
Started Mar 26 03:23:25 PM PDT 24
Finished Mar 26 03:23:26 PM PDT 24
Peak memory 200656 kb
Host smart-dc5e15a8-7bb0-4113-a952-744cf2695e7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727641862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2727641862
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2063447018
Short name T225
Test name
Test status
Simulation time 1889919222 ps
CPU time 7.61 seconds
Started Mar 26 03:23:17 PM PDT 24
Finished Mar 26 03:23:25 PM PDT 24
Peak memory 218556 kb
Host smart-0e82d133-c8ae-47c0-a26b-d5a20de92054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063447018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2063447018
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1598561061
Short name T535
Test name
Test status
Simulation time 244533477 ps
CPU time 1.05 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:40 PM PDT 24
Peak memory 218028 kb
Host smart-c91555d0-c107-4fa8-8e2c-211e62df186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598561061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1598561061
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2036621910
Short name T266
Test name
Test status
Simulation time 222072128 ps
CPU time 0.9 seconds
Started Mar 26 03:23:22 PM PDT 24
Finished Mar 26 03:23:23 PM PDT 24
Peak memory 200684 kb
Host smart-a167b9d0-349a-4bd0-86b7-490f2587e8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036621910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2036621910
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1769495388
Short name T83
Test name
Test status
Simulation time 1552038477 ps
CPU time 5.4 seconds
Started Mar 26 03:23:13 PM PDT 24
Finished Mar 26 03:23:18 PM PDT 24
Peak memory 201016 kb
Host smart-502bf26b-921e-4a16-b540-0dd31b6071a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769495388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1769495388
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.235964688
Short name T344
Test name
Test status
Simulation time 142981855 ps
CPU time 1.15 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:11 PM PDT 24
Peak memory 200784 kb
Host smart-30bed5c4-717e-47c1-b26d-9ef16dcd82f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235964688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.235964688
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.368395898
Short name T281
Test name
Test status
Simulation time 245113620 ps
CPU time 1.54 seconds
Started Mar 26 03:23:11 PM PDT 24
Finished Mar 26 03:23:12 PM PDT 24
Peak memory 200972 kb
Host smart-cbb813c7-ab83-4696-b03c-9afdad5ecc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368395898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.368395898
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2471761757
Short name T51
Test name
Test status
Simulation time 5264147187 ps
CPU time 18.95 seconds
Started Mar 26 03:23:18 PM PDT 24
Finished Mar 26 03:23:37 PM PDT 24
Peak memory 209328 kb
Host smart-10aede79-f625-4df0-a75a-814572ddf35e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471761757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2471761757
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.418406023
Short name T167
Test name
Test status
Simulation time 134161352 ps
CPU time 1.67 seconds
Started Mar 26 03:23:07 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 200868 kb
Host smart-e7399161-3d66-4238-8d09-2fe729a48c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418406023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.418406023
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3010447470
Short name T90
Test name
Test status
Simulation time 129236092 ps
CPU time 1.05 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:11 PM PDT 24
Peak memory 200812 kb
Host smart-a047e4a9-9703-4e19-ad37-58771472c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010447470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3010447470
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1159430698
Short name T390
Test name
Test status
Simulation time 55451500 ps
CPU time 0.75 seconds
Started Mar 26 03:23:18 PM PDT 24
Finished Mar 26 03:23:19 PM PDT 24
Peak memory 200672 kb
Host smart-ad4d754b-d8e5-43d3-97ee-ec454420163c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159430698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1159430698
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3542795427
Short name T68
Test name
Test status
Simulation time 1227575422 ps
CPU time 5.87 seconds
Started Mar 26 03:23:11 PM PDT 24
Finished Mar 26 03:23:17 PM PDT 24
Peak memory 222624 kb
Host smart-f817db72-4926-49c3-aa49-59459df9c114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542795427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3542795427
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3005388779
Short name T419
Test name
Test status
Simulation time 244371253 ps
CPU time 1.16 seconds
Started Mar 26 03:23:08 PM PDT 24
Finished Mar 26 03:23:10 PM PDT 24
Peak memory 218096 kb
Host smart-01e14597-7e1a-4d73-8846-7e9315342b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005388779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3005388779
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.75580316
Short name T430
Test name
Test status
Simulation time 97396828 ps
CPU time 0.77 seconds
Started Mar 26 03:23:09 PM PDT 24
Finished Mar 26 03:23:10 PM PDT 24
Peak memory 200664 kb
Host smart-f36791aa-712f-4078-964d-633128d0b71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75580316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.75580316
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3000636165
Short name T112
Test name
Test status
Simulation time 1023743616 ps
CPU time 5.03 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:15 PM PDT 24
Peak memory 201080 kb
Host smart-8117203c-cbc9-4023-9ccd-9e10b6f1f04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000636165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3000636165
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1183231191
Short name T540
Test name
Test status
Simulation time 180525013 ps
CPU time 1.18 seconds
Started Mar 26 03:23:09 PM PDT 24
Finished Mar 26 03:23:10 PM PDT 24
Peak memory 201012 kb
Host smart-3beb2218-5aa2-46b6-9c1d-c0f2a2bdb8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183231191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1183231191
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2770067113
Short name T152
Test name
Test status
Simulation time 123649099 ps
CPU time 1.17 seconds
Started Mar 26 03:23:29 PM PDT 24
Finished Mar 26 03:23:30 PM PDT 24
Peak memory 201020 kb
Host smart-1800dcf7-4e75-4305-ac43-2af1a0008459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770067113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2770067113
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2763239225
Short name T260
Test name
Test status
Simulation time 9351106721 ps
CPU time 31.05 seconds
Started Mar 26 03:23:12 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 201140 kb
Host smart-1e14da70-827c-4f49-adfa-b73a8829997c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763239225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2763239225
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4253023015
Short name T6
Test name
Test status
Simulation time 414901427 ps
CPU time 2.21 seconds
Started Mar 26 03:23:23 PM PDT 24
Finished Mar 26 03:23:25 PM PDT 24
Peak memory 209144 kb
Host smart-13d9876f-b7bd-4408-9d48-4a6e7ede85a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253023015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4253023015
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1501045083
Short name T224
Test name
Test status
Simulation time 132777269 ps
CPU time 1 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:11 PM PDT 24
Peak memory 200860 kb
Host smart-ab12b984-1f11-4e5b-b193-8664b7b9d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501045083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1501045083
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1102359651
Short name T79
Test name
Test status
Simulation time 61661797 ps
CPU time 0.74 seconds
Started Mar 26 03:23:23 PM PDT 24
Finished Mar 26 03:23:24 PM PDT 24
Peak memory 200720 kb
Host smart-8e2215c4-c191-49b1-8a7e-8ecd0015fa3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102359651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1102359651
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1546319261
Short name T228
Test name
Test status
Simulation time 244693694 ps
CPU time 1.06 seconds
Started Mar 26 03:23:12 PM PDT 24
Finished Mar 26 03:23:13 PM PDT 24
Peak memory 218136 kb
Host smart-d73616b5-8dec-434c-8621-5ebc28563032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546319261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1546319261
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1216619299
Short name T527
Test name
Test status
Simulation time 101983690 ps
CPU time 0.78 seconds
Started Mar 26 03:23:11 PM PDT 24
Finished Mar 26 03:23:12 PM PDT 24
Peak memory 200700 kb
Host smart-9019f0e8-568c-48e5-82d6-3c50683d04e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216619299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1216619299
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.4119968106
Short name T189
Test name
Test status
Simulation time 930491736 ps
CPU time 4.18 seconds
Started Mar 26 03:23:20 PM PDT 24
Finished Mar 26 03:23:24 PM PDT 24
Peak memory 201052 kb
Host smart-08c88d8e-4f5f-4f8f-864a-f5b725d3e0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119968106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.4119968106
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1444819959
Short name T65
Test name
Test status
Simulation time 107108138 ps
CPU time 1.01 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:11 PM PDT 24
Peak memory 200844 kb
Host smart-0f46200e-374d-4d2f-83a9-a21d535f56f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444819959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1444819959
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1017718656
Short name T526
Test name
Test status
Simulation time 204830245 ps
CPU time 1.44 seconds
Started Mar 26 03:23:17 PM PDT 24
Finished Mar 26 03:23:18 PM PDT 24
Peak memory 201004 kb
Host smart-a03bf4e1-24cd-4291-8b38-e889b91cabab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017718656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1017718656
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.647371864
Short name T233
Test name
Test status
Simulation time 3666182570 ps
CPU time 16.1 seconds
Started Mar 26 03:23:10 PM PDT 24
Finished Mar 26 03:23:26 PM PDT 24
Peak memory 201112 kb
Host smart-3daee86b-50d2-4e16-98cf-736f1981ec52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647371864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.647371864
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2963603734
Short name T453
Test name
Test status
Simulation time 335868341 ps
CPU time 2.22 seconds
Started Mar 26 03:23:11 PM PDT 24
Finished Mar 26 03:23:13 PM PDT 24
Peak memory 200932 kb
Host smart-e100a2b4-ba1f-448d-bc66-ce2f3f2f4284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963603734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2963603734
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2775192244
Short name T491
Test name
Test status
Simulation time 191731516 ps
CPU time 1.34 seconds
Started Mar 26 03:23:07 PM PDT 24
Finished Mar 26 03:23:09 PM PDT 24
Peak memory 200692 kb
Host smart-2c5bd1a5-ddf4-4ca9-bbf7-dfa50d169e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775192244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2775192244
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3894019586
Short name T451
Test name
Test status
Simulation time 89700173 ps
CPU time 0.84 seconds
Started Mar 26 03:23:11 PM PDT 24
Finished Mar 26 03:23:12 PM PDT 24
Peak memory 200684 kb
Host smart-e9180305-a7a5-42f3-9195-6a27806502c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894019586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3894019586
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2290608110
Short name T214
Test name
Test status
Simulation time 1908302681 ps
CPU time 8.09 seconds
Started Mar 26 03:23:25 PM PDT 24
Finished Mar 26 03:23:33 PM PDT 24
Peak memory 222544 kb
Host smart-0ee4baf9-e7b1-447e-b9e1-2a0ed52cf20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290608110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2290608110
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3448476211
Short name T145
Test name
Test status
Simulation time 243439434 ps
CPU time 1.12 seconds
Started Mar 26 03:23:21 PM PDT 24
Finished Mar 26 03:23:22 PM PDT 24
Peak memory 218136 kb
Host smart-561dd55f-4881-4354-82fb-13e34c75d92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448476211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3448476211
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4283006139
Short name T282
Test name
Test status
Simulation time 179705560 ps
CPU time 0.94 seconds
Started Mar 26 03:23:11 PM PDT 24
Finished Mar 26 03:23:12 PM PDT 24
Peak memory 200700 kb
Host smart-fa1f60fc-e663-46c2-8a40-2060d9e52d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283006139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4283006139
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3629543441
Short name T203
Test name
Test status
Simulation time 1465370528 ps
CPU time 5.38 seconds
Started Mar 26 03:23:12 PM PDT 24
Finished Mar 26 03:23:18 PM PDT 24
Peak memory 201000 kb
Host smart-2a673f0a-399a-4a21-8c12-cfa2e88c403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629543441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3629543441
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2983774523
Short name T204
Test name
Test status
Simulation time 163026848 ps
CPU time 1.15 seconds
Started Mar 26 03:23:12 PM PDT 24
Finished Mar 26 03:23:13 PM PDT 24
Peak memory 200836 kb
Host smart-160e4ce8-42e9-4b52-9c51-b1a06ef184ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983774523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2983774523
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1218410872
Short name T415
Test name
Test status
Simulation time 126324799 ps
CPU time 1.25 seconds
Started Mar 26 03:23:22 PM PDT 24
Finished Mar 26 03:23:24 PM PDT 24
Peak memory 200988 kb
Host smart-f281e8eb-3cac-4810-8ea5-9a3640169f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218410872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1218410872
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1322352308
Short name T362
Test name
Test status
Simulation time 15912782840 ps
CPU time 62.08 seconds
Started Mar 26 03:23:17 PM PDT 24
Finished Mar 26 03:24:19 PM PDT 24
Peak memory 201112 kb
Host smart-bb1045b0-b23d-4de2-baa8-7b61c46ea2ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322352308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1322352308
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.32197989
Short name T166
Test name
Test status
Simulation time 522577028 ps
CPU time 2.6 seconds
Started Mar 26 03:23:11 PM PDT 24
Finished Mar 26 03:23:14 PM PDT 24
Peak memory 200868 kb
Host smart-5d0777b2-0e22-42f0-8b47-d8d768745204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32197989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.32197989
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3430486401
Short name T539
Test name
Test status
Simulation time 226697853 ps
CPU time 1.44 seconds
Started Mar 26 03:23:19 PM PDT 24
Finished Mar 26 03:23:21 PM PDT 24
Peak memory 201040 kb
Host smart-46ded2a1-0865-4425-9dc8-cd830c0ab0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430486401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3430486401
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1497184179
Short name T261
Test name
Test status
Simulation time 67735011 ps
CPU time 0.76 seconds
Started Mar 26 03:23:29 PM PDT 24
Finished Mar 26 03:23:30 PM PDT 24
Peak memory 200872 kb
Host smart-b4b84077-7d1e-458f-b5b5-bb081d4965db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497184179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1497184179
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1919084246
Short name T41
Test name
Test status
Simulation time 1231421984 ps
CPU time 5.96 seconds
Started Mar 26 03:23:28 PM PDT 24
Finished Mar 26 03:23:34 PM PDT 24
Peak memory 218500 kb
Host smart-0d7dea4b-cb66-4480-af87-9ae891d59900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919084246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1919084246
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2688314687
Short name T379
Test name
Test status
Simulation time 244529762 ps
CPU time 1.1 seconds
Started Mar 26 03:23:44 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 218096 kb
Host smart-20f23e0f-9bf2-47d5-ba71-39725da2b13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688314687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2688314687
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1587412820
Short name T427
Test name
Test status
Simulation time 107705148 ps
CPU time 0.79 seconds
Started Mar 26 03:23:06 PM PDT 24
Finished Mar 26 03:23:06 PM PDT 24
Peak memory 200656 kb
Host smart-fdb7e61e-0167-4ab4-b9ae-41740694b8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587412820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1587412820
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.222514911
Short name T193
Test name
Test status
Simulation time 1791374104 ps
CPU time 6.45 seconds
Started Mar 26 03:23:35 PM PDT 24
Finished Mar 26 03:23:42 PM PDT 24
Peak memory 201040 kb
Host smart-1a394ef6-2192-44a6-a357-98246c5e8d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222514911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.222514911
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1819186263
Short name T520
Test name
Test status
Simulation time 99857783 ps
CPU time 1.08 seconds
Started Mar 26 03:23:25 PM PDT 24
Finished Mar 26 03:23:26 PM PDT 24
Peak memory 201016 kb
Host smart-f62f7f37-18a3-4e03-afbd-52f035a105e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819186263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1819186263
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3377443319
Short name T254
Test name
Test status
Simulation time 123284376 ps
CPU time 1.14 seconds
Started Mar 26 03:23:28 PM PDT 24
Finished Mar 26 03:23:30 PM PDT 24
Peak memory 200964 kb
Host smart-19e7f3a2-674c-479a-a354-6d792c5b7b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377443319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3377443319
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.402214625
Short name T290
Test name
Test status
Simulation time 16304618900 ps
CPU time 60.47 seconds
Started Mar 26 03:23:29 PM PDT 24
Finished Mar 26 03:24:29 PM PDT 24
Peak memory 209360 kb
Host smart-5952846a-cb92-4ad3-aee8-f71c06741109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402214625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.402214625
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1533122786
Short name T265
Test name
Test status
Simulation time 137242841 ps
CPU time 1.62 seconds
Started Mar 26 03:23:24 PM PDT 24
Finished Mar 26 03:23:26 PM PDT 24
Peak memory 208984 kb
Host smart-a68703ac-e174-46e4-81d0-df0b1e3abe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533122786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1533122786
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2291567564
Short name T227
Test name
Test status
Simulation time 266705709 ps
CPU time 1.49 seconds
Started Mar 26 03:23:32 PM PDT 24
Finished Mar 26 03:23:34 PM PDT 24
Peak memory 200828 kb
Host smart-cab72209-6b5a-4be0-918b-3d4fe5df7a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291567564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2291567564
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.19979270
Short name T300
Test name
Test status
Simulation time 64694840 ps
CPU time 0.78 seconds
Started Mar 26 03:23:38 PM PDT 24
Finished Mar 26 03:23:39 PM PDT 24
Peak memory 200712 kb
Host smart-8c0764bd-0e3c-4a7e-b2b0-33ec0f0e0f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19979270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.19979270
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3402096419
Short name T377
Test name
Test status
Simulation time 1907172242 ps
CPU time 7.55 seconds
Started Mar 26 03:23:36 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 218508 kb
Host smart-c18e7d33-b7cc-4027-89aa-fa02596ed81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402096419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3402096419
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.154390829
Short name T305
Test name
Test status
Simulation time 244166016 ps
CPU time 1.06 seconds
Started Mar 26 03:23:35 PM PDT 24
Finished Mar 26 03:23:36 PM PDT 24
Peak memory 218172 kb
Host smart-4562acec-814a-4934-8209-d9f7bf052902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154390829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.154390829
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.4169988863
Short name T346
Test name
Test status
Simulation time 179314257 ps
CPU time 0.98 seconds
Started Mar 26 03:23:26 PM PDT 24
Finished Mar 26 03:23:27 PM PDT 24
Peak memory 200684 kb
Host smart-97fd6976-dac0-41f3-ba9a-6e60bdf94f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169988863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.4169988863
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2676293145
Short name T356
Test name
Test status
Simulation time 797535870 ps
CPU time 4.04 seconds
Started Mar 26 03:23:44 PM PDT 24
Finished Mar 26 03:23:49 PM PDT 24
Peak memory 201044 kb
Host smart-cc29f495-05a1-47fe-9140-ef681e10a950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676293145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2676293145
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1958274386
Short name T431
Test name
Test status
Simulation time 96285075 ps
CPU time 0.98 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 200812 kb
Host smart-60e7ad1e-bf6a-4d2d-b214-ac8be7386235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958274386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1958274386
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3566660464
Short name T91
Test name
Test status
Simulation time 204865544 ps
CPU time 1.61 seconds
Started Mar 26 03:23:37 PM PDT 24
Finished Mar 26 03:23:39 PM PDT 24
Peak memory 201036 kb
Host smart-4b836e82-76f4-4eca-abcc-36e9f9cf0099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566660464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3566660464
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2084485720
Short name T219
Test name
Test status
Simulation time 193486545 ps
CPU time 1.37 seconds
Started Mar 26 03:23:35 PM PDT 24
Finished Mar 26 03:23:36 PM PDT 24
Peak memory 200792 kb
Host smart-2e2c1212-6e1c-4c41-8eee-48495e734e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084485720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2084485720
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3339782774
Short name T174
Test name
Test status
Simulation time 136610142 ps
CPU time 1.77 seconds
Started Mar 26 03:23:31 PM PDT 24
Finished Mar 26 03:23:33 PM PDT 24
Peak memory 209080 kb
Host smart-8db53deb-8c7e-44f4-8564-773aaca01f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339782774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3339782774
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.4091783138
Short name T142
Test name
Test status
Simulation time 135285750 ps
CPU time 1.17 seconds
Started Mar 26 03:23:24 PM PDT 24
Finished Mar 26 03:23:25 PM PDT 24
Peak memory 200788 kb
Host smart-c5f816ca-7bf2-4ebf-ba79-03d80543a244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091783138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4091783138
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2477195612
Short name T82
Test name
Test status
Simulation time 72077219 ps
CPU time 0.77 seconds
Started Mar 26 03:23:28 PM PDT 24
Finished Mar 26 03:23:28 PM PDT 24
Peak memory 200708 kb
Host smart-8fea0794-d49a-4c1f-86fa-1a0733366603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477195612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2477195612
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2352093433
Short name T42
Test name
Test status
Simulation time 2352466125 ps
CPU time 7.82 seconds
Started Mar 26 03:23:32 PM PDT 24
Finished Mar 26 03:23:40 PM PDT 24
Peak memory 218368 kb
Host smart-848e9781-b70f-42e2-82a5-5dbae2f4acf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352093433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2352093433
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2240570608
Short name T309
Test name
Test status
Simulation time 244066278 ps
CPU time 1.04 seconds
Started Mar 26 03:23:31 PM PDT 24
Finished Mar 26 03:23:32 PM PDT 24
Peak memory 218124 kb
Host smart-0587437f-4d93-43b5-ae81-bf87445d30e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240570608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2240570608
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1205474747
Short name T477
Test name
Test status
Simulation time 81623004 ps
CPU time 0.75 seconds
Started Mar 26 03:23:31 PM PDT 24
Finished Mar 26 03:23:32 PM PDT 24
Peak memory 200660 kb
Host smart-16e34b7e-c2a3-4838-8223-a4a02f0bf964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205474747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1205474747
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2135709498
Short name T3
Test name
Test status
Simulation time 1674040491 ps
CPU time 6.29 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 201008 kb
Host smart-270ef23a-22aa-4c47-bd30-2ecb3ba39264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135709498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2135709498
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1800562256
Short name T378
Test name
Test status
Simulation time 107208201 ps
CPU time 1 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 200808 kb
Host smart-fade99b8-407a-42fd-a098-e325b03da1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800562256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1800562256
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1837683844
Short name T391
Test name
Test status
Simulation time 184692373 ps
CPU time 1.35 seconds
Started Mar 26 03:23:34 PM PDT 24
Finished Mar 26 03:23:36 PM PDT 24
Peak memory 201004 kb
Host smart-961a9cbf-d7fc-46f8-8d51-98ef894e42d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837683844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1837683844
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.593885503
Short name T241
Test name
Test status
Simulation time 1799970560 ps
CPU time 8.04 seconds
Started Mar 26 03:23:32 PM PDT 24
Finished Mar 26 03:23:40 PM PDT 24
Peak memory 201024 kb
Host smart-89e3f227-7b1f-4620-9f10-62bfe382a702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593885503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.593885503
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.847425264
Short name T428
Test name
Test status
Simulation time 369376559 ps
CPU time 2.48 seconds
Started Mar 26 03:23:33 PM PDT 24
Finished Mar 26 03:23:36 PM PDT 24
Peak memory 200876 kb
Host smart-7dc4a5a3-b5b6-48db-bb5b-31d2cfc7eb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847425264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.847425264
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.788772633
Short name T423
Test name
Test status
Simulation time 197526451 ps
CPU time 1.29 seconds
Started Mar 26 03:23:32 PM PDT 24
Finished Mar 26 03:23:34 PM PDT 24
Peak memory 200868 kb
Host smart-750a0350-ba6e-44c5-ba59-b53fe48d73a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788772633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.788772633
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2294602317
Short name T182
Test name
Test status
Simulation time 78539368 ps
CPU time 0.79 seconds
Started Mar 26 03:22:12 PM PDT 24
Finished Mar 26 03:22:13 PM PDT 24
Peak memory 200676 kb
Host smart-0cd411d5-432e-4305-8e27-c625c85027bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294602317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2294602317
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.678704743
Short name T35
Test name
Test status
Simulation time 1230085382 ps
CPU time 5.42 seconds
Started Mar 26 03:22:07 PM PDT 24
Finished Mar 26 03:22:13 PM PDT 24
Peak memory 217504 kb
Host smart-4f886b83-e381-4716-9cbe-f58bc4f99f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678704743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.678704743
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2427322405
Short name T197
Test name
Test status
Simulation time 245157935 ps
CPU time 1.05 seconds
Started Mar 26 03:22:10 PM PDT 24
Finished Mar 26 03:22:11 PM PDT 24
Peak memory 218124 kb
Host smart-d03df1aa-a481-469d-a4e3-caa50af0ba2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427322405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2427322405
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1675811568
Short name T352
Test name
Test status
Simulation time 210450822 ps
CPU time 0.91 seconds
Started Mar 26 03:22:07 PM PDT 24
Finished Mar 26 03:22:08 PM PDT 24
Peak memory 200672 kb
Host smart-32576279-b727-4b65-bd0d-2a85e5bb8120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675811568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1675811568
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2019152547
Short name T385
Test name
Test status
Simulation time 2063967333 ps
CPU time 7.89 seconds
Started Mar 26 03:22:07 PM PDT 24
Finished Mar 26 03:22:15 PM PDT 24
Peak memory 201036 kb
Host smart-06fbd04b-4622-4b85-a9d3-87c64a663d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019152547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2019152547
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4058159625
Short name T269
Test name
Test status
Simulation time 106446940 ps
CPU time 0.98 seconds
Started Mar 26 03:22:10 PM PDT 24
Finished Mar 26 03:22:11 PM PDT 24
Peak memory 200804 kb
Host smart-51dbbd10-0f78-4e99-a604-bd1a63ee93c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058159625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4058159625
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2919985960
Short name T195
Test name
Test status
Simulation time 202489076 ps
CPU time 1.49 seconds
Started Mar 26 03:22:14 PM PDT 24
Finished Mar 26 03:22:16 PM PDT 24
Peak memory 201016 kb
Host smart-1d7be5d2-c8ff-4803-aa66-ea68fb8f1329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919985960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2919985960
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.28670508
Short name T273
Test name
Test status
Simulation time 4192102009 ps
CPU time 19.43 seconds
Started Mar 26 03:22:09 PM PDT 24
Finished Mar 26 03:22:29 PM PDT 24
Peak memory 201152 kb
Host smart-1e3d16c6-f9c8-4345-9c87-6a0be5a36818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28670508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.28670508
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.922989052
Short name T234
Test name
Test status
Simulation time 509072399 ps
CPU time 2.61 seconds
Started Mar 26 03:22:08 PM PDT 24
Finished Mar 26 03:22:11 PM PDT 24
Peak memory 200868 kb
Host smart-40851abc-aba7-477b-baa0-e1f6360e7816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922989052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.922989052
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.25183586
Short name T55
Test name
Test status
Simulation time 107998905 ps
CPU time 0.95 seconds
Started Mar 26 03:22:09 PM PDT 24
Finished Mar 26 03:22:10 PM PDT 24
Peak memory 200828 kb
Host smart-b9188a7d-e1c6-45f0-b3a7-078c9a1a669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25183586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.25183586
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.412890615
Short name T512
Test name
Test status
Simulation time 94652490 ps
CPU time 0.85 seconds
Started Mar 26 03:22:17 PM PDT 24
Finished Mar 26 03:22:18 PM PDT 24
Peak memory 200680 kb
Host smart-1bc726b9-17cb-44e0-90af-8a65e99becd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412890615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.412890615
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3312152924
Short name T31
Test name
Test status
Simulation time 1887000784 ps
CPU time 7.21 seconds
Started Mar 26 03:22:09 PM PDT 24
Finished Mar 26 03:22:16 PM PDT 24
Peak memory 218536 kb
Host smart-72a764cf-7147-4c0d-99b0-365fe7d9a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312152924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3312152924
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3461789643
Short name T479
Test name
Test status
Simulation time 243874947 ps
CPU time 1.09 seconds
Started Mar 26 03:22:11 PM PDT 24
Finished Mar 26 03:22:12 PM PDT 24
Peak memory 218060 kb
Host smart-ff0bf6da-de9e-4ffe-b2ea-d8a4f5fa3561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461789643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3461789643
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.715216409
Short name T24
Test name
Test status
Simulation time 225190506 ps
CPU time 0.9 seconds
Started Mar 26 03:22:10 PM PDT 24
Finished Mar 26 03:22:11 PM PDT 24
Peak memory 200640 kb
Host smart-00c082e6-e423-4e67-b204-df14e3124428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715216409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.715216409
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3667670920
Short name T318
Test name
Test status
Simulation time 834247029 ps
CPU time 4.08 seconds
Started Mar 26 03:22:07 PM PDT 24
Finished Mar 26 03:22:12 PM PDT 24
Peak memory 201020 kb
Host smart-398f2b66-41bf-4a82-9c18-8b5e7c8646b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667670920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3667670920
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.4133543373
Short name T399
Test name
Test status
Simulation time 178450805 ps
CPU time 1.17 seconds
Started Mar 26 03:22:14 PM PDT 24
Finished Mar 26 03:22:16 PM PDT 24
Peak memory 200796 kb
Host smart-e8cfa43a-bc53-4525-b5cb-8c6937029ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133543373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.4133543373
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2897432798
Short name T397
Test name
Test status
Simulation time 198416980 ps
CPU time 1.42 seconds
Started Mar 26 03:22:10 PM PDT 24
Finished Mar 26 03:22:12 PM PDT 24
Peak memory 200996 kb
Host smart-a724366f-2693-424c-8f3d-9b5f828cea08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897432798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2897432798
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.366828021
Short name T407
Test name
Test status
Simulation time 4125985404 ps
CPU time 18.35 seconds
Started Mar 26 03:22:24 PM PDT 24
Finished Mar 26 03:22:43 PM PDT 24
Peak memory 209276 kb
Host smart-579320ac-2392-44cc-8791-d7bb660dcf56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366828021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.366828021
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.520038722
Short name T463
Test name
Test status
Simulation time 115200502 ps
CPU time 1.54 seconds
Started Mar 26 03:22:08 PM PDT 24
Finished Mar 26 03:22:10 PM PDT 24
Peak memory 200808 kb
Host smart-261ed7a3-dbdd-4a7b-bd24-3afa338d44b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520038722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.520038722
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.801523074
Short name T26
Test name
Test status
Simulation time 109860815 ps
CPU time 0.9 seconds
Started Mar 26 03:22:11 PM PDT 24
Finished Mar 26 03:22:12 PM PDT 24
Peak memory 200828 kb
Host smart-f094fa7f-61f0-416e-b356-64048201c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801523074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.801523074
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2788149850
Short name T349
Test name
Test status
Simulation time 68481781 ps
CPU time 0.8 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:19 PM PDT 24
Peak memory 200664 kb
Host smart-78e296fa-a2ad-4674-aef0-78ab9d51dbf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788149850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2788149850
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.4116643168
Short name T5
Test name
Test status
Simulation time 2357014023 ps
CPU time 8.01 seconds
Started Mar 26 03:22:16 PM PDT 24
Finished Mar 26 03:22:24 PM PDT 24
Peak memory 222728 kb
Host smart-bd6c99c0-a4d9-4464-9f8f-ce059b5170c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116643168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.4116643168
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.994329925
Short name T236
Test name
Test status
Simulation time 245403489 ps
CPU time 1.08 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 218044 kb
Host smart-abbb017a-2d4d-4f5d-839d-2918dd3d4c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994329925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.994329925
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1902608295
Short name T11
Test name
Test status
Simulation time 88246750 ps
CPU time 0.77 seconds
Started Mar 26 03:22:20 PM PDT 24
Finished Mar 26 03:22:21 PM PDT 24
Peak memory 200696 kb
Host smart-8e349be1-9fec-47bf-9d9a-227f295328c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902608295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1902608295
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.912349355
Short name T216
Test name
Test status
Simulation time 1310490913 ps
CPU time 5.13 seconds
Started Mar 26 03:22:17 PM PDT 24
Finished Mar 26 03:22:22 PM PDT 24
Peak memory 201020 kb
Host smart-7f9abd6a-961b-4ed4-bcd4-8ddb638cbd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912349355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.912349355
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2068763350
Short name T366
Test name
Test status
Simulation time 160071686 ps
CPU time 1.17 seconds
Started Mar 26 03:22:19 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 200804 kb
Host smart-7a4d4f99-fb6a-4255-8d40-3c89877d08f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068763350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2068763350
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1158088416
Short name T383
Test name
Test status
Simulation time 234196831 ps
CPU time 1.39 seconds
Started Mar 26 03:22:15 PM PDT 24
Finished Mar 26 03:22:17 PM PDT 24
Peak memory 200988 kb
Host smart-94fdbded-5418-46ff-82f8-ed57793a3e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158088416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1158088416
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2625261590
Short name T94
Test name
Test status
Simulation time 3042217321 ps
CPU time 13.37 seconds
Started Mar 26 03:22:14 PM PDT 24
Finished Mar 26 03:22:28 PM PDT 24
Peak memory 201180 kb
Host smart-b55ea0f1-fc66-4c71-8c14-ced04fdb9ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625261590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2625261590
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.396684469
Short name T96
Test name
Test status
Simulation time 117028376 ps
CPU time 1.53 seconds
Started Mar 26 03:22:17 PM PDT 24
Finished Mar 26 03:22:19 PM PDT 24
Peak memory 200892 kb
Host smart-1ddff68f-2fc5-4664-9fde-cf8d29acaff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396684469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.396684469
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1316320801
Short name T410
Test name
Test status
Simulation time 211323907 ps
CPU time 1.24 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 200836 kb
Host smart-a4f28946-df42-44c5-9de6-dcc4c03278e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316320801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1316320801
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3494774632
Short name T293
Test name
Test status
Simulation time 64731498 ps
CPU time 0.74 seconds
Started Mar 26 03:22:21 PM PDT 24
Finished Mar 26 03:22:22 PM PDT 24
Peak memory 200680 kb
Host smart-93ee4c03-5c5f-4db2-afe5-cdce5d7ac721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494774632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3494774632
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3516536655
Short name T39
Test name
Test status
Simulation time 1224716464 ps
CPU time 5.52 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:24 PM PDT 24
Peak memory 222588 kb
Host smart-b3b07f92-0112-4c36-8827-92fd3dec63b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516536655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3516536655
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3472333795
Short name T245
Test name
Test status
Simulation time 244033990 ps
CPU time 1.05 seconds
Started Mar 26 03:22:19 PM PDT 24
Finished Mar 26 03:22:21 PM PDT 24
Peak memory 218068 kb
Host smart-764a6ba9-e8c3-4aff-9cb2-b2fa337808e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472333795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3472333795
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.4194584351
Short name T325
Test name
Test status
Simulation time 123076263 ps
CPU time 0.84 seconds
Started Mar 26 03:22:16 PM PDT 24
Finished Mar 26 03:22:18 PM PDT 24
Peak memory 200692 kb
Host smart-564f310d-41d3-4e20-96a9-0e8467858248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194584351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.4194584351
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1512578326
Short name T461
Test name
Test status
Simulation time 1036575266 ps
CPU time 4.89 seconds
Started Mar 26 03:22:19 PM PDT 24
Finished Mar 26 03:22:24 PM PDT 24
Peak memory 201020 kb
Host smart-b1ae588a-7219-4d70-8a17-946ec44714f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512578326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1512578326
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2834184030
Short name T503
Test name
Test status
Simulation time 109278456 ps
CPU time 1.04 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 200844 kb
Host smart-bda523b1-6da5-4540-a4aa-e44227a94332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834184030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2834184030
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.534290297
Short name T532
Test name
Test status
Simulation time 245206704 ps
CPU time 1.44 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:19 PM PDT 24
Peak memory 200952 kb
Host smart-3b9e1d06-6ec4-447f-a451-fba53c0dc41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534290297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.534290297
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.462682845
Short name T223
Test name
Test status
Simulation time 4413355410 ps
CPU time 16.12 seconds
Started Mar 26 03:22:17 PM PDT 24
Finished Mar 26 03:22:34 PM PDT 24
Peak memory 211040 kb
Host smart-49b1613d-5d56-44d8-abcc-2ccc727bedcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462682845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.462682845
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.669488262
Short name T192
Test name
Test status
Simulation time 349704510 ps
CPU time 2.09 seconds
Started Mar 26 03:22:21 PM PDT 24
Finished Mar 26 03:22:23 PM PDT 24
Peak memory 200880 kb
Host smart-5d125aa4-8ea1-4733-9402-5ef8de4af838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669488262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.669488262
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3371179775
Short name T149
Test name
Test status
Simulation time 81537394 ps
CPU time 0.85 seconds
Started Mar 26 03:22:19 PM PDT 24
Finished Mar 26 03:22:21 PM PDT 24
Peak memory 200808 kb
Host smart-dd6e2981-b73d-4677-99c0-d7515c75ec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371179775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3371179775
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3645102992
Short name T313
Test name
Test status
Simulation time 72739424 ps
CPU time 0.76 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:18 PM PDT 24
Peak memory 200696 kb
Host smart-5422657f-c65e-4692-8f48-2d4fb83083e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645102992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3645102992
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1371880118
Short name T259
Test name
Test status
Simulation time 1229698989 ps
CPU time 6.13 seconds
Started Mar 26 03:22:17 PM PDT 24
Finished Mar 26 03:22:23 PM PDT 24
Peak memory 230308 kb
Host smart-15921a4f-1b5c-48dc-9a22-77dad046ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371880118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1371880118
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.365073251
Short name T275
Test name
Test status
Simulation time 243690836 ps
CPU time 1.1 seconds
Started Mar 26 03:22:21 PM PDT 24
Finished Mar 26 03:22:23 PM PDT 24
Peak memory 218148 kb
Host smart-f7aaadb8-5479-43d9-8459-c8e3305d538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365073251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.365073251
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3123085755
Short name T490
Test name
Test status
Simulation time 162123630 ps
CPU time 0.82 seconds
Started Mar 26 03:22:18 PM PDT 24
Finished Mar 26 03:22:19 PM PDT 24
Peak memory 200660 kb
Host smart-e84d4408-cc06-401b-9d21-a63fff2a437e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123085755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3123085755
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3112769094
Short name T54
Test name
Test status
Simulation time 1457040181 ps
CPU time 5.49 seconds
Started Mar 26 03:22:13 PM PDT 24
Finished Mar 26 03:22:19 PM PDT 24
Peak memory 200992 kb
Host smart-0375ff25-1832-4701-9ba3-38f31f2ecaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112769094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3112769094
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.136692480
Short name T464
Test name
Test status
Simulation time 156829230 ps
CPU time 1.09 seconds
Started Mar 26 03:22:16 PM PDT 24
Finished Mar 26 03:22:18 PM PDT 24
Peak memory 200832 kb
Host smart-44e0225e-7f7f-462e-a9f1-2ca4a55af6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136692480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.136692480
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2638637467
Short name T476
Test name
Test status
Simulation time 124735416 ps
CPU time 1.23 seconds
Started Mar 26 03:22:19 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 200992 kb
Host smart-bf3a0175-b2d5-4344-ac7a-77a2eb333e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638637467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2638637467
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2212582318
Short name T168
Test name
Test status
Simulation time 149747389 ps
CPU time 1.85 seconds
Started Mar 26 03:22:20 PM PDT 24
Finished Mar 26 03:22:22 PM PDT 24
Peak memory 200860 kb
Host smart-0f514c30-9fd1-47ae-866b-e871f1313bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212582318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2212582318
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3006459084
Short name T185
Test name
Test status
Simulation time 87576411 ps
CPU time 0.88 seconds
Started Mar 26 03:22:19 PM PDT 24
Finished Mar 26 03:22:20 PM PDT 24
Peak memory 200796 kb
Host smart-4a363bd1-835e-406d-8db0-6bc2dd1a6715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006459084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3006459084
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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