Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8531

1

T15

29

T16

16

T18

35

auto[1]

11577

1

T10

4

T11

4

T15

23

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6054	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6821	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3140	1			T10	1		T11	1		T15	10
reset_info_cp[4]	4139	1			T10	1		T11	1		T15	12
reset_info_cp[8]	98	1			T33	2		T51	1		T34	1
reset_info_cp[16]	123	1			T20	1		T33	2		T51	3
reset_info_cp[32]	114	1			T15	1		T16	1		T19	1
reset_info_cp[64]	121	1			T16	2		T32	1		T33	2
reset_info_cp[128]	118	1			T16	1		T18	1		T20	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3278	1			T15	7		T16	16		T18	9
reset_info_cp[1]	auto[1]	2923	1			T10	1		T11	1		T15	9
reset_info_cp[2]	auto[0]	1013	1			T15	4		T18	5		T19	4
reset_info_cp[2]	auto[1]	2127	1			T10	1		T11	1		T15	6
reset_info_cp[4]	auto[0]	1486	1			T15	9		T18	10		T19	6
reset_info_cp[4]	auto[1]	2653	1			T10	1		T11	1		T15	3
reset_info_cp[8]	auto[0]	40	1			T33	1		T58	1		T132	2
reset_info_cp[8]	auto[1]	58	1			T33	1		T51	1		T34	1
reset_info_cp[16]	auto[0]	54	1			T20	1		T33	1		T51	1
reset_info_cp[16]	auto[1]	69	1			T33	1		T51	2		T137	1
reset_info_cp[32]	auto[0]	54	1			T15	1		T32	1		T90	1
reset_info_cp[32]	auto[1]	60	1			T16	1		T19	1		T33	2
reset_info_cp[64]	auto[0]	38	1			T32	1		T33	1		T90	1
reset_info_cp[64]	auto[1]	83	1			T16	2		T33	1		T97	1
reset_info_cp[128]	auto[0]	38	1			T33	1		T60	1		T102	1
reset_info_cp[128]	auto[1]	80	1			T16	1		T18	1		T20	1